Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.88 99.33 93.67 100.00 98.40 99.51 48.40


Total test records in report: 416
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T36 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1429945035 Jul 01 10:49:51 AM PDT 24 Jul 01 10:49:54 AM PDT 24 2596667728 ps
T283 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.528773960 Jul 01 10:50:14 AM PDT 24 Jul 01 10:50:17 AM PDT 24 484660424 ps
T284 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1667963045 Jul 01 10:50:03 AM PDT 24 Jul 01 10:50:06 AM PDT 24 352528372 ps
T285 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2299735217 Jul 01 10:49:37 AM PDT 24 Jul 01 10:49:38 AM PDT 24 459935985 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.102713693 Jul 01 10:49:31 AM PDT 24 Jul 01 10:49:34 AM PDT 24 863064988 ps
T74 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3415083560 Jul 01 10:50:06 AM PDT 24 Jul 01 10:50:10 AM PDT 24 1978702780 ps
T38 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2190844645 Jul 01 10:50:01 AM PDT 24 Jul 01 10:50:05 AM PDT 24 8029159081 ps
T286 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2356266982 Jul 01 10:49:52 AM PDT 24 Jul 01 10:49:55 AM PDT 24 464618950 ps
T196 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1095631901 Jul 01 10:49:37 AM PDT 24 Jul 01 10:49:39 AM PDT 24 480811635 ps
T287 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4055857861 Jul 01 10:49:32 AM PDT 24 Jul 01 10:49:34 AM PDT 24 347849988 ps
T288 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2543004472 Jul 01 10:50:07 AM PDT 24 Jul 01 10:50:10 AM PDT 24 815729452 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.130041587 Jul 01 10:49:54 AM PDT 24 Jul 01 10:50:05 AM PDT 24 6986440466 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.423102332 Jul 01 10:49:32 AM PDT 24 Jul 01 10:49:35 AM PDT 24 1398399119 ps
T289 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2212537553 Jul 01 10:49:38 AM PDT 24 Jul 01 10:49:40 AM PDT 24 501799668 ps
T290 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3932253964 Jul 01 10:49:44 AM PDT 24 Jul 01 10:49:47 AM PDT 24 609160914 ps
T190 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2430284233 Jul 01 10:49:47 AM PDT 24 Jul 01 10:49:56 AM PDT 24 4659921236 ps
T291 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1178742645 Jul 01 10:49:57 AM PDT 24 Jul 01 10:49:58 AM PDT 24 334008793 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3574934184 Jul 01 10:49:37 AM PDT 24 Jul 01 10:49:39 AM PDT 24 480438761 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.777209685 Jul 01 10:50:07 AM PDT 24 Jul 01 10:50:09 AM PDT 24 565340238 ps
T293 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4203825185 Jul 01 10:49:46 AM PDT 24 Jul 01 10:49:48 AM PDT 24 380106977 ps
T294 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4137267820 Jul 01 10:50:03 AM PDT 24 Jul 01 10:50:05 AM PDT 24 320005802 ps
T75 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3101275574 Jul 01 10:50:09 AM PDT 24 Jul 01 10:50:17 AM PDT 24 1635088957 ps
T295 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.247101986 Jul 01 10:49:55 AM PDT 24 Jul 01 10:49:57 AM PDT 24 556211062 ps
T296 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2200444996 Jul 01 10:49:44 AM PDT 24 Jul 01 10:49:46 AM PDT 24 726450398 ps
T297 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3212868486 Jul 01 10:49:44 AM PDT 24 Jul 01 10:49:46 AM PDT 24 361423423 ps
T76 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4001059815 Jul 01 10:49:44 AM PDT 24 Jul 01 10:49:46 AM PDT 24 418020903 ps
T298 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2657655572 Jul 01 10:50:03 AM PDT 24 Jul 01 10:50:04 AM PDT 24 342623226 ps
T63 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3306372459 Jul 01 10:50:16 AM PDT 24 Jul 01 10:50:19 AM PDT 24 424193430 ps
T299 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2247159901 Jul 01 10:50:12 AM PDT 24 Jul 01 10:50:16 AM PDT 24 380006122 ps
T300 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4169555823 Jul 01 10:50:08 AM PDT 24 Jul 01 10:50:15 AM PDT 24 588570406 ps
T301 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.51411802 Jul 01 10:50:06 AM PDT 24 Jul 01 10:50:09 AM PDT 24 434147394 ps
T77 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1708594748 Jul 01 10:49:51 AM PDT 24 Jul 01 10:49:53 AM PDT 24 420461483 ps
T302 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2404054644 Jul 01 10:49:59 AM PDT 24 Jul 01 10:50:01 AM PDT 24 413226480 ps
T64 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.560116346 Jul 01 10:49:37 AM PDT 24 Jul 01 10:49:39 AM PDT 24 1224499125 ps
T78 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3975811626 Jul 01 10:50:00 AM PDT 24 Jul 01 10:50:02 AM PDT 24 395821764 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.557378158 Jul 01 10:49:47 AM PDT 24 Jul 01 10:49:51 AM PDT 24 809938088 ps
T304 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2982640419 Jul 01 10:49:39 AM PDT 24 Jul 01 10:49:40 AM PDT 24 404613431 ps
T305 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.4234587852 Jul 01 10:49:55 AM PDT 24 Jul 01 10:49:57 AM PDT 24 465837214 ps
T79 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3733017051 Jul 01 10:49:53 AM PDT 24 Jul 01 10:49:55 AM PDT 24 2944069505 ps
T306 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1495388374 Jul 01 10:49:51 AM PDT 24 Jul 01 10:49:53 AM PDT 24 553338528 ps
T192 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2333380284 Jul 01 10:49:50 AM PDT 24 Jul 01 10:49:54 AM PDT 24 8334126341 ps
T307 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1060602193 Jul 01 10:49:42 AM PDT 24 Jul 01 10:49:44 AM PDT 24 434547575 ps
T308 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1857603412 Jul 01 10:49:43 AM PDT 24 Jul 01 10:49:52 AM PDT 24 4172407220 ps
T309 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2940993363 Jul 01 10:49:54 AM PDT 24 Jul 01 10:49:56 AM PDT 24 458094471 ps
T310 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2479493455 Jul 01 10:50:10 AM PDT 24 Jul 01 10:50:14 AM PDT 24 326130820 ps
T193 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.448232481 Jul 01 10:49:48 AM PDT 24 Jul 01 10:49:51 AM PDT 24 4763801629 ps
T65 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.646707723 Jul 01 10:50:09 AM PDT 24 Jul 01 10:50:13 AM PDT 24 387205300 ps
T80 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.610141552 Jul 01 10:49:48 AM PDT 24 Jul 01 10:49:50 AM PDT 24 2577042776 ps
T311 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3737100171 Jul 01 10:49:51 AM PDT 24 Jul 01 10:49:52 AM PDT 24 507977604 ps
T66 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4005797192 Jul 01 10:49:48 AM PDT 24 Jul 01 10:49:50 AM PDT 24 513401741 ps
T312 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3954059093 Jul 01 10:50:04 AM PDT 24 Jul 01 10:50:06 AM PDT 24 667396686 ps
T313 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2423955223 Jul 01 10:50:00 AM PDT 24 Jul 01 10:50:01 AM PDT 24 442863518 ps
T81 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2380223813 Jul 01 10:49:38 AM PDT 24 Jul 01 10:49:44 AM PDT 24 1797440473 ps
T314 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.997319098 Jul 01 10:49:59 AM PDT 24 Jul 01 10:50:06 AM PDT 24 8445892359 ps
T315 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.81970090 Jul 01 10:49:43 AM PDT 24 Jul 01 10:49:45 AM PDT 24 478288461 ps
T316 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1949108327 Jul 01 10:50:00 AM PDT 24 Jul 01 10:50:02 AM PDT 24 391026567 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.453409609 Jul 01 10:50:06 AM PDT 24 Jul 01 10:50:07 AM PDT 24 445728390 ps
T317 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2349123371 Jul 01 10:49:55 AM PDT 24 Jul 01 10:49:56 AM PDT 24 293898234 ps
T318 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.366527455 Jul 01 10:49:56 AM PDT 24 Jul 01 10:49:57 AM PDT 24 447415062 ps
T319 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.540589541 Jul 01 10:49:59 AM PDT 24 Jul 01 10:50:01 AM PDT 24 460703577 ps
T320 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2721081418 Jul 01 10:49:52 AM PDT 24 Jul 01 10:49:53 AM PDT 24 451982754 ps
T321 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.105154822 Jul 01 10:49:39 AM PDT 24 Jul 01 10:49:40 AM PDT 24 324171376 ps
T322 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1627407350 Jul 01 10:50:08 AM PDT 24 Jul 01 10:50:10 AM PDT 24 447911643 ps
T69 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1595830176 Jul 01 10:49:57 AM PDT 24 Jul 01 10:49:59 AM PDT 24 412396941 ps
T323 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2674102717 Jul 01 10:49:51 AM PDT 24 Jul 01 10:49:54 AM PDT 24 549704042 ps
T324 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.477041231 Jul 01 10:49:41 AM PDT 24 Jul 01 10:49:42 AM PDT 24 523541900 ps
T82 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4240848412 Jul 01 10:49:52 AM PDT 24 Jul 01 10:49:55 AM PDT 24 1532363682 ps
T325 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2915158040 Jul 01 10:49:33 AM PDT 24 Jul 01 10:49:35 AM PDT 24 4521622536 ps
T326 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.190961099 Jul 01 10:49:45 AM PDT 24 Jul 01 10:49:48 AM PDT 24 442984986 ps
T327 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2869452641 Jul 01 10:49:56 AM PDT 24 Jul 01 10:49:59 AM PDT 24 488678399 ps
T328 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3692977926 Jul 01 10:50:12 AM PDT 24 Jul 01 10:50:17 AM PDT 24 395499302 ps
T329 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1915227902 Jul 01 10:49:53 AM PDT 24 Jul 01 10:49:54 AM PDT 24 507952262 ps
T330 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1185040782 Jul 01 10:49:45 AM PDT 24 Jul 01 10:49:49 AM PDT 24 2055152827 ps
T331 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4086100667 Jul 01 10:49:51 AM PDT 24 Jul 01 10:49:54 AM PDT 24 910008174 ps
T332 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2426565548 Jul 01 10:49:44 AM PDT 24 Jul 01 10:49:46 AM PDT 24 330581004 ps
T333 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.270393813 Jul 01 10:49:57 AM PDT 24 Jul 01 10:49:58 AM PDT 24 448496343 ps
T334 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.909969207 Jul 01 10:49:37 AM PDT 24 Jul 01 10:49:39 AM PDT 24 348602319 ps
T335 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1772167742 Jul 01 10:49:31 AM PDT 24 Jul 01 10:49:33 AM PDT 24 458861304 ps
T336 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.175438025 Jul 01 10:49:58 AM PDT 24 Jul 01 10:50:00 AM PDT 24 439409071 ps
T194 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.145657498 Jul 01 10:49:55 AM PDT 24 Jul 01 10:49:58 AM PDT 24 8741242485 ps
T337 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1033818867 Jul 01 10:49:37 AM PDT 24 Jul 01 10:49:39 AM PDT 24 372887095 ps
T338 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.609509055 Jul 01 10:49:50 AM PDT 24 Jul 01 10:49:54 AM PDT 24 467941412 ps
T339 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3598128930 Jul 01 10:50:07 AM PDT 24 Jul 01 10:50:09 AM PDT 24 383330323 ps
T70 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2756685879 Jul 01 10:49:48 AM PDT 24 Jul 01 10:49:50 AM PDT 24 406622566 ps
T340 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.57769557 Jul 01 10:49:55 AM PDT 24 Jul 01 10:49:57 AM PDT 24 351509377 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4250028402 Jul 01 10:49:42 AM PDT 24 Jul 01 10:49:45 AM PDT 24 2419882989 ps
T342 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1092008793 Jul 01 10:49:38 AM PDT 24 Jul 01 10:49:42 AM PDT 24 2770788482 ps
T343 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1286185101 Jul 01 10:49:40 AM PDT 24 Jul 01 10:49:42 AM PDT 24 546600081 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2535062197 Jul 01 10:49:36 AM PDT 24 Jul 01 10:49:42 AM PDT 24 7247526785 ps
T345 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4013818658 Jul 01 10:49:59 AM PDT 24 Jul 01 10:50:01 AM PDT 24 309386491 ps
T346 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2055900515 Jul 01 10:49:48 AM PDT 24 Jul 01 10:49:50 AM PDT 24 603547521 ps
T347 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.146461879 Jul 01 10:50:10 AM PDT 24 Jul 01 10:50:14 AM PDT 24 407306182 ps
T348 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1593975012 Jul 01 10:49:29 AM PDT 24 Jul 01 10:49:36 AM PDT 24 8686700643 ps
T349 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2078017496 Jul 01 10:49:46 AM PDT 24 Jul 01 10:49:48 AM PDT 24 365845285 ps
T71 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2189973887 Jul 01 10:50:03 AM PDT 24 Jul 01 10:50:04 AM PDT 24 535957372 ps
T350 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3735543330 Jul 01 10:49:54 AM PDT 24 Jul 01 10:49:56 AM PDT 24 358687658 ps
T351 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2444501561 Jul 01 10:50:06 AM PDT 24 Jul 01 10:50:08 AM PDT 24 431853107 ps
T352 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3537125613 Jul 01 10:49:37 AM PDT 24 Jul 01 10:49:39 AM PDT 24 389577761 ps
T353 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.120261098 Jul 01 10:49:51 AM PDT 24 Jul 01 10:49:55 AM PDT 24 2242146127 ps
T354 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.820664910 Jul 01 10:49:40 AM PDT 24 Jul 01 10:49:43 AM PDT 24 609599944 ps
T355 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1017624979 Jul 01 10:50:10 AM PDT 24 Jul 01 10:50:14 AM PDT 24 344929740 ps
T356 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1638335303 Jul 01 10:50:10 AM PDT 24 Jul 01 10:50:14 AM PDT 24 437183952 ps
T357 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2763479744 Jul 01 10:49:58 AM PDT 24 Jul 01 10:50:00 AM PDT 24 407590839 ps
T358 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3716720156 Jul 01 10:50:13 AM PDT 24 Jul 01 10:50:18 AM PDT 24 4150201364 ps
T359 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2631290627 Jul 01 10:49:49 AM PDT 24 Jul 01 10:50:40 AM PDT 24 14132227148 ps
T360 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4172164108 Jul 01 10:49:55 AM PDT 24 Jul 01 10:49:56 AM PDT 24 532579669 ps
T361 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1648997624 Jul 01 10:49:58 AM PDT 24 Jul 01 10:50:00 AM PDT 24 525291209 ps
T362 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2186070795 Jul 01 10:49:57 AM PDT 24 Jul 01 10:49:59 AM PDT 24 407821999 ps
T363 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1988622455 Jul 01 10:49:56 AM PDT 24 Jul 01 10:49:58 AM PDT 24 368034843 ps
T364 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.146278951 Jul 01 10:49:55 AM PDT 24 Jul 01 10:49:57 AM PDT 24 377661142 ps
T365 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4106640608 Jul 01 10:50:04 AM PDT 24 Jul 01 10:50:06 AM PDT 24 514024878 ps
T68 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.770862425 Jul 01 10:49:53 AM PDT 24 Jul 01 10:50:16 AM PDT 24 8883254485 ps
T366 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2661941702 Jul 01 10:50:07 AM PDT 24 Jul 01 10:50:24 AM PDT 24 7972045569 ps
T367 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4073512646 Jul 01 10:49:58 AM PDT 24 Jul 01 10:50:00 AM PDT 24 294859189 ps
T368 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4276115733 Jul 01 10:49:51 AM PDT 24 Jul 01 10:49:53 AM PDT 24 721707594 ps
T369 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1566734998 Jul 01 10:49:43 AM PDT 24 Jul 01 10:49:46 AM PDT 24 417037321 ps
T72 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1663502370 Jul 01 10:50:05 AM PDT 24 Jul 01 10:50:07 AM PDT 24 366942091 ps
T370 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3965067389 Jul 01 10:49:46 AM PDT 24 Jul 01 10:49:50 AM PDT 24 1182640796 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.443993476 Jul 01 10:49:43 AM PDT 24 Jul 01 10:49:46 AM PDT 24 1071091241 ps
T372 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2586494756 Jul 01 10:49:59 AM PDT 24 Jul 01 10:50:01 AM PDT 24 315383257 ps
T373 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3049319226 Jul 01 10:50:02 AM PDT 24 Jul 01 10:50:04 AM PDT 24 2358200068 ps
T374 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.441847702 Jul 01 10:50:06 AM PDT 24 Jul 01 10:50:09 AM PDT 24 514820080 ps
T375 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4117397088 Jul 01 10:49:41 AM PDT 24 Jul 01 10:49:43 AM PDT 24 1472441379 ps
T376 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1860728099 Jul 01 10:50:08 AM PDT 24 Jul 01 10:50:19 AM PDT 24 7308776208 ps
T377 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3482784144 Jul 01 10:50:10 AM PDT 24 Jul 01 10:50:15 AM PDT 24 1333232008 ps
T378 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2291451980 Jul 01 10:50:08 AM PDT 24 Jul 01 10:50:17 AM PDT 24 2793243081 ps
T379 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3465347277 Jul 01 10:50:06 AM PDT 24 Jul 01 10:50:11 AM PDT 24 4333750599 ps
T380 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3718416574 Jul 01 10:49:57 AM PDT 24 Jul 01 10:49:58 AM PDT 24 277259727 ps
T381 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2967460109 Jul 01 10:50:09 AM PDT 24 Jul 01 10:50:12 AM PDT 24 374938868 ps
T382 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1727751489 Jul 01 10:49:44 AM PDT 24 Jul 01 10:49:46 AM PDT 24 327946566 ps
T383 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3383608810 Jul 01 10:49:43 AM PDT 24 Jul 01 10:49:49 AM PDT 24 3952079698 ps
T384 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3350306086 Jul 01 10:50:07 AM PDT 24 Jul 01 10:50:11 AM PDT 24 353819334 ps
T385 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1920843658 Jul 01 10:49:52 AM PDT 24 Jul 01 10:49:53 AM PDT 24 2430698885 ps
T386 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2136968069 Jul 01 10:49:45 AM PDT 24 Jul 01 10:49:49 AM PDT 24 7753273083 ps
T387 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2041146227 Jul 01 10:49:58 AM PDT 24 Jul 01 10:50:00 AM PDT 24 414952470 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.502466072 Jul 01 10:50:05 AM PDT 24 Jul 01 10:50:07 AM PDT 24 490083507 ps
T389 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.551342682 Jul 01 10:49:46 AM PDT 24 Jul 01 10:49:49 AM PDT 24 520597251 ps
T390 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.323693923 Jul 01 10:49:40 AM PDT 24 Jul 01 10:49:43 AM PDT 24 619357253 ps
T391 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.747616149 Jul 01 10:50:07 AM PDT 24 Jul 01 10:50:09 AM PDT 24 446278576 ps
T392 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.657734560 Jul 01 10:49:52 AM PDT 24 Jul 01 10:49:54 AM PDT 24 269995806 ps
T393 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.437407794 Jul 01 10:49:48 AM PDT 24 Jul 01 10:49:50 AM PDT 24 386755107 ps
T394 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1815483825 Jul 01 10:50:09 AM PDT 24 Jul 01 10:50:15 AM PDT 24 446861883 ps
T73 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2045098918 Jul 01 10:50:05 AM PDT 24 Jul 01 10:50:06 AM PDT 24 417835416 ps
T395 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2781433376 Jul 01 10:49:59 AM PDT 24 Jul 01 10:50:01 AM PDT 24 308205457 ps
T396 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2917341124 Jul 01 10:50:06 AM PDT 24 Jul 01 10:50:08 AM PDT 24 341966402 ps
T397 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3906554476 Jul 01 10:50:08 AM PDT 24 Jul 01 10:50:10 AM PDT 24 439054248 ps
T398 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2682745094 Jul 01 10:50:05 AM PDT 24 Jul 01 10:50:08 AM PDT 24 1258162016 ps
T399 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.402887375 Jul 01 10:50:08 AM PDT 24 Jul 01 10:50:11 AM PDT 24 368763906 ps
T400 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3040221649 Jul 01 10:49:58 AM PDT 24 Jul 01 10:49:59 AM PDT 24 405908740 ps
T401 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3170844375 Jul 01 10:50:00 AM PDT 24 Jul 01 10:50:02 AM PDT 24 378320998 ps
T402 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.783080065 Jul 01 10:49:46 AM PDT 24 Jul 01 10:49:48 AM PDT 24 300118637 ps
T191 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3452316900 Jul 01 10:49:50 AM PDT 24 Jul 01 10:49:54 AM PDT 24 9086766705 ps
T403 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.19439230 Jul 01 10:50:11 AM PDT 24 Jul 01 10:50:18 AM PDT 24 1558468957 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3401028275 Jul 01 10:49:37 AM PDT 24 Jul 01 10:49:39 AM PDT 24 603526708 ps
T405 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2148181109 Jul 01 10:49:43 AM PDT 24 Jul 01 10:49:45 AM PDT 24 444530075 ps
T406 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.726906316 Jul 01 10:49:28 AM PDT 24 Jul 01 10:49:30 AM PDT 24 392856279 ps
T407 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1885051159 Jul 01 10:49:57 AM PDT 24 Jul 01 10:49:59 AM PDT 24 1218308148 ps
T408 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2087220408 Jul 01 10:50:08 AM PDT 24 Jul 01 10:50:14 AM PDT 24 615456536 ps
T409 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1226257664 Jul 01 10:49:43 AM PDT 24 Jul 01 10:49:46 AM PDT 24 479844102 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.412804250 Jul 01 10:50:06 AM PDT 24 Jul 01 10:50:14 AM PDT 24 8514809336 ps
T411 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2675651479 Jul 01 10:49:59 AM PDT 24 Jul 01 10:50:00 AM PDT 24 493216673 ps
T412 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2257181877 Jul 01 10:50:04 AM PDT 24 Jul 01 10:50:06 AM PDT 24 764073597 ps
T413 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.207644038 Jul 01 10:49:59 AM PDT 24 Jul 01 10:50:01 AM PDT 24 388946430 ps
T414 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2769480684 Jul 01 10:50:08 AM PDT 24 Jul 01 10:50:11 AM PDT 24 966582658 ps
T415 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1930115270 Jul 01 10:49:57 AM PDT 24 Jul 01 10:50:00 AM PDT 24 4287507243 ps
T416 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3508759380 Jul 01 10:49:48 AM PDT 24 Jul 01 10:49:57 AM PDT 24 4383772653 ps

Test location /workspace/coverage/default/33.aon_timer_stress_all.1285590395
Short name T5
Test name
Test status
Simulation time 394789036539 ps
CPU time 42.12 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:52:34 AM PDT 24
Peak memory 197944 kb
Host smart-9dd1c374-bfa6-4b14-b4b0-9b6b46b09e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285590395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1285590395
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.898128368
Short name T1
Test name
Test status
Simulation time 130049819671 ps
CPU time 443.37 seconds
Started Jul 01 10:51:35 AM PDT 24
Finished Jul 01 10:58:59 AM PDT 24
Peak memory 202852 kb
Host smart-c48094cf-fdb5-4d19-8c66-566cba926647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898128368 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.898128368
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3982051957
Short name T34
Test name
Test status
Simulation time 7960444446 ps
CPU time 11.1 seconds
Started Jul 01 10:49:32 AM PDT 24
Finished Jul 01 10:49:43 AM PDT 24
Peak memory 198284 kb
Host smart-e2ef33c2-1d2b-48c5-9f4a-c7e47aa9d606
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982051957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3982051957
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3785593918
Short name T43
Test name
Test status
Simulation time 648033866739 ps
CPU time 650.62 seconds
Started Jul 01 10:51:08 AM PDT 24
Finished Jul 01 11:02:00 AM PDT 24
Peak memory 214440 kb
Host smart-22004bea-4462-4211-981f-23e3ca6c7cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785593918 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3785593918
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2643081551
Short name T40
Test name
Test status
Simulation time 142341402151 ps
CPU time 304.35 seconds
Started Jul 01 10:51:26 AM PDT 24
Finished Jul 01 10:56:31 AM PDT 24
Peak memory 201272 kb
Host smart-891e3cc7-e545-4074-b315-202f1452feda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643081551 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2643081551
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1415788889
Short name T130
Test name
Test status
Simulation time 161759939317 ps
CPU time 605 seconds
Started Jul 01 10:51:40 AM PDT 24
Finished Jul 01 11:01:46 AM PDT 24
Peak memory 212992 kb
Host smart-58373935-9ef6-4da2-b40d-d084f14a8e46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415788889 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1415788889
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.4233631184
Short name T123
Test name
Test status
Simulation time 204781692459 ps
CPU time 665.47 seconds
Started Jul 01 10:51:53 AM PDT 24
Finished Jul 01 11:03:00 AM PDT 24
Peak memory 213228 kb
Host smart-f3199514-f65a-4310-ba95-4b46ff3a6649
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233631184 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.4233631184
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1156523387
Short name T91
Test name
Test status
Simulation time 32105970252 ps
CPU time 227.46 seconds
Started Jul 01 10:51:40 AM PDT 24
Finished Jul 01 10:55:28 AM PDT 24
Peak memory 213920 kb
Host smart-19ca72a9-aa7c-449f-b24e-5caa8ec53b93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156523387 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1156523387
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3243681199
Short name T116
Test name
Test status
Simulation time 31789099704 ps
CPU time 220.65 seconds
Started Jul 01 10:51:11 AM PDT 24
Finished Jul 01 10:54:52 AM PDT 24
Peak memory 206524 kb
Host smart-4b5fd4bd-55cc-4b0a-8a4b-643891474913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243681199 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3243681199
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2061791243
Short name T113
Test name
Test status
Simulation time 210952249753 ps
CPU time 307.24 seconds
Started Jul 01 10:51:45 AM PDT 24
Finished Jul 01 10:56:53 AM PDT 24
Peak memory 198012 kb
Host smart-bce7c358-9cef-46ad-b893-0788c024e0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061791243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2061791243
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.837616983
Short name T22
Test name
Test status
Simulation time 4546505977 ps
CPU time 7.4 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:06 AM PDT 24
Peak memory 215604 kb
Host smart-4bd2ac8f-c2e0-4de4-b6f0-c32a42d7dd4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837616983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.837616983
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1035931124
Short name T101
Test name
Test status
Simulation time 232191942646 ps
CPU time 86.16 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:53:15 AM PDT 24
Peak memory 192700 kb
Host smart-7ceebb98-3b81-4fe0-ab65-b9dd3ac89bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035931124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1035931124
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2955175985
Short name T137
Test name
Test status
Simulation time 254533254517 ps
CPU time 477.78 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:59:49 AM PDT 24
Peak memory 211604 kb
Host smart-cd928fd2-1a1f-41ff-b62d-22de7c0cc892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955175985 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2955175985
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3749439205
Short name T126
Test name
Test status
Simulation time 69867063035 ps
CPU time 17.68 seconds
Started Jul 01 10:51:26 AM PDT 24
Finished Jul 01 10:51:45 AM PDT 24
Peak memory 191704 kb
Host smart-a175c402-a8f6-41ac-9916-b2b82285b637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749439205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3749439205
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.396714723
Short name T102
Test name
Test status
Simulation time 136542631621 ps
CPU time 112.49 seconds
Started Jul 01 10:51:05 AM PDT 24
Finished Jul 01 10:52:58 AM PDT 24
Peak memory 198200 kb
Host smart-4d33b1ba-2588-419e-8520-0afcfac853e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396714723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.396714723
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1162760158
Short name T16
Test name
Test status
Simulation time 36529467039 ps
CPU time 278.68 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:56:28 AM PDT 24
Peak memory 198420 kb
Host smart-14da83a3-2df9-4f69-9b8b-1cf3a50eb81d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162760158 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1162760158
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2628252155
Short name T84
Test name
Test status
Simulation time 55062558650 ps
CPU time 126.16 seconds
Started Jul 01 10:51:41 AM PDT 24
Finished Jul 01 10:53:48 AM PDT 24
Peak memory 206552 kb
Host smart-e74c7dc3-f43f-4d39-bc56-d8d765078177
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628252155 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2628252155
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1923195615
Short name T94
Test name
Test status
Simulation time 33141120068 ps
CPU time 336.82 seconds
Started Jul 01 10:51:09 AM PDT 24
Finished Jul 01 10:56:46 AM PDT 24
Peak memory 198628 kb
Host smart-aa97e40b-d38e-4b7f-9a32-9c0fa5e5163e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923195615 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1923195615
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2880150522
Short name T142
Test name
Test status
Simulation time 38535896952 ps
CPU time 275.92 seconds
Started Jul 01 10:51:56 AM PDT 24
Finished Jul 01 10:56:33 AM PDT 24
Peak memory 198232 kb
Host smart-75446b29-d889-4aad-b0d4-b020eeabf0fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880150522 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2880150522
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1217464677
Short name T96
Test name
Test status
Simulation time 87863914030 ps
CPU time 284.61 seconds
Started Jul 01 10:51:10 AM PDT 24
Finished Jul 01 10:55:55 AM PDT 24
Peak memory 201672 kb
Host smart-2aa6f703-3b60-4226-8bbf-eb774e0c62fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217464677 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1217464677
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3587227876
Short name T158
Test name
Test status
Simulation time 239441462224 ps
CPU time 408.3 seconds
Started Jul 01 10:51:31 AM PDT 24
Finished Jul 01 10:58:20 AM PDT 24
Peak memory 206584 kb
Host smart-48c93f17-71ed-488f-aa84-5000b9c109d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587227876 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3587227876
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3357148643
Short name T42
Test name
Test status
Simulation time 171341304956 ps
CPU time 331.92 seconds
Started Jul 01 10:51:23 AM PDT 24
Finished Jul 01 10:56:56 AM PDT 24
Peak memory 213676 kb
Host smart-48bc8d08-6169-4045-8470-8a55a1aacbc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357148643 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3357148643
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.896479791
Short name T131
Test name
Test status
Simulation time 139322712900 ps
CPU time 212.58 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:55:22 AM PDT 24
Peak memory 192768 kb
Host smart-686cd1d0-3c6f-4a43-940f-b186e66b1f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896479791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.896479791
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2518435325
Short name T159
Test name
Test status
Simulation time 85091850593 ps
CPU time 485.08 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:59:57 AM PDT 24
Peak memory 204008 kb
Host smart-295323ef-59ed-47a9-a623-b8a830a643f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518435325 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2518435325
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.713723040
Short name T44
Test name
Test status
Simulation time 64466984247 ps
CPU time 238.65 seconds
Started Jul 01 10:51:54 AM PDT 24
Finished Jul 01 10:55:54 AM PDT 24
Peak memory 198900 kb
Host smart-a4df3445-fcee-4107-9cc1-e7bc95b6e3d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713723040 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.713723040
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3338662360
Short name T112
Test name
Test status
Simulation time 43508604777 ps
CPU time 10.79 seconds
Started Jul 01 10:51:08 AM PDT 24
Finished Jul 01 10:51:19 AM PDT 24
Peak memory 192752 kb
Host smart-e79b0944-2308-4df1-aea1-185cede4611f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338662360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3338662360
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2135447122
Short name T132
Test name
Test status
Simulation time 117438840068 ps
CPU time 86.35 seconds
Started Jul 01 10:51:10 AM PDT 24
Finished Jul 01 10:52:37 AM PDT 24
Peak memory 192740 kb
Host smart-d6c8c0d0-fdbf-4762-85a2-422cb68fcf4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135447122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2135447122
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.455108737
Short name T6
Test name
Test status
Simulation time 284353834382 ps
CPU time 200.41 seconds
Started Jul 01 10:51:43 AM PDT 24
Finished Jul 01 10:55:04 AM PDT 24
Peak memory 192612 kb
Host smart-71857716-2394-4a61-ba9a-ab26e2430687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455108737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.455108737
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2597756152
Short name T37
Test name
Test status
Simulation time 142999890861 ps
CPU time 188.83 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:55:00 AM PDT 24
Peak memory 192676 kb
Host smart-e26b3e85-063a-477d-8ca9-736c1264bad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597756152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2597756152
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.948291028
Short name T129
Test name
Test status
Simulation time 180027053310 ps
CPU time 584.18 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 11:01:37 AM PDT 24
Peak memory 213776 kb
Host smart-ca75406b-c5d4-43b8-8f1c-b1f05765583a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948291028 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.948291028
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3123253679
Short name T150
Test name
Test status
Simulation time 47759521246 ps
CPU time 492.4 seconds
Started Jul 01 10:51:12 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 201448 kb
Host smart-2a4fc35d-8b1b-4722-b6bd-375697cf6a41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123253679 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3123253679
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3991275073
Short name T95
Test name
Test status
Simulation time 208520151622 ps
CPU time 334.2 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:57:26 AM PDT 24
Peak memory 192344 kb
Host smart-2a1a928e-681b-4e38-9341-44d3320d5137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991275073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3991275073
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.846242302
Short name T118
Test name
Test status
Simulation time 112835372628 ps
CPU time 16.69 seconds
Started Jul 01 10:51:33 AM PDT 24
Finished Jul 01 10:51:50 AM PDT 24
Peak memory 191732 kb
Host smart-7d3c361c-7ade-43f6-a540-40eaf578735c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846242302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.846242302
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3469107901
Short name T145
Test name
Test status
Simulation time 78023358736 ps
CPU time 25.76 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:52:17 AM PDT 24
Peak memory 192380 kb
Host smart-dd94157b-d06e-4a50-a336-5e7225a5efc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469107901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3469107901
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3496848118
Short name T152
Test name
Test status
Simulation time 49407249033 ps
CPU time 73.74 seconds
Started Jul 01 10:51:12 AM PDT 24
Finished Jul 01 10:52:27 AM PDT 24
Peak memory 184308 kb
Host smart-76364da4-4e09-4ebc-ad3c-47acdd697942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496848118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3496848118
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2163933078
Short name T15
Test name
Test status
Simulation time 96779628713 ps
CPU time 35.1 seconds
Started Jul 01 10:51:29 AM PDT 24
Finished Jul 01 10:52:04 AM PDT 24
Peak memory 192668 kb
Host smart-87731218-c757-406f-a7f5-1a0ee27d305e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163933078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2163933078
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.836326922
Short name T98
Test name
Test status
Simulation time 416998721319 ps
CPU time 282.73 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:56:33 AM PDT 24
Peak memory 209380 kb
Host smart-831b1d38-bab5-484a-9b12-1bd499bc67bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836326922 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.836326922
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2351559347
Short name T87
Test name
Test status
Simulation time 486510554404 ps
CPU time 1207.53 seconds
Started Jul 01 10:51:40 AM PDT 24
Finished Jul 01 11:11:48 AM PDT 24
Peak memory 212188 kb
Host smart-b0e5fd01-f601-460e-9313-1f395c475b5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351559347 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2351559347
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2013526033
Short name T127
Test name
Test status
Simulation time 171908152816 ps
CPU time 130.33 seconds
Started Jul 01 10:51:53 AM PDT 24
Finished Jul 01 10:54:05 AM PDT 24
Peak memory 191664 kb
Host smart-d5ef7ec6-dcd3-434c-95b4-0247f317a806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013526033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2013526033
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3439204941
Short name T54
Test name
Test status
Simulation time 30886034480 ps
CPU time 13.52 seconds
Started Jul 01 10:51:16 AM PDT 24
Finished Jul 01 10:51:30 AM PDT 24
Peak memory 192252 kb
Host smart-af28acd8-42ee-482a-aec9-dae81a57527f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439204941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3439204941
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2808931572
Short name T114
Test name
Test status
Simulation time 169501396742 ps
CPU time 114.72 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:53:46 AM PDT 24
Peak memory 183960 kb
Host smart-ec75f474-737e-4076-9f9f-cc01ac3b3dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808931572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2808931572
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1911933582
Short name T99
Test name
Test status
Simulation time 146678381289 ps
CPU time 225.49 seconds
Started Jul 01 10:51:31 AM PDT 24
Finished Jul 01 10:55:18 AM PDT 24
Peak memory 198020 kb
Host smart-ef86a1ab-a34f-4e1e-9aff-ee1beafbf1e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911933582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1911933582
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3910184575
Short name T138
Test name
Test status
Simulation time 244832900673 ps
CPU time 246.74 seconds
Started Jul 01 10:51:30 AM PDT 24
Finished Jul 01 10:55:38 AM PDT 24
Peak memory 183860 kb
Host smart-ec80176f-39e4-4435-ab62-8a1371f10212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910184575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3910184575
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3105162567
Short name T124
Test name
Test status
Simulation time 134955798983 ps
CPU time 207.57 seconds
Started Jul 01 10:51:40 AM PDT 24
Finished Jul 01 10:55:09 AM PDT 24
Peak memory 192744 kb
Host smart-98ca3a91-693a-4011-bd88-dad62491d6e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105162567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3105162567
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.66465421
Short name T134
Test name
Test status
Simulation time 589313917313 ps
CPU time 777.09 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 11:04:49 AM PDT 24
Peak memory 192672 kb
Host smart-5578c69a-2b0e-436c-a62f-35866f7ee050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66465421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_al
l.66465421
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.921344118
Short name T120
Test name
Test status
Simulation time 212698243800 ps
CPU time 165.15 seconds
Started Jul 01 10:51:56 AM PDT 24
Finished Jul 01 10:54:42 AM PDT 24
Peak memory 192664 kb
Host smart-c0624634-9907-4568-9032-edc44aab32fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921344118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.921344118
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3621971741
Short name T108
Test name
Test status
Simulation time 170208813175 ps
CPU time 232.09 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:55:45 AM PDT 24
Peak memory 192328 kb
Host smart-7761498b-7887-44af-9976-b01486d96ace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621971741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3621971741
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3180241031
Short name T93
Test name
Test status
Simulation time 92950129391 ps
CPU time 30.73 seconds
Started Jul 01 10:51:58 AM PDT 24
Finished Jul 01 10:52:30 AM PDT 24
Peak memory 198152 kb
Host smart-a0bf74c1-62c3-467f-ab11-d32f5caa51f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180241031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3180241031
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1498954413
Short name T8
Test name
Test status
Simulation time 221741193265 ps
CPU time 38.64 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:40 AM PDT 24
Peak memory 192880 kb
Host smart-4792cb0b-5c83-42bc-be7c-ec9e9bdc9201
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498954413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1498954413
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3134777313
Short name T45
Test name
Test status
Simulation time 65345516164 ps
CPU time 407.34 seconds
Started Jul 01 10:51:31 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 200032 kb
Host smart-2330ccf5-f28e-4304-b2a9-2977152896bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134777313 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3134777313
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3238677190
Short name T83
Test name
Test status
Simulation time 292784714732 ps
CPU time 353.43 seconds
Started Jul 01 10:51:21 AM PDT 24
Finished Jul 01 10:57:15 AM PDT 24
Peak memory 201232 kb
Host smart-f75127b0-33ae-4807-86e1-33850d6191ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238677190 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3238677190
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1947464694
Short name T17
Test name
Test status
Simulation time 38571340949 ps
CPU time 133.73 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:54:08 AM PDT 24
Peak memory 198416 kb
Host smart-4994fa04-a8aa-41f9-b461-e7261a038d95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947464694 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1947464694
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.803858340
Short name T88
Test name
Test status
Simulation time 62476836750 ps
CPU time 617.3 seconds
Started Jul 01 10:51:18 AM PDT 24
Finished Jul 01 11:01:36 AM PDT 24
Peak memory 211448 kb
Host smart-d4a6f1e2-6875-4096-a91a-1b037ca1d558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803858340 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.803858340
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.566944519
Short name T90
Test name
Test status
Simulation time 59554916167 ps
CPU time 230.75 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:55:41 AM PDT 24
Peak memory 206756 kb
Host smart-bc1fcf66-8f79-426f-9f09-368e47321b82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566944519 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.566944519
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4005797192
Short name T66
Test name
Test status
Simulation time 513401741 ps
CPU time 0.97 seconds
Started Jul 01 10:49:48 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 183768 kb
Host smart-09918388-e47f-4933-ab3a-0722a841cb5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005797192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4005797192
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3975811626
Short name T78
Test name
Test status
Simulation time 395821764 ps
CPU time 0.96 seconds
Started Jul 01 10:50:00 AM PDT 24
Finished Jul 01 10:50:02 AM PDT 24
Peak memory 193300 kb
Host smart-02680816-9761-4371-babd-24c70e6ff486
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975811626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3975811626
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3391804579
Short name T165
Test name
Test status
Simulation time 221638219610 ps
CPU time 357.47 seconds
Started Jul 01 10:51:16 AM PDT 24
Finished Jul 01 10:57:14 AM PDT 24
Peak memory 192728 kb
Host smart-b22773e6-2a81-4b9c-8b69-46b02ab6df36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391804579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3391804579
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1846758534
Short name T57
Test name
Test status
Simulation time 258968057305 ps
CPU time 186.17 seconds
Started Jul 01 10:51:33 AM PDT 24
Finished Jul 01 10:54:39 AM PDT 24
Peak memory 192748 kb
Host smart-dc188ae4-4df6-4a79-97b4-aab9a15bc132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846758534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1846758534
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.279205968
Short name T121
Test name
Test status
Simulation time 168057224077 ps
CPU time 58.28 seconds
Started Jul 01 10:51:31 AM PDT 24
Finished Jul 01 10:52:30 AM PDT 24
Peak memory 193032 kb
Host smart-b02f797a-a09d-4e3f-934e-2950f2b0f8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279205968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.279205968
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.481865610
Short name T103
Test name
Test status
Simulation time 160777936339 ps
CPU time 316.74 seconds
Started Jul 01 10:51:05 AM PDT 24
Finished Jul 01 10:56:22 AM PDT 24
Peak memory 210020 kb
Host smart-265e0660-43d1-4bd4-9939-6d5870f932bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481865610 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.481865610
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4072464412
Short name T86
Test name
Test status
Simulation time 14998172845 ps
CPU time 72.35 seconds
Started Jul 01 10:51:03 AM PDT 24
Finished Jul 01 10:52:15 AM PDT 24
Peak memory 206596 kb
Host smart-1f1bafab-d63c-4765-b6b2-6b3c38fda25a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072464412 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4072464412
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2353710508
Short name T141
Test name
Test status
Simulation time 59980560814 ps
CPU time 162.2 seconds
Started Jul 01 10:51:26 AM PDT 24
Finished Jul 01 10:54:09 AM PDT 24
Peak memory 206588 kb
Host smart-12ec2b98-1705-456f-b3f2-d36de97ed71f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353710508 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2353710508
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1823449751
Short name T100
Test name
Test status
Simulation time 296303091876 ps
CPU time 230.43 seconds
Started Jul 01 10:51:26 AM PDT 24
Finished Jul 01 10:55:17 AM PDT 24
Peak memory 192744 kb
Host smart-4c0d6ae7-95db-4c61-baaa-b435ef2b1aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823449751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1823449751
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3854111978
Short name T140
Test name
Test status
Simulation time 456025908 ps
CPU time 0.73 seconds
Started Jul 01 10:51:33 AM PDT 24
Finished Jul 01 10:51:34 AM PDT 24
Peak memory 196384 kb
Host smart-ccdd02d0-c944-491f-9b9b-3b8c0bf1e19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854111978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3854111978
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3603529325
Short name T122
Test name
Test status
Simulation time 629732228498 ps
CPU time 461.05 seconds
Started Jul 01 10:51:12 AM PDT 24
Finished Jul 01 10:58:53 AM PDT 24
Peak memory 191864 kb
Host smart-9142e4a2-8266-4310-82fe-15fa28787d20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603529325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3603529325
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3490934489
Short name T146
Test name
Test status
Simulation time 214095509642 ps
CPU time 266.09 seconds
Started Jul 01 10:51:26 AM PDT 24
Finished Jul 01 10:55:53 AM PDT 24
Peak memory 191628 kb
Host smart-fe455f68-efb1-41e2-839c-0ae98ab24d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490934489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3490934489
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2444789715
Short name T119
Test name
Test status
Simulation time 25872479728 ps
CPU time 150.66 seconds
Started Jul 01 10:51:37 AM PDT 24
Finished Jul 01 10:54:08 AM PDT 24
Peak memory 206512 kb
Host smart-06c34655-db5d-4ca0-b5d7-4597a14c5c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444789715 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2444789715
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2080941788
Short name T31
Test name
Test status
Simulation time 520578471 ps
CPU time 1.33 seconds
Started Jul 01 10:51:33 AM PDT 24
Finished Jul 01 10:51:35 AM PDT 24
Peak memory 196748 kb
Host smart-014d8b3b-5e73-401d-b57e-fd21122494a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080941788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2080941788
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1526363920
Short name T32
Test name
Test status
Simulation time 524468097 ps
CPU time 1.43 seconds
Started Jul 01 10:51:38 AM PDT 24
Finished Jul 01 10:51:40 AM PDT 24
Peak memory 196384 kb
Host smart-f45ab1a2-d368-4e03-bcaf-6d3f0fefacc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526363920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1526363920
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1138048914
Short name T85
Test name
Test status
Simulation time 77485650544 ps
CPU time 216.62 seconds
Started Jul 01 10:51:41 AM PDT 24
Finished Jul 01 10:55:18 AM PDT 24
Peak memory 214036 kb
Host smart-489f9c44-944c-4211-a5e2-86d8909db562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138048914 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1138048914
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2243062634
Short name T97
Test name
Test status
Simulation time 531638637 ps
CPU time 1.17 seconds
Started Jul 01 10:51:56 AM PDT 24
Finished Jul 01 10:51:58 AM PDT 24
Peak memory 196460 kb
Host smart-79323e6e-1d76-4616-a45b-7835a0628258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243062634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2243062634
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2674979912
Short name T106
Test name
Test status
Simulation time 453064153 ps
CPU time 0.77 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:51:52 AM PDT 24
Peak memory 196496 kb
Host smart-a3fabc6b-723c-49b3-860f-bf740401db15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674979912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2674979912
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3640282449
Short name T115
Test name
Test status
Simulation time 409364342 ps
CPU time 0.78 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:51:53 AM PDT 24
Peak memory 196408 kb
Host smart-1c76bb9d-f12f-425c-9778-8798b8fe5115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640282449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3640282449
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1343912884
Short name T111
Test name
Test status
Simulation time 402592295 ps
CPU time 0.84 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 196448 kb
Host smart-50dde24a-68cc-4b07-b976-f7ff66a6ab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343912884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1343912884
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.759337766
Short name T157
Test name
Test status
Simulation time 66081571509 ps
CPU time 41.46 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:52:35 AM PDT 24
Peak memory 192652 kb
Host smart-1df9db87-809e-4174-a620-6026e0b82eae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759337766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.759337766
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2348793461
Short name T133
Test name
Test status
Simulation time 181750864629 ps
CPU time 280.28 seconds
Started Jul 01 10:51:55 AM PDT 24
Finished Jul 01 10:56:36 AM PDT 24
Peak memory 201144 kb
Host smart-a19f6cc4-48dd-4e9e-a2ed-34ef2e571d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348793461 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2348793461
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.28666857
Short name T143
Test name
Test status
Simulation time 480285706 ps
CPU time 0.78 seconds
Started Jul 01 10:52:01 AM PDT 24
Finished Jul 01 10:52:05 AM PDT 24
Peak memory 196388 kb
Host smart-6d694e65-5769-45ca-9d77-7d17a53b18ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28666857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.28666857
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1225606239
Short name T33
Test name
Test status
Simulation time 239372106965 ps
CPU time 378.38 seconds
Started Jul 01 10:51:55 AM PDT 24
Finished Jul 01 10:58:15 AM PDT 24
Peak memory 192560 kb
Host smart-3a012498-fcd2-42c6-9fa0-98fd2feeab62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225606239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1225606239
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1592285572
Short name T162
Test name
Test status
Simulation time 81972686531 ps
CPU time 27.99 seconds
Started Jul 01 10:51:08 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 192520 kb
Host smart-360fe0c1-7896-4087-8dc6-9221adeef536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592285572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1592285572
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3833310257
Short name T125
Test name
Test status
Simulation time 343637348 ps
CPU time 0.88 seconds
Started Jul 01 10:51:31 AM PDT 24
Finished Jul 01 10:51:32 AM PDT 24
Peak memory 196360 kb
Host smart-9c303228-6a33-4c6e-89f1-7ff77ff92285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833310257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3833310257
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.774309899
Short name T109
Test name
Test status
Simulation time 403661318 ps
CPU time 0.89 seconds
Started Jul 01 10:51:19 AM PDT 24
Finished Jul 01 10:51:21 AM PDT 24
Peak memory 196328 kb
Host smart-4458762f-1133-48d7-930a-f2770f1f156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774309899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.774309899
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.778010557
Short name T26
Test name
Test status
Simulation time 36081765776 ps
CPU time 251.02 seconds
Started Jul 01 10:51:43 AM PDT 24
Finished Jul 01 10:55:55 AM PDT 24
Peak memory 198392 kb
Host smart-c2b01517-ca8e-4f47-a06f-892a6b363a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778010557 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.778010557
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1192431226
Short name T155
Test name
Test status
Simulation time 21344739707 ps
CPU time 157.43 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:54:28 AM PDT 24
Peak memory 206564 kb
Host smart-63ca16ca-1a51-4d6a-912a-a8d329c93cfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192431226 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1192431226
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.905515569
Short name T153
Test name
Test status
Simulation time 471107523 ps
CPU time 0.97 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 196460 kb
Host smart-7db91363-0562-4e6a-b7ba-5afe406a76da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905515569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.905515569
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.308085204
Short name T139
Test name
Test status
Simulation time 185243170870 ps
CPU time 38.73 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:52:30 AM PDT 24
Peak memory 191580 kb
Host smart-d3381096-bcd4-4fee-b339-82db04e44308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308085204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.308085204
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1820431930
Short name T156
Test name
Test status
Simulation time 375218835 ps
CPU time 1.13 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:51:52 AM PDT 24
Peak memory 196348 kb
Host smart-2eaf59b8-da95-4921-8e8d-2ce1021dbdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820431930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1820431930
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2388758120
Short name T104
Test name
Test status
Simulation time 430644490 ps
CPU time 1.2 seconds
Started Jul 01 10:51:59 AM PDT 24
Finished Jul 01 10:52:01 AM PDT 24
Peak memory 196536 kb
Host smart-ca8917b2-4130-479c-98c0-b1a7965fe4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388758120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2388758120
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2165131678
Short name T147
Test name
Test status
Simulation time 480156532 ps
CPU time 0.78 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:02 AM PDT 24
Peak memory 196464 kb
Host smart-63463ae3-2fb1-458a-b5ee-749fc31c1260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165131678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2165131678
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2765602523
Short name T154
Test name
Test status
Simulation time 592246741 ps
CPU time 0.83 seconds
Started Jul 01 10:51:34 AM PDT 24
Finished Jul 01 10:51:35 AM PDT 24
Peak memory 196340 kb
Host smart-022ce9a7-c50e-4442-8633-104d147638a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765602523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2765602523
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3621604698
Short name T107
Test name
Test status
Simulation time 582339185 ps
CPU time 0.78 seconds
Started Jul 01 10:51:15 AM PDT 24
Finished Jul 01 10:51:16 AM PDT 24
Peak memory 196476 kb
Host smart-e661d788-85ea-4435-abd8-a94f57ce0cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621604698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3621604698
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1952579328
Short name T55
Test name
Test status
Simulation time 531978727 ps
CPU time 1.43 seconds
Started Jul 01 10:51:16 AM PDT 24
Finished Jul 01 10:51:18 AM PDT 24
Peak memory 196384 kb
Host smart-1423c3b7-aa1e-43c4-ac56-37f37d55605f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952579328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1952579328
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3277229667
Short name T105
Test name
Test status
Simulation time 280764332974 ps
CPU time 132.98 seconds
Started Jul 01 10:51:30 AM PDT 24
Finished Jul 01 10:53:44 AM PDT 24
Peak memory 197992 kb
Host smart-eedfc5c3-591f-452d-ae40-ee72b5e947a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277229667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3277229667
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2250681962
Short name T148
Test name
Test status
Simulation time 403282144 ps
CPU time 1.11 seconds
Started Jul 01 10:51:41 AM PDT 24
Finished Jul 01 10:51:43 AM PDT 24
Peak memory 196416 kb
Host smart-4c5f329e-1121-4211-8664-f4fa9de53a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250681962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2250681962
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2580504081
Short name T110
Test name
Test status
Simulation time 569729921466 ps
CPU time 215.11 seconds
Started Jul 01 10:51:09 AM PDT 24
Finished Jul 01 10:54:46 AM PDT 24
Peak memory 192664 kb
Host smart-558a4316-be47-4bf8-825b-220699812b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580504081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2580504081
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2807615843
Short name T41
Test name
Test status
Simulation time 94109870580 ps
CPU time 191.02 seconds
Started Jul 01 10:51:01 AM PDT 24
Finished Jul 01 10:54:13 AM PDT 24
Peak memory 199940 kb
Host smart-dd2dc5c1-3679-43a2-ad9a-34b6f210fe45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807615843 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2807615843
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.4174034479
Short name T128
Test name
Test status
Simulation time 557253198 ps
CPU time 0.75 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:02 AM PDT 24
Peak memory 196380 kb
Host smart-e27faef8-4aad-46ab-94ba-5e32d81e5bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174034479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.4174034479
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2913410951
Short name T170
Test name
Test status
Simulation time 30763236250 ps
CPU time 65.21 seconds
Started Jul 01 10:51:09 AM PDT 24
Finished Jul 01 10:52:16 AM PDT 24
Peak memory 214036 kb
Host smart-efc3efc2-f286-41cd-9828-d866dd8816da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913410951 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2913410951
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3754380287
Short name T163
Test name
Test status
Simulation time 48439676650 ps
CPU time 261.47 seconds
Started Jul 01 10:51:38 AM PDT 24
Finished Jul 01 10:56:00 AM PDT 24
Peak memory 198616 kb
Host smart-123b9340-067c-4bf0-b8c9-051a1efb53f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754380287 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3754380287
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1593278286
Short name T2
Test name
Test status
Simulation time 371143056 ps
CPU time 0.69 seconds
Started Jul 01 10:51:42 AM PDT 24
Finished Jul 01 10:51:44 AM PDT 24
Peak memory 196304 kb
Host smart-c96c5ac0-aaf3-465f-a58d-60db6229e51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593278286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1593278286
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2766115744
Short name T117
Test name
Test status
Simulation time 471883263 ps
CPU time 0.8 seconds
Started Jul 01 10:51:38 AM PDT 24
Finished Jul 01 10:51:40 AM PDT 24
Peak memory 196388 kb
Host smart-3b5b13ea-97cf-4ea5-bd09-62f381a3d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766115744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2766115744
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.110901876
Short name T89
Test name
Test status
Simulation time 173612559568 ps
CPU time 154.23 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:54:26 AM PDT 24
Peak memory 199680 kb
Host smart-22172f4f-bac6-4ea3-9fb6-c35d810feb16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110901876 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.110901876
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.553620061
Short name T151
Test name
Test status
Simulation time 548171761 ps
CPU time 0.8 seconds
Started Jul 01 10:51:57 AM PDT 24
Finished Jul 01 10:51:58 AM PDT 24
Peak memory 196500 kb
Host smart-1a772ce1-4e02-43ad-8461-6727ad1bd91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553620061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.553620061
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3670226497
Short name T135
Test name
Test status
Simulation time 390144878 ps
CPU time 0.75 seconds
Started Jul 01 10:51:57 AM PDT 24
Finished Jul 01 10:51:58 AM PDT 24
Peak memory 196428 kb
Host smart-1f395a62-aac5-47ef-b101-583bef428580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670226497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3670226497
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1986270091
Short name T149
Test name
Test status
Simulation time 457282556 ps
CPU time 0.95 seconds
Started Jul 01 10:51:08 AM PDT 24
Finished Jul 01 10:51:10 AM PDT 24
Peak memory 196292 kb
Host smart-d9e12b67-f0d0-46ea-94e4-ae25e1f3fe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986270091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1986270091
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2055940006
Short name T58
Test name
Test status
Simulation time 601261855 ps
CPU time 0.82 seconds
Started Jul 01 10:51:09 AM PDT 24
Finished Jul 01 10:51:11 AM PDT 24
Peak memory 196328 kb
Host smart-68a1ec00-6901-479d-8d6d-6a42965f7b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055940006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2055940006
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3475188450
Short name T173
Test name
Test status
Simulation time 610964054 ps
CPU time 0.77 seconds
Started Jul 01 10:51:32 AM PDT 24
Finished Jul 01 10:51:33 AM PDT 24
Peak memory 196460 kb
Host smart-925324bc-40f9-4dc6-bfca-699c96b54802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475188450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3475188450
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4146112720
Short name T136
Test name
Test status
Simulation time 573648242 ps
CPU time 1.46 seconds
Started Jul 01 10:51:47 AM PDT 24
Finished Jul 01 10:51:49 AM PDT 24
Peak memory 196396 kb
Host smart-85767f74-838f-45db-92a0-cbb89d533a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146112720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4146112720
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3973103278
Short name T186
Test name
Test status
Simulation time 202869676455 ps
CPU time 256.83 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:56:06 AM PDT 24
Peak memory 197936 kb
Host smart-c4072736-6b33-4fe7-b4aa-eee8b8fc6316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973103278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3973103278
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2004204685
Short name T27
Test name
Test status
Simulation time 398549976 ps
CPU time 1.17 seconds
Started Jul 01 10:51:40 AM PDT 24
Finished Jul 01 10:51:42 AM PDT 24
Peak memory 196384 kb
Host smart-f606d44b-eb6e-4b1e-aa19-21e11da1c6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004204685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2004204685
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.577271838
Short name T179
Test name
Test status
Simulation time 567367887 ps
CPU time 1.45 seconds
Started Jul 01 10:51:07 AM PDT 24
Finished Jul 01 10:51:09 AM PDT 24
Peak memory 196404 kb
Host smart-d0f9c4a4-e245-48a0-91e4-2f1b7aeb0746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577271838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.577271838
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.343659418
Short name T161
Test name
Test status
Simulation time 74658929819 ps
CPU time 48.45 seconds
Started Jul 01 10:51:12 AM PDT 24
Finished Jul 01 10:52:01 AM PDT 24
Peak memory 192688 kb
Host smart-f4a38b75-e3a4-498a-a535-4470d2fbcb21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343659418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.343659418
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1499470038
Short name T178
Test name
Test status
Simulation time 319095255526 ps
CPU time 481.74 seconds
Started Jul 01 10:51:03 AM PDT 24
Finished Jul 01 10:59:05 AM PDT 24
Peak memory 191624 kb
Host smart-91cf3a93-c45b-40b4-8596-f4de2c253c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499470038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1499470038
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1935197691
Short name T189
Test name
Test status
Simulation time 26929334747 ps
CPU time 187.3 seconds
Started Jul 01 10:51:19 AM PDT 24
Finished Jul 01 10:54:27 AM PDT 24
Peak memory 206584 kb
Host smart-5034995e-f8a3-458c-9d62-2bf9adf8dde4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935197691 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1935197691
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2017007776
Short name T50
Test name
Test status
Simulation time 436284634 ps
CPU time 1.33 seconds
Started Jul 01 10:51:24 AM PDT 24
Finished Jul 01 10:51:26 AM PDT 24
Peak memory 196492 kb
Host smart-d4207e3d-7744-465f-beea-996fef429149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017007776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2017007776
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.4115260568
Short name T92
Test name
Test status
Simulation time 102277558974 ps
CPU time 371.24 seconds
Started Jul 01 10:51:24 AM PDT 24
Finished Jul 01 10:57:36 AM PDT 24
Peak memory 206596 kb
Host smart-880c4e6c-9e81-4aa3-a540-c3e0cdcb7c8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115260568 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.4115260568
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4247190994
Short name T172
Test name
Test status
Simulation time 415096662 ps
CPU time 0.73 seconds
Started Jul 01 10:51:08 AM PDT 24
Finished Jul 01 10:51:09 AM PDT 24
Peak memory 196228 kb
Host smart-0b2f86bd-02d7-4b7f-9ed5-493003d5f20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247190994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4247190994
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1885497707
Short name T169
Test name
Test status
Simulation time 524212458 ps
CPU time 1.42 seconds
Started Jul 01 10:51:22 AM PDT 24
Finished Jul 01 10:51:24 AM PDT 24
Peak memory 196448 kb
Host smart-ce6c2e09-40f7-44dc-960f-046e7580f34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885497707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1885497707
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3656030131
Short name T174
Test name
Test status
Simulation time 501857701 ps
CPU time 1.29 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:51:52 AM PDT 24
Peak memory 196324 kb
Host smart-a017d03e-b97e-4175-883d-43d265a38a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656030131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3656030131
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.573883399
Short name T46
Test name
Test status
Simulation time 435787440 ps
CPU time 1.32 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:51:54 AM PDT 24
Peak memory 196408 kb
Host smart-f58216a1-acb0-4dc3-84ce-9f40eb931088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573883399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.573883399
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3827317046
Short name T188
Test name
Test status
Simulation time 436684913 ps
CPU time 1.24 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:51:54 AM PDT 24
Peak memory 196404 kb
Host smart-94e8b73b-6aca-4feb-bf56-3bfdd989be65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827317046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3827317046
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.4022124722
Short name T185
Test name
Test status
Simulation time 514785284 ps
CPU time 0.84 seconds
Started Jul 01 10:51:02 AM PDT 24
Finished Jul 01 10:51:04 AM PDT 24
Peak memory 196380 kb
Host smart-221188d6-0680-4efe-97dc-a8a20480469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022124722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.4022124722
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3843265778
Short name T144
Test name
Test status
Simulation time 447040441 ps
CPU time 0.77 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:04 AM PDT 24
Peak memory 196392 kb
Host smart-c3d21c5e-39d7-41bf-a289-67e3bfc5cb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843265778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3843265778
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2126234407
Short name T180
Test name
Test status
Simulation time 502496805 ps
CPU time 0.7 seconds
Started Jul 01 10:51:56 AM PDT 24
Finished Jul 01 10:51:58 AM PDT 24
Peak memory 196392 kb
Host smart-6b6b54a1-ab3a-495e-8242-c060323b54b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126234407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2126234407
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3172606419
Short name T168
Test name
Test status
Simulation time 382768542 ps
CPU time 1.13 seconds
Started Jul 01 10:51:13 AM PDT 24
Finished Jul 01 10:51:15 AM PDT 24
Peak memory 196380 kb
Host smart-ba53a6e4-90c7-46cf-8e88-6bcd844726e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172606419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3172606419
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.412804250
Short name T410
Test name
Test status
Simulation time 8514809336 ps
CPU time 6.84 seconds
Started Jul 01 10:50:06 AM PDT 24
Finished Jul 01 10:50:14 AM PDT 24
Peak memory 198036 kb
Host smart-8469e73b-c489-4e53-a0b5-c32deb0cbe5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412804250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.412804250
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2333380284
Short name T192
Test name
Test status
Simulation time 8334126341 ps
CPU time 3.61 seconds
Started Jul 01 10:49:50 AM PDT 24
Finished Jul 01 10:49:54 AM PDT 24
Peak memory 198288 kb
Host smart-d88f4738-8eb1-409b-8fc2-2ac91792ea45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333380284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2333380284
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1927288717
Short name T183
Test name
Test status
Simulation time 611455078 ps
CPU time 0.76 seconds
Started Jul 01 10:51:45 AM PDT 24
Finished Jul 01 10:51:46 AM PDT 24
Peak memory 196400 kb
Host smart-c4c86fd2-aaac-463c-b93e-8d01638828b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927288717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1927288717
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.881430174
Short name T184
Test name
Test status
Simulation time 271860997521 ps
CPU time 412.86 seconds
Started Jul 01 10:51:42 AM PDT 24
Finished Jul 01 10:58:35 AM PDT 24
Peak memory 191576 kb
Host smart-d3c9debe-1890-4d61-8c9f-3fff76b19fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881430174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.881430174
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2499105633
Short name T166
Test name
Test status
Simulation time 467448737 ps
CPU time 0.72 seconds
Started Jul 01 10:51:43 AM PDT 24
Finished Jul 01 10:51:44 AM PDT 24
Peak memory 196408 kb
Host smart-f746b6b5-ed80-4214-9bb9-0585d60dd2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499105633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2499105633
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.767224425
Short name T171
Test name
Test status
Simulation time 437817647 ps
CPU time 0.91 seconds
Started Jul 01 10:51:54 AM PDT 24
Finished Jul 01 10:51:57 AM PDT 24
Peak memory 196292 kb
Host smart-4e70d18d-a9bd-4a99-9189-80bcc8462881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767224425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.767224425
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2660055423
Short name T187
Test name
Test status
Simulation time 594565899 ps
CPU time 0.77 seconds
Started Jul 01 10:51:15 AM PDT 24
Finished Jul 01 10:51:16 AM PDT 24
Peak memory 196544 kb
Host smart-d2d71ea6-2dbe-42e8-9747-cbdbbe780315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660055423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2660055423
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1989166989
Short name T164
Test name
Test status
Simulation time 426331775 ps
CPU time 0.7 seconds
Started Jul 01 10:51:45 AM PDT 24
Finished Jul 01 10:51:46 AM PDT 24
Peak memory 196376 kb
Host smart-2f39d953-bb81-4be5-8e01-7761e58bbf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989166989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1989166989
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3799882517
Short name T182
Test name
Test status
Simulation time 587450271 ps
CPU time 0.78 seconds
Started Jul 01 10:51:59 AM PDT 24
Finished Jul 01 10:52:01 AM PDT 24
Peak memory 196456 kb
Host smart-20b675ee-1406-4c85-ad66-b89d03e2ed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799882517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3799882517
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2520045543
Short name T9
Test name
Test status
Simulation time 575849517 ps
CPU time 1.01 seconds
Started Jul 01 10:51:13 AM PDT 24
Finished Jul 01 10:51:14 AM PDT 24
Peak memory 196436 kb
Host smart-85c449a1-a0cf-4db2-bf95-d2dd0d8c54dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520045543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2520045543
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2631290627
Short name T359
Test name
Test status
Simulation time 14132227148 ps
CPU time 49.45 seconds
Started Jul 01 10:49:49 AM PDT 24
Finished Jul 01 10:50:40 AM PDT 24
Peak memory 196464 kb
Host smart-9e4e37df-87f8-49fc-9b81-bed02583c501
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631290627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2631290627
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.102713693
Short name T59
Test name
Test status
Simulation time 863064988 ps
CPU time 1.97 seconds
Started Jul 01 10:49:31 AM PDT 24
Finished Jul 01 10:49:34 AM PDT 24
Peak memory 183776 kb
Host smart-6d3bf315-49a1-4760-a1d5-e15cb75e79d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102713693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.102713693
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.726906316
Short name T406
Test name
Test status
Simulation time 392856279 ps
CPU time 0.99 seconds
Started Jul 01 10:49:28 AM PDT 24
Finished Jul 01 10:49:30 AM PDT 24
Peak memory 196596 kb
Host smart-1420ce89-8d04-4dfc-ae44-573ab954173c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726906316 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.726906316
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1727751489
Short name T382
Test name
Test status
Simulation time 327946566 ps
CPU time 1.04 seconds
Started Jul 01 10:49:44 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 192020 kb
Host smart-15835a5d-eb91-4bab-9cb6-04864bbc4ea2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727751489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1727751489
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2299735217
Short name T285
Test name
Test status
Simulation time 459935985 ps
CPU time 1.09 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:49:38 AM PDT 24
Peak memory 183792 kb
Host smart-bf5d775c-8c43-4eb9-82c5-46dfe5045fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299735217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2299735217
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2068788258
Short name T277
Test name
Test status
Simulation time 434953605 ps
CPU time 0.68 seconds
Started Jul 01 10:49:54 AM PDT 24
Finished Jul 01 10:49:55 AM PDT 24
Peak memory 183716 kb
Host smart-4c09507f-b674-42df-beca-810e19413bd6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068788258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2068788258
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4203825185
Short name T293
Test name
Test status
Simulation time 380106977 ps
CPU time 1.1 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:49:48 AM PDT 24
Peak memory 183704 kb
Host smart-831fd728-2cfb-4185-80cb-e1e959f4a71a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203825185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.4203825185
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.443993476
Short name T371
Test name
Test status
Simulation time 1071091241 ps
CPU time 1.13 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 193432 kb
Host smart-b743c058-ee36-49ee-ae96-77dc6bbb27f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443993476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.443993476
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1772167742
Short name T335
Test name
Test status
Simulation time 458861304 ps
CPU time 2.05 seconds
Started Jul 01 10:49:31 AM PDT 24
Finished Jul 01 10:49:33 AM PDT 24
Peak memory 198640 kb
Host smart-b8a816d1-f6c8-4b6c-86cc-4f3be670ccc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772167742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1772167742
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.453409609
Short name T67
Test name
Test status
Simulation time 445728390 ps
CPU time 1.35 seconds
Started Jul 01 10:50:06 AM PDT 24
Finished Jul 01 10:50:07 AM PDT 24
Peak memory 193432 kb
Host smart-80ebed6a-c092-4034-a1f1-8e7cc26b32b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453409609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.453409609
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2535062197
Short name T344
Test name
Test status
Simulation time 7247526785 ps
CPU time 4.93 seconds
Started Jul 01 10:49:36 AM PDT 24
Finished Jul 01 10:49:42 AM PDT 24
Peak memory 192232 kb
Host smart-0adf9967-7cb3-48c5-b694-5c5720af48ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535062197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2535062197
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.560116346
Short name T64
Test name
Test status
Simulation time 1224499125 ps
CPU time 0.95 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:49:39 AM PDT 24
Peak memory 193164 kb
Host smart-c828f456-b222-495c-9309-5fc8c060bfcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560116346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.560116346
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.247101986
Short name T295
Test name
Test status
Simulation time 556211062 ps
CPU time 1.5 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:49:57 AM PDT 24
Peak memory 196200 kb
Host smart-83f0abd4-2155-4f09-ae15-6aff87423b9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247101986 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.247101986
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1033818867
Short name T337
Test name
Test status
Simulation time 372887095 ps
CPU time 0.8 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:49:39 AM PDT 24
Peak memory 183796 kb
Host smart-a387421b-dfb2-4eb4-a19f-576cc0b89e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033818867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1033818867
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3040221649
Short name T400
Test name
Test status
Simulation time 405908740 ps
CPU time 1.06 seconds
Started Jul 01 10:49:58 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 183732 kb
Host smart-50068e6f-b173-40c7-b162-fa6c306758be
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040221649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3040221649
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2444501561
Short name T351
Test name
Test status
Simulation time 431853107 ps
CPU time 0.64 seconds
Started Jul 01 10:50:06 AM PDT 24
Finished Jul 01 10:50:08 AM PDT 24
Peak memory 183588 kb
Host smart-60ddd262-b2a7-4f1f-9c9c-7f76ca10c3e0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444501561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2444501561
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2682745094
Short name T398
Test name
Test status
Simulation time 1258162016 ps
CPU time 2.39 seconds
Started Jul 01 10:50:05 AM PDT 24
Finished Jul 01 10:50:08 AM PDT 24
Peak memory 193756 kb
Host smart-b9b7a8e6-3b4a-4eec-a660-b80b872999d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682745094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2682745094
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.557378158
Short name T303
Test name
Test status
Simulation time 809938088 ps
CPU time 2.8 seconds
Started Jul 01 10:49:47 AM PDT 24
Finished Jul 01 10:49:51 AM PDT 24
Peak memory 198608 kb
Host smart-397cd226-e7c1-4e48-9786-c63ad7b7ea5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557378158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.557378158
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1593975012
Short name T348
Test name
Test status
Simulation time 8686700643 ps
CPU time 6.63 seconds
Started Jul 01 10:49:29 AM PDT 24
Finished Jul 01 10:49:36 AM PDT 24
Peak memory 198184 kb
Host smart-bedecd76-c1f6-4ae5-a03b-034df10dec06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593975012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1593975012
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1566734998
Short name T369
Test name
Test status
Simulation time 417037321 ps
CPU time 0.96 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 196804 kb
Host smart-1abbb1f4-1cfa-4c08-9519-e005244af139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566734998 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1566734998
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2426565548
Short name T332
Test name
Test status
Simulation time 330581004 ps
CPU time 1.04 seconds
Started Jul 01 10:49:44 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 192960 kb
Host smart-2c4b827b-7476-482d-ad03-7f1f539af54f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426565548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2426565548
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3212868486
Short name T297
Test name
Test status
Simulation time 361423423 ps
CPU time 0.69 seconds
Started Jul 01 10:49:44 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 183804 kb
Host smart-c99c418a-40fa-466a-829f-cb2ee97cf344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212868486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3212868486
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3415083560
Short name T74
Test name
Test status
Simulation time 1978702780 ps
CPU time 2.05 seconds
Started Jul 01 10:50:06 AM PDT 24
Finished Jul 01 10:50:10 AM PDT 24
Peak memory 193072 kb
Host smart-b0c5dd77-e146-4222-a585-ebb5c6e8d022
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415083560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3415083560
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.81970090
Short name T315
Test name
Test status
Simulation time 478288461 ps
CPU time 1.99 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:45 AM PDT 24
Peak memory 198640 kb
Host smart-0d3b387e-a193-4f82-bfb7-9d1995a97c71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81970090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.81970090
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3465347277
Short name T379
Test name
Test status
Simulation time 4333750599 ps
CPU time 2.79 seconds
Started Jul 01 10:50:06 AM PDT 24
Finished Jul 01 10:50:11 AM PDT 24
Peak memory 197892 kb
Host smart-81051dc3-6cfc-4651-bc08-969d03804615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465347277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3465347277
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.551342682
Short name T389
Test name
Test status
Simulation time 520597251 ps
CPU time 0.97 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:49:49 AM PDT 24
Peak memory 196476 kb
Host smart-8d54566f-1d0d-4386-b963-f15ed9f79d76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551342682 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.551342682
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2078017496
Short name T349
Test name
Test status
Simulation time 365845285 ps
CPU time 1.06 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:49:48 AM PDT 24
Peak memory 191972 kb
Host smart-43646642-8190-40f0-a11a-0736ce5d4c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078017496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2078017496
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1060602193
Short name T307
Test name
Test status
Simulation time 434547575 ps
CPU time 1.19 seconds
Started Jul 01 10:49:42 AM PDT 24
Finished Jul 01 10:49:44 AM PDT 24
Peak memory 193032 kb
Host smart-68b04e4e-d1c1-42a8-972a-4b1ea9c4e903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060602193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1060602193
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3965067389
Short name T370
Test name
Test status
Simulation time 1182640796 ps
CPU time 3.14 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 193004 kb
Host smart-dfd3f5d3-f7d3-49e2-a419-5a5ff6d1179e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965067389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3965067389
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2543004472
Short name T288
Test name
Test status
Simulation time 815729452 ps
CPU time 1.8 seconds
Started Jul 01 10:50:07 AM PDT 24
Finished Jul 01 10:50:10 AM PDT 24
Peak memory 198616 kb
Host smart-a45e01a8-407e-4eab-9979-6712450a55a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543004472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2543004472
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2087220408
Short name T408
Test name
Test status
Simulation time 615456536 ps
CPU time 1.04 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:14 AM PDT 24
Peak memory 196924 kb
Host smart-f9d78f62-dea7-4631-a361-7450902484ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087220408 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2087220408
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2967460109
Short name T381
Test name
Test status
Simulation time 374938868 ps
CPU time 1.14 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:12 AM PDT 24
Peak memory 193392 kb
Host smart-b3396713-07e5-45cb-a809-38cb82602a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967460109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2967460109
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2917341124
Short name T396
Test name
Test status
Simulation time 341966402 ps
CPU time 1.03 seconds
Started Jul 01 10:50:06 AM PDT 24
Finished Jul 01 10:50:08 AM PDT 24
Peak memory 192896 kb
Host smart-5fc3aecf-84d3-4a46-a46d-270e8a90ac26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917341124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2917341124
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.120261098
Short name T353
Test name
Test status
Simulation time 2242146127 ps
CPU time 3.99 seconds
Started Jul 01 10:49:51 AM PDT 24
Finished Jul 01 10:49:55 AM PDT 24
Peak memory 192036 kb
Host smart-3afcdf3e-2117-45fc-a928-c023a218c78a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120261098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.120261098
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4086100667
Short name T331
Test name
Test status
Simulation time 910008174 ps
CPU time 2.26 seconds
Started Jul 01 10:49:51 AM PDT 24
Finished Jul 01 10:49:54 AM PDT 24
Peak memory 198612 kb
Host smart-3b32d93e-952c-4bdb-9627-034af074b2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086100667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4086100667
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3452316900
Short name T191
Test name
Test status
Simulation time 9086766705 ps
CPU time 3.12 seconds
Started Jul 01 10:49:50 AM PDT 24
Finished Jul 01 10:49:54 AM PDT 24
Peak memory 198060 kb
Host smart-9cbea7b1-6612-4852-b31b-4be386de7f53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452316900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3452316900
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2055900515
Short name T346
Test name
Test status
Simulation time 603547521 ps
CPU time 1.02 seconds
Started Jul 01 10:49:48 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 198156 kb
Host smart-806e5ec1-48e9-4cfe-9d96-c8ed967dc816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055900515 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2055900515
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2756685879
Short name T70
Test name
Test status
Simulation time 406622566 ps
CPU time 1.21 seconds
Started Jul 01 10:49:48 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 193988 kb
Host smart-73002b8b-b037-4e4a-b738-dbd8f54e76cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756685879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2756685879
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3737100171
Short name T311
Test name
Test status
Simulation time 507977604 ps
CPU time 0.89 seconds
Started Jul 01 10:49:51 AM PDT 24
Finished Jul 01 10:49:52 AM PDT 24
Peak memory 183812 kb
Host smart-10dd5413-5893-4485-8d2f-9d85d33afbdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737100171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3737100171
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3482784144
Short name T377
Test name
Test status
Simulation time 1333232008 ps
CPU time 2.32 seconds
Started Jul 01 10:50:10 AM PDT 24
Finished Jul 01 10:50:15 AM PDT 24
Peak memory 193596 kb
Host smart-fcebb97c-6646-4e10-a2bd-51a80ffd1d69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482784144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3482784144
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4137267820
Short name T294
Test name
Test status
Simulation time 320005802 ps
CPU time 1.79 seconds
Started Jul 01 10:50:03 AM PDT 24
Finished Jul 01 10:50:05 AM PDT 24
Peak memory 198360 kb
Host smart-9020cc75-9f86-4f53-8207-32de50f37250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137267820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.4137267820
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2897427699
Short name T35
Test name
Test status
Simulation time 7942440804 ps
CPU time 6.85 seconds
Started Jul 01 10:50:16 AM PDT 24
Finished Jul 01 10:50:25 AM PDT 24
Peak memory 198284 kb
Host smart-aff1e6d5-f354-4dc5-9a6f-1048400b4455
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897427699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2897427699
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2257181877
Short name T412
Test name
Test status
Simulation time 764073597 ps
CPU time 0.81 seconds
Started Jul 01 10:50:04 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 197576 kb
Host smart-38e3a555-07cc-4d8f-a17e-9e7cbd552fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257181877 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2257181877
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1017624979
Short name T355
Test name
Test status
Simulation time 344929740 ps
CPU time 1.18 seconds
Started Jul 01 10:50:10 AM PDT 24
Finished Jul 01 10:50:14 AM PDT 24
Peak memory 192032 kb
Host smart-d9d86a8e-2103-4b08-9f9d-d6a77312d926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017624979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1017624979
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1815483825
Short name T394
Test name
Test status
Simulation time 446861883 ps
CPU time 1.19 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:15 AM PDT 24
Peak memory 192892 kb
Host smart-e7c386fd-2a7b-48dd-9878-c26c06d86bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815483825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1815483825
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1920843658
Short name T385
Test name
Test status
Simulation time 2430698885 ps
CPU time 1.05 seconds
Started Jul 01 10:49:52 AM PDT 24
Finished Jul 01 10:49:53 AM PDT 24
Peak memory 195188 kb
Host smart-6561b1c4-32f7-4360-bc06-40226642654c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920843658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1920843658
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2769480684
Short name T414
Test name
Test status
Simulation time 966582658 ps
CPU time 2.31 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:11 AM PDT 24
Peak memory 198588 kb
Host smart-0be33471-cf4b-4e1e-a7c4-452bf42a9cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769480684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2769480684
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.437407794
Short name T393
Test name
Test status
Simulation time 386755107 ps
CPU time 0.96 seconds
Started Jul 01 10:49:48 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 196100 kb
Host smart-fa82f3b3-47d0-4a8c-bbfd-e19050790177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437407794 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.437407794
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1708594748
Short name T77
Test name
Test status
Simulation time 420461483 ps
CPU time 0.91 seconds
Started Jul 01 10:49:51 AM PDT 24
Finished Jul 01 10:49:53 AM PDT 24
Peak memory 193996 kb
Host smart-32e9b2b5-ae1e-4f9e-ab65-4a1962728fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708594748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1708594748
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.657734560
Short name T392
Test name
Test status
Simulation time 269995806 ps
CPU time 0.99 seconds
Started Jul 01 10:49:52 AM PDT 24
Finished Jul 01 10:49:54 AM PDT 24
Peak memory 183804 kb
Host smart-ac12afa8-77ae-4e6d-b037-8dd935eb7bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657734560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.657734560
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.610141552
Short name T80
Test name
Test status
Simulation time 2577042776 ps
CPU time 1.03 seconds
Started Jul 01 10:49:48 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 194732 kb
Host smart-cf445805-5b46-42bd-a3e4-2dd1e58aeb04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610141552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.610141552
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2356266982
Short name T286
Test name
Test status
Simulation time 464618950 ps
CPU time 2.56 seconds
Started Jul 01 10:49:52 AM PDT 24
Finished Jul 01 10:49:55 AM PDT 24
Peak memory 198616 kb
Host smart-0fea9ead-a6cb-4a07-8b32-63dcda9112e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356266982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2356266982
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2430284233
Short name T190
Test name
Test status
Simulation time 4659921236 ps
CPU time 7.7 seconds
Started Jul 01 10:49:47 AM PDT 24
Finished Jul 01 10:49:56 AM PDT 24
Peak memory 198088 kb
Host smart-c8feb7ed-56ab-46ef-8e19-dbdbc9157646
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430284233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2430284233
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3692977926
Short name T328
Test name
Test status
Simulation time 395499302 ps
CPU time 1.04 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:17 AM PDT 24
Peak memory 195432 kb
Host smart-56a07e71-71fd-439a-ba00-cdbd444aee08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692977926 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3692977926
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3306372459
Short name T63
Test name
Test status
Simulation time 424193430 ps
CPU time 1.2 seconds
Started Jul 01 10:50:16 AM PDT 24
Finished Jul 01 10:50:19 AM PDT 24
Peak memory 192036 kb
Host smart-e4e0da27-77d5-497f-887e-ebba927f9e9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306372459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3306372459
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2721081418
Short name T320
Test name
Test status
Simulation time 451982754 ps
CPU time 0.71 seconds
Started Jul 01 10:49:52 AM PDT 24
Finished Jul 01 10:49:53 AM PDT 24
Peak memory 183804 kb
Host smart-1bda750b-ee26-4b4f-9db0-c675ca3a8a92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721081418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2721081418
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4240848412
Short name T82
Test name
Test status
Simulation time 1532363682 ps
CPU time 2.54 seconds
Started Jul 01 10:49:52 AM PDT 24
Finished Jul 01 10:49:55 AM PDT 24
Peak memory 193484 kb
Host smart-e491da99-289b-474e-9c48-8e1485ff6863
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240848412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.4240848412
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1495388374
Short name T306
Test name
Test status
Simulation time 553338528 ps
CPU time 1.37 seconds
Started Jul 01 10:49:51 AM PDT 24
Finished Jul 01 10:49:53 AM PDT 24
Peak memory 198672 kb
Host smart-4ebb131f-5235-4944-a0b6-940113fdf5a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495388374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1495388374
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2661941702
Short name T366
Test name
Test status
Simulation time 7972045569 ps
CPU time 12.67 seconds
Started Jul 01 10:50:07 AM PDT 24
Finished Jul 01 10:50:24 AM PDT 24
Peak memory 198144 kb
Host smart-85310287-877c-447f-96e6-218a4c8e137e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661941702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2661941702
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.747616149
Short name T391
Test name
Test status
Simulation time 446278576 ps
CPU time 0.86 seconds
Started Jul 01 10:50:07 AM PDT 24
Finished Jul 01 10:50:09 AM PDT 24
Peak memory 196192 kb
Host smart-87c53cd3-a588-44e1-ac23-78b727acd47e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747616149 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.747616149
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.646707723
Short name T65
Test name
Test status
Simulation time 387205300 ps
CPU time 0.72 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:13 AM PDT 24
Peak memory 193168 kb
Host smart-6f6a7ff7-6035-4edb-8e6f-fc5b360890cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646707723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.646707723
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1627407350
Short name T322
Test name
Test status
Simulation time 447911643 ps
CPU time 0.84 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:10 AM PDT 24
Peak memory 183764 kb
Host smart-9a1eeedd-a8fc-4814-a658-beb76f90c4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627407350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1627407350
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1429945035
Short name T36
Test name
Test status
Simulation time 2596667728 ps
CPU time 2.36 seconds
Started Jul 01 10:49:51 AM PDT 24
Finished Jul 01 10:49:54 AM PDT 24
Peak memory 195176 kb
Host smart-37997027-a7b5-4c41-bec8-0fb4f967e7b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429945035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1429945035
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2674102717
Short name T323
Test name
Test status
Simulation time 549704042 ps
CPU time 2.13 seconds
Started Jul 01 10:49:51 AM PDT 24
Finished Jul 01 10:49:54 AM PDT 24
Peak memory 198592 kb
Host smart-8c8feffe-402c-4760-a5af-d5f8cfcb5c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674102717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2674102717
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3508759380
Short name T416
Test name
Test status
Simulation time 4383772653 ps
CPU time 7.88 seconds
Started Jul 01 10:49:48 AM PDT 24
Finished Jul 01 10:49:57 AM PDT 24
Peak memory 197800 kb
Host smart-97f6d3eb-7835-4071-b02f-b0f7f397fae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508759380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3508759380
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3598128930
Short name T339
Test name
Test status
Simulation time 383330323 ps
CPU time 1.21 seconds
Started Jul 01 10:50:07 AM PDT 24
Finished Jul 01 10:50:09 AM PDT 24
Peak memory 195924 kb
Host smart-0978bb56-f54a-4eaa-8e51-8e336785a288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598128930 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3598128930
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3735543330
Short name T350
Test name
Test status
Simulation time 358687658 ps
CPU time 0.81 seconds
Started Jul 01 10:49:54 AM PDT 24
Finished Jul 01 10:49:56 AM PDT 24
Peak memory 192044 kb
Host smart-e9a26c26-cfe3-4c30-9e98-fab6fc64550c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735543330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3735543330
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.175438025
Short name T336
Test name
Test status
Simulation time 439409071 ps
CPU time 1.13 seconds
Started Jul 01 10:49:58 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 183804 kb
Host smart-4384acd7-9309-4bf4-9365-c722ce4e6ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175438025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.175438025
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.19439230
Short name T403
Test name
Test status
Simulation time 1558468957 ps
CPU time 3.6 seconds
Started Jul 01 10:50:11 AM PDT 24
Finished Jul 01 10:50:18 AM PDT 24
Peak memory 193000 kb
Host smart-d9863314-750e-4bfa-a85c-7b55237ed627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19439230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_
timer_same_csr_outstanding.19439230
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.57769557
Short name T340
Test name
Test status
Simulation time 351509377 ps
CPU time 1.49 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:49:57 AM PDT 24
Peak memory 198572 kb
Host smart-4301edf4-a921-402b-be4d-1b4ac0063fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57769557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.57769557
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3716720156
Short name T358
Test name
Test status
Simulation time 4150201364 ps
CPU time 2.47 seconds
Started Jul 01 10:50:13 AM PDT 24
Finished Jul 01 10:50:18 AM PDT 24
Peak memory 197752 kb
Host smart-dda5570a-9d69-466e-a760-a52f40081409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716720156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3716720156
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.146461879
Short name T347
Test name
Test status
Simulation time 407306182 ps
CPU time 0.84 seconds
Started Jul 01 10:50:10 AM PDT 24
Finished Jul 01 10:50:14 AM PDT 24
Peak memory 196552 kb
Host smart-fbb97b11-2f22-4ee7-9cf8-2d57c0cf7cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146461879 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.146461879
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4073512646
Short name T367
Test name
Test status
Simulation time 294859189 ps
CPU time 1.03 seconds
Started Jul 01 10:49:58 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 193008 kb
Host smart-9301c087-1c28-4772-b76e-c0559b864e7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073512646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4073512646
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2186070795
Short name T362
Test name
Test status
Simulation time 407821999 ps
CPU time 1.13 seconds
Started Jul 01 10:49:57 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 183604 kb
Host smart-894b74bf-d22d-412f-9fae-7bf1414d644f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186070795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2186070795
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3733017051
Short name T79
Test name
Test status
Simulation time 2944069505 ps
CPU time 1.75 seconds
Started Jul 01 10:49:53 AM PDT 24
Finished Jul 01 10:49:55 AM PDT 24
Peak memory 194188 kb
Host smart-7cd0a56e-e81d-407c-95e0-47913c837965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733017051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3733017051
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1636621861
Short name T282
Test name
Test status
Simulation time 652019699 ps
CPU time 2.42 seconds
Started Jul 01 10:49:54 AM PDT 24
Finished Jul 01 10:49:56 AM PDT 24
Peak memory 198656 kb
Host smart-73eb139d-aade-4ccc-8c9b-6975216fc25e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636621861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1636621861
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1930115270
Short name T415
Test name
Test status
Simulation time 4287507243 ps
CPU time 2.19 seconds
Started Jul 01 10:49:57 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 197764 kb
Host smart-be72c03f-1b96-4a35-9ade-ff0dee3fdcce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930115270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1930115270
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.441847702
Short name T374
Test name
Test status
Simulation time 514820080 ps
CPU time 0.88 seconds
Started Jul 01 10:50:06 AM PDT 24
Finished Jul 01 10:50:09 AM PDT 24
Peak memory 183668 kb
Host smart-00331eb9-ce9c-43b1-90ed-c4d326f7bb22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441847702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.441847702
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.770862425
Short name T68
Test name
Test status
Simulation time 8883254485 ps
CPU time 22.82 seconds
Started Jul 01 10:49:53 AM PDT 24
Finished Jul 01 10:50:16 AM PDT 24
Peak memory 192240 kb
Host smart-ace724de-0058-4eae-a85a-f2598966ce9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770862425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.770862425
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.423102332
Short name T61
Test name
Test status
Simulation time 1398399119 ps
CPU time 2.69 seconds
Started Jul 01 10:49:32 AM PDT 24
Finished Jul 01 10:49:35 AM PDT 24
Peak memory 193072 kb
Host smart-8c0bd8f3-33d5-4f41-897f-edec46163269
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423102332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.423102332
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1095631901
Short name T196
Test name
Test status
Simulation time 480811635 ps
CPU time 0.78 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:49:39 AM PDT 24
Peak memory 196708 kb
Host smart-6880c5e0-55e7-418b-be53-b702e6bc6305
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095631901 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1095631901
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.777209685
Short name T62
Test name
Test status
Simulation time 565340238 ps
CPU time 0.88 seconds
Started Jul 01 10:50:07 AM PDT 24
Finished Jul 01 10:50:09 AM PDT 24
Peak memory 192968 kb
Host smart-faef2165-0960-49e5-970c-d9b08a949832
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777209685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.777209685
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4172164108
Short name T360
Test name
Test status
Simulation time 532579669 ps
CPU time 0.71 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:49:56 AM PDT 24
Peak memory 193016 kb
Host smart-0b9a6fbd-affd-4cd9-99af-e5441f17b75e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172164108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.4172164108
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3574934184
Short name T292
Test name
Test status
Simulation time 480438761 ps
CPU time 0.68 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:49:39 AM PDT 24
Peak memory 183736 kb
Host smart-f2558ddc-0664-4b0d-b8c5-ff1d72b09698
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574934184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3574934184
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.146278951
Short name T364
Test name
Test status
Simulation time 377661142 ps
CPU time 1.11 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:49:57 AM PDT 24
Peak memory 183712 kb
Host smart-4b413d39-719e-4281-9644-046ca9093636
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146278951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.146278951
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3049319226
Short name T373
Test name
Test status
Simulation time 2358200068 ps
CPU time 1.62 seconds
Started Jul 01 10:50:02 AM PDT 24
Finished Jul 01 10:50:04 AM PDT 24
Peak memory 194376 kb
Host smart-b414e671-fe22-4539-a493-bbbb63ead7cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049319226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3049319226
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.609509055
Short name T338
Test name
Test status
Simulation time 467941412 ps
CPU time 2.58 seconds
Started Jul 01 10:49:50 AM PDT 24
Finished Jul 01 10:49:54 AM PDT 24
Peak memory 198620 kb
Host smart-2359e970-d95d-4952-96a2-9e0a086434d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609509055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.609509055
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2915158040
Short name T325
Test name
Test status
Simulation time 4521622536 ps
CPU time 1.92 seconds
Started Jul 01 10:49:33 AM PDT 24
Finished Jul 01 10:49:35 AM PDT 24
Peak memory 197864 kb
Host smart-a7c266e0-f142-4b08-bbc9-305e40ce7c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915158040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2915158040
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.528773960
Short name T283
Test name
Test status
Simulation time 484660424 ps
CPU time 0.71 seconds
Started Jul 01 10:50:14 AM PDT 24
Finished Jul 01 10:50:17 AM PDT 24
Peak memory 193024 kb
Host smart-989f4216-5fe9-465b-a6cb-76d705224609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528773960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.528773960
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1648997624
Short name T361
Test name
Test status
Simulation time 525291209 ps
CPU time 0.87 seconds
Started Jul 01 10:49:58 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 183608 kb
Host smart-46fb09d9-a38c-4096-893c-e5e24c61b8a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648997624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1648997624
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2404054644
Short name T302
Test name
Test status
Simulation time 413226480 ps
CPU time 0.61 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:50:01 AM PDT 24
Peak memory 183768 kb
Host smart-7c32c89c-d1ba-4b43-ae6c-9829fe96438a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404054644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2404054644
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2528559261
Short name T279
Test name
Test status
Simulation time 306478369 ps
CPU time 0.92 seconds
Started Jul 01 10:50:10 AM PDT 24
Finished Jul 01 10:50:14 AM PDT 24
Peak memory 183792 kb
Host smart-3bb255bb-f20e-4b4f-a39f-d045b2c1cb11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528559261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2528559261
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2763479744
Short name T357
Test name
Test status
Simulation time 407590839 ps
CPU time 0.72 seconds
Started Jul 01 10:49:58 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 183804 kb
Host smart-16f8dbfb-15d5-4a10-9619-a22c5ee8c481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763479744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2763479744
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.540589541
Short name T319
Test name
Test status
Simulation time 460703577 ps
CPU time 1.13 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:50:01 AM PDT 24
Peak memory 183768 kb
Host smart-47e8a006-6b4f-408a-9d65-14b88df7e192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540589541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.540589541
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2041146227
Short name T387
Test name
Test status
Simulation time 414952470 ps
CPU time 0.81 seconds
Started Jul 01 10:49:58 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 183608 kb
Host smart-2b01b378-ca38-4028-8733-9edb4006a94c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041146227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2041146227
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.402887375
Short name T399
Test name
Test status
Simulation time 368763906 ps
CPU time 1.01 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:11 AM PDT 24
Peak memory 183792 kb
Host smart-d8aec9b7-65e4-4a9b-9e95-98f9bec67e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402887375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.402887375
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2349123371
Short name T317
Test name
Test status
Simulation time 293898234 ps
CPU time 0.68 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:49:56 AM PDT 24
Peak memory 183756 kb
Host smart-bc009e77-7fcc-450a-a2a8-b2a8b69b7926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349123371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2349123371
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.270393813
Short name T333
Test name
Test status
Simulation time 448496343 ps
CPU time 0.67 seconds
Started Jul 01 10:49:57 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 183780 kb
Host smart-f5ae01e7-84ae-4d34-8475-d421577abe0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270393813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.270393813
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2189973887
Short name T71
Test name
Test status
Simulation time 535957372 ps
CPU time 0.66 seconds
Started Jul 01 10:50:03 AM PDT 24
Finished Jul 01 10:50:04 AM PDT 24
Peak memory 193916 kb
Host smart-575ff8d2-fe25-4781-b9f8-37e5eb922607
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189973887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2189973887
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1860728099
Short name T376
Test name
Test status
Simulation time 7308776208 ps
CPU time 9.97 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:19 AM PDT 24
Peak memory 196212 kb
Host smart-261f2977-a039-40bd-89b5-4f350ed66b27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860728099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1860728099
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4276115733
Short name T368
Test name
Test status
Simulation time 721707594 ps
CPU time 1.31 seconds
Started Jul 01 10:49:51 AM PDT 24
Finished Jul 01 10:49:53 AM PDT 24
Peak memory 192028 kb
Host smart-2ef9d44c-06c4-4511-9006-e097e91abe0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276115733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4276115733
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3401028275
Short name T404
Test name
Test status
Simulation time 603526708 ps
CPU time 1.43 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:49:39 AM PDT 24
Peak memory 196532 kb
Host smart-74a97b03-32a0-4020-9b5e-b1c6a99e3c25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401028275 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3401028275
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.502466072
Short name T388
Test name
Test status
Simulation time 490083507 ps
CPU time 1.23 seconds
Started Jul 01 10:50:05 AM PDT 24
Finished Jul 01 10:50:07 AM PDT 24
Peak memory 193460 kb
Host smart-bd1e9538-8683-4ab3-9584-bb76792b4938
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502466072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.502466072
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.366527455
Short name T318
Test name
Test status
Simulation time 447415062 ps
CPU time 0.6 seconds
Started Jul 01 10:49:56 AM PDT 24
Finished Jul 01 10:49:57 AM PDT 24
Peak memory 183688 kb
Host smart-121d541a-5239-4e1b-9c5b-90fb57007c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366527455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.366527455
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.51411802
Short name T301
Test name
Test status
Simulation time 434147394 ps
CPU time 1.13 seconds
Started Jul 01 10:50:06 AM PDT 24
Finished Jul 01 10:50:09 AM PDT 24
Peak memory 183624 kb
Host smart-2bd3c8a3-1d19-48c2-8056-93b49e1d8231
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51411802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_mem_partial_access.51411802
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.980360705
Short name T280
Test name
Test status
Simulation time 395369544 ps
CPU time 0.94 seconds
Started Jul 01 10:49:34 AM PDT 24
Finished Jul 01 10:49:36 AM PDT 24
Peak memory 183728 kb
Host smart-e35e5a25-2c1c-491b-9928-d7d2c12537a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980360705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.980360705
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2380223813
Short name T81
Test name
Test status
Simulation time 1797440473 ps
CPU time 5.19 seconds
Started Jul 01 10:49:38 AM PDT 24
Finished Jul 01 10:49:44 AM PDT 24
Peak memory 194716 kb
Host smart-200a9c29-5a51-4d40-b64b-7a2656c6e71c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380223813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2380223813
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4055857861
Short name T287
Test name
Test status
Simulation time 347849988 ps
CPU time 1.84 seconds
Started Jul 01 10:49:32 AM PDT 24
Finished Jul 01 10:49:34 AM PDT 24
Peak memory 198392 kb
Host smart-51d9608d-e040-4d78-ab4d-9095d8358dfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055857861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4055857861
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.448232481
Short name T193
Test name
Test status
Simulation time 4763801629 ps
CPU time 2.42 seconds
Started Jul 01 10:49:48 AM PDT 24
Finished Jul 01 10:49:51 AM PDT 24
Peak memory 197800 kb
Host smart-950eab72-cbc0-4e0e-9989-0adc905881cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448232481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.448232481
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2586494756
Short name T372
Test name
Test status
Simulation time 315383257 ps
CPU time 0.63 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:50:01 AM PDT 24
Peak memory 183764 kb
Host smart-44a3d55c-b0a8-41b5-b860-d1251486bd04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586494756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2586494756
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3718416574
Short name T380
Test name
Test status
Simulation time 277259727 ps
CPU time 0.85 seconds
Started Jul 01 10:49:57 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 183608 kb
Host smart-b37f415f-3b58-4e65-9ffe-e41131788e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718416574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3718416574
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1949108327
Short name T316
Test name
Test status
Simulation time 391026567 ps
CPU time 0.79 seconds
Started Jul 01 10:50:00 AM PDT 24
Finished Jul 01 10:50:02 AM PDT 24
Peak memory 183816 kb
Host smart-a622dbc4-3f72-4c23-9bc2-f4ead858dd11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949108327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1949108327
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.4234587852
Short name T305
Test name
Test status
Simulation time 465837214 ps
CPU time 1.16 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:49:57 AM PDT 24
Peak memory 183756 kb
Host smart-c4c05972-128f-4378-994c-82acf0c4c583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234587852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.4234587852
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3575032656
Short name T278
Test name
Test status
Simulation time 368487016 ps
CPU time 0.67 seconds
Started Jul 01 10:49:58 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 183804 kb
Host smart-d5d88849-eca2-4a9b-83a7-366bd09e89ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575032656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3575032656
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4013818658
Short name T345
Test name
Test status
Simulation time 309386491 ps
CPU time 0.65 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:50:01 AM PDT 24
Peak memory 183768 kb
Host smart-7a197e59-da4b-4757-a419-5862d6a0366d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013818658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.4013818658
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1178742645
Short name T291
Test name
Test status
Simulation time 334008793 ps
CPU time 1.07 seconds
Started Jul 01 10:49:57 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 183804 kb
Host smart-1e927c8e-076c-4b36-b892-529b54fb5e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178742645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1178742645
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2479493455
Short name T310
Test name
Test status
Simulation time 326130820 ps
CPU time 1.02 seconds
Started Jul 01 10:50:10 AM PDT 24
Finished Jul 01 10:50:14 AM PDT 24
Peak memory 183788 kb
Host smart-a1f7397e-5e5c-4195-b66d-9020f17d94e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479493455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2479493455
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4106640608
Short name T365
Test name
Test status
Simulation time 514024878 ps
CPU time 1.15 seconds
Started Jul 01 10:50:04 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 183784 kb
Host smart-a7063de1-1db6-484b-a80e-e196e71fc391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106640608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4106640608
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2781433376
Short name T395
Test name
Test status
Simulation time 308205457 ps
CPU time 0.75 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:50:01 AM PDT 24
Peak memory 183780 kb
Host smart-8b90a49f-94b3-4639-9ff6-2a03cf6b632b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781433376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2781433376
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1988622455
Short name T363
Test name
Test status
Simulation time 368034843 ps
CPU time 1.07 seconds
Started Jul 01 10:49:56 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 183740 kb
Host smart-2f5cd5b8-1fe9-4e50-9b17-afd902bf01e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988622455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1988622455
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.130041587
Short name T60
Test name
Test status
Simulation time 6986440466 ps
CPU time 10.8 seconds
Started Jul 01 10:49:54 AM PDT 24
Finished Jul 01 10:50:05 AM PDT 24
Peak memory 196332 kb
Host smart-af3fc5c6-7207-46eb-998b-cbe1aef4ba88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130041587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.130041587
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1885051159
Short name T407
Test name
Test status
Simulation time 1218308148 ps
CPU time 1.05 seconds
Started Jul 01 10:49:57 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 183768 kb
Host smart-95c116e0-948d-4a05-b84a-fe9dc2a44d05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885051159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1885051159
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2212537553
Short name T289
Test name
Test status
Simulation time 501799668 ps
CPU time 0.9 seconds
Started Jul 01 10:49:38 AM PDT 24
Finished Jul 01 10:49:40 AM PDT 24
Peak memory 196972 kb
Host smart-1b47cbd0-21a6-4b86-bcdc-a943667e7f0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212537553 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2212537553
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1663502370
Short name T72
Test name
Test status
Simulation time 366942091 ps
CPU time 1.1 seconds
Started Jul 01 10:50:05 AM PDT 24
Finished Jul 01 10:50:07 AM PDT 24
Peak memory 193420 kb
Host smart-cfde2ab2-b3a3-4844-9e26-bc24bec4a39a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663502370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1663502370
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3537125613
Short name T352
Test name
Test status
Simulation time 389577761 ps
CPU time 0.73 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:49:39 AM PDT 24
Peak memory 183796 kb
Host smart-fe325db6-30f0-4f9c-8329-9e7e7493e131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537125613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3537125613
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.909969207
Short name T334
Test name
Test status
Simulation time 348602319 ps
CPU time 1.01 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:49:39 AM PDT 24
Peak memory 183780 kb
Host smart-b9302db9-78e0-4e96-a5ce-f389bbd147d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909969207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.909969207
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2657655572
Short name T298
Test name
Test status
Simulation time 342623226 ps
CPU time 0.63 seconds
Started Jul 01 10:50:03 AM PDT 24
Finished Jul 01 10:50:04 AM PDT 24
Peak memory 183704 kb
Host smart-6d050f44-309b-44f0-b18e-da6e54b48d11
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657655572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2657655572
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1092008793
Short name T342
Test name
Test status
Simulation time 2770788482 ps
CPU time 2.65 seconds
Started Jul 01 10:49:38 AM PDT 24
Finished Jul 01 10:49:42 AM PDT 24
Peak memory 194228 kb
Host smart-147d4b87-5912-4b5c-b171-6105ea07ecba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092008793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1092008793
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2869452641
Short name T327
Test name
Test status
Simulation time 488678399 ps
CPU time 2.81 seconds
Started Jul 01 10:49:56 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 198648 kb
Host smart-e291bd58-dd7d-4d3e-9363-d8ad81a44d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869452641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2869452641
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2190844645
Short name T38
Test name
Test status
Simulation time 8029159081 ps
CPU time 4.12 seconds
Started Jul 01 10:50:01 AM PDT 24
Finished Jul 01 10:50:05 AM PDT 24
Peak memory 198124 kb
Host smart-94f0acaa-76c1-4924-832b-8f59b3102b45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190844645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2190844645
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2247159901
Short name T299
Test name
Test status
Simulation time 380006122 ps
CPU time 0.64 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:16 AM PDT 24
Peak memory 183784 kb
Host smart-96287c6a-a2b4-4baf-97a6-90438ac42759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247159901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2247159901
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.207644038
Short name T413
Test name
Test status
Simulation time 388946430 ps
CPU time 0.76 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:50:01 AM PDT 24
Peak memory 183780 kb
Host smart-58b5098c-3c7f-4cdc-9380-9315754d89b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207644038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.207644038
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3170844375
Short name T401
Test name
Test status
Simulation time 378320998 ps
CPU time 1.14 seconds
Started Jul 01 10:50:00 AM PDT 24
Finished Jul 01 10:50:02 AM PDT 24
Peak memory 183768 kb
Host smart-44b672cf-04f5-47a2-aec0-0483f82b6593
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170844375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3170844375
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1638335303
Short name T356
Test name
Test status
Simulation time 437183952 ps
CPU time 0.83 seconds
Started Jul 01 10:50:10 AM PDT 24
Finished Jul 01 10:50:14 AM PDT 24
Peak memory 183804 kb
Host smart-996e9829-4fcc-4f36-91f9-1f45d4cb4f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638335303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1638335303
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2675651479
Short name T411
Test name
Test status
Simulation time 493216673 ps
CPU time 0.71 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 183816 kb
Host smart-404e731c-34be-4785-9792-068613dfefca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675651479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2675651479
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1915227902
Short name T329
Test name
Test status
Simulation time 507952262 ps
CPU time 1.2 seconds
Started Jul 01 10:49:53 AM PDT 24
Finished Jul 01 10:49:54 AM PDT 24
Peak memory 193012 kb
Host smart-c73c1b39-72dc-4e71-b5f4-17b0bf45a505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915227902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1915227902
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2423955223
Short name T313
Test name
Test status
Simulation time 442863518 ps
CPU time 0.66 seconds
Started Jul 01 10:50:00 AM PDT 24
Finished Jul 01 10:50:01 AM PDT 24
Peak memory 192988 kb
Host smart-92ad6a07-0170-48a6-815f-eec73151abac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423955223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2423955223
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3350306086
Short name T384
Test name
Test status
Simulation time 353819334 ps
CPU time 0.8 seconds
Started Jul 01 10:50:07 AM PDT 24
Finished Jul 01 10:50:11 AM PDT 24
Peak memory 183804 kb
Host smart-9056afa8-94bd-4cf7-8dfd-99ce91e7221a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350306086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3350306086
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2940993363
Short name T309
Test name
Test status
Simulation time 458094471 ps
CPU time 1.27 seconds
Started Jul 01 10:49:54 AM PDT 24
Finished Jul 01 10:49:56 AM PDT 24
Peak memory 183664 kb
Host smart-e150d156-9771-4fdf-a212-51227802dc8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940993363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2940993363
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.33998756
Short name T281
Test name
Test status
Simulation time 459273394 ps
CPU time 1.22 seconds
Started Jul 01 10:50:12 AM PDT 24
Finished Jul 01 10:50:16 AM PDT 24
Peak memory 192660 kb
Host smart-6d529180-1815-47b7-82cd-dddf0bbe6328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33998756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.33998756
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1226257664
Short name T409
Test name
Test status
Simulation time 479844102 ps
CPU time 1.38 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 196496 kb
Host smart-6214ffdf-b8be-457f-a148-e6ae61c7c909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226257664 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1226257664
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2709549268
Short name T39
Test name
Test status
Simulation time 375290282 ps
CPU time 0.72 seconds
Started Jul 01 10:50:06 AM PDT 24
Finished Jul 01 10:50:07 AM PDT 24
Peak memory 192880 kb
Host smart-e4f5e353-9dab-4aa0-bf87-a75d79f31723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709549268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2709549268
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3906554476
Short name T397
Test name
Test status
Simulation time 439054248 ps
CPU time 0.86 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:10 AM PDT 24
Peak memory 183792 kb
Host smart-7605cc30-1928-40d1-bcfa-41f4cdc3cff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906554476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3906554476
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.4117397088
Short name T375
Test name
Test status
Simulation time 1472441379 ps
CPU time 1.41 seconds
Started Jul 01 10:49:41 AM PDT 24
Finished Jul 01 10:49:43 AM PDT 24
Peak memory 193000 kb
Host smart-188d1a0f-c66d-4b2d-b5b9-21f9f3eced59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117397088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.4117397088
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1286185101
Short name T343
Test name
Test status
Simulation time 546600081 ps
CPU time 1.27 seconds
Started Jul 01 10:49:40 AM PDT 24
Finished Jul 01 10:49:42 AM PDT 24
Peak memory 198524 kb
Host smart-12bc0e4b-1169-4c63-87d0-9550f1885358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286185101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1286185101
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.997319098
Short name T314
Test name
Test status
Simulation time 8445892359 ps
CPU time 5.16 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 198292 kb
Host smart-eedcb8b9-6e1f-44bf-9608-8985bd2f2773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997319098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.997319098
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3954059093
Short name T312
Test name
Test status
Simulation time 667396686 ps
CPU time 0.83 seconds
Started Jul 01 10:50:04 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 197068 kb
Host smart-86908646-d101-4982-8425-1afe65566107
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954059093 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3954059093
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2045098918
Short name T73
Test name
Test status
Simulation time 417835416 ps
CPU time 0.85 seconds
Started Jul 01 10:50:05 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 193148 kb
Host smart-1d93e199-c2f6-408a-bafa-939023792244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045098918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2045098918
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.105154822
Short name T321
Test name
Test status
Simulation time 324171376 ps
CPU time 0.75 seconds
Started Jul 01 10:49:39 AM PDT 24
Finished Jul 01 10:49:40 AM PDT 24
Peak memory 183796 kb
Host smart-84fd2ebf-4c3a-40b6-b2fe-1562d6b50d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105154822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.105154822
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2291451980
Short name T378
Test name
Test status
Simulation time 2793243081 ps
CPU time 5.68 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:17 AM PDT 24
Peak memory 194016 kb
Host smart-b37d061b-4553-44bf-8f08-102c2675e18b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291451980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2291451980
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.323693923
Short name T390
Test name
Test status
Simulation time 619357253 ps
CPU time 2.57 seconds
Started Jul 01 10:49:40 AM PDT 24
Finished Jul 01 10:49:43 AM PDT 24
Peak memory 198640 kb
Host smart-af99092c-16fb-45b7-8cb3-03cea8b5bd5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323693923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.323693923
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1857603412
Short name T308
Test name
Test status
Simulation time 4172407220 ps
CPU time 7.33 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:52 AM PDT 24
Peak memory 198052 kb
Host smart-7b186397-687d-4e3b-8a24-6be640c4b150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857603412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1857603412
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2982640419
Short name T304
Test name
Test status
Simulation time 404613431 ps
CPU time 0.94 seconds
Started Jul 01 10:49:39 AM PDT 24
Finished Jul 01 10:49:40 AM PDT 24
Peak memory 195864 kb
Host smart-3b452304-f335-4f02-a48b-7b482185b91c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982640419 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2982640419
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1595830176
Short name T69
Test name
Test status
Simulation time 412396941 ps
CPU time 1.22 seconds
Started Jul 01 10:49:57 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 192056 kb
Host smart-204a948a-6039-4674-890d-3a135846cea5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595830176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1595830176
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.477041231
Short name T324
Test name
Test status
Simulation time 523541900 ps
CPU time 0.65 seconds
Started Jul 01 10:49:41 AM PDT 24
Finished Jul 01 10:49:42 AM PDT 24
Peak memory 183784 kb
Host smart-b29e0798-2b5f-41d9-bdef-c4cf060e6df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477041231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.477041231
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3101275574
Short name T75
Test name
Test status
Simulation time 1635088957 ps
CPU time 2.57 seconds
Started Jul 01 10:50:09 AM PDT 24
Finished Jul 01 10:50:17 AM PDT 24
Peak memory 193880 kb
Host smart-a5ec0c14-e5c2-42ac-906c-114f51a1add5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101275574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3101275574
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4169555823
Short name T300
Test name
Test status
Simulation time 588570406 ps
CPU time 1.21 seconds
Started Jul 01 10:50:08 AM PDT 24
Finished Jul 01 10:50:15 AM PDT 24
Peak memory 198296 kb
Host smart-094794a3-7506-45ba-a38c-472587c695d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169555823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.4169555823
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.145657498
Short name T194
Test name
Test status
Simulation time 8741242485 ps
CPU time 2.14 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 198156 kb
Host smart-95a0ee97-df2c-4bdb-b18c-3b3bc90acb93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145657498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.145657498
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3932253964
Short name T290
Test name
Test status
Simulation time 609160914 ps
CPU time 1.59 seconds
Started Jul 01 10:49:44 AM PDT 24
Finished Jul 01 10:49:47 AM PDT 24
Peak memory 196308 kb
Host smart-891992dc-48be-4308-be07-8beb0ee5be63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932253964 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3932253964
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2148181109
Short name T405
Test name
Test status
Simulation time 444530075 ps
CPU time 0.92 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:45 AM PDT 24
Peak memory 192976 kb
Host smart-eb3c1264-153e-4ef1-ba69-0c4d0cb51820
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148181109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2148181109
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.783080065
Short name T402
Test name
Test status
Simulation time 300118637 ps
CPU time 1.02 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:49:48 AM PDT 24
Peak memory 183688 kb
Host smart-4496aaa3-d6ed-45cf-ba24-33f4b6bf3141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783080065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.783080065
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4250028402
Short name T341
Test name
Test status
Simulation time 2419882989 ps
CPU time 3.08 seconds
Started Jul 01 10:49:42 AM PDT 24
Finished Jul 01 10:49:45 AM PDT 24
Peak memory 195012 kb
Host smart-4ba0e1d5-a988-4dca-8579-3ea0d8484b02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250028402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4250028402
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.820664910
Short name T354
Test name
Test status
Simulation time 609599944 ps
CPU time 1.84 seconds
Started Jul 01 10:49:40 AM PDT 24
Finished Jul 01 10:49:43 AM PDT 24
Peak memory 198556 kb
Host smart-6c44b223-529b-449c-b229-6e78a17f8990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820664910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.820664910
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3383608810
Short name T383
Test name
Test status
Simulation time 3952079698 ps
CPU time 4.77 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:49 AM PDT 24
Peak memory 197636 kb
Host smart-eec0cfb9-5481-4554-8de8-353eedcf9a36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383608810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3383608810
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2200444996
Short name T296
Test name
Test status
Simulation time 726450398 ps
CPU time 0.82 seconds
Started Jul 01 10:49:44 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 197632 kb
Host smart-48f5ff20-aa43-48c3-847e-59d383d2d5e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200444996 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2200444996
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4001059815
Short name T76
Test name
Test status
Simulation time 418020903 ps
CPU time 1.15 seconds
Started Jul 01 10:49:44 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 193124 kb
Host smart-91870009-63d1-4e02-9030-566c5131483e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001059815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4001059815
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.190961099
Short name T326
Test name
Test status
Simulation time 442984986 ps
CPU time 1.14 seconds
Started Jul 01 10:49:45 AM PDT 24
Finished Jul 01 10:49:48 AM PDT 24
Peak memory 183788 kb
Host smart-b8d6cc94-3d8b-44b9-a751-ab1c7a24607f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190961099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.190961099
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1185040782
Short name T330
Test name
Test status
Simulation time 2055152827 ps
CPU time 3.97 seconds
Started Jul 01 10:49:45 AM PDT 24
Finished Jul 01 10:49:49 AM PDT 24
Peak memory 194116 kb
Host smart-b7b4677b-c6f5-4587-a7f4-00c227763233
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185040782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1185040782
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1667963045
Short name T284
Test name
Test status
Simulation time 352528372 ps
CPU time 1.98 seconds
Started Jul 01 10:50:03 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 198508 kb
Host smart-3f9e72ec-7dda-4c79-af1f-504ba0e115b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667963045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1667963045
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2136968069
Short name T386
Test name
Test status
Simulation time 7753273083 ps
CPU time 4.01 seconds
Started Jul 01 10:49:45 AM PDT 24
Finished Jul 01 10:49:49 AM PDT 24
Peak memory 198280 kb
Host smart-2edeb9c3-ad20-4a63-af70-ee90db28d53b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136968069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2136968069
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3766457070
Short name T195
Test name
Test status
Simulation time 19684565898 ps
CPU time 25.72 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 196704 kb
Host smart-f3b2434d-7593-4877-aa34-aef9b4971465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766457070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3766457070
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3906657925
Short name T51
Test name
Test status
Simulation time 425942635 ps
CPU time 1.12 seconds
Started Jul 01 10:50:59 AM PDT 24
Finished Jul 01 10:51:02 AM PDT 24
Peak memory 191568 kb
Host smart-99d7703d-1ef6-480f-a640-5e3650f0a984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906657925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3906657925
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3100070865
Short name T204
Test name
Test status
Simulation time 45974961612 ps
CPU time 18.77 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:19 AM PDT 24
Peak memory 191664 kb
Host smart-040f2ecf-8f4a-4145-8d73-9ff5d26b4062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100070865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3100070865
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1879202482
Short name T18
Test name
Test status
Simulation time 4192640078 ps
CPU time 2.26 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:02 AM PDT 24
Peak memory 215364 kb
Host smart-8369d247-d61f-4012-9ab8-07fcab4c19f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879202482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1879202482
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.978014423
Short name T210
Test name
Test status
Simulation time 480378736 ps
CPU time 1.32 seconds
Started Jul 01 10:50:57 AM PDT 24
Finished Jul 01 10:51:00 AM PDT 24
Peak memory 196448 kb
Host smart-c97f369d-6642-4fce-9992-3e57cf2f37e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978014423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.978014423
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1034516855
Short name T175
Test name
Test status
Simulation time 579236790 ps
CPU time 0.83 seconds
Started Jul 01 10:51:11 AM PDT 24
Finished Jul 01 10:51:13 AM PDT 24
Peak memory 196372 kb
Host smart-7b9d5330-caad-4290-8993-c357f9bc808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034516855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1034516855
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.150332105
Short name T249
Test name
Test status
Simulation time 36462357522 ps
CPU time 45.93 seconds
Started Jul 01 10:51:11 AM PDT 24
Finished Jul 01 10:51:57 AM PDT 24
Peak memory 191676 kb
Host smart-3c29e2b2-dcdb-4f5b-a7d8-49b724a6eb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150332105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.150332105
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1614466267
Short name T239
Test name
Test status
Simulation time 547639362 ps
CPU time 1.25 seconds
Started Jul 01 10:51:30 AM PDT 24
Finished Jul 01 10:51:33 AM PDT 24
Peak memory 191604 kb
Host smart-c0b494fa-ec42-4494-bd0f-6fe0dc49fcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614466267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1614466267
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1408435401
Short name T229
Test name
Test status
Simulation time 12316370421 ps
CPU time 19.35 seconds
Started Jul 01 10:51:11 AM PDT 24
Finished Jul 01 10:51:31 AM PDT 24
Peak memory 191652 kb
Host smart-c2036869-d376-4626-96a9-2c0f7975abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408435401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1408435401
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2822175659
Short name T53
Test name
Test status
Simulation time 598415992 ps
CPU time 1.03 seconds
Started Jul 01 10:51:10 AM PDT 24
Finished Jul 01 10:51:12 AM PDT 24
Peak memory 196444 kb
Host smart-f746803f-ee04-4883-9d17-5e2ea72ecf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822175659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2822175659
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4070195211
Short name T218
Test name
Test status
Simulation time 24533624227 ps
CPU time 18.1 seconds
Started Jul 01 10:51:12 AM PDT 24
Finished Jul 01 10:51:31 AM PDT 24
Peak memory 191676 kb
Host smart-a83bf008-995f-47c5-9e06-c17b4fcb241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070195211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4070195211
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3923521147
Short name T251
Test name
Test status
Simulation time 452359212 ps
CPU time 0.74 seconds
Started Jul 01 10:51:12 AM PDT 24
Finished Jul 01 10:51:13 AM PDT 24
Peak memory 191580 kb
Host smart-4c91de42-4c79-472d-a8b3-787fa6cd0e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923521147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3923521147
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3608117139
Short name T238
Test name
Test status
Simulation time 50395173770 ps
CPU time 17.48 seconds
Started Jul 01 10:51:31 AM PDT 24
Finished Jul 01 10:51:49 AM PDT 24
Peak memory 196660 kb
Host smart-7038d83e-452c-48d0-a9b4-79c46b4fe6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608117139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3608117139
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1906954840
Short name T224
Test name
Test status
Simulation time 424628615 ps
CPU time 0.85 seconds
Started Jul 01 10:51:36 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 196444 kb
Host smart-0dce1cb8-05ef-434e-bca6-d7d393cc0d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906954840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1906954840
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3682975240
Short name T203
Test name
Test status
Simulation time 28587623516 ps
CPU time 11.62 seconds
Started Jul 01 10:51:25 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 191660 kb
Host smart-d8c60c1d-7e7f-495e-9df3-2042e232cbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682975240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3682975240
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3800316809
Short name T257
Test name
Test status
Simulation time 397888035 ps
CPU time 0.85 seconds
Started Jul 01 10:51:18 AM PDT 24
Finished Jul 01 10:51:19 AM PDT 24
Peak memory 196468 kb
Host smart-70b378bf-b817-4102-97d4-c9a516f6334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800316809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3800316809
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2531198711
Short name T222
Test name
Test status
Simulation time 513126974822 ps
CPU time 174.08 seconds
Started Jul 01 10:51:30 AM PDT 24
Finished Jul 01 10:54:30 AM PDT 24
Peak memory 184148 kb
Host smart-303fbbc9-ba7f-40b4-8a3a-0b0db9029c07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531198711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2531198711
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.240244327
Short name T225
Test name
Test status
Simulation time 32348116177 ps
CPU time 36.75 seconds
Started Jul 01 10:51:25 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 196704 kb
Host smart-968051bf-afe3-4e10-b6d6-d0b4602b6cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240244327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.240244327
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2074246611
Short name T274
Test name
Test status
Simulation time 451658890 ps
CPU time 0.61 seconds
Started Jul 01 10:51:16 AM PDT 24
Finished Jul 01 10:51:17 AM PDT 24
Peak memory 191584 kb
Host smart-b8c66401-a8ec-4de8-b954-3626efedb84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074246611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2074246611
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.576676225
Short name T176
Test name
Test status
Simulation time 203629394398 ps
CPU time 271.32 seconds
Started Jul 01 10:51:20 AM PDT 24
Finished Jul 01 10:55:52 AM PDT 24
Peak memory 192032 kb
Host smart-50618e64-3c0a-4305-afe9-5471cf696d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576676225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.576676225
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.691850687
Short name T245
Test name
Test status
Simulation time 28323701474 ps
CPU time 10.17 seconds
Started Jul 01 10:51:22 AM PDT 24
Finished Jul 01 10:51:33 AM PDT 24
Peak memory 191672 kb
Host smart-533d9486-6332-4603-a1cc-cf44a16486ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691850687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.691850687
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.113445463
Short name T255
Test name
Test status
Simulation time 396435221 ps
CPU time 1.12 seconds
Started Jul 01 10:51:29 AM PDT 24
Finished Jul 01 10:51:31 AM PDT 24
Peak memory 191608 kb
Host smart-ae5f7df0-7258-4186-a5c8-8e51b5835dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113445463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.113445463
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1119965572
Short name T201
Test name
Test status
Simulation time 41591776508 ps
CPU time 11.65 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:52:01 AM PDT 24
Peak memory 196692 kb
Host smart-bf47c965-5295-4ec6-8a21-19fac0be070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119965572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1119965572
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1851960406
Short name T230
Test name
Test status
Simulation time 558168348 ps
CPU time 0.76 seconds
Started Jul 01 10:51:21 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 191584 kb
Host smart-92403d3f-645f-4ae6-8199-afa5bd579fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851960406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1851960406
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_jump.666114131
Short name T167
Test name
Test status
Simulation time 365454964 ps
CPU time 1.08 seconds
Started Jul 01 10:51:21 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 196372 kb
Host smart-3bee05ff-3bec-4857-a916-d73d8db26065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666114131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.666114131
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.284900801
Short name T273
Test name
Test status
Simulation time 2323257189 ps
CPU time 1.38 seconds
Started Jul 01 10:51:23 AM PDT 24
Finished Jul 01 10:51:25 AM PDT 24
Peak memory 191612 kb
Host smart-6a5a027d-9734-4310-9848-9e3985cadabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284900801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.284900801
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3794064465
Short name T271
Test name
Test status
Simulation time 503517790 ps
CPU time 1.1 seconds
Started Jul 01 10:51:43 AM PDT 24
Finished Jul 01 10:51:45 AM PDT 24
Peak memory 196452 kb
Host smart-a920628b-23d0-4e1d-8eb4-6aadafb62073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794064465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3794064465
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1452109798
Short name T262
Test name
Test status
Simulation time 38369857356 ps
CPU time 12.52 seconds
Started Jul 01 10:51:24 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 196668 kb
Host smart-727fcbf7-7369-44e2-950e-9f3f1dfc0bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452109798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1452109798
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1945461522
Short name T231
Test name
Test status
Simulation time 681991150 ps
CPU time 0.65 seconds
Started Jul 01 10:51:32 AM PDT 24
Finished Jul 01 10:51:34 AM PDT 24
Peak memory 191532 kb
Host smart-dda0eae3-bd7c-453c-8c1d-9639a994959b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945461522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1945461522
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3569754480
Short name T232
Test name
Test status
Simulation time 10013008300 ps
CPU time 2.3 seconds
Started Jul 01 10:51:05 AM PDT 24
Finished Jul 01 10:51:07 AM PDT 24
Peak memory 191660 kb
Host smart-b404f44f-586a-4c95-b2f0-46466175e20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569754480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3569754480
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.621483943
Short name T19
Test name
Test status
Simulation time 7525623419 ps
CPU time 3.3 seconds
Started Jul 01 10:51:02 AM PDT 24
Finished Jul 01 10:51:06 AM PDT 24
Peak memory 215768 kb
Host smart-52521c5f-7d9a-43a8-896e-40dbad648ddf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621483943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.621483943
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2322595943
Short name T254
Test name
Test status
Simulation time 419301182 ps
CPU time 0.85 seconds
Started Jul 01 10:50:58 AM PDT 24
Finished Jul 01 10:51:00 AM PDT 24
Peak memory 191584 kb
Host smart-c221315b-4db7-486a-a6a0-c603deb110f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322595943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2322595943
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1389697919
Short name T200
Test name
Test status
Simulation time 47928943746 ps
CPU time 33.95 seconds
Started Jul 01 10:51:31 AM PDT 24
Finished Jul 01 10:52:06 AM PDT 24
Peak memory 196664 kb
Host smart-f8787bc3-df27-4697-9263-2c2a74950601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389697919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1389697919
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.418216853
Short name T265
Test name
Test status
Simulation time 452318866 ps
CPU time 0.76 seconds
Started Jul 01 10:51:22 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 191596 kb
Host smart-a8f71d5b-8c3f-452e-be8f-6af75471befd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418216853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.418216853
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1497833405
Short name T11
Test name
Test status
Simulation time 10828056716 ps
CPU time 1.98 seconds
Started Jul 01 10:51:39 AM PDT 24
Finished Jul 01 10:51:42 AM PDT 24
Peak memory 191608 kb
Host smart-0f633036-e08c-40a7-956d-a49438b2a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497833405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1497833405
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3460823699
Short name T197
Test name
Test status
Simulation time 394743484 ps
CPU time 1.22 seconds
Started Jul 01 10:51:39 AM PDT 24
Finished Jul 01 10:51:40 AM PDT 24
Peak memory 191580 kb
Host smart-2ee1a4ec-64d0-4fab-9958-9d7d7190686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460823699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3460823699
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.204149328
Short name T240
Test name
Test status
Simulation time 34154681900 ps
CPU time 11.58 seconds
Started Jul 01 10:51:25 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 191680 kb
Host smart-e6d9033e-abc9-4980-a917-3835b85935ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204149328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.204149328
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.139437713
Short name T261
Test name
Test status
Simulation time 519884757 ps
CPU time 1.36 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:51:50 AM PDT 24
Peak memory 191568 kb
Host smart-406fdcfa-9c34-4c06-9e3b-b9de923f152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139437713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.139437713
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3418448559
Short name T160
Test name
Test status
Simulation time 402358871 ps
CPU time 0.86 seconds
Started Jul 01 10:51:37 AM PDT 24
Finished Jul 01 10:51:39 AM PDT 24
Peak memory 196392 kb
Host smart-9c5785f2-2ed6-42fc-9f1a-3f89a2b3be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418448559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3418448559
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1325300294
Short name T252
Test name
Test status
Simulation time 11158665098 ps
CPU time 8.13 seconds
Started Jul 01 10:51:41 AM PDT 24
Finished Jul 01 10:51:50 AM PDT 24
Peak memory 196660 kb
Host smart-5bf79ee6-c70a-4200-bfa7-40d8a57da2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325300294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1325300294
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2590593396
Short name T205
Test name
Test status
Simulation time 572329509 ps
CPU time 1 seconds
Started Jul 01 10:51:26 AM PDT 24
Finished Jul 01 10:51:27 AM PDT 24
Peak memory 191520 kb
Host smart-32617eff-a5ab-4d70-9b5f-70c49c51a0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590593396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2590593396
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3945527714
Short name T12
Test name
Test status
Simulation time 33880555183 ps
CPU time 53.26 seconds
Started Jul 01 10:51:24 AM PDT 24
Finished Jul 01 10:52:18 AM PDT 24
Peak memory 196668 kb
Host smart-2a2e91dd-6c3a-4e4d-9878-dc62b1ea39db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945527714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3945527714
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.820069900
Short name T213
Test name
Test status
Simulation time 373964138 ps
CPU time 1.08 seconds
Started Jul 01 10:51:47 AM PDT 24
Finished Jul 01 10:51:49 AM PDT 24
Peak memory 191572 kb
Host smart-70a38538-0fcb-4981-b9d8-294d2d938ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820069900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.820069900
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2768959070
Short name T248
Test name
Test status
Simulation time 9097425238 ps
CPU time 3.68 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:51:53 AM PDT 24
Peak memory 191624 kb
Host smart-a50da8c2-8585-48df-bb2b-454b4220a0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768959070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2768959070
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2603471332
Short name T208
Test name
Test status
Simulation time 358824918 ps
CPU time 1.11 seconds
Started Jul 01 10:51:31 AM PDT 24
Finished Jul 01 10:51:33 AM PDT 24
Peak memory 196388 kb
Host smart-f4649197-944c-4c72-bb86-7824beabb01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603471332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2603471332
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1734273135
Short name T268
Test name
Test status
Simulation time 37246527856 ps
CPU time 388.99 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:58:22 AM PDT 24
Peak memory 199080 kb
Host smart-3d67b4e2-cee0-4ec5-961c-f369103d99c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734273135 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1734273135
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1620515662
Short name T23
Test name
Test status
Simulation time 30624377133 ps
CPU time 22.58 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:52:13 AM PDT 24
Peak memory 191684 kb
Host smart-7916691a-c196-48df-b397-290c6fddba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620515662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1620515662
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.669406980
Short name T220
Test name
Test status
Simulation time 494638768 ps
CPU time 1.27 seconds
Started Jul 01 10:51:30 AM PDT 24
Finished Jul 01 10:51:33 AM PDT 24
Peak memory 191604 kb
Host smart-4745ce39-524f-4c0c-947f-f6bc82beded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669406980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.669406980
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3572837342
Short name T226
Test name
Test status
Simulation time 50910222347 ps
CPU time 73.94 seconds
Started Jul 01 10:51:28 AM PDT 24
Finished Jul 01 10:52:43 AM PDT 24
Peak memory 191668 kb
Host smart-bf0e9ce8-c749-4a64-9b56-c44bd95df704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572837342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3572837342
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3162047539
Short name T56
Test name
Test status
Simulation time 537328670 ps
CPU time 1.38 seconds
Started Jul 01 10:52:03 AM PDT 24
Finished Jul 01 10:52:08 AM PDT 24
Peak memory 196340 kb
Host smart-5562baa8-2287-4282-8f68-d58cf8605957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162047539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3162047539
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.789671905
Short name T234
Test name
Test status
Simulation time 26183366964 ps
CPU time 6.19 seconds
Started Jul 01 10:51:45 AM PDT 24
Finished Jul 01 10:51:52 AM PDT 24
Peak memory 191680 kb
Host smart-7f3af4e5-533d-47f0-8e12-bf3970d19476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789671905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.789671905
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.684057255
Short name T198
Test name
Test status
Simulation time 515007644 ps
CPU time 1.26 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 196380 kb
Host smart-15c38ebb-6c2c-45df-b044-9fe210a2ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684057255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.684057255
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.50491468
Short name T266
Test name
Test status
Simulation time 33745550287 ps
CPU time 14.13 seconds
Started Jul 01 10:51:34 AM PDT 24
Finished Jul 01 10:51:49 AM PDT 24
Peak memory 191632 kb
Host smart-1a2fc323-79db-432b-9b55-73bc9f129044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50491468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.50491468
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.179004413
Short name T209
Test name
Test status
Simulation time 438292315 ps
CPU time 0.65 seconds
Started Jul 01 10:51:49 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 191580 kb
Host smart-45938e6d-55b0-4647-a206-f476b91e5d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179004413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.179004413
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3193764499
Short name T207
Test name
Test status
Simulation time 12696001094 ps
CPU time 10.63 seconds
Started Jul 01 10:51:11 AM PDT 24
Finished Jul 01 10:51:22 AM PDT 24
Peak memory 191604 kb
Host smart-8bf4f1e9-caea-469e-8170-4febaace1d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193764499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3193764499
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2716911983
Short name T20
Test name
Test status
Simulation time 3992322721 ps
CPU time 3.59 seconds
Started Jul 01 10:51:02 AM PDT 24
Finished Jul 01 10:51:06 AM PDT 24
Peak memory 215320 kb
Host smart-d0017202-4a0f-4dab-a122-02f74977ef3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716911983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2716911983
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.88842592
Short name T199
Test name
Test status
Simulation time 434326969 ps
CPU time 1.18 seconds
Started Jul 01 10:51:04 AM PDT 24
Finished Jul 01 10:51:05 AM PDT 24
Peak memory 191576 kb
Host smart-8407da98-dd70-4823-a9f3-c2bfdfbc082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88842592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.88842592
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3654309987
Short name T276
Test name
Test status
Simulation time 29683093676 ps
CPU time 11.65 seconds
Started Jul 01 10:51:54 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 191576 kb
Host smart-f213a135-f9fd-4080-b708-c68fd8cf299e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654309987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3654309987
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2451389265
Short name T25
Test name
Test status
Simulation time 565787588 ps
CPU time 0.74 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 196440 kb
Host smart-eaabb336-9d5c-4e17-bcbc-18da68893646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451389265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2451389265
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1493261953
Short name T181
Test name
Test status
Simulation time 616390800 ps
CPU time 0.79 seconds
Started Jul 01 10:51:55 AM PDT 24
Finished Jul 01 10:51:57 AM PDT 24
Peak memory 196280 kb
Host smart-0d112397-e117-4758-a44c-6b82e78dd76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493261953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1493261953
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.738870825
Short name T244
Test name
Test status
Simulation time 26968076502 ps
CPU time 11.19 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:52:02 AM PDT 24
Peak memory 191572 kb
Host smart-4a7d90cb-7ea6-4f75-a41f-5a1a00e561cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738870825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.738870825
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1133955143
Short name T253
Test name
Test status
Simulation time 420278776 ps
CPU time 0.92 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:51:55 AM PDT 24
Peak memory 191512 kb
Host smart-294c1d51-5b17-4384-9148-c2fd496e68b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133955143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1133955143
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.88195712
Short name T216
Test name
Test status
Simulation time 46834550985 ps
CPU time 3.63 seconds
Started Jul 01 10:51:37 AM PDT 24
Finished Jul 01 10:51:41 AM PDT 24
Peak memory 191680 kb
Host smart-445c0445-1230-4960-bb4f-b17d9eee72e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88195712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.88195712
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2291867845
Short name T219
Test name
Test status
Simulation time 432848727 ps
CPU time 0.75 seconds
Started Jul 01 10:51:35 AM PDT 24
Finished Jul 01 10:51:36 AM PDT 24
Peak memory 191584 kb
Host smart-0be37ee2-9384-4ab4-93ec-7223f1f9940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291867845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2291867845
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2706907532
Short name T177
Test name
Test status
Simulation time 43533250916 ps
CPU time 442.77 seconds
Started Jul 01 10:51:57 AM PDT 24
Finished Jul 01 10:59:21 AM PDT 24
Peak memory 208852 kb
Host smart-c0d41a1d-bc5c-44c0-9e8a-eb19df70eb10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706907532 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2706907532
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1236027835
Short name T236
Test name
Test status
Simulation time 32190685893 ps
CPU time 50.14 seconds
Started Jul 01 10:51:38 AM PDT 24
Finished Jul 01 10:52:28 AM PDT 24
Peak memory 191640 kb
Host smart-0fea19af-77f2-4a4b-a140-ac05c79ab548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236027835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1236027835
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2048563843
Short name T243
Test name
Test status
Simulation time 596796079 ps
CPU time 0.62 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:51:55 AM PDT 24
Peak memory 191508 kb
Host smart-2cb6af1b-920b-484d-bdf0-b833e331bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048563843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2048563843
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2046922662
Short name T49
Test name
Test status
Simulation time 16843971488 ps
CPU time 11.98 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:52:06 AM PDT 24
Peak memory 191580 kb
Host smart-85f85f7d-b3b8-4391-98c2-4432f2428923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046922662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2046922662
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1827624483
Short name T24
Test name
Test status
Simulation time 480570134 ps
CPU time 0.76 seconds
Started Jul 01 10:51:38 AM PDT 24
Finished Jul 01 10:51:39 AM PDT 24
Peak memory 191580 kb
Host smart-92afd936-0135-4cd7-921c-2b764f4d8d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827624483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1827624483
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.368333592
Short name T48
Test name
Test status
Simulation time 17930017295 ps
CPU time 7.63 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:52:01 AM PDT 24
Peak memory 191584 kb
Host smart-0541585e-792e-4c2c-a93d-17e7aed40c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368333592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.368333592
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3579681406
Short name T260
Test name
Test status
Simulation time 478052627 ps
CPU time 1.34 seconds
Started Jul 01 10:51:37 AM PDT 24
Finished Jul 01 10:51:39 AM PDT 24
Peak memory 191584 kb
Host smart-c4896b12-dfcd-4d6c-89f9-3f0a85034885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579681406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3579681406
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1665179249
Short name T215
Test name
Test status
Simulation time 43925032769 ps
CPU time 16.06 seconds
Started Jul 01 10:51:40 AM PDT 24
Finished Jul 01 10:51:57 AM PDT 24
Peak memory 191672 kb
Host smart-3a8208bd-47a4-475e-b379-be7f660be2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665179249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1665179249
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1488623546
Short name T202
Test name
Test status
Simulation time 635816923 ps
CPU time 0.88 seconds
Started Jul 01 10:51:42 AM PDT 24
Finished Jul 01 10:51:44 AM PDT 24
Peak memory 191604 kb
Host smart-509b266b-db21-4452-8b11-3eb27238d22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488623546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1488623546
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.4003908230
Short name T52
Test name
Test status
Simulation time 22619248550 ps
CPU time 32.37 seconds
Started Jul 01 10:51:39 AM PDT 24
Finished Jul 01 10:52:12 AM PDT 24
Peak memory 196700 kb
Host smart-f115193f-51a8-4918-914d-5331974ae87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003908230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.4003908230
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2402695807
Short name T269
Test name
Test status
Simulation time 399615930 ps
CPU time 0.72 seconds
Started Jul 01 10:51:40 AM PDT 24
Finished Jul 01 10:51:42 AM PDT 24
Peak memory 191600 kb
Host smart-cc0989fb-18ad-41eb-8bf9-bb1384ca0fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402695807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2402695807
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1256196638
Short name T246
Test name
Test status
Simulation time 6015928011 ps
CPU time 9.02 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 196548 kb
Host smart-ce855d1c-bd8b-43dc-9b5b-98014de24da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256196638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1256196638
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3842363174
Short name T242
Test name
Test status
Simulation time 378862767 ps
CPU time 0.9 seconds
Started Jul 01 10:51:41 AM PDT 24
Finished Jul 01 10:51:43 AM PDT 24
Peak memory 191604 kb
Host smart-d0bbd9d4-16b5-4fe2-a711-4b64157df83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842363174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3842363174
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4103941517
Short name T237
Test name
Test status
Simulation time 5817606653 ps
CPU time 2.63 seconds
Started Jul 01 10:51:45 AM PDT 24
Finished Jul 01 10:51:49 AM PDT 24
Peak memory 191636 kb
Host smart-b70f4283-dbae-48b5-b864-f2b3df52048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103941517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4103941517
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2023179194
Short name T211
Test name
Test status
Simulation time 574077366 ps
CPU time 1.37 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:51:55 AM PDT 24
Peak memory 196456 kb
Host smart-d8f09c1c-b98e-46cd-988c-37825b08eb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023179194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2023179194
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3947955444
Short name T7
Test name
Test status
Simulation time 40294982663 ps
CPU time 52.25 seconds
Started Jul 01 10:51:00 AM PDT 24
Finished Jul 01 10:51:54 AM PDT 24
Peak memory 191640 kb
Host smart-7976cbdd-02b5-473a-8972-9f5fe9fa51a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947955444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3947955444
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.700438798
Short name T21
Test name
Test status
Simulation time 7581472034 ps
CPU time 3.66 seconds
Started Jul 01 10:51:09 AM PDT 24
Finished Jul 01 10:51:14 AM PDT 24
Peak memory 215752 kb
Host smart-9e4e4147-77f7-49f0-b219-18f778ac8e8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700438798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.700438798
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.4060196694
Short name T263
Test name
Test status
Simulation time 597296365 ps
CPU time 1.47 seconds
Started Jul 01 10:51:05 AM PDT 24
Finished Jul 01 10:51:07 AM PDT 24
Peak memory 196452 kb
Host smart-203aefdd-90f7-4036-a0c4-a95d11a81ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060196694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.4060196694
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2264645681
Short name T14
Test name
Test status
Simulation time 38712171407 ps
CPU time 20.78 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:52:13 AM PDT 24
Peak memory 196684 kb
Host smart-b7e371f9-99bc-4753-90d7-d339a239e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264645681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2264645681
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3342185153
Short name T258
Test name
Test status
Simulation time 518522246 ps
CPU time 0.75 seconds
Started Jul 01 10:51:52 AM PDT 24
Finished Jul 01 10:51:54 AM PDT 24
Peak memory 191580 kb
Host smart-e737ab93-e171-4edc-8fc6-a09e0677d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342185153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3342185153
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2265340429
Short name T28
Test name
Test status
Simulation time 36068673766 ps
CPU time 46.86 seconds
Started Jul 01 10:51:42 AM PDT 24
Finished Jul 01 10:52:30 AM PDT 24
Peak memory 196580 kb
Host smart-52d89087-3e3a-4419-8942-f521aa23e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265340429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2265340429
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1098736742
Short name T214
Test name
Test status
Simulation time 369929581 ps
CPU time 0.79 seconds
Started Jul 01 10:51:47 AM PDT 24
Finished Jul 01 10:51:48 AM PDT 24
Peak memory 191572 kb
Host smart-2c539415-457a-483e-b953-b4823186e889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098736742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1098736742
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2546695104
Short name T4
Test name
Test status
Simulation time 12182277785 ps
CPU time 9.57 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 191636 kb
Host smart-6adba94e-cc90-46bc-b404-778ec238723b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546695104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2546695104
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1556077413
Short name T10
Test name
Test status
Simulation time 431929616 ps
CPU time 0.72 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:51:53 AM PDT 24
Peak memory 196392 kb
Host smart-188924df-433e-4fc2-a5f3-ac4307cd32a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556077413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1556077413
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2256337958
Short name T256
Test name
Test status
Simulation time 49253576698 ps
CPU time 5.19 seconds
Started Jul 01 10:51:53 AM PDT 24
Finished Jul 01 10:52:00 AM PDT 24
Peak memory 196680 kb
Host smart-d4eba447-ff3c-49e5-b0dc-789683ade5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256337958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2256337958
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2441812585
Short name T217
Test name
Test status
Simulation time 602953442 ps
CPU time 1.07 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:51:54 AM PDT 24
Peak memory 191536 kb
Host smart-6fce5b38-ddb2-46a0-8398-a1002798823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441812585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2441812585
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1025978594
Short name T270
Test name
Test status
Simulation time 40550490185 ps
CPU time 16.03 seconds
Started Jul 01 10:51:55 AM PDT 24
Finished Jul 01 10:52:12 AM PDT 24
Peak memory 196672 kb
Host smart-15490daa-def8-4cf4-bd11-4f0256ca0ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025978594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1025978594
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3209340678
Short name T223
Test name
Test status
Simulation time 517107107 ps
CPU time 1.29 seconds
Started Jul 01 10:52:00 AM PDT 24
Finished Jul 01 10:52:04 AM PDT 24
Peak memory 196388 kb
Host smart-7921e294-6f42-40ef-b6ac-b407e5901a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209340678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3209340678
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3623365742
Short name T264
Test name
Test status
Simulation time 1828126097 ps
CPU time 3.23 seconds
Started Jul 01 10:51:50 AM PDT 24
Finished Jul 01 10:51:55 AM PDT 24
Peak memory 196304 kb
Host smart-6226d89c-4ff8-4295-9e9f-e1291820ca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623365742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3623365742
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2540552749
Short name T221
Test name
Test status
Simulation time 540248618 ps
CPU time 0.75 seconds
Started Jul 01 10:52:01 AM PDT 24
Finished Jul 01 10:52:04 AM PDT 24
Peak memory 196472 kb
Host smart-3e939834-9004-4fd8-944f-27bf59139bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540552749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2540552749
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1316191337
Short name T30
Test name
Test status
Simulation time 13059006391 ps
CPU time 1.94 seconds
Started Jul 01 10:51:53 AM PDT 24
Finished Jul 01 10:51:57 AM PDT 24
Peak memory 191684 kb
Host smart-9fafef09-07aa-4f14-8404-8a36cf0dc5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316191337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1316191337
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2773898190
Short name T13
Test name
Test status
Simulation time 568311152 ps
CPU time 0.8 seconds
Started Jul 01 10:51:51 AM PDT 24
Finished Jul 01 10:51:54 AM PDT 24
Peak memory 191584 kb
Host smart-9789b7f1-d389-406e-beb6-4cd64588b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773898190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2773898190
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.738881307
Short name T29
Test name
Test status
Simulation time 16867001751 ps
CPU time 6.94 seconds
Started Jul 01 10:51:53 AM PDT 24
Finished Jul 01 10:52:01 AM PDT 24
Peak memory 191612 kb
Host smart-1c9d6fb7-1df1-481a-8fbd-2d550d9b692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738881307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.738881307
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3302131144
Short name T241
Test name
Test status
Simulation time 534300537 ps
CPU time 1.23 seconds
Started Jul 01 10:51:48 AM PDT 24
Finished Jul 01 10:51:51 AM PDT 24
Peak memory 191596 kb
Host smart-01fdba1c-2a3b-4aa8-b8c6-f01ea68fa381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302131144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3302131144
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.862685809
Short name T228
Test name
Test status
Simulation time 5405002786 ps
CPU time 1.94 seconds
Started Jul 01 10:52:02 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 191592 kb
Host smart-ea96b0ff-0ad5-4fb9-970b-08646b5038c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862685809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.862685809
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.4225682479
Short name T227
Test name
Test status
Simulation time 412495996 ps
CPU time 0.76 seconds
Started Jul 01 10:52:10 AM PDT 24
Finished Jul 01 10:52:14 AM PDT 24
Peak memory 191728 kb
Host smart-ce7493e6-26aa-4b22-bbfe-efcca6f89c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225682479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.4225682479
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3988839517
Short name T259
Test name
Test status
Simulation time 37775457041 ps
CPU time 13.38 seconds
Started Jul 01 10:51:54 AM PDT 24
Finished Jul 01 10:52:09 AM PDT 24
Peak memory 191608 kb
Host smart-ea461d5a-382b-42ee-a255-f45e5a5cb2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988839517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3988839517
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2991022720
Short name T272
Test name
Test status
Simulation time 370637866 ps
CPU time 0.92 seconds
Started Jul 01 10:51:58 AM PDT 24
Finished Jul 01 10:52:00 AM PDT 24
Peak memory 191620 kb
Host smart-21bc0bdb-1b56-43ac-8f67-d16eaab28395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991022720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2991022720
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2873590926
Short name T212
Test name
Test status
Simulation time 40872904150 ps
CPU time 59.58 seconds
Started Jul 01 10:51:07 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 191672 kb
Host smart-c7156e28-36c5-4240-b3cf-8fd3e771e252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873590926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2873590926
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.628965148
Short name T233
Test name
Test status
Simulation time 410414638 ps
CPU time 1.14 seconds
Started Jul 01 10:51:04 AM PDT 24
Finished Jul 01 10:51:05 AM PDT 24
Peak memory 191576 kb
Host smart-66ede6b7-4462-4d17-9b90-9d266b9be505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628965148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.628965148
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3473464790
Short name T47
Test name
Test status
Simulation time 47177494926 ps
CPU time 16.33 seconds
Started Jul 01 10:51:07 AM PDT 24
Finished Jul 01 10:51:24 AM PDT 24
Peak memory 191688 kb
Host smart-8608ac6a-6c98-470f-b8b5-f5bc55e643a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473464790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3473464790
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.4184340049
Short name T3
Test name
Test status
Simulation time 419217799 ps
CPU time 1.23 seconds
Started Jul 01 10:51:08 AM PDT 24
Finished Jul 01 10:51:09 AM PDT 24
Peak memory 196480 kb
Host smart-026d6ef3-437e-40cb-abcc-0d15959abe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184340049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4184340049
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3136666281
Short name T267
Test name
Test status
Simulation time 24714451751 ps
CPU time 31.43 seconds
Started Jul 01 10:51:09 AM PDT 24
Finished Jul 01 10:51:42 AM PDT 24
Peak memory 196672 kb
Host smart-16a7de89-e039-4ffe-a0de-078f9219b019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136666281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3136666281
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1985685164
Short name T206
Test name
Test status
Simulation time 402723187 ps
CPU time 0.75 seconds
Started Jul 01 10:51:09 AM PDT 24
Finished Jul 01 10:51:10 AM PDT 24
Peak memory 196404 kb
Host smart-b201a5a7-6525-445e-9c17-21421d137715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985685164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1985685164
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1487438842
Short name T247
Test name
Test status
Simulation time 9596671902 ps
CPU time 15.55 seconds
Started Jul 01 10:51:10 AM PDT 24
Finished Jul 01 10:51:27 AM PDT 24
Peak memory 191672 kb
Host smart-b14c2c96-7384-40b0-ae96-90c4bf140750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487438842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1487438842
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.409321855
Short name T235
Test name
Test status
Simulation time 542183697 ps
CPU time 0.73 seconds
Started Jul 01 10:51:10 AM PDT 24
Finished Jul 01 10:51:12 AM PDT 24
Peak memory 196404 kb
Host smart-5c1e2ba8-44a6-4a4e-9827-e919eb2abf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409321855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.409321855
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1442683171
Short name T275
Test name
Test status
Simulation time 53084879973 ps
CPU time 41.84 seconds
Started Jul 01 10:51:12 AM PDT 24
Finished Jul 01 10:51:54 AM PDT 24
Peak memory 191644 kb
Host smart-7b63677c-ef0e-48e9-b028-f05c7d53ae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442683171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1442683171
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.755553656
Short name T250
Test name
Test status
Simulation time 423555783 ps
CPU time 0.78 seconds
Started Jul 01 10:51:11 AM PDT 24
Finished Jul 01 10:51:13 AM PDT 24
Peak memory 196436 kb
Host smart-88c5d5ee-6486-4784-aa6e-ccbe28418cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755553656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.755553656
Directory /workspace/9.aon_timer_smoke/latest
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