Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	28899	1		T1	344		T2	12		T3	12
bark[1]	441	1		T5	7		T40	76		T24	21
bark[2]	528	1		T14	21		T32	35		T24	14
bark[3]	931	1		T40	26		T41	21		T25	112
bark[4]	576	1		T8	14		T31	270		T88	14
bark[5]	271	1		T21	26		T24	30		T117	35
bark[6]	201	1		T12	21		T48	26		T69	21
bark[7]	236	1		T8	21		T92	14		T93	21
bark[8]	547	1		T97	21		T140	21		T71	21
bark[9]	164	1		T6	14		T105	26		T106	14
bark[10]	186	1		T36	39		T87	21		T94	21
bark[11]	408	1		T42	21		T105	21		T107	14
bark[12]	338	1		T104	14		T70	21		T140	21
bark[13]	521	1		T14	30		T106	21		T160	219
bark[14]	769	1		T20	30		T149	30		T166	21
bark[15]	425	1		T25	234		T97	21		T152	42
bark[16]	598	1		T5	95		T14	21		T32	7
bark[17]	237	1		T173	14		T140	21		T102	26
bark[18]	307	1		T5	21		T10	83		T27	21
bark[19]	262	1		T119	21		T99	21		T121	14
bark[20]	653	1		T5	153		T123	14		T46	21
bark[21]	393	1		T10	21		T45	14		T42	21
bark[22]	902	1		T14	21		T32	21		T139	14
bark[23]	272	1		T1	47		T23	14		T27	71
bark[24]	316	1		T31	7		T20	26		T105	60
bark[25]	1224	1		T32	187		T77	21		T46	200
bark[26]	1021	1		T1	30		T5	74		T8	108
bark[27]	664	1		T14	40		T40	21		T117	61
bark[28]	535	1		T4	14		T12	21		T14	42
bark[29]	208	1		T149	44		T176	14		T166	21
bark[30]	1067	1		T30	14		T25	35		T70	51
bark[31]	480	1		T10	30		T12	78		T97	30
bark_0	4412	1		T1	103		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	28797	1		T1	335		T2	11		T3	11
bite[1]	965	1		T5	122		T10	21		T25	233
bite[2]	816	1		T30	13		T119	30		T71	21
bite[3]	624	1		T5	73		T149	44		T97	21
bite[4]	217	1		T5	6		T105	21		T140	21
bite[5]	370	1		T27	70		T160	116		T96	30
bite[6]	132	1		T92	13		T119	21		T156	13
bite[7]	335	1		T42	21		T166	21		T87	21
bite[8]	191	1		T1	46		T31	4		T40	26
bite[9]	462	1		T75	13		T46	21		T140	21
bite[10]	857	1		T40	96		T105	26		T87	305
bite[11]	279	1		T10	82		T104	13		T24	21
bite[12]	522	1		T5	94		T12	21		T20	30
bite[13]	447	1		T1	30		T8	13		T12	21
bite[14]	594	1		T4	13		T6	13		T32	186
bite[15]	885	1		T8	129		T42	21		T75	21
bite[16]	533	1		T32	6		T117	61		T123	13
bite[17]	584	1		T31	6		T117	35		T140	21
bite[18]	352	1		T12	78		T24	30		T119	21
bite[19]	413	1		T14	21		T40	274		T177	13
bite[20]	366	1		T110	44		T125	13		T87	225
bite[21]	331	1		T14	30		T32	21		T25	35
bite[22]	605	1		T14	42		T31	21		T27	21
bite[23]	413	1		T14	21		T41	25		T157	13
bite[24]	333	1		T14	40		T171	13		T70	26
bite[25]	164	1		T45	13		T106	13		T121	13
bite[26]	517	1		T21	25		T71	24		T163	13
bite[27]	398	1		T77	21		T139	13		T46	6
bite[28]	354	1		T5	21		T32	34		T21	26
bite[29]	950	1		T31	272		T41	21		T20	26
bite[30]	478	1		T5	30		T10	30		T140	21
bite[31]	816	1		T77	21		T68	154		T47	351
bite_0	4892	1		T1	113		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	48992	1		T1	524		T2	19		T3	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1387	1		T1	59		T31	126		T40	67
prescale[1]	756	1		T14	9		T40	2		T42	27
prescale[2]	508	1		T42	80		T27	20		T46	63
prescale[3]	1279	1		T5	62		T8	19		T32	58
prescale[4]	565	1		T5	40		T32	28		T40	118
prescale[5]	752	1		T1	130		T10	2		T36	42
prescale[6]	955	1		T1	9		T32	80		T21	2
prescale[7]	688	1		T32	19		T24	38		T77	19
prescale[8]	573	1		T9	9		T10	9		T12	38
prescale[9]	872	1		T5	41		T40	2		T24	73
prescale[10]	942	1		T1	2		T5	2		T27	79
prescale[11]	1073	1		T5	67		T21	19		T24	28
prescale[12]	561	1		T5	37		T8	19		T31	41
prescale[13]	640	1		T5	19		T40	29		T27	2
prescale[14]	837	1		T5	19		T12	41		T40	76
prescale[15]	557	1		T1	28		T3	9		T10	2
prescale[16]	830	1		T1	4		T5	20		T11	9
prescale[17]	787	1		T1	2		T14	19		T77	9
prescale[18]	874	1		T8	23		T32	28		T40	2
prescale[19]	1016	1		T31	40		T21	76		T149	19
prescale[20]	964	1		T5	63		T8	77		T36	32
prescale[21]	595	1		T1	2		T5	50		T10	42
prescale[22]	705	1		T10	40		T32	21		T42	29
prescale[23]	786	1		T32	55		T184	9		T40	2
prescale[24]	616	1		T32	19		T40	143		T42	65
prescale[25]	1045	1		T5	20		T14	23		T36	19
prescale[26]	914	1		T1	2		T2	9		T5	2
prescale[27]	628	1		T14	41		T25	2		T185	9
prescale[28]	970	1		T41	62		T42	66		T20	54
prescale[29]	521	1		T10	60		T32	37		T21	2
prescale[30]	1027	1		T10	37		T43	9		T40	45
prescale[31]	599	1		T5	37		T13	9		T31	2
prescale_0	23170	1		T1	286		T2	10		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36071	1		T1	384		T2	9		T3	9
auto[1]	12921	1		T1	140		T2	10		T3	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	48992	1		T1	524		T2	19		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	28818	1		T1	241		T2	14		T3	14
wkup[1]	134	1		T46	8		T140	21		T103	21
wkup[2]	323	1		T21	15		T24	30		T27	21
wkup[3]	171	1		T14	21		T27	21		T46	21
wkup[4]	218	1		T31	30		T25	21		T77	42
wkup[5]	264	1		T5	8		T40	63		T127	15
wkup[6]	127	1		T42	21		T21	35		T159	30
wkup[7]	291	1		T5	8		T31	8		T21	21
wkup[8]	258	1		T5	21		T20	26		T171	15
wkup[9]	295	1		T5	21		T25	21		T27	21
wkup[10]	466	1		T41	21		T77	21		T140	30
wkup[11]	270	1		T152	21		T119	21		T71	21
wkup[12]	354	1		T5	21		T40	21		T41	21
wkup[13]	215	1		T10	21		T21	26		T27	21
wkup[14]	230	1		T1	44		T149	30		T140	21
wkup[15]	450	1		T5	30		T31	21		T149	26
wkup[16]	415	1		T1	21		T5	21		T30	15
wkup[17]	306	1		T10	21		T14	21		T104	15
wkup[18]	131	1		T27	21		T135	39		T87	36
wkup[19]	198	1		T5	21		T14	21		T40	31
wkup[20]	265	1		T12	21		T36	21		T160	21
wkup[21]	341	1		T4	15		T40	21		T25	21
wkup[22]	135	1		T12	21		T173	15		T97	21
wkup[23]	216	1		T40	21		T45	15		T42	21
wkup[24]	280	1		T77	30		T119	42		T69	26
wkup[25]	350	1		T8	30		T41	21		T119	21
wkup[26]	289	1		T5	21		T10	30		T31	21
wkup[27]	275	1		T42	21		T106	26		T119	21
wkup[28]	313	1		T31	51		T27	21		T105	21
wkup[29]	207	1		T25	21		T77	21		T160	24
wkup[30]	319	1		T1	21		T41	15		T21	42
wkup[31]	235	1		T5	49		T14	21		T40	21
wkup[32]	310	1		T5	8		T10	21		T42	26
wkup[33]	207	1		T140	15		T71	21		T153	21
wkup[34]	359	1		T1	21		T31	21		T42	15
wkup[35]	233	1		T1	30		T5	21		T10	21
wkup[36]	328	1		T31	6		T27	26		T105	26
wkup[37]	414	1		T25	35		T77	21		T119	21
wkup[38]	155	1		T119	26		T93	21		T48	30
wkup[39]	281	1		T5	8		T20	30		T152	21
wkup[40]	172	1		T42	21		T117	35		T161	30
wkup[41]	186	1		T97	30		T119	30		T83	21
wkup[42]	367	1		T40	77		T24	15		T99	30
wkup[43]	366	1		T32	8		T40	21		T140	21
wkup[44]	250	1		T68	26		T160	21		T150	21
wkup[45]	240	1		T8	15		T27	21		T160	21
wkup[46]	272	1		T14	30		T119	21		T47	53
wkup[47]	341	1		T8	21		T32	50		T41	30
wkup[48]	327	1		T14	21		T99	39		T121	15
wkup[49]	278	1		T8	21		T31	21		T40	26
wkup[50]	131	1		T8	21		T12	21		T32	21
wkup[51]	337	1		T1	21		T31	21		T25	35
wkup[52]	258	1		T6	15		T40	21		T70	26
wkup[53]	200	1		T1	21		T31	21		T112	21
wkup[54]	128	1		T47	21		T160	21		T87	15
wkup[55]	114	1		T47	21		T83	21		T147	21
wkup[56]	344	1		T12	21		T40	21		T27	21
wkup[57]	290	1		T1	21		T40	15		T42	21
wkup[58]	277	1		T42	21		T46	21		T160	26
wkup[59]	307	1		T42	21		T27	21		T75	21
wkup[60]	173	1		T27	8		T149	30		T68	21
wkup[61]	213	1		T14	21		T106	21		T153	21
wkup[62]	247	1		T140	21		T114	21		T48	21
wkup[63]	302	1		T10	21		T32	21		T40	21
wkup_0	3426	1		T1	83		T2	5		T3	5