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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.08 99.33 93.67 100.00 98.40 99.51 49.59


Total test records in report: 418
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T274 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3306918433 Jul 01 04:33:02 PM PDT 24 Jul 01 04:33:11 PM PDT 24 456795471 ps
T275 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3180495799 Jul 01 04:32:49 PM PDT 24 Jul 01 04:33:02 PM PDT 24 567936053 ps
T276 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1568199455 Jul 01 04:33:06 PM PDT 24 Jul 01 04:33:14 PM PDT 24 506611328 ps
T277 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.261206893 Jul 01 04:32:36 PM PDT 24 Jul 01 04:32:52 PM PDT 24 592112681 ps
T37 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.813089528 Jul 01 04:32:28 PM PDT 24 Jul 01 04:32:53 PM PDT 24 8317281412 ps
T38 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2081449870 Jul 01 04:32:53 PM PDT 24 Jul 01 04:33:06 PM PDT 24 10129027298 ps
T278 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.783304655 Jul 01 04:32:35 PM PDT 24 Jul 01 04:32:50 PM PDT 24 504459569 ps
T279 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2419111524 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:03 PM PDT 24 466086772 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2822401101 Jul 01 04:32:52 PM PDT 24 Jul 01 04:33:03 PM PDT 24 560583042 ps
T280 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1803742506 Jul 01 04:33:02 PM PDT 24 Jul 01 04:33:12 PM PDT 24 430808085 ps
T50 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1106084713 Jul 01 04:32:47 PM PDT 24 Jul 01 04:33:00 PM PDT 24 436000849 ps
T281 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1679192441 Jul 01 04:32:44 PM PDT 24 Jul 01 04:32:59 PM PDT 24 502980169 ps
T39 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2397319535 Jul 01 04:32:51 PM PDT 24 Jul 01 04:33:07 PM PDT 24 8686213559 ps
T282 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1460397946 Jul 01 04:32:42 PM PDT 24 Jul 01 04:32:56 PM PDT 24 470280623 ps
T283 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3789729081 Jul 01 04:33:10 PM PDT 24 Jul 01 04:33:17 PM PDT 24 380634051 ps
T284 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.54860366 Jul 01 04:32:42 PM PDT 24 Jul 01 04:32:56 PM PDT 24 604578899 ps
T285 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1294221541 Jul 01 04:32:39 PM PDT 24 Jul 01 04:32:54 PM PDT 24 367414834 ps
T63 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.528611964 Jul 01 04:32:41 PM PDT 24 Jul 01 04:32:56 PM PDT 24 1468028648 ps
T64 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4066011868 Jul 01 04:33:02 PM PDT 24 Jul 01 04:33:10 PM PDT 24 1589391447 ps
T286 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2728741673 Jul 01 04:33:04 PM PDT 24 Jul 01 04:33:13 PM PDT 24 419491109 ps
T187 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1122607950 Jul 01 04:32:34 PM PDT 24 Jul 01 04:32:59 PM PDT 24 7003504936 ps
T287 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2664898800 Jul 01 04:33:19 PM PDT 24 Jul 01 04:33:21 PM PDT 24 328011536 ps
T288 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2533043720 Jul 01 04:33:02 PM PDT 24 Jul 01 04:33:12 PM PDT 24 518588195 ps
T289 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4203018423 Jul 01 04:32:28 PM PDT 24 Jul 01 04:32:48 PM PDT 24 411696816 ps
T290 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.110345865 Jul 01 04:33:02 PM PDT 24 Jul 01 04:33:11 PM PDT 24 331993468 ps
T65 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3846992913 Jul 01 04:32:51 PM PDT 24 Jul 01 04:33:04 PM PDT 24 1078384338 ps
T291 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2481771266 Jul 01 04:33:09 PM PDT 24 Jul 01 04:33:16 PM PDT 24 530535722 ps
T66 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.843195961 Jul 01 04:32:52 PM PDT 24 Jul 01 04:33:04 PM PDT 24 1642105509 ps
T51 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1204102633 Jul 01 04:32:27 PM PDT 24 Jul 01 04:32:45 PM PDT 24 612259282 ps
T292 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1399733918 Jul 01 04:32:57 PM PDT 24 Jul 01 04:33:07 PM PDT 24 407073256 ps
T183 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1624401523 Jul 01 04:32:57 PM PDT 24 Jul 01 04:33:20 PM PDT 24 8635935276 ps
T52 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.864511857 Jul 01 04:33:00 PM PDT 24 Jul 01 04:33:09 PM PDT 24 286898349 ps
T293 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1071766629 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:02 PM PDT 24 320660528 ps
T294 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2652650231 Jul 01 04:32:33 PM PDT 24 Jul 01 04:32:51 PM PDT 24 517607487 ps
T295 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3358496503 Jul 01 04:33:09 PM PDT 24 Jul 01 04:33:17 PM PDT 24 468841920 ps
T296 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2366568343 Jul 01 04:32:40 PM PDT 24 Jul 01 04:32:55 PM PDT 24 537667697 ps
T297 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3225936320 Jul 01 04:33:10 PM PDT 24 Jul 01 04:33:17 PM PDT 24 521163551 ps
T182 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2859479620 Jul 01 04:32:36 PM PDT 24 Jul 01 04:32:58 PM PDT 24 4194670117 ps
T298 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3372356019 Jul 01 04:32:43 PM PDT 24 Jul 01 04:32:56 PM PDT 24 442045872 ps
T299 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3033211524 Jul 01 04:32:59 PM PDT 24 Jul 01 04:33:08 PM PDT 24 503465844 ps
T300 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2719578088 Jul 01 04:32:40 PM PDT 24 Jul 01 04:32:55 PM PDT 24 393608751 ps
T301 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3339674664 Jul 01 04:32:40 PM PDT 24 Jul 01 04:32:55 PM PDT 24 555114856 ps
T302 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.707371496 Jul 01 04:32:58 PM PDT 24 Jul 01 04:33:12 PM PDT 24 4333912443 ps
T54 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.75723030 Jul 01 04:32:54 PM PDT 24 Jul 01 04:33:05 PM PDT 24 319903893 ps
T303 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3870936856 Jul 01 04:32:48 PM PDT 24 Jul 01 04:33:00 PM PDT 24 306691110 ps
T304 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1439834245 Jul 01 04:32:55 PM PDT 24 Jul 01 04:33:13 PM PDT 24 4399952404 ps
T305 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3785744216 Jul 01 04:33:10 PM PDT 24 Jul 01 04:33:17 PM PDT 24 536313722 ps
T306 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.680833579 Jul 01 04:32:54 PM PDT 24 Jul 01 04:33:04 PM PDT 24 607071125 ps
T307 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3196979018 Jul 01 04:32:27 PM PDT 24 Jul 01 04:32:45 PM PDT 24 318258402 ps
T67 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1679985825 Jul 01 04:32:49 PM PDT 24 Jul 01 04:33:03 PM PDT 24 1642711538 ps
T308 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2134127699 Jul 01 04:32:56 PM PDT 24 Jul 01 04:33:12 PM PDT 24 7263604874 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3865310366 Jul 01 04:32:25 PM PDT 24 Jul 01 04:32:45 PM PDT 24 1500978317 ps
T310 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2942033670 Jul 01 04:32:39 PM PDT 24 Jul 01 04:32:55 PM PDT 24 4444532050 ps
T311 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2175571537 Jul 01 04:33:05 PM PDT 24 Jul 01 04:33:13 PM PDT 24 552503517 ps
T312 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2073474870 Jul 01 04:32:58 PM PDT 24 Jul 01 04:33:09 PM PDT 24 470106797 ps
T313 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2210638328 Jul 01 04:33:18 PM PDT 24 Jul 01 04:33:21 PM PDT 24 539059007 ps
T314 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4146420469 Jul 01 04:33:10 PM PDT 24 Jul 01 04:33:17 PM PDT 24 375494003 ps
T315 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1390621377 Jul 01 04:32:52 PM PDT 24 Jul 01 04:33:15 PM PDT 24 8320741675 ps
T316 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3625263059 Jul 01 04:32:54 PM PDT 24 Jul 01 04:33:05 PM PDT 24 500031326 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2795570408 Jul 01 04:32:40 PM PDT 24 Jul 01 04:32:56 PM PDT 24 1545603694 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.648300142 Jul 01 04:32:43 PM PDT 24 Jul 01 04:32:56 PM PDT 24 454509764 ps
T319 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.822742088 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:04 PM PDT 24 2539348677 ps
T320 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2461803825 Jul 01 04:33:03 PM PDT 24 Jul 01 04:33:12 PM PDT 24 465999791 ps
T321 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1938849126 Jul 01 04:32:40 PM PDT 24 Jul 01 04:32:59 PM PDT 24 2308188856 ps
T322 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.453591820 Jul 01 04:33:05 PM PDT 24 Jul 01 04:33:14 PM PDT 24 506723869 ps
T323 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3811898246 Jul 01 04:32:53 PM PDT 24 Jul 01 04:33:07 PM PDT 24 4393164591 ps
T324 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1561193559 Jul 01 04:32:39 PM PDT 24 Jul 01 04:32:54 PM PDT 24 578360401 ps
T325 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2289145496 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:03 PM PDT 24 377857336 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.825199204 Jul 01 04:32:46 PM PDT 24 Jul 01 04:32:59 PM PDT 24 346136497 ps
T327 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3567611279 Jul 01 04:33:01 PM PDT 24 Jul 01 04:33:10 PM PDT 24 550945273 ps
T328 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2726124311 Jul 01 04:32:40 PM PDT 24 Jul 01 04:32:55 PM PDT 24 1644585269 ps
T329 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1713129347 Jul 01 04:33:08 PM PDT 24 Jul 01 04:33:17 PM PDT 24 2438854301 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3255399209 Jul 01 04:32:35 PM PDT 24 Jul 01 04:32:50 PM PDT 24 304457157 ps
T331 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1573035230 Jul 01 04:32:47 PM PDT 24 Jul 01 04:33:19 PM PDT 24 14010736152 ps
T332 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1308220158 Jul 01 04:33:07 PM PDT 24 Jul 01 04:33:15 PM PDT 24 288393438 ps
T53 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1175862856 Jul 01 04:32:40 PM PDT 24 Jul 01 04:33:01 PM PDT 24 7336889891 ps
T333 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1351145112 Jul 01 04:32:39 PM PDT 24 Jul 01 04:32:54 PM PDT 24 279917963 ps
T334 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4214230391 Jul 01 04:32:47 PM PDT 24 Jul 01 04:33:00 PM PDT 24 902160207 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2980027281 Jul 01 04:32:37 PM PDT 24 Jul 01 04:32:55 PM PDT 24 6996911334 ps
T336 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.50724201 Jul 01 04:32:52 PM PDT 24 Jul 01 04:33:05 PM PDT 24 490153011 ps
T337 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4042266902 Jul 01 04:32:45 PM PDT 24 Jul 01 04:32:58 PM PDT 24 519244791 ps
T338 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1538953947 Jul 01 04:32:48 PM PDT 24 Jul 01 04:33:00 PM PDT 24 428269815 ps
T339 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.155044244 Jul 01 04:32:48 PM PDT 24 Jul 01 04:33:01 PM PDT 24 1570386866 ps
T340 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.344683345 Jul 01 04:33:09 PM PDT 24 Jul 01 04:33:17 PM PDT 24 380321908 ps
T341 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3167562765 Jul 01 04:32:49 PM PDT 24 Jul 01 04:33:01 PM PDT 24 494787985 ps
T342 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1287530952 Jul 01 04:33:03 PM PDT 24 Jul 01 04:33:12 PM PDT 24 489072244 ps
T343 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3307813634 Jul 01 04:32:29 PM PDT 24 Jul 01 04:32:49 PM PDT 24 717164333 ps
T344 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2546801461 Jul 01 04:33:11 PM PDT 24 Jul 01 04:33:18 PM PDT 24 435637059 ps
T345 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3013682745 Jul 01 04:33:07 PM PDT 24 Jul 01 04:33:15 PM PDT 24 436048843 ps
T346 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.826835322 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:04 PM PDT 24 387529147 ps
T347 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4056164903 Jul 01 04:32:49 PM PDT 24 Jul 01 04:33:02 PM PDT 24 367343154 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.250307037 Jul 01 04:32:28 PM PDT 24 Jul 01 04:32:46 PM PDT 24 357433171 ps
T349 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.950585094 Jul 01 04:33:08 PM PDT 24 Jul 01 04:33:15 PM PDT 24 499769517 ps
T350 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4114413694 Jul 01 04:33:08 PM PDT 24 Jul 01 04:33:16 PM PDT 24 299220935 ps
T351 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3282431312 Jul 01 04:32:55 PM PDT 24 Jul 01 04:33:06 PM PDT 24 384256636 ps
T352 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3073471243 Jul 01 04:33:08 PM PDT 24 Jul 01 04:33:16 PM PDT 24 473480931 ps
T353 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.558490207 Jul 01 04:33:09 PM PDT 24 Jul 01 04:33:17 PM PDT 24 545830411 ps
T354 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.34532575 Jul 01 04:32:58 PM PDT 24 Jul 01 04:33:09 PM PDT 24 835786728 ps
T355 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1120462028 Jul 01 04:33:09 PM PDT 24 Jul 01 04:33:17 PM PDT 24 468099652 ps
T356 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3262882039 Jul 01 04:32:42 PM PDT 24 Jul 01 04:32:56 PM PDT 24 447097180 ps
T357 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3318853078 Jul 01 04:32:28 PM PDT 24 Jul 01 04:32:47 PM PDT 24 781785870 ps
T358 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4106836379 Jul 01 04:33:01 PM PDT 24 Jul 01 04:33:10 PM PDT 24 302410506 ps
T359 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2785710081 Jul 01 04:32:49 PM PDT 24 Jul 01 04:33:03 PM PDT 24 484877073 ps
T360 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.497156848 Jul 01 04:32:59 PM PDT 24 Jul 01 04:33:09 PM PDT 24 534353074 ps
T361 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3022221891 Jul 01 04:32:48 PM PDT 24 Jul 01 04:33:02 PM PDT 24 359889918 ps
T362 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2228773958 Jul 01 04:32:57 PM PDT 24 Jul 01 04:33:07 PM PDT 24 501211693 ps
T363 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.84575483 Jul 01 04:32:41 PM PDT 24 Jul 01 04:32:56 PM PDT 24 405927370 ps
T364 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1096721061 Jul 01 04:32:53 PM PDT 24 Jul 01 04:33:04 PM PDT 24 440043400 ps
T365 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2049574728 Jul 01 04:32:48 PM PDT 24 Jul 01 04:33:00 PM PDT 24 327696921 ps
T366 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3209462826 Jul 01 04:33:12 PM PDT 24 Jul 01 04:33:19 PM PDT 24 506052421 ps
T367 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.244465406 Jul 01 04:32:43 PM PDT 24 Jul 01 04:32:56 PM PDT 24 428676750 ps
T368 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1397645746 Jul 01 04:32:44 PM PDT 24 Jul 01 04:32:59 PM PDT 24 644146592 ps
T369 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1427118269 Jul 01 04:32:57 PM PDT 24 Jul 01 04:33:07 PM PDT 24 299626709 ps
T55 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3861416199 Jul 01 04:32:56 PM PDT 24 Jul 01 04:33:07 PM PDT 24 474764136 ps
T370 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3265012871 Jul 01 04:32:53 PM PDT 24 Jul 01 04:33:05 PM PDT 24 1536288572 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1295696778 Jul 01 04:32:55 PM PDT 24 Jul 01 04:33:11 PM PDT 24 8489917717 ps
T372 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2597365751 Jul 01 04:33:07 PM PDT 24 Jul 01 04:33:18 PM PDT 24 8349305523 ps
T373 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.981302962 Jul 01 04:33:02 PM PDT 24 Jul 01 04:33:12 PM PDT 24 1195139609 ps
T374 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.31206528 Jul 01 04:32:59 PM PDT 24 Jul 01 04:33:09 PM PDT 24 478537720 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1032061347 Jul 01 04:32:35 PM PDT 24 Jul 01 04:32:51 PM PDT 24 530437122 ps
T375 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2564830236 Jul 01 04:32:43 PM PDT 24 Jul 01 04:32:56 PM PDT 24 579003970 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2209289579 Jul 01 04:32:27 PM PDT 24 Jul 01 04:32:45 PM PDT 24 476597249 ps
T377 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2303131257 Jul 01 04:33:03 PM PDT 24 Jul 01 04:33:13 PM PDT 24 1470617839 ps
T57 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2395569826 Jul 01 04:32:47 PM PDT 24 Jul 01 04:33:01 PM PDT 24 647298220 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1036613514 Jul 01 04:32:27 PM PDT 24 Jul 01 04:32:46 PM PDT 24 407134195 ps
T379 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1528204937 Jul 01 04:32:57 PM PDT 24 Jul 01 04:33:08 PM PDT 24 2147014106 ps
T380 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.4090922572 Jul 01 04:33:08 PM PDT 24 Jul 01 04:33:16 PM PDT 24 442899837 ps
T381 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1403167256 Jul 01 04:33:09 PM PDT 24 Jul 01 04:33:17 PM PDT 24 418744753 ps
T382 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1456949917 Jul 01 04:32:52 PM PDT 24 Jul 01 04:33:04 PM PDT 24 468567020 ps
T383 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3271393231 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:02 PM PDT 24 366620650 ps
T384 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3861903695 Jul 01 04:32:28 PM PDT 24 Jul 01 04:32:47 PM PDT 24 289223471 ps
T385 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1318472037 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:06 PM PDT 24 4510691173 ps
T386 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2112455620 Jul 01 04:33:00 PM PDT 24 Jul 01 04:33:10 PM PDT 24 363320893 ps
T387 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3320142448 Jul 01 04:32:28 PM PDT 24 Jul 01 04:32:49 PM PDT 24 8007170586 ps
T388 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1410315570 Jul 01 04:32:52 PM PDT 24 Jul 01 04:33:04 PM PDT 24 513167581 ps
T389 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3851952855 Jul 01 04:32:49 PM PDT 24 Jul 01 04:33:02 PM PDT 24 469682541 ps
T390 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.798310446 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:03 PM PDT 24 1141421508 ps
T58 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1046419558 Jul 01 04:32:46 PM PDT 24 Jul 01 04:32:59 PM PDT 24 430396424 ps
T59 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3149432833 Jul 01 04:32:28 PM PDT 24 Jul 01 04:32:47 PM PDT 24 601007043 ps
T391 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.738116344 Jul 01 04:32:58 PM PDT 24 Jul 01 04:33:09 PM PDT 24 504134165 ps
T392 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4166140632 Jul 01 04:33:07 PM PDT 24 Jul 01 04:33:15 PM PDT 24 498035158 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3342712606 Jul 01 04:32:30 PM PDT 24 Jul 01 04:32:52 PM PDT 24 4427833659 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1114825406 Jul 01 04:32:28 PM PDT 24 Jul 01 04:32:46 PM PDT 24 379095591 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1083746966 Jul 01 04:32:45 PM PDT 24 Jul 01 04:33:04 PM PDT 24 4189834431 ps
T396 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2532312631 Jul 01 04:32:53 PM PDT 24 Jul 01 04:33:09 PM PDT 24 4265747307 ps
T397 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1161338385 Jul 01 04:32:37 PM PDT 24 Jul 01 04:32:53 PM PDT 24 563427901 ps
T398 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2399346078 Jul 01 04:32:57 PM PDT 24 Jul 01 04:33:09 PM PDT 24 8516164521 ps
T399 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.172173412 Jul 01 04:33:07 PM PDT 24 Jul 01 04:33:15 PM PDT 24 276222783 ps
T400 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2958023620 Jul 01 04:32:49 PM PDT 24 Jul 01 04:33:02 PM PDT 24 879564221 ps
T401 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3959322169 Jul 01 04:32:36 PM PDT 24 Jul 01 04:32:53 PM PDT 24 4913669442 ps
T402 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3428048487 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:04 PM PDT 24 544883693 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.485160080 Jul 01 04:32:35 PM PDT 24 Jul 01 04:32:51 PM PDT 24 489498159 ps
T404 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1555798052 Jul 01 04:32:58 PM PDT 24 Jul 01 04:33:09 PM PDT 24 384440915 ps
T60 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3681353925 Jul 01 04:32:43 PM PDT 24 Jul 01 04:32:57 PM PDT 24 1100731016 ps
T405 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4166947367 Jul 01 04:33:00 PM PDT 24 Jul 01 04:33:09 PM PDT 24 279363018 ps
T406 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1135263560 Jul 01 04:32:39 PM PDT 24 Jul 01 04:32:54 PM PDT 24 636183197 ps
T407 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.948196986 Jul 01 04:32:39 PM PDT 24 Jul 01 04:32:53 PM PDT 24 479525222 ps
T408 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.966149102 Jul 01 04:33:10 PM PDT 24 Jul 01 04:33:17 PM PDT 24 302349908 ps
T409 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2029652125 Jul 01 04:33:02 PM PDT 24 Jul 01 04:33:13 PM PDT 24 784896088 ps
T410 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2551472051 Jul 01 04:32:41 PM PDT 24 Jul 01 04:32:55 PM PDT 24 790327778 ps
T411 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3165234506 Jul 01 04:32:55 PM PDT 24 Jul 01 04:33:09 PM PDT 24 8416546864 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.837726019 Jul 01 04:32:34 PM PDT 24 Jul 01 04:32:51 PM PDT 24 2484082314 ps
T413 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.902078046 Jul 01 04:32:50 PM PDT 24 Jul 01 04:33:02 PM PDT 24 422579582 ps
T414 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.751488969 Jul 01 04:32:35 PM PDT 24 Jul 01 04:32:51 PM PDT 24 2383239568 ps
T415 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.153493057 Jul 01 04:32:55 PM PDT 24 Jul 01 04:33:06 PM PDT 24 438919298 ps
T416 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3120137459 Jul 01 04:32:43 PM PDT 24 Jul 01 04:32:56 PM PDT 24 523694340 ps
T417 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2247293741 Jul 01 04:33:06 PM PDT 24 Jul 01 04:33:15 PM PDT 24 422456816 ps
T418 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3431580509 Jul 01 04:33:10 PM PDT 24 Jul 01 04:33:17 PM PDT 24 475387827 ps

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3191672658
Short name T5
Test name
Test status
Simulation time 930269546074 ps
CPU time 658.02 seconds
Started Jul 01 04:33:56 PM PDT 24
Finished Jul 01 04:44:57 PM PDT 24
Peak memory 214080 kb
Host smart-33c52ede-d0db-448f-8223-1f7e1c69d360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191672658 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3191672658
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.528261511
Short name T31
Test name
Test status
Simulation time 80511863362 ps
CPU time 246.48 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:38:27 PM PDT 24
Peak memory 206508 kb
Host smart-14d42bf4-4eb5-4e52-b8c6-80ae343b5a22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528261511 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.528261511
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2418614962
Short name T33
Test name
Test status
Simulation time 469595241 ps
CPU time 1.3 seconds
Started Jul 01 04:32:53 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 193304 kb
Host smart-98cf9b1d-ae14-46d3-8d89-ad4b47be5010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418614962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2418614962
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2527099780
Short name T8
Test name
Test status
Simulation time 43596365760 ps
CPU time 6.23 seconds
Started Jul 01 04:33:47 PM PDT 24
Finished Jul 01 04:33:55 PM PDT 24
Peak memory 192680 kb
Host smart-a299d02d-07e3-4227-8eca-c54d8c6671d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527099780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2527099780
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1565156999
Short name T16
Test name
Test status
Simulation time 8339755169 ps
CPU time 4.17 seconds
Started Jul 01 04:33:39 PM PDT 24
Finished Jul 01 04:33:46 PM PDT 24
Peak memory 215676 kb
Host smart-4b6d0602-fce9-47d2-9412-44c18817d7bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565156999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1565156999
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2616328070
Short name T87
Test name
Test status
Simulation time 232132253663 ps
CPU time 543.51 seconds
Started Jul 01 04:34:19 PM PDT 24
Finished Jul 01 04:43:32 PM PDT 24
Peak memory 204860 kb
Host smart-1417042d-70cc-436e-8ee0-bd27308e6f3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616328070 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2616328070
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3908926449
Short name T83
Test name
Test status
Simulation time 66900285396 ps
CPU time 611.91 seconds
Started Jul 01 04:34:07 PM PDT 24
Finished Jul 01 04:44:24 PM PDT 24
Peak memory 203904 kb
Host smart-7f16b24e-2cd6-410d-a224-893ef1a8f0db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908926449 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3908926449
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3502541418
Short name T120
Test name
Test status
Simulation time 139175324987 ps
CPU time 585.55 seconds
Started Jul 01 04:33:47 PM PDT 24
Finished Jul 01 04:43:34 PM PDT 24
Peak memory 204900 kb
Host smart-e3bc080c-cc52-409f-9d36-2c4be338cf96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502541418 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3502541418
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3348340346
Short name T119
Test name
Test status
Simulation time 75595998306 ps
CPU time 397.68 seconds
Started Jul 01 04:33:49 PM PDT 24
Finished Jul 01 04:40:28 PM PDT 24
Peak memory 213804 kb
Host smart-0bef9a46-6fb7-4948-9606-d36ebf730db7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348340346 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3348340346
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2964389027
Short name T79
Test name
Test status
Simulation time 285802266649 ps
CPU time 497.84 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:42:37 PM PDT 24
Peak memory 213868 kb
Host smart-45a76731-6be5-4169-8daa-1237f302f326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964389027 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2964389027
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3417957605
Short name T132
Test name
Test status
Simulation time 82593674494 ps
CPU time 619.63 seconds
Started Jul 01 04:34:07 PM PDT 24
Finished Jul 01 04:44:33 PM PDT 24
Peak memory 213812 kb
Host smart-f1f12b55-a402-4297-842b-f9ef26067368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417957605 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3417957605
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1668068532
Short name T94
Test name
Test status
Simulation time 532537605827 ps
CPU time 462.86 seconds
Started Jul 01 04:33:36 PM PDT 24
Finished Jul 01 04:41:21 PM PDT 24
Peak memory 206480 kb
Host smart-c2e603d9-19c5-48b4-976a-7ae1e14d0580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668068532 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1668068532
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2072152215
Short name T80
Test name
Test status
Simulation time 33533513554 ps
CPU time 244.93 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:38:23 PM PDT 24
Peak memory 214052 kb
Host smart-b6ebea92-29c2-4e81-8320-ceb9014255f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072152215 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2072152215
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1826702152
Short name T74
Test name
Test status
Simulation time 88611576109 ps
CPU time 126.96 seconds
Started Jul 01 04:33:58 PM PDT 24
Finished Jul 01 04:36:08 PM PDT 24
Peak memory 192744 kb
Host smart-7666342c-b37e-49f9-ac2c-50600be4be97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826702152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1826702152
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1785111080
Short name T84
Test name
Test status
Simulation time 85223682187 ps
CPU time 136.86 seconds
Started Jul 01 04:33:56 PM PDT 24
Finished Jul 01 04:36:16 PM PDT 24
Peak memory 192664 kb
Host smart-15abb861-ed89-4064-bce5-4a247c3f4b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785111080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1785111080
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2359474916
Short name T42
Test name
Test status
Simulation time 143790607970 ps
CPU time 222.06 seconds
Started Jul 01 04:33:58 PM PDT 24
Finished Jul 01 04:37:44 PM PDT 24
Peak memory 199368 kb
Host smart-3151420f-1206-4dbc-bae0-66b0c568e352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359474916 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2359474916
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3691341874
Short name T40
Test name
Test status
Simulation time 178528803941 ps
CPU time 474.92 seconds
Started Jul 01 04:33:40 PM PDT 24
Finished Jul 01 04:41:37 PM PDT 24
Peak memory 210804 kb
Host smart-cf604022-32ac-40a6-8844-166441262be1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691341874 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3691341874
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.937074301
Short name T101
Test name
Test status
Simulation time 189323534793 ps
CPU time 57.67 seconds
Started Jul 01 04:33:53 PM PDT 24
Finished Jul 01 04:34:53 PM PDT 24
Peak memory 192788 kb
Host smart-7a5e28ce-3d9b-4c49-a849-f5f0ebd78e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937074301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.937074301
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1662770380
Short name T27
Test name
Test status
Simulation time 57598817672 ps
CPU time 611.65 seconds
Started Jul 01 04:33:56 PM PDT 24
Finished Jul 01 04:44:10 PM PDT 24
Peak memory 206508 kb
Host smart-240f0bce-c077-4430-96e6-1a119df71349
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662770380 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1662770380
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.813089528
Short name T37
Test name
Test status
Simulation time 8317281412 ps
CPU time 7.13 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 198136 kb
Host smart-c775586d-e4c8-45ff-8e58-29c50669d71f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813089528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.813089528
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1599959732
Short name T77
Test name
Test status
Simulation time 202588927595 ps
CPU time 371.53 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:40:05 PM PDT 24
Peak memory 201716 kb
Host smart-e2c9208b-b945-46f0-860a-be1f7f1a3386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599959732 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1599959732
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1376966003
Short name T103
Test name
Test status
Simulation time 53287015147 ps
CPU time 84.3 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:35:31 PM PDT 24
Peak memory 197928 kb
Host smart-e5fc45d5-8e0f-4190-a318-e0589f3c992b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376966003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1376966003
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2734724573
Short name T115
Test name
Test status
Simulation time 213286257507 ps
CPU time 65.51 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 197808 kb
Host smart-6fc1e3c5-c195-4760-bb7e-0e08d6c0e48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734724573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2734724573
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2500561575
Short name T113
Test name
Test status
Simulation time 144152858551 ps
CPU time 208.15 seconds
Started Jul 01 04:34:15 PM PDT 24
Finished Jul 01 04:37:53 PM PDT 24
Peak memory 197924 kb
Host smart-8a2b60fc-813a-421d-910d-71d59e923104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500561575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2500561575
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.217021882
Short name T75
Test name
Test status
Simulation time 42728980467 ps
CPU time 14.74 seconds
Started Jul 01 04:34:13 PM PDT 24
Finished Jul 01 04:34:38 PM PDT 24
Peak memory 191580 kb
Host smart-1e8e3c27-2bdf-4fca-9fd1-7710bb7a76eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217021882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.217021882
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1225620083
Short name T76
Test name
Test status
Simulation time 36947262779 ps
CPU time 60.94 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:35:06 PM PDT 24
Peak memory 198124 kb
Host smart-dcfa2e3f-d669-4313-9472-3d5f344afce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225620083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1225620083
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1450429309
Short name T106
Test name
Test status
Simulation time 468952690673 ps
CPU time 356.06 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:40:15 PM PDT 24
Peak memory 197916 kb
Host smart-3e1afe37-419a-47fe-ac23-924365a774c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450429309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1450429309
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2968896105
Short name T97
Test name
Test status
Simulation time 156557031229 ps
CPU time 224.07 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:38:00 PM PDT 24
Peak memory 192532 kb
Host smart-90b9bbf0-f0aa-4f5f-b11f-d7f596bb3aa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968896105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2968896105
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.4196893203
Short name T69
Test name
Test status
Simulation time 178423746832 ps
CPU time 527.18 seconds
Started Jul 01 04:33:48 PM PDT 24
Finished Jul 01 04:42:36 PM PDT 24
Peak memory 204704 kb
Host smart-00795846-009c-47ec-94c3-5a32b06ff01d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196893203 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.4196893203
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.371805261
Short name T71
Test name
Test status
Simulation time 50773209452 ps
CPU time 382.89 seconds
Started Jul 01 04:33:46 PM PDT 24
Finished Jul 01 04:40:10 PM PDT 24
Peak memory 199932 kb
Host smart-fde54e13-1898-46ad-8d5a-f7d9c9c662e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371805261 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.371805261
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2417187010
Short name T48
Test name
Test status
Simulation time 34867307524 ps
CPU time 312.68 seconds
Started Jul 01 04:33:56 PM PDT 24
Finished Jul 01 04:39:12 PM PDT 24
Peak memory 198456 kb
Host smart-537d884a-8ab4-4ad3-8ff6-e4df19e4e09d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417187010 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2417187010
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.863633716
Short name T91
Test name
Test status
Simulation time 412124483513 ps
CPU time 156.83 seconds
Started Jul 01 04:33:50 PM PDT 24
Finished Jul 01 04:36:29 PM PDT 24
Peak memory 191764 kb
Host smart-326f55f1-a902-46fc-bbae-11a7933fad17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863633716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.863633716
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3042227140
Short name T146
Test name
Test status
Simulation time 196801118501 ps
CPU time 341.98 seconds
Started Jul 01 04:33:43 PM PDT 24
Finished Jul 01 04:39:27 PM PDT 24
Peak memory 209712 kb
Host smart-bd9995eb-1253-44a8-9f5a-877ca17f549d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042227140 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3042227140
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2044643146
Short name T160
Test name
Test status
Simulation time 176072527361 ps
CPU time 361.71 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:40:02 PM PDT 24
Peak memory 206592 kb
Host smart-26b70622-14f2-425e-867b-7235fe690a47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044643146 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2044643146
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1497949191
Short name T10
Test name
Test status
Simulation time 24752551124 ps
CPU time 180.51 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:37:07 PM PDT 24
Peak memory 206504 kb
Host smart-cee79304-cd92-4c94-bad7-d357bdc68253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497949191 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1497949191
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3898782929
Short name T99
Test name
Test status
Simulation time 319476738168 ps
CPU time 431.56 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:41:14 PM PDT 24
Peak memory 192680 kb
Host smart-1de9ccb1-52a4-40cf-9f9e-192324a15f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898782929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3898782929
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.119463186
Short name T70
Test name
Test status
Simulation time 374324595171 ps
CPU time 637.1 seconds
Started Jul 01 04:34:16 PM PDT 24
Finished Jul 01 04:45:03 PM PDT 24
Peak memory 213476 kb
Host smart-7fab71b5-98fc-4c72-8e1d-7880b3aeb30c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119463186 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.119463186
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.937893994
Short name T116
Test name
Test status
Simulation time 146952457429 ps
CPU time 94.01 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:35:35 PM PDT 24
Peak memory 197864 kb
Host smart-8ef20331-f312-4f71-a2c4-6cc310f823a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937893994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.937893994
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.655686776
Short name T12
Test name
Test status
Simulation time 58152173630 ps
CPU time 41.74 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:34:45 PM PDT 24
Peak memory 191644 kb
Host smart-c7b19a44-97c5-48ba-a895-cdbef734e1c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655686776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.655686776
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1205934151
Short name T73
Test name
Test status
Simulation time 42858698464 ps
CPU time 227.49 seconds
Started Jul 01 04:33:47 PM PDT 24
Finished Jul 01 04:37:36 PM PDT 24
Peak memory 198340 kb
Host smart-181927c4-3ab2-4f59-8e96-bb917a2a2d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205934151 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1205934151
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.4281200471
Short name T72
Test name
Test status
Simulation time 12217455656 ps
CPU time 87.1 seconds
Started Jul 01 04:34:12 PM PDT 24
Finished Jul 01 04:35:49 PM PDT 24
Peak memory 198512 kb
Host smart-95698360-ae1c-4591-bd18-0d9cb75a4591
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281200471 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.4281200471
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2803050998
Short name T93
Test name
Test status
Simulation time 91703902591 ps
CPU time 489.36 seconds
Started Jul 01 04:33:49 PM PDT 24
Finished Jul 01 04:42:00 PM PDT 24
Peak memory 203788 kb
Host smart-5cd1e4f4-97a8-4a55-ad35-404846fa9d0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803050998 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2803050998
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2744703920
Short name T14
Test name
Test status
Simulation time 97441634599 ps
CPU time 37.93 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:34:38 PM PDT 24
Peak memory 192668 kb
Host smart-24fe6b40-c28f-4fb5-9bac-31d926935427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744703920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2744703920
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.4059488049
Short name T21
Test name
Test status
Simulation time 31640645248 ps
CPU time 151.86 seconds
Started Jul 01 04:34:12 PM PDT 24
Finished Jul 01 04:36:54 PM PDT 24
Peak memory 213648 kb
Host smart-84d51259-eedc-4d7d-a1ae-6c1e254f401e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059488049 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.4059488049
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3991146682
Short name T144
Test name
Test status
Simulation time 180358202544 ps
CPU time 228.04 seconds
Started Jul 01 04:34:05 PM PDT 24
Finished Jul 01 04:37:58 PM PDT 24
Peak memory 192744 kb
Host smart-3a9a8a28-2bc9-4761-9567-ac69e76a00b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991146682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3991146682
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2939172
Short name T111
Test name
Test status
Simulation time 262971118291 ps
CPU time 145.7 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:36:34 PM PDT 24
Peak memory 192588 kb
Host smart-cdd20cd0-2023-4d9f-91d7-4dca609b51b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.2939172
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3663666779
Short name T118
Test name
Test status
Simulation time 264023258159 ps
CPU time 66.49 seconds
Started Jul 01 04:34:06 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 198260 kb
Host smart-10830157-cd0c-4f85-a5c4-1d90ce6328e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663666779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3663666779
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.812568986
Short name T68
Test name
Test status
Simulation time 61769958061 ps
CPU time 485.21 seconds
Started Jul 01 04:34:05 PM PDT 24
Finished Jul 01 04:42:15 PM PDT 24
Peak memory 201676 kb
Host smart-5f1a77e1-9b7c-429d-a932-4298f6955df8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812568986 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.812568986
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3073681399
Short name T102
Test name
Test status
Simulation time 81500964453 ps
CPU time 450.36 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:41:24 PM PDT 24
Peak memory 202608 kb
Host smart-3a0b292b-2659-44f8-b1e1-2dc1a27af774
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073681399 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3073681399
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3175318631
Short name T47
Test name
Test status
Simulation time 20807857038 ps
CPU time 125.1 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:36:23 PM PDT 24
Peak memory 206520 kb
Host smart-5b59107c-37ef-47af-86ae-6b16c310fed2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175318631 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3175318631
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1553809370
Short name T110
Test name
Test status
Simulation time 333690848179 ps
CPU time 465.29 seconds
Started Jul 01 04:33:54 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 191468 kb
Host smart-b62a7b57-8782-4a79-b907-cd896b255600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553809370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1553809370
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.4120902646
Short name T25
Test name
Test status
Simulation time 35314422905 ps
CPU time 368.68 seconds
Started Jul 01 04:33:55 PM PDT 24
Finished Jul 01 04:40:05 PM PDT 24
Peak memory 214136 kb
Host smart-debed9e3-58d2-4bc6-8d38-a722e7ae0540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120902646 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.4120902646
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3681353925
Short name T60
Test name
Test status
Simulation time 1100731016 ps
CPU time 2.11 seconds
Started Jul 01 04:32:43 PM PDT 24
Finished Jul 01 04:32:57 PM PDT 24
Peak memory 183984 kb
Host smart-aedc5da7-bfcf-4ca9-ad84-406131db8d60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681353925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3681353925
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2613419871
Short name T82
Test name
Test status
Simulation time 231370923994 ps
CPU time 85.72 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:35:18 PM PDT 24
Peak memory 192188 kb
Host smart-2c6301c8-3413-47bf-b33c-64c20ec77122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613419871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2613419871
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1394590450
Short name T86
Test name
Test status
Simulation time 49518434673 ps
CPU time 345.37 seconds
Started Jul 01 04:33:56 PM PDT 24
Finished Jul 01 04:39:45 PM PDT 24
Peak memory 207664 kb
Host smart-03c7f16d-3207-4895-8e70-9ac4c1c8c282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394590450 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1394590450
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2038812837
Short name T143
Test name
Test status
Simulation time 133340373732 ps
CPU time 48.85 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:35:07 PM PDT 24
Peak memory 198012 kb
Host smart-904dd518-e09f-4bd4-a3e6-15d69954c6e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038812837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2038812837
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3127656120
Short name T161
Test name
Test status
Simulation time 104148905367 ps
CPU time 136.36 seconds
Started Jul 01 04:33:43 PM PDT 24
Finished Jul 01 04:36:01 PM PDT 24
Peak memory 199264 kb
Host smart-bb4855b9-8c7d-424f-80fa-d6740be6a03e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127656120 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3127656120
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1092704472
Short name T89
Test name
Test status
Simulation time 117657057243 ps
CPU time 87.52 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:35:28 PM PDT 24
Peak memory 192204 kb
Host smart-7b525f6e-58dd-4c44-8e65-9e59b2e4bb62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092704472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1092704472
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.533613331
Short name T122
Test name
Test status
Simulation time 80263040807 ps
CPU time 115.12 seconds
Started Jul 01 04:34:17 PM PDT 24
Finished Jul 01 04:36:22 PM PDT 24
Peak memory 197924 kb
Host smart-511e6003-b5c5-4086-a94f-1312f319a87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533613331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.533613331
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.517522853
Short name T1
Test name
Test status
Simulation time 43869817598 ps
CPU time 284.69 seconds
Started Jul 01 04:34:14 PM PDT 24
Finished Jul 01 04:39:09 PM PDT 24
Peak memory 206668 kb
Host smart-1bf189b4-00b7-410e-ad26-1aa798adc2be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517522853 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.517522853
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.328562884
Short name T154
Test name
Test status
Simulation time 41442255598 ps
CPU time 295.79 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:38:49 PM PDT 24
Peak memory 206576 kb
Host smart-e6c10cbc-6cbe-4eac-aa4e-95d2f28902db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328562884 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.328562884
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3236209678
Short name T90
Test name
Test status
Simulation time 391274941 ps
CPU time 0.73 seconds
Started Jul 01 04:33:42 PM PDT 24
Finished Jul 01 04:33:45 PM PDT 24
Peak memory 196540 kb
Host smart-f5cccbf8-3cb6-4aab-93cd-bbb67d612f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236209678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3236209678
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2192761972
Short name T139
Test name
Test status
Simulation time 599568151 ps
CPU time 1.17 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:34:01 PM PDT 24
Peak memory 196616 kb
Host smart-b36d0e74-729c-4ac8-9ca2-fd3417f3f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192761972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2192761972
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.134863904
Short name T125
Test name
Test status
Simulation time 428885730 ps
CPU time 1.28 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:34:02 PM PDT 24
Peak memory 196552 kb
Host smart-a65907c8-3970-47f5-840c-6b39beac3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134863904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.134863904
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3360866155
Short name T117
Test name
Test status
Simulation time 34278055109 ps
CPU time 42.49 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:34:43 PM PDT 24
Peak memory 191712 kb
Host smart-4f9cea63-b41c-4180-ab4a-90bb03e6a2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360866155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3360866155
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2710107892
Short name T104
Test name
Test status
Simulation time 551916991 ps
CPU time 0.8 seconds
Started Jul 01 04:33:56 PM PDT 24
Finished Jul 01 04:33:59 PM PDT 24
Peak memory 196440 kb
Host smart-78390047-1d29-4e52-b98f-90b67d1fb7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710107892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2710107892
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.350953467
Short name T151
Test name
Test status
Simulation time 199156097423 ps
CPU time 460.56 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 203212 kb
Host smart-29a6711b-56b3-4764-a02d-39a4e6e545d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350953467 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.350953467
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.4159758031
Short name T158
Test name
Test status
Simulation time 77375288436 ps
CPU time 209.89 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:37:48 PM PDT 24
Peak memory 208240 kb
Host smart-ff6f95d9-aff4-42a6-8226-2f9045fd623a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159758031 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.4159758031
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4113585415
Short name T130
Test name
Test status
Simulation time 534634627 ps
CPU time 0.75 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:34:03 PM PDT 24
Peak memory 196428 kb
Host smart-6dbf7da8-3e2e-43b6-86be-49b5958489c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113585415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4113585415
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.492435581
Short name T114
Test name
Test status
Simulation time 77226441699 ps
CPU time 96.56 seconds
Started Jul 01 04:34:15 PM PDT 24
Finished Jul 01 04:36:02 PM PDT 24
Peak memory 183844 kb
Host smart-4c5ac8c5-c57c-414a-b9c7-96b0fa881014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492435581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.492435581
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1383692597
Short name T46
Test name
Test status
Simulation time 48269611497 ps
CPU time 459.95 seconds
Started Jul 01 04:34:07 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 209368 kb
Host smart-bb13d707-024f-4294-8dff-7aab12480442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383692597 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1383692597
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2311888798
Short name T20
Test name
Test status
Simulation time 111762587457 ps
CPU time 156.34 seconds
Started Jul 01 04:34:14 PM PDT 24
Finished Jul 01 04:37:01 PM PDT 24
Peak memory 197996 kb
Host smart-f85e8176-7e04-4c09-a809-8a07b2013116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311888798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2311888798
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4227197886
Short name T108
Test name
Test status
Simulation time 230690641154 ps
CPU time 44.78 seconds
Started Jul 01 04:33:42 PM PDT 24
Finished Jul 01 04:34:28 PM PDT 24
Peak memory 192672 kb
Host smart-acaf516a-3797-42db-b965-f368ad488acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227197886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4227197886
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3196714242
Short name T81
Test name
Test status
Simulation time 543815212150 ps
CPU time 198.8 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:37:12 PM PDT 24
Peak memory 198012 kb
Host smart-4a012696-76c2-47b5-8b13-21a25a06787d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196714242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3196714242
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2037448994
Short name T148
Test name
Test status
Simulation time 162297180550 ps
CPU time 227.78 seconds
Started Jul 01 04:33:48 PM PDT 24
Finished Jul 01 04:37:37 PM PDT 24
Peak memory 192668 kb
Host smart-061285ad-3958-439e-85ea-8b5e16475a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037448994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2037448994
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3129607368
Short name T127
Test name
Test status
Simulation time 525494607 ps
CPU time 0.96 seconds
Started Jul 01 04:34:12 PM PDT 24
Finished Jul 01 04:34:23 PM PDT 24
Peak memory 196308 kb
Host smart-dc750d7e-1553-4599-b163-c38c22e6828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129607368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3129607368
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1748099335
Short name T147
Test name
Test status
Simulation time 29140121289 ps
CPU time 222.53 seconds
Started Jul 01 04:34:07 PM PDT 24
Finished Jul 01 04:37:57 PM PDT 24
Peak memory 206564 kb
Host smart-1e117067-988f-466b-89e3-2cbbccefdf05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748099335 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1748099335
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3119256371
Short name T131
Test name
Test status
Simulation time 315677795452 ps
CPU time 472.32 seconds
Started Jul 01 04:34:15 PM PDT 24
Finished Jul 01 04:42:18 PM PDT 24
Peak memory 192412 kb
Host smart-e5f8d26f-e340-4602-a8f1-c77c2999c69b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119256371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3119256371
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3188736890
Short name T88
Test name
Test status
Simulation time 555446399 ps
CPU time 0.75 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:34:04 PM PDT 24
Peak memory 196504 kb
Host smart-122fdb49-28ce-472e-bb3a-b2af91d90d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188736890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3188736890
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3413715734
Short name T140
Test name
Test status
Simulation time 3932914410 ps
CPU time 6.18 seconds
Started Jul 01 04:34:01 PM PDT 24
Finished Jul 01 04:34:11 PM PDT 24
Peak memory 197964 kb
Host smart-d33866ea-a7b3-423f-86c5-b1523873dae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413715734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3413715734
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2222244174
Short name T153
Test name
Test status
Simulation time 48990504777 ps
CPU time 67.81 seconds
Started Jul 01 04:33:49 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 192312 kb
Host smart-11f7b6f4-0a84-4ac9-afb4-adadc419b76e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222244174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2222244174
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.811255774
Short name T136
Test name
Test status
Simulation time 419305206 ps
CPU time 1.28 seconds
Started Jul 01 04:33:54 PM PDT 24
Finished Jul 01 04:33:58 PM PDT 24
Peak memory 196280 kb
Host smart-2c498a51-d814-4d65-a0c4-5a9752ad0477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811255774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.811255774
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2463313738
Short name T105
Test name
Test status
Simulation time 55625048993 ps
CPU time 17.02 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:23 PM PDT 24
Peak memory 197852 kb
Host smart-c6dacdb3-0401-402b-ad46-66016f383851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463313738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2463313738
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2590405940
Short name T23
Test name
Test status
Simulation time 548426619 ps
CPU time 1.29 seconds
Started Jul 01 04:34:06 PM PDT 24
Finished Jul 01 04:34:13 PM PDT 24
Peak memory 196472 kb
Host smart-37e1f456-627b-42ce-a872-9669ae8fada3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590405940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2590405940
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1969365675
Short name T32
Test name
Test status
Simulation time 43338414144 ps
CPU time 177.45 seconds
Started Jul 01 04:34:06 PM PDT 24
Finished Jul 01 04:37:10 PM PDT 24
Peak memory 206520 kb
Host smart-0eca6d99-569b-4e2a-b62c-359b1bdf9028
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969365675 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1969365675
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3663170031
Short name T95
Test name
Test status
Simulation time 493764834 ps
CPU time 0.93 seconds
Started Jul 01 04:33:55 PM PDT 24
Finished Jul 01 04:33:59 PM PDT 24
Peak memory 196456 kb
Host smart-51db285b-9979-4a68-a8c5-dae3b277bcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663170031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3663170031
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1249630289
Short name T123
Test name
Test status
Simulation time 381236644 ps
CPU time 1.14 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:34:02 PM PDT 24
Peak memory 196416 kb
Host smart-0d78bffb-131d-4018-aa84-fcef69c64810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249630289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1249630289
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.679401498
Short name T24
Test name
Test status
Simulation time 121295367171 ps
CPU time 39.85 seconds
Started Jul 01 04:34:15 PM PDT 24
Finished Jul 01 04:35:05 PM PDT 24
Peak memory 197920 kb
Host smart-caaeb051-13f1-4211-af47-e5168c902202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679401498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.679401498
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4282878726
Short name T96
Test name
Test status
Simulation time 153283907061 ps
CPU time 53.61 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:34:46 PM PDT 24
Peak memory 192668 kb
Host smart-8b3f618c-3fa6-4f61-949c-296e95aa7a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282878726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4282878726
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.947144606
Short name T85
Test name
Test status
Simulation time 302397956397 ps
CPU time 121.52 seconds
Started Jul 01 04:34:13 PM PDT 24
Finished Jul 01 04:36:24 PM PDT 24
Peak memory 198104 kb
Host smart-5670fdf4-443d-4ba9-a6e3-96fbc5236e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947144606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.947144606
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.564838985
Short name T98
Test name
Test status
Simulation time 96293340290 ps
CPU time 74.07 seconds
Started Jul 01 04:33:43 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 191640 kb
Host smart-4277c61c-e4c1-4d52-a592-fdf1ccb1947a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564838985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.564838985
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.7212365
Short name T135
Test name
Test status
Simulation time 59720756351 ps
CPU time 242.9 seconds
Started Jul 01 04:33:53 PM PDT 24
Finished Jul 01 04:37:59 PM PDT 24
Peak memory 206936 kb
Host smart-151a2d8d-6bd8-47ed-8f56-3f2b48ffb5e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7212365 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.7212365
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2328906534
Short name T133
Test name
Test status
Simulation time 577700466 ps
CPU time 0.71 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:34:08 PM PDT 24
Peak memory 196400 kb
Host smart-2aff9fcf-fd62-47a3-8ba0-6b2afcc80e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328906534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2328906534
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4132137131
Short name T126
Test name
Test status
Simulation time 577813213 ps
CPU time 0.86 seconds
Started Jul 01 04:33:50 PM PDT 24
Finished Jul 01 04:33:53 PM PDT 24
Peak memory 196600 kb
Host smart-f752e18c-e2fb-4b19-b3ec-4d6202041764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132137131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4132137131
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.845867467
Short name T138
Test name
Test status
Simulation time 551809178 ps
CPU time 1.44 seconds
Started Jul 01 04:33:48 PM PDT 24
Finished Jul 01 04:33:50 PM PDT 24
Peak memory 196504 kb
Host smart-45fa9e19-0716-4350-9b8a-bc1ef903c56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845867467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.845867467
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3029324182
Short name T112
Test name
Test status
Simulation time 95962522964 ps
CPU time 21.31 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 191656 kb
Host smart-2aba2b37-7e6c-4a2d-98b5-bf306ce3fb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029324182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3029324182
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2979568496
Short name T121
Test name
Test status
Simulation time 609524768 ps
CPU time 0.8 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 196324 kb
Host smart-bba5c1ee-e3eb-42d5-825e-7613aa40b159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979568496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2979568496
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3472682433
Short name T149
Test name
Test status
Simulation time 570580011078 ps
CPU time 804.39 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:47:41 PM PDT 24
Peak memory 191560 kb
Host smart-1601c1ad-491d-49bb-bac1-4cf7bd45ff8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472682433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3472682433
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3136663456
Short name T92
Test name
Test status
Simulation time 440836795 ps
CPU time 0.85 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 196436 kb
Host smart-5705123f-3b11-48ef-9805-df667b1d2445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136663456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3136663456
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2777714229
Short name T107
Test name
Test status
Simulation time 429796614 ps
CPU time 1.16 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:06 PM PDT 24
Peak memory 196296 kb
Host smart-fc1110fd-9bbf-4e61-97ee-9b20e069c43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777714229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2777714229
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3184306535
Short name T129
Test name
Test status
Simulation time 573895562 ps
CPU time 1.51 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:08 PM PDT 24
Peak memory 196308 kb
Host smart-4bf66b70-3b87-4f25-8bbf-97f4c87547c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184306535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3184306535
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2903908742
Short name T30
Test name
Test status
Simulation time 527855792 ps
CPU time 0.86 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:34:16 PM PDT 24
Peak memory 196452 kb
Host smart-8bf05c8d-c3e9-4234-90cc-3c1e9ead3c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903908742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2903908742
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1593187373
Short name T109
Test name
Test status
Simulation time 334272045337 ps
CPU time 123.43 seconds
Started Jul 01 04:33:42 PM PDT 24
Finished Jul 01 04:35:48 PM PDT 24
Peak memory 191768 kb
Host smart-2b0e5673-d1e1-4952-b930-ce060dd94e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593187373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1593187373
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.214411099
Short name T152
Test name
Test status
Simulation time 73952144437 ps
CPU time 28.39 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 192676 kb
Host smart-359c5408-634e-4dae-a248-c299c292bb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214411099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.214411099
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1618632758
Short name T142
Test name
Test status
Simulation time 477790375 ps
CPU time 0.72 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:21 PM PDT 24
Peak memory 196380 kb
Host smart-c034ec53-d052-465c-be6b-e79079e5bbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618632758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1618632758
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1233635705
Short name T137
Test name
Test status
Simulation time 448718357 ps
CPU time 1.28 seconds
Started Jul 01 04:33:43 PM PDT 24
Finished Jul 01 04:33:46 PM PDT 24
Peak memory 196380 kb
Host smart-6eace5e4-d8a0-4514-b1ab-582b030d7e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233635705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1233635705
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3330488920
Short name T162
Test name
Test status
Simulation time 504439164246 ps
CPU time 694.41 seconds
Started Jul 01 04:33:42 PM PDT 24
Finished Jul 01 04:45:18 PM PDT 24
Peak memory 192348 kb
Host smart-385c1fdc-afc9-475c-864d-88f13f30c25f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330488920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3330488920
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2905859947
Short name T150
Test name
Test status
Simulation time 355925272118 ps
CPU time 445.5 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:41:26 PM PDT 24
Peak memory 192744 kb
Host smart-e5fc39f8-87ad-4850-80bf-434565bc143f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905859947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2905859947
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1319628066
Short name T141
Test name
Test status
Simulation time 351282391 ps
CPU time 1.14 seconds
Started Jul 01 04:33:44 PM PDT 24
Finished Jul 01 04:33:47 PM PDT 24
Peak memory 196408 kb
Host smart-4e4f7eb2-33cc-4254-8393-e5e14492f928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319628066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1319628066
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.4126196920
Short name T41
Test name
Test status
Simulation time 28183244404 ps
CPU time 291.78 seconds
Started Jul 01 04:34:04 PM PDT 24
Finished Jul 01 04:39:01 PM PDT 24
Peak memory 198368 kb
Host smart-ad5151e5-d9aa-4831-8a34-adfd1cecc4fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126196920 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.4126196920
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1217554538
Short name T171
Test name
Test status
Simulation time 586260682 ps
CPU time 1.44 seconds
Started Jul 01 04:33:46 PM PDT 24
Finished Jul 01 04:33:49 PM PDT 24
Peak memory 196360 kb
Host smart-eb3766bd-9544-4506-ab71-42225404094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217554538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1217554538
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1707674726
Short name T100
Test name
Test status
Simulation time 516272264 ps
CPU time 1.42 seconds
Started Jul 01 04:33:55 PM PDT 24
Finished Jul 01 04:33:59 PM PDT 24
Peak memory 196304 kb
Host smart-12e16082-17cf-4986-a8c2-504615be1710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707674726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1707674726
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1912567967
Short name T128
Test name
Test status
Simulation time 219069452762 ps
CPU time 16.14 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:34:13 PM PDT 24
Peak memory 192564 kb
Host smart-c18716d2-a4f1-46ae-aa09-a2eb85be7dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912567967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1912567967
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.970173484
Short name T6
Test name
Test status
Simulation time 373705494 ps
CPU time 1.12 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 196376 kb
Host smart-0da59658-8ac8-4ae0-805b-d1fb5c2f1e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970173484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.970173484
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2777879734
Short name T124
Test name
Test status
Simulation time 355899441 ps
CPU time 1.02 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:22 PM PDT 24
Peak memory 196392 kb
Host smart-7fabdd38-aa72-41ec-a6e1-96197af59411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777879734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2777879734
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.503837746
Short name T166
Test name
Test status
Simulation time 113802811480 ps
CPU time 150.54 seconds
Started Jul 01 04:33:44 PM PDT 24
Finished Jul 01 04:36:16 PM PDT 24
Peak memory 198004 kb
Host smart-6bafbb3f-8b1d-4d58-b478-cc6fba887638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503837746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.503837746
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.4150236819
Short name T134
Test name
Test status
Simulation time 378873678 ps
CPU time 1.05 seconds
Started Jul 01 04:33:43 PM PDT 24
Finished Jul 01 04:33:46 PM PDT 24
Peak memory 196224 kb
Host smart-18ff0983-e49d-41c2-acbe-fedfdc4d1b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150236819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4150236819
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1227956123
Short name T173
Test name
Test status
Simulation time 498711096 ps
CPU time 1.04 seconds
Started Jul 01 04:34:08 PM PDT 24
Finished Jul 01 04:34:16 PM PDT 24
Peak memory 196576 kb
Host smart-15355dc4-5c9b-43f9-afd7-60d9ff4a4fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227956123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1227956123
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1126446284
Short name T157
Test name
Test status
Simulation time 411183391 ps
CPU time 1.1 seconds
Started Jul 01 04:34:07 PM PDT 24
Finished Jul 01 04:34:14 PM PDT 24
Peak memory 196632 kb
Host smart-81ed03f0-3696-47d6-bb14-7ee876617b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126446284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1126446284
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1108506676
Short name T45
Test name
Test status
Simulation time 552464510 ps
CPU time 1.44 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:07 PM PDT 24
Peak memory 196448 kb
Host smart-c09345c8-4925-4726-b7d5-f9890fa5189c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108506676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1108506676
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3421494474
Short name T167
Test name
Test status
Simulation time 489682300 ps
CPU time 0.77 seconds
Started Jul 01 04:33:53 PM PDT 24
Finished Jul 01 04:33:56 PM PDT 24
Peak memory 196360 kb
Host smart-61d1e28f-4498-4669-89f4-f2583ecf2c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421494474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3421494474
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.249460724
Short name T156
Test name
Test status
Simulation time 595962547 ps
CPU time 0.8 seconds
Started Jul 01 04:33:50 PM PDT 24
Finished Jul 01 04:33:53 PM PDT 24
Peak memory 196508 kb
Host smart-b8d9d89f-14fe-4930-bedd-c115c3b5748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249460724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.249460724
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2144128891
Short name T78
Test name
Test status
Simulation time 368812727 ps
CPU time 0.89 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:07 PM PDT 24
Peak memory 196244 kb
Host smart-fa00578d-b58f-4348-8e4d-c1a069b9b1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144128891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2144128891
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.28441473
Short name T180
Test name
Test status
Simulation time 352898647 ps
CPU time 1.09 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 196544 kb
Host smart-bb68a7cd-91f2-4d68-84f9-2343545fefe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28441473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.28441473
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3112731411
Short name T4
Test name
Test status
Simulation time 487003743 ps
CPU time 0.75 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 196444 kb
Host smart-5c8dfdd3-f8ea-41fa-aba7-ca6396f493ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112731411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3112731411
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3011809347
Short name T177
Test name
Test status
Simulation time 476909489 ps
CPU time 0.83 seconds
Started Jul 01 04:34:04 PM PDT 24
Finished Jul 01 04:34:10 PM PDT 24
Peak memory 196416 kb
Host smart-e391a3e6-6bd4-4caf-bfe7-3691d0d0ec23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011809347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3011809347
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.274167901
Short name T165
Test name
Test status
Simulation time 482444702 ps
CPU time 0.78 seconds
Started Jul 01 04:33:47 PM PDT 24
Finished Jul 01 04:33:49 PM PDT 24
Peak memory 196300 kb
Host smart-b8a7591e-820e-4742-977b-9fbbd1a8110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274167901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.274167901
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3320142448
Short name T387
Test name
Test status
Simulation time 8007170586 ps
CPU time 3.77 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:49 PM PDT 24
Peak memory 198396 kb
Host smart-9c6644bb-c66a-4556-9bfa-2ddf9ad059f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320142448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3320142448
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1634145336
Short name T179
Test name
Test status
Simulation time 474117354 ps
CPU time 0.74 seconds
Started Jul 01 04:33:41 PM PDT 24
Finished Jul 01 04:33:43 PM PDT 24
Peak memory 196376 kb
Host smart-39f16408-112f-4ea4-b5e3-00c09e00bdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634145336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1634145336
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2864417248
Short name T36
Test name
Test status
Simulation time 107974716179 ps
CPU time 42.28 seconds
Started Jul 01 04:33:53 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 198072 kb
Host smart-103ede5f-d769-4ffb-9f41-2ebc4473a909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864417248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2864417248
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1656088927
Short name T181
Test name
Test status
Simulation time 505261289 ps
CPU time 0.79 seconds
Started Jul 01 04:34:06 PM PDT 24
Finished Jul 01 04:34:13 PM PDT 24
Peak memory 196624 kb
Host smart-4542e530-4807-4080-a47d-e9fdda691add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656088927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1656088927
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1272189622
Short name T175
Test name
Test status
Simulation time 532266920 ps
CPU time 1.37 seconds
Started Jul 01 04:34:08 PM PDT 24
Finished Jul 01 04:34:16 PM PDT 24
Peak memory 196368 kb
Host smart-3902a8ed-d2d1-4b00-bf1b-aed61de6a8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272189622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1272189622
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2440238310
Short name T159
Test name
Test status
Simulation time 43830689595 ps
CPU time 331.99 seconds
Started Jul 01 04:33:56 PM PDT 24
Finished Jul 01 04:39:32 PM PDT 24
Peak memory 207064 kb
Host smart-09e5890b-3d96-44cd-bb12-b158ae5157ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440238310 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2440238310
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2955170275
Short name T163
Test name
Test status
Simulation time 399063528 ps
CPU time 0.77 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:34:01 PM PDT 24
Peak memory 196460 kb
Host smart-6319c0e1-33f7-4b1c-8af0-d772ac0025e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955170275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2955170275
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1419758669
Short name T169
Test name
Test status
Simulation time 415397352 ps
CPU time 0.74 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:34:17 PM PDT 24
Peak memory 196444 kb
Host smart-64f61d11-b2de-4b8a-8cd0-7fa1bd8b985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419758669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1419758669
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.4110902140
Short name T168
Test name
Test status
Simulation time 631190655 ps
CPU time 0.81 seconds
Started Jul 01 04:33:49 PM PDT 24
Finished Jul 01 04:33:52 PM PDT 24
Peak memory 196320 kb
Host smart-5e8f1c8f-b6a4-4cb2-bc6a-2ddeb56bae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110902140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.4110902140
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3727799576
Short name T170
Test name
Test status
Simulation time 594807538 ps
CPU time 0.81 seconds
Started Jul 01 04:33:43 PM PDT 24
Finished Jul 01 04:33:46 PM PDT 24
Peak memory 196168 kb
Host smart-726d2b61-8e67-4c76-8365-e8d8e798cdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727799576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3727799576
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2652650231
Short name T294
Test name
Test status
Simulation time 517607487 ps
CPU time 1.44 seconds
Started Jul 01 04:32:33 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 193228 kb
Host smart-78549a37-f665-4b53-b800-ec520b6396be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652650231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2652650231
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2134127699
Short name T308
Test name
Test status
Simulation time 7263604874 ps
CPU time 5.99 seconds
Started Jul 01 04:32:56 PM PDT 24
Finished Jul 01 04:33:12 PM PDT 24
Peak memory 196672 kb
Host smart-6c0b3728-5e4a-403c-b990-ce7b83b7dbf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134127699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2134127699
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.648300142
Short name T318
Test name
Test status
Simulation time 454509764 ps
CPU time 1.02 seconds
Started Jul 01 04:32:43 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 195700 kb
Host smart-35239248-18cb-4603-a7cb-9a28f6dc73ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648300142 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.648300142
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1161338385
Short name T397
Test name
Test status
Simulation time 563427901 ps
CPU time 0.89 seconds
Started Jul 01 04:32:37 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 193480 kb
Host smart-eff39967-8899-4bc8-a227-86ad43175bd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161338385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1161338385
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.250307037
Short name T348
Test name
Test status
Simulation time 357433171 ps
CPU time 0.66 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:46 PM PDT 24
Peak memory 183680 kb
Host smart-ae12cf07-9db9-43d5-9a1d-32e2bcd3497a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250307037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.250307037
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2209289579
Short name T376
Test name
Test status
Simulation time 476597249 ps
CPU time 0.84 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:45 PM PDT 24
Peak memory 183848 kb
Host smart-9cdd5382-68cf-42cc-bd67-8d02d693d9b6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209289579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2209289579
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1036613514
Short name T378
Test name
Test status
Simulation time 407134195 ps
CPU time 0.77 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:46 PM PDT 24
Peak memory 183704 kb
Host smart-5789bdb1-b05b-42a3-b06a-095449df5468
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036613514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1036613514
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3865310366
Short name T309
Test name
Test status
Simulation time 1500978317 ps
CPU time 2.74 seconds
Started Jul 01 04:32:25 PM PDT 24
Finished Jul 01 04:32:45 PM PDT 24
Peak memory 183752 kb
Host smart-ee47490f-9da6-4899-ad0b-f145507d8fec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865310366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3865310366
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3196979018
Short name T307
Test name
Test status
Simulation time 318258402 ps
CPU time 1.27 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:45 PM PDT 24
Peak memory 198448 kb
Host smart-e3848c3b-1838-465c-80ae-8a0befadaf6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196979018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3196979018
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3149432833
Short name T59
Test name
Test status
Simulation time 601007043 ps
CPU time 1.37 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:47 PM PDT 24
Peak memory 193120 kb
Host smart-7c78fa8e-92c9-4b36-b440-b7d1490e8706
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149432833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3149432833
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1122607950
Short name T187
Test name
Test status
Simulation time 7003504936 ps
CPU time 9.42 seconds
Started Jul 01 04:32:34 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 196572 kb
Host smart-69b4de51-4409-45ef-8a42-310abd9de8fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122607950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1122607950
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2958023620
Short name T400
Test name
Test status
Simulation time 879564221 ps
CPU time 1.28 seconds
Started Jul 01 04:32:49 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 193072 kb
Host smart-4ecd33e3-d59f-4c1f-b5e7-c661584a98b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958023620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2958023620
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3851952855
Short name T389
Test name
Test status
Simulation time 469682541 ps
CPU time 0.81 seconds
Started Jul 01 04:32:49 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 196524 kb
Host smart-cb3e7706-21e6-4c7b-9db4-d2bb803ad006
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851952855 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3851952855
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1046419558
Short name T58
Test name
Test status
Simulation time 430396424 ps
CPU time 0.69 seconds
Started Jul 01 04:32:46 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 193020 kb
Host smart-6a64051b-749e-4de5-9665-42493a3316a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046419558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1046419558
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1460397946
Short name T282
Test name
Test status
Simulation time 470280623 ps
CPU time 1.17 seconds
Started Jul 01 04:32:42 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 183792 kb
Host smart-6b4d1e31-f430-458b-9851-1f9795e6fd37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460397946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1460397946
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3262882039
Short name T356
Test name
Test status
Simulation time 447097180 ps
CPU time 1.2 seconds
Started Jul 01 04:32:42 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 183784 kb
Host smart-39ca7ca4-6031-461c-8712-a6ca43d05169
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262882039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3262882039
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3861903695
Short name T384
Test name
Test status
Simulation time 289223471 ps
CPU time 0.97 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:47 PM PDT 24
Peak memory 183788 kb
Host smart-91f8c981-b2aa-45f6-83ee-85025c47c003
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861903695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3861903695
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.155044244
Short name T339
Test name
Test status
Simulation time 1570386866 ps
CPU time 1.57 seconds
Started Jul 01 04:32:48 PM PDT 24
Finished Jul 01 04:33:01 PM PDT 24
Peak memory 192860 kb
Host smart-5a185222-6fad-4ef2-8e97-d97812a1fdad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155044244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.155044244
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3307813634
Short name T343
Test name
Test status
Simulation time 717164333 ps
CPU time 2.08 seconds
Started Jul 01 04:32:29 PM PDT 24
Finished Jul 01 04:32:49 PM PDT 24
Peak memory 198540 kb
Host smart-d8ec35c2-704e-44cc-85c3-2a50a66086fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307813634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3307813634
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3342712606
Short name T393
Test name
Test status
Simulation time 4427833659 ps
CPU time 4.17 seconds
Started Jul 01 04:32:30 PM PDT 24
Finished Jul 01 04:32:52 PM PDT 24
Peak memory 197876 kb
Host smart-9e73d2cb-2c58-4c88-a4d4-ebc0492343e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342712606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3342712606
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3180495799
Short name T275
Test name
Test status
Simulation time 567936053 ps
CPU time 1.48 seconds
Started Jul 01 04:32:49 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 195928 kb
Host smart-308c7ffe-9cac-4d93-8334-146bcc6acb88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180495799 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3180495799
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3625263059
Short name T316
Test name
Test status
Simulation time 500031326 ps
CPU time 0.66 seconds
Started Jul 01 04:32:54 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 192992 kb
Host smart-a5d12306-06f5-4dcf-b2f8-6db078443301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625263059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3625263059
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.902078046
Short name T413
Test name
Test status
Simulation time 422579582 ps
CPU time 0.8 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 183804 kb
Host smart-4bf54f08-b56e-4249-a23c-6e975b2e7d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902078046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.902078046
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1679985825
Short name T67
Test name
Test status
Simulation time 1642711538 ps
CPU time 2.62 seconds
Started Jul 01 04:32:49 PM PDT 24
Finished Jul 01 04:33:03 PM PDT 24
Peak memory 195048 kb
Host smart-c916c0eb-e0f3-4168-ab31-eba77efb634d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679985825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1679985825
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3022221891
Short name T361
Test name
Test status
Simulation time 359889918 ps
CPU time 2.46 seconds
Started Jul 01 04:32:48 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 198644 kb
Host smart-f2fc549d-03d6-4d07-ab51-b78258a02ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022221891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3022221891
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3165234506
Short name T411
Test name
Test status
Simulation time 8416546864 ps
CPU time 3.88 seconds
Started Jul 01 04:32:55 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 198160 kb
Host smart-3df29012-9800-44b7-a88a-a0fa9181a0b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165234506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3165234506
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2289145496
Short name T325
Test name
Test status
Simulation time 377857336 ps
CPU time 1.32 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:03 PM PDT 24
Peak memory 196156 kb
Host smart-965ceec4-7658-4f05-990a-060a87920d63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289145496 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2289145496
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.153493057
Short name T415
Test name
Test status
Simulation time 438919298 ps
CPU time 1.13 seconds
Started Jul 01 04:32:55 PM PDT 24
Finished Jul 01 04:33:06 PM PDT 24
Peak memory 192924 kb
Host smart-6b8d03df-a96d-404d-985f-a46f0dfb95bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153493057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.153493057
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2049574728
Short name T365
Test name
Test status
Simulation time 327696921 ps
CPU time 0.62 seconds
Started Jul 01 04:32:48 PM PDT 24
Finished Jul 01 04:33:00 PM PDT 24
Peak memory 183760 kb
Host smart-0ee6e4df-c5f2-44a0-a89e-ac9eec204f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049574728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2049574728
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1528204937
Short name T379
Test name
Test status
Simulation time 2147014106 ps
CPU time 1.81 seconds
Started Jul 01 04:32:57 PM PDT 24
Finished Jul 01 04:33:08 PM PDT 24
Peak memory 193980 kb
Host smart-9cc39ff7-d1ac-426d-8c8e-3840f0e57283
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528204937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1528204937
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.110345865
Short name T290
Test name
Test status
Simulation time 331993468 ps
CPU time 1.84 seconds
Started Jul 01 04:33:02 PM PDT 24
Finished Jul 01 04:33:11 PM PDT 24
Peak memory 198496 kb
Host smart-3c5682dc-7797-4602-acaf-b7d3fd5178b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110345865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.110345865
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1439834245
Short name T304
Test name
Test status
Simulation time 4399952404 ps
CPU time 7.66 seconds
Started Jul 01 04:32:55 PM PDT 24
Finished Jul 01 04:33:13 PM PDT 24
Peak memory 197940 kb
Host smart-97499288-6fb8-42d8-b61b-d4b20fcb1503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439834245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1439834245
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.50724201
Short name T336
Test name
Test status
Simulation time 490153011 ps
CPU time 1.25 seconds
Started Jul 01 04:32:52 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 196252 kb
Host smart-333dce23-95a7-4326-a5cb-9f7bc2021778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50724201 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.50724201
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1096721061
Short name T364
Test name
Test status
Simulation time 440043400 ps
CPU time 0.75 seconds
Started Jul 01 04:32:53 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 191952 kb
Host smart-4dea7905-335f-4a10-998f-4a701b1d3506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096721061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1096721061
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3870936856
Short name T303
Test name
Test status
Simulation time 306691110 ps
CPU time 1.07 seconds
Started Jul 01 04:32:48 PM PDT 24
Finished Jul 01 04:33:00 PM PDT 24
Peak memory 183788 kb
Host smart-c9f58a22-4f87-4af9-a0ef-ccdf6e8b9839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870936856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3870936856
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.798310446
Short name T390
Test name
Test status
Simulation time 1141421508 ps
CPU time 2.18 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:03 PM PDT 24
Peak memory 193440 kb
Host smart-4b7ba0b0-9ff0-411a-94ef-d15b76c21e50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798310446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.798310446
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4056164903
Short name T347
Test name
Test status
Simulation time 367343154 ps
CPU time 1.59 seconds
Started Jul 01 04:32:49 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 198436 kb
Host smart-2f5cf2cd-5c88-4d16-bd52-d22de24eca94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056164903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4056164903
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1295696778
Short name T371
Test name
Test status
Simulation time 8489917717 ps
CPU time 5.91 seconds
Started Jul 01 04:32:55 PM PDT 24
Finished Jul 01 04:33:11 PM PDT 24
Peak memory 198212 kb
Host smart-e2025c48-396c-4ee5-a6a3-b23d752e29d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295696778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1295696778
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1399733918
Short name T292
Test name
Test status
Simulation time 407073256 ps
CPU time 0.9 seconds
Started Jul 01 04:32:57 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 195544 kb
Host smart-47161516-8323-45e6-9ed8-fd3b559b3d8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399733918 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1399733918
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.864511857
Short name T52
Test name
Test status
Simulation time 286898349 ps
CPU time 0.97 seconds
Started Jul 01 04:33:00 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 193156 kb
Host smart-40a3c8b4-3db8-4f33-b3e8-ca4deff11ef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864511857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.864511857
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3033211524
Short name T299
Test name
Test status
Simulation time 503465844 ps
CPU time 0.61 seconds
Started Jul 01 04:32:59 PM PDT 24
Finished Jul 01 04:33:08 PM PDT 24
Peak memory 183836 kb
Host smart-8c2b76dc-7b68-4ef0-aa28-3359087ab188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033211524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3033211524
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.843195961
Short name T66
Test name
Test status
Simulation time 1642105509 ps
CPU time 0.85 seconds
Started Jul 01 04:32:52 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 193916 kb
Host smart-e957a6cf-7174-4c2f-b0a2-b1d70a17fd0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843195961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.843195961
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2785710081
Short name T359
Test name
Test status
Simulation time 484877073 ps
CPU time 2.11 seconds
Started Jul 01 04:32:49 PM PDT 24
Finished Jul 01 04:33:03 PM PDT 24
Peak memory 198496 kb
Host smart-df8abcd2-754c-42ec-b306-b923c7a14b97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785710081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2785710081
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2397319535
Short name T39
Test name
Test status
Simulation time 8686213559 ps
CPU time 4.52 seconds
Started Jul 01 04:32:51 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 198124 kb
Host smart-fa341acb-b973-4f96-ac52-7d5115391c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397319535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2397319535
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.453591820
Short name T322
Test name
Test status
Simulation time 506723869 ps
CPU time 1.32 seconds
Started Jul 01 04:33:05 PM PDT 24
Finished Jul 01 04:33:14 PM PDT 24
Peak memory 196672 kb
Host smart-9f6b8e57-466a-45c0-b1a1-309b92181e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453591820 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.453591820
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2228773958
Short name T362
Test name
Test status
Simulation time 501211693 ps
CPU time 0.73 seconds
Started Jul 01 04:32:57 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 192980 kb
Host smart-9a383b04-7fcb-457a-98e4-01f1c73f8a9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228773958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2228773958
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2533043720
Short name T288
Test name
Test status
Simulation time 518588195 ps
CPU time 1.36 seconds
Started Jul 01 04:33:02 PM PDT 24
Finished Jul 01 04:33:12 PM PDT 24
Peak memory 183876 kb
Host smart-0c10619c-521c-45f4-a96b-5067dbc676a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533043720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2533043720
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2303131257
Short name T377
Test name
Test status
Simulation time 1470617839 ps
CPU time 1.02 seconds
Started Jul 01 04:33:03 PM PDT 24
Finished Jul 01 04:33:13 PM PDT 24
Peak memory 192936 kb
Host smart-7d7ee572-0562-458f-98cd-2e692542490e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303131257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2303131257
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1555798052
Short name T404
Test name
Test status
Simulation time 384440915 ps
CPU time 2.06 seconds
Started Jul 01 04:32:58 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 198472 kb
Host smart-ee4a2b90-95d6-431c-9db8-b1d045160a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555798052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1555798052
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3811898246
Short name T323
Test name
Test status
Simulation time 4393164591 ps
CPU time 3.23 seconds
Started Jul 01 04:32:53 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 198060 kb
Host smart-dcb19fec-e582-4289-9952-f85aabc32a94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811898246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3811898246
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1410315570
Short name T388
Test name
Test status
Simulation time 513167581 ps
CPU time 1.38 seconds
Started Jul 01 04:32:52 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 197144 kb
Host smart-0fa2e9a5-100d-43d2-b76a-35347b37e609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410315570 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1410315570
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.75723030
Short name T54
Test name
Test status
Simulation time 319903893 ps
CPU time 1.04 seconds
Started Jul 01 04:32:54 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 192888 kb
Host smart-577244b8-3050-4735-a8cc-398f18d87a8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75723030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.75723030
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2073474870
Short name T312
Test name
Test status
Simulation time 470106797 ps
CPU time 1.28 seconds
Started Jul 01 04:32:58 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 183832 kb
Host smart-5a40c7f6-77fa-4e41-a241-9c8d01648a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073474870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2073474870
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4066011868
Short name T64
Test name
Test status
Simulation time 1589391447 ps
CPU time 1.04 seconds
Started Jul 01 04:33:02 PM PDT 24
Finished Jul 01 04:33:10 PM PDT 24
Peak memory 193012 kb
Host smart-2fe1cb9b-1f3a-4ff3-9a9c-199aaef3237b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066011868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.4066011868
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.34532575
Short name T354
Test name
Test status
Simulation time 835786728 ps
CPU time 2.25 seconds
Started Jul 01 04:32:58 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 198688 kb
Host smart-a0acb1c5-541d-4138-82a8-251ec88d1616
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34532575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.34532575
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1624401523
Short name T183
Test name
Test status
Simulation time 8635935276 ps
CPU time 13.4 seconds
Started Jul 01 04:32:57 PM PDT 24
Finished Jul 01 04:33:20 PM PDT 24
Peak memory 198104 kb
Host smart-654e8997-4702-49bc-b6db-2571f7b9d869
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624401523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1624401523
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.680833579
Short name T306
Test name
Test status
Simulation time 607071125 ps
CPU time 0.74 seconds
Started Jul 01 04:32:54 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 197080 kb
Host smart-c7718193-a9f8-4cac-bc82-a8fb6bd24d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680833579 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.680833579
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1427118269
Short name T369
Test name
Test status
Simulation time 299626709 ps
CPU time 0.65 seconds
Started Jul 01 04:32:57 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 183792 kb
Host smart-8ab160c1-5709-453a-a494-276323c63d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427118269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1427118269
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3265012871
Short name T370
Test name
Test status
Simulation time 1536288572 ps
CPU time 1.23 seconds
Started Jul 01 04:32:53 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 194024 kb
Host smart-e57d08ec-fece-4cfb-b92b-cedba0972e2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265012871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3265012871
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.497156848
Short name T360
Test name
Test status
Simulation time 534353074 ps
CPU time 2.1 seconds
Started Jul 01 04:32:59 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 198580 kb
Host smart-3bc3f32e-4a0f-40f7-816e-4a2db4b2d402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497156848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.497156848
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2532312631
Short name T396
Test name
Test status
Simulation time 4265747307 ps
CPU time 5.37 seconds
Started Jul 01 04:32:53 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 197764 kb
Host smart-e7a55f2b-5c5d-4f80-8186-4cdab00cd73e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532312631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2532312631
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3060861935
Short name T35
Test name
Test status
Simulation time 499699233 ps
CPU time 0.93 seconds
Started Jul 01 04:32:57 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 196460 kb
Host smart-c42b72b9-3ba7-4c38-a943-4c10e089a2a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060861935 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3060861935
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.650634641
Short name T49
Test name
Test status
Simulation time 397370907 ps
CPU time 1.26 seconds
Started Jul 01 04:33:05 PM PDT 24
Finished Jul 01 04:33:14 PM PDT 24
Peak memory 193024 kb
Host smart-3028783a-454d-43a2-9c5d-f49bc9d5c2dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650634641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.650634641
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4166947367
Short name T405
Test name
Test status
Simulation time 279363018 ps
CPU time 0.84 seconds
Started Jul 01 04:33:00 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 193052 kb
Host smart-a3da9aea-990b-4247-ad96-2d838a3ea7bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166947367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.4166947367
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.822742088
Short name T319
Test name
Test status
Simulation time 2539348677 ps
CPU time 2.16 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 195104 kb
Host smart-9af6e285-16e4-4710-bf37-a9d4f0d8dff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822742088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.822742088
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2029652125
Short name T409
Test name
Test status
Simulation time 784896088 ps
CPU time 1.93 seconds
Started Jul 01 04:33:02 PM PDT 24
Finished Jul 01 04:33:13 PM PDT 24
Peak memory 198552 kb
Host smart-a821ae0b-231b-4e2c-9568-8bc2ae606583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029652125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2029652125
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1390621377
Short name T315
Test name
Test status
Simulation time 8320741675 ps
CPU time 12.44 seconds
Started Jul 01 04:32:52 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 198196 kb
Host smart-24422776-8ec0-42cf-9b64-1b79fd7f5829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390621377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1390621377
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1803742506
Short name T280
Test name
Test status
Simulation time 430808085 ps
CPU time 0.87 seconds
Started Jul 01 04:33:02 PM PDT 24
Finished Jul 01 04:33:12 PM PDT 24
Peak memory 195604 kb
Host smart-94594a42-31fc-4c5c-ba46-b6024ff980d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803742506 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1803742506
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2112455620
Short name T386
Test name
Test status
Simulation time 363320893 ps
CPU time 0.9 seconds
Started Jul 01 04:33:00 PM PDT 24
Finished Jul 01 04:33:10 PM PDT 24
Peak memory 193452 kb
Host smart-13349c2b-2741-4736-9785-bc2f9a1dba25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112455620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2112455620
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3567611279
Short name T327
Test name
Test status
Simulation time 550945273 ps
CPU time 0.69 seconds
Started Jul 01 04:33:01 PM PDT 24
Finished Jul 01 04:33:10 PM PDT 24
Peak memory 193008 kb
Host smart-3542cb18-14f3-40e0-92c8-485e6ab9ed81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567611279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3567611279
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.981302962
Short name T373
Test name
Test status
Simulation time 1195139609 ps
CPU time 1.35 seconds
Started Jul 01 04:33:02 PM PDT 24
Finished Jul 01 04:33:12 PM PDT 24
Peak memory 183648 kb
Host smart-6d8c844c-0f11-401f-b6b5-df3e42558c20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981302962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.981302962
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.738116344
Short name T391
Test name
Test status
Simulation time 504134165 ps
CPU time 2.2 seconds
Started Jul 01 04:32:58 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 198604 kb
Host smart-4bcfd833-d34a-4757-8e04-872df0fed6dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738116344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.738116344
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.707371496
Short name T302
Test name
Test status
Simulation time 4333912443 ps
CPU time 4.2 seconds
Started Jul 01 04:32:58 PM PDT 24
Finished Jul 01 04:33:12 PM PDT 24
Peak memory 197624 kb
Host smart-03c2acd6-cc35-4600-9af9-3675696b34c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707371496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.707371496
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2728741673
Short name T286
Test name
Test status
Simulation time 419491109 ps
CPU time 0.83 seconds
Started Jul 01 04:33:04 PM PDT 24
Finished Jul 01 04:33:13 PM PDT 24
Peak memory 196016 kb
Host smart-d0ef6bff-1805-4a1b-8ef4-389991f92293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728741673 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2728741673
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2461803825
Short name T320
Test name
Test status
Simulation time 465999791 ps
CPU time 0.77 seconds
Started Jul 01 04:33:03 PM PDT 24
Finished Jul 01 04:33:12 PM PDT 24
Peak memory 191920 kb
Host smart-a2d14908-0623-4cbb-ba85-bae0ca7cb13b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461803825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2461803825
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.4166140632
Short name T392
Test name
Test status
Simulation time 498035158 ps
CPU time 0.88 seconds
Started Jul 01 04:33:07 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 192996 kb
Host smart-02b59676-0125-4754-ad6b-8bbd4c123252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166140632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.4166140632
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1713129347
Short name T329
Test name
Test status
Simulation time 2438854301 ps
CPU time 2.44 seconds
Started Jul 01 04:33:08 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 191928 kb
Host smart-faa6da25-942a-4b08-9cd5-9d7aed847ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713129347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1713129347
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3306918433
Short name T274
Test name
Test status
Simulation time 456795471 ps
CPU time 1.78 seconds
Started Jul 01 04:33:02 PM PDT 24
Finished Jul 01 04:33:11 PM PDT 24
Peak memory 198516 kb
Host smart-cc5a754b-187d-432a-8b88-f82ad1a91cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306918433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3306918433
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2597365751
Short name T372
Test name
Test status
Simulation time 8349305523 ps
CPU time 2.96 seconds
Started Jul 01 04:33:07 PM PDT 24
Finished Jul 01 04:33:18 PM PDT 24
Peak memory 198176 kb
Host smart-4d982d65-72e1-43a0-ace3-4fd64591131a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597365751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2597365751
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1204102633
Short name T51
Test name
Test status
Simulation time 612259282 ps
CPU time 1.16 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:45 PM PDT 24
Peak memory 194344 kb
Host smart-b1596c64-7294-4e03-8372-db35c9a2e0b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204102633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1204102633
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1573035230
Short name T331
Test name
Test status
Simulation time 14010736152 ps
CPU time 20.19 seconds
Started Jul 01 04:32:47 PM PDT 24
Finished Jul 01 04:33:19 PM PDT 24
Peak memory 196260 kb
Host smart-d9b72dee-9568-431c-a458-19a505336f66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573035230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1573035230
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3318853078
Short name T357
Test name
Test status
Simulation time 781785870 ps
CPU time 1.01 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:47 PM PDT 24
Peak memory 191952 kb
Host smart-2e21afd4-8e87-47c7-a579-2a3e5d24c724
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318853078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3318853078
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1561193559
Short name T324
Test name
Test status
Simulation time 578360401 ps
CPU time 1.39 seconds
Started Jul 01 04:32:39 PM PDT 24
Finished Jul 01 04:32:54 PM PDT 24
Peak memory 195964 kb
Host smart-2f2ea3e1-e4ac-41c5-89aa-4056e7bc8b4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561193559 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1561193559
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3861416199
Short name T55
Test name
Test status
Simulation time 474764136 ps
CPU time 1.21 seconds
Started Jul 01 04:32:56 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 193212 kb
Host smart-103ee560-908d-4620-bf93-95de01e96715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861416199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3861416199
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1538953947
Short name T338
Test name
Test status
Simulation time 428269815 ps
CPU time 0.88 seconds
Started Jul 01 04:32:48 PM PDT 24
Finished Jul 01 04:33:00 PM PDT 24
Peak memory 193100 kb
Host smart-6b3a8432-7c49-422a-ab61-319aab62b139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538953947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1538953947
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3271393231
Short name T383
Test name
Test status
Simulation time 366620650 ps
CPU time 0.82 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 183572 kb
Host smart-6b089d1a-fdce-4302-a328-ef51d80ac07d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271393231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3271393231
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1114825406
Short name T394
Test name
Test status
Simulation time 379095591 ps
CPU time 0.63 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:46 PM PDT 24
Peak memory 183704 kb
Host smart-48cc299f-ae88-41d4-a753-d785f68c3fea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114825406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1114825406
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2795570408
Short name T317
Test name
Test status
Simulation time 1545603694 ps
CPU time 2.61 seconds
Started Jul 01 04:32:40 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 193120 kb
Host smart-c1c51041-9670-4dc1-803c-0104e214a00e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795570408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2795570408
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4203018423
Short name T289
Test name
Test status
Simulation time 411696816 ps
CPU time 1.75 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:48 PM PDT 24
Peak memory 198504 kb
Host smart-0c69e235-3893-4cf7-bf52-724d00afea99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203018423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4203018423
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.31206528
Short name T374
Test name
Test status
Simulation time 478537720 ps
CPU time 1.27 seconds
Started Jul 01 04:32:59 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 183796 kb
Host smart-8065d605-ce4b-4d5f-a1cf-84f0da553a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31206528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.31206528
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1287530952
Short name T342
Test name
Test status
Simulation time 489072244 ps
CPU time 0.87 seconds
Started Jul 01 04:33:03 PM PDT 24
Finished Jul 01 04:33:12 PM PDT 24
Peak memory 183676 kb
Host smart-5dc7cd49-0e2e-4ac2-ac89-54518dc2ddfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287530952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1287530952
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4114413694
Short name T350
Test name
Test status
Simulation time 299220935 ps
CPU time 1.03 seconds
Started Jul 01 04:33:08 PM PDT 24
Finished Jul 01 04:33:16 PM PDT 24
Peak memory 193196 kb
Host smart-966e070d-56a4-4299-b17d-e43a19a8b9f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114413694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4114413694
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2247293741
Short name T417
Test name
Test status
Simulation time 422456816 ps
CPU time 0.7 seconds
Started Jul 01 04:33:06 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 183896 kb
Host smart-47a18b40-e288-4a0c-88a4-dc96e1844a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247293741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2247293741
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2175571537
Short name T311
Test name
Test status
Simulation time 552503517 ps
CPU time 0.62 seconds
Started Jul 01 04:33:05 PM PDT 24
Finished Jul 01 04:33:13 PM PDT 24
Peak memory 192996 kb
Host smart-9f43d007-7a55-4b3d-8e92-98f32a5cb9b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175571537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2175571537
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1568199455
Short name T276
Test name
Test status
Simulation time 506611328 ps
CPU time 0.89 seconds
Started Jul 01 04:33:06 PM PDT 24
Finished Jul 01 04:33:14 PM PDT 24
Peak memory 183788 kb
Host smart-2110647e-8f19-477b-be6d-02417c4e9b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568199455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1568199455
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4106836379
Short name T358
Test name
Test status
Simulation time 302410506 ps
CPU time 0.67 seconds
Started Jul 01 04:33:01 PM PDT 24
Finished Jul 01 04:33:10 PM PDT 24
Peak memory 183792 kb
Host smart-2ee3cf73-4630-4e86-80c3-2e660126e7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106836379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4106836379
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.172173412
Short name T399
Test name
Test status
Simulation time 276222783 ps
CPU time 0.96 seconds
Started Jul 01 04:33:07 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 183684 kb
Host smart-4daca795-6bcf-44b0-b7a8-1adb061f0b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172173412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.172173412
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3013682745
Short name T345
Test name
Test status
Simulation time 436048843 ps
CPU time 0.9 seconds
Started Jul 01 04:33:07 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 183680 kb
Host smart-eaa054a3-15f4-4618-9765-ed06405d24a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013682745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3013682745
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1120462028
Short name T355
Test name
Test status
Simulation time 468099652 ps
CPU time 1.13 seconds
Started Jul 01 04:33:09 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 183876 kb
Host smart-d098babe-f694-4711-8372-ae0629a0e26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120462028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1120462028
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2395569826
Short name T57
Test name
Test status
Simulation time 647298220 ps
CPU time 2.1 seconds
Started Jul 01 04:32:47 PM PDT 24
Finished Jul 01 04:33:01 PM PDT 24
Peak memory 194820 kb
Host smart-efd543f9-702f-4484-bfbf-b8d9a189b1f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395569826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2395569826
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1175862856
Short name T53
Test name
Test status
Simulation time 7336889891 ps
CPU time 6.97 seconds
Started Jul 01 04:32:40 PM PDT 24
Finished Jul 01 04:33:01 PM PDT 24
Peak memory 196604 kb
Host smart-401c6da6-6937-46d4-91fe-9ebde6095d8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175862856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1175862856
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2551472051
Short name T410
Test name
Test status
Simulation time 790327778 ps
CPU time 0.83 seconds
Started Jul 01 04:32:41 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 183672 kb
Host smart-04d4041b-f2d4-4fff-992a-5f223eac5bdf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551472051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2551472051
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2366568343
Short name T296
Test name
Test status
Simulation time 537667697 ps
CPU time 0.98 seconds
Started Jul 01 04:32:40 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 195464 kb
Host smart-8165f850-bac1-4355-9f8e-a6c12a17c2ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366568343 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2366568343
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.948196986
Short name T407
Test name
Test status
Simulation time 479525222 ps
CPU time 0.74 seconds
Started Jul 01 04:32:39 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 193308 kb
Host smart-26505c53-c899-4fa6-8a27-9b63c5887f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948196986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.948196986
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1294221541
Short name T285
Test name
Test status
Simulation time 367414834 ps
CPU time 0.72 seconds
Started Jul 01 04:32:39 PM PDT 24
Finished Jul 01 04:32:54 PM PDT 24
Peak memory 183788 kb
Host smart-6b1e9ee1-5603-4e66-9897-2796f0ea35a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294221541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1294221541
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3255399209
Short name T330
Test name
Test status
Simulation time 304457157 ps
CPU time 0.72 seconds
Started Jul 01 04:32:35 PM PDT 24
Finished Jul 01 04:32:50 PM PDT 24
Peak memory 183584 kb
Host smart-f98db05c-dac8-4142-8bce-fdcb46cdae57
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255399209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3255399209
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.783304655
Short name T278
Test name
Test status
Simulation time 504459569 ps
CPU time 0.61 seconds
Started Jul 01 04:32:35 PM PDT 24
Finished Jul 01 04:32:50 PM PDT 24
Peak memory 183704 kb
Host smart-0bdc3348-3fae-409b-b63c-53ec5ceac092
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783304655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.783304655
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.751488969
Short name T414
Test name
Test status
Simulation time 2383239568 ps
CPU time 1.13 seconds
Started Jul 01 04:32:35 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 195240 kb
Host smart-4e46076d-a38c-4f34-bfaf-bf082fad9277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751488969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.751488969
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.485160080
Short name T403
Test name
Test status
Simulation time 489498159 ps
CPU time 1.51 seconds
Started Jul 01 04:32:35 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 198612 kb
Host smart-a0a19470-64e9-4115-a460-c9be6e800dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485160080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.485160080
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3959322169
Short name T401
Test name
Test status
Simulation time 4913669442 ps
CPU time 2.25 seconds
Started Jul 01 04:32:36 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 197808 kb
Host smart-80d720cc-6f06-4714-8faa-65c7b350ebb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959322169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3959322169
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.4090922572
Short name T380
Test name
Test status
Simulation time 442899837 ps
CPU time 0.74 seconds
Started Jul 01 04:33:08 PM PDT 24
Finished Jul 01 04:33:16 PM PDT 24
Peak memory 183896 kb
Host smart-aff0d3b0-957d-4a59-b6b8-9d6329ffc86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090922572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.4090922572
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1403167256
Short name T381
Test name
Test status
Simulation time 418744753 ps
CPU time 0.87 seconds
Started Jul 01 04:33:09 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 183676 kb
Host smart-7acc4aa8-0d83-4dde-8fa1-96575aba081f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403167256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1403167256
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3358496503
Short name T295
Test name
Test status
Simulation time 468841920 ps
CPU time 0.66 seconds
Started Jul 01 04:33:09 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 183692 kb
Host smart-069b4fb3-70cc-4288-bacd-0cefcb4dfd51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358496503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3358496503
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3225936320
Short name T297
Test name
Test status
Simulation time 521163551 ps
CPU time 1.24 seconds
Started Jul 01 04:33:10 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 183788 kb
Host smart-ef5456d7-5b0d-43b7-892a-8775fb300de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225936320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3225936320
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4146420469
Short name T314
Test name
Test status
Simulation time 375494003 ps
CPU time 1.13 seconds
Started Jul 01 04:33:10 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 192900 kb
Host smart-3d498688-73ae-44c1-9254-551652c4bc45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146420469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4146420469
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.558490207
Short name T353
Test name
Test status
Simulation time 545830411 ps
CPU time 0.65 seconds
Started Jul 01 04:33:09 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 183788 kb
Host smart-58ebde5e-929a-411a-b111-1717e6590a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558490207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.558490207
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2664898800
Short name T287
Test name
Test status
Simulation time 328011536 ps
CPU time 0.76 seconds
Started Jul 01 04:33:19 PM PDT 24
Finished Jul 01 04:33:21 PM PDT 24
Peak memory 192908 kb
Host smart-d8d3d626-2cff-4040-ae0f-229f2254836e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664898800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2664898800
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.950585094
Short name T349
Test name
Test status
Simulation time 499769517 ps
CPU time 0.69 seconds
Started Jul 01 04:33:08 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 183664 kb
Host smart-3f4af5de-e13d-4f61-a9f2-e3b625f5c8bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950585094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.950585094
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1308220158
Short name T332
Test name
Test status
Simulation time 288393438 ps
CPU time 0.61 seconds
Started Jul 01 04:33:07 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 183656 kb
Host smart-1260f549-8a79-46a8-922a-da8c22efe29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308220158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1308220158
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3073471243
Short name T352
Test name
Test status
Simulation time 473480931 ps
CPU time 1.16 seconds
Started Jul 01 04:33:08 PM PDT 24
Finished Jul 01 04:33:16 PM PDT 24
Peak memory 183788 kb
Host smart-b5dc9c92-7aac-4ad3-8256-557f73915fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073471243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3073471243
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1032061347
Short name T56
Test name
Test status
Simulation time 530437122 ps
CPU time 0.7 seconds
Started Jul 01 04:32:35 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 183932 kb
Host smart-81dfc02f-426c-42f2-9381-1d5e664d6609
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032061347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1032061347
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2980027281
Short name T335
Test name
Test status
Simulation time 6996911334 ps
CPU time 3.04 seconds
Started Jul 01 04:32:37 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 183928 kb
Host smart-02d1a9bd-8ba6-4451-a1e7-e1a27a98b888
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980027281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2980027281
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4214230391
Short name T334
Test name
Test status
Simulation time 902160207 ps
CPU time 0.96 seconds
Started Jul 01 04:32:47 PM PDT 24
Finished Jul 01 04:33:00 PM PDT 24
Peak memory 193136 kb
Host smart-f1304451-b064-4378-855b-309f9664fc7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214230391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.4214230391
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1135263560
Short name T406
Test name
Test status
Simulation time 636183197 ps
CPU time 0.96 seconds
Started Jul 01 04:32:39 PM PDT 24
Finished Jul 01 04:32:54 PM PDT 24
Peak memory 195948 kb
Host smart-b82d13a5-6b3d-490c-a918-2d73ecc4361a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135263560 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1135263560
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2822401101
Short name T62
Test name
Test status
Simulation time 560583042 ps
CPU time 0.6 seconds
Started Jul 01 04:32:52 PM PDT 24
Finished Jul 01 04:33:03 PM PDT 24
Peak memory 191856 kb
Host smart-317c7d6a-8e63-438a-ae4d-c541ae7d2202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822401101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2822401101
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3372356019
Short name T298
Test name
Test status
Simulation time 442045872 ps
CPU time 1.15 seconds
Started Jul 01 04:32:43 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 192896 kb
Host smart-b47be70c-2453-44d2-8099-5ed7671406f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372356019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3372356019
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.825199204
Short name T326
Test name
Test status
Simulation time 346136497 ps
CPU time 0.82 seconds
Started Jul 01 04:32:46 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 183916 kb
Host smart-9825d6d1-1d66-4d58-b324-e76756fb8896
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825199204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.825199204
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1351145112
Short name T333
Test name
Test status
Simulation time 279917963 ps
CPU time 0.7 seconds
Started Jul 01 04:32:39 PM PDT 24
Finished Jul 01 04:32:54 PM PDT 24
Peak memory 183700 kb
Host smart-7872a058-1203-4ee9-85e5-f145ed57ce06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351145112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1351145112
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.837726019
Short name T412
Test name
Test status
Simulation time 2484082314 ps
CPU time 1.46 seconds
Started Jul 01 04:32:34 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 193768 kb
Host smart-313d1221-307b-47ba-b6f7-ae08f104c854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837726019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.837726019
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.261206893
Short name T277
Test name
Test status
Simulation time 592112681 ps
CPU time 1.7 seconds
Started Jul 01 04:32:36 PM PDT 24
Finished Jul 01 04:32:52 PM PDT 24
Peak memory 198628 kb
Host smart-cfd747c0-6b0a-4384-80a7-be1016c5d706
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261206893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.261206893
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2942033670
Short name T310
Test name
Test status
Simulation time 4444532050 ps
CPU time 2.12 seconds
Started Jul 01 04:32:39 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 196388 kb
Host smart-76bcfcb9-43fa-4724-95ff-d130e9ad09ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942033670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2942033670
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3785744216
Short name T305
Test name
Test status
Simulation time 536313722 ps
CPU time 0.73 seconds
Started Jul 01 04:33:10 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 183804 kb
Host smart-823f7948-6e84-4a4e-8976-a9fa506e9ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785744216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3785744216
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2546801461
Short name T344
Test name
Test status
Simulation time 435637059 ps
CPU time 0.93 seconds
Started Jul 01 04:33:11 PM PDT 24
Finished Jul 01 04:33:18 PM PDT 24
Peak memory 183788 kb
Host smart-84aaeb73-70d9-41dd-a2d9-3fe0e7832005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546801461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2546801461
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.344683345
Short name T340
Test name
Test status
Simulation time 380321908 ps
CPU time 1.11 seconds
Started Jul 01 04:33:09 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 183696 kb
Host smart-c147790f-c9bc-4f5c-ab2a-c8c5ee5d7f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344683345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.344683345
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2481771266
Short name T291
Test name
Test status
Simulation time 530535722 ps
CPU time 0.73 seconds
Started Jul 01 04:33:09 PM PDT 24
Finished Jul 01 04:33:16 PM PDT 24
Peak memory 193008 kb
Host smart-7c395cd0-a990-4dc2-9732-edc8e26a6fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481771266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2481771266
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3209462826
Short name T366
Test name
Test status
Simulation time 506052421 ps
CPU time 1.23 seconds
Started Jul 01 04:33:12 PM PDT 24
Finished Jul 01 04:33:19 PM PDT 24
Peak memory 193020 kb
Host smart-e95d18d0-0a7a-4ee6-89fa-41e684535264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209462826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3209462826
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3577392836
Short name T273
Test name
Test status
Simulation time 452168306 ps
CPU time 0.68 seconds
Started Jul 01 04:33:08 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 192904 kb
Host smart-adcee3fc-6481-4073-850f-af24d894cb95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577392836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3577392836
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2210638328
Short name T313
Test name
Test status
Simulation time 539059007 ps
CPU time 0.56 seconds
Started Jul 01 04:33:18 PM PDT 24
Finished Jul 01 04:33:21 PM PDT 24
Peak memory 183688 kb
Host smart-930a63e8-9526-41ae-af01-11e91ee84ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210638328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2210638328
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.966149102
Short name T408
Test name
Test status
Simulation time 302349908 ps
CPU time 0.98 seconds
Started Jul 01 04:33:10 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 183728 kb
Host smart-e54c11a2-94db-40fd-bde8-331467244724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966149102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.966149102
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3431580509
Short name T418
Test name
Test status
Simulation time 475387827 ps
CPU time 0.71 seconds
Started Jul 01 04:33:10 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 183976 kb
Host smart-b67dbd28-4bdf-4bb0-942c-f63931ef8701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431580509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3431580509
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3789729081
Short name T283
Test name
Test status
Simulation time 380634051 ps
CPU time 1.1 seconds
Started Jul 01 04:33:10 PM PDT 24
Finished Jul 01 04:33:17 PM PDT 24
Peak memory 193124 kb
Host smart-9a564122-54d5-4b66-99a1-26ec1188ab3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789729081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3789729081
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.54860366
Short name T284
Test name
Test status
Simulation time 604578899 ps
CPU time 1.23 seconds
Started Jul 01 04:32:42 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 197140 kb
Host smart-36182ce7-2f6b-4038-8a33-483df903304c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54860366 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.54860366
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1106084713
Short name T50
Test name
Test status
Simulation time 436000849 ps
CPU time 1.27 seconds
Started Jul 01 04:32:47 PM PDT 24
Finished Jul 01 04:33:00 PM PDT 24
Peak memory 193412 kb
Host smart-08b4f430-c147-49f4-a259-372b260c4e30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106084713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1106084713
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1456949917
Short name T382
Test name
Test status
Simulation time 468567020 ps
CPU time 0.99 seconds
Started Jul 01 04:32:52 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 192992 kb
Host smart-1d82b3e2-0d8f-4634-8f57-d75790855a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456949917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1456949917
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3846992913
Short name T65
Test name
Test status
Simulation time 1078384338 ps
CPU time 1.79 seconds
Started Jul 01 04:32:51 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 194004 kb
Host smart-a60a0c7c-f89e-4529-9341-0b0b21d31b0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846992913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3846992913
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1397645746
Short name T368
Test name
Test status
Simulation time 644146592 ps
CPU time 1.87 seconds
Started Jul 01 04:32:44 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 198644 kb
Host smart-6a273b21-af17-4666-be80-8cc672087938
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397645746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1397645746
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2859479620
Short name T182
Test name
Test status
Simulation time 4194670117 ps
CPU time 6.46 seconds
Started Jul 01 04:32:36 PM PDT 24
Finished Jul 01 04:32:58 PM PDT 24
Peak memory 196768 kb
Host smart-5630812e-bb62-45ff-9ccb-8bb642ab0c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859479620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2859479620
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3339674664
Short name T301
Test name
Test status
Simulation time 555114856 ps
CPU time 0.89 seconds
Started Jul 01 04:32:40 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 196440 kb
Host smart-c0c4d83e-5339-44fb-bf0f-3dab051e6d89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339674664 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3339674664
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3120137459
Short name T416
Test name
Test status
Simulation time 523694340 ps
CPU time 0.75 seconds
Started Jul 01 04:32:43 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 192880 kb
Host smart-75c360fa-269e-4b28-b119-ea80fca0cae1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120137459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3120137459
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2419111524
Short name T279
Test name
Test status
Simulation time 466086772 ps
CPU time 1.14 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:03 PM PDT 24
Peak memory 183960 kb
Host smart-db48a4ee-3efd-4c1f-b91a-5aec9848f50e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419111524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2419111524
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1938849126
Short name T321
Test name
Test status
Simulation time 2308188856 ps
CPU time 5.71 seconds
Started Jul 01 04:32:40 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 194060 kb
Host smart-a7c5b236-3dc1-4046-9cce-d8906daef22d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938849126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1938849126
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1679192441
Short name T281
Test name
Test status
Simulation time 502980169 ps
CPU time 1.74 seconds
Started Jul 01 04:32:44 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 198676 kb
Host smart-4aa04ff1-9e18-4954-b9dd-17ddf6336ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679192441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1679192441
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1083746966
Short name T395
Test name
Test status
Simulation time 4189834431 ps
CPU time 6.35 seconds
Started Jul 01 04:32:45 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 197692 kb
Host smart-bac204d9-e0b6-466d-9d5a-9d684d332cc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083746966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1083746966
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2719578088
Short name T300
Test name
Test status
Simulation time 393608751 ps
CPU time 1.16 seconds
Started Jul 01 04:32:40 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 195664 kb
Host smart-0c2a94b9-96a6-40a2-a6f4-7bbdaf1175d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719578088 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2719578088
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.244465406
Short name T367
Test name
Test status
Simulation time 428676750 ps
CPU time 1.07 seconds
Started Jul 01 04:32:43 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 193180 kb
Host smart-33ae3c24-12f8-4aa3-a563-7f91014411f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244465406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.244465406
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4042266902
Short name T337
Test name
Test status
Simulation time 519244791 ps
CPU time 0.83 seconds
Started Jul 01 04:32:45 PM PDT 24
Finished Jul 01 04:32:58 PM PDT 24
Peak memory 183796 kb
Host smart-bb718c38-d645-467c-a034-be597f51e22c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042266902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4042266902
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2726124311
Short name T328
Test name
Test status
Simulation time 1644585269 ps
CPU time 1.22 seconds
Started Jul 01 04:32:40 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 193528 kb
Host smart-66074177-5337-40fa-8537-0477edaf0e5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726124311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2726124311
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3428048487
Short name T402
Test name
Test status
Simulation time 544883693 ps
CPU time 2.27 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 198688 kb
Host smart-aa310206-2353-4292-9cd4-76faaefd6908
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428048487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3428048487
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2081449870
Short name T38
Test name
Test status
Simulation time 10129027298 ps
CPU time 2.56 seconds
Started Jul 01 04:32:53 PM PDT 24
Finished Jul 01 04:33:06 PM PDT 24
Peak memory 197968 kb
Host smart-2ea825c4-f8c1-45f1-be54-56a20bb1a9da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081449870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2081449870
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.959398818
Short name T186
Test name
Test status
Simulation time 372528704 ps
CPU time 1.19 seconds
Started Jul 01 04:32:55 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 196036 kb
Host smart-f68663c2-6535-41e6-8620-3ad9ab358a6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959398818 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.959398818
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1071766629
Short name T293
Test name
Test status
Simulation time 320660528 ps
CPU time 0.73 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 192976 kb
Host smart-bf2a9dde-3862-4087-8685-b89f8bf116a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071766629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1071766629
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2564830236
Short name T375
Test name
Test status
Simulation time 579003970 ps
CPU time 0.61 seconds
Started Jul 01 04:32:43 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 183800 kb
Host smart-176ee4fc-844a-44ce-a7c3-d3515acdd0b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564830236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2564830236
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.528611964
Short name T63
Test name
Test status
Simulation time 1468028648 ps
CPU time 2.22 seconds
Started Jul 01 04:32:41 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 193468 kb
Host smart-38ae0d46-0ec1-4828-9352-603a57693fdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528611964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.528611964
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.84575483
Short name T363
Test name
Test status
Simulation time 405927370 ps
CPU time 1.81 seconds
Started Jul 01 04:32:41 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 198508 kb
Host smart-ba28fe4e-9d15-4304-9a6f-5b865136dc18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84575483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.84575483
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1318472037
Short name T385
Test name
Test status
Simulation time 4510691173 ps
CPU time 4.39 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:06 PM PDT 24
Peak memory 197776 kb
Host smart-1fb0e432-2d34-47a0-810e-44a12c860c52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318472037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1318472037
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3282431312
Short name T351
Test name
Test status
Simulation time 384256636 ps
CPU time 1.33 seconds
Started Jul 01 04:32:55 PM PDT 24
Finished Jul 01 04:33:06 PM PDT 24
Peak memory 195352 kb
Host smart-219b1cde-fcc1-4965-8f73-41237e3dc735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282431312 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3282431312
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1787282623
Short name T34
Test name
Test status
Simulation time 476542029 ps
CPU time 0.77 seconds
Started Jul 01 04:32:42 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 193412 kb
Host smart-77877ce4-e2cd-4532-b07b-e7bda8080f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787282623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1787282623
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3167562765
Short name T341
Test name
Test status
Simulation time 494787985 ps
CPU time 1.2 seconds
Started Jul 01 04:32:49 PM PDT 24
Finished Jul 01 04:33:01 PM PDT 24
Peak memory 183792 kb
Host smart-eb33ad3c-629d-443a-811d-7a18675486aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167562765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3167562765
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1525095795
Short name T61
Test name
Test status
Simulation time 3206003935 ps
CPU time 2.71 seconds
Started Jul 01 04:32:55 PM PDT 24
Finished Jul 01 04:33:08 PM PDT 24
Peak memory 194332 kb
Host smart-0e2b3c75-c404-4077-b1b5-291a9412afaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525095795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1525095795
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.826835322
Short name T346
Test name
Test status
Simulation time 387529147 ps
CPU time 2.22 seconds
Started Jul 01 04:32:50 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 198584 kb
Host smart-c45284b4-c8d0-40d1-a48c-6b95a146bf84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826835322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.826835322
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2399346078
Short name T398
Test name
Test status
Simulation time 8516164521 ps
CPU time 2.57 seconds
Started Jul 01 04:32:57 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 198252 kb
Host smart-5cc56f20-81d7-4be6-ad2a-eceb67b781e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399346078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2399346078
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.963779637
Short name T260
Test name
Test status
Simulation time 13390405351 ps
CPU time 4.83 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:33:58 PM PDT 24
Peak memory 191568 kb
Host smart-c7c9b513-9ed3-407e-bf31-fa90f6a75f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963779637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.963779637
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.822664507
Short name T192
Test name
Test status
Simulation time 574722248 ps
CPU time 1.42 seconds
Started Jul 01 04:33:47 PM PDT 24
Finished Jul 01 04:33:50 PM PDT 24
Peak memory 196408 kb
Host smart-9c7b73d5-bacc-4506-b1ac-d0723f9add20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822664507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.822664507
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2933121242
Short name T272
Test name
Test status
Simulation time 25901022065 ps
CPU time 4.39 seconds
Started Jul 01 04:33:41 PM PDT 24
Finished Jul 01 04:33:47 PM PDT 24
Peak memory 191508 kb
Host smart-febbc47c-00d4-431e-a786-1e85878c61c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933121242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2933121242
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.572175072
Short name T15
Test name
Test status
Simulation time 4567394863 ps
CPU time 2.6 seconds
Started Jul 01 04:33:53 PM PDT 24
Finished Jul 01 04:33:58 PM PDT 24
Peak memory 215804 kb
Host smart-31e216f9-d813-4734-92f6-66b4cccb59b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572175072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.572175072
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3966935852
Short name T195
Test name
Test status
Simulation time 436149597 ps
CPU time 0.93 seconds
Started Jul 01 04:33:40 PM PDT 24
Finished Jul 01 04:33:43 PM PDT 24
Peak memory 191348 kb
Host smart-6564aeba-218b-411c-bd3f-5c7fcf72d1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966935852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3966935852
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.100112476
Short name T22
Test name
Test status
Simulation time 58003643965 ps
CPU time 87.14 seconds
Started Jul 01 04:33:55 PM PDT 24
Finished Jul 01 04:35:24 PM PDT 24
Peak memory 191644 kb
Host smart-076e4b67-e7c1-4802-b51a-d90062fe64b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100112476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.100112476
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3401131075
Short name T254
Test name
Test status
Simulation time 379877795 ps
CPU time 0.85 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:33:54 PM PDT 24
Peak memory 196440 kb
Host smart-6ff119d5-e39f-485e-a0ba-8eb8c7b355dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401131075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3401131075
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2423249701
Short name T190
Test name
Test status
Simulation time 16784536091 ps
CPU time 23.24 seconds
Started Jul 01 04:33:59 PM PDT 24
Finished Jul 01 04:34:25 PM PDT 24
Peak memory 196688 kb
Host smart-5d666904-0594-4372-8602-9abd62b1853f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423249701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2423249701
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2539904949
Short name T243
Test name
Test status
Simulation time 465780288 ps
CPU time 1.16 seconds
Started Jul 01 04:33:52 PM PDT 24
Finished Jul 01 04:33:56 PM PDT 24
Peak memory 191592 kb
Host smart-f083634f-29f7-4c48-b46b-3453fb090fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539904949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2539904949
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3573022364
Short name T218
Test name
Test status
Simulation time 33512787438 ps
CPU time 44.13 seconds
Started Jul 01 04:33:54 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 191504 kb
Host smart-93a0e454-fb97-40d7-9045-91e27e3cc4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573022364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3573022364
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.4148051083
Short name T213
Test name
Test status
Simulation time 454010379 ps
CPU time 0.67 seconds
Started Jul 01 04:33:47 PM PDT 24
Finished Jul 01 04:33:49 PM PDT 24
Peak memory 196332 kb
Host smart-331d74e8-20e7-4fac-9530-f946c461d3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148051083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.4148051083
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3989340481
Short name T2
Test name
Test status
Simulation time 50378392942 ps
CPU time 20 seconds
Started Jul 01 04:33:46 PM PDT 24
Finished Jul 01 04:34:07 PM PDT 24
Peak memory 191624 kb
Host smart-65968c10-dc6f-4a50-a126-372056bbef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989340481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3989340481
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1960996405
Short name T244
Test name
Test status
Simulation time 428311375 ps
CPU time 1 seconds
Started Jul 01 04:33:59 PM PDT 24
Finished Jul 01 04:34:03 PM PDT 24
Peak memory 191512 kb
Host smart-25d3405d-a468-4467-a1ad-7ef8a960a043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960996405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1960996405
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3450693637
Short name T226
Test name
Test status
Simulation time 1452088947 ps
CPU time 1.06 seconds
Started Jul 01 04:33:49 PM PDT 24
Finished Jul 01 04:33:51 PM PDT 24
Peak memory 191500 kb
Host smart-cb6187e9-4d1d-4b59-80f8-2495da63c1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450693637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3450693637
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.930713678
Short name T267
Test name
Test status
Simulation time 449245001 ps
CPU time 0.76 seconds
Started Jul 01 04:33:54 PM PDT 24
Finished Jul 01 04:33:57 PM PDT 24
Peak memory 191400 kb
Host smart-afe64eb4-452e-4324-aab1-193038c6fe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930713678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.930713678
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2716387409
Short name T205
Test name
Test status
Simulation time 15939619120 ps
CPU time 6.72 seconds
Started Jul 01 04:33:54 PM PDT 24
Finished Jul 01 04:34:03 PM PDT 24
Peak memory 191532 kb
Host smart-73b2c0b7-38d1-48ff-9847-84382ff34840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716387409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2716387409
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.103969541
Short name T233
Test name
Test status
Simulation time 370730391 ps
CPU time 1.13 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:08 PM PDT 24
Peak memory 191508 kb
Host smart-39e5eac1-ff3c-482d-a17f-e553575dc559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103969541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.103969541
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2272359234
Short name T155
Test name
Test status
Simulation time 526925660 ps
CPU time 0.79 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 196252 kb
Host smart-dfd60e10-1433-4a0e-b48a-9e5cbc6c0438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272359234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2272359234
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1893556234
Short name T222
Test name
Test status
Simulation time 31953676330 ps
CPU time 20.95 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:34:14 PM PDT 24
Peak memory 191652 kb
Host smart-5ba8e604-dda5-4e98-9a88-e8815fe9781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893556234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1893556234
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1530181701
Short name T271
Test name
Test status
Simulation time 496176271 ps
CPU time 1.27 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:33:59 PM PDT 24
Peak memory 196436 kb
Host smart-86ac0709-e961-4b1b-b51c-fd9b2817bef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530181701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1530181701
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3961045330
Short name T240
Test name
Test status
Simulation time 10803425591 ps
CPU time 15.09 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:34:15 PM PDT 24
Peak memory 196672 kb
Host smart-9b023116-67ec-4d52-8c42-2b614036cd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961045330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3961045330
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2435512257
Short name T256
Test name
Test status
Simulation time 492900529 ps
CPU time 0.84 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:33:54 PM PDT 24
Peak memory 191776 kb
Host smart-1f883adc-576d-4abb-947e-4bc582d7f035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435512257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2435512257
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2491089335
Short name T227
Test name
Test status
Simulation time 6867635356 ps
CPU time 2.97 seconds
Started Jul 01 04:34:04 PM PDT 24
Finished Jul 01 04:34:12 PM PDT 24
Peak memory 191756 kb
Host smart-80fed665-3886-4f3a-9ecd-e47e058f6a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491089335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2491089335
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.493251689
Short name T198
Test name
Test status
Simulation time 402023876 ps
CPU time 1.07 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:34:08 PM PDT 24
Peak memory 191504 kb
Host smart-ff67f003-aaa2-4d75-8abe-29ce33f37e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493251689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.493251689
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1089104646
Short name T13
Test name
Test status
Simulation time 59973593186 ps
CPU time 20.7 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:34:24 PM PDT 24
Peak memory 196580 kb
Host smart-c25b293e-3a23-4951-8448-7d3c0ba0c8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089104646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1089104646
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3066160830
Short name T199
Test name
Test status
Simulation time 535043889 ps
CPU time 0.7 seconds
Started Jul 01 04:34:07 PM PDT 24
Finished Jul 01 04:34:14 PM PDT 24
Peak memory 196436 kb
Host smart-0abba691-e548-4766-9f6b-8109fdf0f96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066160830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3066160830
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.749087748
Short name T9
Test name
Test status
Simulation time 10990471294 ps
CPU time 15.04 seconds
Started Jul 01 04:33:41 PM PDT 24
Finished Jul 01 04:33:58 PM PDT 24
Peak memory 191632 kb
Host smart-e188680c-a813-4a5b-96e5-d526f4c04e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749087748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.749087748
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2048938219
Short name T17
Test name
Test status
Simulation time 3801479766 ps
CPU time 4.36 seconds
Started Jul 01 04:33:43 PM PDT 24
Finished Jul 01 04:33:49 PM PDT 24
Peak memory 215324 kb
Host smart-d216fd56-668e-46f1-ba63-aa9a408a1929
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048938219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2048938219
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2292895699
Short name T225
Test name
Test status
Simulation time 345767444 ps
CPU time 1.13 seconds
Started Jul 01 04:33:34 PM PDT 24
Finished Jul 01 04:33:37 PM PDT 24
Peak memory 191692 kb
Host smart-f4ffd1bd-b0bf-453a-85c9-ff79da6c56d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292895699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2292895699
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3160055580
Short name T219
Test name
Test status
Simulation time 33816194079 ps
CPU time 54.81 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 196556 kb
Host smart-9217c4fa-eec5-4dc6-9a37-2ef411fba6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160055580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3160055580
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2896039635
Short name T215
Test name
Test status
Simulation time 401216087 ps
CPU time 1.17 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:07 PM PDT 24
Peak memory 191572 kb
Host smart-6fc10214-4aca-4204-8a77-df59ada2d9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896039635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2896039635
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1892655584
Short name T220
Test name
Test status
Simulation time 14665398417 ps
CPU time 1.99 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:20 PM PDT 24
Peak memory 191652 kb
Host smart-8d2aba31-859f-4ee4-9357-71c043ae5ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892655584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1892655584
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.4168075352
Short name T201
Test name
Test status
Simulation time 606545662 ps
CPU time 1.03 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 196452 kb
Host smart-269372e7-c644-4d42-acce-adb0c7e143f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168075352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4168075352
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.4180003701
Short name T221
Test name
Test status
Simulation time 8243115090 ps
CPU time 5.69 seconds
Started Jul 01 04:34:06 PM PDT 24
Finished Jul 01 04:34:18 PM PDT 24
Peak memory 191568 kb
Host smart-850bfb8c-0db9-4be1-bc29-178d70862322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180003701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.4180003701
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1157863357
Short name T250
Test name
Test status
Simulation time 492833774 ps
CPU time 0.82 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:33:58 PM PDT 24
Peak memory 191520 kb
Host smart-ce2622a3-f5d2-42c3-a6f5-5fafea9717bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157863357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1157863357
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1403505621
Short name T241
Test name
Test status
Simulation time 30600257264 ps
CPU time 11.42 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 196568 kb
Host smart-61d44f90-e195-43f2-978a-bb90f8bf986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403505621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1403505621
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1199849552
Short name T234
Test name
Test status
Simulation time 480608836 ps
CPU time 0.92 seconds
Started Jul 01 04:33:55 PM PDT 24
Finished Jul 01 04:33:59 PM PDT 24
Peak memory 191572 kb
Host smart-4ab4e173-c570-4ca7-ab3d-7f23453532a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199849552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1199849552
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1153946364
Short name T172
Test name
Test status
Simulation time 557183122 ps
CPU time 0.68 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:34:00 PM PDT 24
Peak memory 196448 kb
Host smart-4d5a0b78-3569-439d-98db-3585e88d48ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153946364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1153946364
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1664281645
Short name T231
Test name
Test status
Simulation time 22838452464 ps
CPU time 21.38 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 191648 kb
Host smart-a09f8dbe-70b7-4c12-9cd2-5f068b277c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664281645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1664281645
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.833107342
Short name T188
Test name
Test status
Simulation time 511785677 ps
CPU time 0.79 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:34:04 PM PDT 24
Peak memory 191596 kb
Host smart-436e1fe7-76bb-4ec9-a92c-c3a4b758d36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833107342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.833107342
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3990311604
Short name T248
Test name
Test status
Simulation time 6442144338 ps
CPU time 10.89 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 191568 kb
Host smart-b0f33b26-f401-40ea-9ca6-8bfa6d2474a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990311604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3990311604
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2453378431
Short name T145
Test name
Test status
Simulation time 414321033 ps
CPU time 0.73 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:06 PM PDT 24
Peak memory 191512 kb
Host smart-4e50a8e6-ea2e-4b29-92d9-d4d3d4fdfe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453378431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2453378431
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3555767714
Short name T242
Test name
Test status
Simulation time 34153039502 ps
CPU time 13.84 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:34:21 PM PDT 24
Peak memory 191900 kb
Host smart-6642d7e9-56eb-4886-866f-b264ceebbc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555767714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3555767714
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2744655920
Short name T203
Test name
Test status
Simulation time 428679469 ps
CPU time 1.18 seconds
Started Jul 01 04:34:04 PM PDT 24
Finished Jul 01 04:34:09 PM PDT 24
Peak memory 191596 kb
Host smart-97d2b493-b46b-43fa-b13a-76211d6edac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744655920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2744655920
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1250577979
Short name T249
Test name
Test status
Simulation time 32855730393 ps
CPU time 12.48 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 191564 kb
Host smart-c1988525-0d11-4a1d-b36f-affb4917ecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250577979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1250577979
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.939475863
Short name T255
Test name
Test status
Simulation time 583947556 ps
CPU time 1.33 seconds
Started Jul 01 04:34:06 PM PDT 24
Finished Jul 01 04:34:14 PM PDT 24
Peak memory 191460 kb
Host smart-5ae9e4ea-f857-425d-b223-bde9bb0b3aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939475863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.939475863
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.143774863
Short name T235
Test name
Test status
Simulation time 33724990534 ps
CPU time 45.92 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:52 PM PDT 24
Peak memory 196660 kb
Host smart-a6d07521-12d6-4221-9608-c33e1fe723a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143774863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.143774863
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1797909124
Short name T246
Test name
Test status
Simulation time 465805078 ps
CPU time 0.93 seconds
Started Jul 01 04:33:48 PM PDT 24
Finished Jul 01 04:33:51 PM PDT 24
Peak memory 191596 kb
Host smart-2dafd9b7-b1eb-44ef-945b-9b2b639443a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797909124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1797909124
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2312344460
Short name T228
Test name
Test status
Simulation time 14106128084 ps
CPU time 10.39 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:34:18 PM PDT 24
Peak memory 191564 kb
Host smart-ce2e251e-9b25-4f22-b744-c04e50b2bd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312344460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2312344460
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2504419219
Short name T265
Test name
Test status
Simulation time 469891422 ps
CPU time 0.73 seconds
Started Jul 01 04:34:04 PM PDT 24
Finished Jul 01 04:34:10 PM PDT 24
Peak memory 191504 kb
Host smart-b81667e9-2402-4416-a194-308b4a63b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504419219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2504419219
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.247995721
Short name T217
Test name
Test status
Simulation time 9211914786 ps
CPU time 3.67 seconds
Started Jul 01 04:33:54 PM PDT 24
Finished Jul 01 04:34:00 PM PDT 24
Peak memory 191536 kb
Host smart-98b05281-fc0f-4f08-9a78-5d05b0d48283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247995721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.247995721
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4206382664
Short name T19
Test name
Test status
Simulation time 4366945456 ps
CPU time 2.37 seconds
Started Jul 01 04:33:42 PM PDT 24
Finished Jul 01 04:33:47 PM PDT 24
Peak memory 215876 kb
Host smart-774fe630-9b5a-4bd9-83fc-acb9aff79f61
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206382664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4206382664
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1258614028
Short name T264
Test name
Test status
Simulation time 416913199 ps
CPU time 0.89 seconds
Started Jul 01 04:34:05 PM PDT 24
Finished Jul 01 04:34:10 PM PDT 24
Peak memory 191584 kb
Host smart-b19209ad-a36d-4dc7-9535-5d416ed2e1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258614028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1258614028
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1020269941
Short name T237
Test name
Test status
Simulation time 21690693663 ps
CPU time 3.06 seconds
Started Jul 01 04:34:20 PM PDT 24
Finished Jul 01 04:34:33 PM PDT 24
Peak memory 196564 kb
Host smart-5b297691-1429-4022-adb2-faa26c7354bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020269941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1020269941
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1715469716
Short name T229
Test name
Test status
Simulation time 341083128 ps
CPU time 1.06 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:34:18 PM PDT 24
Peak memory 191596 kb
Host smart-8bd080fe-666f-4800-aa3c-22a873701aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715469716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1715469716
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.4069081083
Short name T197
Test name
Test status
Simulation time 13768246329 ps
CPU time 1.95 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:23 PM PDT 24
Peak memory 191572 kb
Host smart-406925a3-52f7-43a4-8826-94355abf2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069081083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.4069081083
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3378644861
Short name T211
Test name
Test status
Simulation time 426843304 ps
CPU time 0.9 seconds
Started Jul 01 04:34:20 PM PDT 24
Finished Jul 01 04:34:30 PM PDT 24
Peak memory 191504 kb
Host smart-6249d387-daf3-45ec-b891-0e2b2cd77093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378644861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3378644861
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3163006387
Short name T259
Test name
Test status
Simulation time 34284152270 ps
CPU time 5 seconds
Started Jul 01 04:34:08 PM PDT 24
Finished Jul 01 04:34:20 PM PDT 24
Peak memory 191568 kb
Host smart-a79d3b29-83a5-4aa8-83d8-97832f1b43ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163006387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3163006387
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.996815919
Short name T200
Test name
Test status
Simulation time 406615769 ps
CPU time 0.73 seconds
Started Jul 01 04:34:08 PM PDT 24
Finished Jul 01 04:34:15 PM PDT 24
Peak memory 196292 kb
Host smart-63ed5415-bf4f-4bfa-8f1f-ac8f6ad49663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996815919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.996815919
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1313688616
Short name T208
Test name
Test status
Simulation time 33209827816 ps
CPU time 12.88 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:34 PM PDT 24
Peak memory 191504 kb
Host smart-76e667c4-27dc-4aca-8781-f11f75be6330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313688616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1313688616
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.133991286
Short name T270
Test name
Test status
Simulation time 385771683 ps
CPU time 1.11 seconds
Started Jul 01 04:34:08 PM PDT 24
Finished Jul 01 04:34:17 PM PDT 24
Peak memory 196400 kb
Host smart-ef4dba4f-cae4-4496-a9c7-6c1de14aaf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133991286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.133991286
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.744728520
Short name T185
Test name
Test status
Simulation time 35700210695 ps
CPU time 46.58 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:35:02 PM PDT 24
Peak memory 191576 kb
Host smart-2e280e38-de67-4a55-87ed-99cd55a886a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744728520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.744728520
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.52348825
Short name T223
Test name
Test status
Simulation time 482591284 ps
CPU time 0.95 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:34:04 PM PDT 24
Peak memory 191576 kb
Host smart-bc2ff3f6-ad44-4806-a9f6-833d4ba9ff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52348825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.52348825
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3759139028
Short name T184
Test name
Test status
Simulation time 45561697846 ps
CPU time 8.38 seconds
Started Jul 01 04:34:12 PM PDT 24
Finished Jul 01 04:34:30 PM PDT 24
Peak memory 191632 kb
Host smart-c6d442fa-2497-4a78-9ba4-40bad1889630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759139028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3759139028
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3607467329
Short name T204
Test name
Test status
Simulation time 549880012 ps
CPU time 0.99 seconds
Started Jul 01 04:34:06 PM PDT 24
Finished Jul 01 04:34:13 PM PDT 24
Peak memory 196420 kb
Host smart-9a4f3e72-4919-4bac-be45-74ed4030b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607467329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3607467329
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3450295666
Short name T176
Test name
Test status
Simulation time 610021600 ps
CPU time 0.8 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:34:04 PM PDT 24
Peak memory 196372 kb
Host smart-f6d26625-a4bc-47af-a2cd-7694895d287d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450295666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3450295666
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2747862978
Short name T207
Test name
Test status
Simulation time 40051725720 ps
CPU time 54.99 seconds
Started Jul 01 04:33:57 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 196792 kb
Host smart-05ef3f3f-f43d-4f4a-8bf3-a15649b5b25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747862978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2747862978
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.775686861
Short name T202
Test name
Test status
Simulation time 509828040 ps
CPU time 1.3 seconds
Started Jul 01 04:34:05 PM PDT 24
Finished Jul 01 04:34:11 PM PDT 24
Peak memory 191440 kb
Host smart-a10f3582-9f2f-4bf4-8ef6-0b25e9ae18be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775686861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.775686861
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1096049788
Short name T257
Test name
Test status
Simulation time 58528823394 ps
CPU time 23.53 seconds
Started Jul 01 04:34:07 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 196896 kb
Host smart-2eea264e-3677-40c6-bcef-642660d7301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096049788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1096049788
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.408787123
Short name T266
Test name
Test status
Simulation time 511376599 ps
CPU time 1.15 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:20 PM PDT 24
Peak memory 196344 kb
Host smart-3dbc924a-b1b4-4a20-a352-06e3b99d0932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408787123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.408787123
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.66409855
Short name T268
Test name
Test status
Simulation time 42519450788 ps
CPU time 14.23 seconds
Started Jul 01 04:33:58 PM PDT 24
Finished Jul 01 04:34:21 PM PDT 24
Peak memory 196672 kb
Host smart-ace7d636-52c3-45e0-b103-11a199cb13d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66409855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.66409855
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1159897993
Short name T206
Test name
Test status
Simulation time 505525798 ps
CPU time 0.88 seconds
Started Jul 01 04:34:00 PM PDT 24
Finished Jul 01 04:34:04 PM PDT 24
Peak memory 191596 kb
Host smart-66d5b86f-7312-4f9e-bb75-0e2e06a03626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159897993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1159897993
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2719596428
Short name T164
Test name
Test status
Simulation time 459372061 ps
CPU time 0.77 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:34:18 PM PDT 24
Peak memory 196420 kb
Host smart-2ee8fe26-711b-423f-9ceb-a9b0e7741fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719596428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2719596428
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4132067620
Short name T44
Test name
Test status
Simulation time 33365977122 ps
CPU time 51.5 seconds
Started Jul 01 04:34:08 PM PDT 24
Finished Jul 01 04:35:07 PM PDT 24
Peak memory 191680 kb
Host smart-966827df-eb8f-422a-9576-aabba5294aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132067620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4132067620
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.867197839
Short name T28
Test name
Test status
Simulation time 549891538 ps
CPU time 0.75 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:21 PM PDT 24
Peak memory 196560 kb
Host smart-0a160e32-26c9-49e3-9509-864af1e506b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867197839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.867197839
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.274211402
Short name T245
Test name
Test status
Simulation time 29869833440 ps
CPU time 12.07 seconds
Started Jul 01 04:33:44 PM PDT 24
Finished Jul 01 04:33:57 PM PDT 24
Peak memory 196680 kb
Host smart-8e6e4b89-3314-413b-acda-953df036c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274211402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.274211402
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3178317068
Short name T18
Test name
Test status
Simulation time 7809508359 ps
CPU time 10.65 seconds
Started Jul 01 04:33:47 PM PDT 24
Finished Jul 01 04:33:59 PM PDT 24
Peak memory 215640 kb
Host smart-4588f80a-47ed-42f2-a461-35ba531ba585
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178317068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3178317068
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2848331941
Short name T269
Test name
Test status
Simulation time 476958301 ps
CPU time 1.24 seconds
Started Jul 01 04:33:50 PM PDT 24
Finished Jul 01 04:33:54 PM PDT 24
Peak memory 196380 kb
Host smart-24bc4781-2d02-4717-a6ef-005c660e0c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848331941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2848331941
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1847508240
Short name T263
Test name
Test status
Simulation time 40712024421 ps
CPU time 13.81 seconds
Started Jul 01 04:34:13 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 191640 kb
Host smart-9ef15329-e483-4c9d-821a-bc7b3f96f7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847508240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1847508240
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3719523646
Short name T253
Test name
Test status
Simulation time 374538038 ps
CPU time 0.72 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 191592 kb
Host smart-b62b168e-fcf6-48d6-a9c1-c5b7feff976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719523646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3719523646
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3192645296
Short name T232
Test name
Test status
Simulation time 25219202172 ps
CPU time 12.66 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:33 PM PDT 24
Peak memory 191604 kb
Host smart-72882346-d0bb-4719-be09-f67215ba3697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192645296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3192645296
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.91541132
Short name T193
Test name
Test status
Simulation time 458958087 ps
CPU time 0.73 seconds
Started Jul 01 04:33:56 PM PDT 24
Finished Jul 01 04:34:00 PM PDT 24
Peak memory 196400 kb
Host smart-34b0c023-8062-4271-bf68-bf0f765c1243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91541132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.91541132
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.956869880
Short name T224
Test name
Test status
Simulation time 21533797002 ps
CPU time 7.91 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:13 PM PDT 24
Peak memory 191588 kb
Host smart-7f70f9e4-8326-420b-83dc-b28f3edf363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956869880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.956869880
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1437077377
Short name T261
Test name
Test status
Simulation time 465606795 ps
CPU time 1.12 seconds
Started Jul 01 04:34:17 PM PDT 24
Finished Jul 01 04:34:28 PM PDT 24
Peak memory 191596 kb
Host smart-727673fc-fe0a-4515-9ce4-463b0cbb2321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437077377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1437077377
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1988524241
Short name T258
Test name
Test status
Simulation time 12504773859 ps
CPU time 16.25 seconds
Started Jul 01 04:34:15 PM PDT 24
Finished Jul 01 04:34:42 PM PDT 24
Peak memory 191568 kb
Host smart-9a6962a6-d1d7-4315-a952-b9cec09aa6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988524241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1988524241
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.550173068
Short name T216
Test name
Test status
Simulation time 645035818 ps
CPU time 0.66 seconds
Started Jul 01 04:34:06 PM PDT 24
Finished Jul 01 04:34:12 PM PDT 24
Peak memory 191588 kb
Host smart-5549f13b-85f8-4e2b-8a65-cb65a33e5df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550173068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.550173068
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.96994551
Short name T239
Test name
Test status
Simulation time 25123940371 ps
CPU time 19.38 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 191580 kb
Host smart-3d30178a-5267-45f5-a11d-7f42ca992b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96994551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.96994551
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2794481322
Short name T252
Test name
Test status
Simulation time 582526237 ps
CPU time 0.77 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:06 PM PDT 24
Peak memory 191520 kb
Host smart-83bacf4a-e643-4790-b8a2-80d8de0b22b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794481322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2794481322
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1061840728
Short name T178
Test name
Test status
Simulation time 432660360 ps
CPU time 1.18 seconds
Started Jul 01 04:34:19 PM PDT 24
Finished Jul 01 04:34:30 PM PDT 24
Peak memory 196368 kb
Host smart-86b77924-7493-4862-b3fe-a2ac1bc8f6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061840728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1061840728
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.589685488
Short name T26
Test name
Test status
Simulation time 20198508921 ps
CPU time 15.89 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 191576 kb
Host smart-441367c8-4514-429f-bbc8-f36eae726efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589685488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.589685488
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1490274056
Short name T210
Test name
Test status
Simulation time 429751926 ps
CPU time 1.2 seconds
Started Jul 01 04:34:02 PM PDT 24
Finished Jul 01 04:34:08 PM PDT 24
Peak memory 191592 kb
Host smart-447c46fe-50dd-4c39-9ffc-1054421c2714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490274056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1490274056
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3966924667
Short name T3
Test name
Test status
Simulation time 20484881496 ps
CPU time 3.51 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:23 PM PDT 24
Peak memory 191632 kb
Host smart-615317ea-9291-48b1-9617-1786a8d65ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966924667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3966924667
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3036580088
Short name T247
Test name
Test status
Simulation time 575953011 ps
CPU time 0.77 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:22 PM PDT 24
Peak memory 191712 kb
Host smart-622bd0af-c619-4e95-ae1a-053edb367e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036580088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3036580088
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2406210944
Short name T174
Test name
Test status
Simulation time 568926356 ps
CPU time 0.71 seconds
Started Jul 01 04:34:20 PM PDT 24
Finished Jul 01 04:34:30 PM PDT 24
Peak memory 196276 kb
Host smart-edf52109-3288-45bf-8b6a-8f35d157682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406210944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2406210944
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.841799682
Short name T43
Test name
Test status
Simulation time 58989104564 ps
CPU time 23.05 seconds
Started Jul 01 04:34:15 PM PDT 24
Finished Jul 01 04:34:48 PM PDT 24
Peak memory 191576 kb
Host smart-5ab82383-1982-41e6-86df-aa2018977630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841799682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.841799682
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1362135548
Short name T189
Test name
Test status
Simulation time 578746447 ps
CPU time 0.68 seconds
Started Jul 01 04:34:12 PM PDT 24
Finished Jul 01 04:34:23 PM PDT 24
Peak memory 191676 kb
Host smart-b19b1ef8-68c9-4aad-a18c-812b648e6147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362135548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1362135548
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1058980475
Short name T251
Test name
Test status
Simulation time 34619183681 ps
CPU time 27.13 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:34:43 PM PDT 24
Peak memory 191732 kb
Host smart-7f86aae8-b1c6-4049-aeb4-70524965e774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058980475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1058980475
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3217929111
Short name T230
Test name
Test status
Simulation time 510223627 ps
CPU time 1.15 seconds
Started Jul 01 04:34:21 PM PDT 24
Finished Jul 01 04:34:31 PM PDT 24
Peak memory 191472 kb
Host smart-8a22cc2c-b471-4705-94d1-b7ebd4bd5e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217929111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3217929111
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3133020597
Short name T209
Test name
Test status
Simulation time 39624912337 ps
CPU time 12.98 seconds
Started Jul 01 04:34:13 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 191760 kb
Host smart-f33b8d36-d3ac-4719-89ce-d2b603a6a214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133020597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3133020597
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3874717815
Short name T194
Test name
Test status
Simulation time 538584718 ps
CPU time 1.14 seconds
Started Jul 01 04:34:18 PM PDT 24
Finished Jul 01 04:34:29 PM PDT 24
Peak memory 196364 kb
Host smart-1027002a-b392-45cf-8641-e4dd27b5a8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874717815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3874717815
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2985512986
Short name T11
Test name
Test status
Simulation time 21205468830 ps
CPU time 7.36 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:34:15 PM PDT 24
Peak memory 191652 kb
Host smart-e3000022-de79-4426-860b-aee7c930b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985512986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2985512986
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3116233154
Short name T196
Test name
Test status
Simulation time 366562754 ps
CPU time 0.85 seconds
Started Jul 01 04:33:43 PM PDT 24
Finished Jul 01 04:33:46 PM PDT 24
Peak memory 191584 kb
Host smart-e0a42fdc-393d-4515-8139-54e0348212d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116233154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3116233154
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4036659515
Short name T212
Test name
Test status
Simulation time 35572827323 ps
CPU time 12.78 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:34:11 PM PDT 24
Peak memory 191644 kb
Host smart-15ad86c1-a629-438a-8ba4-6639d3d94c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036659515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4036659515
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3388716677
Short name T236
Test name
Test status
Simulation time 429416035 ps
CPU time 1.18 seconds
Started Jul 01 04:33:54 PM PDT 24
Finished Jul 01 04:33:58 PM PDT 24
Peak memory 191452 kb
Host smart-2a8f4fce-6c02-4536-a561-accbcf266ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388716677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3388716677
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2945074006
Short name T191
Test name
Test status
Simulation time 60124794904 ps
CPU time 46.05 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:34:43 PM PDT 24
Peak memory 191644 kb
Host smart-10d83ba9-f60f-4e87-afd5-02bc7c0e8359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945074006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2945074006
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2624875957
Short name T214
Test name
Test status
Simulation time 573980890 ps
CPU time 0.78 seconds
Started Jul 01 04:33:52 PM PDT 24
Finished Jul 01 04:33:55 PM PDT 24
Peak memory 196708 kb
Host smart-deaf6973-7826-4eb3-b989-ef4bc93e654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624875957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2624875957
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4106973965
Short name T238
Test name
Test status
Simulation time 7328594109 ps
CPU time 2.57 seconds
Started Jul 01 04:33:59 PM PDT 24
Finished Jul 01 04:34:05 PM PDT 24
Peak memory 196776 kb
Host smart-7a4c3efa-763a-4a4d-be74-4d1c459f6af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106973965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4106973965
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1969469146
Short name T7
Test name
Test status
Simulation time 602935944 ps
CPU time 0.96 seconds
Started Jul 01 04:34:03 PM PDT 24
Finished Jul 01 04:34:08 PM PDT 24
Peak memory 191588 kb
Host smart-098b84c6-cb0b-4af9-9759-6c76422c9a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969469146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1969469146
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2752385650
Short name T262
Test name
Test status
Simulation time 2217784286 ps
CPU time 3.67 seconds
Started Jul 01 04:33:51 PM PDT 24
Finished Jul 01 04:33:56 PM PDT 24
Peak memory 191644 kb
Host smart-0e0e9001-b73a-4107-97fa-894760b526c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752385650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2752385650
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2419825083
Short name T29
Test name
Test status
Simulation time 511559080 ps
CPU time 1.33 seconds
Started Jul 01 04:33:52 PM PDT 24
Finished Jul 01 04:33:55 PM PDT 24
Peak memory 191696 kb
Host smart-629a2801-0de8-491d-a019-b48521ff7c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419825083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2419825083
Directory /workspace/9.aon_timer_smoke/latest
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