Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	28007	1		T1	12		T2	12		T3	12
bark[1]	299	1		T8	21		T29	57		T46	30
bark[2]	607	1		T4	21		T31	21		T120	14
bark[3]	510	1		T4	129		T17	21		T108	14
bark[4]	164	1		T110	31		T111	42		T83	49
bark[5]	334	1		T46	21		T116	14		T183	14
bark[6]	675	1		T4	263		T14	21		T98	268
bark[7]	377	1		T4	21		T17	21		T110	14
bark[8]	231	1		T14	40		T129	35		T163	5
bark[9]	520	1		T7	21		T10	5		T35	21
bark[10]	157	1		T10	26		T104	21		T129	21
bark[11]	564	1		T29	187		T44	21		T98	21
bark[12]	297	1		T7	21		T30	58		T37	42
bark[13]	881	1		T7	28		T8	5		T21	14
bark[14]	968	1		T30	294		T142	21		T138	21
bark[15]	105	1		T44	26		T121	21		T90	7
bark[16]	542	1		T12	14		T23	31		T110	21
bark[17]	289	1		T7	21		T29	26		T44	40
bark[18]	703	1		T35	21		T33	21		T179	14
bark[19]	389	1		T36	14		T103	21		T83	21
bark[20]	555	1		T7	94		T30	21		T44	30
bark[21]	292	1		T29	21		T114	21		T84	91
bark[22]	1262	1		T8	47		T10	114		T23	21
bark[23]	564	1		T14	21		T33	26		T44	39
bark[24]	297	1		T17	21		T30	131		T168	30
bark[25]	212	1		T4	30		T23	7		T40	14
bark[26]	588	1		T9	14		T14	14		T29	21
bark[27]	641	1		T14	21		T29	21		T156	14
bark[28]	680	1		T8	291		T158	14		T98	5
bark[29]	598	1		T110	30		T29	62		T37	21
bark[30]	344	1		T8	21		T29	21		T84	42
bark[31]	201	1		T17	21		T169	40		T174	63
bark_0	4655	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	27640	1		T1	11		T2	11		T3	11
bite[1]	1022	1		T4	21		T12	13		T110	31
bite[2]	601	1		T4	262		T44	26		T46	30
bite[3]	501	1		T21	13		T23	30		T100	21
bite[4]	811	1		T8	290		T147	26		T100	30
bite[5]	1132	1		T35	21		T32	55		T33	115
bite[6]	269	1		T29	72		T89	74		T135	21
bite[7]	567	1		T10	113		T29	242		T30	130
bite[8]	807	1		T7	53		T10	4		T17	21
bite[9]	576	1		T7	21		T142	21		T111	21
bite[10]	257	1		T100	93		T129	35		T125	13
bite[11]	659	1		T8	25		T17	21		T89	44
bite[12]	485	1		T110	21		T29	21		T44	21
bite[13]	284	1		T7	21		T47	116		T161	13
bite[14]	224	1		T14	40		T40	13		T139	13
bite[15]	207	1		T90	13		T106	21		T185	13
bite[16]	1332	1		T14	21		T30	293		T37	13
bite[17]	270	1		T142	21		T181	6		T111	21
bite[18]	114	1		T37	21		T100	34		T98	25
bite[19]	392	1		T7	68		T23	6		T110	30
bite[20]	632	1		T4	128		T14	21		T31	21
bite[21]	187	1		T4	30		T33	26		T46	21
bite[22]	499	1		T29	21		T30	57		T36	13
bite[23]	350	1		T17	21		T44	70		T83	21
bite[24]	162	1		T7	21		T8	46		T29	61
bite[25]	414	1		T14	21		T23	21		T29	21
bite[26]	244	1		T17	21		T31	21		T169	40
bite[27]	123	1		T4	21		T14	13		T35	21
bite[28]	542	1		T8	21		T10	25		T35	21
bite[29]	437	1		T29	21		T30	21		T156	13
bite[30]	377	1		T23	21		T29	25		T162	13
bite[31]	217	1		T9	13		T110	13		T147	48
bite_0	5174	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	47508	1		T1	19		T2	19		T3	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	915	1		T17	32		T30	136		T35	40
prescale[1]	880	1		T8	2		T14	24		T29	67
prescale[2]	474	1		T30	61		T47	28		T165	19
prescale[3]	656	1		T1	9		T4	53		T14	24
prescale[4]	872	1		T8	19		T17	23		T200	9
prescale[5]	736	1		T10	2		T14	51		T110	23
prescale[6]	628	1		T6	9		T8	23		T32	2
prescale[7]	619	1		T4	19		T201	9		T30	2
prescale[8]	935	1		T4	4		T29	72		T30	242
prescale[9]	627	1		T4	84		T23	2		T110	40
prescale[10]	845	1		T8	171		T29	2		T30	104
prescale[11]	874	1		T4	76		T7	23		T202	9
prescale[12]	972	1		T29	2		T31	2		T34	44
prescale[13]	279	1		T10	2		T203	9		T169	24
prescale[14]	667	1		T4	33		T10	2		T17	19
prescale[15]	679	1		T3	9		T7	74		T30	21
prescale[16]	377	1		T4	4		T10	2		T30	20
prescale[17]	271	1		T10	2		T33	2		T34	38
prescale[18]	601	1		T8	9		T10	2		T32	21
prescale[19]	868	1		T4	37		T37	19		T31	48
prescale[20]	547	1		T17	19		T110	41		T30	2
prescale[21]	402	1		T14	38		T23	19		T32	2
prescale[22]	624	1		T34	60		T204	9		T181	85
prescale[23]	1151	1		T4	21		T31	19		T34	2
prescale[24]	614	1		T23	28		T29	24		T121	9
prescale[25]	760	1		T8	48		T17	23		T29	2
prescale[26]	840	1		T8	120		T41	9		T98	50
prescale[27]	464	1		T4	51		T10	2		T29	30
prescale[28]	997	1		T5	9		T23	11		T29	2
prescale[29]	873	1		T23	202		T37	24		T33	2
prescale[30]	485	1		T2	9		T10	2		T32	40
prescale[31]	1227	1		T4	151		T29	187		T30	94
prescale_0	24749	1		T1	10		T2	10		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34674	1		T1	9		T2	19		T3	9
auto[1]	12834	1		T1	10		T3	10		T4	218

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	47508	1		T1	19		T2	19		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27218	1		T1	14		T2	14		T3	14
wkup[1]	285	1		T23	26		T30	65		T47	26
wkup[2]	304	1		T7	21		T17	21		T38	15
wkup[3]	214	1		T37	21		T32	21		T98	21
wkup[4]	368	1		T14	21		T30	21		T31	30
wkup[5]	189	1		T10	21		T29	8		T35	21
wkup[6]	282	1		T8	26		T29	21		T30	21
wkup[7]	345	1		T9	15		T110	21		T30	42
wkup[8]	345	1		T14	21		T29	42		T31	30
wkup[9]	337	1		T23	21		T29	21		T30	21
wkup[10]	264	1		T4	21		T23	21		T31	21
wkup[11]	233	1		T181	35		T114	26		T104	8
wkup[12]	256	1		T4	21		T37	15		T46	30
wkup[13]	304	1		T8	21		T14	21		T29	21
wkup[14]	307	1		T4	42		T8	21		T103	21
wkup[15]	320	1		T23	21		T30	30		T44	30
wkup[16]	180	1		T8	21		T36	15		T32	21
wkup[17]	204	1		T4	35		T23	29		T37	42
wkup[18]	227	1		T29	21		T46	21		T100	51
wkup[19]	135	1		T31	15		T138	21		T111	21
wkup[20]	316	1		T30	65		T31	30		T32	56
wkup[21]	177	1		T29	21		T98	21		T154	21
wkup[22]	218	1		T33	26		T142	21		T98	42
wkup[23]	309	1		T7	21		T10	21		T17	21
wkup[24]	261	1		T110	31		T181	38		T180	21
wkup[25]	296	1		T4	21		T29	21		T30	21
wkup[26]	207	1		T4	21		T10	15		T47	21
wkup[27]	460	1		T8	39		T162	15		T98	51
wkup[28]	160	1		T31	21		T100	21		T98	21
wkup[29]	226	1		T21	15		T30	26		T34	8
wkup[30]	269	1		T4	42		T8	42		T35	21
wkup[31]	185	1		T23	21		T31	21		T89	21
wkup[32]	93	1		T4	21		T31	21		T122	15
wkup[33]	163	1		T29	30		T30	26		T31	21
wkup[34]	225	1		T10	21		T110	21		T29	21
wkup[35]	274	1		T17	21		T44	21		T34	21
wkup[36]	403	1		T7	29		T30	30		T147	26
wkup[37]	198	1		T4	42		T165	21		T154	21
wkup[38]	192	1		T7	21		T37	21		T31	21
wkup[39]	275	1		T30	56		T34	21		T142	21
wkup[40]	129	1		T29	36		T32	21		T205	21
wkup[41]	288	1		T8	6		T110	15		T32	21
wkup[42]	362	1		T110	30		T29	21		T32	21
wkup[43]	235	1		T14	21		T32	21		T44	20
wkup[44]	321	1		T7	31		T30	26		T161	15
wkup[45]	273	1		T7	30		T100	30		T153	21
wkup[46]	286	1		T29	26		T89	60		T104	57
wkup[47]	305	1		T4	30		T7	26		T8	21
wkup[48]	154	1		T4	15		T129	21		T86	21
wkup[49]	170	1		T153	21		T106	21		T175	21
wkup[50]	309	1		T4	26		T8	21		T23	21
wkup[51]	321	1		T4	26		T31	26		T160	26
wkup[52]	190	1		T10	27		T192	15		T104	26
wkup[53]	282	1		T4	15		T29	21		T30	21
wkup[54]	179	1		T12	15		T30	21		T167	15
wkup[55]	228	1		T14	15		T29	21		T31	21
wkup[56]	288	1		T37	21		T138	21		T100	15
wkup[57]	270	1		T23	31		T29	26		T181	26
wkup[58]	414	1		T8	8		T31	42		T32	6
wkup[59]	380	1		T33	21		T44	39		T165	26
wkup[60]	182	1		T7	21		T8	21		T104	21
wkup[61]	212	1		T160	39		T135	21		T175	21
wkup[62]	336	1		T40	15		T168	15		T129	35
wkup[63]	452	1		T30	72		T156	15		T100	26
wkup_0	3718	1		T1	5		T2	5		T3	5