Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.09 99.33 93.67 100.00 98.40 99.51 49.66


Total test records in report: 425
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T24 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3211370790 Jul 02 09:50:12 AM PDT 24 Jul 02 09:50:21 AM PDT 24 390803172 ps
T25 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.209374681 Jul 02 09:49:30 AM PDT 24 Jul 02 09:49:36 AM PDT 24 1233455826 ps
T26 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.906756185 Jul 02 09:50:06 AM PDT 24 Jul 02 09:50:19 AM PDT 24 8340381849 ps
T27 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.463398191 Jul 02 09:49:52 AM PDT 24 Jul 02 09:50:11 AM PDT 24 7817389957 ps
T286 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1172708211 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:09 AM PDT 24 481024873 ps
T287 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3989866029 Jul 02 09:49:50 AM PDT 24 Jul 02 09:49:57 AM PDT 24 423520167 ps
T288 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1861841032 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:01 AM PDT 24 462015887 ps
T289 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1145275810 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:14 AM PDT 24 568098666 ps
T290 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2541164806 Jul 02 09:49:43 AM PDT 24 Jul 02 09:49:47 AM PDT 24 453269363 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2797681168 Jul 02 09:49:33 AM PDT 24 Jul 02 09:49:38 AM PDT 24 398974825 ps
T292 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.926561243 Jul 02 09:49:45 AM PDT 24 Jul 02 09:49:49 AM PDT 24 314032993 ps
T293 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2124377594 Jul 02 09:49:59 AM PDT 24 Jul 02 09:50:08 AM PDT 24 482350059 ps
T206 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3119377783 Jul 02 09:49:48 AM PDT 24 Jul 02 09:49:54 AM PDT 24 579483452 ps
T50 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3478001647 Jul 02 09:49:28 AM PDT 24 Jul 02 09:49:34 AM PDT 24 519786325 ps
T294 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1282344314 Jul 02 09:49:26 AM PDT 24 Jul 02 09:49:31 AM PDT 24 581996772 ps
T28 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4117502231 Jul 02 09:49:52 AM PDT 24 Jul 02 09:50:06 AM PDT 24 4801976763 ps
T51 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1254905722 Jul 02 09:49:59 AM PDT 24 Jul 02 09:50:07 AM PDT 24 1215444466 ps
T52 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2546425163 Jul 02 09:49:56 AM PDT 24 Jul 02 09:50:05 AM PDT 24 339134592 ps
T53 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.130409081 Jul 02 09:49:28 AM PDT 24 Jul 02 09:49:34 AM PDT 24 483857375 ps
T75 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1344539757 Jul 02 09:49:52 AM PDT 24 Jul 02 09:50:00 AM PDT 24 1615325747 ps
T76 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3534525614 Jul 02 09:50:12 AM PDT 24 Jul 02 09:50:24 AM PDT 24 2973330683 ps
T195 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1825733770 Jul 02 09:49:44 AM PDT 24 Jul 02 09:49:52 AM PDT 24 7997725638 ps
T295 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.660954462 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:02 AM PDT 24 298133865 ps
T296 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1026990602 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:17 AM PDT 24 930559776 ps
T297 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.855284065 Jul 02 09:49:31 AM PDT 24 Jul 02 09:49:36 AM PDT 24 446453875 ps
T298 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2368897778 Jul 02 09:49:51 AM PDT 24 Jul 02 09:50:03 AM PDT 24 401035858 ps
T299 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2954970602 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:14 AM PDT 24 452764283 ps
T300 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1675309636 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:01 AM PDT 24 455865032 ps
T77 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3834078046 Jul 02 09:49:51 AM PDT 24 Jul 02 09:50:03 AM PDT 24 2689417250 ps
T301 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1380188258 Jul 02 09:49:29 AM PDT 24 Jul 02 09:49:34 AM PDT 24 404471413 ps
T78 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2179847706 Jul 02 09:49:48 AM PDT 24 Jul 02 09:49:54 AM PDT 24 494668213 ps
T302 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.750815296 Jul 02 09:49:41 AM PDT 24 Jul 02 09:49:44 AM PDT 24 395117435 ps
T79 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2355215028 Jul 02 09:49:46 AM PDT 24 Jul 02 09:49:51 AM PDT 24 1234626132 ps
T303 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4113272769 Jul 02 09:49:46 AM PDT 24 Jul 02 09:49:51 AM PDT 24 434056839 ps
T304 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.549174142 Jul 02 09:49:51 AM PDT 24 Jul 02 09:50:00 AM PDT 24 499109511 ps
T305 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3997545387 Jul 02 09:50:04 AM PDT 24 Jul 02 09:50:13 AM PDT 24 530763214 ps
T306 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1069841918 Jul 02 09:49:31 AM PDT 24 Jul 02 09:49:36 AM PDT 24 315397266 ps
T307 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3066375602 Jul 02 09:49:56 AM PDT 24 Jul 02 09:50:11 AM PDT 24 4243043571 ps
T308 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.612872382 Jul 02 09:49:28 AM PDT 24 Jul 02 09:49:34 AM PDT 24 652184059 ps
T309 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1284431619 Jul 02 09:49:36 AM PDT 24 Jul 02 09:49:41 AM PDT 24 518882753 ps
T310 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.398976560 Jul 02 09:49:30 AM PDT 24 Jul 02 09:49:38 AM PDT 24 13996150051 ps
T311 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3401408163 Jul 02 09:49:30 AM PDT 24 Jul 02 09:49:35 AM PDT 24 357931732 ps
T312 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1813566851 Jul 02 09:49:46 AM PDT 24 Jul 02 09:49:50 AM PDT 24 825266348 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.520444336 Jul 02 09:49:56 AM PDT 24 Jul 02 09:50:06 AM PDT 24 560532247 ps
T314 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3407947008 Jul 02 09:49:31 AM PDT 24 Jul 02 09:49:41 AM PDT 24 359106231 ps
T315 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.4064099371 Jul 02 09:49:58 AM PDT 24 Jul 02 09:50:07 AM PDT 24 477387834 ps
T316 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3766038407 Jul 02 09:50:09 AM PDT 24 Jul 02 09:50:19 AM PDT 24 414196091 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.924665839 Jul 02 09:49:58 AM PDT 24 Jul 02 09:50:06 AM PDT 24 506123561 ps
T317 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2657233976 Jul 02 09:49:45 AM PDT 24 Jul 02 09:49:49 AM PDT 24 343073726 ps
T318 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1968629313 Jul 02 09:50:03 AM PDT 24 Jul 02 09:50:11 AM PDT 24 382339166 ps
T319 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1354181866 Jul 02 09:49:43 AM PDT 24 Jul 02 09:49:46 AM PDT 24 456153985 ps
T320 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4021629855 Jul 02 09:49:54 AM PDT 24 Jul 02 09:50:02 AM PDT 24 528378336 ps
T321 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1098358757 Jul 02 09:49:26 AM PDT 24 Jul 02 09:49:30 AM PDT 24 384101631 ps
T322 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3950723087 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:10 AM PDT 24 4369724069 ps
T80 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1056965208 Jul 02 09:49:31 AM PDT 24 Jul 02 09:49:37 AM PDT 24 1281815116 ps
T323 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4138902238 Jul 02 09:49:29 AM PDT 24 Jul 02 09:49:35 AM PDT 24 518971175 ps
T197 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3213626902 Jul 02 09:49:50 AM PDT 24 Jul 02 09:50:03 AM PDT 24 8042027348 ps
T324 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1564216536 Jul 02 09:49:28 AM PDT 24 Jul 02 09:49:34 AM PDT 24 567991740 ps
T325 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3964712004 Jul 02 09:49:27 AM PDT 24 Jul 02 09:49:33 AM PDT 24 977229718 ps
T326 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1114923316 Jul 02 09:49:57 AM PDT 24 Jul 02 09:50:07 AM PDT 24 567447967 ps
T327 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.940145128 Jul 02 09:49:52 AM PDT 24 Jul 02 09:50:00 AM PDT 24 510715902 ps
T55 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1374124351 Jul 02 09:49:35 AM PDT 24 Jul 02 09:49:40 AM PDT 24 516649619 ps
T328 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3728216104 Jul 02 09:50:02 AM PDT 24 Jul 02 09:50:10 AM PDT 24 340673644 ps
T81 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1688802728 Jul 02 09:49:58 AM PDT 24 Jul 02 09:50:06 AM PDT 24 1529203324 ps
T329 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1086483183 Jul 02 09:49:23 AM PDT 24 Jul 02 09:49:29 AM PDT 24 414276933 ps
T330 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3314908338 Jul 02 09:49:55 AM PDT 24 Jul 02 09:50:03 AM PDT 24 350434292 ps
T68 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2489512453 Jul 02 09:49:59 AM PDT 24 Jul 02 09:50:08 AM PDT 24 403529595 ps
T331 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.158919187 Jul 02 09:49:52 AM PDT 24 Jul 02 09:50:00 AM PDT 24 446807648 ps
T82 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2025385992 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:04 AM PDT 24 2505798674 ps
T332 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2679907779 Jul 02 09:49:33 AM PDT 24 Jul 02 09:49:39 AM PDT 24 2632499320 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1327367233 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:09 AM PDT 24 391768388 ps
T334 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3495306488 Jul 02 09:49:38 AM PDT 24 Jul 02 09:49:44 AM PDT 24 1266981353 ps
T335 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.319423880 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:21 AM PDT 24 386942546 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1251979778 Jul 02 09:49:58 AM PDT 24 Jul 02 09:50:10 AM PDT 24 7800125989 ps
T336 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2076954010 Jul 02 09:50:07 AM PDT 24 Jul 02 09:50:16 AM PDT 24 424469692 ps
T337 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1068900667 Jul 02 09:50:03 AM PDT 24 Jul 02 09:50:11 AM PDT 24 512655335 ps
T338 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.756339587 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:02 AM PDT 24 511683258 ps
T339 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.93834848 Jul 02 09:49:34 AM PDT 24 Jul 02 09:49:39 AM PDT 24 327619177 ps
T340 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3516446085 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:21 AM PDT 24 646105745 ps
T341 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1404366863 Jul 02 09:49:50 AM PDT 24 Jul 02 09:49:58 AM PDT 24 552946939 ps
T342 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2768239513 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:09 AM PDT 24 320504066 ps
T343 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1312520333 Jul 02 09:49:55 AM PDT 24 Jul 02 09:50:04 AM PDT 24 396546144 ps
T344 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1874495766 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:13 AM PDT 24 299585036 ps
T345 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2493230375 Jul 02 09:50:13 AM PDT 24 Jul 02 09:50:24 AM PDT 24 1377775883 ps
T346 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2706509938 Jul 02 09:49:42 AM PDT 24 Jul 02 09:49:46 AM PDT 24 409481301 ps
T347 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2802817655 Jul 02 09:49:32 AM PDT 24 Jul 02 09:49:39 AM PDT 24 1080983903 ps
T348 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2455598849 Jul 02 09:49:54 AM PDT 24 Jul 02 09:50:02 AM PDT 24 400167039 ps
T349 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2283716283 Jul 02 09:49:48 AM PDT 24 Jul 02 09:49:53 AM PDT 24 566195049 ps
T350 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.28585280 Jul 02 09:49:49 AM PDT 24 Jul 02 09:49:55 AM PDT 24 296851335 ps
T351 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2373973005 Jul 02 09:49:29 AM PDT 24 Jul 02 09:49:35 AM PDT 24 293339589 ps
T352 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3706274453 Jul 02 09:49:30 AM PDT 24 Jul 02 09:49:36 AM PDT 24 558718177 ps
T353 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2308772693 Jul 02 09:49:40 AM PDT 24 Jul 02 09:49:45 AM PDT 24 4076734834 ps
T354 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2161631949 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:21 AM PDT 24 1155656353 ps
T355 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1009429398 Jul 02 09:49:24 AM PDT 24 Jul 02 09:49:37 AM PDT 24 2985850974 ps
T356 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1849318332 Jul 02 09:49:30 AM PDT 24 Jul 02 09:49:36 AM PDT 24 317608942 ps
T357 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1890149728 Jul 02 09:49:55 AM PDT 24 Jul 02 09:50:03 AM PDT 24 648431668 ps
T358 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.237687588 Jul 02 09:49:50 AM PDT 24 Jul 02 09:49:58 AM PDT 24 4285867920 ps
T359 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2261455360 Jul 02 09:50:13 AM PDT 24 Jul 02 09:50:22 AM PDT 24 505793803 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2785071043 Jul 02 09:49:34 AM PDT 24 Jul 02 09:49:39 AM PDT 24 432889505 ps
T360 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1870793937 Jul 02 09:50:10 AM PDT 24 Jul 02 09:50:21 AM PDT 24 475391965 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1057160979 Jul 02 09:49:51 AM PDT 24 Jul 02 09:49:59 AM PDT 24 468390547 ps
T362 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1886777525 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:14 AM PDT 24 451553553 ps
T363 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1894084772 Jul 02 09:49:46 AM PDT 24 Jul 02 09:49:50 AM PDT 24 387503493 ps
T364 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3682941223 Jul 02 09:49:57 AM PDT 24 Jul 02 09:50:07 AM PDT 24 680716057 ps
T365 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2335415476 Jul 02 09:50:15 AM PDT 24 Jul 02 09:50:25 AM PDT 24 454395887 ps
T366 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2305042060 Jul 02 09:49:24 AM PDT 24 Jul 02 09:49:30 AM PDT 24 4669599218 ps
T74 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1130151764 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:09 AM PDT 24 338086070 ps
T367 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2380755046 Jul 02 09:50:04 AM PDT 24 Jul 02 09:50:15 AM PDT 24 1279674326 ps
T368 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3744996556 Jul 02 09:49:58 AM PDT 24 Jul 02 09:50:06 AM PDT 24 344063014 ps
T369 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4284171243 Jul 02 09:49:49 AM PDT 24 Jul 02 09:49:55 AM PDT 24 323994157 ps
T370 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.455281429 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:03 AM PDT 24 450822120 ps
T198 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3730460719 Jul 02 09:50:02 AM PDT 24 Jul 02 09:50:17 AM PDT 24 8397706254 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.350347448 Jul 02 09:49:47 AM PDT 24 Jul 02 09:49:52 AM PDT 24 468264733 ps
T199 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2106272078 Jul 02 09:49:28 AM PDT 24 Jul 02 09:49:44 AM PDT 24 7607410436 ps
T372 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2512475203 Jul 02 09:49:50 AM PDT 24 Jul 02 09:49:57 AM PDT 24 410737529 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3716409363 Jul 02 09:49:29 AM PDT 24 Jul 02 09:49:41 AM PDT 24 4066957225 ps
T58 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3729170398 Jul 02 09:49:47 AM PDT 24 Jul 02 09:49:53 AM PDT 24 473668219 ps
T374 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1372654369 Jul 02 09:49:29 AM PDT 24 Jul 02 09:49:35 AM PDT 24 469491994 ps
T375 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3384990815 Jul 02 09:49:38 AM PDT 24 Jul 02 09:49:42 AM PDT 24 1036142812 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2859522126 Jul 02 09:49:35 AM PDT 24 Jul 02 09:50:02 AM PDT 24 13467579877 ps
T376 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3328047098 Jul 02 09:50:08 AM PDT 24 Jul 02 09:50:17 AM PDT 24 381001758 ps
T377 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2583174681 Jul 02 09:49:44 AM PDT 24 Jul 02 09:49:48 AM PDT 24 484144216 ps
T378 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.275812741 Jul 02 09:50:02 AM PDT 24 Jul 02 09:50:12 AM PDT 24 9101924892 ps
T379 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1153213755 Jul 02 09:49:58 AM PDT 24 Jul 02 09:50:06 AM PDT 24 399375485 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.487015743 Jul 02 09:50:23 AM PDT 24 Jul 02 09:50:35 AM PDT 24 2481485130 ps
T381 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2024881034 Jul 02 09:49:30 AM PDT 24 Jul 02 09:49:50 AM PDT 24 7003057596 ps
T382 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.388516767 Jul 02 09:49:38 AM PDT 24 Jul 02 09:49:42 AM PDT 24 376158861 ps
T383 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.710763835 Jul 02 09:49:40 AM PDT 24 Jul 02 09:49:54 AM PDT 24 4109591681 ps
T384 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1245643545 Jul 02 09:49:46 AM PDT 24 Jul 02 09:49:50 AM PDT 24 463532527 ps
T385 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.538726538 Jul 02 09:49:38 AM PDT 24 Jul 02 09:49:43 AM PDT 24 347830797 ps
T386 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2805159441 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:19 AM PDT 24 283417914 ps
T387 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3493719153 Jul 02 09:49:26 AM PDT 24 Jul 02 09:49:31 AM PDT 24 288628812 ps
T388 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.681906548 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:05 AM PDT 24 2723636895 ps
T70 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.735398857 Jul 02 09:49:27 AM PDT 24 Jul 02 09:49:42 AM PDT 24 5188783915 ps
T389 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1270546464 Jul 02 09:49:56 AM PDT 24 Jul 02 09:50:06 AM PDT 24 414853333 ps
T390 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3056914237 Jul 02 09:49:25 AM PDT 24 Jul 02 09:49:30 AM PDT 24 335909165 ps
T391 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2627350429 Jul 02 09:50:02 AM PDT 24 Jul 02 09:50:10 AM PDT 24 493801736 ps
T392 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2423801070 Jul 02 09:50:00 AM PDT 24 Jul 02 09:50:11 AM PDT 24 2780127356 ps
T393 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.306735952 Jul 02 09:50:06 AM PDT 24 Jul 02 09:50:15 AM PDT 24 280443644 ps
T394 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3193816230 Jul 02 09:50:13 AM PDT 24 Jul 02 09:50:24 AM PDT 24 4654408056 ps
T395 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2612332721 Jul 02 09:49:47 AM PDT 24 Jul 02 09:49:53 AM PDT 24 321047072 ps
T396 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1461155867 Jul 02 09:49:55 AM PDT 24 Jul 02 09:50:03 AM PDT 24 515350784 ps
T397 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.384620076 Jul 02 09:49:54 AM PDT 24 Jul 02 09:50:03 AM PDT 24 1115703500 ps
T398 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1778589848 Jul 02 09:50:11 AM PDT 24 Jul 02 09:50:21 AM PDT 24 329608823 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3424376235 Jul 02 09:49:31 AM PDT 24 Jul 02 09:49:37 AM PDT 24 783402915 ps
T71 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4140793391 Jul 02 09:49:31 AM PDT 24 Jul 02 09:49:36 AM PDT 24 330025550 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1687224999 Jul 02 09:49:40 AM PDT 24 Jul 02 09:49:44 AM PDT 24 500264605 ps
T401 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3616191596 Jul 02 09:49:57 AM PDT 24 Jul 02 09:50:06 AM PDT 24 293245325 ps
T402 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.619066338 Jul 02 09:49:50 AM PDT 24 Jul 02 09:49:57 AM PDT 24 523193562 ps
T403 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.647716389 Jul 02 09:49:39 AM PDT 24 Jul 02 09:49:43 AM PDT 24 404987439 ps
T404 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3735869286 Jul 02 09:49:51 AM PDT 24 Jul 02 09:49:58 AM PDT 24 447270458 ps
T405 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.569051903 Jul 02 09:49:33 AM PDT 24 Jul 02 09:49:40 AM PDT 24 2266009906 ps
T406 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2076816071 Jul 02 09:49:49 AM PDT 24 Jul 02 09:49:55 AM PDT 24 474134160 ps
T196 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1983941886 Jul 02 09:49:39 AM PDT 24 Jul 02 09:49:48 AM PDT 24 4246205165 ps
T407 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.657278808 Jul 02 09:49:43 AM PDT 24 Jul 02 09:49:49 AM PDT 24 8296067120 ps
T408 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.165275810 Jul 02 09:49:45 AM PDT 24 Jul 02 09:49:49 AM PDT 24 505265619 ps
T409 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4054572195 Jul 02 09:49:52 AM PDT 24 Jul 02 09:50:01 AM PDT 24 353382574 ps
T410 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.779826756 Jul 02 09:49:44 AM PDT 24 Jul 02 09:49:49 AM PDT 24 502259288 ps
T411 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3042684567 Jul 02 09:49:51 AM PDT 24 Jul 02 09:49:59 AM PDT 24 346890118 ps
T72 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4175837700 Jul 02 09:50:01 AM PDT 24 Jul 02 09:50:10 AM PDT 24 1402384692 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1088943955 Jul 02 09:49:31 AM PDT 24 Jul 02 09:49:46 AM PDT 24 8683177407 ps
T413 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1522395838 Jul 02 09:49:29 AM PDT 24 Jul 02 09:49:34 AM PDT 24 433216784 ps
T73 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1067628720 Jul 02 09:49:26 AM PDT 24 Jul 02 09:49:32 AM PDT 24 653391879 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2551081885 Jul 02 09:49:36 AM PDT 24 Jul 02 09:49:41 AM PDT 24 545685359 ps
T415 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3296595558 Jul 02 09:49:50 AM PDT 24 Jul 02 09:49:57 AM PDT 24 533760321 ps
T416 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1379376944 Jul 02 09:49:28 AM PDT 24 Jul 02 09:49:34 AM PDT 24 858954406 ps
T417 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1578736140 Jul 02 09:49:56 AM PDT 24 Jul 02 09:50:05 AM PDT 24 508768274 ps
T418 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4046424804 Jul 02 09:49:31 AM PDT 24 Jul 02 09:49:39 AM PDT 24 600534320 ps
T419 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.244447194 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:15 AM PDT 24 1701911682 ps
T420 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1652809647 Jul 02 09:49:53 AM PDT 24 Jul 02 09:50:03 AM PDT 24 458143504 ps
T421 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2738425531 Jul 02 09:50:03 AM PDT 24 Jul 02 09:50:13 AM PDT 24 525792896 ps
T422 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3648257525 Jul 02 09:50:01 AM PDT 24 Jul 02 09:50:11 AM PDT 24 4640520341 ps
T423 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.853025563 Jul 02 09:49:44 AM PDT 24 Jul 02 09:49:48 AM PDT 24 338871503 ps
T424 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3932873090 Jul 02 09:49:28 AM PDT 24 Jul 02 09:49:33 AM PDT 24 426383809 ps
T425 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3570469485 Jul 02 09:50:05 AM PDT 24 Jul 02 09:50:13 AM PDT 24 371619968 ps

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3911260228
Short name T8
Test name
Test status
Simulation time 60558218785 ps
CPU time 221.58 seconds
Started Jul 02 09:18:04 AM PDT 24
Finished Jul 02 09:21:47 AM PDT 24
Peak memory 206660 kb
Host smart-4c5277de-e9ec-47f0-8e47-6373575fd5fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911260228 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3911260228
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3528309077
Short name T30
Test name
Test status
Simulation time 334918900935 ps
CPU time 460.61 seconds
Started Jul 02 09:17:04 AM PDT 24
Finished Jul 02 09:24:45 AM PDT 24
Peak memory 203172 kb
Host smart-f2c8519b-985d-4573-86b2-bdcd3e6df871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528309077 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3528309077
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.463398191
Short name T27
Test name
Test status
Simulation time 7817389957 ps
CPU time 12.13 seconds
Started Jul 02 09:49:52 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 198348 kb
Host smart-85f9d37e-4c68-4cba-a056-ad54d6e51193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463398191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.463398191
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1221749610
Short name T7
Test name
Test status
Simulation time 156412102934 ps
CPU time 239.23 seconds
Started Jul 02 09:17:43 AM PDT 24
Finished Jul 02 09:21:43 AM PDT 24
Peak memory 198044 kb
Host smart-49dbd45d-f5da-4dc6-9fdd-46e93cf2c3d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221749610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1221749610
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1586590836
Short name T48
Test name
Test status
Simulation time 197665288606 ps
CPU time 402.93 seconds
Started Jul 02 09:17:25 AM PDT 24
Finished Jul 02 09:24:08 AM PDT 24
Peak memory 214816 kb
Host smart-997e8ea7-f628-4dcc-bde7-3ed1a0dc90ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586590836 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1586590836
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2438589954
Short name T86
Test name
Test status
Simulation time 770610561813 ps
CPU time 417.33 seconds
Started Jul 02 09:17:49 AM PDT 24
Finished Jul 02 09:24:47 AM PDT 24
Peak memory 202764 kb
Host smart-0b30f37c-6a5a-45ff-aafb-ee9c9f69d4d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438589954 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2438589954
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2196411896
Short name T98
Test name
Test status
Simulation time 61756676240 ps
CPU time 513.61 seconds
Started Jul 02 09:18:03 AM PDT 24
Finished Jul 02 09:26:38 AM PDT 24
Peak memory 201564 kb
Host smart-c88de602-4f95-42be-ba35-cdcde5b69f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196411896 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2196411896
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1646298438
Short name T84
Test name
Test status
Simulation time 220781313518 ps
CPU time 419.46 seconds
Started Jul 02 09:17:56 AM PDT 24
Finished Jul 02 09:24:57 AM PDT 24
Peak memory 202684 kb
Host smart-704db758-7a5b-47f1-a329-a35365da5d5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646298438 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1646298438
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2921230837
Short name T88
Test name
Test status
Simulation time 456784267425 ps
CPU time 863.49 seconds
Started Jul 02 09:17:56 AM PDT 24
Finished Jul 02 09:32:20 AM PDT 24
Peak memory 214832 kb
Host smart-299abfec-17a8-469c-8fa1-a9af81bbe27c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921230837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2921230837
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3920484204
Short name T29
Test name
Test status
Simulation time 38838443383 ps
CPU time 397 seconds
Started Jul 02 09:17:17 AM PDT 24
Finished Jul 02 09:23:55 AM PDT 24
Peak memory 199684 kb
Host smart-e2e910fd-f87e-40b9-af9c-50518052d461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920484204 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3920484204
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1108328978
Short name T14
Test name
Test status
Simulation time 112920685001 ps
CPU time 163.19 seconds
Started Jul 02 09:17:07 AM PDT 24
Finished Jul 02 09:19:51 AM PDT 24
Peak memory 192424 kb
Host smart-b1a09559-4579-4e76-9dc2-ba767d954115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108328978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1108328978
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.688646727
Short name T16
Test name
Test status
Simulation time 8224518014 ps
CPU time 6.86 seconds
Started Jul 02 09:17:00 AM PDT 24
Finished Jul 02 09:17:08 AM PDT 24
Peak memory 215844 kb
Host smart-aaf46090-14a8-46a1-8c3b-411a4a3f6363
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688646727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.688646727
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1710077369
Short name T91
Test name
Test status
Simulation time 67517283056 ps
CPU time 125.7 seconds
Started Jul 02 09:17:46 AM PDT 24
Finished Jul 02 09:19:52 AM PDT 24
Peak memory 206640 kb
Host smart-1be3d16c-aa45-4c7c-b804-8f5ae1b17208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710077369 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1710077369
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3087989429
Short name T117
Test name
Test status
Simulation time 18766665718 ps
CPU time 4.87 seconds
Started Jul 02 09:18:03 AM PDT 24
Finished Jul 02 09:18:08 AM PDT 24
Peak memory 184236 kb
Host smart-c538a204-d0c6-490b-a0bc-b20d4393542a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087989429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3087989429
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1237679006
Short name T4
Test name
Test status
Simulation time 22136070153 ps
CPU time 197.19 seconds
Started Jul 02 09:17:53 AM PDT 24
Finished Jul 02 09:21:11 AM PDT 24
Peak memory 206640 kb
Host smart-df3225b5-fc17-45fa-94be-3d1c705c03ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237679006 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1237679006
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3241639919
Short name T93
Test name
Test status
Simulation time 27777459854 ps
CPU time 211.26 seconds
Started Jul 02 09:17:12 AM PDT 24
Finished Jul 02 09:20:45 AM PDT 24
Peak memory 198404 kb
Host smart-45370fd4-8e31-40f5-9806-a12d86225a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241639919 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3241639919
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.933679420
Short name T104
Test name
Test status
Simulation time 48955213137 ps
CPU time 526.07 seconds
Started Jul 02 09:17:21 AM PDT 24
Finished Jul 02 09:26:08 AM PDT 24
Peak memory 213860 kb
Host smart-8efd2e70-54f1-49d5-92c3-05ce7a17f2e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933679420 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.933679420
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.4253263662
Short name T100
Test name
Test status
Simulation time 156340893941 ps
CPU time 16.14 seconds
Started Jul 02 09:17:37 AM PDT 24
Finished Jul 02 09:17:55 AM PDT 24
Peak memory 192836 kb
Host smart-f3ebf14b-2cf9-4ab9-9f1a-475a6b518434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253263662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.4253263662
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2489512453
Short name T68
Test name
Test status
Simulation time 403529595 ps
CPU time 1.29 seconds
Started Jul 02 09:49:59 AM PDT 24
Finished Jul 02 09:50:08 AM PDT 24
Peak memory 194064 kb
Host smart-8526354b-ef4d-4818-bcce-5b66227cb641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489512453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2489512453
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1674781405
Short name T111
Test name
Test status
Simulation time 113803235908 ps
CPU time 154.95 seconds
Started Jul 02 09:17:46 AM PDT 24
Finished Jul 02 09:20:21 AM PDT 24
Peak memory 192824 kb
Host smart-a82cd70e-56dc-425b-978a-f8b4acb1bd89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674781405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1674781405
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2181761210
Short name T17
Test name
Test status
Simulation time 93045832360 ps
CPU time 42.81 seconds
Started Jul 02 09:17:37 AM PDT 24
Finished Jul 02 09:18:21 AM PDT 24
Peak memory 191676 kb
Host smart-3f5376c3-8eff-43ee-af16-e7f8ec03bfc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181761210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2181761210
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1350677779
Short name T132
Test name
Test status
Simulation time 165132138617 ps
CPU time 57.86 seconds
Started Jul 02 09:17:03 AM PDT 24
Finished Jul 02 09:18:02 AM PDT 24
Peak memory 191736 kb
Host smart-48fac1b0-f5fd-45e1-9af6-3381a3d941f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350677779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1350677779
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2382499067
Short name T123
Test name
Test status
Simulation time 158325668768 ps
CPU time 54.35 seconds
Started Jul 02 09:17:47 AM PDT 24
Finished Jul 02 09:18:42 AM PDT 24
Peak memory 198056 kb
Host smart-d275b55a-6234-4b77-af3f-96fe79975ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382499067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2382499067
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2081289658
Short name T97
Test name
Test status
Simulation time 250454675274 ps
CPU time 480.56 seconds
Started Jul 02 09:17:34 AM PDT 24
Finished Jul 02 09:25:35 AM PDT 24
Peak memory 211856 kb
Host smart-2ef221d3-905b-4074-b25c-c5a75b2a33ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081289658 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2081289658
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3407741648
Short name T106
Test name
Test status
Simulation time 84907185633 ps
CPU time 120.29 seconds
Started Jul 02 09:17:59 AM PDT 24
Finished Jul 02 09:20:00 AM PDT 24
Peak memory 198040 kb
Host smart-5dcfb852-304a-4964-8d37-d48d482470be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407741648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3407741648
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.497774136
Short name T136
Test name
Test status
Simulation time 126739837520 ps
CPU time 86.43 seconds
Started Jul 02 09:17:29 AM PDT 24
Finished Jul 02 09:18:57 AM PDT 24
Peak memory 191700 kb
Host smart-d8150065-266a-4626-8f4b-f2e0bf1e6de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497774136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.497774136
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.982411168
Short name T107
Test name
Test status
Simulation time 84705980004 ps
CPU time 33.61 seconds
Started Jul 02 09:17:20 AM PDT 24
Finished Jul 02 09:17:54 AM PDT 24
Peak memory 191696 kb
Host smart-f1b64ca5-07eb-4850-b654-220444575454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982411168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.982411168
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.617699238
Short name T129
Test name
Test status
Simulation time 367759812413 ps
CPU time 100.75 seconds
Started Jul 02 09:17:13 AM PDT 24
Finished Jul 02 09:18:55 AM PDT 24
Peak memory 192684 kb
Host smart-eec700e7-bcf2-48fe-bcd0-7cfe68d09bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617699238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.617699238
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.467296625
Short name T37
Test name
Test status
Simulation time 307212006928 ps
CPU time 244.97 seconds
Started Jul 02 09:17:02 AM PDT 24
Finished Jul 02 09:21:07 AM PDT 24
Peak memory 192484 kb
Host smart-ff946414-e066-4069-a4ba-fea73dd96680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467296625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.467296625
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2179131369
Short name T101
Test name
Test status
Simulation time 111618326579 ps
CPU time 36.72 seconds
Started Jul 02 09:17:24 AM PDT 24
Finished Jul 02 09:18:01 AM PDT 24
Peak memory 184000 kb
Host smart-3e7969f7-07ed-40ac-b2e7-b5e33d977706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179131369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2179131369
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.130761219
Short name T113
Test name
Test status
Simulation time 259665210685 ps
CPU time 116.1 seconds
Started Jul 02 09:17:25 AM PDT 24
Finished Jul 02 09:19:22 AM PDT 24
Peak memory 191732 kb
Host smart-b6043546-5036-431c-8047-9fb341c48f82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130761219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.130761219
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.594329231
Short name T44
Test name
Test status
Simulation time 267104314858 ps
CPU time 177.4 seconds
Started Jul 02 09:17:25 AM PDT 24
Finished Jul 02 09:20:23 AM PDT 24
Peak memory 198028 kb
Host smart-eecf17fd-3053-4b48-8cbe-4af5dfe7fa3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594329231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.594329231
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1891824663
Short name T83
Test name
Test status
Simulation time 178642348215 ps
CPU time 1024.26 seconds
Started Jul 02 09:17:46 AM PDT 24
Finished Jul 02 09:34:52 AM PDT 24
Peak memory 214856 kb
Host smart-9934a0f9-78fc-4386-8b15-36f1718a75d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891824663 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1891824663
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.4165647984
Short name T92
Test name
Test status
Simulation time 73584116840 ps
CPU time 157.48 seconds
Started Jul 02 09:18:08 AM PDT 24
Finished Jul 02 09:20:46 AM PDT 24
Peak memory 198828 kb
Host smart-f56982d3-c4d4-4211-a103-a51711a84f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165647984 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.4165647984
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.725098571
Short name T150
Test name
Test status
Simulation time 196572108556 ps
CPU time 47.75 seconds
Started Jul 02 09:17:11 AM PDT 24
Finished Jul 02 09:18:00 AM PDT 24
Peak memory 191708 kb
Host smart-59bdeaea-ab68-4bc1-a49e-ccab7751485c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725098571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.725098571
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2919891149
Short name T140
Test name
Test status
Simulation time 113710611574 ps
CPU time 43.11 seconds
Started Jul 02 09:17:32 AM PDT 24
Finished Jul 02 09:18:16 AM PDT 24
Peak memory 198096 kb
Host smart-3a7554b8-9f58-4390-a267-0aac29d58291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919891149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2919891149
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2992222082
Short name T145
Test name
Test status
Simulation time 135576782468 ps
CPU time 178.35 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:20:41 AM PDT 24
Peak memory 206576 kb
Host smart-28918b97-9abb-4f09-8bd4-0774ec5cc8d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992222082 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2992222082
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.851530063
Short name T96
Test name
Test status
Simulation time 173667329360 ps
CPU time 277.57 seconds
Started Jul 02 09:17:45 AM PDT 24
Finished Jul 02 09:22:24 AM PDT 24
Peak memory 198268 kb
Host smart-4448b2ec-221d-49e4-9dcc-f6a15f80f7b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851530063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.851530063
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1930581198
Short name T126
Test name
Test status
Simulation time 97193580039 ps
CPU time 145.39 seconds
Started Jul 02 09:17:55 AM PDT 24
Finished Jul 02 09:20:21 AM PDT 24
Peak memory 184028 kb
Host smart-199fd328-7a97-4baa-96ff-6a6fd888b230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930581198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1930581198
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1803057734
Short name T142
Test name
Test status
Simulation time 37265157370 ps
CPU time 53.56 seconds
Started Jul 02 09:17:16 AM PDT 24
Finished Jul 02 09:18:10 AM PDT 24
Peak memory 191692 kb
Host smart-32658f4d-1eb1-4317-bdef-7f236f2f7bdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803057734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1803057734
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2783011372
Short name T49
Test name
Test status
Simulation time 128465324286 ps
CPU time 511.53 seconds
Started Jul 02 09:18:02 AM PDT 24
Finished Jul 02 09:26:34 AM PDT 24
Peak memory 211800 kb
Host smart-8bee57f5-3a89-4803-8e2b-51bf808ef31d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783011372 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2783011372
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.905481714
Short name T153
Test name
Test status
Simulation time 64718830159 ps
CPU time 443.24 seconds
Started Jul 02 09:17:00 AM PDT 24
Finished Jul 02 09:24:25 AM PDT 24
Peak memory 206680 kb
Host smart-9a65347a-41aa-45e8-a5a6-c5f233cf179d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905481714 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.905481714
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.4047761088
Short name T102
Test name
Test status
Simulation time 513662795091 ps
CPU time 72.6 seconds
Started Jul 02 09:17:46 AM PDT 24
Finished Jul 02 09:19:00 AM PDT 24
Peak memory 192896 kb
Host smart-2b76b126-2d2e-4d79-94a8-806b502624a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047761088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.4047761088
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3456021194
Short name T115
Test name
Test status
Simulation time 42947364763 ps
CPU time 66.52 seconds
Started Jul 02 09:17:57 AM PDT 24
Finished Jul 02 09:19:04 AM PDT 24
Peak memory 198020 kb
Host smart-53a2c02e-e440-438d-9307-3e825e14a730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456021194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3456021194
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.741797977
Short name T130
Test name
Test status
Simulation time 103766081681 ps
CPU time 214.13 seconds
Started Jul 02 09:17:22 AM PDT 24
Finished Jul 02 09:20:57 AM PDT 24
Peak memory 208368 kb
Host smart-6d8c37d0-706c-45bf-ac35-35dc1cf1e977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741797977 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.741797977
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.233689375
Short name T109
Test name
Test status
Simulation time 797603784816 ps
CPU time 1051.44 seconds
Started Jul 02 09:17:35 AM PDT 24
Finished Jul 02 09:35:08 AM PDT 24
Peak memory 184304 kb
Host smart-4c3bb886-ae07-4245-81cd-5a4cb2a067aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233689375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.233689375
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.314187770
Short name T138
Test name
Test status
Simulation time 220266303671 ps
CPU time 165.09 seconds
Started Jul 02 09:17:11 AM PDT 24
Finished Jul 02 09:19:56 AM PDT 24
Peak memory 198100 kb
Host smart-107b26ff-1057-424b-be6b-bdf79363f3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314187770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.314187770
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3178707796
Short name T144
Test name
Test status
Simulation time 436233810914 ps
CPU time 244.33 seconds
Started Jul 02 09:17:26 AM PDT 24
Finished Jul 02 09:21:30 AM PDT 24
Peak memory 198068 kb
Host smart-f60a5b16-cdc6-46bb-be1a-2190be7b80de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178707796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3178707796
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3081260517
Short name T87
Test name
Test status
Simulation time 65653676872 ps
CPU time 501.62 seconds
Started Jul 02 09:17:33 AM PDT 24
Finished Jul 02 09:25:55 AM PDT 24
Peak memory 210692 kb
Host smart-106b28a6-f766-4401-a76c-737ee8318ee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081260517 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3081260517
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2552627963
Short name T168
Test name
Test status
Simulation time 23484094058 ps
CPU time 31.85 seconds
Started Jul 02 09:17:37 AM PDT 24
Finished Jul 02 09:18:09 AM PDT 24
Peak memory 198064 kb
Host smart-0311d719-2c59-40bb-8327-4cdf255c583a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552627963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2552627963
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3939523760
Short name T32
Test name
Test status
Simulation time 28269510646 ps
CPU time 181.29 seconds
Started Jul 02 09:17:37 AM PDT 24
Finished Jul 02 09:20:40 AM PDT 24
Peak memory 214756 kb
Host smart-d5b133c0-3360-4b9b-84cc-1bcf9f910f76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939523760 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3939523760
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3937940884
Short name T135
Test name
Test status
Simulation time 407776592921 ps
CPU time 316.06 seconds
Started Jul 02 09:18:05 AM PDT 24
Finished Jul 02 09:23:22 AM PDT 24
Peak memory 192752 kb
Host smart-ad8cb3b7-fa2d-4ede-b42e-022017648814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937940884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3937940884
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2906721157
Short name T33
Test name
Test status
Simulation time 75918187540 ps
CPU time 505.52 seconds
Started Jul 02 09:17:41 AM PDT 24
Finished Jul 02 09:26:07 AM PDT 24
Peak memory 201004 kb
Host smart-1db62f14-3ed6-49b1-9931-1a6fcaa23608
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906721157 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2906721157
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2690929200
Short name T94
Test name
Test status
Simulation time 41312133945 ps
CPU time 69.97 seconds
Started Jul 02 09:17:03 AM PDT 24
Finished Jul 02 09:18:14 AM PDT 24
Peak memory 198436 kb
Host smart-efa452d5-84b1-4bfd-a216-82d073799197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690929200 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2690929200
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.459828281
Short name T114
Test name
Test status
Simulation time 159639860864 ps
CPU time 204.32 seconds
Started Jul 02 09:17:48 AM PDT 24
Finished Jul 02 09:21:12 AM PDT 24
Peak memory 198068 kb
Host smart-a75e1bd0-76e9-4e05-9f14-f20a16ccd0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459828281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.459828281
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2886220965
Short name T110
Test name
Test status
Simulation time 58693091047 ps
CPU time 46.07 seconds
Started Jul 02 09:18:02 AM PDT 24
Finished Jul 02 09:18:49 AM PDT 24
Peak memory 192356 kb
Host smart-7590315a-71a0-4824-83eb-d1954a50cab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886220965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2886220965
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.4119818933
Short name T157
Test name
Test status
Simulation time 176143849321 ps
CPU time 384.49 seconds
Started Jul 02 09:17:30 AM PDT 24
Finished Jul 02 09:23:55 AM PDT 24
Peak memory 210580 kb
Host smart-4f7d5b2a-859a-4068-9a26-d2fc5a14c785
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119818933 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.4119818933
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.902993394
Short name T134
Test name
Test status
Simulation time 239591885235 ps
CPU time 85.18 seconds
Started Jul 02 09:17:36 AM PDT 24
Finished Jul 02 09:19:01 AM PDT 24
Peak memory 198248 kb
Host smart-2a463d2b-48a3-445f-961a-c8854786b786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902993394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.902993394
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3010942368
Short name T127
Test name
Test status
Simulation time 197889008611 ps
CPU time 103.54 seconds
Started Jul 02 09:17:54 AM PDT 24
Finished Jul 02 09:19:38 AM PDT 24
Peak memory 206992 kb
Host smart-8ace933d-0208-4cbd-9f20-9b593ce65b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010942368 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3010942368
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4017211318
Short name T89
Test name
Test status
Simulation time 135417395196 ps
CPU time 272.05 seconds
Started Jul 02 09:17:08 AM PDT 24
Finished Jul 02 09:21:41 AM PDT 24
Peak memory 200748 kb
Host smart-f83240bf-a703-455b-9188-bc7bc132df4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017211318 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4017211318
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1856927912
Short name T165
Test name
Test status
Simulation time 122979804192 ps
CPU time 508.85 seconds
Started Jul 02 09:17:16 AM PDT 24
Finished Jul 02 09:25:46 AM PDT 24
Peak memory 206656 kb
Host smart-2aaeb6d4-3eef-432d-be9e-34d245c4aea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856927912 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1856927912
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.4015727139
Short name T35
Test name
Test status
Simulation time 244843583905 ps
CPU time 95.15 seconds
Started Jul 02 09:17:33 AM PDT 24
Finished Jul 02 09:19:09 AM PDT 24
Peak memory 191708 kb
Host smart-9509db58-5a1b-4085-a323-5d0f0b11d9d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015727139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.4015727139
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.409324940
Short name T163
Test name
Test status
Simulation time 57473268548 ps
CPU time 340.99 seconds
Started Jul 02 09:17:43 AM PDT 24
Finished Jul 02 09:23:25 AM PDT 24
Peak memory 207924 kb
Host smart-58cedb2c-4725-4d14-8a24-dd83515edab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409324940 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.409324940
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3526988188
Short name T112
Test name
Test status
Simulation time 317998633757 ps
CPU time 393.06 seconds
Started Jul 02 09:18:07 AM PDT 24
Finished Jul 02 09:24:41 AM PDT 24
Peak memory 192584 kb
Host smart-6b6e9613-4d1c-49de-bc56-a72267e360e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526988188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3526988188
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.695077991
Short name T31
Test name
Test status
Simulation time 19800506317 ps
CPU time 205.83 seconds
Started Jul 02 09:18:05 AM PDT 24
Finished Jul 02 09:21:32 AM PDT 24
Peak memory 206892 kb
Host smart-6e356ab1-6e87-4337-a5c6-d5912d91a659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695077991 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.695077991
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.444057151
Short name T103
Test name
Test status
Simulation time 38013649856 ps
CPU time 4.32 seconds
Started Jul 02 09:17:18 AM PDT 24
Finished Jul 02 09:17:23 AM PDT 24
Peak memory 192744 kb
Host smart-9aec18bf-a19d-4407-95e6-71c26f16484a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444057151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.444057151
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2013297363
Short name T46
Test name
Test status
Simulation time 55853798906 ps
CPU time 67.04 seconds
Started Jul 02 09:17:38 AM PDT 24
Finished Jul 02 09:18:46 AM PDT 24
Peak memory 192788 kb
Host smart-11a1bd20-1f24-4a99-9cc9-6d7fea52c030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013297363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2013297363
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1968616691
Short name T65
Test name
Test status
Simulation time 360924162936 ps
CPU time 144.95 seconds
Started Jul 02 09:17:49 AM PDT 24
Finished Jul 02 09:20:14 AM PDT 24
Peak memory 207352 kb
Host smart-d870c25b-2acd-4a02-a336-0ef3d11cc42e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968616691 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1968616691
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2970143576
Short name T128
Test name
Test status
Simulation time 16791955026 ps
CPU time 24.18 seconds
Started Jul 02 09:18:00 AM PDT 24
Finished Jul 02 09:18:25 AM PDT 24
Peak memory 192796 kb
Host smart-acfd67e8-9f9c-4f47-b7a0-831f1e970de2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970143576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2970143576
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3098999922
Short name T148
Test name
Test status
Simulation time 189497682669 ps
CPU time 279.08 seconds
Started Jul 02 09:17:59 AM PDT 24
Finished Jul 02 09:22:39 AM PDT 24
Peak memory 209028 kb
Host smart-564c5f43-b859-4a3e-8a63-871981caed46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098999922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3098999922
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3177488800
Short name T160
Test name
Test status
Simulation time 24769397479 ps
CPU time 65.47 seconds
Started Jul 02 09:18:09 AM PDT 24
Finished Jul 02 09:19:15 AM PDT 24
Peak memory 198372 kb
Host smart-54d71488-8c27-486d-a491-9218fc958801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177488800 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3177488800
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2015013741
Short name T47
Test name
Test status
Simulation time 31830056024 ps
CPU time 329.88 seconds
Started Jul 02 09:17:38 AM PDT 24
Finished Jul 02 09:23:09 AM PDT 24
Peak memory 206620 kb
Host smart-6f6aaf7f-f26d-4616-80eb-476cc90de978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015013741 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2015013741
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3951630853
Short name T161
Test name
Test status
Simulation time 603724147 ps
CPU time 0.9 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:17:43 AM PDT 24
Peak memory 196564 kb
Host smart-54be5772-5b8f-441c-b343-a995b1a97c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951630853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3951630853
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.97598970
Short name T131
Test name
Test status
Simulation time 273681980460 ps
CPU time 155.44 seconds
Started Jul 02 09:17:55 AM PDT 24
Finished Jul 02 09:20:31 AM PDT 24
Peak memory 206644 kb
Host smart-5876d7e0-8880-41b0-8c29-5b03eba2ea00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97598970 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.97598970
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2289414507
Short name T158
Test name
Test status
Simulation time 366448981 ps
CPU time 0.75 seconds
Started Jul 02 09:18:03 AM PDT 24
Finished Jul 02 09:18:04 AM PDT 24
Peak memory 196472 kb
Host smart-2caa597f-08f6-4a1b-804d-ac7bdd2a5a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289414507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2289414507
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2723243084
Short name T23
Test name
Test status
Simulation time 22153089043 ps
CPU time 93.18 seconds
Started Jul 02 09:17:13 AM PDT 24
Finished Jul 02 09:18:47 AM PDT 24
Peak memory 198468 kb
Host smart-42b0d401-ed5c-4db8-9eb0-551b480015e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723243084 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2723243084
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1643733789
Short name T60
Test name
Test status
Simulation time 576045297 ps
CPU time 0.79 seconds
Started Jul 02 09:17:20 AM PDT 24
Finished Jul 02 09:17:21 AM PDT 24
Peak memory 196584 kb
Host smart-b50a096d-7360-4055-810e-5d10ac3eef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643733789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1643733789
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4274300995
Short name T34
Test name
Test status
Simulation time 245265926342 ps
CPU time 241.25 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:21:43 AM PDT 24
Peak memory 214824 kb
Host smart-9e6f38ee-100f-4696-b813-123413b5d26d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274300995 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4274300995
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3462056032
Short name T149
Test name
Test status
Simulation time 559787012 ps
CPU time 1 seconds
Started Jul 02 09:17:43 AM PDT 24
Finished Jul 02 09:17:45 AM PDT 24
Peak memory 196480 kb
Host smart-ed218247-6aa0-40e9-9952-b60371b3ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462056032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3462056032
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3948044649
Short name T147
Test name
Test status
Simulation time 24708252113 ps
CPU time 28.33 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:18:11 AM PDT 24
Peak memory 192784 kb
Host smart-ffc0d1db-a52a-43b5-a536-ddcb36dd1c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948044649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3948044649
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1356519459
Short name T133
Test name
Test status
Simulation time 488824243 ps
CPU time 0.99 seconds
Started Jul 02 09:17:56 AM PDT 24
Finished Jul 02 09:17:58 AM PDT 24
Peak memory 196500 kb
Host smart-7ec2b89d-112b-470e-8249-5dfc4c6bd9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356519459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1356519459
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2458616353
Short name T121
Test name
Test status
Simulation time 208566916292 ps
CPU time 61.51 seconds
Started Jul 02 09:17:12 AM PDT 24
Finished Jul 02 09:18:14 AM PDT 24
Peak memory 198072 kb
Host smart-12fca88d-8f34-4d44-bb40-380daf56c9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458616353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2458616353
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1162444046
Short name T66
Test name
Test status
Simulation time 520227698 ps
CPU time 0.77 seconds
Started Jul 02 09:17:23 AM PDT 24
Finished Jul 02 09:17:25 AM PDT 24
Peak memory 196488 kb
Host smart-2473d6b1-ebbb-4b59-9afc-dee315834e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162444046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1162444046
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.390839516
Short name T10
Test name
Test status
Simulation time 36711032620 ps
CPU time 237.28 seconds
Started Jul 02 09:17:25 AM PDT 24
Finished Jul 02 09:21:23 AM PDT 24
Peak memory 206636 kb
Host smart-de114466-8a8a-425b-a483-7480f53a9a0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390839516 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.390839516
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.362554738
Short name T152
Test name
Test status
Simulation time 432324805 ps
CPU time 0.77 seconds
Started Jul 02 09:17:34 AM PDT 24
Finished Jul 02 09:17:35 AM PDT 24
Peak memory 196468 kb
Host smart-6c3cdd29-98ae-43fc-9987-b0697da2c1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362554738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.362554738
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3012906239
Short name T120
Test name
Test status
Simulation time 556669848 ps
CPU time 1.43 seconds
Started Jul 02 09:17:37 AM PDT 24
Finished Jul 02 09:17:39 AM PDT 24
Peak memory 196532 kb
Host smart-c10ca392-c59b-4427-8184-005068ce06b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012906239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3012906239
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2314234621
Short name T105
Test name
Test status
Simulation time 389656256183 ps
CPU time 118.71 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:19:41 AM PDT 24
Peak memory 192640 kb
Host smart-7ceba8d4-2b80-4d1f-a25b-21bb49f374ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314234621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2314234621
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2753968767
Short name T119
Test name
Test status
Simulation time 611711216 ps
CPU time 0.8 seconds
Started Jul 02 09:17:37 AM PDT 24
Finished Jul 02 09:17:39 AM PDT 24
Peak memory 196436 kb
Host smart-5bc24336-eb3f-4ba5-aa8a-596b03ea0fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753968767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2753968767
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1385420705
Short name T99
Test name
Test status
Simulation time 443073363 ps
CPU time 0.87 seconds
Started Jul 02 09:17:43 AM PDT 24
Finished Jul 02 09:17:45 AM PDT 24
Peak memory 196572 kb
Host smart-307c62c4-e971-477e-a321-1954d6b53f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385420705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1385420705
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1340323851
Short name T137
Test name
Test status
Simulation time 360785450 ps
CPU time 1.18 seconds
Started Jul 02 09:17:47 AM PDT 24
Finished Jul 02 09:17:49 AM PDT 24
Peak memory 196500 kb
Host smart-865a0d7f-8368-4956-b3a1-5fd5c920ea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340323851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1340323851
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2621339578
Short name T90
Test name
Test status
Simulation time 15945473062 ps
CPU time 122.64 seconds
Started Jul 02 09:17:52 AM PDT 24
Finished Jul 02 09:19:55 AM PDT 24
Peak memory 198488 kb
Host smart-e6230268-8bf0-4a6f-a278-6c7c840473fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621339578 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2621339578
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3742753110
Short name T154
Test name
Test status
Simulation time 58415574365 ps
CPU time 22.22 seconds
Started Jul 02 09:17:56 AM PDT 24
Finished Jul 02 09:18:19 AM PDT 24
Peak memory 191644 kb
Host smart-999e68d1-1e17-4b42-931b-5f29a1c1d0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742753110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3742753110
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1553013208
Short name T116
Test name
Test status
Simulation time 413151147 ps
CPU time 0.74 seconds
Started Jul 02 09:18:05 AM PDT 24
Finished Jul 02 09:18:07 AM PDT 24
Peak memory 196412 kb
Host smart-1f7c07ee-55ba-4b9d-bdd7-991c7ff1bb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553013208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1553013208
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1973148374
Short name T118
Test name
Test status
Simulation time 181013641566 ps
CPU time 58.33 seconds
Started Jul 02 09:18:11 AM PDT 24
Finished Jul 02 09:19:09 AM PDT 24
Peak memory 198068 kb
Host smart-cce0f418-7c07-4a8b-b009-391c1581a018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973148374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1973148374
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.512288573
Short name T146
Test name
Test status
Simulation time 373324343611 ps
CPU time 47.01 seconds
Started Jul 02 09:18:09 AM PDT 24
Finished Jul 02 09:18:57 AM PDT 24
Peak memory 192820 kb
Host smart-f04dc120-032a-484d-a2ce-47bf46cc747a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512288573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.512288573
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3019641156
Short name T164
Test name
Test status
Simulation time 176334538079 ps
CPU time 113.56 seconds
Started Jul 02 09:17:19 AM PDT 24
Finished Jul 02 09:19:13 AM PDT 24
Peak memory 191644 kb
Host smart-e06efa71-e231-4a31-b594-6c08422befec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019641156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3019641156
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.526321269
Short name T122
Test name
Test status
Simulation time 390125724 ps
CPU time 0.88 seconds
Started Jul 02 09:17:23 AM PDT 24
Finished Jul 02 09:17:24 AM PDT 24
Peak memory 196560 kb
Host smart-915430ba-00f8-4a8d-baed-b05943ccde51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526321269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.526321269
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2344479232
Short name T175
Test name
Test status
Simulation time 21813367116 ps
CPU time 228.94 seconds
Started Jul 02 09:17:44 AM PDT 24
Finished Jul 02 09:21:34 AM PDT 24
Peak memory 206644 kb
Host smart-00a4c27c-2f2a-4135-a962-8a4b2530392c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344479232 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2344479232
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1952960888
Short name T155
Test name
Test status
Simulation time 118617676376 ps
CPU time 168.85 seconds
Started Jul 02 09:17:44 AM PDT 24
Finished Jul 02 09:20:34 AM PDT 24
Peak memory 198008 kb
Host smart-f0434739-8533-488a-a038-3ead4083a74c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952960888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1952960888
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.738923074
Short name T124
Test name
Test status
Simulation time 440787440 ps
CPU time 1.23 seconds
Started Jul 02 09:17:43 AM PDT 24
Finished Jul 02 09:17:46 AM PDT 24
Peak memory 196448 kb
Host smart-8fbac904-2efc-40ca-85ab-fa59d9c5abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738923074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.738923074
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4175184174
Short name T182
Test name
Test status
Simulation time 266458052207 ps
CPU time 377.2 seconds
Started Jul 02 09:17:54 AM PDT 24
Finished Jul 02 09:24:12 AM PDT 24
Peak memory 191728 kb
Host smart-952ba125-a837-4dce-89b5-f5f7eda3047b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175184174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4175184174
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2866437232
Short name T169
Test name
Test status
Simulation time 254260736534 ps
CPU time 369.58 seconds
Started Jul 02 09:18:01 AM PDT 24
Finished Jul 02 09:24:11 AM PDT 24
Peak memory 198048 kb
Host smart-afaec488-9b99-4044-b886-198f27697ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866437232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2866437232
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.841742858
Short name T108
Test name
Test status
Simulation time 394318278 ps
CPU time 1.19 seconds
Started Jul 02 09:17:13 AM PDT 24
Finished Jul 02 09:17:15 AM PDT 24
Peak memory 196480 kb
Host smart-f6f02097-3305-45d1-82b4-02f1180c4fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841742858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.841742858
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.872198615
Short name T125
Test name
Test status
Simulation time 394893004 ps
CPU time 0.99 seconds
Started Jul 02 09:17:16 AM PDT 24
Finished Jul 02 09:17:18 AM PDT 24
Peak memory 196780 kb
Host smart-acc3a08c-333f-4227-a36c-312ba93be353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872198615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.872198615
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1942210212
Short name T95
Test name
Test status
Simulation time 499365024 ps
CPU time 0.96 seconds
Started Jul 02 09:17:37 AM PDT 24
Finished Jul 02 09:17:39 AM PDT 24
Peak memory 196496 kb
Host smart-04f7a70a-af36-4e25-a35c-7f44531502a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942210212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1942210212
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.747996189
Short name T180
Test name
Test status
Simulation time 50657949307 ps
CPU time 283.75 seconds
Started Jul 02 09:17:39 AM PDT 24
Finished Jul 02 09:22:24 AM PDT 24
Peak memory 207388 kb
Host smart-6a328161-05f1-4ba2-95be-8e82e7004c66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747996189 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.747996189
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1407913416
Short name T139
Test name
Test status
Simulation time 387946860 ps
CPU time 1.22 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:17:44 AM PDT 24
Peak memory 196472 kb
Host smart-2b6d6d9a-ac9c-4675-9893-7346b7096826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407913416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1407913416
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3501868085
Short name T174
Test name
Test status
Simulation time 325742510717 ps
CPU time 121.94 seconds
Started Jul 02 09:17:08 AM PDT 24
Finished Jul 02 09:19:11 AM PDT 24
Peak memory 192732 kb
Host smart-950f537f-368d-47be-ad71-3f57658e1704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501868085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3501868085
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2928930613
Short name T141
Test name
Test status
Simulation time 415910844 ps
CPU time 0.71 seconds
Started Jul 02 09:18:06 AM PDT 24
Finished Jul 02 09:18:07 AM PDT 24
Peak memory 196748 kb
Host smart-ab8af6df-ea76-45e2-a940-04e11a3f4de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928930613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2928930613
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2735957336
Short name T156
Test name
Test status
Simulation time 460984647 ps
CPU time 1.28 seconds
Started Jul 02 09:18:07 AM PDT 24
Finished Jul 02 09:18:09 AM PDT 24
Peak memory 196572 kb
Host smart-b20d28f6-9637-40a2-8b7f-6252efaf1911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735957336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2735957336
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1512833616
Short name T181
Test name
Test status
Simulation time 46102802939 ps
CPU time 245.54 seconds
Started Jul 02 09:17:08 AM PDT 24
Finished Jul 02 09:21:15 AM PDT 24
Peak memory 206624 kb
Host smart-0d62ff04-4652-44c4-af1d-fb6f88a6b9dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512833616 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1512833616
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.545922938
Short name T162
Test name
Test status
Simulation time 518581539 ps
CPU time 0.74 seconds
Started Jul 02 09:17:00 AM PDT 24
Finished Jul 02 09:17:02 AM PDT 24
Peak memory 196528 kb
Host smart-bd940bea-57e1-4272-87be-39cbe7694d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545922938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.545922938
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.953972774
Short name T172
Test name
Test status
Simulation time 607110614 ps
CPU time 1.09 seconds
Started Jul 02 09:17:23 AM PDT 24
Finished Jul 02 09:17:24 AM PDT 24
Peak memory 196392 kb
Host smart-8f0a1e6e-5449-4123-b646-2e6c9ae65e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953972774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.953972774
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3141246057
Short name T159
Test name
Test status
Simulation time 355938643 ps
CPU time 1.16 seconds
Started Jul 02 09:17:30 AM PDT 24
Finished Jul 02 09:17:32 AM PDT 24
Peak memory 196516 kb
Host smart-1789c6db-5fae-4a51-adc1-a24643273802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141246057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3141246057
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.795313982
Short name T12
Test name
Test status
Simulation time 518580995 ps
CPU time 0.77 seconds
Started Jul 02 09:17:38 AM PDT 24
Finished Jul 02 09:17:40 AM PDT 24
Peak memory 196568 kb
Host smart-338729bd-ea06-4c93-884a-bf20bf5789cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795313982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.795313982
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2976965031
Short name T184
Test name
Test status
Simulation time 456865253 ps
CPU time 1.31 seconds
Started Jul 02 09:17:08 AM PDT 24
Finished Jul 02 09:17:10 AM PDT 24
Peak memory 196548 kb
Host smart-c9c161c2-fa70-40f2-8cae-d61c8dc83c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976965031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2976965031
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4048312717
Short name T151
Test name
Test status
Simulation time 551596142 ps
CPU time 1.44 seconds
Started Jul 02 09:17:47 AM PDT 24
Finished Jul 02 09:17:49 AM PDT 24
Peak memory 196488 kb
Host smart-d824be93-e3af-4610-aefb-9b9d00d4ed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048312717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4048312717
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3499652791
Short name T9
Test name
Test status
Simulation time 458915278 ps
CPU time 1.18 seconds
Started Jul 02 09:17:55 AM PDT 24
Finished Jul 02 09:17:57 AM PDT 24
Peak memory 196484 kb
Host smart-7271fac1-9e95-4ec2-b5a1-9acb5475fe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499652791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3499652791
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3991177666
Short name T186
Test name
Test status
Simulation time 443700477 ps
CPU time 1.31 seconds
Started Jul 02 09:17:07 AM PDT 24
Finished Jul 02 09:17:10 AM PDT 24
Peak memory 196424 kb
Host smart-1df3d4f1-576e-4308-9072-7814f68fae8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991177666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3991177666
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.109704044
Short name T38
Test name
Test status
Simulation time 474391634 ps
CPU time 0.69 seconds
Started Jul 02 09:17:02 AM PDT 24
Finished Jul 02 09:17:03 AM PDT 24
Peak memory 196516 kb
Host smart-792eb5c0-c61b-4d6b-84f5-beaedf98bcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109704044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.109704044
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1788869498
Short name T85
Test name
Test status
Simulation time 62324885366 ps
CPU time 175.99 seconds
Started Jul 02 09:17:01 AM PDT 24
Finished Jul 02 09:19:58 AM PDT 24
Peak memory 206652 kb
Host smart-d97d6879-ee98-4bc0-8f17-eeaaef45129e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788869498 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1788869498
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2240108734
Short name T173
Test name
Test status
Simulation time 443356915 ps
CPU time 0.69 seconds
Started Jul 02 09:17:29 AM PDT 24
Finished Jul 02 09:17:30 AM PDT 24
Peak memory 196460 kb
Host smart-1071b4ad-475a-4783-aec3-ec3ec258bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240108734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2240108734
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3543963087
Short name T143
Test name
Test status
Simulation time 520517832 ps
CPU time 1.38 seconds
Started Jul 02 09:17:48 AM PDT 24
Finished Jul 02 09:17:50 AM PDT 24
Peak memory 196448 kb
Host smart-81578cce-1e7b-4434-a711-dc29153be036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543963087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3543963087
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3189094946
Short name T190
Test name
Test status
Simulation time 516441847 ps
CPU time 0.81 seconds
Started Jul 02 09:17:57 AM PDT 24
Finished Jul 02 09:17:58 AM PDT 24
Peak memory 196520 kb
Host smart-e4453617-48f1-464e-9a7b-34ed1d6798e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189094946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3189094946
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1374044954
Short name T170
Test name
Test status
Simulation time 413722488 ps
CPU time 0.67 seconds
Started Jul 02 09:18:01 AM PDT 24
Finished Jul 02 09:18:02 AM PDT 24
Peak memory 196500 kb
Host smart-1da1a015-ec83-4510-8cd5-f7f6e7fd3af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374044954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1374044954
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1948418989
Short name T179
Test name
Test status
Simulation time 367177902 ps
CPU time 0.76 seconds
Started Jul 02 09:18:05 AM PDT 24
Finished Jul 02 09:18:07 AM PDT 24
Peak memory 196648 kb
Host smart-e4a35296-c0c1-4fc5-80b8-c74c8fc52234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948418989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1948418989
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.840151930
Short name T192
Test name
Test status
Simulation time 373866801 ps
CPU time 0.68 seconds
Started Jul 02 09:17:18 AM PDT 24
Finished Jul 02 09:17:19 AM PDT 24
Peak memory 196364 kb
Host smart-492ef41b-c7fb-4173-80f1-d9f56722445b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840151930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.840151930
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.275812741
Short name T378
Test name
Test status
Simulation time 9101924892 ps
CPU time 2.68 seconds
Started Jul 02 09:50:02 AM PDT 24
Finished Jul 02 09:50:12 AM PDT 24
Peak memory 198156 kb
Host smart-bbf6ec74-20a8-47ca-bfcb-b027f3e99cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275812741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.275812741
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.63823907
Short name T171
Test name
Test status
Simulation time 531059520 ps
CPU time 1.36 seconds
Started Jul 02 09:17:16 AM PDT 24
Finished Jul 02 09:17:18 AM PDT 24
Peak memory 196380 kb
Host smart-839739e9-9331-46cb-b06b-9f685fd3a4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63823907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.63823907
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2376665459
Short name T189
Test name
Test status
Simulation time 497561570 ps
CPU time 0.81 seconds
Started Jul 02 09:17:25 AM PDT 24
Finished Jul 02 09:17:26 AM PDT 24
Peak memory 196368 kb
Host smart-3a600b95-da16-4ef3-81ee-1838c9ac4b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376665459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2376665459
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2285389556
Short name T187
Test name
Test status
Simulation time 490246922 ps
CPU time 0.74 seconds
Started Jul 02 09:17:32 AM PDT 24
Finished Jul 02 09:17:34 AM PDT 24
Peak memory 196468 kb
Host smart-8d709691-9e18-4491-bf87-7e066e4b7cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285389556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2285389556
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3781675833
Short name T62
Test name
Test status
Simulation time 83217007582 ps
CPU time 326.91 seconds
Started Jul 02 09:17:29 AM PDT 24
Finished Jul 02 09:22:57 AM PDT 24
Peak memory 213796 kb
Host smart-59a1a62d-bc01-4319-b889-72710caafea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781675833 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3781675833
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.207187852
Short name T36
Test name
Test status
Simulation time 586076133 ps
CPU time 0.7 seconds
Started Jul 02 09:17:04 AM PDT 24
Finished Jul 02 09:17:05 AM PDT 24
Peak memory 196552 kb
Host smart-dcb238d3-102b-4ce5-bfb1-a6454047a9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207187852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.207187852
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2346756622
Short name T194
Test name
Test status
Simulation time 391814969 ps
CPU time 0.89 seconds
Started Jul 02 09:17:36 AM PDT 24
Finished Jul 02 09:17:38 AM PDT 24
Peak memory 196460 kb
Host smart-47712a24-4743-4aad-9267-39f4b6146fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346756622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2346756622
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.625325691
Short name T21
Test name
Test status
Simulation time 460312849 ps
CPU time 1.3 seconds
Started Jul 02 09:17:48 AM PDT 24
Finished Jul 02 09:17:50 AM PDT 24
Peak memory 196440 kb
Host smart-b9a5eab1-539e-4953-8c13-3ebe156e2256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625325691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.625325691
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2184731989
Short name T177
Test name
Test status
Simulation time 862893701418 ps
CPU time 319.52 seconds
Started Jul 02 09:17:53 AM PDT 24
Finished Jul 02 09:23:13 AM PDT 24
Peak memory 192232 kb
Host smart-33877042-6e8c-4583-ab02-a5273847a84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184731989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2184731989
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2511256551
Short name T185
Test name
Test status
Simulation time 378180961 ps
CPU time 1.25 seconds
Started Jul 02 09:17:54 AM PDT 24
Finished Jul 02 09:17:55 AM PDT 24
Peak memory 196464 kb
Host smart-c2d9a5b9-5a7c-41ea-be47-5a60e2a435d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511256551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2511256551
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3310433466
Short name T183
Test name
Test status
Simulation time 564112275 ps
CPU time 0.8 seconds
Started Jul 02 09:18:01 AM PDT 24
Finished Jul 02 09:18:02 AM PDT 24
Peak memory 196428 kb
Host smart-cc8bb0b5-6ccf-442c-a9b6-d2e065d74d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310433466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3310433466
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.419661915
Short name T191
Test name
Test status
Simulation time 585199267 ps
CPU time 0.82 seconds
Started Jul 02 09:18:06 AM PDT 24
Finished Jul 02 09:18:07 AM PDT 24
Peak memory 196364 kb
Host smart-d871f78f-8103-4346-bd1d-b48286cfee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419661915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.419661915
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.747975347
Short name T193
Test name
Test status
Simulation time 454320425 ps
CPU time 0.74 seconds
Started Jul 02 09:17:08 AM PDT 24
Finished Jul 02 09:17:09 AM PDT 24
Peak memory 196472 kb
Host smart-87eca4bc-b54c-4831-be0e-6d2033a58204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747975347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.747975347
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.350347448
Short name T371
Test name
Test status
Simulation time 468264733 ps
CPU time 1.3 seconds
Started Jul 02 09:49:47 AM PDT 24
Finished Jul 02 09:49:52 AM PDT 24
Peak memory 194076 kb
Host smart-28cc5e34-5188-40d2-b422-7f1c919bd378
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350347448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.350347448
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.398976560
Short name T310
Test name
Test status
Simulation time 13996150051 ps
CPU time 4.05 seconds
Started Jul 02 09:49:30 AM PDT 24
Finished Jul 02 09:49:38 AM PDT 24
Peak memory 192276 kb
Host smart-6872ae18-41ad-45da-9458-37fd2284fab1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398976560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.398976560
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1254905722
Short name T51
Test name
Test status
Simulation time 1215444466 ps
CPU time 1.02 seconds
Started Jul 02 09:49:59 AM PDT 24
Finished Jul 02 09:50:07 AM PDT 24
Peak memory 193216 kb
Host smart-0835a609-31d0-42f4-919a-ee4fa3f53748
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254905722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1254905722
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1522395838
Short name T413
Test name
Test status
Simulation time 433216784 ps
CPU time 1.08 seconds
Started Jul 02 09:49:29 AM PDT 24
Finished Jul 02 09:49:34 AM PDT 24
Peak memory 196180 kb
Host smart-4f5a8ad2-610a-4e77-a611-f28839ad2183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522395838 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1522395838
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3493719153
Short name T387
Test name
Test status
Simulation time 288628812 ps
CPU time 0.99 seconds
Started Jul 02 09:49:26 AM PDT 24
Finished Jul 02 09:49:31 AM PDT 24
Peak memory 192104 kb
Host smart-f66e90c7-dfde-429f-9b9b-42fba9f0c815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493719153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3493719153
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4113272769
Short name T303
Test name
Test status
Simulation time 434056839 ps
CPU time 0.61 seconds
Started Jul 02 09:49:46 AM PDT 24
Finished Jul 02 09:49:51 AM PDT 24
Peak memory 183768 kb
Host smart-d131da81-7b9d-474a-bae6-d67c5d91b37b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113272769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4113272769
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2797681168
Short name T291
Test name
Test status
Simulation time 398974825 ps
CPU time 1.01 seconds
Started Jul 02 09:49:33 AM PDT 24
Finished Jul 02 09:49:38 AM PDT 24
Peak memory 183712 kb
Host smart-2e8fabba-6db1-4fc7-b593-b6a6ffe9fcc4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797681168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2797681168
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3401408163
Short name T311
Test name
Test status
Simulation time 357931732 ps
CPU time 0.63 seconds
Started Jul 02 09:49:30 AM PDT 24
Finished Jul 02 09:49:35 AM PDT 24
Peak memory 183768 kb
Host smart-10be34c7-e886-44e5-9297-3cd00a18dc9f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401408163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3401408163
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2355215028
Short name T79
Test name
Test status
Simulation time 1234626132 ps
CPU time 1.24 seconds
Started Jul 02 09:49:46 AM PDT 24
Finished Jul 02 09:49:51 AM PDT 24
Peak memory 193040 kb
Host smart-803d1d8a-30b2-4c1b-bb87-26c2b95db5bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355215028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2355215028
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1379376944
Short name T416
Test name
Test status
Simulation time 858954406 ps
CPU time 2.13 seconds
Started Jul 02 09:49:28 AM PDT 24
Finished Jul 02 09:49:34 AM PDT 24
Peak memory 198652 kb
Host smart-dbbe1ca5-f9da-4edd-b193-f992a6ede702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379376944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1379376944
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3716409363
Short name T373
Test name
Test status
Simulation time 4066957225 ps
CPU time 7.03 seconds
Started Jul 02 09:49:29 AM PDT 24
Finished Jul 02 09:49:41 AM PDT 24
Peak memory 196748 kb
Host smart-cfd9eeec-2277-4bff-8ad8-ba3fc2e6ca97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716409363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3716409363
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.924665839
Short name T54
Test name
Test status
Simulation time 506123561 ps
CPU time 1.17 seconds
Started Jul 02 09:49:58 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 183788 kb
Host smart-619465ed-f9d2-49aa-b444-f0674925ee42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924665839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.924665839
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2859522126
Short name T69
Test name
Test status
Simulation time 13467579877 ps
CPU time 22.59 seconds
Started Jul 02 09:49:35 AM PDT 24
Finished Jul 02 09:50:02 AM PDT 24
Peak memory 196356 kb
Host smart-df828c07-15f1-4e64-bee8-245c9f2bf70e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859522126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2859522126
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3964712004
Short name T325
Test name
Test status
Simulation time 977229718 ps
CPU time 1.87 seconds
Started Jul 02 09:49:27 AM PDT 24
Finished Jul 02 09:49:33 AM PDT 24
Peak memory 193036 kb
Host smart-bf0e5fca-f53b-4d6e-bddd-133cf32de194
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964712004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3964712004
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1282344314
Short name T294
Test name
Test status
Simulation time 581996772 ps
CPU time 1.09 seconds
Started Jul 02 09:49:26 AM PDT 24
Finished Jul 02 09:49:31 AM PDT 24
Peak memory 198344 kb
Host smart-fe64ac47-5778-4947-915f-dfc61824bf9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282344314 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1282344314
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2785071043
Short name T57
Test name
Test status
Simulation time 432889505 ps
CPU time 1.13 seconds
Started Jul 02 09:49:34 AM PDT 24
Finished Jul 02 09:49:39 AM PDT 24
Peak memory 193044 kb
Host smart-4e3f9dc3-0794-4533-bade-3aa25776069e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785071043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2785071043
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1098358757
Short name T321
Test name
Test status
Simulation time 384101631 ps
CPU time 0.77 seconds
Started Jul 02 09:49:26 AM PDT 24
Finished Jul 02 09:49:30 AM PDT 24
Peak memory 183792 kb
Host smart-9a0d2fdd-14f4-4f4f-a8f0-0d49fea00e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098358757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1098358757
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.4054572195
Short name T409
Test name
Test status
Simulation time 353382574 ps
CPU time 1.02 seconds
Started Jul 02 09:49:52 AM PDT 24
Finished Jul 02 09:50:01 AM PDT 24
Peak memory 183696 kb
Host smart-7e77f1d1-870d-409d-bf01-d2c9b64654a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054572195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.4054572195
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.926561243
Short name T292
Test name
Test status
Simulation time 314032993 ps
CPU time 0.63 seconds
Started Jul 02 09:49:45 AM PDT 24
Finished Jul 02 09:49:49 AM PDT 24
Peak memory 183704 kb
Host smart-f18e9e10-3340-4d89-ad3b-0c823de8c992
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926561243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.926561243
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2025385992
Short name T82
Test name
Test status
Simulation time 2505798674 ps
CPU time 4.06 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:04 AM PDT 24
Peak memory 195532 kb
Host smart-bb0e5b6a-e319-4adb-8a78-44b1c237351c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025385992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2025385992
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2612332721
Short name T395
Test name
Test status
Simulation time 321047072 ps
CPU time 2.29 seconds
Started Jul 02 09:49:47 AM PDT 24
Finished Jul 02 09:49:53 AM PDT 24
Peak memory 198628 kb
Host smart-39ed5df9-0138-4a79-844b-4de445637d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612332721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2612332721
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2305042060
Short name T366
Test name
Test status
Simulation time 4669599218 ps
CPU time 1.92 seconds
Started Jul 02 09:49:24 AM PDT 24
Finished Jul 02 09:49:30 AM PDT 24
Peak memory 196664 kb
Host smart-b15c1dae-2ff0-4958-9c1c-feacf7a470b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305042060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2305042060
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3119377783
Short name T206
Test name
Test status
Simulation time 579483452 ps
CPU time 1.4 seconds
Started Jul 02 09:49:48 AM PDT 24
Finished Jul 02 09:49:54 AM PDT 24
Peak memory 196524 kb
Host smart-56de6003-dd6d-4c25-94c1-112bde8e3f4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119377783 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3119377783
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2512475203
Short name T372
Test name
Test status
Simulation time 410737529 ps
CPU time 1.24 seconds
Started Jul 02 09:49:50 AM PDT 24
Finished Jul 02 09:49:57 AM PDT 24
Peak memory 193184 kb
Host smart-dd3f7451-136a-4f53-9636-ad4b3d637a6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512475203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2512475203
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1894084772
Short name T363
Test name
Test status
Simulation time 387503493 ps
CPU time 0.74 seconds
Started Jul 02 09:49:46 AM PDT 24
Finished Jul 02 09:49:50 AM PDT 24
Peak memory 192968 kb
Host smart-729300c0-f764-4854-879b-180e78aba3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894084772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1894084772
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1344539757
Short name T75
Test name
Test status
Simulation time 1615325747 ps
CPU time 1.23 seconds
Started Jul 02 09:49:52 AM PDT 24
Finished Jul 02 09:50:00 AM PDT 24
Peak memory 193336 kb
Host smart-3b752389-96dc-4187-bb15-ad695c416fee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344539757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1344539757
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3682941223
Short name T364
Test name
Test status
Simulation time 680716057 ps
CPU time 1.85 seconds
Started Jul 02 09:49:57 AM PDT 24
Finished Jul 02 09:50:07 AM PDT 24
Peak memory 198652 kb
Host smart-75a79eac-fff9-47a5-86e3-23243b6eea23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682941223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3682941223
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1675309636
Short name T300
Test name
Test status
Simulation time 455865032 ps
CPU time 0.98 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:01 AM PDT 24
Peak memory 197772 kb
Host smart-77c1f674-6763-4cc4-9538-32dd4b299624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675309636 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1675309636
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3042684567
Short name T411
Test name
Test status
Simulation time 346890118 ps
CPU time 0.68 seconds
Started Jul 02 09:49:51 AM PDT 24
Finished Jul 02 09:49:59 AM PDT 24
Peak memory 193012 kb
Host smart-24040c0f-6a21-49ea-b11a-dcd03e7ab457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042684567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3042684567
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1069841918
Short name T306
Test name
Test status
Simulation time 315397266 ps
CPU time 1.07 seconds
Started Jul 02 09:49:31 AM PDT 24
Finished Jul 02 09:49:36 AM PDT 24
Peak memory 183784 kb
Host smart-c01eb1e4-8fb0-4678-ae71-9afbe7b85f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069841918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1069841918
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1056965208
Short name T80
Test name
Test status
Simulation time 1281815116 ps
CPU time 1.33 seconds
Started Jul 02 09:49:31 AM PDT 24
Finished Jul 02 09:49:37 AM PDT 24
Peak memory 193784 kb
Host smart-4a575e41-9a31-4e05-bb96-f0bc8d87c047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056965208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1056965208
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1652809647
Short name T420
Test name
Test status
Simulation time 458143504 ps
CPU time 2.65 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 198716 kb
Host smart-f0cf40fe-c234-4881-9168-9c5aa90e45f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652809647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1652809647
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.237687588
Short name T358
Test name
Test status
Simulation time 4285867920 ps
CPU time 2.29 seconds
Started Jul 02 09:49:50 AM PDT 24
Finished Jul 02 09:49:58 AM PDT 24
Peak memory 197856 kb
Host smart-8c62c120-a694-4ac0-aaed-f4274360f312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237687588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.237687588
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2076816071
Short name T406
Test name
Test status
Simulation time 474134160 ps
CPU time 1.35 seconds
Started Jul 02 09:49:49 AM PDT 24
Finished Jul 02 09:49:55 AM PDT 24
Peak memory 198644 kb
Host smart-af97841f-7db6-440d-bc54-854a89de12bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076816071 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2076816071
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3296595558
Short name T415
Test name
Test status
Simulation time 533760321 ps
CPU time 0.93 seconds
Started Jul 02 09:49:50 AM PDT 24
Finished Jul 02 09:49:57 AM PDT 24
Peak memory 193032 kb
Host smart-c7c6c448-cec3-4404-b6a8-659443a37c80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296595558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3296595558
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2657233976
Short name T317
Test name
Test status
Simulation time 343073726 ps
CPU time 0.65 seconds
Started Jul 02 09:49:45 AM PDT 24
Finished Jul 02 09:49:49 AM PDT 24
Peak memory 183784 kb
Host smart-63f3e32f-a90c-4ffd-98c5-b83c909617dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657233976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2657233976
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3495306488
Short name T334
Test name
Test status
Simulation time 1266981353 ps
CPU time 2.76 seconds
Started Jul 02 09:49:38 AM PDT 24
Finished Jul 02 09:49:44 AM PDT 24
Peak memory 193048 kb
Host smart-01d33839-2207-4387-a231-4a3410a54a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495306488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3495306488
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.538726538
Short name T385
Test name
Test status
Simulation time 347830797 ps
CPU time 1.7 seconds
Started Jul 02 09:49:38 AM PDT 24
Finished Jul 02 09:49:43 AM PDT 24
Peak memory 198620 kb
Host smart-0039a646-afa3-4409-b183-8404e91f2b79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538726538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.538726538
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1825733770
Short name T195
Test name
Test status
Simulation time 7997725638 ps
CPU time 4.71 seconds
Started Jul 02 09:49:44 AM PDT 24
Finished Jul 02 09:49:52 AM PDT 24
Peak memory 198296 kb
Host smart-560b5f1e-bbac-4665-afa4-dbecf2ae541b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825733770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1825733770
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3735869286
Short name T404
Test name
Test status
Simulation time 447270458 ps
CPU time 0.81 seconds
Started Jul 02 09:49:51 AM PDT 24
Finished Jul 02 09:49:58 AM PDT 24
Peak memory 197136 kb
Host smart-fbe571c5-0266-470e-b434-f8f1db834c1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735869286 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3735869286
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.93834848
Short name T339
Test name
Test status
Simulation time 327619177 ps
CPU time 0.72 seconds
Started Jul 02 09:49:34 AM PDT 24
Finished Jul 02 09:49:39 AM PDT 24
Peak memory 193072 kb
Host smart-c8551af7-5aa1-43d3-b1d8-7cbc1fc11716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93834848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.93834848
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2583174681
Short name T377
Test name
Test status
Simulation time 484144216 ps
CPU time 0.73 seconds
Started Jul 02 09:49:44 AM PDT 24
Finished Jul 02 09:49:48 AM PDT 24
Peak memory 183916 kb
Host smart-660a8cf7-b543-41b7-9639-e10621fcc670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583174681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2583174681
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2679907779
Short name T332
Test name
Test status
Simulation time 2632499320 ps
CPU time 2.21 seconds
Started Jul 02 09:49:33 AM PDT 24
Finished Jul 02 09:49:39 AM PDT 24
Peak memory 195252 kb
Host smart-21c94e92-0bbe-4a08-b235-6db60161505c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679907779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2679907779
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2541164806
Short name T290
Test name
Test status
Simulation time 453269363 ps
CPU time 1.52 seconds
Started Jul 02 09:49:43 AM PDT 24
Finished Jul 02 09:49:47 AM PDT 24
Peak memory 198496 kb
Host smart-54c4c110-e056-4c02-9df3-f01c6cabb26b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541164806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2541164806
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3950723087
Short name T322
Test name
Test status
Simulation time 4369724069 ps
CPU time 2.4 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:10 AM PDT 24
Peak memory 197964 kb
Host smart-7b4e3835-8359-47b6-b5af-d6fe886a6723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950723087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3950723087
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3997545387
Short name T305
Test name
Test status
Simulation time 530763214 ps
CPU time 1.48 seconds
Started Jul 02 09:50:04 AM PDT 24
Finished Jul 02 09:50:13 AM PDT 24
Peak memory 196804 kb
Host smart-71346e7c-ffeb-4962-a4ce-7301cb7f2d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997545387 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3997545387
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1130151764
Short name T74
Test name
Test status
Simulation time 338086070 ps
CPU time 1.06 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:09 AM PDT 24
Peak memory 192068 kb
Host smart-ea7abcd8-6055-47d7-8e69-fc847d7c7009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130151764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1130151764
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1172708211
Short name T286
Test name
Test status
Simulation time 481024873 ps
CPU time 1.3 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:09 AM PDT 24
Peak memory 183740 kb
Host smart-3cebdfb7-3cc0-422b-bb49-dfe93fb03ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172708211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1172708211
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2380755046
Short name T367
Test name
Test status
Simulation time 1279674326 ps
CPU time 3.4 seconds
Started Jul 02 09:50:04 AM PDT 24
Finished Jul 02 09:50:15 AM PDT 24
Peak memory 193608 kb
Host smart-6e42aff2-f336-4dd2-9cac-1a52d86dec6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380755046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2380755046
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3516446085
Short name T340
Test name
Test status
Simulation time 646105745 ps
CPU time 1.3 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 198588 kb
Host smart-21c169bb-7a3f-4ed1-897e-5043288716a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516446085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3516446085
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1114923316
Short name T326
Test name
Test status
Simulation time 567447967 ps
CPU time 1.5 seconds
Started Jul 02 09:49:57 AM PDT 24
Finished Jul 02 09:50:07 AM PDT 24
Peak memory 196504 kb
Host smart-3975ad44-45f0-4507-a4fe-8bd45deb2e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114923316 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1114923316
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2546425163
Short name T52
Test name
Test status
Simulation time 339134592 ps
CPU time 0.7 seconds
Started Jul 02 09:49:56 AM PDT 24
Finished Jul 02 09:50:05 AM PDT 24
Peak memory 194036 kb
Host smart-9c5296e8-089e-4508-abc3-5ee23d93de16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546425163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2546425163
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1327367233
Short name T333
Test name
Test status
Simulation time 391768388 ps
CPU time 1.07 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:09 AM PDT 24
Peak memory 192956 kb
Host smart-95fda82e-5761-44c2-bec4-66b027ab0d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327367233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1327367233
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2423801070
Short name T392
Test name
Test status
Simulation time 2780127356 ps
CPU time 3.08 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 195120 kb
Host smart-7257b41f-6282-491b-912e-dc413a2cec71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423801070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2423801070
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2738425531
Short name T421
Test name
Test status
Simulation time 525792896 ps
CPU time 2.16 seconds
Started Jul 02 09:50:03 AM PDT 24
Finished Jul 02 09:50:13 AM PDT 24
Peak memory 198656 kb
Host smart-5c19bafa-cb4b-4d94-831c-5f4cff3aaf17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738425531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2738425531
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3066375602
Short name T307
Test name
Test status
Simulation time 4243043571 ps
CPU time 7.02 seconds
Started Jul 02 09:49:56 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 197900 kb
Host smart-2be6ceb8-525d-495d-8c38-5d0d1f8ff9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066375602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3066375602
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1890149728
Short name T357
Test name
Test status
Simulation time 648431668 ps
CPU time 0.78 seconds
Started Jul 02 09:49:55 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 196120 kb
Host smart-131d93ef-9acb-4c60-baa1-fb7dc7182854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890149728 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1890149728
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2335415476
Short name T365
Test name
Test status
Simulation time 454395887 ps
CPU time 1.22 seconds
Started Jul 02 09:50:15 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 193300 kb
Host smart-e344f21c-c6a1-498f-a556-6e49848b1dff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335415476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2335415476
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.660954462
Short name T295
Test name
Test status
Simulation time 298133865 ps
CPU time 0.76 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:02 AM PDT 24
Peak memory 192976 kb
Host smart-c60443d4-ee97-4621-bc31-ee2c654d0d75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660954462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.660954462
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3834078046
Short name T77
Test name
Test status
Simulation time 2689417250 ps
CPU time 5.6 seconds
Started Jul 02 09:49:51 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 194768 kb
Host smart-85fc2404-0037-4341-a06c-f85898f86269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834078046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3834078046
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1270546464
Short name T389
Test name
Test status
Simulation time 414853333 ps
CPU time 1.74 seconds
Started Jul 02 09:49:56 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 198692 kb
Host smart-7dd8c4ca-2727-4bfa-b5d2-3b83734f85ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270546464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1270546464
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.657278808
Short name T407
Test name
Test status
Simulation time 8296067120 ps
CPU time 3.34 seconds
Started Jul 02 09:49:43 AM PDT 24
Finished Jul 02 09:49:49 AM PDT 24
Peak memory 198108 kb
Host smart-b10bb6e9-9a17-41f8-aebb-5e89d6f5f701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657278808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.657278808
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1886777525
Short name T362
Test name
Test status
Simulation time 451553553 ps
CPU time 1.28 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:14 AM PDT 24
Peak memory 197176 kb
Host smart-15b62412-eba8-4fe8-ac35-b04ccf90be2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886777525 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1886777525
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2179847706
Short name T78
Test name
Test status
Simulation time 494668213 ps
CPU time 0.98 seconds
Started Jul 02 09:49:48 AM PDT 24
Finished Jul 02 09:49:54 AM PDT 24
Peak memory 192100 kb
Host smart-c22d4899-347f-4792-aa88-791d299d10c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179847706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2179847706
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2768239513
Short name T342
Test name
Test status
Simulation time 320504066 ps
CPU time 0.94 seconds
Started Jul 02 09:50:00 AM PDT 24
Finished Jul 02 09:50:09 AM PDT 24
Peak memory 183772 kb
Host smart-98adac1c-4df6-438b-a26e-11ab6623679f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768239513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2768239513
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3534525614
Short name T76
Test name
Test status
Simulation time 2973330683 ps
CPU time 2.62 seconds
Started Jul 02 09:50:12 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 194024 kb
Host smart-075af938-0df1-458b-9eb3-b4bc2514ae8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534525614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3534525614
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1404366863
Short name T341
Test name
Test status
Simulation time 552946939 ps
CPU time 1.92 seconds
Started Jul 02 09:49:50 AM PDT 24
Finished Jul 02 09:49:58 AM PDT 24
Peak memory 198648 kb
Host smart-fb9a6629-7ae4-4043-87b1-a4422900cd3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404366863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1404366863
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4117502231
Short name T28
Test name
Test status
Simulation time 4801976763 ps
CPU time 7.12 seconds
Started Jul 02 09:49:52 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 198108 kb
Host smart-4488af15-3e10-4c1a-84ea-913a8e122968
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117502231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.4117502231
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1145275810
Short name T289
Test name
Test status
Simulation time 568098666 ps
CPU time 0.86 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:14 AM PDT 24
Peak memory 196208 kb
Host smart-f8210aef-cd20-40ca-9c6d-6147826391f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145275810 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1145275810
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.158919187
Short name T331
Test name
Test status
Simulation time 446807648 ps
CPU time 0.9 seconds
Started Jul 02 09:49:52 AM PDT 24
Finished Jul 02 09:50:00 AM PDT 24
Peak memory 192984 kb
Host smart-a590a8ad-dd5a-4cd7-950c-2fff46f469e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158919187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.158919187
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.681906548
Short name T388
Test name
Test status
Simulation time 2723636895 ps
CPU time 4.32 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:05 AM PDT 24
Peak memory 194304 kb
Host smart-7d55ce0d-10c6-4d1d-97d4-ea8275b18838
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681906548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.681906548
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.549174142
Short name T304
Test name
Test status
Simulation time 499109511 ps
CPU time 2.47 seconds
Started Jul 02 09:49:51 AM PDT 24
Finished Jul 02 09:50:00 AM PDT 24
Peak memory 198232 kb
Host smart-999c87ea-d139-4592-9b43-c498086589ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549174142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.549174142
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3213626902
Short name T197
Test name
Test status
Simulation time 8042027348 ps
CPU time 6.55 seconds
Started Jul 02 09:49:50 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 198328 kb
Host smart-8ae3cb07-6e7a-40c5-8dc4-11ecdd44d31c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213626902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3213626902
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.779826756
Short name T410
Test name
Test status
Simulation time 502259288 ps
CPU time 1.37 seconds
Started Jul 02 09:49:44 AM PDT 24
Finished Jul 02 09:49:49 AM PDT 24
Peak memory 196080 kb
Host smart-b476860d-413e-4547-95fb-fe38bbbaeaa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779826756 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.779826756
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3211370790
Short name T24
Test name
Test status
Simulation time 390803172 ps
CPU time 0.68 seconds
Started Jul 02 09:50:12 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 192172 kb
Host smart-165144bf-2e43-4f01-b998-2d171d5bb69d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211370790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3211370790
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.306735952
Short name T393
Test name
Test status
Simulation time 280443644 ps
CPU time 0.88 seconds
Started Jul 02 09:50:06 AM PDT 24
Finished Jul 02 09:50:15 AM PDT 24
Peak memory 192964 kb
Host smart-38fb6382-0f0b-42c4-89c9-3cace47a60c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306735952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.306735952
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.384620076
Short name T397
Test name
Test status
Simulation time 1115703500 ps
CPU time 1.43 seconds
Started Jul 02 09:49:54 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 194076 kb
Host smart-38232922-4f5d-4989-b712-48300de4da78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384620076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.384620076
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3328047098
Short name T376
Test name
Test status
Simulation time 381001758 ps
CPU time 1.53 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 198476 kb
Host smart-5e92e2c9-373c-4775-8685-04729a842e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328047098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3328047098
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3193816230
Short name T394
Test name
Test status
Simulation time 4654408056 ps
CPU time 1.51 seconds
Started Jul 02 09:50:13 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 196496 kb
Host smart-6f3f5708-1d44-46be-8a7f-e47b55df6d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193816230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3193816230
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1067628720
Short name T73
Test name
Test status
Simulation time 653391879 ps
CPU time 0.99 seconds
Started Jul 02 09:49:26 AM PDT 24
Finished Jul 02 09:49:32 AM PDT 24
Peak memory 192028 kb
Host smart-41c427a6-945a-4400-863c-e7c1d1077659
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067628720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1067628720
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2024881034
Short name T381
Test name
Test status
Simulation time 7003057596 ps
CPU time 15.37 seconds
Started Jul 02 09:49:30 AM PDT 24
Finished Jul 02 09:49:50 AM PDT 24
Peak memory 192232 kb
Host smart-b84ea13e-4c60-4997-a5fd-4694424b64ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024881034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2024881034
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3384990815
Short name T375
Test name
Test status
Simulation time 1036142812 ps
CPU time 1.3 seconds
Started Jul 02 09:49:38 AM PDT 24
Finished Jul 02 09:49:42 AM PDT 24
Peak memory 192992 kb
Host smart-f07c3c1a-1846-42ae-864c-a8bea592edd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384990815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3384990815
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.619066338
Short name T402
Test name
Test status
Simulation time 523193562 ps
CPU time 1.07 seconds
Started Jul 02 09:49:50 AM PDT 24
Finished Jul 02 09:49:57 AM PDT 24
Peak memory 196720 kb
Host smart-d6e2152d-d266-4988-b05d-045ce00afca5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619066338 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.619066338
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1057160979
Short name T361
Test name
Test status
Simulation time 468390547 ps
CPU time 0.93 seconds
Started Jul 02 09:49:51 AM PDT 24
Finished Jul 02 09:49:59 AM PDT 24
Peak memory 193304 kb
Host smart-61b8998a-d46d-478b-9bd4-fbaa55538990
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057160979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1057160979
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.165275810
Short name T408
Test name
Test status
Simulation time 505265619 ps
CPU time 0.69 seconds
Started Jul 02 09:49:45 AM PDT 24
Finished Jul 02 09:49:49 AM PDT 24
Peak memory 183716 kb
Host smart-9221b37d-17b5-491a-af7d-4f099dc20b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165275810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.165275810
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3932873090
Short name T424
Test name
Test status
Simulation time 426383809 ps
CPU time 1.14 seconds
Started Jul 02 09:49:28 AM PDT 24
Finished Jul 02 09:49:33 AM PDT 24
Peak memory 183824 kb
Host smart-ea1eaf2c-23f8-4f08-a86c-5f9e3b97fd19
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932873090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3932873090
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4284171243
Short name T369
Test name
Test status
Simulation time 323994157 ps
CPU time 0.7 seconds
Started Jul 02 09:49:49 AM PDT 24
Finished Jul 02 09:49:55 AM PDT 24
Peak memory 183752 kb
Host smart-e7dddccf-ad5f-444d-8035-3294e94bdde0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284171243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4284171243
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1009429398
Short name T355
Test name
Test status
Simulation time 2985850974 ps
CPU time 3.17 seconds
Started Jul 02 09:49:24 AM PDT 24
Finished Jul 02 09:49:37 AM PDT 24
Peak memory 194836 kb
Host smart-e5d5ad9e-ed95-4bb2-acc1-9096d5e123ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009429398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1009429398
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3424376235
Short name T399
Test name
Test status
Simulation time 783402915 ps
CPU time 2.27 seconds
Started Jul 02 09:49:31 AM PDT 24
Finished Jul 02 09:49:37 AM PDT 24
Peak memory 198340 kb
Host smart-26a6d9d2-02f7-4bb1-b947-5d2c119250f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424376235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3424376235
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3648257525
Short name T422
Test name
Test status
Simulation time 4640520341 ps
CPU time 2.15 seconds
Started Jul 02 09:50:01 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 197932 kb
Host smart-3a127dff-b834-4020-81e1-61ec1404bdf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648257525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3648257525
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.940145128
Short name T327
Test name
Test status
Simulation time 510715902 ps
CPU time 0.72 seconds
Started Jul 02 09:49:52 AM PDT 24
Finished Jul 02 09:50:00 AM PDT 24
Peak memory 183776 kb
Host smart-6cb6fdb3-362a-4930-ae5d-6b36b79f7d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940145128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.940145128
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1068900667
Short name T337
Test name
Test status
Simulation time 512655335 ps
CPU time 0.92 seconds
Started Jul 02 09:50:03 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 192988 kb
Host smart-55b26995-cec0-4c0d-8beb-fc1e42fb386b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068900667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1068900667
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3570469485
Short name T425
Test name
Test status
Simulation time 371619968 ps
CPU time 0.69 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:13 AM PDT 24
Peak memory 183780 kb
Host smart-be337313-fec3-4681-92b2-207e4a8fd101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570469485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3570469485
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1461155867
Short name T396
Test name
Test status
Simulation time 515350784 ps
CPU time 0.74 seconds
Started Jul 02 09:49:55 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 192932 kb
Host smart-f5267078-767e-42b5-9453-1c57e73aa874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461155867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1461155867
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2261455360
Short name T359
Test name
Test status
Simulation time 505793803 ps
CPU time 0.75 seconds
Started Jul 02 09:50:13 AM PDT 24
Finished Jul 02 09:50:22 AM PDT 24
Peak memory 193000 kb
Host smart-98ff2ca6-6581-4230-b3e8-653e9ae41eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261455360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2261455360
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2124377594
Short name T293
Test name
Test status
Simulation time 482350059 ps
CPU time 1.26 seconds
Started Jul 02 09:49:59 AM PDT 24
Finished Jul 02 09:50:08 AM PDT 24
Peak memory 183772 kb
Host smart-f2658b65-ca6b-465d-87c2-67621e27f303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124377594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2124377594
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3616191596
Short name T401
Test name
Test status
Simulation time 293245325 ps
CPU time 0.96 seconds
Started Jul 02 09:49:57 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 183752 kb
Host smart-20d52efd-0213-4ca6-aa60-5dc60ed6c0f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616191596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3616191596
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1874495766
Short name T344
Test name
Test status
Simulation time 299585036 ps
CPU time 0.68 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:13 AM PDT 24
Peak memory 183744 kb
Host smart-131d88c7-a398-4a36-b458-45fcfd69fd0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874495766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1874495766
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2455598849
Short name T348
Test name
Test status
Simulation time 400167039 ps
CPU time 1.02 seconds
Started Jul 02 09:49:54 AM PDT 24
Finished Jul 02 09:50:02 AM PDT 24
Peak memory 183760 kb
Host smart-93222397-89ce-4823-8737-26758c55336e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455598849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2455598849
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3989866029
Short name T287
Test name
Test status
Simulation time 423520167 ps
CPU time 0.62 seconds
Started Jul 02 09:49:50 AM PDT 24
Finished Jul 02 09:49:57 AM PDT 24
Peak memory 183744 kb
Host smart-d08fe6d9-f0d0-4648-87ff-72d38b609f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989866029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3989866029
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3478001647
Short name T50
Test name
Test status
Simulation time 519786325 ps
CPU time 1.24 seconds
Started Jul 02 09:49:28 AM PDT 24
Finished Jul 02 09:49:34 AM PDT 24
Peak memory 195132 kb
Host smart-4f8a13f7-3ac0-4054-b15a-32849df72161
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478001647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3478001647
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.735398857
Short name T70
Test name
Test status
Simulation time 5188783915 ps
CPU time 11.19 seconds
Started Jul 02 09:49:27 AM PDT 24
Finished Jul 02 09:49:42 AM PDT 24
Peak memory 192248 kb
Host smart-2a860e30-87ad-4e5b-a73b-d0ca98b78f6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735398857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.735398857
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4175837700
Short name T72
Test name
Test status
Simulation time 1402384692 ps
CPU time 1.08 seconds
Started Jul 02 09:50:01 AM PDT 24
Finished Jul 02 09:50:10 AM PDT 24
Peak memory 193268 kb
Host smart-04669795-a43c-4e0a-b3cc-68c7d203b217
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175837700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4175837700
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1026990602
Short name T296
Test name
Test status
Simulation time 930559776 ps
CPU time 1.55 seconds
Started Jul 02 09:50:08 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 198700 kb
Host smart-1798300f-e916-498d-aa93-5ef45589b559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026990602 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1026990602
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.319423880
Short name T335
Test name
Test status
Simulation time 386942546 ps
CPU time 0.72 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 194076 kb
Host smart-7a95ab12-131b-4cff-89e4-9cb2b418a501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319423880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.319423880
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1380188258
Short name T301
Test name
Test status
Simulation time 404471413 ps
CPU time 1.08 seconds
Started Jul 02 09:49:29 AM PDT 24
Finished Jul 02 09:49:34 AM PDT 24
Peak memory 183768 kb
Host smart-c69ab3e9-ffe0-4e3d-aa3a-153006775e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380188258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1380188258
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.853025563
Short name T423
Test name
Test status
Simulation time 338871503 ps
CPU time 0.93 seconds
Started Jul 02 09:49:44 AM PDT 24
Finished Jul 02 09:49:48 AM PDT 24
Peak memory 183692 kb
Host smart-676e34c4-a91c-451c-bf93-f26f0302eb51
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853025563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.853025563
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1849318332
Short name T356
Test name
Test status
Simulation time 317608942 ps
CPU time 0.72 seconds
Started Jul 02 09:49:30 AM PDT 24
Finished Jul 02 09:49:36 AM PDT 24
Peak memory 183736 kb
Host smart-21851236-8905-4048-8cc6-ad9496c1a8f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849318332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1849318332
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.487015743
Short name T380
Test name
Test status
Simulation time 2481485130 ps
CPU time 4.36 seconds
Started Jul 02 09:50:23 AM PDT 24
Finished Jul 02 09:50:35 AM PDT 24
Peak memory 195140 kb
Host smart-92ce494a-f026-47ff-b487-c1472ceed510
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487015743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.487015743
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4046424804
Short name T418
Test name
Test status
Simulation time 600534320 ps
CPU time 2.59 seconds
Started Jul 02 09:49:31 AM PDT 24
Finished Jul 02 09:49:39 AM PDT 24
Peak memory 198640 kb
Host smart-477be048-e2e2-4f66-83a7-ad844d870b00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046424804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4046424804
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1088943955
Short name T412
Test name
Test status
Simulation time 8683177407 ps
CPU time 11.17 seconds
Started Jul 02 09:49:31 AM PDT 24
Finished Jul 02 09:49:46 AM PDT 24
Peak memory 197872 kb
Host smart-46a73db0-c2f6-4381-844f-e35a0a967d85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088943955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1088943955
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1153213755
Short name T379
Test name
Test status
Simulation time 399375485 ps
CPU time 0.61 seconds
Started Jul 02 09:49:58 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 183780 kb
Host smart-9abc04ee-e01a-4a4b-a4b9-040c6cf73e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153213755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1153213755
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1312520333
Short name T343
Test name
Test status
Simulation time 396546144 ps
CPU time 0.79 seconds
Started Jul 02 09:49:55 AM PDT 24
Finished Jul 02 09:50:04 AM PDT 24
Peak memory 183772 kb
Host smart-ccc743e6-d2f2-4662-ac8a-a01861624ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312520333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1312520333
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2076954010
Short name T336
Test name
Test status
Simulation time 424469692 ps
CPU time 1.16 seconds
Started Jul 02 09:50:07 AM PDT 24
Finished Jul 02 09:50:16 AM PDT 24
Peak memory 183744 kb
Host smart-edd54cf6-aeea-4f76-bd01-9842c0f27994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076954010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2076954010
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2368897778
Short name T298
Test name
Test status
Simulation time 401035858 ps
CPU time 1.01 seconds
Started Jul 02 09:49:51 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 183340 kb
Host smart-be7b7fa9-9827-4b63-b4f9-37680f9945d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368897778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2368897778
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1778589848
Short name T398
Test name
Test status
Simulation time 329608823 ps
CPU time 1.01 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 183760 kb
Host smart-02a11bea-baf2-455d-b1b1-a6d70d28d987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778589848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1778589848
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1968629313
Short name T318
Test name
Test status
Simulation time 382339166 ps
CPU time 0.61 seconds
Started Jul 02 09:50:03 AM PDT 24
Finished Jul 02 09:50:11 AM PDT 24
Peak memory 192984 kb
Host smart-de3c65ee-c956-4af9-916d-e745e2153c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968629313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1968629313
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2706509938
Short name T346
Test name
Test status
Simulation time 409481301 ps
CPU time 0.85 seconds
Started Jul 02 09:49:42 AM PDT 24
Finished Jul 02 09:49:46 AM PDT 24
Peak memory 192960 kb
Host smart-d0a5c3a6-fe15-4ac5-b661-aec30ac69426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706509938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2706509938
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1578736140
Short name T417
Test name
Test status
Simulation time 508768274 ps
CPU time 1.26 seconds
Started Jul 02 09:49:56 AM PDT 24
Finished Jul 02 09:50:05 AM PDT 24
Peak memory 183788 kb
Host smart-edc1af68-d1c2-431c-87da-72488b61e86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578736140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1578736140
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3728216104
Short name T328
Test name
Test status
Simulation time 340673644 ps
CPU time 0.78 seconds
Started Jul 02 09:50:02 AM PDT 24
Finished Jul 02 09:50:10 AM PDT 24
Peak memory 192996 kb
Host smart-fa6cb93d-4c45-4a5c-ba32-3a49848b0648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728216104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3728216104
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2954970602
Short name T299
Test name
Test status
Simulation time 452764283 ps
CPU time 0.71 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:14 AM PDT 24
Peak memory 192988 kb
Host smart-5a20567c-0ca7-4a73-97ed-e797368d5b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954970602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2954970602
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1687224999
Short name T400
Test name
Test status
Simulation time 500264605 ps
CPU time 1.36 seconds
Started Jul 02 09:49:40 AM PDT 24
Finished Jul 02 09:49:44 AM PDT 24
Peak memory 194352 kb
Host smart-d6ed6ed1-8666-46c0-827c-24f919a4424e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687224999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1687224999
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1251979778
Short name T56
Test name
Test status
Simulation time 7800125989 ps
CPU time 4.46 seconds
Started Jul 02 09:49:58 AM PDT 24
Finished Jul 02 09:50:10 AM PDT 24
Peak memory 196696 kb
Host smart-1d477ce3-138b-421a-ae05-4853de514ec2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251979778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1251979778
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.209374681
Short name T25
Test name
Test status
Simulation time 1233455826 ps
CPU time 1.45 seconds
Started Jul 02 09:49:30 AM PDT 24
Finished Jul 02 09:49:36 AM PDT 24
Peak memory 193168 kb
Host smart-5e9b9cf1-04c3-470f-9ebf-5f9baec528f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209374681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.209374681
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.455281429
Short name T370
Test name
Test status
Simulation time 450822120 ps
CPU time 1.22 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 195548 kb
Host smart-73251c11-8e41-40bb-881f-db34604c78b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455281429 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.455281429
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3056914237
Short name T390
Test name
Test status
Simulation time 335909165 ps
CPU time 0.7 seconds
Started Jul 02 09:49:25 AM PDT 24
Finished Jul 02 09:49:30 AM PDT 24
Peak memory 193036 kb
Host smart-3dddea01-71ae-4f20-9577-2649d735ac7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056914237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3056914237
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2373973005
Short name T351
Test name
Test status
Simulation time 293339589 ps
CPU time 0.96 seconds
Started Jul 02 09:49:29 AM PDT 24
Finished Jul 02 09:49:35 AM PDT 24
Peak memory 192944 kb
Host smart-4c00da1f-409b-486a-8f68-a4babde69880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373973005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2373973005
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2551081885
Short name T414
Test name
Test status
Simulation time 545685359 ps
CPU time 0.57 seconds
Started Jul 02 09:49:36 AM PDT 24
Finished Jul 02 09:49:41 AM PDT 24
Peak memory 183696 kb
Host smart-c006b941-3db9-4e7e-8d27-9f425d031473
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551081885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2551081885
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3407947008
Short name T314
Test name
Test status
Simulation time 359106231 ps
CPU time 0.99 seconds
Started Jul 02 09:49:31 AM PDT 24
Finished Jul 02 09:49:41 AM PDT 24
Peak memory 183756 kb
Host smart-5c409e76-62d8-4cc6-8e6c-915381852748
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407947008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3407947008
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.244447194
Short name T419
Test name
Test status
Simulation time 1701911682 ps
CPU time 2.67 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:15 AM PDT 24
Peak memory 194972 kb
Host smart-239c3f86-19bf-4a8b-b75e-55de2a166fb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244447194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.244447194
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.520444336
Short name T313
Test name
Test status
Simulation time 560532247 ps
CPU time 2.32 seconds
Started Jul 02 09:49:56 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 198656 kb
Host smart-a6dcdf9c-5336-4c88-8379-c39d14a070e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520444336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.520444336
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.710763835
Short name T383
Test name
Test status
Simulation time 4109591681 ps
CPU time 5.84 seconds
Started Jul 02 09:49:40 AM PDT 24
Finished Jul 02 09:49:54 AM PDT 24
Peak memory 198060 kb
Host smart-4cccb7ba-08f8-4ae3-9e81-5dd2b1f0f012
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710763835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.710763835
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3766038407
Short name T316
Test name
Test status
Simulation time 414196091 ps
CPU time 1.14 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 183720 kb
Host smart-3c20e6d7-6015-45d0-9cf3-27307608d219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766038407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3766038407
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.756339587
Short name T338
Test name
Test status
Simulation time 511683258 ps
CPU time 1.31 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:02 AM PDT 24
Peak memory 183744 kb
Host smart-d7e902b5-8ca5-440f-ad17-8245075f34ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756339587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.756339587
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2627350429
Short name T391
Test name
Test status
Simulation time 493801736 ps
CPU time 0.58 seconds
Started Jul 02 09:50:02 AM PDT 24
Finished Jul 02 09:50:10 AM PDT 24
Peak memory 183764 kb
Host smart-6a604b70-a6d4-4bd4-a517-3ca71308c772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627350429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2627350429
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1861841032
Short name T288
Test name
Test status
Simulation time 462015887 ps
CPU time 0.88 seconds
Started Jul 02 09:49:53 AM PDT 24
Finished Jul 02 09:50:01 AM PDT 24
Peak memory 183772 kb
Host smart-3c04675f-0627-4fd0-a010-627a0723f7cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861841032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1861841032
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4021629855
Short name T320
Test name
Test status
Simulation time 528378336 ps
CPU time 0.75 seconds
Started Jul 02 09:49:54 AM PDT 24
Finished Jul 02 09:50:02 AM PDT 24
Peak memory 183780 kb
Host smart-a5ebb635-2e6b-4cd3-9dfb-20cb8c47101b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021629855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4021629855
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.4064099371
Short name T315
Test name
Test status
Simulation time 477387834 ps
CPU time 1.21 seconds
Started Jul 02 09:49:58 AM PDT 24
Finished Jul 02 09:50:07 AM PDT 24
Peak memory 183728 kb
Host smart-986c8c92-b157-4f8e-8281-d9f8880f9113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064099371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.4064099371
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2283716283
Short name T349
Test name
Test status
Simulation time 566195049 ps
CPU time 0.61 seconds
Started Jul 02 09:49:48 AM PDT 24
Finished Jul 02 09:49:53 AM PDT 24
Peak memory 183768 kb
Host smart-7a2cfcb2-e83f-4a66-847e-37519d672e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283716283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2283716283
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3314908338
Short name T330
Test name
Test status
Simulation time 350434292 ps
CPU time 1.06 seconds
Started Jul 02 09:49:55 AM PDT 24
Finished Jul 02 09:50:03 AM PDT 24
Peak memory 183780 kb
Host smart-755c013c-a3ee-4d6d-b016-80062d070ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314908338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3314908338
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.28585280
Short name T350
Test name
Test status
Simulation time 296851335 ps
CPU time 0.7 seconds
Started Jul 02 09:49:49 AM PDT 24
Finished Jul 02 09:49:55 AM PDT 24
Peak memory 183784 kb
Host smart-55d0fefc-6dea-4b4c-af23-9ff2de6c8601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28585280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.28585280
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2805159441
Short name T386
Test name
Test status
Simulation time 283417914 ps
CPU time 0.91 seconds
Started Jul 02 09:50:05 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 183768 kb
Host smart-1f162b1e-d2e1-4fd0-9629-6380c01f9fbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805159441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2805159441
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.855284065
Short name T297
Test name
Test status
Simulation time 446453875 ps
CPU time 1.26 seconds
Started Jul 02 09:49:31 AM PDT 24
Finished Jul 02 09:49:36 AM PDT 24
Peak memory 196144 kb
Host smart-e9cda2c6-b049-4849-977b-9e15c47853ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855284065 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.855284065
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4140793391
Short name T71
Test name
Test status
Simulation time 330025550 ps
CPU time 0.7 seconds
Started Jul 02 09:49:31 AM PDT 24
Finished Jul 02 09:49:36 AM PDT 24
Peak memory 193212 kb
Host smart-05f31f27-c3c4-4bf6-b38c-44acead292e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140793391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.4140793391
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.647716389
Short name T403
Test name
Test status
Simulation time 404987439 ps
CPU time 1.22 seconds
Started Jul 02 09:49:39 AM PDT 24
Finished Jul 02 09:49:43 AM PDT 24
Peak memory 192972 kb
Host smart-c901bfbb-c410-4047-bb4b-a168786c13ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647716389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.647716389
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2802817655
Short name T347
Test name
Test status
Simulation time 1080983903 ps
CPU time 2.26 seconds
Started Jul 02 09:49:32 AM PDT 24
Finished Jul 02 09:49:39 AM PDT 24
Peak memory 193720 kb
Host smart-950949bd-09e5-43ec-8989-755fdf93ec9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802817655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2802817655
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.612872382
Short name T308
Test name
Test status
Simulation time 652184059 ps
CPU time 1.24 seconds
Started Jul 02 09:49:28 AM PDT 24
Finished Jul 02 09:49:34 AM PDT 24
Peak memory 198692 kb
Host smart-c4fdfc88-1796-4d9f-9989-b9d7bd5562fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612872382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.612872382
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2106272078
Short name T199
Test name
Test status
Simulation time 7607410436 ps
CPU time 11.54 seconds
Started Jul 02 09:49:28 AM PDT 24
Finished Jul 02 09:49:44 AM PDT 24
Peak memory 198340 kb
Host smart-7bc6089d-97bc-4280-b23a-436048f580d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106272078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2106272078
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3706274453
Short name T352
Test name
Test status
Simulation time 558718177 ps
CPU time 1.14 seconds
Started Jul 02 09:49:30 AM PDT 24
Finished Jul 02 09:49:36 AM PDT 24
Peak memory 196944 kb
Host smart-929d24c0-2eaa-4fd0-9cbf-bb44d3540848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706274453 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3706274453
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1086483183
Short name T329
Test name
Test status
Simulation time 414276933 ps
CPU time 0.69 seconds
Started Jul 02 09:49:23 AM PDT 24
Finished Jul 02 09:49:29 AM PDT 24
Peak memory 192116 kb
Host smart-7a639e7c-6057-4f7e-b7d5-8c99846e1012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086483183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1086483183
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4138902238
Short name T323
Test name
Test status
Simulation time 518971175 ps
CPU time 0.74 seconds
Started Jul 02 09:49:29 AM PDT 24
Finished Jul 02 09:49:35 AM PDT 24
Peak memory 183772 kb
Host smart-fe8244e2-86b5-43f2-b0fe-8a93d62d8c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138902238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.4138902238
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2161631949
Short name T354
Test name
Test status
Simulation time 1155656353 ps
CPU time 1.15 seconds
Started Jul 02 09:50:11 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 193020 kb
Host smart-78876fa2-3b08-4953-a22a-704e75e149b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161631949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2161631949
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1870793937
Short name T360
Test name
Test status
Simulation time 475391965 ps
CPU time 2.09 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 198664 kb
Host smart-78d1c463-33b2-43f5-b780-72a0e1f21be3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870793937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1870793937
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3730460719
Short name T198
Test name
Test status
Simulation time 8397706254 ps
CPU time 7.67 seconds
Started Jul 02 09:50:02 AM PDT 24
Finished Jul 02 09:50:17 AM PDT 24
Peak memory 198304 kb
Host smart-72cca2cb-0621-40db-9ed2-25f09e125a70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730460719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3730460719
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.388516767
Short name T382
Test name
Test status
Simulation time 376158861 ps
CPU time 1 seconds
Started Jul 02 09:49:38 AM PDT 24
Finished Jul 02 09:49:42 AM PDT 24
Peak memory 196332 kb
Host smart-b0005a7f-3330-4021-a89d-2feb160af879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388516767 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.388516767
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1374124351
Short name T55
Test name
Test status
Simulation time 516649619 ps
CPU time 1.25 seconds
Started Jul 02 09:49:35 AM PDT 24
Finished Jul 02 09:49:40 AM PDT 24
Peak memory 193240 kb
Host smart-00c25f29-41e5-48c2-a2df-ead0279d65ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374124351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1374124351
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.750815296
Short name T302
Test name
Test status
Simulation time 395117435 ps
CPU time 1.1 seconds
Started Jul 02 09:49:41 AM PDT 24
Finished Jul 02 09:49:44 AM PDT 24
Peak memory 183712 kb
Host smart-2a8c1c9c-ef53-4958-8dfe-09bbd4c1bcca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750815296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.750815296
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2493230375
Short name T345
Test name
Test status
Simulation time 1377775883 ps
CPU time 2.32 seconds
Started Jul 02 09:50:13 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 194060 kb
Host smart-bdb354fa-4641-4134-b962-5f0f6a60ae06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493230375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2493230375
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1564216536
Short name T324
Test name
Test status
Simulation time 567991740 ps
CPU time 1.33 seconds
Started Jul 02 09:49:28 AM PDT 24
Finished Jul 02 09:49:34 AM PDT 24
Peak memory 198408 kb
Host smart-a3e15c03-67af-4a0d-a637-2e1c4e53f894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564216536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1564216536
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.906756185
Short name T26
Test name
Test status
Simulation time 8340381849 ps
CPU time 4.4 seconds
Started Jul 02 09:50:06 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 198384 kb
Host smart-b2617c60-0b8b-4d92-924f-8434254f8873
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906756185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.906756185
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1354181866
Short name T319
Test name
Test status
Simulation time 456153985 ps
CPU time 1 seconds
Started Jul 02 09:49:43 AM PDT 24
Finished Jul 02 09:49:46 AM PDT 24
Peak memory 196740 kb
Host smart-cffce929-616e-4d56-a40a-247d95d9f4bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354181866 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1354181866
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3729170398
Short name T58
Test name
Test status
Simulation time 473668219 ps
CPU time 1.24 seconds
Started Jul 02 09:49:47 AM PDT 24
Finished Jul 02 09:49:53 AM PDT 24
Peak memory 193148 kb
Host smart-2f1adb90-9654-4ebf-b3a0-7d490cc8097e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729170398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3729170398
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1245643545
Short name T384
Test name
Test status
Simulation time 463532527 ps
CPU time 0.89 seconds
Started Jul 02 09:49:46 AM PDT 24
Finished Jul 02 09:49:50 AM PDT 24
Peak memory 183764 kb
Host smart-f97c7a94-f43c-4a38-b383-630b6d7ff002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245643545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1245643545
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.569051903
Short name T405
Test name
Test status
Simulation time 2266009906 ps
CPU time 3.06 seconds
Started Jul 02 09:49:33 AM PDT 24
Finished Jul 02 09:49:40 AM PDT 24
Peak memory 195044 kb
Host smart-a0afc8c9-cd40-4ed1-9ccf-844961d9424c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569051903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.569051903
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1284431619
Short name T309
Test name
Test status
Simulation time 518882753 ps
CPU time 1.65 seconds
Started Jul 02 09:49:36 AM PDT 24
Finished Jul 02 09:49:41 AM PDT 24
Peak memory 198648 kb
Host smart-39754655-a737-42e0-856f-1a4e556089f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284431619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1284431619
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2308772693
Short name T353
Test name
Test status
Simulation time 4076734834 ps
CPU time 2.42 seconds
Started Jul 02 09:49:40 AM PDT 24
Finished Jul 02 09:49:45 AM PDT 24
Peak memory 197884 kb
Host smart-a5081697-c7f8-4ebb-ac0d-1ebb71bc6ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308772693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2308772693
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1813566851
Short name T312
Test name
Test status
Simulation time 825266348 ps
CPU time 0.78 seconds
Started Jul 02 09:49:46 AM PDT 24
Finished Jul 02 09:49:50 AM PDT 24
Peak memory 197292 kb
Host smart-9a795fac-1d52-470c-9dde-207b448cf539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813566851 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1813566851
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.130409081
Short name T53
Test name
Test status
Simulation time 483857375 ps
CPU time 0.77 seconds
Started Jul 02 09:49:28 AM PDT 24
Finished Jul 02 09:49:34 AM PDT 24
Peak memory 192996 kb
Host smart-32cb31ac-7f6f-4483-9852-03f1cf9e54b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130409081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.130409081
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3744996556
Short name T368
Test name
Test status
Simulation time 344063014 ps
CPU time 0.68 seconds
Started Jul 02 09:49:58 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 192920 kb
Host smart-333e5384-b328-4051-be5a-833d72129218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744996556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3744996556
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1688802728
Short name T81
Test name
Test status
Simulation time 1529203324 ps
CPU time 1.36 seconds
Started Jul 02 09:49:58 AM PDT 24
Finished Jul 02 09:50:06 AM PDT 24
Peak memory 193952 kb
Host smart-62157e5e-7bfa-4fb8-8632-9796094a019a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688802728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1688802728
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1372654369
Short name T374
Test name
Test status
Simulation time 469491994 ps
CPU time 1.86 seconds
Started Jul 02 09:49:29 AM PDT 24
Finished Jul 02 09:49:35 AM PDT 24
Peak memory 198468 kb
Host smart-bea3cf38-7c34-4b6a-815d-e89ebdbd32b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372654369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1372654369
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1983941886
Short name T196
Test name
Test status
Simulation time 4246205165 ps
CPU time 6.45 seconds
Started Jul 02 09:49:39 AM PDT 24
Finished Jul 02 09:49:48 AM PDT 24
Peak memory 197944 kb
Host smart-4292f01e-f2d5-43ab-8b28-07250f7f57fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983941886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1983941886
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2503822436
Short name T239
Test name
Test status
Simulation time 8169955886 ps
CPU time 6.76 seconds
Started Jul 02 09:17:01 AM PDT 24
Finished Jul 02 09:17:09 AM PDT 24
Peak memory 191748 kb
Host smart-c4c65727-61bb-4850-8ca6-68d6d61dc6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503822436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2503822436
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2076714761
Short name T61
Test name
Test status
Simulation time 561405376 ps
CPU time 0.81 seconds
Started Jul 02 09:17:00 AM PDT 24
Finished Jul 02 09:17:01 AM PDT 24
Peak memory 196536 kb
Host smart-bef79b3b-c641-4d33-a931-e4aa4dddd5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076714761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2076714761
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.4211788472
Short name T266
Test name
Test status
Simulation time 13397751395 ps
CPU time 17.32 seconds
Started Jul 02 09:17:00 AM PDT 24
Finished Jul 02 09:17:18 AM PDT 24
Peak memory 191712 kb
Host smart-4c7d3828-d975-4bd1-87b7-f9796e446ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211788472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4211788472
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3292370413
Short name T15
Test name
Test status
Simulation time 4004677063 ps
CPU time 2 seconds
Started Jul 02 09:17:04 AM PDT 24
Finished Jul 02 09:17:07 AM PDT 24
Peak memory 215392 kb
Host smart-0e391ba6-af2d-4afb-b850-d49e3039e047
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292370413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3292370413
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.878206101
Short name T209
Test name
Test status
Simulation time 387739082 ps
CPU time 1.11 seconds
Started Jul 02 09:17:00 AM PDT 24
Finished Jul 02 09:17:03 AM PDT 24
Peak memory 191620 kb
Host smart-908c2286-4887-4d04-a2ee-9fa30329b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878206101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.878206101
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1853664673
Short name T248
Test name
Test status
Simulation time 33104128857 ps
CPU time 11.75 seconds
Started Jul 02 09:17:18 AM PDT 24
Finished Jul 02 09:17:31 AM PDT 24
Peak memory 191712 kb
Host smart-bf2cf798-ac42-4352-84f2-4bccac29816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853664673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1853664673
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.164175453
Short name T274
Test name
Test status
Simulation time 498163024 ps
CPU time 1.37 seconds
Started Jul 02 09:17:15 AM PDT 24
Finished Jul 02 09:17:17 AM PDT 24
Peak memory 191656 kb
Host smart-ca0cf880-7125-468d-a0d6-b4d20a7aede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164175453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.164175453
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3584272653
Short name T281
Test name
Test status
Simulation time 32500514520 ps
CPU time 22 seconds
Started Jul 02 09:17:20 AM PDT 24
Finished Jul 02 09:17:43 AM PDT 24
Peak memory 191712 kb
Host smart-7aa8ef6c-88ba-4310-8613-70ccb9d87bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584272653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3584272653
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1603026294
Short name T207
Test name
Test status
Simulation time 509907386 ps
CPU time 0.99 seconds
Started Jul 02 09:17:23 AM PDT 24
Finished Jul 02 09:17:25 AM PDT 24
Peak memory 191664 kb
Host smart-15c8a943-5da3-4743-96a8-8ee5e257d35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603026294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1603026294
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.567701359
Short name T283
Test name
Test status
Simulation time 34650056716 ps
CPU time 51.24 seconds
Started Jul 02 09:17:23 AM PDT 24
Finished Jul 02 09:18:14 AM PDT 24
Peak memory 191700 kb
Host smart-ab465503-e214-46c1-8df4-529ab35e6817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567701359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.567701359
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2744706731
Short name T244
Test name
Test status
Simulation time 521522365 ps
CPU time 0.66 seconds
Started Jul 02 09:17:22 AM PDT 24
Finished Jul 02 09:17:23 AM PDT 24
Peak memory 191660 kb
Host smart-e6f492d1-c8e6-4d13-b0c5-15b797135d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744706731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2744706731
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3676910403
Short name T204
Test name
Test status
Simulation time 43081680859 ps
CPU time 16.03 seconds
Started Jul 02 09:17:21 AM PDT 24
Finished Jul 02 09:17:38 AM PDT 24
Peak memory 191740 kb
Host smart-6baa7605-77d2-414d-8eec-528c38b61278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676910403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3676910403
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.996438890
Short name T220
Test name
Test status
Simulation time 665008422 ps
CPU time 0.77 seconds
Started Jul 02 09:17:22 AM PDT 24
Finished Jul 02 09:17:23 AM PDT 24
Peak memory 191860 kb
Host smart-579f2b98-ad21-42b6-858a-6bf6418f132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996438890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.996438890
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.4182124923
Short name T260
Test name
Test status
Simulation time 8948480723 ps
CPU time 6.59 seconds
Started Jul 02 09:17:24 AM PDT 24
Finished Jul 02 09:17:32 AM PDT 24
Peak memory 191756 kb
Host smart-9eecfd4e-c35b-4e21-9e98-fe25ac6511e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182124923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.4182124923
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3820605220
Short name T254
Test name
Test status
Simulation time 368121476 ps
CPU time 0.88 seconds
Started Jul 02 09:17:24 AM PDT 24
Finished Jul 02 09:17:26 AM PDT 24
Peak memory 191596 kb
Host smart-e85a4bff-47ac-40b3-af0f-da59ed570249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820605220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3820605220
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2290839446
Short name T252
Test name
Test status
Simulation time 9907779648 ps
CPU time 3.28 seconds
Started Jul 02 09:17:25 AM PDT 24
Finished Jul 02 09:17:29 AM PDT 24
Peak memory 196900 kb
Host smart-7146cfdf-ef46-4127-84db-a185182bb6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290839446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2290839446
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1695057231
Short name T238
Test name
Test status
Simulation time 384496991 ps
CPU time 0.89 seconds
Started Jul 02 09:17:26 AM PDT 24
Finished Jul 02 09:17:28 AM PDT 24
Peak memory 196464 kb
Host smart-3cb9a23c-d699-490f-9510-4cbef955890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695057231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1695057231
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.635347013
Short name T278
Test name
Test status
Simulation time 36372668317 ps
CPU time 15.18 seconds
Started Jul 02 09:17:30 AM PDT 24
Finished Jul 02 09:17:46 AM PDT 24
Peak memory 191668 kb
Host smart-64d5bd07-b60c-48f8-879c-81188753f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635347013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.635347013
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2655121180
Short name T228
Test name
Test status
Simulation time 595238877 ps
CPU time 0.76 seconds
Started Jul 02 09:17:28 AM PDT 24
Finished Jul 02 09:17:29 AM PDT 24
Peak memory 191604 kb
Host smart-935818c5-5c40-4702-adaf-5a0b1187ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655121180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2655121180
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.281331582
Short name T2
Test name
Test status
Simulation time 38852620900 ps
CPU time 56.2 seconds
Started Jul 02 09:17:30 AM PDT 24
Finished Jul 02 09:18:27 AM PDT 24
Peak memory 191748 kb
Host smart-9317eaf2-5411-42f7-adab-46ea54756093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281331582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.281331582
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.233987423
Short name T230
Test name
Test status
Simulation time 576740753 ps
CPU time 1.36 seconds
Started Jul 02 09:17:29 AM PDT 24
Finished Jul 02 09:17:32 AM PDT 24
Peak memory 191628 kb
Host smart-759e3fad-1535-477a-9096-c35aeaf35d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233987423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.233987423
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2999371934
Short name T215
Test name
Test status
Simulation time 18573915670 ps
CPU time 13.68 seconds
Started Jul 02 09:17:31 AM PDT 24
Finished Jul 02 09:17:46 AM PDT 24
Peak memory 196760 kb
Host smart-c870a4d3-60f3-4c41-aee9-974b1988ec1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999371934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2999371934
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.4118395875
Short name T263
Test name
Test status
Simulation time 342278330 ps
CPU time 0.83 seconds
Started Jul 02 09:17:29 AM PDT 24
Finished Jul 02 09:17:31 AM PDT 24
Peak memory 191688 kb
Host smart-293ba50e-ae3e-42e8-9104-5b70f2c8f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118395875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4118395875
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2019598014
Short name T264
Test name
Test status
Simulation time 40969097287 ps
CPU time 21.13 seconds
Started Jul 02 09:17:31 AM PDT 24
Finished Jul 02 09:17:53 AM PDT 24
Peak memory 191664 kb
Host smart-f046fd8e-a997-4435-a51d-6129c74ee068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019598014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2019598014
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3041243634
Short name T240
Test name
Test status
Simulation time 504809404 ps
CPU time 0.61 seconds
Started Jul 02 09:17:36 AM PDT 24
Finished Jul 02 09:17:38 AM PDT 24
Peak memory 191636 kb
Host smart-ea043e1c-7151-406e-a784-298786c99c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041243634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3041243634
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1862698202
Short name T282
Test name
Test status
Simulation time 44332038266 ps
CPU time 59.78 seconds
Started Jul 02 09:17:04 AM PDT 24
Finished Jul 02 09:18:04 AM PDT 24
Peak memory 196932 kb
Host smart-68ecf30f-3d93-43ff-85ea-be3c82cd2b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862698202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1862698202
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.926154006
Short name T19
Test name
Test status
Simulation time 4055647644 ps
CPU time 1.89 seconds
Started Jul 02 09:17:03 AM PDT 24
Finished Jul 02 09:17:05 AM PDT 24
Peak memory 215688 kb
Host smart-2ca80261-dcb8-4a58-a432-2c4376f9f870
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926154006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.926154006
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.4001203552
Short name T275
Test name
Test status
Simulation time 608668715 ps
CPU time 1.35 seconds
Started Jul 02 09:17:07 AM PDT 24
Finished Jul 02 09:17:08 AM PDT 24
Peak memory 196484 kb
Host smart-cc03431a-55da-4c39-aafb-8b999a807e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001203552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.4001203552
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.488091232
Short name T40
Test name
Test status
Simulation time 432952448 ps
CPU time 0.7 seconds
Started Jul 02 09:17:33 AM PDT 24
Finished Jul 02 09:17:34 AM PDT 24
Peak memory 196436 kb
Host smart-b671cd5d-33f5-485d-b554-0d3d2ea69b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488091232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.488091232
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1002052745
Short name T232
Test name
Test status
Simulation time 3043627856 ps
CPU time 1.65 seconds
Started Jul 02 09:17:36 AM PDT 24
Finished Jul 02 09:17:38 AM PDT 24
Peak memory 191708 kb
Host smart-2f4f4015-c266-4c07-94e7-52497cc4a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002052745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1002052745
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.904281241
Short name T261
Test name
Test status
Simulation time 535139541 ps
CPU time 0.99 seconds
Started Jul 02 09:17:34 AM PDT 24
Finished Jul 02 09:17:36 AM PDT 24
Peak memory 196480 kb
Host smart-748918fc-44f7-41df-9219-69baefb2b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904281241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.904281241
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4247562337
Short name T250
Test name
Test status
Simulation time 34787051700 ps
CPU time 24.46 seconds
Started Jul 02 09:17:34 AM PDT 24
Finished Jul 02 09:17:59 AM PDT 24
Peak memory 191688 kb
Host smart-6df83bd5-8d4a-4881-99f0-2e9786507240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247562337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4247562337
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2253842776
Short name T222
Test name
Test status
Simulation time 556722173 ps
CPU time 1.04 seconds
Started Jul 02 09:17:34 AM PDT 24
Finished Jul 02 09:17:36 AM PDT 24
Peak memory 191656 kb
Host smart-432ae600-15c1-4e45-8b3a-0580fb30e1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253842776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2253842776
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3833762568
Short name T231
Test name
Test status
Simulation time 25991699329 ps
CPU time 144.16 seconds
Started Jul 02 09:17:37 AM PDT 24
Finished Jul 02 09:20:02 AM PDT 24
Peak memory 198460 kb
Host smart-cd74d8d6-fd7e-4402-bb63-84aa14299e79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833762568 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3833762568
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3294246862
Short name T285
Test name
Test status
Simulation time 15255969734 ps
CPU time 5.72 seconds
Started Jul 02 09:17:39 AM PDT 24
Finished Jul 02 09:17:45 AM PDT 24
Peak memory 191752 kb
Host smart-d247a0c9-3463-4ed4-b638-0aa4fc6f54d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294246862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3294246862
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1954844739
Short name T213
Test name
Test status
Simulation time 619749265 ps
CPU time 0.87 seconds
Started Jul 02 09:17:36 AM PDT 24
Finished Jul 02 09:17:38 AM PDT 24
Peak memory 191660 kb
Host smart-0161cb85-47a4-4de4-b401-10117bb45b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954844739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1954844739
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4214028746
Short name T234
Test name
Test status
Simulation time 24966120156 ps
CPU time 9.09 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:17:52 AM PDT 24
Peak memory 191620 kb
Host smart-1b568a05-66dd-4226-81ca-64ab8802c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214028746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4214028746
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4143458863
Short name T233
Test name
Test status
Simulation time 555203241 ps
CPU time 0.85 seconds
Started Jul 02 09:17:46 AM PDT 24
Finished Jul 02 09:17:47 AM PDT 24
Peak memory 191652 kb
Host smart-9abebbb9-ee21-4259-944c-7af47893cfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143458863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4143458863
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2624317820
Short name T211
Test name
Test status
Simulation time 24083348912 ps
CPU time 25.66 seconds
Started Jul 02 09:17:38 AM PDT 24
Finished Jul 02 09:18:05 AM PDT 24
Peak memory 196752 kb
Host smart-9b9a2135-54e1-48ad-ba7c-cc1a804dca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624317820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2624317820
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2508050575
Short name T270
Test name
Test status
Simulation time 512568517 ps
CPU time 0.69 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:17:44 AM PDT 24
Peak memory 196388 kb
Host smart-eaa76a31-d1e3-4e68-827d-039427a16cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508050575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2508050575
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1076273750
Short name T224
Test name
Test status
Simulation time 34945911063 ps
CPU time 5.48 seconds
Started Jul 02 09:17:37 AM PDT 24
Finished Jul 02 09:17:44 AM PDT 24
Peak memory 196752 kb
Host smart-1d924a01-4166-4d4a-99cf-57a4aa5db679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076273750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1076273750
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4160186968
Short name T227
Test name
Test status
Simulation time 367501918 ps
CPU time 0.92 seconds
Started Jul 02 09:17:45 AM PDT 24
Finished Jul 02 09:17:47 AM PDT 24
Peak memory 191652 kb
Host smart-e1081577-601d-491b-b0ab-3f503cf937c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160186968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4160186968
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2847436579
Short name T235
Test name
Test status
Simulation time 47699024647 ps
CPU time 36.11 seconds
Started Jul 02 09:17:38 AM PDT 24
Finished Jul 02 09:18:15 AM PDT 24
Peak memory 191740 kb
Host smart-f5fa1293-6f33-4f17-a69b-10be0eb5a78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847436579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2847436579
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.966288097
Short name T267
Test name
Test status
Simulation time 483773368 ps
CPU time 0.75 seconds
Started Jul 02 09:17:46 AM PDT 24
Finished Jul 02 09:17:48 AM PDT 24
Peak memory 196504 kb
Host smart-461f2e88-545a-4ac5-a378-8ae68fbceb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966288097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.966288097
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.929331219
Short name T218
Test name
Test status
Simulation time 10981379825 ps
CPU time 15.46 seconds
Started Jul 02 09:17:43 AM PDT 24
Finished Jul 02 09:18:00 AM PDT 24
Peak memory 191760 kb
Host smart-0a92cf53-6671-4070-8c59-ee71a16f4bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929331219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.929331219
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1019614232
Short name T214
Test name
Test status
Simulation time 461152711 ps
CPU time 1.09 seconds
Started Jul 02 09:17:45 AM PDT 24
Finished Jul 02 09:17:47 AM PDT 24
Peak memory 191632 kb
Host smart-4242246c-3af5-45e6-8e92-cde9a4fe0b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019614232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1019614232
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1911369102
Short name T67
Test name
Test status
Simulation time 227439080362 ps
CPU time 156.96 seconds
Started Jul 02 09:17:45 AM PDT 24
Finished Jul 02 09:20:22 AM PDT 24
Peak memory 192712 kb
Host smart-34e3d2a8-7fce-41eb-a36d-d291b4b618c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911369102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1911369102
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2340048155
Short name T203
Test name
Test status
Simulation time 25511296635 ps
CPU time 39.14 seconds
Started Jul 02 09:17:45 AM PDT 24
Finished Jul 02 09:18:25 AM PDT 24
Peak memory 191748 kb
Host smart-e8fbc41f-1b7e-4f64-8b6c-12ceb1b675a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340048155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2340048155
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1051048540
Short name T208
Test name
Test status
Simulation time 447715437 ps
CPU time 0.8 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:17:43 AM PDT 24
Peak memory 191676 kb
Host smart-0f4bfa20-60a0-4cdf-a98c-09cfd8785606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051048540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1051048540
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3977086137
Short name T276
Test name
Test status
Simulation time 31546444368 ps
CPU time 4.65 seconds
Started Jul 02 09:17:45 AM PDT 24
Finished Jul 02 09:17:51 AM PDT 24
Peak memory 191700 kb
Host smart-8ce8f57c-2409-4323-be67-80e789d1fc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977086137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3977086137
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1191917931
Short name T256
Test name
Test status
Simulation time 558611023 ps
CPU time 1.39 seconds
Started Jul 02 09:17:43 AM PDT 24
Finished Jul 02 09:17:45 AM PDT 24
Peak memory 196516 kb
Host smart-3c3a5a01-d8f9-45b1-aa53-53912f5bbb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191917931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1191917931
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2964922680
Short name T236
Test name
Test status
Simulation time 3093512721 ps
CPU time 2.65 seconds
Started Jul 02 09:17:05 AM PDT 24
Finished Jul 02 09:17:08 AM PDT 24
Peak memory 196556 kb
Host smart-952202b6-7609-4060-8918-7f847b275c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964922680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2964922680
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2266270642
Short name T11
Test name
Test status
Simulation time 3980871682 ps
CPU time 2.13 seconds
Started Jul 02 09:17:06 AM PDT 24
Finished Jul 02 09:17:09 AM PDT 24
Peak memory 215432 kb
Host smart-00a037f5-8f82-4ea9-b221-8601f458d4c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266270642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2266270642
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3822467465
Short name T226
Test name
Test status
Simulation time 400686077 ps
CPU time 0.85 seconds
Started Jul 02 09:17:03 AM PDT 24
Finished Jul 02 09:17:04 AM PDT 24
Peak memory 191676 kb
Host smart-417d5989-b168-4fd4-8bfd-320678943f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822467465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3822467465
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4264819225
Short name T42
Test name
Test status
Simulation time 32401380050 ps
CPU time 44.49 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:18:28 AM PDT 24
Peak memory 196756 kb
Host smart-f17f33d4-c72f-43b1-b936-6162d3b2cb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264819225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4264819225
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2498785930
Short name T63
Test name
Test status
Simulation time 486033706 ps
CPU time 1.31 seconds
Started Jul 02 09:17:42 AM PDT 24
Finished Jul 02 09:17:45 AM PDT 24
Peak memory 191680 kb
Host smart-8aafa063-2f43-49f1-9528-c5f8134c653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498785930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2498785930
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.370992337
Short name T259
Test name
Test status
Simulation time 38863522377 ps
CPU time 9.95 seconds
Started Jul 02 09:17:43 AM PDT 24
Finished Jul 02 09:17:54 AM PDT 24
Peak memory 191744 kb
Host smart-a943f7f8-0090-40ae-98b3-96bc161e6d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370992337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.370992337
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.590155091
Short name T251
Test name
Test status
Simulation time 448479115 ps
CPU time 0.87 seconds
Started Jul 02 09:17:45 AM PDT 24
Finished Jul 02 09:17:46 AM PDT 24
Peak memory 191640 kb
Host smart-8d996354-04b5-4e49-ac2a-6fc94d2e2ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590155091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.590155091
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3563098799
Short name T202
Test name
Test status
Simulation time 23006921656 ps
CPU time 5 seconds
Started Jul 02 09:17:44 AM PDT 24
Finished Jul 02 09:17:50 AM PDT 24
Peak memory 196720 kb
Host smart-cec38c31-8783-44c0-9e31-d5b6f5254c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563098799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3563098799
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2938793875
Short name T20
Test name
Test status
Simulation time 451000889 ps
CPU time 1.2 seconds
Started Jul 02 09:17:46 AM PDT 24
Finished Jul 02 09:17:48 AM PDT 24
Peak memory 191672 kb
Host smart-00e0e5c2-471c-48e4-a688-4174d528d8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938793875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2938793875
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1442808967
Short name T210
Test name
Test status
Simulation time 59128919830 ps
CPU time 77.99 seconds
Started Jul 02 09:17:48 AM PDT 24
Finished Jul 02 09:19:07 AM PDT 24
Peak memory 191656 kb
Host smart-759da84b-86cd-4068-b4af-f66b23d2fe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442808967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1442808967
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1935502640
Short name T221
Test name
Test status
Simulation time 363652315 ps
CPU time 1.09 seconds
Started Jul 02 09:17:46 AM PDT 24
Finished Jul 02 09:17:48 AM PDT 24
Peak memory 191656 kb
Host smart-c4404784-c264-45a0-bf06-6c1a015139a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935502640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1935502640
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2222459422
Short name T277
Test name
Test status
Simulation time 15683873001 ps
CPU time 23.7 seconds
Started Jul 02 09:17:45 AM PDT 24
Finished Jul 02 09:18:10 AM PDT 24
Peak memory 191732 kb
Host smart-dadfcd78-d082-467d-8e86-bdaed788723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222459422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2222459422
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3070325834
Short name T245
Test name
Test status
Simulation time 407866603 ps
CPU time 0.75 seconds
Started Jul 02 09:17:49 AM PDT 24
Finished Jul 02 09:17:50 AM PDT 24
Peak memory 196560 kb
Host smart-59c92ec8-4a01-48d0-bab6-4d1b853fb929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070325834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3070325834
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1534592928
Short name T64
Test name
Test status
Simulation time 16504698425 ps
CPU time 4.92 seconds
Started Jul 02 09:17:51 AM PDT 24
Finished Jul 02 09:17:57 AM PDT 24
Peak memory 191740 kb
Host smart-2a8b198f-c3b7-49f7-980b-0ef9d9b7d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534592928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1534592928
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3659174466
Short name T13
Test name
Test status
Simulation time 565643736 ps
CPU time 0.8 seconds
Started Jul 02 09:17:53 AM PDT 24
Finished Jul 02 09:17:54 AM PDT 24
Peak memory 191668 kb
Host smart-04119100-8025-407f-8f20-48635fd772e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659174466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3659174466
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1278522266
Short name T166
Test name
Test status
Simulation time 596783312 ps
CPU time 0.87 seconds
Started Jul 02 09:17:53 AM PDT 24
Finished Jul 02 09:17:55 AM PDT 24
Peak memory 196428 kb
Host smart-f91a53ac-f77a-4bbd-8052-e793cdb946ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278522266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1278522266
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2270107592
Short name T257
Test name
Test status
Simulation time 20240848789 ps
CPU time 12.67 seconds
Started Jul 02 09:17:55 AM PDT 24
Finished Jul 02 09:18:08 AM PDT 24
Peak memory 196732 kb
Host smart-f0dfe9b8-ff7b-472e-aed0-10da649d0a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270107592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2270107592
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.217655999
Short name T269
Test name
Test status
Simulation time 378454944 ps
CPU time 1.13 seconds
Started Jul 02 09:17:52 AM PDT 24
Finished Jul 02 09:17:54 AM PDT 24
Peak memory 191672 kb
Host smart-d2c05a2c-08a6-4b4c-80d1-4a5b1d8f6e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217655999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.217655999
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.4076411706
Short name T284
Test name
Test status
Simulation time 57440875898 ps
CPU time 44.8 seconds
Started Jul 02 09:17:54 AM PDT 24
Finished Jul 02 09:18:39 AM PDT 24
Peak memory 191696 kb
Host smart-23d85001-e94a-4519-8878-708d7dbe9bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076411706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.4076411706
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3329806110
Short name T255
Test name
Test status
Simulation time 426018314 ps
CPU time 1.28 seconds
Started Jul 02 09:17:55 AM PDT 24
Finished Jul 02 09:17:57 AM PDT 24
Peak memory 191640 kb
Host smart-e53f1a37-f5fc-46e7-95c3-78b8ed6d7c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329806110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3329806110
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2091817161
Short name T41
Test name
Test status
Simulation time 51226902577 ps
CPU time 76.75 seconds
Started Jul 02 09:17:57 AM PDT 24
Finished Jul 02 09:19:14 AM PDT 24
Peak memory 191728 kb
Host smart-573b3635-c893-4215-a7ee-24b48bf70685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091817161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2091817161
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1870308140
Short name T279
Test name
Test status
Simulation time 437749128 ps
CPU time 1.11 seconds
Started Jul 02 09:17:56 AM PDT 24
Finished Jul 02 09:17:58 AM PDT 24
Peak memory 191864 kb
Host smart-12fe8660-80b5-4ce1-ac83-66d4b5377916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870308140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1870308140
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2909547006
Short name T268
Test name
Test status
Simulation time 5052316409 ps
CPU time 8.26 seconds
Started Jul 02 09:17:56 AM PDT 24
Finished Jul 02 09:18:05 AM PDT 24
Peak memory 191668 kb
Host smart-3c592b94-3830-486b-ad1f-9477f7ea2ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909547006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2909547006
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2047914067
Short name T271
Test name
Test status
Simulation time 391906865 ps
CPU time 0.72 seconds
Started Jul 02 09:17:55 AM PDT 24
Finished Jul 02 09:17:56 AM PDT 24
Peak memory 191672 kb
Host smart-7d577be6-8a44-4277-b720-7b4c5d56f2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047914067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2047914067
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2290233619
Short name T225
Test name
Test status
Simulation time 30099464782 ps
CPU time 21.62 seconds
Started Jul 02 09:17:09 AM PDT 24
Finished Jul 02 09:17:32 AM PDT 24
Peak memory 196736 kb
Host smart-0e4d2570-8438-4c4b-9bfb-08df228b8e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290233619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2290233619
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2635874179
Short name T18
Test name
Test status
Simulation time 4016268769 ps
CPU time 3.4 seconds
Started Jul 02 09:17:11 AM PDT 24
Finished Jul 02 09:17:15 AM PDT 24
Peak memory 215452 kb
Host smart-93415f76-09ca-48ee-908b-85cbde10fc35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635874179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2635874179
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3505701272
Short name T241
Test name
Test status
Simulation time 604895075 ps
CPU time 0.71 seconds
Started Jul 02 09:17:03 AM PDT 24
Finished Jul 02 09:17:04 AM PDT 24
Peak memory 191624 kb
Host smart-85e4a216-27d3-4664-8f19-04103ec1f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505701272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3505701272
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4262793303
Short name T167
Test name
Test status
Simulation time 414380190 ps
CPU time 1.15 seconds
Started Jul 02 09:17:59 AM PDT 24
Finished Jul 02 09:18:00 AM PDT 24
Peak memory 196528 kb
Host smart-9f23476c-14b2-4b06-99cb-a28f6bbc1f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262793303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4262793303
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3195784673
Short name T43
Test name
Test status
Simulation time 7767682267 ps
CPU time 13.13 seconds
Started Jul 02 09:17:55 AM PDT 24
Finished Jul 02 09:18:09 AM PDT 24
Peak memory 191684 kb
Host smart-23dc460d-e32a-46b4-a61a-0ec7754c41e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195784673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3195784673
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2301343044
Short name T272
Test name
Test status
Simulation time 544384251 ps
CPU time 0.72 seconds
Started Jul 02 09:17:55 AM PDT 24
Finished Jul 02 09:17:57 AM PDT 24
Peak memory 196508 kb
Host smart-0ebcb6a3-31f0-40a9-b158-1ac59a180bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301343044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2301343044
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2825079309
Short name T246
Test name
Test status
Simulation time 470195075 ps
CPU time 0.84 seconds
Started Jul 02 09:17:57 AM PDT 24
Finished Jul 02 09:17:59 AM PDT 24
Peak memory 191668 kb
Host smart-e4be106f-716f-415e-933a-a12c79a125d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825079309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2825079309
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.689675350
Short name T22
Test name
Test status
Simulation time 441121482 ps
CPU time 0.75 seconds
Started Jul 02 09:17:57 AM PDT 24
Finished Jul 02 09:17:58 AM PDT 24
Peak memory 191660 kb
Host smart-bc6cbd03-f57d-48c2-9fbd-698904de0d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689675350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.689675350
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_jump.467075399
Short name T178
Test name
Test status
Simulation time 616350582 ps
CPU time 0.72 seconds
Started Jul 02 09:18:07 AM PDT 24
Finished Jul 02 09:18:09 AM PDT 24
Peak memory 196440 kb
Host smart-c7c6cb7a-7b2d-4728-bfcb-041987e1f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467075399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.467075399
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3710748588
Short name T1
Test name
Test status
Simulation time 4646546729 ps
CPU time 4 seconds
Started Jul 02 09:18:00 AM PDT 24
Finished Jul 02 09:18:05 AM PDT 24
Peak memory 196752 kb
Host smart-3db6d77e-b2e1-4c15-906d-0b4c1f131fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710748588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3710748588
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3079247843
Short name T262
Test name
Test status
Simulation time 385353914 ps
CPU time 1.13 seconds
Started Jul 02 09:18:04 AM PDT 24
Finished Jul 02 09:18:06 AM PDT 24
Peak memory 191672 kb
Host smart-6ccad2a3-c8e1-404f-924d-14bbb8496006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079247843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3079247843
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.239479947
Short name T280
Test name
Test status
Simulation time 38796492422 ps
CPU time 15.45 seconds
Started Jul 02 09:18:00 AM PDT 24
Finished Jul 02 09:18:16 AM PDT 24
Peak memory 191736 kb
Host smart-18c45e67-5fd1-4d25-bf8d-ad1032bc6f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239479947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.239479947
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.973561199
Short name T242
Test name
Test status
Simulation time 628816964 ps
CPU time 0.83 seconds
Started Jul 02 09:18:02 AM PDT 24
Finished Jul 02 09:18:03 AM PDT 24
Peak memory 191584 kb
Host smart-e4aa33ba-d0b1-47f5-8bac-bc3c077f198f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973561199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.973561199
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.106924252
Short name T200
Test name
Test status
Simulation time 9940592320 ps
CPU time 15.52 seconds
Started Jul 02 09:18:07 AM PDT 24
Finished Jul 02 09:18:23 AM PDT 24
Peak memory 191736 kb
Host smart-a8226c27-12fc-4ec7-b1b6-04f8fcc21eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106924252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.106924252
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.737143870
Short name T273
Test name
Test status
Simulation time 488828815 ps
CPU time 0.97 seconds
Started Jul 02 09:18:00 AM PDT 24
Finished Jul 02 09:18:01 AM PDT 24
Peak memory 196516 kb
Host smart-a1297d9a-b9c2-44a1-97f0-6ad98ad5b360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737143870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.737143870
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.975533296
Short name T45
Test name
Test status
Simulation time 49182862627 ps
CPU time 36.65 seconds
Started Jul 02 09:18:05 AM PDT 24
Finished Jul 02 09:18:42 AM PDT 24
Peak memory 191744 kb
Host smart-9d633504-4653-4999-94b7-30b64bea3f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975533296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.975533296
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1697527933
Short name T39
Test name
Test status
Simulation time 565179600 ps
CPU time 0.77 seconds
Started Jul 02 09:18:07 AM PDT 24
Finished Jul 02 09:18:08 AM PDT 24
Peak memory 196484 kb
Host smart-453d0339-41f4-4c13-847a-d7f2fe77b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697527933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1697527933
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.969115763
Short name T201
Test name
Test status
Simulation time 10530828575 ps
CPU time 16.92 seconds
Started Jul 02 09:18:07 AM PDT 24
Finished Jul 02 09:18:24 AM PDT 24
Peak memory 191660 kb
Host smart-6ff1c7a4-dc48-4e15-b584-f03daa2c9a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969115763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.969115763
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1045858764
Short name T223
Test name
Test status
Simulation time 578790434 ps
CPU time 0.68 seconds
Started Jul 02 09:18:04 AM PDT 24
Finished Jul 02 09:18:06 AM PDT 24
Peak memory 191652 kb
Host smart-520e3d53-9cd4-4909-951c-3f733b60099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045858764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1045858764
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1755640594
Short name T258
Test name
Test status
Simulation time 17731352313 ps
CPU time 8.57 seconds
Started Jul 02 09:18:03 AM PDT 24
Finished Jul 02 09:18:12 AM PDT 24
Peak memory 196740 kb
Host smart-d0e61bd2-a8b5-48af-9736-15e7a1708c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755640594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1755640594
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.775390050
Short name T265
Test name
Test status
Simulation time 607228819 ps
CPU time 0.7 seconds
Started Jul 02 09:18:03 AM PDT 24
Finished Jul 02 09:18:04 AM PDT 24
Peak memory 191668 kb
Host smart-ed044a12-166e-4871-b1d1-dff7bb6791e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775390050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.775390050
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1853410617
Short name T205
Test name
Test status
Simulation time 385553855800 ps
CPU time 263.77 seconds
Started Jul 02 09:18:04 AM PDT 24
Finished Jul 02 09:22:29 AM PDT 24
Peak memory 192080 kb
Host smart-68d0da8b-a75a-479f-8d7a-e476d24c02dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853410617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1853410617
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2063476002
Short name T188
Test name
Test status
Simulation time 43537040971 ps
CPU time 182.35 seconds
Started Jul 02 09:18:10 AM PDT 24
Finished Jul 02 09:21:13 AM PDT 24
Peak memory 206580 kb
Host smart-1f76c5e3-b81a-44ee-856d-da21ad86d82b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063476002 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2063476002
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2829776785
Short name T253
Test name
Test status
Simulation time 2451844243 ps
CPU time 1.35 seconds
Started Jul 02 09:18:06 AM PDT 24
Finished Jul 02 09:18:08 AM PDT 24
Peak memory 191656 kb
Host smart-850be246-1b95-4676-ae09-2925de6250fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829776785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2829776785
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2426464467
Short name T243
Test name
Test status
Simulation time 607897857 ps
CPU time 0.75 seconds
Started Jul 02 09:18:06 AM PDT 24
Finished Jul 02 09:18:07 AM PDT 24
Peak memory 196496 kb
Host smart-a4499ef8-0fc7-4cec-9219-3f91f419deff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426464467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2426464467
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2739457075
Short name T249
Test name
Test status
Simulation time 4168932585 ps
CPU time 6.06 seconds
Started Jul 02 09:18:10 AM PDT 24
Finished Jul 02 09:18:17 AM PDT 24
Peak memory 191736 kb
Host smart-383a110d-d625-4949-b5f0-4e20be9b91fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739457075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2739457075
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1639606204
Short name T237
Test name
Test status
Simulation time 391351439 ps
CPU time 1.17 seconds
Started Jul 02 09:18:08 AM PDT 24
Finished Jul 02 09:18:10 AM PDT 24
Peak memory 191636 kb
Host smart-e392e3d2-aa6c-48fd-845e-aebca3827704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639606204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1639606204
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3193682359
Short name T229
Test name
Test status
Simulation time 36210266664 ps
CPU time 22.87 seconds
Started Jul 02 09:17:07 AM PDT 24
Finished Jul 02 09:17:31 AM PDT 24
Peak memory 191740 kb
Host smart-e64e744c-bce6-4cef-a8b4-5534a44bebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193682359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3193682359
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2379339586
Short name T217
Test name
Test status
Simulation time 561893796 ps
CPU time 0.75 seconds
Started Jul 02 09:17:12 AM PDT 24
Finished Jul 02 09:17:13 AM PDT 24
Peak memory 191668 kb
Host smart-b12b855e-4275-4345-a0e0-8c728fb7fee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379339586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2379339586
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2617043375
Short name T176
Test name
Test status
Simulation time 370498457 ps
CPU time 0.87 seconds
Started Jul 02 09:17:11 AM PDT 24
Finished Jul 02 09:17:12 AM PDT 24
Peak memory 196400 kb
Host smart-4a005b02-b9e6-4b99-bf14-924090149d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617043375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2617043375
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1616313300
Short name T5
Test name
Test status
Simulation time 54110963174 ps
CPU time 74.98 seconds
Started Jul 02 09:17:10 AM PDT 24
Finished Jul 02 09:18:26 AM PDT 24
Peak memory 191744 kb
Host smart-70f4fd94-e287-4c69-8acd-52eddf4ae212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616313300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1616313300
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3700702890
Short name T212
Test name
Test status
Simulation time 616940051 ps
CPU time 1.41 seconds
Started Jul 02 09:17:08 AM PDT 24
Finished Jul 02 09:17:11 AM PDT 24
Peak memory 191620 kb
Host smart-b5ff0c5a-43a9-4080-ab90-d3f441695359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700702890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3700702890
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3331161036
Short name T6
Test name
Test status
Simulation time 12830190373 ps
CPU time 9.39 seconds
Started Jul 02 09:17:12 AM PDT 24
Finished Jul 02 09:17:22 AM PDT 24
Peak memory 191656 kb
Host smart-40efe1af-4959-4fa9-815c-4183957b5eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331161036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3331161036
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2077958012
Short name T247
Test name
Test status
Simulation time 567351718 ps
CPU time 0.69 seconds
Started Jul 02 09:17:12 AM PDT 24
Finished Jul 02 09:17:14 AM PDT 24
Peak memory 191640 kb
Host smart-fffc94d7-1462-4515-bfef-d0001a2fdbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077958012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2077958012
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3295325848
Short name T219
Test name
Test status
Simulation time 25928918281 ps
CPU time 11.05 seconds
Started Jul 02 09:17:12 AM PDT 24
Finished Jul 02 09:17:23 AM PDT 24
Peak memory 191712 kb
Host smart-c4b74600-c168-44ae-a9ec-cc9400e0a04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295325848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3295325848
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1502637090
Short name T216
Test name
Test status
Simulation time 595840269 ps
CPU time 0.78 seconds
Started Jul 02 09:17:12 AM PDT 24
Finished Jul 02 09:17:14 AM PDT 24
Peak memory 196480 kb
Host smart-863a29d1-5ccc-44ed-808e-2dc38f44ba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502637090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1502637090
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2237208812
Short name T3
Test name
Test status
Simulation time 19713070793 ps
CPU time 8.33 seconds
Started Jul 02 09:17:16 AM PDT 24
Finished Jul 02 09:17:24 AM PDT 24
Peak memory 191748 kb
Host smart-308b79b1-75a4-4c70-b3a4-04877d42344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237208812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2237208812
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1195041433
Short name T59
Test name
Test status
Simulation time 528275774 ps
CPU time 0.78 seconds
Started Jul 02 09:17:19 AM PDT 24
Finished Jul 02 09:17:20 AM PDT 24
Peak memory 191616 kb
Host smart-21687439-a59d-428e-9c89-3dcd811d8576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195041433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1195041433
Directory /workspace/9.aon_timer_smoke/latest
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