Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.11	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	5	168	97.11

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	32626	1		T1	130		T2	204		T3	224
bark[1]	738	1		T1	19		T4	88		T101	14
bark[2]	439	1		T112	21		T127	21		T122	21
bark[3]	963	1		T13	21		T24	21		T114	21
bark[4]	758	1		T172	14		T46	86		T48	26
bark[5]	507	1		T5	14		T36	31		T37	68
bark[6]	269	1		T13	21		T36	26		T101	21
bark[7]	249	1		T1	21		T22	14		T81	51
bark[8]	505	1		T4	21		T37	7		T23	14
bark[9]	334	1		T3	21		T125	59		T127	21
bark[10]	960	1		T13	21		T36	306		T25	26
bark[11]	662	1		T11	59		T25	21		T39	14
bark[12]	408	1		T40	21		T83	14		T119	21
bark[13]	620	1		T11	21		T36	30		T43	21
bark[14]	979	1		T2	21		T9	30		T24	75
bark[15]	1303	1		T3	21		T13	257		T37	68
bark[16]	467	1		T1	21		T179	21		T114	21
bark[17]	796	1		T13	86		T37	102		T42	21
bark[18]	200	1		T42	26		T114	71		T127	21
bark[19]	411	1		T2	21		T4	72		T36	21
bark[20]	316	1		T9	21		T27	33		T40	26
bark[21]	794	1		T1	21		T2	30		T44	26
bark[22]	409	1		T27	21		T114	42		T125	21
bark[23]	391	1		T3	23		T114	21		T82	14
bark[24]	357	1		T8	21		T178	14		T150	14
bark[25]	479	1		T39	47		T157	14		T139	21
bark[26]	918	1		T1	39		T8	165		T42	35
bark[27]	630	1		T4	256		T37	47		T52	40
bark[28]	706	1		T8	21		T9	21		T37	157
bark[29]	641	1		T11	21		T13	26		T27	21
bark[30]	536	1		T6	14		T9	21		T43	26
bark[31]	650	1		T13	323		T36	5		T42	33
bark_0	4693	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	31939	1		T1	130		T2	144		T3	224
bite[1]	390	1		T2	21		T8	21		T27	45
bite[2]	475	1		T4	30		T9	21		T82	13
bite[3]	302	1		T36	4		T109	21		T92	235
bite[4]	676	1		T8	21		T36	30		T42	35
bite[5]	815	1		T9	21		T36	305		T37	101
bite[6]	299	1		T1	21		T13	21		T37	67
bite[7]	835	1		T2	30		T37	46		T101	21
bite[8]	257	1		T3	22		T5	13		T122	26
bite[9]	615	1		T2	59		T36	21		T179	30
bite[10]	305	1		T11	59		T179	21		T46	85
bite[11]	918	1		T8	324		T179	21		T52	40
bite[12]	572	1		T101	21		T44	26		T25	21
bite[13]	548	1		T36	31		T37	6		T177	21
bite[14]	383	1		T4	87		T91	21		T187	13
bite[15]	1013	1		T4	21		T8	164		T24	74
bite[16]	179	1		T2	21		T13	26		T138	21
bite[17]	682	1		T135	13		T51	125		T52	30
bite[18]	757	1		T3	21		T22	13		T52	21
bite[19]	954	1		T4	276		T13	256		T81	30
bite[20]	423	1		T1	39		T4	21		T9	21
bite[21]	1222	1		T13	322		T42	21		T43	21
bite[22]	487	1		T1	18		T125	21		T48	26
bite[23]	1345	1		T11	21		T37	223		T39	92
bite[24]	265	1		T1	21		T13	21		T27	21
bite[25]	754	1		T25	21		T114	91		T138	30
bite[26]	151	1		T9	30		T40	64		T46	30
bite[27]	617	1		T11	21		T45	13		T40	21
bite[28]	900	1		T43	26		T23	13		T27	130
bite[29]	485	1		T42	32		T81	21		T157	21
bite[30]	523	1		T1	21		T3	21		T36	25
bite[31]	444	1		T6	13		T13	21		T37	186
bite_0	5184	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	55714	1		T1	258		T2	283		T3	296

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	930	1		T11	19		T13	116		T36	66
prescale[1]	898	1		T4	58		T36	105		T179	28
prescale[2]	1096	1		T4	98		T13	2		T36	2
prescale[3]	742	1		T4	103		T36	9		T24	32
prescale[4]	1413	1		T1	28		T4	58		T8	40
prescale[5]	724	1		T3	24		T4	64		T42	28
prescale[6]	763	1		T13	19		T36	2		T37	25
prescale[7]	825	1		T4	171		T8	64		T11	28
prescale[8]	850	1		T3	19		T27	77		T40	112
prescale[9]	726	1		T3	23		T9	23		T13	9
prescale[10]	510	1		T43	32		T24	2		T46	2
prescale[11]	814	1		T3	19		T8	48		T13	30
prescale[12]	1367	1		T4	2		T8	30		T13	63
prescale[13]	861	1		T4	19		T13	150		T36	104
prescale[14]	865	1		T4	2		T8	2		T13	58
prescale[15]	769	1		T8	2		T36	37		T114	28
prescale[16]	1335	1		T4	88		T11	28		T37	19
prescale[17]	742	1		T8	73		T13	49		T44	19
prescale[18]	1246	1		T11	23		T13	97		T36	55
prescale[19]	1134	1		T4	62		T11	48		T36	2
prescale[20]	764	1		T2	43		T8	19		T9	37
prescale[21]	605	1		T1	23		T8	150		T13	2
prescale[22]	488	1		T3	46		T4	19		T36	19
prescale[23]	1191	1		T4	37		T8	37		T36	215
prescale[24]	677	1		T36	24		T37	2		T27	21
prescale[25]	1168	1		T1	47		T2	23		T9	9
prescale[26]	1179	1		T4	40		T8	226		T37	2
prescale[27]	818	1		T3	19		T8	94		T13	58
prescale[28]	1203	1		T4	70		T8	48		T9	19
prescale[29]	1043	1		T8	19		T9	32		T13	36
prescale[30]	940	1		T2	19		T4	34		T36	19
prescale[31]	980	1		T3	28		T24	2		T27	19
prescale_0	26048	1		T1	160		T2	198		T3	118

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	42487	1		T1	116		T2	140		T3	199
auto[1]	13227	1		T1	142		T2	143		T3	97

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	55714	1		T1	258		T2	283		T3	296

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	33266	1		T1	131		T2	185		T3	225
wkup[1]	344	1		T2	30		T3	21		T4	21
wkup[2]	212	1		T3	24		T8	47		T13	21
wkup[3]	305	1		T2	21		T27	30		T138	26
wkup[4]	279	1		T36	21		T19	15		T81	21
wkup[5]	241	1		T13	21		T43	26		T103	21
wkup[6]	356	1		T37	42		T42	21		T27	21
wkup[7]	317	1		T24	21		T27	21		T112	21
wkup[8]	161	1		T36	42		T85	21		T134	21
wkup[9]	360	1		T8	15		T27	21		T114	42
wkup[10]	471	1		T8	24		T37	42		T38	21
wkup[11]	405	1		T13	30		T36	21		T24	21
wkup[12]	382	1		T11	21		T13	21		T36	21
wkup[13]	214	1		T4	15		T8	21		T37	21
wkup[14]	308	1		T5	15		T23	15		T25	21
wkup[15]	399	1		T13	21		T36	21		T101	15
wkup[16]	305	1		T13	68		T101	21		T138	21
wkup[17]	288	1		T13	38		T36	21		T27	21
wkup[18]	382	1		T37	21		T24	31		T40	21
wkup[19]	373	1		T4	42		T44	30		T83	15
wkup[20]	158	1		T4	21		T27	21		T135	15
wkup[21]	187	1		T2	21		T103	21		T109	21
wkup[22]	312	1		T27	21		T40	21		T103	26
wkup[23]	334	1		T1	20		T13	21		T39	8
wkup[24]	375	1		T43	15		T39	42		T40	31
wkup[25]	274	1		T44	21		T114	21		T125	21
wkup[26]	500	1		T4	21		T8	21		T9	30
wkup[27]	241	1		T42	21		T114	21		T138	21
wkup[28]	218	1		T36	21		T27	21		T40	21
wkup[29]	351	1		T4	21		T9	21		T37	21
wkup[30]	239	1		T9	21		T37	21		T24	30
wkup[31]	335	1		T1	21		T4	21		T11	36
wkup[32]	221	1		T4	8		T36	21		T27	21
wkup[33]	302	1		T37	21		T40	21		T157	21
wkup[34]	365	1		T1	39		T4	21		T36	30
wkup[35]	304	1		T4	35		T119	21		T46	21
wkup[36]	160	1		T48	26		T109	21		T92	21
wkup[37]	358	1		T13	21		T36	15		T37	21
wkup[38]	310	1		T13	21		T101	21		T27	8
wkup[39]	276	1		T13	21		T36	61		T125	59
wkup[40]	340	1		T4	30		T8	21		T40	21
wkup[41]	141	1		T13	21		T157	21		T109	21
wkup[42]	367	1		T11	21		T13	21		T38	29
wkup[43]	407	1		T4	21		T8	15		T44	26
wkup[44]	197	1		T4	21		T20	15		T138	21
wkup[45]	165	1		T43	21		T25	21		T103	21
wkup[46]	276	1		T13	21		T36	21		T38	21
wkup[47]	278	1		T37	21		T179	30		T53	51
wkup[48]	281	1		T4	21		T24	21		T81	21
wkup[49]	361	1		T8	21		T37	21		T27	42
wkup[50]	200	1		T1	21		T13	21		T37	21
wkup[51]	400	1		T1	21		T4	21		T6	15
wkup[52]	253	1		T4	42		T11	26		T27	21
wkup[53]	191	1		T24	21		T27	6		T53	21
wkup[54]	304	1		T8	21		T13	8		T45	15
wkup[55]	312	1		T2	21		T4	41		T9	21
wkup[56]	443	1		T3	21		T4	46		T8	21
wkup[57]	266	1		T4	21		T9	21		T44	21
wkup[58]	263	1		T4	21		T8	21		T119	15
wkup[59]	225	1		T8	21		T11	21		T38	21
wkup[60]	385	1		T13	35		T42	26		T22	15
wkup[61]	287	1		T8	30		T36	26		T38	21
wkup[62]	135	1		T157	21		T177	21		T103	30
wkup[63]	406	1		T36	21		T37	21		T27	21
wkup_0	3643	1		T1	5		T2	5		T3	5