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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.36 99.33 93.67 100.00 98.40 99.51 51.27


Total test records in report: 421
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T33 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3714676267 Jul 03 05:55:45 PM PDT 24 Jul 03 05:55:46 PM PDT 24 387016892 ps
T34 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3432110856 Jul 03 05:55:25 PM PDT 24 Jul 03 05:55:27 PM PDT 24 479633386 ps
T283 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.301053429 Jul 03 05:56:01 PM PDT 24 Jul 03 05:56:02 PM PDT 24 338338575 ps
T35 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1815425091 Jul 03 05:55:39 PM PDT 24 Jul 03 05:55:41 PM PDT 24 434599441 ps
T29 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2703015103 Jul 03 05:55:31 PM PDT 24 Jul 03 05:55:36 PM PDT 24 4302587010 ps
T284 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2788904656 Jul 03 05:55:31 PM PDT 24 Jul 03 05:55:33 PM PDT 24 444274436 ps
T285 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.351197547 Jul 03 05:55:40 PM PDT 24 Jul 03 05:55:42 PM PDT 24 322977356 ps
T286 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.324020424 Jul 03 05:55:39 PM PDT 24 Jul 03 05:55:40 PM PDT 24 446418986 ps
T30 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.377417559 Jul 03 05:54:50 PM PDT 24 Jul 03 05:54:51 PM PDT 24 363244422 ps
T71 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2775078088 Jul 03 05:54:30 PM PDT 24 Jul 03 05:54:32 PM PDT 24 1588724763 ps
T287 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1080322307 Jul 03 05:55:11 PM PDT 24 Jul 03 05:55:13 PM PDT 24 505232135 ps
T31 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.350230133 Jul 03 05:54:34 PM PDT 24 Jul 03 05:54:46 PM PDT 24 8372568227 ps
T288 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4268666572 Jul 03 05:55:25 PM PDT 24 Jul 03 05:55:27 PM PDT 24 540182098 ps
T289 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.33908907 Jul 03 05:54:33 PM PDT 24 Jul 03 05:54:35 PM PDT 24 652288162 ps
T290 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.426800350 Jul 03 05:55:21 PM PDT 24 Jul 03 05:55:22 PM PDT 24 518911297 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2389940938 Jul 03 05:55:00 PM PDT 24 Jul 03 05:55:01 PM PDT 24 446928810 ps
T72 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2197766094 Jul 03 05:55:31 PM PDT 24 Jul 03 05:55:33 PM PDT 24 2040341975 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.38931069 Jul 03 05:54:31 PM PDT 24 Jul 03 05:54:32 PM PDT 24 537087485 ps
T57 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.610936555 Jul 03 05:55:43 PM PDT 24 Jul 03 05:55:45 PM PDT 24 356244825 ps
T292 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.793323836 Jul 03 05:55:30 PM PDT 24 Jul 03 05:55:31 PM PDT 24 678630599 ps
T73 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.587054070 Jul 03 05:55:36 PM PDT 24 Jul 03 05:55:39 PM PDT 24 2445547444 ps
T58 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1824442409 Jul 03 05:54:33 PM PDT 24 Jul 03 05:54:36 PM PDT 24 1309329203 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.19125955 Jul 03 05:54:31 PM PDT 24 Jul 03 05:54:32 PM PDT 24 354859512 ps
T293 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2528100474 Jul 03 05:55:42 PM PDT 24 Jul 03 05:55:44 PM PDT 24 530045263 ps
T294 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2031637998 Jul 03 05:55:34 PM PDT 24 Jul 03 05:55:36 PM PDT 24 573033072 ps
T295 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.622389062 Jul 03 05:54:41 PM PDT 24 Jul 03 05:54:43 PM PDT 24 566733843 ps
T296 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3502096493 Jul 03 05:55:52 PM PDT 24 Jul 03 05:55:53 PM PDT 24 284350959 ps
T74 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1098681626 Jul 03 05:54:40 PM PDT 24 Jul 03 05:54:45 PM PDT 24 2452140971 ps
T60 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2507798290 Jul 03 05:55:38 PM PDT 24 Jul 03 05:55:39 PM PDT 24 539217221 ps
T297 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1266040631 Jul 03 05:55:37 PM PDT 24 Jul 03 05:55:38 PM PDT 24 470587610 ps
T75 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1608624316 Jul 03 05:55:41 PM PDT 24 Jul 03 05:55:43 PM PDT 24 1070790710 ps
T298 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3321400659 Jul 03 05:55:42 PM PDT 24 Jul 03 05:55:43 PM PDT 24 406843691 ps
T32 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2454117234 Jul 03 05:55:34 PM PDT 24 Jul 03 05:55:41 PM PDT 24 8790441700 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.267474264 Jul 03 05:55:05 PM PDT 24 Jul 03 05:55:07 PM PDT 24 332920277 ps
T76 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2983342835 Jul 03 05:55:34 PM PDT 24 Jul 03 05:55:38 PM PDT 24 1797435055 ps
T299 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.522827275 Jul 03 05:55:45 PM PDT 24 Jul 03 05:55:46 PM PDT 24 370355225 ps
T300 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2580552553 Jul 03 05:56:05 PM PDT 24 Jul 03 05:56:06 PM PDT 24 340846614 ps
T301 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.961589095 Jul 03 05:55:14 PM PDT 24 Jul 03 05:55:17 PM PDT 24 712686981 ps
T302 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1817670463 Jul 03 05:55:43 PM PDT 24 Jul 03 05:55:45 PM PDT 24 1252445086 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.786518283 Jul 03 05:54:34 PM PDT 24 Jul 03 05:54:35 PM PDT 24 330340984 ps
T304 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.69866480 Jul 03 05:55:45 PM PDT 24 Jul 03 05:55:46 PM PDT 24 348703191 ps
T305 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1913674879 Jul 03 05:55:31 PM PDT 24 Jul 03 05:55:39 PM PDT 24 4410910999 ps
T306 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3969933303 Jul 03 05:54:59 PM PDT 24 Jul 03 05:55:00 PM PDT 24 437735043 ps
T307 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1301097731 Jul 03 05:55:51 PM PDT 24 Jul 03 05:55:52 PM PDT 24 306831339 ps
T199 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1443260042 Jul 03 05:55:39 PM PDT 24 Jul 03 05:55:47 PM PDT 24 4533712532 ps
T308 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1071358493 Jul 03 05:55:57 PM PDT 24 Jul 03 05:55:58 PM PDT 24 555536586 ps
T309 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2520031852 Jul 03 05:55:43 PM PDT 24 Jul 03 05:55:44 PM PDT 24 390906213 ps
T310 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1481770677 Jul 03 05:54:54 PM PDT 24 Jul 03 05:54:55 PM PDT 24 461466071 ps
T311 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1080334299 Jul 03 05:56:00 PM PDT 24 Jul 03 05:56:01 PM PDT 24 541579969 ps
T312 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3060376979 Jul 03 05:55:31 PM PDT 24 Jul 03 05:55:32 PM PDT 24 464964079 ps
T62 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.70983258 Jul 03 05:54:36 PM PDT 24 Jul 03 05:54:39 PM PDT 24 4607662032 ps
T313 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2242185235 Jul 03 05:55:32 PM PDT 24 Jul 03 05:55:33 PM PDT 24 489655036 ps
T198 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.363639958 Jul 03 05:55:03 PM PDT 24 Jul 03 05:55:08 PM PDT 24 8121134079 ps
T314 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2567626176 Jul 03 05:55:23 PM PDT 24 Jul 03 05:55:30 PM PDT 24 3016536040 ps
T66 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4274407331 Jul 03 05:54:39 PM PDT 24 Jul 03 05:54:41 PM PDT 24 573269511 ps
T315 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2852393919 Jul 03 05:54:53 PM PDT 24 Jul 03 05:54:55 PM PDT 24 502933849 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.210410653 Jul 03 05:55:02 PM PDT 24 Jul 03 05:55:04 PM PDT 24 1277012988 ps
T196 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1323543635 Jul 03 05:55:12 PM PDT 24 Jul 03 05:55:19 PM PDT 24 7925520812 ps
T317 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3540749519 Jul 03 05:55:30 PM PDT 24 Jul 03 05:55:31 PM PDT 24 641122388 ps
T318 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3313290845 Jul 03 05:55:57 PM PDT 24 Jul 03 05:55:58 PM PDT 24 322744873 ps
T319 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2775072615 Jul 03 05:56:04 PM PDT 24 Jul 03 05:56:05 PM PDT 24 515684358 ps
T320 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.543596341 Jul 03 05:55:42 PM PDT 24 Jul 03 05:55:45 PM PDT 24 872689336 ps
T321 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2205960708 Jul 03 05:55:48 PM PDT 24 Jul 03 05:55:49 PM PDT 24 474420521 ps
T322 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1805429982 Jul 03 05:55:58 PM PDT 24 Jul 03 05:56:00 PM PDT 24 347635668 ps
T323 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.260268342 Jul 03 05:55:09 PM PDT 24 Jul 03 05:55:10 PM PDT 24 1361586580 ps
T324 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1751536743 Jul 03 05:55:26 PM PDT 24 Jul 03 05:55:28 PM PDT 24 1778542999 ps
T325 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.18991323 Jul 03 05:56:01 PM PDT 24 Jul 03 05:56:01 PM PDT 24 336209795 ps
T197 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.588126762 Jul 03 05:55:02 PM PDT 24 Jul 03 05:55:06 PM PDT 24 8453984262 ps
T326 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.88780415 Jul 03 05:55:52 PM PDT 24 Jul 03 05:55:54 PM PDT 24 302185230 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.843066582 Jul 03 05:54:32 PM PDT 24 Jul 03 05:54:33 PM PDT 24 503443837 ps
T328 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.413544775 Jul 03 05:54:53 PM PDT 24 Jul 03 05:54:55 PM PDT 24 4377726082 ps
T329 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2141815031 Jul 03 05:55:09 PM PDT 24 Jul 03 05:55:10 PM PDT 24 355645228 ps
T330 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2651196004 Jul 03 05:55:43 PM PDT 24 Jul 03 05:55:45 PM PDT 24 607656749 ps
T331 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2613698971 Jul 03 05:55:27 PM PDT 24 Jul 03 05:55:34 PM PDT 24 8375028889 ps
T332 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4147408859 Jul 03 05:55:48 PM PDT 24 Jul 03 05:55:48 PM PDT 24 450577497 ps
T333 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1564820055 Jul 03 05:54:47 PM PDT 24 Jul 03 05:54:48 PM PDT 24 346840540 ps
T334 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2154375787 Jul 03 05:55:45 PM PDT 24 Jul 03 05:55:46 PM PDT 24 557629939 ps
T335 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1317379811 Jul 03 05:54:27 PM PDT 24 Jul 03 05:54:29 PM PDT 24 620920933 ps
T336 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1756005096 Jul 03 05:55:46 PM PDT 24 Jul 03 05:55:47 PM PDT 24 415470985 ps
T337 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.375336258 Jul 03 05:55:53 PM PDT 24 Jul 03 05:55:55 PM PDT 24 415982409 ps
T338 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.270614755 Jul 03 05:55:06 PM PDT 24 Jul 03 05:55:07 PM PDT 24 307832580 ps
T339 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3920915380 Jul 03 05:55:07 PM PDT 24 Jul 03 05:55:09 PM PDT 24 877346652 ps
T340 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3165339417 Jul 03 05:55:43 PM PDT 24 Jul 03 05:55:44 PM PDT 24 348781150 ps
T341 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.341256509 Jul 03 05:55:57 PM PDT 24 Jul 03 05:55:58 PM PDT 24 465839023 ps
T342 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1981138354 Jul 03 05:55:29 PM PDT 24 Jul 03 05:55:29 PM PDT 24 576337431 ps
T343 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1172488361 Jul 03 05:54:41 PM PDT 24 Jul 03 05:54:42 PM PDT 24 415468811 ps
T344 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.716702337 Jul 03 05:55:47 PM PDT 24 Jul 03 05:55:48 PM PDT 24 371713869 ps
T345 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.817658720 Jul 03 05:55:47 PM PDT 24 Jul 03 05:55:54 PM PDT 24 4881269361 ps
T346 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2355831047 Jul 03 05:55:06 PM PDT 24 Jul 03 05:55:08 PM PDT 24 479555944 ps
T347 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.517051660 Jul 03 05:55:15 PM PDT 24 Jul 03 05:55:28 PM PDT 24 8287840407 ps
T348 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4209070607 Jul 03 05:55:57 PM PDT 24 Jul 03 05:55:58 PM PDT 24 285704025 ps
T349 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3295355472 Jul 03 05:55:01 PM PDT 24 Jul 03 05:55:10 PM PDT 24 7026333342 ps
T350 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2959108267 Jul 03 05:55:19 PM PDT 24 Jul 03 05:55:21 PM PDT 24 468011525 ps
T351 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2955067489 Jul 03 05:56:00 PM PDT 24 Jul 03 05:56:01 PM PDT 24 300679458 ps
T352 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3848419119 Jul 03 05:55:26 PM PDT 24 Jul 03 05:55:27 PM PDT 24 481969717 ps
T353 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2486128241 Jul 03 05:56:00 PM PDT 24 Jul 03 05:56:01 PM PDT 24 344060809 ps
T354 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3050906789 Jul 03 05:55:30 PM PDT 24 Jul 03 05:55:33 PM PDT 24 394189422 ps
T355 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2876053311 Jul 03 05:54:49 PM PDT 24 Jul 03 05:54:50 PM PDT 24 468398907 ps
T356 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2806930878 Jul 03 05:55:06 PM PDT 24 Jul 03 05:55:07 PM PDT 24 312260699 ps
T357 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.844571124 Jul 03 05:55:39 PM PDT 24 Jul 03 05:55:41 PM PDT 24 487639036 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2774873340 Jul 03 05:55:03 PM PDT 24 Jul 03 05:55:17 PM PDT 24 6483473726 ps
T358 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1293127262 Jul 03 05:54:58 PM PDT 24 Jul 03 05:54:59 PM PDT 24 378633043 ps
T68 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.978086080 Jul 03 05:55:31 PM PDT 24 Jul 03 05:55:32 PM PDT 24 355955031 ps
T359 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3078608662 Jul 03 05:55:04 PM PDT 24 Jul 03 05:55:05 PM PDT 24 366040890 ps
T360 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.485530362 Jul 03 05:55:06 PM PDT 24 Jul 03 05:55:09 PM PDT 24 401232705 ps
T361 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3031453600 Jul 03 05:55:03 PM PDT 24 Jul 03 05:55:05 PM PDT 24 1353672277 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2279371387 Jul 03 05:54:31 PM PDT 24 Jul 03 05:54:35 PM PDT 24 3670337307 ps
T64 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1128152970 Jul 03 05:55:08 PM PDT 24 Jul 03 05:55:09 PM PDT 24 290456026 ps
T362 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2463995099 Jul 03 05:55:44 PM PDT 24 Jul 03 05:55:45 PM PDT 24 457426932 ps
T363 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1908252685 Jul 03 05:55:26 PM PDT 24 Jul 03 05:55:28 PM PDT 24 538786878 ps
T364 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3258686720 Jul 03 05:55:30 PM PDT 24 Jul 03 05:55:33 PM PDT 24 8962157789 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1380794591 Jul 03 05:55:00 PM PDT 24 Jul 03 05:55:01 PM PDT 24 319266407 ps
T366 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.931854672 Jul 03 05:55:43 PM PDT 24 Jul 03 05:55:44 PM PDT 24 2277084567 ps
T367 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3620790254 Jul 03 05:55:39 PM PDT 24 Jul 03 05:55:41 PM PDT 24 443072812 ps
T368 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.734911576 Jul 03 05:54:50 PM PDT 24 Jul 03 05:54:56 PM PDT 24 2369116865 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1700456695 Jul 03 05:55:06 PM PDT 24 Jul 03 05:55:08 PM PDT 24 370534640 ps
T370 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.66003664 Jul 03 05:55:47 PM PDT 24 Jul 03 05:55:48 PM PDT 24 405505522 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2713846086 Jul 03 05:54:28 PM PDT 24 Jul 03 05:54:29 PM PDT 24 321641022 ps
T372 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4151333779 Jul 03 05:55:11 PM PDT 24 Jul 03 05:55:12 PM PDT 24 564152169 ps
T373 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3319769527 Jul 03 05:55:33 PM PDT 24 Jul 03 05:55:33 PM PDT 24 296623419 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3209631325 Jul 03 05:55:03 PM PDT 24 Jul 03 05:55:07 PM PDT 24 2083391233 ps
T375 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4231607162 Jul 03 05:54:35 PM PDT 24 Jul 03 05:54:36 PM PDT 24 434303033 ps
T376 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2345682262 Jul 03 05:55:02 PM PDT 24 Jul 03 05:55:03 PM PDT 24 492859335 ps
T377 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1485311697 Jul 03 05:55:26 PM PDT 24 Jul 03 05:55:27 PM PDT 24 294533332 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1454111359 Jul 03 05:54:29 PM PDT 24 Jul 03 05:54:30 PM PDT 24 404857344 ps
T379 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3804536581 Jul 03 05:54:42 PM PDT 24 Jul 03 05:54:55 PM PDT 24 8326619930 ps
T380 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2216368263 Jul 03 05:55:41 PM PDT 24 Jul 03 05:55:43 PM PDT 24 490190634 ps
T69 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1378326624 Jul 03 05:55:03 PM PDT 24 Jul 03 05:55:04 PM PDT 24 601517817 ps
T381 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3513852435 Jul 03 05:55:41 PM PDT 24 Jul 03 05:55:43 PM PDT 24 2436501969 ps
T382 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1564400278 Jul 03 05:55:44 PM PDT 24 Jul 03 05:55:45 PM PDT 24 927740032 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.703257641 Jul 03 05:54:51 PM PDT 24 Jul 03 05:54:52 PM PDT 24 463081261 ps
T383 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1924808228 Jul 03 05:55:53 PM PDT 24 Jul 03 05:55:54 PM PDT 24 326439777 ps
T65 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3997798041 Jul 03 05:55:17 PM PDT 24 Jul 03 05:55:19 PM PDT 24 511826058 ps
T384 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.248731845 Jul 03 05:54:50 PM PDT 24 Jul 03 05:54:52 PM PDT 24 1223469244 ps
T385 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1485289772 Jul 03 05:55:38 PM PDT 24 Jul 03 05:55:39 PM PDT 24 549177832 ps
T386 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2408783699 Jul 03 05:55:44 PM PDT 24 Jul 03 05:55:45 PM PDT 24 322919561 ps
T387 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1926626235 Jul 03 05:55:51 PM PDT 24 Jul 03 05:55:52 PM PDT 24 280537513 ps
T388 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2434211677 Jul 03 05:55:11 PM PDT 24 Jul 03 05:55:15 PM PDT 24 2230438943 ps
T389 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1920302561 Jul 03 05:55:48 PM PDT 24 Jul 03 05:55:49 PM PDT 24 344752985 ps
T390 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3281204527 Jul 03 05:54:27 PM PDT 24 Jul 03 05:54:28 PM PDT 24 477780814 ps
T391 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1852553128 Jul 03 05:54:36 PM PDT 24 Jul 03 05:54:37 PM PDT 24 295808112 ps
T392 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2390160355 Jul 03 05:55:16 PM PDT 24 Jul 03 05:55:18 PM PDT 24 556207117 ps
T393 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3841969028 Jul 03 05:55:46 PM PDT 24 Jul 03 05:55:48 PM PDT 24 472665958 ps
T394 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1520165991 Jul 03 05:54:28 PM PDT 24 Jul 03 05:54:30 PM PDT 24 1462598523 ps
T395 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1159435838 Jul 03 05:55:45 PM PDT 24 Jul 03 05:55:48 PM PDT 24 864224236 ps
T396 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3733948404 Jul 03 05:55:08 PM PDT 24 Jul 03 05:55:09 PM PDT 24 472256875 ps
T397 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3093016388 Jul 03 05:55:30 PM PDT 24 Jul 03 05:55:31 PM PDT 24 385222211 ps
T398 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1173510305 Jul 03 05:54:27 PM PDT 24 Jul 03 05:54:31 PM PDT 24 8131660349 ps
T399 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3786323905 Jul 03 05:55:13 PM PDT 24 Jul 03 05:55:14 PM PDT 24 617614783 ps
T400 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4264951383 Jul 03 05:55:47 PM PDT 24 Jul 03 05:55:48 PM PDT 24 287624715 ps
T401 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1867204455 Jul 03 05:55:20 PM PDT 24 Jul 03 05:55:25 PM PDT 24 8225641001 ps
T402 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1750906176 Jul 03 05:55:08 PM PDT 24 Jul 03 05:55:09 PM PDT 24 337318605 ps
T403 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3126190471 Jul 03 05:56:00 PM PDT 24 Jul 03 05:56:01 PM PDT 24 419898002 ps
T404 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1182191454 Jul 03 05:55:43 PM PDT 24 Jul 03 05:55:47 PM PDT 24 8652363493 ps
T405 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3816431559 Jul 03 05:56:00 PM PDT 24 Jul 03 05:56:02 PM PDT 24 423620261 ps
T406 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1436229626 Jul 03 05:54:50 PM PDT 24 Jul 03 05:55:02 PM PDT 24 14100510804 ps
T407 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4021126093 Jul 03 05:55:20 PM PDT 24 Jul 03 05:55:21 PM PDT 24 428581685 ps
T408 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.360517065 Jul 03 05:54:49 PM PDT 24 Jul 03 05:54:50 PM PDT 24 309595289 ps
T409 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.919539723 Jul 03 05:55:34 PM PDT 24 Jul 03 05:55:35 PM PDT 24 508848316 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.130321555 Jul 03 05:54:36 PM PDT 24 Jul 03 05:54:37 PM PDT 24 303281372 ps
T411 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4181701826 Jul 03 05:55:29 PM PDT 24 Jul 03 05:55:30 PM PDT 24 648601752 ps
T412 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4019736127 Jul 03 05:55:54 PM PDT 24 Jul 03 05:55:56 PM PDT 24 491723519 ps
T413 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3144247800 Jul 03 05:55:01 PM PDT 24 Jul 03 05:55:04 PM PDT 24 1319289048 ps
T414 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2571816259 Jul 03 05:55:41 PM PDT 24 Jul 03 05:55:43 PM PDT 24 4864240057 ps
T415 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.304108947 Jul 03 05:55:40 PM PDT 24 Jul 03 05:55:44 PM PDT 24 9010347173 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3587353566 Jul 03 05:55:04 PM PDT 24 Jul 03 05:55:05 PM PDT 24 732484461 ps
T417 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1905658922 Jul 03 05:55:10 PM PDT 24 Jul 03 05:55:10 PM PDT 24 350821476 ps
T418 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1418174804 Jul 03 05:55:27 PM PDT 24 Jul 03 05:55:28 PM PDT 24 1166017298 ps
T419 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.451662518 Jul 03 05:55:07 PM PDT 24 Jul 03 05:55:13 PM PDT 24 7765799185 ps
T420 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1229512646 Jul 03 05:55:33 PM PDT 24 Jul 03 05:55:35 PM PDT 24 519938259 ps
T421 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2252405852 Jul 03 05:55:55 PM PDT 24 Jul 03 05:55:56 PM PDT 24 428037602 ps

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1544957034
Short name T8
Test name
Test status
Simulation time 92645926789 ps
CPU time 754.07 seconds
Started Jul 03 05:47:15 PM PDT 24
Finished Jul 03 05:59:50 PM PDT 24
Peak memory 207336 kb
Host smart-14d3885a-4483-4b26-9d4a-d81b27d63ae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544957034 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1544957034
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.4223680719
Short name T1
Test name
Test status
Simulation time 78487438386 ps
CPU time 54.01 seconds
Started Jul 03 05:46:57 PM PDT 24
Finished Jul 03 05:47:51 PM PDT 24
Peak memory 198072 kb
Host smart-8beea344-6763-4510-8bfb-330637e32677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223680719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.4223680719
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2703015103
Short name T29
Test name
Test status
Simulation time 4302587010 ps
CPU time 4 seconds
Started Jul 03 05:55:31 PM PDT 24
Finished Jul 03 05:55:36 PM PDT 24
Peak memory 197800 kb
Host smart-fe063da7-22e6-4a8f-88fd-88262bccc86a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703015103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2703015103
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1165270374
Short name T95
Test name
Test status
Simulation time 30916897578 ps
CPU time 214.44 seconds
Started Jul 03 05:46:27 PM PDT 24
Finished Jul 03 05:50:03 PM PDT 24
Peak memory 213816 kb
Host smart-34cc67f6-c08a-48a0-8777-56d0feadc4e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165270374 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1165270374
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2604007869
Short name T109
Test name
Test status
Simulation time 194332975274 ps
CPU time 582.5 seconds
Started Jul 03 05:46:55 PM PDT 24
Finished Jul 03 05:56:38 PM PDT 24
Peak memory 205324 kb
Host smart-ab975dfe-01ac-4e3d-8f24-036efd8c58a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604007869 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2604007869
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1543023073
Short name T46
Test name
Test status
Simulation time 156204955313 ps
CPU time 659.68 seconds
Started Jul 03 05:46:56 PM PDT 24
Finished Jul 03 05:57:56 PM PDT 24
Peak memory 206636 kb
Host smart-4ce6b56a-6554-4eda-8f73-81f93c9ac849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543023073 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1543023073
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.4188588378
Short name T162
Test name
Test status
Simulation time 75486752888 ps
CPU time 794.7 seconds
Started Jul 03 05:46:49 PM PDT 24
Finished Jul 03 06:00:04 PM PDT 24
Peak memory 214888 kb
Host smart-87f0d005-53d9-4ffe-ac9c-04c63584f5b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188588378 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.4188588378
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2679460399
Short name T106
Test name
Test status
Simulation time 79297122940 ps
CPU time 411.36 seconds
Started Jul 03 05:47:02 PM PDT 24
Finished Jul 03 05:53:53 PM PDT 24
Peak memory 206524 kb
Host smart-7fae390e-ea59-44a4-b6a0-b0bd11324065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679460399 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2679460399
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1782649313
Short name T4
Test name
Test status
Simulation time 675967233826 ps
CPU time 531.25 seconds
Started Jul 03 05:46:26 PM PDT 24
Finished Jul 03 05:55:18 PM PDT 24
Peak memory 206608 kb
Host smart-839f870c-dbbf-40fa-8b93-e7dedaa80807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782649313 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1782649313
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2472254643
Short name T13
Test name
Test status
Simulation time 316918953219 ps
CPU time 215.05 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 05:50:29 PM PDT 24
Peak memory 200332 kb
Host smart-75ad4314-12d5-431d-9d36-20f95d9f507c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472254643 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2472254643
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3749955897
Short name T37
Test name
Test status
Simulation time 119307911163 ps
CPU time 372.81 seconds
Started Jul 03 05:46:43 PM PDT 24
Finished Jul 03 05:52:56 PM PDT 24
Peak memory 211028 kb
Host smart-22be9c77-7b5c-41e7-b6b0-e28128c5eee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749955897 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3749955897
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.325781367
Short name T119
Test name
Test status
Simulation time 63451205429 ps
CPU time 284.27 seconds
Started Jul 03 05:47:02 PM PDT 24
Finished Jul 03 05:51:46 PM PDT 24
Peak memory 214836 kb
Host smart-19702063-d075-4cf8-9cbc-4d42a385695f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325781367 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.325781367
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.112833172
Short name T16
Test name
Test status
Simulation time 7627605857 ps
CPU time 3.27 seconds
Started Jul 03 05:46:22 PM PDT 24
Finished Jul 03 05:46:26 PM PDT 24
Peak memory 215800 kb
Host smart-e548d5a3-0de6-4959-8451-c0153fb7a255
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112833172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.112833172
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3893615619
Short name T89
Test name
Test status
Simulation time 218896727680 ps
CPU time 361.31 seconds
Started Jul 03 05:46:47 PM PDT 24
Finished Jul 03 05:52:49 PM PDT 24
Peak memory 202048 kb
Host smart-a43de7bf-3405-48ad-a8bf-5284834699e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893615619 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3893615619
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3657862130
Short name T27
Test name
Test status
Simulation time 36721381308 ps
CPU time 376.49 seconds
Started Jul 03 05:47:04 PM PDT 24
Finished Jul 03 05:53:21 PM PDT 24
Peak memory 199144 kb
Host smart-6d6a8fbc-9121-41ea-ad21-58cf5bff1c88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657862130 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3657862130
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2734046478
Short name T87
Test name
Test status
Simulation time 47252835467 ps
CPU time 339.91 seconds
Started Jul 03 05:47:04 PM PDT 24
Finished Jul 03 05:52:44 PM PDT 24
Peak memory 199172 kb
Host smart-b5cd4644-7171-4ce4-bb8b-e73f8a50a75d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734046478 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2734046478
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1952659988
Short name T113
Test name
Test status
Simulation time 28227399039 ps
CPU time 40.05 seconds
Started Jul 03 05:47:16 PM PDT 24
Finished Jul 03 05:47:56 PM PDT 24
Peak memory 192804 kb
Host smart-4f3e5488-94f5-4fb4-acf6-60aa1480ec9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952659988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1952659988
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3633470742
Short name T104
Test name
Test status
Simulation time 134441206539 ps
CPU time 391.99 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:53:42 PM PDT 24
Peak memory 213704 kb
Host smart-16c45340-754f-4f7c-9b71-e683fbf31a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633470742 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3633470742
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3696524044
Short name T110
Test name
Test status
Simulation time 167906810536 ps
CPU time 57.12 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:48:07 PM PDT 24
Peak memory 191632 kb
Host smart-d8fde3a0-53d9-42fa-84f5-45bbcdce5b71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696524044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3696524044
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3019484185
Short name T36
Test name
Test status
Simulation time 42618842251 ps
CPU time 300.22 seconds
Started Jul 03 05:47:08 PM PDT 24
Finished Jul 03 05:52:09 PM PDT 24
Peak memory 198448 kb
Host smart-e9cba7f5-35f4-4016-9462-64aa9a5602ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019484185 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3019484185
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.643889158
Short name T143
Test name
Test status
Simulation time 347156692346 ps
CPU time 185.76 seconds
Started Jul 03 05:46:30 PM PDT 24
Finished Jul 03 05:49:36 PM PDT 24
Peak memory 199980 kb
Host smart-77ce47e1-160a-40b6-b083-664bc34aa682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643889158 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.643889158
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3835011647
Short name T114
Test name
Test status
Simulation time 43452322750 ps
CPU time 67.23 seconds
Started Jul 03 05:46:39 PM PDT 24
Finished Jul 03 05:47:46 PM PDT 24
Peak memory 197948 kb
Host smart-1dad03ad-6d21-4e90-a995-76dd9990d854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835011647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3835011647
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.683359259
Short name T103
Test name
Test status
Simulation time 44942967536 ps
CPU time 347.94 seconds
Started Jul 03 05:46:47 PM PDT 24
Finished Jul 03 05:52:35 PM PDT 24
Peak memory 207176 kb
Host smart-42f56650-7d7a-4689-87c1-34beab3cf0fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683359259 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.683359259
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.258345854
Short name T52
Test name
Test status
Simulation time 273386381368 ps
CPU time 186.36 seconds
Started Jul 03 05:46:50 PM PDT 24
Finished Jul 03 05:49:56 PM PDT 24
Peak memory 192844 kb
Host smart-05d83327-cb0c-4923-bf9b-42ca419686d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258345854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.258345854
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.466837049
Short name T130
Test name
Test status
Simulation time 39508781165 ps
CPU time 314.28 seconds
Started Jul 03 05:47:16 PM PDT 24
Finished Jul 03 05:52:30 PM PDT 24
Peak memory 214704 kb
Host smart-ebc44b1d-4e0a-4015-b67b-d8e95616337d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466837049 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.466837049
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1942628566
Short name T105
Test name
Test status
Simulation time 140857229285 ps
CPU time 39.73 seconds
Started Jul 03 05:46:53 PM PDT 24
Finished Jul 03 05:47:33 PM PDT 24
Peak memory 198100 kb
Host smart-28f18656-a5f7-478c-afa7-0167a0176090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942628566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1942628566
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2830562310
Short name T157
Test name
Test status
Simulation time 335092385273 ps
CPU time 263.26 seconds
Started Jul 03 05:46:20 PM PDT 24
Finished Jul 03 05:50:44 PM PDT 24
Peak memory 192432 kb
Host smart-92b0b138-26e1-4ad9-bdd3-ef1fa2932311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830562310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2830562310
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3819305439
Short name T158
Test name
Test status
Simulation time 165430468675 ps
CPU time 220.68 seconds
Started Jul 03 05:47:06 PM PDT 24
Finished Jul 03 05:50:47 PM PDT 24
Peak memory 191696 kb
Host smart-809e08f0-39f6-45b9-a334-2d2d894a0084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819305439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3819305439
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1702991277
Short name T90
Test name
Test status
Simulation time 767516800112 ps
CPU time 420.11 seconds
Started Jul 03 05:46:34 PM PDT 24
Finished Jul 03 05:53:35 PM PDT 24
Peak memory 214796 kb
Host smart-42224936-38a4-4b22-a316-9dfd7f512840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702991277 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1702991277
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3953403246
Short name T40
Test name
Test status
Simulation time 170957654959 ps
CPU time 801.22 seconds
Started Jul 03 05:46:32 PM PDT 24
Finished Jul 03 05:59:54 PM PDT 24
Peak memory 214764 kb
Host smart-a6350838-fc28-486a-9dd6-6c2a86756338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953403246 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3953403246
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1478559101
Short name T155
Test name
Test status
Simulation time 267421406340 ps
CPU time 93.53 seconds
Started Jul 03 05:47:13 PM PDT 24
Finished Jul 03 05:48:47 PM PDT 24
Peak memory 193028 kb
Host smart-5075bc96-d438-4c1b-8438-60c1d008d250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478559101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1478559101
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.4014164700
Short name T133
Test name
Test status
Simulation time 67487138550 ps
CPU time 264.57 seconds
Started Jul 03 05:47:15 PM PDT 24
Finished Jul 03 05:51:40 PM PDT 24
Peak memory 207916 kb
Host smart-cdf9e38f-825e-4035-8674-f3c280a68a9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014164700 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.4014164700
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2279371387
Short name T63
Test name
Test status
Simulation time 3670337307 ps
CPU time 3.24 seconds
Started Jul 03 05:54:31 PM PDT 24
Finished Jul 03 05:54:35 PM PDT 24
Peak memory 192228 kb
Host smart-48cb4d02-138b-4d73-9cb3-6afb5f8126a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279371387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2279371387
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2877768313
Short name T48
Test name
Test status
Simulation time 329168097286 ps
CPU time 103.62 seconds
Started Jul 03 05:47:02 PM PDT 24
Finished Jul 03 05:48:46 PM PDT 24
Peak memory 192748 kb
Host smart-637ffac7-ff3c-46ff-a6d1-0744d9593a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877768313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2877768313
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2954895228
Short name T128
Test name
Test status
Simulation time 102367295119 ps
CPU time 32.28 seconds
Started Jul 03 05:46:52 PM PDT 24
Finished Jul 03 05:47:24 PM PDT 24
Peak memory 193064 kb
Host smart-de6373aa-a5ca-4c8f-8697-8c6e3df06525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954895228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2954895228
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2599867104
Short name T127
Test name
Test status
Simulation time 332962617564 ps
CPU time 159.9 seconds
Started Jul 03 05:46:26 PM PDT 24
Finished Jul 03 05:49:07 PM PDT 24
Peak memory 191748 kb
Host smart-57c553f0-099b-490b-bd7e-912af18c0c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599867104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2599867104
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3773806280
Short name T139
Test name
Test status
Simulation time 185424316949 ps
CPU time 273.75 seconds
Started Jul 03 05:46:46 PM PDT 24
Finished Jul 03 05:51:20 PM PDT 24
Peak memory 192784 kb
Host smart-ac3b962c-8240-4130-b4a4-4eabba2ec96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773806280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3773806280
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1719494203
Short name T92
Test name
Test status
Simulation time 203426157775 ps
CPU time 436.96 seconds
Started Jul 03 05:46:29 PM PDT 24
Finished Jul 03 05:53:46 PM PDT 24
Peak memory 203480 kb
Host smart-b9f38ed8-a813-4b39-8cef-874b78b6366f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719494203 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1719494203
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2278756372
Short name T24
Test name
Test status
Simulation time 47626826067 ps
CPU time 277.2 seconds
Started Jul 03 05:46:16 PM PDT 24
Finished Jul 03 05:50:53 PM PDT 24
Peak memory 198832 kb
Host smart-042dca78-3e1c-49f8-a46d-da6cfd11d162
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278756372 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2278756372
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1861174325
Short name T122
Test name
Test status
Simulation time 72005189830 ps
CPU time 61.27 seconds
Started Jul 03 05:46:52 PM PDT 24
Finished Jul 03 05:47:54 PM PDT 24
Peak memory 197992 kb
Host smart-a73bd892-6256-4d93-b8f7-3bc03e7fe42f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861174325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1861174325
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1907822166
Short name T39
Test name
Test status
Simulation time 253660189051 ps
CPU time 545.58 seconds
Started Jul 03 05:46:38 PM PDT 24
Finished Jul 03 05:55:44 PM PDT 24
Peak memory 212624 kb
Host smart-1de1ccb3-a660-48eb-8a5c-ce797568f6d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907822166 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1907822166
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1018878347
Short name T53
Test name
Test status
Simulation time 31173204121 ps
CPU time 168.27 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:49:58 PM PDT 24
Peak memory 214060 kb
Host smart-4ec5ec7e-655d-4139-bfc8-dd9bfec92cf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018878347 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1018878347
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1760323856
Short name T121
Test name
Test status
Simulation time 51207367067 ps
CPU time 14.28 seconds
Started Jul 03 05:47:12 PM PDT 24
Finished Jul 03 05:47:27 PM PDT 24
Peak memory 198076 kb
Host smart-0170f2b1-b806-4f95-a17d-6ca136e22725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760323856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1760323856
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2970770250
Short name T175
Test name
Test status
Simulation time 237554651702 ps
CPU time 867.12 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 06:01:21 PM PDT 24
Peak memory 214688 kb
Host smart-300164dc-05e1-45b2-919d-cbee2505c8aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970770250 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2970770250
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.47843432
Short name T144
Test name
Test status
Simulation time 71589484194 ps
CPU time 44.56 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:47:54 PM PDT 24
Peak memory 191680 kb
Host smart-9a8fe72b-8712-492d-9f15-ab7a49e1d943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47843432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_al
l.47843432
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.88312239
Short name T93
Test name
Test status
Simulation time 54980935549 ps
CPU time 172.77 seconds
Started Jul 03 05:46:19 PM PDT 24
Finished Jul 03 05:49:12 PM PDT 24
Peak memory 206604 kb
Host smart-cb1be065-9821-4478-a49a-eacdb0198baa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88312239 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.88312239
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1713406018
Short name T120
Test name
Test status
Simulation time 73184276603 ps
CPU time 24.89 seconds
Started Jul 03 05:47:08 PM PDT 24
Finished Jul 03 05:47:33 PM PDT 24
Peak memory 191732 kb
Host smart-c5d712e9-aec9-4ced-997b-f61910aed0c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713406018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1713406018
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4038537153
Short name T25
Test name
Test status
Simulation time 64960432166 ps
CPU time 93.5 seconds
Started Jul 03 05:46:34 PM PDT 24
Finished Jul 03 05:48:08 PM PDT 24
Peak memory 191808 kb
Host smart-8b52568c-8dd8-432f-9a36-a34a550e980a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038537153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4038537153
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3574946284
Short name T115
Test name
Test status
Simulation time 75968322628 ps
CPU time 117.86 seconds
Started Jul 03 05:46:56 PM PDT 24
Finished Jul 03 05:48:55 PM PDT 24
Peak memory 191732 kb
Host smart-27ebdd3c-3ca9-4000-af07-a77c3af7bb51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574946284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3574946284
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2350528140
Short name T132
Test name
Test status
Simulation time 232461580866 ps
CPU time 335.38 seconds
Started Jul 03 05:46:26 PM PDT 24
Finished Jul 03 05:52:02 PM PDT 24
Peak memory 197996 kb
Host smart-d359ecb9-3318-4ca8-ac75-c5f699b324df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350528140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2350528140
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1839762751
Short name T44
Test name
Test status
Simulation time 62876909414 ps
CPU time 90.13 seconds
Started Jul 03 05:47:04 PM PDT 24
Finished Jul 03 05:48:34 PM PDT 24
Peak memory 184008 kb
Host smart-5a8b7e16-2dee-43cf-b0cc-bc6ee102ef11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839762751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1839762751
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2026162087
Short name T9
Test name
Test status
Simulation time 281214499195 ps
CPU time 81.16 seconds
Started Jul 03 05:46:58 PM PDT 24
Finished Jul 03 05:48:19 PM PDT 24
Peak memory 197872 kb
Host smart-5d20a3e3-2883-4240-8a4d-14f42dcaa9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026162087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2026162087
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3172174968
Short name T152
Test name
Test status
Simulation time 96807423642 ps
CPU time 132.82 seconds
Started Jul 03 05:46:23 PM PDT 24
Finished Jul 03 05:48:37 PM PDT 24
Peak memory 192788 kb
Host smart-491003de-af84-4762-af29-fc5e6ca815c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172174968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3172174968
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4048798969
Short name T166
Test name
Test status
Simulation time 307616638967 ps
CPU time 284.45 seconds
Started Jul 03 05:47:14 PM PDT 24
Finished Jul 03 05:51:59 PM PDT 24
Peak memory 209144 kb
Host smart-4365f2d8-2dbc-4bc3-a6fe-c84d07afe6ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048798969 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4048798969
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.742176200
Short name T124
Test name
Test status
Simulation time 73133548647 ps
CPU time 56.77 seconds
Started Jul 03 05:46:45 PM PDT 24
Finished Jul 03 05:47:42 PM PDT 24
Peak memory 192816 kb
Host smart-1c01d779-a3f8-4061-89cf-6fbfa30d3425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742176200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.742176200
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.949668099
Short name T138
Test name
Test status
Simulation time 44300642217 ps
CPU time 358.3 seconds
Started Jul 03 05:46:52 PM PDT 24
Finished Jul 03 05:52:51 PM PDT 24
Peak memory 206612 kb
Host smart-0ed58444-4eef-4230-8b71-0b84cc598a86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949668099 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.949668099
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4279312995
Short name T94
Test name
Test status
Simulation time 88665793931 ps
CPU time 402.06 seconds
Started Jul 03 05:46:58 PM PDT 24
Finished Jul 03 05:53:41 PM PDT 24
Peak memory 206604 kb
Host smart-4a3bb155-22ac-41de-826b-8c18ba394f14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279312995 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4279312995
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1558771180
Short name T161
Test name
Test status
Simulation time 270452270414 ps
CPU time 93.53 seconds
Started Jul 03 05:47:02 PM PDT 24
Finished Jul 03 05:48:36 PM PDT 24
Peak memory 192808 kb
Host smart-df3a8d47-8df9-4ecc-98c9-3b4dd29c908b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558771180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1558771180
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3007038739
Short name T85
Test name
Test status
Simulation time 407185699253 ps
CPU time 237.07 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 05:50:51 PM PDT 24
Peak memory 208312 kb
Host smart-486a817c-48c4-4f7f-b22c-ddc088d1da9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007038739 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3007038739
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3575841412
Short name T146
Test name
Test status
Simulation time 25146173197 ps
CPU time 110.56 seconds
Started Jul 03 05:46:28 PM PDT 24
Finished Jul 03 05:48:20 PM PDT 24
Peak memory 214864 kb
Host smart-0ed6b44d-0bed-4ea0-b033-03d9aece1d0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575841412 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3575841412
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.19125955
Short name T59
Test name
Test status
Simulation time 354859512 ps
CPU time 0.8 seconds
Started Jul 03 05:54:31 PM PDT 24
Finished Jul 03 05:54:32 PM PDT 24
Peak memory 193028 kb
Host smart-7185cb40-663a-432e-8a4f-8acafb25aadf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19125955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.19125955
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2109854506
Short name T125
Test name
Test status
Simulation time 4261429838 ps
CPU time 4.78 seconds
Started Jul 03 05:46:19 PM PDT 24
Finished Jul 03 05:46:24 PM PDT 24
Peak memory 198060 kb
Host smart-512a1a94-c588-41dd-8ade-2318ea6c1154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109854506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2109854506
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.4108290514
Short name T81
Test name
Test status
Simulation time 72990527669 ps
CPU time 44.45 seconds
Started Jul 03 05:46:57 PM PDT 24
Finished Jul 03 05:47:42 PM PDT 24
Peak memory 191672 kb
Host smart-54baef74-1df0-4e9d-892a-b6391f66c2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108290514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.4108290514
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2556539356
Short name T86
Test name
Test status
Simulation time 290835585436 ps
CPU time 1115.16 seconds
Started Jul 03 05:47:03 PM PDT 24
Finished Jul 03 06:05:39 PM PDT 24
Peak memory 214824 kb
Host smart-618000c9-6fec-45c7-ba53-949951a6d032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556539356 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2556539356
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.419072859
Short name T101
Test name
Test status
Simulation time 107756379232 ps
CPU time 69.38 seconds
Started Jul 03 05:46:28 PM PDT 24
Finished Jul 03 05:47:38 PM PDT 24
Peak memory 192320 kb
Host smart-9e21cab5-edb2-4b29-9845-34217c591628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419072859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.419072859
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3820347463
Short name T154
Test name
Test status
Simulation time 274995784473 ps
CPU time 201.08 seconds
Started Jul 03 05:46:41 PM PDT 24
Finished Jul 03 05:50:02 PM PDT 24
Peak memory 192468 kb
Host smart-5377a676-c437-4bdd-ad78-55636e53458e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820347463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3820347463
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3219697164
Short name T141
Test name
Test status
Simulation time 208268947593 ps
CPU time 83.44 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:48:32 PM PDT 24
Peak memory 198088 kb
Host smart-dffb50c7-d93e-4afd-a82f-22418d974ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219697164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3219697164
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.374060274
Short name T88
Test name
Test status
Simulation time 81224205112 ps
CPU time 314.99 seconds
Started Jul 03 05:47:18 PM PDT 24
Finished Jul 03 05:52:34 PM PDT 24
Peak memory 209068 kb
Host smart-7990040b-8f01-47a3-bf24-5a82a325c137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374060274 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.374060274
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3064961322
Short name T51
Test name
Test status
Simulation time 200947787092 ps
CPU time 296.6 seconds
Started Jul 03 05:46:19 PM PDT 24
Finished Jul 03 05:51:16 PM PDT 24
Peak memory 192188 kb
Host smart-83487289-84f4-45df-afd0-7738544e9302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064961322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3064961322
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2076596129
Short name T22
Test name
Test status
Simulation time 427479210 ps
CPU time 0.7 seconds
Started Jul 03 05:46:56 PM PDT 24
Finished Jul 03 05:46:57 PM PDT 24
Peak memory 196484 kb
Host smart-60729c8a-3d2a-42c7-ae44-72479f21ee64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076596129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2076596129
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3198893483
Short name T2
Test name
Test status
Simulation time 158050107718 ps
CPU time 57.99 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:48:08 PM PDT 24
Peak memory 192720 kb
Host smart-634bd9cf-dbb8-47e0-8bbe-94ef7846a089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198893483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3198893483
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3690090871
Short name T153
Test name
Test status
Simulation time 439795705 ps
CPU time 0.7 seconds
Started Jul 03 05:46:20 PM PDT 24
Finished Jul 03 05:46:21 PM PDT 24
Peak memory 196496 kb
Host smart-8a2b7675-b3ee-47f4-974e-b41780d1bdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690090871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3690090871
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.733460291
Short name T184
Test name
Test status
Simulation time 394653535363 ps
CPU time 135.83 seconds
Started Jul 03 05:46:34 PM PDT 24
Finished Jul 03 05:48:50 PM PDT 24
Peak memory 192856 kb
Host smart-1f9e91e4-28aa-4928-ab28-dcac7ba7600d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733460291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.733460291
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.237932376
Short name T91
Test name
Test status
Simulation time 33472538490 ps
CPU time 243.44 seconds
Started Jul 03 05:47:00 PM PDT 24
Finished Jul 03 05:51:04 PM PDT 24
Peak memory 206660 kb
Host smart-a9ea8e45-604f-4f99-b161-607ba31f7999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237932376 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.237932376
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3193358921
Short name T42
Test name
Test status
Simulation time 97157659399 ps
CPU time 45.31 seconds
Started Jul 03 05:47:00 PM PDT 24
Finished Jul 03 05:47:46 PM PDT 24
Peak memory 192320 kb
Host smart-528eed48-5594-4216-ae78-c496c147b499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193358921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3193358921
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2742176748
Short name T112
Test name
Test status
Simulation time 157600297718 ps
CPU time 44.36 seconds
Started Jul 03 05:47:16 PM PDT 24
Finished Jul 03 05:48:01 PM PDT 24
Peak memory 192832 kb
Host smart-c6342fa2-b85c-451d-bbaa-76e5a1c3162d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742176748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2742176748
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2564275394
Short name T136
Test name
Test status
Simulation time 137627577378 ps
CPU time 42.08 seconds
Started Jul 03 05:46:42 PM PDT 24
Finished Jul 03 05:47:25 PM PDT 24
Peak memory 191716 kb
Host smart-da5e35ad-dec3-4546-b912-3ce309023af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564275394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2564275394
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2478699202
Short name T134
Test name
Test status
Simulation time 33431218789 ps
CPU time 282.73 seconds
Started Jul 03 05:46:50 PM PDT 24
Finished Jul 03 05:51:34 PM PDT 24
Peak memory 206632 kb
Host smart-5ef2e7d9-62bf-41a1-a2a9-fb638c40cf25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478699202 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2478699202
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1422839074
Short name T147
Test name
Test status
Simulation time 583917153 ps
CPU time 1 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 05:46:55 PM PDT 24
Peak memory 196540 kb
Host smart-7e938e05-7eb1-4f0f-a96e-92d7844a98d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422839074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1422839074
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2226622490
Short name T142
Test name
Test status
Simulation time 276357531747 ps
CPU time 102.8 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:48:53 PM PDT 24
Peak memory 198056 kb
Host smart-6c1995cb-914d-4ed1-9bff-b2867883fa0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226622490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2226622490
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3980608818
Short name T107
Test name
Test status
Simulation time 530907405 ps
CPU time 1.38 seconds
Started Jul 03 05:47:14 PM PDT 24
Finished Jul 03 05:47:15 PM PDT 24
Peak memory 196544 kb
Host smart-bcd8404b-fce5-4dd0-8117-95c1c28ed48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980608818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3980608818
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.857329980
Short name T117
Test name
Test status
Simulation time 579886837 ps
CPU time 0.93 seconds
Started Jul 03 05:47:12 PM PDT 24
Finished Jul 03 05:47:13 PM PDT 24
Peak memory 196592 kb
Host smart-d3377659-96c8-4a8d-beb2-562d61e194fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857329980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.857329980
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.899319261
Short name T135
Test name
Test status
Simulation time 579123874 ps
CPU time 0.99 seconds
Started Jul 03 05:46:28 PM PDT 24
Finished Jul 03 05:46:29 PM PDT 24
Peak memory 196556 kb
Host smart-3d2fd1fe-0b8d-4a02-b93a-4464f956916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899319261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.899319261
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1661999473
Short name T3
Test name
Test status
Simulation time 91853213331 ps
CPU time 124.6 seconds
Started Jul 03 05:46:37 PM PDT 24
Finished Jul 03 05:48:42 PM PDT 24
Peak memory 192796 kb
Host smart-9c6a2a99-8a76-4cfd-a929-01902dcd798f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661999473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1661999473
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3813886021
Short name T116
Test name
Test status
Simulation time 530796388 ps
CPU time 0.97 seconds
Started Jul 03 05:46:42 PM PDT 24
Finished Jul 03 05:46:44 PM PDT 24
Peak memory 196556 kb
Host smart-a713f2a5-04e5-4090-9729-94c897c735f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813886021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3813886021
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.387863893
Short name T11
Test name
Test status
Simulation time 50399539000 ps
CPU time 10.02 seconds
Started Jul 03 05:46:50 PM PDT 24
Finished Jul 03 05:47:01 PM PDT 24
Peak memory 192792 kb
Host smart-b481f919-caa5-4475-ba75-29e04f9c44b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387863893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.387863893
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3908132667
Short name T108
Test name
Test status
Simulation time 544769706 ps
CPU time 0.79 seconds
Started Jul 03 05:46:53 PM PDT 24
Finished Jul 03 05:46:54 PM PDT 24
Peak memory 196472 kb
Host smart-7adcebc9-dfda-4a0a-9374-7d323a8fa44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908132667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3908132667
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1329775011
Short name T131
Test name
Test status
Simulation time 412291809 ps
CPU time 0.76 seconds
Started Jul 03 05:47:01 PM PDT 24
Finished Jul 03 05:47:02 PM PDT 24
Peak memory 196456 kb
Host smart-3aedbc79-c375-480f-b1f2-22d73619895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329775011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1329775011
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3923606063
Short name T38
Test name
Test status
Simulation time 20477876778 ps
CPU time 158.26 seconds
Started Jul 03 05:47:01 PM PDT 24
Finished Jul 03 05:49:40 PM PDT 24
Peak memory 206588 kb
Host smart-4ccff160-dc95-4ba7-bc3f-533edb95314a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923606063 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3923606063
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1740626062
Short name T168
Test name
Test status
Simulation time 470323571968 ps
CPU time 349.36 seconds
Started Jul 03 05:47:00 PM PDT 24
Finished Jul 03 05:52:50 PM PDT 24
Peak memory 198104 kb
Host smart-3bb906b8-d363-47e3-b107-3e31d7a70967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740626062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1740626062
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.322532641
Short name T150
Test name
Test status
Simulation time 502966128 ps
CPU time 1.2 seconds
Started Jul 03 05:47:01 PM PDT 24
Finished Jul 03 05:47:02 PM PDT 24
Peak memory 196580 kb
Host smart-2cd71a2b-2d78-4a4b-8208-cc2e350429da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322532641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.322532641
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.578554964
Short name T19
Test name
Test status
Simulation time 524830624 ps
CPU time 1.37 seconds
Started Jul 03 05:47:15 PM PDT 24
Finished Jul 03 05:47:17 PM PDT 24
Peak memory 196568 kb
Host smart-9b16ad0d-ba14-4654-abaa-e391c87bdf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578554964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.578554964
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1770471
Short name T169
Test name
Test status
Simulation time 390386918636 ps
CPU time 559.51 seconds
Started Jul 03 05:46:30 PM PDT 24
Finished Jul 03 05:55:50 PM PDT 24
Peak memory 191736 kb
Host smart-a6109880-6628-4f6c-96b2-3347215a6de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.1770471
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1246784035
Short name T189
Test name
Test status
Simulation time 22864658001 ps
CPU time 85.82 seconds
Started Jul 03 05:46:36 PM PDT 24
Finished Jul 03 05:48:02 PM PDT 24
Peak memory 214172 kb
Host smart-27954516-10d3-41c7-91bd-a642a7fe76e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246784035 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1246784035
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3887905613
Short name T23
Test name
Test status
Simulation time 424640916 ps
CPU time 1.17 seconds
Started Jul 03 05:46:36 PM PDT 24
Finished Jul 03 05:46:38 PM PDT 24
Peak memory 196556 kb
Host smart-6109c703-b021-4003-a41e-d2c49d0d2d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887905613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3887905613
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2267066233
Short name T20
Test name
Test status
Simulation time 342231251 ps
CPU time 1.1 seconds
Started Jul 03 05:46:33 PM PDT 24
Finished Jul 03 05:46:34 PM PDT 24
Peak memory 196556 kb
Host smart-ba8bbdd1-311e-4e91-a0bf-c156dc6d63f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267066233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2267066233
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3276908068
Short name T190
Test name
Test status
Simulation time 26751079417 ps
CPU time 65.1 seconds
Started Jul 03 05:46:19 PM PDT 24
Finished Jul 03 05:47:24 PM PDT 24
Peak memory 206624 kb
Host smart-ff15579c-c9c9-44ba-8aaf-a6c8e9f9519f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276908068 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3276908068
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3916743286
Short name T82
Test name
Test status
Simulation time 567253099 ps
CPU time 1.47 seconds
Started Jul 03 05:46:50 PM PDT 24
Finished Jul 03 05:46:52 PM PDT 24
Peak memory 196456 kb
Host smart-1b5ab692-2898-4e2a-a241-ea6cde8b618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916743286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3916743286
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3988251449
Short name T177
Test name
Test status
Simulation time 107015747080 ps
CPU time 166.21 seconds
Started Jul 03 05:46:52 PM PDT 24
Finished Jul 03 05:49:38 PM PDT 24
Peak memory 192756 kb
Host smart-bf3f8d9d-3314-45ad-aead-d0871482a6ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988251449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3988251449
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.891698780
Short name T43
Test name
Test status
Simulation time 115820966543 ps
CPU time 36.35 seconds
Started Jul 03 05:46:31 PM PDT 24
Finished Jul 03 05:47:07 PM PDT 24
Peak memory 192804 kb
Host smart-0b2ebc9d-eb0d-4e6e-a52f-c6f11a8ddf26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891698780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.891698780
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.548050890
Short name T111
Test name
Test status
Simulation time 549406632 ps
CPU time 1.23 seconds
Started Jul 03 05:46:42 PM PDT 24
Finished Jul 03 05:46:43 PM PDT 24
Peak memory 196448 kb
Host smart-0c586448-befb-43d0-be44-a2f61948398f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548050890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.548050890
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.533392292
Short name T123
Test name
Test status
Simulation time 490911355 ps
CPU time 0.95 seconds
Started Jul 03 05:46:46 PM PDT 24
Finished Jul 03 05:46:47 PM PDT 24
Peak memory 196492 kb
Host smart-44a1e72c-41d2-48bf-9d13-0bec8d52ceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533392292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.533392292
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.89912419
Short name T102
Test name
Test status
Simulation time 555561986 ps
CPU time 1.33 seconds
Started Jul 03 05:46:48 PM PDT 24
Finished Jul 03 05:46:49 PM PDT 24
Peak memory 196352 kb
Host smart-7d6b71c8-f65f-4450-87e4-a6f002f4f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89912419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.89912419
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3402451435
Short name T159
Test name
Test status
Simulation time 441230466 ps
CPU time 0.72 seconds
Started Jul 03 05:46:20 PM PDT 24
Finished Jul 03 05:46:21 PM PDT 24
Peak memory 196412 kb
Host smart-f3b21449-e433-41d2-aef4-bc4dd91ea4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402451435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3402451435
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2863953945
Short name T179
Test name
Test status
Simulation time 292521019434 ps
CPU time 92.57 seconds
Started Jul 03 05:46:55 PM PDT 24
Finished Jul 03 05:48:28 PM PDT 24
Peak memory 192808 kb
Host smart-4f6d7c1e-fba5-4749-a892-31364dde2ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863953945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2863953945
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1818977836
Short name T5
Test name
Test status
Simulation time 522815005 ps
CPU time 1.35 seconds
Started Jul 03 05:47:00 PM PDT 24
Finished Jul 03 05:47:01 PM PDT 24
Peak memory 196452 kb
Host smart-b9e04660-4900-4873-99d2-ccc81d55352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818977836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1818977836
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.138521964
Short name T145
Test name
Test status
Simulation time 488420099 ps
CPU time 0.92 seconds
Started Jul 03 05:47:04 PM PDT 24
Finished Jul 03 05:47:05 PM PDT 24
Peak memory 196448 kb
Host smart-76d8e705-ed29-4823-a52c-7e2bf2ab2fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138521964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.138521964
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3934565826
Short name T148
Test name
Test status
Simulation time 591238844 ps
CPU time 1.04 seconds
Started Jul 03 05:47:08 PM PDT 24
Finished Jul 03 05:47:09 PM PDT 24
Peak memory 196572 kb
Host smart-db40aba9-06e7-4c3b-be64-437df5b8235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934565826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3934565826
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.731462190
Short name T118
Test name
Test status
Simulation time 409830574 ps
CPU time 1.22 seconds
Started Jul 03 05:47:17 PM PDT 24
Finished Jul 03 05:47:19 PM PDT 24
Peak memory 196492 kb
Host smart-0f33fcca-b29b-4070-ac92-3c5638dde544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731462190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.731462190
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3489347574
Short name T156
Test name
Test status
Simulation time 773943653320 ps
CPU time 1185.35 seconds
Started Jul 03 05:47:16 PM PDT 24
Finished Jul 03 06:07:02 PM PDT 24
Peak memory 198112 kb
Host smart-4e92aba5-d236-443c-a590-0f52852c2420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489347574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3489347574
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1166105491
Short name T140
Test name
Test status
Simulation time 420183092 ps
CPU time 0.73 seconds
Started Jul 03 05:46:35 PM PDT 24
Finished Jul 03 05:46:36 PM PDT 24
Peak memory 196584 kb
Host smart-5f745eb8-9323-4759-9db3-83b1e00298e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166105491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1166105491
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3452855057
Short name T181
Test name
Test status
Simulation time 590072172 ps
CPU time 0.68 seconds
Started Jul 03 05:46:38 PM PDT 24
Finished Jul 03 05:46:39 PM PDT 24
Peak memory 196468 kb
Host smart-1c5839a5-e65c-439a-8c85-0548a9b664c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452855057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3452855057
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1374296580
Short name T160
Test name
Test status
Simulation time 420038483 ps
CPU time 0.69 seconds
Started Jul 03 05:46:44 PM PDT 24
Finished Jul 03 05:46:45 PM PDT 24
Peak memory 196500 kb
Host smart-720dac17-4caa-40b3-955a-2897def11eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374296580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1374296580
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1279125530
Short name T6
Test name
Test status
Simulation time 534016289 ps
CPU time 1.37 seconds
Started Jul 03 05:46:23 PM PDT 24
Finished Jul 03 05:46:26 PM PDT 24
Peak memory 196576 kb
Host smart-eaaec51c-db28-42fa-8e4c-ffebf327b64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279125530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1279125530
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1990736427
Short name T83
Test name
Test status
Simulation time 371807921 ps
CPU time 1.13 seconds
Started Jul 03 05:46:59 PM PDT 24
Finished Jul 03 05:47:00 PM PDT 24
Peak memory 196460 kb
Host smart-6d40304b-d052-40b3-b9db-b325b3f2c1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990736427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1990736427
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.4075908342
Short name T137
Test name
Test status
Simulation time 604493286 ps
CPU time 0.76 seconds
Started Jul 03 05:47:17 PM PDT 24
Finished Jul 03 05:47:18 PM PDT 24
Peak memory 196552 kb
Host smart-9535ee76-2bb8-4b76-ba2a-bef5d235b12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075908342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.4075908342
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.17114686
Short name T182
Test name
Test status
Simulation time 516931806 ps
CPU time 0.75 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:47:10 PM PDT 24
Peak memory 196452 kb
Host smart-4845df4c-0696-49b7-a6c7-9cf505ab9188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17114686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.17114686
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.395110243
Short name T165
Test name
Test status
Simulation time 130070276737 ps
CPU time 171.59 seconds
Started Jul 03 05:47:17 PM PDT 24
Finished Jul 03 05:50:09 PM PDT 24
Peak memory 191708 kb
Host smart-ba408369-2422-4160-8f5f-3e113bc0e22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395110243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.395110243
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3804536581
Short name T379
Test name
Test status
Simulation time 8326619930 ps
CPU time 12.4 seconds
Started Jul 03 05:54:42 PM PDT 24
Finished Jul 03 05:54:55 PM PDT 24
Peak memory 198028 kb
Host smart-a6d21fec-992e-429f-ab57-ef34e6ae7a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804536581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3804536581
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3054197717
Short name T174
Test name
Test status
Simulation time 22772208842 ps
CPU time 259.43 seconds
Started Jul 03 05:46:44 PM PDT 24
Finished Jul 03 05:51:03 PM PDT 24
Peak memory 206664 kb
Host smart-88617318-6320-4ebe-9d5a-204cc246c87c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054197717 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3054197717
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.4119210270
Short name T164
Test name
Test status
Simulation time 124660680910 ps
CPU time 103.3 seconds
Started Jul 03 05:46:42 PM PDT 24
Finished Jul 03 05:48:26 PM PDT 24
Peak memory 198344 kb
Host smart-90c26c94-75dd-458f-ad8a-c5d1d38affb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119210270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.4119210270
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2727710364
Short name T194
Test name
Test status
Simulation time 498830354 ps
CPU time 1.23 seconds
Started Jul 03 05:46:50 PM PDT 24
Finished Jul 03 05:46:51 PM PDT 24
Peak memory 196532 kb
Host smart-bada657f-24b1-470b-bc8d-15be7f3b12e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727710364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2727710364
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2838754711
Short name T163
Test name
Test status
Simulation time 399883324 ps
CPU time 0.84 seconds
Started Jul 03 05:46:55 PM PDT 24
Finished Jul 03 05:46:56 PM PDT 24
Peak memory 196504 kb
Host smart-14069df9-71c4-4df1-b438-70198f76a29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838754711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2838754711
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3031487041
Short name T170
Test name
Test status
Simulation time 469791068823 ps
CPU time 276.41 seconds
Started Jul 03 05:46:24 PM PDT 24
Finished Jul 03 05:51:01 PM PDT 24
Peak memory 206688 kb
Host smart-7e590679-1548-4b89-ae71-690f19d6b87f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031487041 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3031487041
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.89965246
Short name T188
Test name
Test status
Simulation time 536439332 ps
CPU time 0.92 seconds
Started Jul 03 05:47:12 PM PDT 24
Finished Jul 03 05:47:13 PM PDT 24
Peak memory 196444 kb
Host smart-878f3d60-d3bb-4655-b190-0ec7182430a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89965246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.89965246
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.4212113793
Short name T185
Test name
Test status
Simulation time 87702588977 ps
CPU time 245.74 seconds
Started Jul 03 05:47:11 PM PDT 24
Finished Jul 03 05:51:17 PM PDT 24
Peak memory 201012 kb
Host smart-7a2680b8-dfb9-472a-95d6-f1970a6369ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212113793 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.4212113793
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3212597089
Short name T126
Test name
Test status
Simulation time 370008740 ps
CPU time 1.14 seconds
Started Jul 03 05:47:15 PM PDT 24
Finished Jul 03 05:47:17 PM PDT 24
Peak memory 196564 kb
Host smart-377502fc-bcec-4dbb-8626-b7c734fd866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212597089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3212597089
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.253807726
Short name T45
Test name
Test status
Simulation time 400121160 ps
CPU time 1.18 seconds
Started Jul 03 05:46:31 PM PDT 24
Finished Jul 03 05:46:32 PM PDT 24
Peak memory 196588 kb
Host smart-775f3a53-08c2-4171-9303-0102fba47b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253807726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.253807726
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.979503930
Short name T195
Test name
Test status
Simulation time 528091637 ps
CPU time 1.36 seconds
Started Jul 03 05:46:31 PM PDT 24
Finished Jul 03 05:46:33 PM PDT 24
Peak memory 196520 kb
Host smart-5d310708-194c-42f8-832b-a5a7647f6ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979503930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.979503930
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3603779731
Short name T172
Test name
Test status
Simulation time 573293951 ps
CPU time 1.38 seconds
Started Jul 03 05:46:16 PM PDT 24
Finished Jul 03 05:46:18 PM PDT 24
Peak memory 196404 kb
Host smart-a061deb2-42b1-4d51-867e-8ef16ab4a27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603779731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3603779731
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.4245675829
Short name T176
Test name
Test status
Simulation time 547280577 ps
CPU time 1.02 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 05:46:55 PM PDT 24
Peak memory 196464 kb
Host smart-142f055f-db28-48e1-bf15-398c7ed3a516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245675829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.4245675829
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3509217149
Short name T186
Test name
Test status
Simulation time 405774728 ps
CPU time 1.21 seconds
Started Jul 03 05:47:05 PM PDT 24
Finished Jul 03 05:47:07 PM PDT 24
Peak memory 196448 kb
Host smart-5fc7d38d-3aae-440b-97c8-3c08aad11499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509217149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3509217149
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3247009617
Short name T193
Test name
Test status
Simulation time 547657807 ps
CPU time 0.78 seconds
Started Jul 03 05:47:05 PM PDT 24
Finished Jul 03 05:47:06 PM PDT 24
Peak memory 196448 kb
Host smart-85fb411d-40b3-40b7-86d5-b00885861f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247009617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3247009617
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.354755647
Short name T151
Test name
Test status
Simulation time 444778709 ps
CPU time 0.67 seconds
Started Jul 03 05:47:10 PM PDT 24
Finished Jul 03 05:47:12 PM PDT 24
Peak memory 196484 kb
Host smart-c1219285-4686-4a18-bc60-2df5bd4a943d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354755647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.354755647
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1110079265
Short name T173
Test name
Test status
Simulation time 110109753919 ps
CPU time 89.49 seconds
Started Jul 03 05:47:12 PM PDT 24
Finished Jul 03 05:48:42 PM PDT 24
Peak memory 191720 kb
Host smart-be065014-c98c-43d2-a76a-9d423532ba6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110079265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1110079265
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3499888896
Short name T149
Test name
Test status
Simulation time 588810014 ps
CPU time 0.64 seconds
Started Jul 03 05:47:17 PM PDT 24
Finished Jul 03 05:47:18 PM PDT 24
Peak memory 196584 kb
Host smart-2d067b54-9c70-48bb-86b9-a2ccdc6b21b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499888896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3499888896
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2722423988
Short name T129
Test name
Test status
Simulation time 486719015 ps
CPU time 0.78 seconds
Started Jul 03 05:46:27 PM PDT 24
Finished Jul 03 05:46:29 PM PDT 24
Peak memory 196512 kb
Host smart-d054fae1-8c86-4e61-81ec-5ac2461047df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722423988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2722423988
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3440563648
Short name T167
Test name
Test status
Simulation time 744942165 ps
CPU time 0.68 seconds
Started Jul 03 05:46:32 PM PDT 24
Finished Jul 03 05:46:33 PM PDT 24
Peak memory 196472 kb
Host smart-f2a25acc-8165-4021-a643-d6f694671a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440563648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3440563648
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.38931069
Short name T291
Test name
Test status
Simulation time 537087485 ps
CPU time 0.87 seconds
Started Jul 03 05:54:31 PM PDT 24
Finished Jul 03 05:54:32 PM PDT 24
Peak memory 183660 kb
Host smart-f41b2879-c31f-4cce-b1e6-40df77ee009b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38931069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_ali
asing.38931069
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1520165991
Short name T394
Test name
Test status
Simulation time 1462598523 ps
CPU time 1.96 seconds
Started Jul 03 05:54:28 PM PDT 24
Finished Jul 03 05:54:30 PM PDT 24
Peak memory 193272 kb
Host smart-723aee31-761c-4964-8a94-571e5fa9f807
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520165991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1520165991
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4231607162
Short name T375
Test name
Test status
Simulation time 434303033 ps
CPU time 1.31 seconds
Started Jul 03 05:54:35 PM PDT 24
Finished Jul 03 05:54:36 PM PDT 24
Peak memory 196132 kb
Host smart-ab4180e4-92c4-4766-aaef-4ea48fa79b40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231607162 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.4231607162
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2713846086
Short name T371
Test name
Test status
Simulation time 321641022 ps
CPU time 0.83 seconds
Started Jul 03 05:54:28 PM PDT 24
Finished Jul 03 05:54:29 PM PDT 24
Peak memory 192984 kb
Host smart-c5661e3f-60d3-4d46-875f-c6a1565bde86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713846086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2713846086
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1454111359
Short name T378
Test name
Test status
Simulation time 404857344 ps
CPU time 1.1 seconds
Started Jul 03 05:54:29 PM PDT 24
Finished Jul 03 05:54:30 PM PDT 24
Peak memory 183656 kb
Host smart-7c91a6ab-8703-4025-b1e2-adffc2cb54e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454111359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1454111359
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3281204527
Short name T390
Test name
Test status
Simulation time 477780814 ps
CPU time 0.69 seconds
Started Jul 03 05:54:27 PM PDT 24
Finished Jul 03 05:54:28 PM PDT 24
Peak memory 183724 kb
Host smart-3a9660fd-5833-48bf-9c9c-3ecd6365b79e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281204527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3281204527
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2775078088
Short name T71
Test name
Test status
Simulation time 1588724763 ps
CPU time 1.7 seconds
Started Jul 03 05:54:30 PM PDT 24
Finished Jul 03 05:54:32 PM PDT 24
Peak memory 191900 kb
Host smart-861ee822-d1a2-4fc1-87c9-fe9ed26fbfed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775078088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2775078088
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1317379811
Short name T335
Test name
Test status
Simulation time 620920933 ps
CPU time 1.71 seconds
Started Jul 03 05:54:27 PM PDT 24
Finished Jul 03 05:54:29 PM PDT 24
Peak memory 198608 kb
Host smart-392f88b7-d297-49eb-989c-0ccf49be5704
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317379811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1317379811
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1173510305
Short name T398
Test name
Test status
Simulation time 8131660349 ps
CPU time 3.38 seconds
Started Jul 03 05:54:27 PM PDT 24
Finished Jul 03 05:54:31 PM PDT 24
Peak memory 198176 kb
Host smart-4b788749-2e1e-4146-9e62-1728cbe9a0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173510305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1173510305
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4274407331
Short name T66
Test name
Test status
Simulation time 573269511 ps
CPU time 0.9 seconds
Started Jul 03 05:54:39 PM PDT 24
Finished Jul 03 05:54:41 PM PDT 24
Peak memory 194272 kb
Host smart-b7c6ea40-b429-47da-a862-b4aa14f90a59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274407331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.4274407331
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.70983258
Short name T62
Test name
Test status
Simulation time 4607662032 ps
CPU time 2.7 seconds
Started Jul 03 05:54:36 PM PDT 24
Finished Jul 03 05:54:39 PM PDT 24
Peak memory 196024 kb
Host smart-5026e9f2-10be-44f0-8c17-0f8bc2712e14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70983258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit
_bash.70983258
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1824442409
Short name T58
Test name
Test status
Simulation time 1309329203 ps
CPU time 2.38 seconds
Started Jul 03 05:54:33 PM PDT 24
Finished Jul 03 05:54:36 PM PDT 24
Peak memory 193232 kb
Host smart-672d8b43-4d61-4d9b-8d07-5edf97ea3f2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824442409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1824442409
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1172488361
Short name T343
Test name
Test status
Simulation time 415468811 ps
CPU time 1.01 seconds
Started Jul 03 05:54:41 PM PDT 24
Finished Jul 03 05:54:42 PM PDT 24
Peak memory 197936 kb
Host smart-b646c92f-3742-4c5a-8e1b-bc42d8732d83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172488361 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1172488361
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1852553128
Short name T391
Test name
Test status
Simulation time 295808112 ps
CPU time 0.8 seconds
Started Jul 03 05:54:36 PM PDT 24
Finished Jul 03 05:54:37 PM PDT 24
Peak memory 192052 kb
Host smart-244a685f-6d40-43fa-85a5-e50921f9b1ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852553128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1852553128
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.843066582
Short name T327
Test name
Test status
Simulation time 503443837 ps
CPU time 0.82 seconds
Started Jul 03 05:54:32 PM PDT 24
Finished Jul 03 05:54:33 PM PDT 24
Peak memory 183720 kb
Host smart-fdb60603-503c-48cb-a5dd-9545a460cc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843066582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.843066582
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.786518283
Short name T303
Test name
Test status
Simulation time 330340984 ps
CPU time 0.61 seconds
Started Jul 03 05:54:34 PM PDT 24
Finished Jul 03 05:54:35 PM PDT 24
Peak memory 183664 kb
Host smart-97839bba-311f-49de-9d98-cd08ba6cd989
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786518283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.786518283
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.130321555
Short name T410
Test name
Test status
Simulation time 303281372 ps
CPU time 0.56 seconds
Started Jul 03 05:54:36 PM PDT 24
Finished Jul 03 05:54:37 PM PDT 24
Peak memory 183724 kb
Host smart-8330e059-451f-442f-9cca-41a2da2ec24e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130321555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.130321555
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1098681626
Short name T74
Test name
Test status
Simulation time 2452140971 ps
CPU time 4.15 seconds
Started Jul 03 05:54:40 PM PDT 24
Finished Jul 03 05:54:45 PM PDT 24
Peak memory 195064 kb
Host smart-81867809-c3b0-43c9-9a27-a9042275a741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098681626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1098681626
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.33908907
Short name T289
Test name
Test status
Simulation time 652288162 ps
CPU time 1.89 seconds
Started Jul 03 05:54:33 PM PDT 24
Finished Jul 03 05:54:35 PM PDT 24
Peak memory 198668 kb
Host smart-c189e41a-4d63-4e25-aaad-d7ace8fec8dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33908907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.33908907
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.350230133
Short name T31
Test name
Test status
Simulation time 8372568227 ps
CPU time 11.97 seconds
Started Jul 03 05:54:34 PM PDT 24
Finished Jul 03 05:54:46 PM PDT 24
Peak memory 198292 kb
Host smart-b50f59e4-2750-4550-b36c-b9423376391d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350230133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.350230133
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4181701826
Short name T411
Test name
Test status
Simulation time 648601752 ps
CPU time 0.93 seconds
Started Jul 03 05:55:29 PM PDT 24
Finished Jul 03 05:55:30 PM PDT 24
Peak memory 197616 kb
Host smart-1f8a9c75-1764-41a2-8a20-5ebbe90eb824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181701826 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4181701826
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3848419119
Short name T352
Test name
Test status
Simulation time 481969717 ps
CPU time 0.79 seconds
Started Jul 03 05:55:26 PM PDT 24
Finished Jul 03 05:55:27 PM PDT 24
Peak memory 193168 kb
Host smart-b9b6c852-121e-49c9-8e33-1291ef51035a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848419119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3848419119
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2788904656
Short name T284
Test name
Test status
Simulation time 444274436 ps
CPU time 0.87 seconds
Started Jul 03 05:55:31 PM PDT 24
Finished Jul 03 05:55:33 PM PDT 24
Peak memory 183716 kb
Host smart-2837cf09-5c46-4632-a9b5-118e51220a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788904656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2788904656
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1418174804
Short name T418
Test name
Test status
Simulation time 1166017298 ps
CPU time 0.99 seconds
Started Jul 03 05:55:27 PM PDT 24
Finished Jul 03 05:55:28 PM PDT 24
Peak memory 193816 kb
Host smart-9b60555d-3cf8-4d35-a850-693546938d92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418174804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1418174804
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1456878029
Short name T281
Test name
Test status
Simulation time 632885547 ps
CPU time 1.52 seconds
Started Jul 03 05:55:31 PM PDT 24
Finished Jul 03 05:55:33 PM PDT 24
Peak memory 198632 kb
Host smart-4a8397b0-360e-42a7-bafa-948836403554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456878029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1456878029
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2242185235
Short name T313
Test name
Test status
Simulation time 489655036 ps
CPU time 0.89 seconds
Started Jul 03 05:55:32 PM PDT 24
Finished Jul 03 05:55:33 PM PDT 24
Peak memory 196228 kb
Host smart-a3a59914-4cea-4399-9839-3b00c6aabfea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242185235 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2242185235
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3432110856
Short name T34
Test name
Test status
Simulation time 479633386 ps
CPU time 1.41 seconds
Started Jul 03 05:55:25 PM PDT 24
Finished Jul 03 05:55:27 PM PDT 24
Peak memory 193380 kb
Host smart-e9ece90e-4ae2-4a52-a93a-4f43c79d6a39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432110856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3432110856
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1485311697
Short name T377
Test name
Test status
Simulation time 294533332 ps
CPU time 0.61 seconds
Started Jul 03 05:55:26 PM PDT 24
Finished Jul 03 05:55:27 PM PDT 24
Peak memory 183760 kb
Host smart-8db83f05-dcec-4df2-8fa3-2af8d0e966f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485311697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1485311697
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1751536743
Short name T324
Test name
Test status
Simulation time 1778542999 ps
CPU time 1.7 seconds
Started Jul 03 05:55:26 PM PDT 24
Finished Jul 03 05:55:28 PM PDT 24
Peak memory 193964 kb
Host smart-3b1f0797-f265-4fd1-820a-4a2353b2ae65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751536743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1751536743
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1908252685
Short name T363
Test name
Test status
Simulation time 538786878 ps
CPU time 1.96 seconds
Started Jul 03 05:55:26 PM PDT 24
Finished Jul 03 05:55:28 PM PDT 24
Peak memory 198664 kb
Host smart-29633f21-b335-42e9-a2d2-ac95c3bcef59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908252685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1908252685
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2613698971
Short name T331
Test name
Test status
Simulation time 8375028889 ps
CPU time 6.99 seconds
Started Jul 03 05:55:27 PM PDT 24
Finished Jul 03 05:55:34 PM PDT 24
Peak memory 198300 kb
Host smart-f7f1d973-76ca-43f7-ba1a-1bffa9aa4857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613698971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2613698971
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.793323836
Short name T292
Test name
Test status
Simulation time 678630599 ps
CPU time 0.82 seconds
Started Jul 03 05:55:30 PM PDT 24
Finished Jul 03 05:55:31 PM PDT 24
Peak memory 197976 kb
Host smart-566d2195-17ac-4139-b82f-cd84e398bfdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793323836 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.793323836
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3093016388
Short name T397
Test name
Test status
Simulation time 385222211 ps
CPU time 1.05 seconds
Started Jul 03 05:55:30 PM PDT 24
Finished Jul 03 05:55:31 PM PDT 24
Peak memory 192992 kb
Host smart-d55853e7-38cc-416b-956b-05de4f66d2b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093016388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3093016388
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1981138354
Short name T342
Test name
Test status
Simulation time 576337431 ps
CPU time 0.59 seconds
Started Jul 03 05:55:29 PM PDT 24
Finished Jul 03 05:55:29 PM PDT 24
Peak memory 183764 kb
Host smart-f95e3eab-3cbb-4052-8e22-b197f106d03a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981138354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1981138354
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2197766094
Short name T72
Test name
Test status
Simulation time 2040341975 ps
CPU time 2.13 seconds
Started Jul 03 05:55:31 PM PDT 24
Finished Jul 03 05:55:33 PM PDT 24
Peak memory 195100 kb
Host smart-3eb362e3-951b-42cc-b25b-c2fed167a77a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197766094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2197766094
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4268666572
Short name T288
Test name
Test status
Simulation time 540182098 ps
CPU time 1.66 seconds
Started Jul 03 05:55:25 PM PDT 24
Finished Jul 03 05:55:27 PM PDT 24
Peak memory 198480 kb
Host smart-b6f73696-4318-41ca-8cbe-c2852f1e4a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268666572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4268666572
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1913674879
Short name T305
Test name
Test status
Simulation time 4410910999 ps
CPU time 7.23 seconds
Started Jul 03 05:55:31 PM PDT 24
Finished Jul 03 05:55:39 PM PDT 24
Peak memory 198008 kb
Host smart-03699440-9f88-4c45-8f5b-7e8f0d6941db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913674879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1913674879
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2031637998
Short name T294
Test name
Test status
Simulation time 573033072 ps
CPU time 1.49 seconds
Started Jul 03 05:55:34 PM PDT 24
Finished Jul 03 05:55:36 PM PDT 24
Peak memory 196152 kb
Host smart-8d039b29-05a2-45ee-89fc-88e5315e5ced
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031637998 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2031637998
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.919539723
Short name T409
Test name
Test status
Simulation time 508848316 ps
CPU time 0.88 seconds
Started Jul 03 05:55:34 PM PDT 24
Finished Jul 03 05:55:35 PM PDT 24
Peak memory 193004 kb
Host smart-26b12a33-d995-4cf3-b3a6-ef9e6282b117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919539723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.919539723
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3319769527
Short name T373
Test name
Test status
Simulation time 296623419 ps
CPU time 0.65 seconds
Started Jul 03 05:55:33 PM PDT 24
Finished Jul 03 05:55:33 PM PDT 24
Peak memory 183772 kb
Host smart-f12a8c15-ba7a-418e-a12b-4a1b97becdfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319769527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3319769527
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2983342835
Short name T76
Test name
Test status
Simulation time 1797435055 ps
CPU time 3.04 seconds
Started Jul 03 05:55:34 PM PDT 24
Finished Jul 03 05:55:38 PM PDT 24
Peak memory 193856 kb
Host smart-cc9adba0-8d20-4c08-8a84-c6065ea9ef4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983342835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2983342835
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3050906789
Short name T354
Test name
Test status
Simulation time 394189422 ps
CPU time 1.93 seconds
Started Jul 03 05:55:30 PM PDT 24
Finished Jul 03 05:55:33 PM PDT 24
Peak memory 198640 kb
Host smart-944cd27a-61fd-495a-8e33-2406fcd82cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050906789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3050906789
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3258686720
Short name T364
Test name
Test status
Simulation time 8962157789 ps
CPU time 2.31 seconds
Started Jul 03 05:55:30 PM PDT 24
Finished Jul 03 05:55:33 PM PDT 24
Peak memory 198252 kb
Host smart-f90b98c9-0a0a-4d00-9bfa-e12991fa5906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258686720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3258686720
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2216368263
Short name T380
Test name
Test status
Simulation time 490190634 ps
CPU time 0.85 seconds
Started Jul 03 05:55:41 PM PDT 24
Finished Jul 03 05:55:43 PM PDT 24
Peak memory 197532 kb
Host smart-8eb5069f-45b7-443e-908d-a545264ba993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216368263 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2216368263
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1485289772
Short name T385
Test name
Test status
Simulation time 549177832 ps
CPU time 0.77 seconds
Started Jul 03 05:55:38 PM PDT 24
Finished Jul 03 05:55:39 PM PDT 24
Peak memory 193108 kb
Host smart-03cf75a3-a0b7-48ba-8c6c-bdb088d3a497
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485289772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1485289772
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1266040631
Short name T297
Test name
Test status
Simulation time 470587610 ps
CPU time 0.69 seconds
Started Jul 03 05:55:37 PM PDT 24
Finished Jul 03 05:55:38 PM PDT 24
Peak memory 192928 kb
Host smart-d33f015d-c6e2-4b51-8bfe-9d44074b51d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266040631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1266040631
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.587054070
Short name T73
Test name
Test status
Simulation time 2445547444 ps
CPU time 3.02 seconds
Started Jul 03 05:55:36 PM PDT 24
Finished Jul 03 05:55:39 PM PDT 24
Peak memory 194500 kb
Host smart-38109379-228b-437f-b7d3-e6681db7dddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587054070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.587054070
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1229512646
Short name T420
Test name
Test status
Simulation time 519938259 ps
CPU time 1.2 seconds
Started Jul 03 05:55:33 PM PDT 24
Finished Jul 03 05:55:35 PM PDT 24
Peak memory 198452 kb
Host smart-9a739141-5cff-4c55-b2b2-0748d69f114a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229512646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1229512646
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2454117234
Short name T32
Test name
Test status
Simulation time 8790441700 ps
CPU time 6.5 seconds
Started Jul 03 05:55:34 PM PDT 24
Finished Jul 03 05:55:41 PM PDT 24
Peak memory 198164 kb
Host smart-7b3e0da7-a5e1-4c11-a3b5-dbccfd4125b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454117234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2454117234
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3620790254
Short name T367
Test name
Test status
Simulation time 443072812 ps
CPU time 1.36 seconds
Started Jul 03 05:55:39 PM PDT 24
Finished Jul 03 05:55:41 PM PDT 24
Peak memory 196128 kb
Host smart-a8f35420-439d-44d7-8ec2-bed022244d0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620790254 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3620790254
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2507798290
Short name T60
Test name
Test status
Simulation time 539217221 ps
CPU time 1.4 seconds
Started Jul 03 05:55:38 PM PDT 24
Finished Jul 03 05:55:39 PM PDT 24
Peak memory 194036 kb
Host smart-bb6c6611-0626-4812-b385-d885e52c996d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507798290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2507798290
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.844571124
Short name T357
Test name
Test status
Simulation time 487639036 ps
CPU time 1.19 seconds
Started Jul 03 05:55:39 PM PDT 24
Finished Jul 03 05:55:41 PM PDT 24
Peak memory 183740 kb
Host smart-7f535bc3-ae94-42d8-8a3a-9d774594c82b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844571124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.844571124
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1608624316
Short name T75
Test name
Test status
Simulation time 1070790710 ps
CPU time 1.29 seconds
Started Jul 03 05:55:41 PM PDT 24
Finished Jul 03 05:55:43 PM PDT 24
Peak memory 193052 kb
Host smart-f1ff223b-bd17-4b75-8ce2-9db61af43b52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608624316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1608624316
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.351197547
Short name T285
Test name
Test status
Simulation time 322977356 ps
CPU time 1.55 seconds
Started Jul 03 05:55:40 PM PDT 24
Finished Jul 03 05:55:42 PM PDT 24
Peak memory 198692 kb
Host smart-46ad487c-53f9-426c-83b5-89b3561df7c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351197547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.351197547
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1443260042
Short name T199
Test name
Test status
Simulation time 4533712532 ps
CPU time 7.64 seconds
Started Jul 03 05:55:39 PM PDT 24
Finished Jul 03 05:55:47 PM PDT 24
Peak memory 196472 kb
Host smart-818d157c-b138-4c72-afd8-d0e1498aa39d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443260042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1443260042
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3321400659
Short name T298
Test name
Test status
Simulation time 406843691 ps
CPU time 0.88 seconds
Started Jul 03 05:55:42 PM PDT 24
Finished Jul 03 05:55:43 PM PDT 24
Peak memory 196596 kb
Host smart-c63b24f2-951a-40ef-bc51-bdaec60ac2ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321400659 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3321400659
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1815425091
Short name T35
Test name
Test status
Simulation time 434599441 ps
CPU time 1.15 seconds
Started Jul 03 05:55:39 PM PDT 24
Finished Jul 03 05:55:41 PM PDT 24
Peak memory 193004 kb
Host smart-36602c8e-b908-4cd2-9882-7e503ab44976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815425091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1815425091
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3165339417
Short name T340
Test name
Test status
Simulation time 348781150 ps
CPU time 0.77 seconds
Started Jul 03 05:55:43 PM PDT 24
Finished Jul 03 05:55:44 PM PDT 24
Peak memory 183736 kb
Host smart-2a69f42f-227f-489e-9701-a098d2cd7ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165339417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3165339417
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3513852435
Short name T381
Test name
Test status
Simulation time 2436501969 ps
CPU time 1.57 seconds
Started Jul 03 05:55:41 PM PDT 24
Finished Jul 03 05:55:43 PM PDT 24
Peak memory 195104 kb
Host smart-8a0c8eba-c587-443d-b3da-a8ada20714a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513852435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3513852435
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.543596341
Short name T320
Test name
Test status
Simulation time 872689336 ps
CPU time 2.76 seconds
Started Jul 03 05:55:42 PM PDT 24
Finished Jul 03 05:55:45 PM PDT 24
Peak memory 198668 kb
Host smart-f22886d9-fa63-426f-bada-15fac81c20c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543596341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.543596341
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.304108947
Short name T415
Test name
Test status
Simulation time 9010347173 ps
CPU time 3.92 seconds
Started Jul 03 05:55:40 PM PDT 24
Finished Jul 03 05:55:44 PM PDT 24
Peak memory 198192 kb
Host smart-34f2343c-0998-462a-8232-2f0bc9413d36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304108947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.304108947
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2463995099
Short name T362
Test name
Test status
Simulation time 457426932 ps
CPU time 1.48 seconds
Started Jul 03 05:55:44 PM PDT 24
Finished Jul 03 05:55:45 PM PDT 24
Peak memory 198608 kb
Host smart-ea8c7815-22bc-44ba-95cb-8e390c837522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463995099 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2463995099
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.610936555
Short name T57
Test name
Test status
Simulation time 356244825 ps
CPU time 1.06 seconds
Started Jul 03 05:55:43 PM PDT 24
Finished Jul 03 05:55:45 PM PDT 24
Peak memory 192064 kb
Host smart-b33e9d4e-4c8d-4027-8090-c2e64bb9176e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610936555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.610936555
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.324020424
Short name T286
Test name
Test status
Simulation time 446418986 ps
CPU time 0.65 seconds
Started Jul 03 05:55:39 PM PDT 24
Finished Jul 03 05:55:40 PM PDT 24
Peak memory 192976 kb
Host smart-69dccfd7-0949-412d-b279-077832c5c8b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324020424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.324020424
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.931854672
Short name T366
Test name
Test status
Simulation time 2277084567 ps
CPU time 1.49 seconds
Started Jul 03 05:55:43 PM PDT 24
Finished Jul 03 05:55:44 PM PDT 24
Peak memory 194148 kb
Host smart-ac1b3224-5f75-41e1-8591-be5b0223058f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931854672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.931854672
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2651196004
Short name T330
Test name
Test status
Simulation time 607656749 ps
CPU time 1.42 seconds
Started Jul 03 05:55:43 PM PDT 24
Finished Jul 03 05:55:45 PM PDT 24
Peak memory 198624 kb
Host smart-97366a3a-9918-47aa-930b-37c208690580
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651196004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2651196004
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2571816259
Short name T414
Test name
Test status
Simulation time 4864240057 ps
CPU time 1.86 seconds
Started Jul 03 05:55:41 PM PDT 24
Finished Jul 03 05:55:43 PM PDT 24
Peak memory 197704 kb
Host smart-1e58b03f-33dc-4406-bc1d-18475df08f63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571816259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2571816259
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2154375787
Short name T334
Test name
Test status
Simulation time 557629939 ps
CPU time 0.82 seconds
Started Jul 03 05:55:45 PM PDT 24
Finished Jul 03 05:55:46 PM PDT 24
Peak memory 196800 kb
Host smart-ca02e6ac-48d1-4394-9085-739af2a0c67b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154375787 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2154375787
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3714676267
Short name T33
Test name
Test status
Simulation time 387016892 ps
CPU time 0.62 seconds
Started Jul 03 05:55:45 PM PDT 24
Finished Jul 03 05:55:46 PM PDT 24
Peak memory 193016 kb
Host smart-1dd33c13-ac8a-4308-913d-268132d31023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714676267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3714676267
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2520031852
Short name T309
Test name
Test status
Simulation time 390906213 ps
CPU time 0.75 seconds
Started Jul 03 05:55:43 PM PDT 24
Finished Jul 03 05:55:44 PM PDT 24
Peak memory 183720 kb
Host smart-d838a53d-7bca-4cc6-bfb0-0c1b336c8828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520031852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2520031852
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1564400278
Short name T382
Test name
Test status
Simulation time 927740032 ps
CPU time 0.94 seconds
Started Jul 03 05:55:44 PM PDT 24
Finished Jul 03 05:55:45 PM PDT 24
Peak memory 193532 kb
Host smart-726c5933-dde4-45fb-b22a-ba7ca2d2b465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564400278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1564400278
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2528100474
Short name T293
Test name
Test status
Simulation time 530045263 ps
CPU time 2.19 seconds
Started Jul 03 05:55:42 PM PDT 24
Finished Jul 03 05:55:44 PM PDT 24
Peak memory 198608 kb
Host smart-0a1bdc55-4dcb-4d49-9729-5e87ef129b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528100474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2528100474
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1182191454
Short name T404
Test name
Test status
Simulation time 8652363493 ps
CPU time 4.2 seconds
Started Jul 03 05:55:43 PM PDT 24
Finished Jul 03 05:55:47 PM PDT 24
Peak memory 198252 kb
Host smart-4ebd800c-2dbc-4bd0-88ce-c613832ff1cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182191454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1182191454
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.716702337
Short name T344
Test name
Test status
Simulation time 371713869 ps
CPU time 1.28 seconds
Started Jul 03 05:55:47 PM PDT 24
Finished Jul 03 05:55:48 PM PDT 24
Peak memory 196240 kb
Host smart-1a11a867-8b56-4ed0-a917-1d482d3408e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716702337 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.716702337
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.69866480
Short name T304
Test name
Test status
Simulation time 348703191 ps
CPU time 1.01 seconds
Started Jul 03 05:55:45 PM PDT 24
Finished Jul 03 05:55:46 PM PDT 24
Peak memory 193000 kb
Host smart-9bc5dd9b-851b-4a7f-a8d4-12df1c34f831
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69866480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.69866480
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1756005096
Short name T336
Test name
Test status
Simulation time 415470985 ps
CPU time 0.67 seconds
Started Jul 03 05:55:46 PM PDT 24
Finished Jul 03 05:55:47 PM PDT 24
Peak memory 183768 kb
Host smart-84a23a4c-608d-4a47-9168-b45774f6b5b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756005096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1756005096
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1817670463
Short name T302
Test name
Test status
Simulation time 1252445086 ps
CPU time 1.03 seconds
Started Jul 03 05:55:43 PM PDT 24
Finished Jul 03 05:55:45 PM PDT 24
Peak memory 191996 kb
Host smart-4535b4bf-dcb2-477e-b59e-4c64e445f011
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817670463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1817670463
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1159435838
Short name T395
Test name
Test status
Simulation time 864224236 ps
CPU time 2.28 seconds
Started Jul 03 05:55:45 PM PDT 24
Finished Jul 03 05:55:48 PM PDT 24
Peak memory 198648 kb
Host smart-a8cb44c1-17fb-47eb-8609-39b9d5fa5edf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159435838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1159435838
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.817658720
Short name T345
Test name
Test status
Simulation time 4881269361 ps
CPU time 6.79 seconds
Started Jul 03 05:55:47 PM PDT 24
Finished Jul 03 05:55:54 PM PDT 24
Peak memory 197804 kb
Host smart-b6b396c4-9cf9-4f01-91dc-e789e970a5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817658720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.817658720
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.703257641
Short name T70
Test name
Test status
Simulation time 463081261 ps
CPU time 0.78 seconds
Started Jul 03 05:54:51 PM PDT 24
Finished Jul 03 05:54:52 PM PDT 24
Peak memory 193300 kb
Host smart-2d5cf2fc-7968-4693-ad4a-2e575e26b4af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703257641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.703257641
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1436229626
Short name T406
Test name
Test status
Simulation time 14100510804 ps
CPU time 11.93 seconds
Started Jul 03 05:54:50 PM PDT 24
Finished Jul 03 05:55:02 PM PDT 24
Peak memory 195928 kb
Host smart-ed8256bf-b7fe-4471-91ca-ea5a7928999b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436229626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1436229626
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.248731845
Short name T384
Test name
Test status
Simulation time 1223469244 ps
CPU time 1.04 seconds
Started Jul 03 05:54:50 PM PDT 24
Finished Jul 03 05:54:52 PM PDT 24
Peak memory 193252 kb
Host smart-9962e408-6ed2-4ac2-b696-cd4aaca2af95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248731845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.248731845
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1481770677
Short name T310
Test name
Test status
Simulation time 461466071 ps
CPU time 0.92 seconds
Started Jul 03 05:54:54 PM PDT 24
Finished Jul 03 05:54:55 PM PDT 24
Peak memory 195944 kb
Host smart-15ca0bc2-6879-413f-9ca6-14c5b1f75643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481770677 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1481770677
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.377417559
Short name T30
Test name
Test status
Simulation time 363244422 ps
CPU time 0.67 seconds
Started Jul 03 05:54:50 PM PDT 24
Finished Jul 03 05:54:51 PM PDT 24
Peak memory 192080 kb
Host smart-9d95c9d0-5851-4fec-be92-aa61e3be04a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377417559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.377417559
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2876053311
Short name T355
Test name
Test status
Simulation time 468398907 ps
CPU time 1.17 seconds
Started Jul 03 05:54:49 PM PDT 24
Finished Jul 03 05:54:50 PM PDT 24
Peak memory 183768 kb
Host smart-e282e0e6-2701-40e2-be8b-d834fd0ee390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876053311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2876053311
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1564820055
Short name T333
Test name
Test status
Simulation time 346840540 ps
CPU time 0.64 seconds
Started Jul 03 05:54:47 PM PDT 24
Finished Jul 03 05:54:48 PM PDT 24
Peak memory 183516 kb
Host smart-5e4e3fb4-55fc-4db4-83da-62bdac2ce1af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564820055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1564820055
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.360517065
Short name T408
Test name
Test status
Simulation time 309595289 ps
CPU time 0.98 seconds
Started Jul 03 05:54:49 PM PDT 24
Finished Jul 03 05:54:50 PM PDT 24
Peak memory 183748 kb
Host smart-08ec1914-e50d-48e8-bc71-e9123d1966f8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360517065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.360517065
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.734911576
Short name T368
Test name
Test status
Simulation time 2369116865 ps
CPU time 5.11 seconds
Started Jul 03 05:54:50 PM PDT 24
Finished Jul 03 05:54:56 PM PDT 24
Peak memory 194112 kb
Host smart-cbf725d8-821b-418f-91d5-91d88dd908a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734911576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.734911576
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.622389062
Short name T295
Test name
Test status
Simulation time 566733843 ps
CPU time 1.73 seconds
Started Jul 03 05:54:41 PM PDT 24
Finished Jul 03 05:54:43 PM PDT 24
Peak memory 198680 kb
Host smart-32e9f385-6621-461c-93ee-9de9f127339e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622389062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.622389062
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.522827275
Short name T299
Test name
Test status
Simulation time 370355225 ps
CPU time 0.6 seconds
Started Jul 03 05:55:45 PM PDT 24
Finished Jul 03 05:55:46 PM PDT 24
Peak memory 183724 kb
Host smart-7e756bae-f3d1-49ad-9cb6-a352b2b18e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522827275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.522827275
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2408783699
Short name T386
Test name
Test status
Simulation time 322919561 ps
CPU time 1 seconds
Started Jul 03 05:55:44 PM PDT 24
Finished Jul 03 05:55:45 PM PDT 24
Peak memory 183604 kb
Host smart-fa919935-d6d8-4ac9-8c08-d06353051ac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408783699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2408783699
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1920302561
Short name T389
Test name
Test status
Simulation time 344752985 ps
CPU time 0.97 seconds
Started Jul 03 05:55:48 PM PDT 24
Finished Jul 03 05:55:49 PM PDT 24
Peak memory 193000 kb
Host smart-da08a87d-897b-4fe4-92df-acffbbcc8ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920302561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1920302561
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3841969028
Short name T393
Test name
Test status
Simulation time 472665958 ps
CPU time 1.19 seconds
Started Jul 03 05:55:46 PM PDT 24
Finished Jul 03 05:55:48 PM PDT 24
Peak memory 183720 kb
Host smart-4859533b-a695-4ac0-9d81-c598f3ed92c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841969028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3841969028
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2205960708
Short name T321
Test name
Test status
Simulation time 474420521 ps
CPU time 1.11 seconds
Started Jul 03 05:55:48 PM PDT 24
Finished Jul 03 05:55:49 PM PDT 24
Peak memory 183752 kb
Host smart-6163dcfb-947c-45f7-a38c-de7dac455384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205960708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2205960708
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4264951383
Short name T400
Test name
Test status
Simulation time 287624715 ps
CPU time 0.73 seconds
Started Jul 03 05:55:47 PM PDT 24
Finished Jul 03 05:55:48 PM PDT 24
Peak memory 183604 kb
Host smart-b4b9e9d9-f6e6-4d53-a18b-f751f355eafb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264951383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4264951383
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4147408859
Short name T332
Test name
Test status
Simulation time 450577497 ps
CPU time 0.6 seconds
Started Jul 03 05:55:48 PM PDT 24
Finished Jul 03 05:55:48 PM PDT 24
Peak memory 183732 kb
Host smart-2204bd3c-d918-4f30-9e33-3fb7c46f1282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147408859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4147408859
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.66003664
Short name T370
Test name
Test status
Simulation time 405505522 ps
CPU time 0.68 seconds
Started Jul 03 05:55:47 PM PDT 24
Finished Jul 03 05:55:48 PM PDT 24
Peak memory 183768 kb
Host smart-ebc611ef-2c41-419e-834c-e5b32a99ae03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66003664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.66003664
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1301097731
Short name T307
Test name
Test status
Simulation time 306831339 ps
CPU time 0.97 seconds
Started Jul 03 05:55:51 PM PDT 24
Finished Jul 03 05:55:52 PM PDT 24
Peak memory 183724 kb
Host smart-20019dec-f2f6-44c3-a86d-01fbeacb79a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301097731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1301097731
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1924808228
Short name T383
Test name
Test status
Simulation time 326439777 ps
CPU time 0.66 seconds
Started Jul 03 05:55:53 PM PDT 24
Finished Jul 03 05:55:54 PM PDT 24
Peak memory 183736 kb
Host smart-71f148f7-85ac-4773-bde6-3659cda2c465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924808228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1924808228
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1378326624
Short name T69
Test name
Test status
Simulation time 601517817 ps
CPU time 1.54 seconds
Started Jul 03 05:55:03 PM PDT 24
Finished Jul 03 05:55:04 PM PDT 24
Peak memory 183812 kb
Host smart-6f3cfe76-aa94-4521-bf22-e42a3a927999
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378326624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1378326624
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3295355472
Short name T349
Test name
Test status
Simulation time 7026333342 ps
CPU time 8.62 seconds
Started Jul 03 05:55:01 PM PDT 24
Finished Jul 03 05:55:10 PM PDT 24
Peak memory 192232 kb
Host smart-4ca9342a-0356-47f6-b3b4-186d513f2f1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295355472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3295355472
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3144247800
Short name T413
Test name
Test status
Simulation time 1319289048 ps
CPU time 2.17 seconds
Started Jul 03 05:55:01 PM PDT 24
Finished Jul 03 05:55:04 PM PDT 24
Peak memory 194040 kb
Host smart-91270b9b-7356-45f9-944d-246d87b383f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144247800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3144247800
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1700456695
Short name T369
Test name
Test status
Simulation time 370534640 ps
CPU time 1 seconds
Started Jul 03 05:55:06 PM PDT 24
Finished Jul 03 05:55:08 PM PDT 24
Peak memory 196040 kb
Host smart-b0cc71d2-43c3-4350-8c35-08f8f7503608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700456695 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1700456695
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2389940938
Short name T56
Test name
Test status
Simulation time 446928810 ps
CPU time 1.21 seconds
Started Jul 03 05:55:00 PM PDT 24
Finished Jul 03 05:55:01 PM PDT 24
Peak memory 193332 kb
Host smart-cdc1e704-6c93-4f55-a19c-3489f7037f2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389940938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2389940938
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3969933303
Short name T306
Test name
Test status
Simulation time 437735043 ps
CPU time 0.92 seconds
Started Jul 03 05:54:59 PM PDT 24
Finished Jul 03 05:55:00 PM PDT 24
Peak memory 183752 kb
Host smart-21d53227-a86c-457b-93c3-7e75f8d93101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969933303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3969933303
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1380794591
Short name T365
Test name
Test status
Simulation time 319266407 ps
CPU time 0.97 seconds
Started Jul 03 05:55:00 PM PDT 24
Finished Jul 03 05:55:01 PM PDT 24
Peak memory 183668 kb
Host smart-7d1a6b43-48c0-4a1c-87b2-5669477bc460
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380794591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1380794591
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1293127262
Short name T358
Test name
Test status
Simulation time 378633043 ps
CPU time 1.16 seconds
Started Jul 03 05:54:58 PM PDT 24
Finished Jul 03 05:54:59 PM PDT 24
Peak memory 183728 kb
Host smart-b074486e-5881-478a-8a89-219f7271d841
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293127262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1293127262
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3031453600
Short name T361
Test name
Test status
Simulation time 1353672277 ps
CPU time 1.16 seconds
Started Jul 03 05:55:03 PM PDT 24
Finished Jul 03 05:55:05 PM PDT 24
Peak memory 193040 kb
Host smart-1ab271c6-9aea-4f90-af12-24fcaa2f1b66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031453600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3031453600
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2852393919
Short name T315
Test name
Test status
Simulation time 502933849 ps
CPU time 2.12 seconds
Started Jul 03 05:54:53 PM PDT 24
Finished Jul 03 05:54:55 PM PDT 24
Peak memory 198636 kb
Host smart-512ed12a-2c5c-4c1f-ae3e-4e4b318fd487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852393919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2852393919
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.413544775
Short name T328
Test name
Test status
Simulation time 4377726082 ps
CPU time 2.34 seconds
Started Jul 03 05:54:53 PM PDT 24
Finished Jul 03 05:54:55 PM PDT 24
Peak memory 197920 kb
Host smart-515fa410-0ce9-4e4c-83ca-14779050f4f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413544775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.413544775
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3502096493
Short name T296
Test name
Test status
Simulation time 284350959 ps
CPU time 0.73 seconds
Started Jul 03 05:55:52 PM PDT 24
Finished Jul 03 05:55:53 PM PDT 24
Peak memory 183728 kb
Host smart-3185d05e-1b4b-43c5-a571-57d81ad9b669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502096493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3502096493
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.375336258
Short name T337
Test name
Test status
Simulation time 415982409 ps
CPU time 1.14 seconds
Started Jul 03 05:55:53 PM PDT 24
Finished Jul 03 05:55:55 PM PDT 24
Peak memory 183744 kb
Host smart-a5fe57d1-a5cf-4e66-93a3-4a0974c4aba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375336258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.375336258
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1926626235
Short name T387
Test name
Test status
Simulation time 280537513 ps
CPU time 0.74 seconds
Started Jul 03 05:55:51 PM PDT 24
Finished Jul 03 05:55:52 PM PDT 24
Peak memory 183728 kb
Host smart-d6aaf2db-3973-4625-847a-0b24b009da54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926626235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1926626235
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.88780415
Short name T326
Test name
Test status
Simulation time 302185230 ps
CPU time 1.01 seconds
Started Jul 03 05:55:52 PM PDT 24
Finished Jul 03 05:55:54 PM PDT 24
Peak memory 183648 kb
Host smart-2e7f0b11-4321-4c3f-ba72-24dca074f680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88780415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.88780415
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.4019736127
Short name T412
Test name
Test status
Simulation time 491723519 ps
CPU time 1.2 seconds
Started Jul 03 05:55:54 PM PDT 24
Finished Jul 03 05:55:56 PM PDT 24
Peak memory 183744 kb
Host smart-cd346c68-bb91-44d8-ba99-87281d1ef603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019736127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.4019736127
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3313290845
Short name T318
Test name
Test status
Simulation time 322744873 ps
CPU time 0.64 seconds
Started Jul 03 05:55:57 PM PDT 24
Finished Jul 03 05:55:58 PM PDT 24
Peak memory 192964 kb
Host smart-dd22fe92-e9e9-4bbb-bb36-d065bbef82c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313290845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3313290845
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1805429982
Short name T322
Test name
Test status
Simulation time 347635668 ps
CPU time 1.15 seconds
Started Jul 03 05:55:58 PM PDT 24
Finished Jul 03 05:56:00 PM PDT 24
Peak memory 183736 kb
Host smart-6bfb2404-7eef-4208-81a6-b2e5d67cb690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805429982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1805429982
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2252405852
Short name T421
Test name
Test status
Simulation time 428037602 ps
CPU time 0.64 seconds
Started Jul 03 05:55:55 PM PDT 24
Finished Jul 03 05:55:56 PM PDT 24
Peak memory 183768 kb
Host smart-32ab7000-6bc2-4ff0-8f8d-eba0ef52be2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252405852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2252405852
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.341256509
Short name T341
Test name
Test status
Simulation time 465839023 ps
CPU time 0.73 seconds
Started Jul 03 05:55:57 PM PDT 24
Finished Jul 03 05:55:58 PM PDT 24
Peak memory 183740 kb
Host smart-a5abcb5c-5797-4ae8-a757-1e09a09c172f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341256509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.341256509
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1071358493
Short name T308
Test name
Test status
Simulation time 555536586 ps
CPU time 0.66 seconds
Started Jul 03 05:55:57 PM PDT 24
Finished Jul 03 05:55:58 PM PDT 24
Peak memory 183752 kb
Host smart-ba3a0529-5a9c-4697-8001-77ffa31fa90f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071358493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1071358493
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3786323905
Short name T399
Test name
Test status
Simulation time 617614783 ps
CPU time 1.12 seconds
Started Jul 03 05:55:13 PM PDT 24
Finished Jul 03 05:55:14 PM PDT 24
Peak memory 193072 kb
Host smart-edc4a898-4fa3-42af-98fd-5be22daebe43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786323905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3786323905
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2774873340
Short name T67
Test name
Test status
Simulation time 6483473726 ps
CPU time 14.31 seconds
Started Jul 03 05:55:03 PM PDT 24
Finished Jul 03 05:55:17 PM PDT 24
Peak memory 192228 kb
Host smart-a1844ef3-ffd4-4e68-9a31-20ca421ffe53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774873340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2774873340
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.210410653
Short name T316
Test name
Test status
Simulation time 1277012988 ps
CPU time 1.59 seconds
Started Jul 03 05:55:02 PM PDT 24
Finished Jul 03 05:55:04 PM PDT 24
Peak memory 183952 kb
Host smart-feb8d7a4-656c-4268-b967-2ed1386fe0f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210410653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.210410653
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3587353566
Short name T416
Test name
Test status
Simulation time 732484461 ps
CPU time 0.89 seconds
Started Jul 03 05:55:04 PM PDT 24
Finished Jul 03 05:55:05 PM PDT 24
Peak memory 198232 kb
Host smart-39cc4ad4-19b9-4d2e-9446-602f99680af7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587353566 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3587353566
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.267474264
Short name T61
Test name
Test status
Simulation time 332920277 ps
CPU time 0.98 seconds
Started Jul 03 05:55:05 PM PDT 24
Finished Jul 03 05:55:07 PM PDT 24
Peak memory 194056 kb
Host smart-638dd848-e7ed-4b00-8f02-9dc6fe2c1bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267474264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.267474264
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2345682262
Short name T376
Test name
Test status
Simulation time 492859335 ps
CPU time 0.64 seconds
Started Jul 03 05:55:02 PM PDT 24
Finished Jul 03 05:55:03 PM PDT 24
Peak memory 183728 kb
Host smart-cf7cfb3c-d41b-48c5-b7da-fe2907022eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345682262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2345682262
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3301089285
Short name T282
Test name
Test status
Simulation time 380542042 ps
CPU time 1.06 seconds
Started Jul 03 05:55:13 PM PDT 24
Finished Jul 03 05:55:14 PM PDT 24
Peak memory 183640 kb
Host smart-91cce5f3-fc45-4779-9a05-de89c2493bb2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301089285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3301089285
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3078608662
Short name T359
Test name
Test status
Simulation time 366040890 ps
CPU time 0.55 seconds
Started Jul 03 05:55:04 PM PDT 24
Finished Jul 03 05:55:05 PM PDT 24
Peak memory 183728 kb
Host smart-f05be7b7-171d-4f5e-be66-1d76ff6ac4f8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078608662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3078608662
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3209631325
Short name T374
Test name
Test status
Simulation time 2083391233 ps
CPU time 3.12 seconds
Started Jul 03 05:55:03 PM PDT 24
Finished Jul 03 05:55:07 PM PDT 24
Peak memory 195052 kb
Host smart-76a79910-9c7c-44e5-86e0-1232bee4bb69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209631325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3209631325
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4200581594
Short name T280
Test name
Test status
Simulation time 652446247 ps
CPU time 1.72 seconds
Started Jul 03 05:55:06 PM PDT 24
Finished Jul 03 05:55:08 PM PDT 24
Peak memory 198656 kb
Host smart-a5a46129-b9a5-487d-8cb4-9d1dd0b72809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200581594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4200581594
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.588126762
Short name T197
Test name
Test status
Simulation time 8453984262 ps
CPU time 3.77 seconds
Started Jul 03 05:55:02 PM PDT 24
Finished Jul 03 05:55:06 PM PDT 24
Peak memory 198184 kb
Host smart-e5d749a7-c575-4d98-ab3d-b8f34400c3b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588126762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.588126762
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4209070607
Short name T348
Test name
Test status
Simulation time 285704025 ps
CPU time 0.73 seconds
Started Jul 03 05:55:57 PM PDT 24
Finished Jul 03 05:55:58 PM PDT 24
Peak memory 183720 kb
Host smart-ad49bc97-204b-4419-9cad-3b1e346e8d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209070607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4209070607
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2955067489
Short name T351
Test name
Test status
Simulation time 300679458 ps
CPU time 1.01 seconds
Started Jul 03 05:56:00 PM PDT 24
Finished Jul 03 05:56:01 PM PDT 24
Peak memory 183752 kb
Host smart-e642c7f9-91d1-475e-8c14-db3ec0817105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955067489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2955067489
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3816431559
Short name T405
Test name
Test status
Simulation time 423620261 ps
CPU time 0.87 seconds
Started Jul 03 05:56:00 PM PDT 24
Finished Jul 03 05:56:02 PM PDT 24
Peak memory 192940 kb
Host smart-e1a7c51f-7a88-45bd-b2bd-25d91a093104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816431559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3816431559
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2486128241
Short name T353
Test name
Test status
Simulation time 344060809 ps
CPU time 0.97 seconds
Started Jul 03 05:56:00 PM PDT 24
Finished Jul 03 05:56:01 PM PDT 24
Peak memory 183752 kb
Host smart-65c77d24-ff63-401d-9aa7-04fb9befb0b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486128241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2486128241
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3126190471
Short name T403
Test name
Test status
Simulation time 419898002 ps
CPU time 1.09 seconds
Started Jul 03 05:56:00 PM PDT 24
Finished Jul 03 05:56:01 PM PDT 24
Peak memory 193000 kb
Host smart-aca7569a-7523-4c38-ab40-637c81bf1852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126190471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3126190471
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1080334299
Short name T311
Test name
Test status
Simulation time 541579969 ps
CPU time 0.63 seconds
Started Jul 03 05:56:00 PM PDT 24
Finished Jul 03 05:56:01 PM PDT 24
Peak memory 183736 kb
Host smart-c1311ce9-2e64-446f-859d-eb260fddde9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080334299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1080334299
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.301053429
Short name T283
Test name
Test status
Simulation time 338338575 ps
CPU time 0.8 seconds
Started Jul 03 05:56:01 PM PDT 24
Finished Jul 03 05:56:02 PM PDT 24
Peak memory 183716 kb
Host smart-7f2946f6-5e9c-4d8e-867a-1f12905968c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301053429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.301053429
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.18991323
Short name T325
Test name
Test status
Simulation time 336209795 ps
CPU time 0.65 seconds
Started Jul 03 05:56:01 PM PDT 24
Finished Jul 03 05:56:01 PM PDT 24
Peak memory 192964 kb
Host smart-63b640f3-3417-431b-9ede-01fc2ab8a95b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18991323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.18991323
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2775072615
Short name T319
Test name
Test status
Simulation time 515684358 ps
CPU time 0.7 seconds
Started Jul 03 05:56:04 PM PDT 24
Finished Jul 03 05:56:05 PM PDT 24
Peak memory 183744 kb
Host smart-903fc29c-110d-47b7-bc09-9bdfeeb43f41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775072615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2775072615
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2580552553
Short name T300
Test name
Test status
Simulation time 340846614 ps
CPU time 0.61 seconds
Started Jul 03 05:56:05 PM PDT 24
Finished Jul 03 05:56:06 PM PDT 24
Peak memory 183736 kb
Host smart-b5adaf1b-f8d0-42a5-ae94-07a91acfe3a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580552553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2580552553
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1750906176
Short name T402
Test name
Test status
Simulation time 337318605 ps
CPU time 0.88 seconds
Started Jul 03 05:55:08 PM PDT 24
Finished Jul 03 05:55:09 PM PDT 24
Peak memory 195976 kb
Host smart-e8903bed-28a6-4d5e-b96c-02f57ef3ac8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750906176 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1750906176
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3733948404
Short name T396
Test name
Test status
Simulation time 472256875 ps
CPU time 0.77 seconds
Started Jul 03 05:55:08 PM PDT 24
Finished Jul 03 05:55:09 PM PDT 24
Peak memory 193424 kb
Host smart-cbc1e45a-1d28-47ee-b57d-89fbf91e6a02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733948404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3733948404
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.270614755
Short name T338
Test name
Test status
Simulation time 307832580 ps
CPU time 0.69 seconds
Started Jul 03 05:55:06 PM PDT 24
Finished Jul 03 05:55:07 PM PDT 24
Peak memory 183768 kb
Host smart-1e13ef8c-dd3d-4816-8c0c-5c7f630c3138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270614755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.270614755
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3920915380
Short name T339
Test name
Test status
Simulation time 877346652 ps
CPU time 2.37 seconds
Started Jul 03 05:55:07 PM PDT 24
Finished Jul 03 05:55:09 PM PDT 24
Peak memory 193032 kb
Host smart-02d7ddc3-47b6-445b-9ece-ba577da6f2a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920915380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3920915380
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2355831047
Short name T346
Test name
Test status
Simulation time 479555944 ps
CPU time 1.97 seconds
Started Jul 03 05:55:06 PM PDT 24
Finished Jul 03 05:55:08 PM PDT 24
Peak memory 198604 kb
Host smart-f8c4d6e5-c7ce-4527-b987-6345da0ed03d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355831047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2355831047
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.363639958
Short name T198
Test name
Test status
Simulation time 8121134079 ps
CPU time 4.17 seconds
Started Jul 03 05:55:03 PM PDT 24
Finished Jul 03 05:55:08 PM PDT 24
Peak memory 198344 kb
Host smart-3121c118-2fa8-45f7-a2ac-0cfbc48dd952
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363639958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.363639958
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4151333779
Short name T372
Test name
Test status
Simulation time 564152169 ps
CPU time 1.1 seconds
Started Jul 03 05:55:11 PM PDT 24
Finished Jul 03 05:55:12 PM PDT 24
Peak memory 196616 kb
Host smart-79be013f-8fdb-4e68-845a-1a31952dee4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151333779 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.4151333779
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1128152970
Short name T64
Test name
Test status
Simulation time 290456026 ps
CPU time 0.82 seconds
Started Jul 03 05:55:08 PM PDT 24
Finished Jul 03 05:55:09 PM PDT 24
Peak memory 193444 kb
Host smart-fbc5842d-0225-461e-8578-c98b01e1162f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128152970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1128152970
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2806930878
Short name T356
Test name
Test status
Simulation time 312260699 ps
CPU time 0.63 seconds
Started Jul 03 05:55:06 PM PDT 24
Finished Jul 03 05:55:07 PM PDT 24
Peak memory 183744 kb
Host smart-fd75ee56-6b18-4dcf-a7db-10f9bfbba6d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806930878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2806930878
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.260268342
Short name T323
Test name
Test status
Simulation time 1361586580 ps
CPU time 0.86 seconds
Started Jul 03 05:55:09 PM PDT 24
Finished Jul 03 05:55:10 PM PDT 24
Peak memory 193020 kb
Host smart-f0976593-d6c3-432e-8c05-97e83aab955f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260268342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.260268342
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.485530362
Short name T360
Test name
Test status
Simulation time 401232705 ps
CPU time 2.25 seconds
Started Jul 03 05:55:06 PM PDT 24
Finished Jul 03 05:55:09 PM PDT 24
Peak memory 198636 kb
Host smart-514e9a81-cfdb-455d-8045-85b18ee55986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485530362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.485530362
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.451662518
Short name T419
Test name
Test status
Simulation time 7765799185 ps
CPU time 5.67 seconds
Started Jul 03 05:55:07 PM PDT 24
Finished Jul 03 05:55:13 PM PDT 24
Peak memory 198140 kb
Host smart-4d348e7e-d999-4be4-9cd2-321afd04cd5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451662518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.451662518
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2390160355
Short name T392
Test name
Test status
Simulation time 556207117 ps
CPU time 1.4 seconds
Started Jul 03 05:55:16 PM PDT 24
Finished Jul 03 05:55:18 PM PDT 24
Peak memory 196516 kb
Host smart-75763c5e-d51f-438d-9e98-31edaad98d4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390160355 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2390160355
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1905658922
Short name T417
Test name
Test status
Simulation time 350821476 ps
CPU time 0.63 seconds
Started Jul 03 05:55:10 PM PDT 24
Finished Jul 03 05:55:10 PM PDT 24
Peak memory 191928 kb
Host smart-dfe588da-6b36-48aa-b47e-052ca2673fb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905658922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1905658922
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1080322307
Short name T287
Test name
Test status
Simulation time 505232135 ps
CPU time 1.19 seconds
Started Jul 03 05:55:11 PM PDT 24
Finished Jul 03 05:55:13 PM PDT 24
Peak memory 183648 kb
Host smart-99247d16-4ca7-4edb-acaf-bec0446caff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080322307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1080322307
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2434211677
Short name T388
Test name
Test status
Simulation time 2230438943 ps
CPU time 3.3 seconds
Started Jul 03 05:55:11 PM PDT 24
Finished Jul 03 05:55:15 PM PDT 24
Peak memory 195032 kb
Host smart-7ecf7824-93ee-4dab-98d4-ecebad39b8bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434211677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2434211677
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2141815031
Short name T329
Test name
Test status
Simulation time 355645228 ps
CPU time 1.08 seconds
Started Jul 03 05:55:09 PM PDT 24
Finished Jul 03 05:55:10 PM PDT 24
Peak memory 197748 kb
Host smart-2ca30299-2b47-4292-96f4-3add74145721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141815031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2141815031
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1323543635
Short name T196
Test name
Test status
Simulation time 7925520812 ps
CPU time 7.07 seconds
Started Jul 03 05:55:12 PM PDT 24
Finished Jul 03 05:55:19 PM PDT 24
Peak memory 198140 kb
Host smart-c503c827-51b5-414c-bcf1-bea5aa4ea3c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323543635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1323543635
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3540749519
Short name T317
Test name
Test status
Simulation time 641122388 ps
CPU time 0.91 seconds
Started Jul 03 05:55:30 PM PDT 24
Finished Jul 03 05:55:31 PM PDT 24
Peak memory 197144 kb
Host smart-d0beb330-2b81-4172-8f5d-e5c87725d5d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540749519 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3540749519
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3997798041
Short name T65
Test name
Test status
Simulation time 511826058 ps
CPU time 1.19 seconds
Started Jul 03 05:55:17 PM PDT 24
Finished Jul 03 05:55:19 PM PDT 24
Peak memory 194024 kb
Host smart-2f71edfb-a66d-475a-8c81-f38ed69e452a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997798041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3997798041
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4021126093
Short name T407
Test name
Test status
Simulation time 428581685 ps
CPU time 0.81 seconds
Started Jul 03 05:55:20 PM PDT 24
Finished Jul 03 05:55:21 PM PDT 24
Peak memory 183724 kb
Host smart-bbf89954-fab3-4948-96ee-b64cb3b18421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021126093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.4021126093
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.399163242
Short name T28
Test name
Test status
Simulation time 2624052350 ps
CPU time 3.56 seconds
Started Jul 03 05:55:21 PM PDT 24
Finished Jul 03 05:55:25 PM PDT 24
Peak memory 195132 kb
Host smart-1af32236-f47b-4e27-9e18-6594ff50c8bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399163242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.399163242
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.961589095
Short name T301
Test name
Test status
Simulation time 712686981 ps
CPU time 2.61 seconds
Started Jul 03 05:55:14 PM PDT 24
Finished Jul 03 05:55:17 PM PDT 24
Peak memory 198644 kb
Host smart-931ced3c-2a22-4727-af2c-94de7a5e3903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961589095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.961589095
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.517051660
Short name T347
Test name
Test status
Simulation time 8287840407 ps
CPU time 12.44 seconds
Started Jul 03 05:55:15 PM PDT 24
Finished Jul 03 05:55:28 PM PDT 24
Peak memory 198152 kb
Host smart-7bccf206-01e9-4d16-ac86-00ef84fff01b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517051660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.517051660
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3060376979
Short name T312
Test name
Test status
Simulation time 464964079 ps
CPU time 1.3 seconds
Started Jul 03 05:55:31 PM PDT 24
Finished Jul 03 05:55:32 PM PDT 24
Peak memory 196048 kb
Host smart-1e83f022-9724-424e-b07d-77331f89c801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060376979 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3060376979
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.978086080
Short name T68
Test name
Test status
Simulation time 355955031 ps
CPU time 0.98 seconds
Started Jul 03 05:55:31 PM PDT 24
Finished Jul 03 05:55:32 PM PDT 24
Peak memory 193396 kb
Host smart-e74baac5-6740-4ac9-a81b-02ede8b0d4ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978086080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.978086080
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.426800350
Short name T290
Test name
Test status
Simulation time 518911297 ps
CPU time 1.19 seconds
Started Jul 03 05:55:21 PM PDT 24
Finished Jul 03 05:55:22 PM PDT 24
Peak memory 192868 kb
Host smart-34ea0079-f1f5-45a9-bb3b-745f5a014c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426800350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.426800350
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2567626176
Short name T314
Test name
Test status
Simulation time 3016536040 ps
CPU time 6.27 seconds
Started Jul 03 05:55:23 PM PDT 24
Finished Jul 03 05:55:30 PM PDT 24
Peak memory 194296 kb
Host smart-439cd1c1-5178-4a90-bec8-ea480026805e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567626176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2567626176
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2959108267
Short name T350
Test name
Test status
Simulation time 468011525 ps
CPU time 1.64 seconds
Started Jul 03 05:55:19 PM PDT 24
Finished Jul 03 05:55:21 PM PDT 24
Peak memory 198508 kb
Host smart-9299301b-df93-4f3a-b01f-353e4e85d49f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959108267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2959108267
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1867204455
Short name T401
Test name
Test status
Simulation time 8225641001 ps
CPU time 4.15 seconds
Started Jul 03 05:55:20 PM PDT 24
Finished Jul 03 05:55:25 PM PDT 24
Peak memory 198228 kb
Host smart-710a5524-a1df-43b7-902a-eb9bc47c88f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867204455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1867204455
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.571150559
Short name T244
Test name
Test status
Simulation time 10167895475 ps
CPU time 3.83 seconds
Started Jul 03 05:46:14 PM PDT 24
Finished Jul 03 05:46:18 PM PDT 24
Peak memory 191744 kb
Host smart-ffe87987-894d-42cd-aee7-f395c416fad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571150559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.571150559
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.908147633
Short name T216
Test name
Test status
Simulation time 607953680 ps
CPU time 1.49 seconds
Started Jul 03 05:46:18 PM PDT 24
Finished Jul 03 05:46:20 PM PDT 24
Peak memory 196488 kb
Host smart-c85fce41-845f-4b3a-8bd2-4ae1bac755c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908147633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.908147633
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.889366590
Short name T229
Test name
Test status
Simulation time 11632642841 ps
CPU time 4.93 seconds
Started Jul 03 05:46:18 PM PDT 24
Finished Jul 03 05:46:24 PM PDT 24
Peak memory 191676 kb
Host smart-1334865d-86c6-4c19-9b9e-e9a61b259842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889366590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.889366590
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.4003488882
Short name T18
Test name
Test status
Simulation time 4532625821 ps
CPU time 1.29 seconds
Started Jul 03 05:46:22 PM PDT 24
Finished Jul 03 05:46:24 PM PDT 24
Peak memory 215708 kb
Host smart-12eef172-4af8-46ec-86a0-110b2ddafe09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003488882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.4003488882
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1837415689
Short name T269
Test name
Test status
Simulation time 371044658 ps
CPU time 1.11 seconds
Started Jul 03 05:46:18 PM PDT 24
Finished Jul 03 05:46:19 PM PDT 24
Peak memory 191632 kb
Host smart-8a7e13b1-2767-4c2d-a16b-9d8254c57813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837415689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1837415689
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2580627956
Short name T262
Test name
Test status
Simulation time 6765756806 ps
CPU time 8.71 seconds
Started Jul 03 05:46:34 PM PDT 24
Finished Jul 03 05:46:43 PM PDT 24
Peak memory 191752 kb
Host smart-fab1b0e6-f444-4de3-8d24-a661df6159f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580627956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2580627956
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1746524457
Short name T223
Test name
Test status
Simulation time 523208821 ps
CPU time 0.73 seconds
Started Jul 03 05:46:31 PM PDT 24
Finished Jul 03 05:46:32 PM PDT 24
Peak memory 191652 kb
Host smart-9a39ff9d-078a-430d-b358-851a92e641fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746524457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1746524457
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4220828206
Short name T266
Test name
Test status
Simulation time 32996328781 ps
CPU time 49.43 seconds
Started Jul 03 05:46:34 PM PDT 24
Finished Jul 03 05:47:24 PM PDT 24
Peak memory 191724 kb
Host smart-9acd314e-37e1-4659-9a7f-1234747cfa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220828206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4220828206
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1218019768
Short name T259
Test name
Test status
Simulation time 464366543 ps
CPU time 1.28 seconds
Started Jul 03 05:46:34 PM PDT 24
Finished Jul 03 05:46:36 PM PDT 24
Peak memory 196448 kb
Host smart-c60b642a-81d9-43e3-8011-d628b9610b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218019768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1218019768
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1507024032
Short name T49
Test name
Test status
Simulation time 15169781159 ps
CPU time 5.95 seconds
Started Jul 03 05:46:34 PM PDT 24
Finished Jul 03 05:46:40 PM PDT 24
Peak memory 196708 kb
Host smart-b010d540-ba1e-43f9-88ae-a2cd8784d9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507024032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1507024032
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2099674981
Short name T202
Test name
Test status
Simulation time 600578872 ps
CPU time 1.37 seconds
Started Jul 03 05:46:33 PM PDT 24
Finished Jul 03 05:46:34 PM PDT 24
Peak memory 191644 kb
Host smart-acc726c8-ec6d-4f78-ba45-585db460f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099674981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2099674981
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2008957874
Short name T218
Test name
Test status
Simulation time 31516392590 ps
CPU time 39.37 seconds
Started Jul 03 05:46:38 PM PDT 24
Finished Jul 03 05:47:17 PM PDT 24
Peak memory 191704 kb
Host smart-dc341ec9-7a73-41ea-9fc0-847dc8a89921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008957874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2008957874
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3139907016
Short name T250
Test name
Test status
Simulation time 486574253 ps
CPU time 0.76 seconds
Started Jul 03 05:46:39 PM PDT 24
Finished Jul 03 05:46:40 PM PDT 24
Peak memory 191668 kb
Host smart-5c62c479-11e9-41e4-98e2-c4cb04f986d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139907016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3139907016
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1372974017
Short name T192
Test name
Test status
Simulation time 583314796 ps
CPU time 1.01 seconds
Started Jul 03 05:46:37 PM PDT 24
Finished Jul 03 05:46:38 PM PDT 24
Peak memory 196464 kb
Host smart-9c0c93c3-1352-46c8-b1d7-725bb2c0ca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372974017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1372974017
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2621606602
Short name T258
Test name
Test status
Simulation time 28014143670 ps
CPU time 37.55 seconds
Started Jul 03 05:46:38 PM PDT 24
Finished Jul 03 05:47:16 PM PDT 24
Peak memory 196748 kb
Host smart-33ac4eef-9ce8-48d1-9757-b703d6c2a3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621606602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2621606602
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2746110792
Short name T274
Test name
Test status
Simulation time 351382821 ps
CPU time 1.03 seconds
Started Jul 03 05:46:37 PM PDT 24
Finished Jul 03 05:46:38 PM PDT 24
Peak memory 191648 kb
Host smart-916d80dc-4ea1-403e-8617-17a3f826f225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746110792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2746110792
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3493522239
Short name T240
Test name
Test status
Simulation time 35876359571 ps
CPU time 52.02 seconds
Started Jul 03 05:46:42 PM PDT 24
Finished Jul 03 05:47:35 PM PDT 24
Peak memory 191744 kb
Host smart-6ff13f56-1466-4bff-87a9-e4c85b6e9488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493522239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3493522239
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3937157340
Short name T255
Test name
Test status
Simulation time 605458071 ps
CPU time 1.03 seconds
Started Jul 03 05:46:40 PM PDT 24
Finished Jul 03 05:46:41 PM PDT 24
Peak memory 191616 kb
Host smart-e077fb3e-df05-4457-aad1-5593094136c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937157340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3937157340
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1915826740
Short name T252
Test name
Test status
Simulation time 34776797486 ps
CPU time 26.88 seconds
Started Jul 03 05:46:44 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 191700 kb
Host smart-7e321b79-be3d-496e-8cb0-96a3203487ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915826740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1915826740
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.455064153
Short name T12
Test name
Test status
Simulation time 430599989 ps
CPU time 0.66 seconds
Started Jul 03 05:46:44 PM PDT 24
Finished Jul 03 05:46:45 PM PDT 24
Peak memory 196456 kb
Host smart-a2fb69fb-9989-4871-8b6d-d719bc65a73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455064153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.455064153
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.507683011
Short name T217
Test name
Test status
Simulation time 37776796956 ps
CPU time 30.42 seconds
Started Jul 03 05:46:43 PM PDT 24
Finished Jul 03 05:47:13 PM PDT 24
Peak memory 191660 kb
Host smart-6c92721b-6917-4723-b48c-2c83c365e129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507683011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.507683011
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4245981222
Short name T276
Test name
Test status
Simulation time 402101349 ps
CPU time 1.18 seconds
Started Jul 03 05:46:43 PM PDT 24
Finished Jul 03 05:46:45 PM PDT 24
Peak memory 196528 kb
Host smart-1dbf7d98-9450-4f07-a9aa-1cd06f3b32a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245981222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4245981222
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3733857060
Short name T47
Test name
Test status
Simulation time 38399510319 ps
CPU time 14.71 seconds
Started Jul 03 05:46:47 PM PDT 24
Finished Jul 03 05:47:02 PM PDT 24
Peak memory 191736 kb
Host smart-83077bf6-0d0b-4230-afa4-e923b496ea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733857060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3733857060
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3811970901
Short name T228
Test name
Test status
Simulation time 485984098 ps
CPU time 1.15 seconds
Started Jul 03 05:46:46 PM PDT 24
Finished Jul 03 05:46:48 PM PDT 24
Peak memory 191628 kb
Host smart-feb47dee-b52d-422d-bbc5-cba296a6071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811970901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3811970901
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.23180775
Short name T54
Test name
Test status
Simulation time 32804842238 ps
CPU time 23.39 seconds
Started Jul 03 05:46:49 PM PDT 24
Finished Jul 03 05:47:12 PM PDT 24
Peak memory 191584 kb
Host smart-138b70c4-2ff9-437d-83c4-e7cf6569d67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23180775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.23180775
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2655605524
Short name T241
Test name
Test status
Simulation time 443989626 ps
CPU time 0.91 seconds
Started Jul 03 05:46:47 PM PDT 24
Finished Jul 03 05:46:49 PM PDT 24
Peak memory 191624 kb
Host smart-386bf06d-7c50-49f7-8798-acbdd6495053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655605524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2655605524
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2326068995
Short name T80
Test name
Test status
Simulation time 23595578966 ps
CPU time 30.36 seconds
Started Jul 03 05:46:20 PM PDT 24
Finished Jul 03 05:46:51 PM PDT 24
Peak memory 191720 kb
Host smart-5d735823-4eec-4ab0-bd6e-a5b72a10db98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326068995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2326068995
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4053757857
Short name T15
Test name
Test status
Simulation time 8046486965 ps
CPU time 3.19 seconds
Started Jul 03 05:46:21 PM PDT 24
Finished Jul 03 05:46:25 PM PDT 24
Peak memory 216016 kb
Host smart-f020c9d7-807d-444b-b6fc-6dd405db0b2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053757857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4053757857
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.856124947
Short name T207
Test name
Test status
Simulation time 417135343 ps
CPU time 1.13 seconds
Started Jul 03 05:46:19 PM PDT 24
Finished Jul 03 05:46:21 PM PDT 24
Peak memory 191660 kb
Host smart-407304db-4f0a-4f83-ab69-ca57d20cd69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856124947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.856124947
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.303926073
Short name T231
Test name
Test status
Simulation time 16353355098 ps
CPU time 20.11 seconds
Started Jul 03 05:46:50 PM PDT 24
Finished Jul 03 05:47:10 PM PDT 24
Peak memory 196712 kb
Host smart-3bcd2007-e8ee-4aec-87a4-b155bc079432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303926073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.303926073
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1164949260
Short name T206
Test name
Test status
Simulation time 421020479 ps
CPU time 0.74 seconds
Started Jul 03 05:46:48 PM PDT 24
Finished Jul 03 05:46:49 PM PDT 24
Peak memory 191676 kb
Host smart-d8d6a6f3-fda0-48b5-8267-ef95b8a94344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164949260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1164949260
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3595576114
Short name T201
Test name
Test status
Simulation time 29353896452 ps
CPU time 42.62 seconds
Started Jul 03 05:46:52 PM PDT 24
Finished Jul 03 05:47:35 PM PDT 24
Peak memory 191692 kb
Host smart-bdaa7f24-898e-4180-8bca-e99aa32fd08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595576114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3595576114
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.296814586
Short name T235
Test name
Test status
Simulation time 383611349 ps
CPU time 0.71 seconds
Started Jul 03 05:46:50 PM PDT 24
Finished Jul 03 05:46:52 PM PDT 24
Peak memory 196500 kb
Host smart-f87fbc8c-d2fa-4256-b4e3-4b9a20b2ffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296814586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.296814586
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1285874294
Short name T275
Test name
Test status
Simulation time 30697010353 ps
CPU time 32.6 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 05:47:27 PM PDT 24
Peak memory 191700 kb
Host smart-5d5bbb9f-26d7-43ff-9325-e5a3c93dd508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285874294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1285874294
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.880360244
Short name T21
Test name
Test status
Simulation time 595717225 ps
CPU time 0.97 seconds
Started Jul 03 05:46:52 PM PDT 24
Finished Jul 03 05:46:53 PM PDT 24
Peak memory 191676 kb
Host smart-46255c30-a816-4c26-a0f7-86df87231dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880360244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.880360244
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3991646864
Short name T272
Test name
Test status
Simulation time 30415765685 ps
CPU time 7.63 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 05:47:01 PM PDT 24
Peak memory 191696 kb
Host smart-a619263f-f702-4adb-a827-3297f776ea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991646864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3991646864
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.449917465
Short name T213
Test name
Test status
Simulation time 441876299 ps
CPU time 0.72 seconds
Started Jul 03 05:46:52 PM PDT 24
Finished Jul 03 05:46:53 PM PDT 24
Peak memory 191680 kb
Host smart-8bbcbe96-6534-49b7-8c32-aae24e2e0e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449917465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.449917465
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2032418137
Short name T10
Test name
Test status
Simulation time 9876454572 ps
CPU time 13.69 seconds
Started Jul 03 05:46:51 PM PDT 24
Finished Jul 03 05:47:05 PM PDT 24
Peak memory 196756 kb
Host smart-22a3ec0f-5be1-4d77-8a30-3057fb7a826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032418137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2032418137
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.422414538
Short name T238
Test name
Test status
Simulation time 421931499 ps
CPU time 0.88 seconds
Started Jul 03 05:46:53 PM PDT 24
Finished Jul 03 05:46:54 PM PDT 24
Peak memory 196508 kb
Host smart-e3c82886-a2ac-40c2-bf99-718636f6847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422414538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.422414538
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3242172452
Short name T209
Test name
Test status
Simulation time 22368108844 ps
CPU time 8.57 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 05:47:03 PM PDT 24
Peak memory 191672 kb
Host smart-6dbc636d-f2b7-4a5a-af40-6647f6688cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242172452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3242172452
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3665422510
Short name T264
Test name
Test status
Simulation time 358566037 ps
CPU time 0.79 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 05:46:55 PM PDT 24
Peak memory 191612 kb
Host smart-0c8a4c38-6169-4523-9932-86dd8bcc2244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665422510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3665422510
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3172466925
Short name T220
Test name
Test status
Simulation time 19532804986 ps
CPU time 5.95 seconds
Started Jul 03 05:46:56 PM PDT 24
Finished Jul 03 05:47:03 PM PDT 24
Peak memory 191696 kb
Host smart-25167bed-7165-43a0-b578-98732d6627e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172466925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3172466925
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1572628073
Short name T260
Test name
Test status
Simulation time 431232664 ps
CPU time 1.09 seconds
Started Jul 03 05:46:54 PM PDT 24
Finished Jul 03 05:46:55 PM PDT 24
Peak memory 191640 kb
Host smart-c7c91427-c6dd-4bbf-87ca-e1bf8092a432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572628073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1572628073
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3845112760
Short name T187
Test name
Test status
Simulation time 492346640 ps
CPU time 1.26 seconds
Started Jul 03 05:46:55 PM PDT 24
Finished Jul 03 05:46:56 PM PDT 24
Peak memory 196376 kb
Host smart-31f3143e-61c3-46d6-be84-2076198d52dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845112760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3845112760
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2088054850
Short name T233
Test name
Test status
Simulation time 12871533936 ps
CPU time 18.83 seconds
Started Jul 03 05:46:55 PM PDT 24
Finished Jul 03 05:47:14 PM PDT 24
Peak memory 196720 kb
Host smart-df188b5a-cf8f-4fe9-95be-2631c3327712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088054850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2088054850
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.235687846
Short name T7
Test name
Test status
Simulation time 613544219 ps
CPU time 0.77 seconds
Started Jul 03 05:46:56 PM PDT 24
Finished Jul 03 05:46:57 PM PDT 24
Peak memory 191680 kb
Host smart-dceab8ae-e323-4720-ad91-fa28f7d43937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235687846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.235687846
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2358239285
Short name T178
Test name
Test status
Simulation time 590908388 ps
CPU time 1.02 seconds
Started Jul 03 05:46:56 PM PDT 24
Finished Jul 03 05:46:57 PM PDT 24
Peak memory 196388 kb
Host smart-05f90469-5fe0-4084-adeb-c441920cc8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358239285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2358239285
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.974313109
Short name T26
Test name
Test status
Simulation time 45570276630 ps
CPU time 18.51 seconds
Started Jul 03 05:46:55 PM PDT 24
Finished Jul 03 05:47:14 PM PDT 24
Peak memory 191704 kb
Host smart-9bb7221e-e997-4588-aa00-42b44437f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974313109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.974313109
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.128796065
Short name T263
Test name
Test status
Simulation time 401020699 ps
CPU time 1.13 seconds
Started Jul 03 05:46:56 PM PDT 24
Finished Jul 03 05:46:57 PM PDT 24
Peak memory 191640 kb
Host smart-4cb8af21-6247-40fd-985d-03755f49455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128796065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.128796065
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3332625029
Short name T50
Test name
Test status
Simulation time 15664521569 ps
CPU time 24.21 seconds
Started Jul 03 05:46:56 PM PDT 24
Finished Jul 03 05:47:20 PM PDT 24
Peak memory 191752 kb
Host smart-2d4006e8-6b40-44d6-abd6-d3f939355bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332625029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3332625029
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3917395570
Short name T214
Test name
Test status
Simulation time 583072618 ps
CPU time 0.79 seconds
Started Jul 03 05:46:56 PM PDT 24
Finished Jul 03 05:46:57 PM PDT 24
Peak memory 191668 kb
Host smart-b5928b1a-f0f5-4e7d-b2c2-f532b0463be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917395570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3917395570
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.640113810
Short name T237
Test name
Test status
Simulation time 51237370702 ps
CPU time 80.75 seconds
Started Jul 03 05:46:26 PM PDT 24
Finished Jul 03 05:47:47 PM PDT 24
Peak memory 191704 kb
Host smart-f9c60eda-615f-4fa2-accf-ce7a4e8f2643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640113810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.640113810
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.985729127
Short name T17
Test name
Test status
Simulation time 4185767226 ps
CPU time 2.82 seconds
Started Jul 03 05:46:24 PM PDT 24
Finished Jul 03 05:46:28 PM PDT 24
Peak memory 215356 kb
Host smart-fda1083a-6cdb-4198-9848-ca07b897b8b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985729127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.985729127
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3814045730
Short name T246
Test name
Test status
Simulation time 696385878 ps
CPU time 0.63 seconds
Started Jul 03 05:46:27 PM PDT 24
Finished Jul 03 05:46:29 PM PDT 24
Peak memory 191656 kb
Host smart-5003f05b-fc06-46e5-baa8-ec79cac57f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814045730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3814045730
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.995302497
Short name T77
Test name
Test status
Simulation time 5953997744 ps
CPU time 2.83 seconds
Started Jul 03 05:47:03 PM PDT 24
Finished Jul 03 05:47:06 PM PDT 24
Peak memory 191736 kb
Host smart-f4d5c2c5-affb-4738-bcb4-852b215a4251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995302497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.995302497
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.784612720
Short name T239
Test name
Test status
Simulation time 599659760 ps
CPU time 1.34 seconds
Started Jul 03 05:47:00 PM PDT 24
Finished Jul 03 05:47:02 PM PDT 24
Peak memory 191636 kb
Host smart-21f0861a-92a9-4c57-88d5-8ffaf047095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784612720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.784612720
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.4008690801
Short name T279
Test name
Test status
Simulation time 12412100936 ps
CPU time 16.46 seconds
Started Jul 03 05:47:00 PM PDT 24
Finished Jul 03 05:47:17 PM PDT 24
Peak memory 191736 kb
Host smart-56dff522-50e9-446d-9727-541f3c1806d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008690801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.4008690801
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2501994452
Short name T97
Test name
Test status
Simulation time 438999120 ps
CPU time 0.65 seconds
Started Jul 03 05:47:00 PM PDT 24
Finished Jul 03 05:47:01 PM PDT 24
Peak memory 191596 kb
Host smart-72818f61-32d8-45a7-95ff-ad5de6726e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501994452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2501994452
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2382029266
Short name T226
Test name
Test status
Simulation time 36046007099 ps
CPU time 56.2 seconds
Started Jul 03 05:47:03 PM PDT 24
Finished Jul 03 05:48:00 PM PDT 24
Peak memory 191740 kb
Host smart-a7ede1b3-14ea-414c-813a-3b90de11b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382029266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2382029266
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1637646662
Short name T208
Test name
Test status
Simulation time 486865884 ps
CPU time 1.17 seconds
Started Jul 03 05:47:01 PM PDT 24
Finished Jul 03 05:47:02 PM PDT 24
Peak memory 191668 kb
Host smart-65d1bbf9-47b4-46e2-bbe7-7d351cbc33e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637646662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1637646662
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3025697009
Short name T41
Test name
Test status
Simulation time 9860251997 ps
CPU time 15.79 seconds
Started Jul 03 05:47:03 PM PDT 24
Finished Jul 03 05:47:19 PM PDT 24
Peak memory 191720 kb
Host smart-a52b22f5-29f0-4d9d-b8de-9a0a2117ea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025697009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3025697009
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1873039960
Short name T249
Test name
Test status
Simulation time 392406706 ps
CPU time 0.9 seconds
Started Jul 03 05:47:02 PM PDT 24
Finished Jul 03 05:47:03 PM PDT 24
Peak memory 191624 kb
Host smart-2270577f-d68a-4b04-8010-186f221cdda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873039960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1873039960
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3829798860
Short name T256
Test name
Test status
Simulation time 5943087853 ps
CPU time 7.89 seconds
Started Jul 03 05:47:02 PM PDT 24
Finished Jul 03 05:47:10 PM PDT 24
Peak memory 191732 kb
Host smart-7970b703-3630-427b-9f84-1ed8be6fb1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829798860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3829798860
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2177025129
Short name T98
Test name
Test status
Simulation time 594181125 ps
CPU time 1.3 seconds
Started Jul 03 05:47:08 PM PDT 24
Finished Jul 03 05:47:10 PM PDT 24
Peak memory 191664 kb
Host smart-3cc6b497-a960-40fd-b167-faa450a6344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177025129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2177025129
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3463122470
Short name T180
Test name
Test status
Simulation time 521268718 ps
CPU time 1.28 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:47:10 PM PDT 24
Peak memory 196452 kb
Host smart-2858f41d-2e9b-4707-a920-4091d58e3bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463122470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3463122470
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4063828507
Short name T219
Test name
Test status
Simulation time 33601455623 ps
CPU time 26.8 seconds
Started Jul 03 05:47:04 PM PDT 24
Finished Jul 03 05:47:31 PM PDT 24
Peak memory 191708 kb
Host smart-c9aa2780-1fe7-4ef2-b381-7caf048293e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063828507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4063828507
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1679522693
Short name T261
Test name
Test status
Simulation time 397126706 ps
CPU time 1.13 seconds
Started Jul 03 05:47:05 PM PDT 24
Finished Jul 03 05:47:07 PM PDT 24
Peak memory 191624 kb
Host smart-6911b756-6e59-40cf-aa42-8193627a77bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679522693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1679522693
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.548264831
Short name T251
Test name
Test status
Simulation time 39342560929 ps
CPU time 29.16 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:47:38 PM PDT 24
Peak memory 196728 kb
Host smart-81b47971-80fd-4bf0-8762-ded5f2201559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548264831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.548264831
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.230791473
Short name T200
Test name
Test status
Simulation time 429951121 ps
CPU time 0.81 seconds
Started Jul 03 05:47:03 PM PDT 24
Finished Jul 03 05:47:04 PM PDT 24
Peak memory 191652 kb
Host smart-172a6c6b-46bc-4d27-b0e1-29cbd48716dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230791473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.230791473
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.835830719
Short name T211
Test name
Test status
Simulation time 26923909766 ps
CPU time 38.08 seconds
Started Jul 03 05:47:02 PM PDT 24
Finished Jul 03 05:47:41 PM PDT 24
Peak memory 191740 kb
Host smart-e46a0d73-945e-4e9f-bf7c-50f32169e2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835830719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.835830719
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1004027592
Short name T253
Test name
Test status
Simulation time 484215324 ps
CPU time 0.75 seconds
Started Jul 03 05:47:03 PM PDT 24
Finished Jul 03 05:47:04 PM PDT 24
Peak memory 191664 kb
Host smart-6af0f254-5716-4f66-813b-fb0be4f2b1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004027592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1004027592
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.260123987
Short name T191
Test name
Test status
Simulation time 435954505 ps
CPU time 1.2 seconds
Started Jul 03 05:47:16 PM PDT 24
Finished Jul 03 05:47:18 PM PDT 24
Peak memory 196440 kb
Host smart-0cbc1dbc-48c7-4896-bfe5-b09a44c4397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260123987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.260123987
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1734577905
Short name T248
Test name
Test status
Simulation time 47734136807 ps
CPU time 61.33 seconds
Started Jul 03 05:47:10 PM PDT 24
Finished Jul 03 05:48:12 PM PDT 24
Peak memory 191664 kb
Host smart-ca0696a8-108a-44d4-a363-ce649ca31b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734577905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1734577905
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3185304670
Short name T227
Test name
Test status
Simulation time 538621656 ps
CPU time 0.8 seconds
Started Jul 03 05:47:10 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 191636 kb
Host smart-6dba5f37-d839-4b55-aa35-2900cbb1e5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185304670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3185304670
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2630281062
Short name T254
Test name
Test status
Simulation time 31435145902 ps
CPU time 22.77 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:47:32 PM PDT 24
Peak memory 191700 kb
Host smart-fba3d0c5-90c4-4546-a599-a7a365ecd2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630281062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2630281062
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2719800468
Short name T212
Test name
Test status
Simulation time 529185834 ps
CPU time 1.38 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 196492 kb
Host smart-baa32ee0-20e9-466e-ba63-daf3840bf4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719800468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2719800468
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3404084868
Short name T183
Test name
Test status
Simulation time 25675339988 ps
CPU time 135.43 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:49:25 PM PDT 24
Peak memory 198416 kb
Host smart-1f2fe1d0-9b8e-42f0-aaec-59f15feebe16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404084868 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3404084868
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3382310314
Short name T84
Test name
Test status
Simulation time 531370468 ps
CPU time 1.32 seconds
Started Jul 03 05:46:24 PM PDT 24
Finished Jul 03 05:46:26 PM PDT 24
Peak memory 196464 kb
Host smart-194b08f4-0521-48e4-b0fc-912900353bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382310314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3382310314
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2096236
Short name T55
Test name
Test status
Simulation time 34464977358 ps
CPU time 23.74 seconds
Started Jul 03 05:46:28 PM PDT 24
Finished Jul 03 05:46:52 PM PDT 24
Peak memory 191700 kb
Host smart-82013421-5309-432d-8462-83e30f2e6591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2096236
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2670588742
Short name T14
Test name
Test status
Simulation time 8142604286 ps
CPU time 12.28 seconds
Started Jul 03 05:46:27 PM PDT 24
Finished Jul 03 05:46:40 PM PDT 24
Peak memory 215784 kb
Host smart-fdefe879-248c-4e8a-a761-d611edc4f26b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670588742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2670588742
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3971992940
Short name T245
Test name
Test status
Simulation time 458901068 ps
CPU time 1.13 seconds
Started Jul 03 05:46:25 PM PDT 24
Finished Jul 03 05:46:27 PM PDT 24
Peak memory 191616 kb
Host smart-f5f3a9be-696f-4359-8f1c-529903653c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971992940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3971992940
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1670606571
Short name T215
Test name
Test status
Simulation time 51389953573 ps
CPU time 75.13 seconds
Started Jul 03 05:47:15 PM PDT 24
Finished Jul 03 05:48:31 PM PDT 24
Peak memory 196716 kb
Host smart-347f6466-54b6-40d6-ac66-f429676dcc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670606571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1670606571
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2898733260
Short name T221
Test name
Test status
Simulation time 490145819 ps
CPU time 0.75 seconds
Started Jul 03 05:47:10 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 191596 kb
Host smart-0902e480-68a5-482d-ad1c-46066ad23384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898733260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2898733260
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.953878601
Short name T277
Test name
Test status
Simulation time 7052264076 ps
CPU time 5.75 seconds
Started Jul 03 05:47:16 PM PDT 24
Finished Jul 03 05:47:22 PM PDT 24
Peak memory 191712 kb
Host smart-baa731a7-d6e7-48f1-a8a1-c3a9eb855b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953878601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.953878601
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3510135771
Short name T210
Test name
Test status
Simulation time 530566721 ps
CPU time 0.76 seconds
Started Jul 03 05:47:11 PM PDT 24
Finished Jul 03 05:47:12 PM PDT 24
Peak memory 191596 kb
Host smart-9238396c-4670-4b6f-b360-ebaaf2e89458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510135771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3510135771
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.4223598391
Short name T236
Test name
Test status
Simulation time 5659195209 ps
CPU time 8.04 seconds
Started Jul 03 05:47:06 PM PDT 24
Finished Jul 03 05:47:15 PM PDT 24
Peak memory 196600 kb
Host smart-0cb22ba6-284b-4c79-bf08-997bacf5f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223598391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4223598391
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3617791280
Short name T78
Test name
Test status
Simulation time 390577973 ps
CPU time 0.93 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 196492 kb
Host smart-b32592c3-3313-4eef-b114-6195f0ec0d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617791280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3617791280
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3884997227
Short name T224
Test name
Test status
Simulation time 44731143913 ps
CPU time 66.6 seconds
Started Jul 03 05:47:11 PM PDT 24
Finished Jul 03 05:48:18 PM PDT 24
Peak memory 191704 kb
Host smart-cc2c71f1-0b72-4d9c-8e55-4c5cc5ba1f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884997227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3884997227
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4032919844
Short name T243
Test name
Test status
Simulation time 569570995 ps
CPU time 0.92 seconds
Started Jul 03 05:47:10 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 196524 kb
Host smart-ad0f293d-7ae1-4ec8-9898-43f50a1cb591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032919844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4032919844
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3527366614
Short name T257
Test name
Test status
Simulation time 25991391797 ps
CPU time 10.16 seconds
Started Jul 03 05:47:13 PM PDT 24
Finished Jul 03 05:47:23 PM PDT 24
Peak memory 196664 kb
Host smart-b17ea94e-0bdc-40f5-a25d-9606ac3a490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527366614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3527366614
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2877366663
Short name T79
Test name
Test status
Simulation time 465779738 ps
CPU time 0.96 seconds
Started Jul 03 05:47:09 PM PDT 24
Finished Jul 03 05:47:11 PM PDT 24
Peak memory 196460 kb
Host smart-1d13ca11-e953-4916-971a-4e7702206df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877366663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2877366663
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.677707017
Short name T100
Test name
Test status
Simulation time 53903197788 ps
CPU time 78.38 seconds
Started Jul 03 05:47:11 PM PDT 24
Finished Jul 03 05:48:30 PM PDT 24
Peak memory 196652 kb
Host smart-d14b6ef6-2b54-44b5-b1c6-d8c8eb0b8eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677707017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.677707017
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.714466218
Short name T267
Test name
Test status
Simulation time 372147333 ps
CPU time 1.09 seconds
Started Jul 03 05:47:11 PM PDT 24
Finished Jul 03 05:47:12 PM PDT 24
Peak memory 196420 kb
Host smart-947b3963-ddc8-4796-a990-97ec97ffce14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714466218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.714466218
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1089650645
Short name T171
Test name
Test status
Simulation time 440647999 ps
CPU time 0.74 seconds
Started Jul 03 05:47:21 PM PDT 24
Finished Jul 03 05:47:22 PM PDT 24
Peak memory 196524 kb
Host smart-83379788-cb6a-44ec-8ee0-74a764d51b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089650645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1089650645
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.4248429944
Short name T234
Test name
Test status
Simulation time 53956747474 ps
CPU time 16.36 seconds
Started Jul 03 05:47:21 PM PDT 24
Finished Jul 03 05:47:37 PM PDT 24
Peak memory 196708 kb
Host smart-ab853df8-9a96-4ccf-a20c-8529284359c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248429944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4248429944
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.581049400
Short name T225
Test name
Test status
Simulation time 431003672 ps
CPU time 0.91 seconds
Started Jul 03 05:47:16 PM PDT 24
Finished Jul 03 05:47:18 PM PDT 24
Peak memory 196464 kb
Host smart-27fb5861-bb64-436a-8a59-1604d634ea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581049400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.581049400
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1783465579
Short name T232
Test name
Test status
Simulation time 9366730389 ps
CPU time 3.67 seconds
Started Jul 03 05:47:15 PM PDT 24
Finished Jul 03 05:47:19 PM PDT 24
Peak memory 191716 kb
Host smart-57d6e08a-fe03-41b7-9f8a-5ab4d24fe417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783465579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1783465579
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2121285409
Short name T96
Test name
Test status
Simulation time 462750459 ps
CPU time 1.23 seconds
Started Jul 03 05:47:17 PM PDT 24
Finished Jul 03 05:47:18 PM PDT 24
Peak memory 191668 kb
Host smart-6b0e1854-f42e-4e9e-80b9-6a6a1285f29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121285409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2121285409
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3183818842
Short name T242
Test name
Test status
Simulation time 59686716665 ps
CPU time 43.57 seconds
Started Jul 03 05:47:16 PM PDT 24
Finished Jul 03 05:48:00 PM PDT 24
Peak memory 196728 kb
Host smart-c125c161-4c03-4044-b200-5235f985f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183818842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3183818842
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2282619057
Short name T203
Test name
Test status
Simulation time 386277202 ps
CPU time 0.75 seconds
Started Jul 03 05:47:21 PM PDT 24
Finished Jul 03 05:47:22 PM PDT 24
Peak memory 191640 kb
Host smart-22546ff7-fadd-44df-8cf1-8421a9d43626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282619057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2282619057
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3390946921
Short name T222
Test name
Test status
Simulation time 44858710654 ps
CPU time 64.16 seconds
Started Jul 03 05:47:16 PM PDT 24
Finished Jul 03 05:48:20 PM PDT 24
Peak memory 191756 kb
Host smart-e018a3d7-fea5-4fc1-bdf0-9f4d77a1e1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390946921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3390946921
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.123529211
Short name T278
Test name
Test status
Simulation time 505265413 ps
CPU time 1.17 seconds
Started Jul 03 05:47:17 PM PDT 24
Finished Jul 03 05:47:19 PM PDT 24
Peak memory 196536 kb
Host smart-80db7272-b6d7-4e33-a5fa-de7afff5cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123529211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.123529211
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4009761264
Short name T247
Test name
Test status
Simulation time 58863469755 ps
CPU time 63.39 seconds
Started Jul 03 05:46:27 PM PDT 24
Finished Jul 03 05:47:31 PM PDT 24
Peak memory 196716 kb
Host smart-172fb702-11ad-4d4b-bb88-4c6894e9ab75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009761264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4009761264
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1607065203
Short name T273
Test name
Test status
Simulation time 561170470 ps
CPU time 0.76 seconds
Started Jul 03 05:46:23 PM PDT 24
Finished Jul 03 05:46:24 PM PDT 24
Peak memory 191668 kb
Host smart-4361c008-e299-4a9f-bef6-6ca06ac40d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607065203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1607065203
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.832176436
Short name T271
Test name
Test status
Simulation time 31411982465 ps
CPU time 6.9 seconds
Started Jul 03 05:46:26 PM PDT 24
Finished Jul 03 05:46:34 PM PDT 24
Peak memory 191564 kb
Host smart-4e3f3039-61d4-4623-813d-e4e9884b9563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832176436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.832176436
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.4258419046
Short name T230
Test name
Test status
Simulation time 572099852 ps
CPU time 0.74 seconds
Started Jul 03 05:46:28 PM PDT 24
Finished Jul 03 05:46:29 PM PDT 24
Peak memory 191656 kb
Host smart-bb0f527f-c9a1-4b59-a4fe-926131ac193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258419046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.4258419046
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2528903964
Short name T270
Test name
Test status
Simulation time 52527196808 ps
CPU time 70.44 seconds
Started Jul 03 05:46:28 PM PDT 24
Finished Jul 03 05:47:39 PM PDT 24
Peak memory 191668 kb
Host smart-cb9e94f1-b5e0-48b5-bf54-2a1d1a85d683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528903964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2528903964
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2199994233
Short name T99
Test name
Test status
Simulation time 521816266 ps
CPU time 0.75 seconds
Started Jul 03 05:46:30 PM PDT 24
Finished Jul 03 05:46:31 PM PDT 24
Peak memory 191612 kb
Host smart-be4738e1-f4b0-453e-80ce-7c5304ec1341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199994233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2199994233
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.20650842
Short name T205
Test name
Test status
Simulation time 2690075009 ps
CPU time 4.05 seconds
Started Jul 03 05:46:31 PM PDT 24
Finished Jul 03 05:46:35 PM PDT 24
Peak memory 191684 kb
Host smart-7f616f66-619c-4349-b170-e26ad0e3998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20650842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.20650842
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.4066668583
Short name T204
Test name
Test status
Simulation time 432918448 ps
CPU time 1.14 seconds
Started Jul 03 05:46:31 PM PDT 24
Finished Jul 03 05:46:32 PM PDT 24
Peak memory 196380 kb
Host smart-01ed7789-079d-43e5-8528-a14229a44370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066668583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4066668583
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.899741960
Short name T265
Test name
Test status
Simulation time 20974476475 ps
CPU time 5.95 seconds
Started Jul 03 05:46:32 PM PDT 24
Finished Jul 03 05:46:39 PM PDT 24
Peak memory 191724 kb
Host smart-728786fe-c7f0-414f-b6eb-bb18e61f138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899741960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.899741960
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3397789952
Short name T268
Test name
Test status
Simulation time 592793983 ps
CPU time 0.76 seconds
Started Jul 03 05:46:32 PM PDT 24
Finished Jul 03 05:46:33 PM PDT 24
Peak memory 196448 kb
Host smart-858817ac-4f0a-46aa-afdf-06379ad87af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397789952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3397789952
Directory /workspace/9.aon_timer_smoke/latest
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