Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	27310	1		T1	808		T3	96		T4	12
bark[1]	257	1		T31	21		T166	21		T41	61
bark[2]	491	1		T12	43		T98	26		T99	26
bark[3]	502	1		T109	21		T113	21		T99	229
bark[4]	736	1		T1	21		T44	21		T41	21
bark[5]	387	1		T41	14		T114	51		T99	5
bark[6]	344	1		T3	19		T50	21		T41	31
bark[7]	168	1		T8	42		T76	21		T164	14
bark[8]	291	1		T28	30		T39	30		T147	14
bark[9]	298	1		T1	21		T13	49		T42	133
bark[10]	861	1		T55	21		T123	21		T102	545
bark[11]	570	1		T1	116		T3	26		T30	108
bark[12]	585	1		T39	123		T53	14		T42	195
bark[13]	549	1		T1	131		T31	21		T134	67
bark[14]	454	1		T2	14		T13	21		T134	21
bark[15]	551	1		T11	21		T13	30		T50	21
bark[16]	744	1		T166	78		T137	21		T70	21
bark[17]	443	1		T3	21		T28	21		T30	5
bark[18]	455	1		T3	80		T8	30		T13	21
bark[19]	404	1		T39	89		T40	26		T161	160
bark[20]	750	1		T31	256		T41	21		T134	42
bark[21]	389	1		T11	40		T30	43		T109	69
bark[22]	656	1		T3	21		T30	30		T55	230
bark[23]	453	1		T41	21		T92	227		T145	63
bark[24]	299	1		T44	86		T46	14		T109	21
bark[25]	506	1		T3	21		T11	30		T30	21
bark[26]	215	1		T11	21		T42	21		T76	42
bark[27]	417	1		T100	208		T92	21		T142	21
bark[28]	112	1		T73	21		T101	21		T153	14
bark[29]	209	1		T7	14		T42	21		T70	21
bark[30]	272	1		T31	174		T164	21		T139	21
bark[31]	303	1		T89	14		T109	84		T159	21
bark_0	4419	1		T1	86		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	26838	1		T1	794		T3	117		T4	11
bite[1]	537	1		T98	25		T99	6		T100	207
bite[2]	132	1		T3	26		T8	21		T171	13
bite[3]	263	1		T2	13		T161	159		T99	25
bite[4]	551	1		T7	13		T44	26		T31	255
bite[5]	342	1		T39	30		T42	132		T113	21
bite[6]	332	1		T134	66		T132	21		T118	21
bite[7]	693	1		T1	104		T11	21		T74	13
bite[8]	404	1		T39	88		T137	21		T42	21
bite[9]	164	1		T13	49		T159	21		T140	39
bite[10]	565	1		T30	107		T41	21		T55	208
bite[11]	286	1		T42	72		T114	51		T100	21
bite[12]	294	1		T53	13		T98	82		T76	21
bite[13]	377	1		T70	21		T71	117		T132	21
bite[14]	435	1		T30	30		T132	30		T176	47
bite[15]	801	1		T41	21		T70	21		T99	228
bite[16]	845	1		T50	21		T39	122		T75	13
bite[17]	228	1		T13	31		T134	21		T139	43
bite[18]	510	1		T11	21		T114	55		T76	21
bite[19]	171	1		T41	21		T55	21		T76	40
bite[20]	651	1		T8	21		T89	13		T31	173
bite[21]	444	1		T50	21		T39	142		T41	13
bite[22]	693	1		T3	18		T134	21		T42	21
bite[23]	264	1		T3	21		T11	40		T13	21
bite[24]	292	1		T13	30		T28	30		T31	21
bite[25]	908	1		T1	21		T10	131		T41	21
bite[26]	352	1		T1	21		T11	30		T30	21
bite[27]	255	1		T44	21		T41	60		T113	21
bite[28]	319	1		T1	26		T3	80		T98	21
bite[29]	418	1		T1	89		T12	42		T13	21
bite[30]	490	1		T3	21		T40	26		T109	69
bite[31]	610	1		T1	25		T8	30		T28	21
bite_0	4936	1		T1	103		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38608	1		T1	1183		T2	21		T3	291
auto[1]	6792	1		T28	214		T29	7		T30	222

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	957	1		T1	60		T3	19		T8	24
prescale[1]	778	1		T1	36		T12	83		T28	47
prescale[2]	1603	1		T1	19		T12	47		T28	19
prescale[3]	599	1		T1	19		T10	19		T28	61
prescale[4]	633	1		T1	19		T8	19		T28	93
prescale[5]	1060	1		T13	28		T30	26		T31	19
prescale[6]	745	1		T1	38		T3	23		T30	4
prescale[7]	535	1		T8	19		T10	19		T28	28
prescale[8]	728	1		T9	9		T10	67		T12	72
prescale[9]	694	1		T1	2		T3	23		T28	55
prescale[10]	1070	1		T10	2		T11	29		T12	14
prescale[11]	926	1		T1	45		T10	65		T13	44
prescale[12]	695	1		T1	94		T4	9		T11	32
prescale[13]	1041	1		T1	2		T5	9		T12	2
prescale[14]	534	1		T28	105		T31	9		T40	2
prescale[15]	533	1		T30	19		T40	37		T41	30
prescale[16]	617	1		T1	38		T31	40		T40	44
prescale[17]	663	1		T1	57		T8	83		T13	9
prescale[18]	810	1		T3	23		T44	19		T40	40
prescale[19]	754	1		T12	36		T88	9		T31	2
prescale[20]	431	1		T1	2		T40	40		T41	2
prescale[21]	470	1		T202	9		T42	2		T98	70
prescale[22]	779	1		T6	9		T28	90		T31	78
prescale[23]	515	1		T1	2		T11	19		T30	19
prescale[24]	322	1		T30	2		T137	79		T70	19
prescale[25]	635	1		T28	2		T30	127		T50	19
prescale[26]	710	1		T1	51		T28	42		T30	67
prescale[27]	601	1		T1	149		T12	2		T31	2
prescale[28]	607	1		T1	19		T3	45		T30	12
prescale[29]	352	1		T10	2		T31	31		T41	77
prescale[30]	298	1		T28	24		T44	23		T31	37
prescale[31]	436	1		T8	40		T71	2		T161	57
prescale_0	23269	1		T1	531		T2	21		T3	158

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32878	1		T1	1016		T2	21		T3	204
auto[1]	12522	1		T1	167		T3	87		T4	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	45400	1		T1	1183		T2	21		T3	291

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	26318	1		T1	756		T2	1		T3	135
wkup[1]	349	1		T1	30		T2	15		T10	30
wkup[2]	341	1		T1	21		T137	21		T42	63
wkup[3]	316	1		T41	30		T98	47		T161	47
wkup[4]	302	1		T13	21		T30	21		T41	21
wkup[5]	162	1		T98	21		T114	21		T117	21
wkup[6]	245	1		T10	21		T13	31		T161	26
wkup[7]	327	1		T39	21		T42	15		T70	21
wkup[8]	371	1		T11	21		T28	21		T166	21
wkup[9]	288	1		T1	21		T28	30		T39	30
wkup[10]	243	1		T1	21		T185	15		T132	21
wkup[11]	128	1		T1	20		T55	21		T74	15
wkup[12]	247	1		T11	30		T39	15		T42	21
wkup[13]	309	1		T28	8		T30	21		T42	30
wkup[14]	332	1		T3	20		T7	15		T28	26
wkup[15]	202	1		T10	21		T30	25		T159	21
wkup[16]	172	1		T1	21		T3	21		T109	21
wkup[17]	99	1		T11	21		T101	21		T159	21
wkup[18]	329	1		T28	21		T39	30		T40	26
wkup[19]	234	1		T1	26		T8	30		T44	26
wkup[20]	288	1		T3	21		T41	44		T42	21
wkup[21]	179	1		T10	8		T11	30		T13	21
wkup[22]	248	1		T1	21		T42	8		T75	15
wkup[23]	284	1		T1	21		T39	21		T132	30
wkup[24]	140	1		T30	6		T98	21		T102	21
wkup[25]	224	1		T98	21		T70	35		T99	29
wkup[26]	368	1		T1	26		T13	21		T28	21
wkup[27]	343	1		T10	24		T28	21		T55	21
wkup[28]	217	1		T3	26		T28	21		T50	21
wkup[29]	173	1		T1	21		T31	21		T98	21
wkup[30]	183	1		T116	15		T114	21		T101	21
wkup[31]	232	1		T31	21		T41	21		T134	21
wkup[32]	147	1		T31	30		T41	21		T98	15
wkup[33]	296	1		T31	21		T40	21		T41	35
wkup[34]	316	1		T1	21		T3	21		T31	26
wkup[35]	312	1		T42	51		T55	21		T132	21
wkup[36]	157	1		T3	21		T89	15		T31	21
wkup[37]	214	1		T8	21		T44	21		T31	21
wkup[38]	158	1		T12	21		T41	21		T55	8
wkup[39]	273	1		T31	21		T53	15		T166	21
wkup[40]	281	1		T30	21		T46	15		T41	15
wkup[41]	260	1		T11	21		T44	21		T31	21
wkup[42]	119	1		T1	21		T40	21		T42	41
wkup[43]	250	1		T28	35		T55	21		T161	35
wkup[44]	303	1		T30	21		T44	21		T109	24
wkup[45]	213	1		T8	21		T42	21		T98	51
wkup[46]	254	1		T30	21		T50	21		T42	21
wkup[47]	222	1		T31	21		T39	29		T55	21
wkup[48]	92	1		T28	21		T101	21		T159	29
wkup[49]	229	1		T12	42		T42	35		T98	21
wkup[50]	225	1		T13	21		T42	21		T73	21
wkup[51]	299	1		T3	21		T134	21		T98	15
wkup[52]	233	1		T1	21		T166	21		T134	21
wkup[53]	195	1		T99	21		T101	33		T22	21
wkup[54]	240	1		T44	21		T31	21		T132	30
wkup[55]	383	1		T1	21		T8	21		T41	21
wkup[56]	234	1		T1	21		T13	30		T30	21
wkup[57]	395	1		T8	21		T28	47		T30	21
wkup[58]	184	1		T30	21		T137	29		T147	15
wkup[59]	234	1		T31	21		T39	21		T166	21
wkup[60]	316	1		T30	30		T134	21		T42	21
wkup[61]	128	1		T132	21		T159	21		T102	15
wkup[62]	299	1		T28	21		T31	21		T41	35
wkup[63]	268	1		T10	21		T39	21		T55	30
wkup_0	3478	1		T1	73		T2	5		T3	5