Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
10408 |
1 |
|
T1 |
234 |
|
T3 |
30 |
|
T8 |
28 |
all_values[1] |
10408 |
1 |
|
T1 |
234 |
|
T3 |
30 |
|
T8 |
28 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_intr_en
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER |
[auto[1]] |
0 |
1 |
1 |
Covered bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20816 |
1 |
|
T1 |
468 |
|
T3 |
60 |
|
T8 |
56 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5300 |
1 |
|
T1 |
124 |
|
T3 |
16 |
|
T8 |
12 |
auto[1] |
15516 |
1 |
|
T1 |
344 |
|
T3 |
44 |
|
T8 |
44 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11776 |
1 |
|
T1 |
258 |
|
T3 |
28 |
|
T8 |
32 |
auto[1] |
9040 |
1 |
|
T1 |
210 |
|
T3 |
32 |
|
T8 |
24 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
12 |
6 |
6 |
50.00 |
6 |
Automatically Generated Cross Bins |
12 |
6 |
6 |
50.00 |
6 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Element holes
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER |
* |
[auto[0]] |
[auto[1]] |
* |
-- |
-- |
4 |
* |
[auto[1]] |
[auto[1]] |
[auto[1]] |
-- |
-- |
2 |
Covered bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
2574 |
1 |
|
T1 |
56 |
|
T3 |
8 |
|
T8 |
12 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
3296 |
1 |
|
T1 |
74 |
|
T3 |
8 |
|
T8 |
4 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
4538 |
1 |
|
T1 |
104 |
|
T3 |
14 |
|
T8 |
12 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
2726 |
1 |
|
T1 |
68 |
|
T3 |
8 |
|
T10 |
40 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
3180 |
1 |
|
T1 |
60 |
|
T3 |
4 |
|
T8 |
16 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
4502 |
1 |
|
T1 |
106 |
|
T3 |
18 |
|
T8 |
12 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |