Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.96 99.33 93.67 100.00 98.40 99.51 48.84


Total test records in report: 416
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T278 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2021496597 Jul 04 05:36:13 PM PDT 24 Jul 04 05:36:14 PM PDT 24 407435518 ps
T279 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.761647379 Jul 04 05:36:30 PM PDT 24 Jul 04 05:36:31 PM PDT 24 383007762 ps
T280 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1171508661 Jul 04 05:36:38 PM PDT 24 Jul 04 05:36:39 PM PDT 24 408217726 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1603178116 Jul 04 05:36:02 PM PDT 24 Jul 04 05:36:20 PM PDT 24 12406457759 ps
T79 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1014339552 Jul 04 05:36:24 PM PDT 24 Jul 04 05:36:28 PM PDT 24 1750974243 ps
T80 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1953354512 Jul 04 05:36:18 PM PDT 24 Jul 04 05:36:20 PM PDT 24 1076504857 ps
T281 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1052519609 Jul 04 05:36:04 PM PDT 24 Jul 04 05:36:07 PM PDT 24 536714475 ps
T282 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3212706750 Jul 04 05:36:17 PM PDT 24 Jul 04 05:36:18 PM PDT 24 557461902 ps
T283 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.782104465 Jul 04 05:36:41 PM PDT 24 Jul 04 05:36:42 PM PDT 24 340195061 ps
T81 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3413847234 Jul 04 05:36:21 PM PDT 24 Jul 04 05:36:23 PM PDT 24 1957421715 ps
T284 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.816343118 Jul 04 05:36:43 PM PDT 24 Jul 04 05:36:44 PM PDT 24 440382690 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3967417433 Jul 04 05:36:04 PM PDT 24 Jul 04 05:36:05 PM PDT 24 468250265 ps
T285 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1074172235 Jul 04 05:36:25 PM PDT 24 Jul 04 05:36:26 PM PDT 24 317663683 ps
T286 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3092200982 Jul 04 05:36:29 PM PDT 24 Jul 04 05:36:30 PM PDT 24 462876934 ps
T287 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3329126023 Jul 04 05:36:05 PM PDT 24 Jul 04 05:36:07 PM PDT 24 336607448 ps
T288 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4120898005 Jul 04 05:36:07 PM PDT 24 Jul 04 05:36:08 PM PDT 24 372652228 ps
T289 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1595734158 Jul 04 05:36:33 PM PDT 24 Jul 04 05:36:34 PM PDT 24 562164450 ps
T290 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1124512072 Jul 04 05:36:33 PM PDT 24 Jul 04 05:36:34 PM PDT 24 463724593 ps
T82 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4039512332 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:34 PM PDT 24 3097043811 ps
T291 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1507562388 Jul 04 05:36:40 PM PDT 24 Jul 04 05:36:42 PM PDT 24 318970117 ps
T292 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.749042933 Jul 04 05:36:27 PM PDT 24 Jul 04 05:36:29 PM PDT 24 1624151508 ps
T58 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.314750279 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:33 PM PDT 24 546557891 ps
T293 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1594768218 Jul 04 05:36:39 PM PDT 24 Jul 04 05:36:40 PM PDT 24 546174243 ps
T294 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2191876736 Jul 04 05:35:57 PM PDT 24 Jul 04 05:35:58 PM PDT 24 514231067 ps
T295 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3047918322 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:32 PM PDT 24 504783916 ps
T296 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.463455043 Jul 04 05:35:58 PM PDT 24 Jul 04 05:35:59 PM PDT 24 751405001 ps
T297 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1335972693 Jul 04 05:35:57 PM PDT 24 Jul 04 05:35:58 PM PDT 24 281220673 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3619696785 Jul 04 05:35:59 PM PDT 24 Jul 04 05:36:00 PM PDT 24 418437934 ps
T299 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2249334709 Jul 04 05:36:33 PM PDT 24 Jul 04 05:36:34 PM PDT 24 506736157 ps
T300 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3924584465 Jul 04 05:35:56 PM PDT 24 Jul 04 05:35:57 PM PDT 24 678835840 ps
T301 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3029991565 Jul 04 05:36:32 PM PDT 24 Jul 04 05:36:33 PM PDT 24 628709734 ps
T83 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1531093314 Jul 04 05:35:56 PM PDT 24 Jul 04 05:35:59 PM PDT 24 2526366972 ps
T302 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.202915902 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:32 PM PDT 24 460776166 ps
T303 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.342303390 Jul 04 05:36:27 PM PDT 24 Jul 04 05:36:29 PM PDT 24 604926082 ps
T304 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3039530812 Jul 04 05:35:55 PM PDT 24 Jul 04 05:35:55 PM PDT 24 329058017 ps
T305 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.220413386 Jul 04 05:35:55 PM PDT 24 Jul 04 05:35:56 PM PDT 24 703102675 ps
T306 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3243117864 Jul 04 05:36:40 PM PDT 24 Jul 04 05:36:41 PM PDT 24 372401511 ps
T307 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2801057571 Jul 04 05:36:17 PM PDT 24 Jul 04 05:36:18 PM PDT 24 366283432 ps
T308 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.97037345 Jul 04 05:36:16 PM PDT 24 Jul 04 05:36:18 PM PDT 24 423349161 ps
T309 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4211597240 Jul 04 05:35:59 PM PDT 24 Jul 04 05:36:01 PM PDT 24 457281794 ps
T84 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1527945621 Jul 04 05:36:30 PM PDT 24 Jul 04 05:36:32 PM PDT 24 1213656949 ps
T310 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.786021483 Jul 04 05:36:38 PM PDT 24 Jul 04 05:36:39 PM PDT 24 356759283 ps
T311 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1727039770 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:33 PM PDT 24 591695228 ps
T85 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2690922884 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:37 PM PDT 24 2526083305 ps
T312 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.23640964 Jul 04 05:36:22 PM PDT 24 Jul 04 05:36:23 PM PDT 24 465088648 ps
T313 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3131584810 Jul 04 05:36:28 PM PDT 24 Jul 04 05:36:30 PM PDT 24 2436469528 ps
T314 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1408897884 Jul 04 05:36:03 PM PDT 24 Jul 04 05:36:04 PM PDT 24 464467675 ps
T315 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.163207785 Jul 04 05:36:39 PM PDT 24 Jul 04 05:36:40 PM PDT 24 426649711 ps
T316 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2793909186 Jul 04 05:36:02 PM PDT 24 Jul 04 05:36:04 PM PDT 24 535895708 ps
T317 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.279987979 Jul 04 05:36:16 PM PDT 24 Jul 04 05:36:18 PM PDT 24 2502303135 ps
T318 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.521780308 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:32 PM PDT 24 357557919 ps
T319 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2734469668 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:34 PM PDT 24 598247570 ps
T36 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4167239664 Jul 04 05:36:02 PM PDT 24 Jul 04 05:36:08 PM PDT 24 4264353023 ps
T59 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1159142287 Jul 04 05:36:15 PM PDT 24 Jul 04 05:36:16 PM PDT 24 305973670 ps
T320 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1775624069 Jul 04 05:36:39 PM PDT 24 Jul 04 05:36:40 PM PDT 24 509291741 ps
T321 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.116574648 Jul 04 05:36:32 PM PDT 24 Jul 04 05:36:34 PM PDT 24 518865305 ps
T197 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3194190256 Jul 04 05:36:29 PM PDT 24 Jul 04 05:36:33 PM PDT 24 4347878641 ps
T322 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4189233866 Jul 04 05:36:04 PM PDT 24 Jul 04 05:36:05 PM PDT 24 366051683 ps
T323 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2068345029 Jul 04 05:36:16 PM PDT 24 Jul 04 05:36:18 PM PDT 24 405536684 ps
T60 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3052842267 Jul 04 05:36:10 PM PDT 24 Jul 04 05:36:11 PM PDT 24 465703514 ps
T324 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.927290989 Jul 04 05:36:03 PM PDT 24 Jul 04 05:36:04 PM PDT 24 1313045198 ps
T325 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1716081383 Jul 04 05:35:59 PM PDT 24 Jul 04 05:36:00 PM PDT 24 496119819 ps
T326 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3566062785 Jul 04 05:36:21 PM PDT 24 Jul 04 05:36:22 PM PDT 24 548522437 ps
T198 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2181862119 Jul 04 05:36:30 PM PDT 24 Jul 04 05:36:37 PM PDT 24 8618569693 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2020804796 Jul 04 05:36:10 PM PDT 24 Jul 04 05:36:11 PM PDT 24 461224646 ps
T328 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3355229761 Jul 04 05:36:29 PM PDT 24 Jul 04 05:36:32 PM PDT 24 4469072826 ps
T329 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1715902284 Jul 04 05:36:41 PM PDT 24 Jul 04 05:36:42 PM PDT 24 446500462 ps
T330 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3541020194 Jul 04 05:36:41 PM PDT 24 Jul 04 05:36:42 PM PDT 24 505408096 ps
T331 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3582648284 Jul 04 05:36:20 PM PDT 24 Jul 04 05:36:22 PM PDT 24 453397060 ps
T332 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.487424811 Jul 04 05:36:11 PM PDT 24 Jul 04 05:36:12 PM PDT 24 293606441 ps
T333 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.666834074 Jul 04 05:36:20 PM PDT 24 Jul 04 05:36:22 PM PDT 24 349942623 ps
T334 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3735473291 Jul 04 05:36:32 PM PDT 24 Jul 04 05:36:33 PM PDT 24 500107296 ps
T335 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2652972832 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:32 PM PDT 24 429908108 ps
T336 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1459813122 Jul 04 05:36:07 PM PDT 24 Jul 04 05:36:09 PM PDT 24 433620789 ps
T337 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2009341871 Jul 04 05:36:02 PM PDT 24 Jul 04 05:36:03 PM PDT 24 513127250 ps
T338 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1337229475 Jul 04 05:36:27 PM PDT 24 Jul 04 05:36:39 PM PDT 24 8334573481 ps
T199 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1710613420 Jul 04 05:36:09 PM PDT 24 Jul 04 05:36:16 PM PDT 24 7719508473 ps
T339 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2511298624 Jul 04 05:36:35 PM PDT 24 Jul 04 05:36:37 PM PDT 24 486560674 ps
T340 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2392183068 Jul 04 05:36:04 PM PDT 24 Jul 04 05:36:05 PM PDT 24 319524827 ps
T341 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1516154031 Jul 04 05:36:32 PM PDT 24 Jul 04 05:36:34 PM PDT 24 528488222 ps
T342 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1703494053 Jul 04 05:36:38 PM PDT 24 Jul 04 05:36:39 PM PDT 24 318955906 ps
T61 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3486932670 Jul 04 05:36:24 PM PDT 24 Jul 04 05:36:25 PM PDT 24 492091088 ps
T343 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4232173943 Jul 04 05:36:40 PM PDT 24 Jul 04 05:36:41 PM PDT 24 501729676 ps
T344 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3671568976 Jul 04 05:36:32 PM PDT 24 Jul 04 05:36:35 PM PDT 24 921721367 ps
T345 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1351585395 Jul 04 05:36:37 PM PDT 24 Jul 04 05:36:38 PM PDT 24 421208296 ps
T346 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1569994924 Jul 04 05:36:38 PM PDT 24 Jul 04 05:36:39 PM PDT 24 502913541 ps
T65 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1775473733 Jul 04 05:36:10 PM PDT 24 Jul 04 05:36:11 PM PDT 24 312257075 ps
T347 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3117441788 Jul 04 05:36:24 PM PDT 24 Jul 04 05:36:28 PM PDT 24 2205729287 ps
T200 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1910094860 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:36 PM PDT 24 4084006715 ps
T348 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.358840110 Jul 04 05:36:05 PM PDT 24 Jul 04 05:36:07 PM PDT 24 549734792 ps
T349 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2335231040 Jul 04 05:36:29 PM PDT 24 Jul 04 05:36:33 PM PDT 24 2675568775 ps
T350 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3067871393 Jul 04 05:36:36 PM PDT 24 Jul 04 05:36:38 PM PDT 24 283306707 ps
T351 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1485420546 Jul 04 05:36:12 PM PDT 24 Jul 04 05:36:13 PM PDT 24 519229634 ps
T352 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.617540162 Jul 04 05:36:01 PM PDT 24 Jul 04 05:36:15 PM PDT 24 8517020087 ps
T353 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.749637204 Jul 04 05:36:23 PM PDT 24 Jul 04 05:36:24 PM PDT 24 364878485 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2706931531 Jul 04 05:36:03 PM PDT 24 Jul 04 05:36:04 PM PDT 24 526415267 ps
T354 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2253646865 Jul 04 05:36:16 PM PDT 24 Jul 04 05:36:20 PM PDT 24 3928722104 ps
T201 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2796633029 Jul 04 05:36:16 PM PDT 24 Jul 04 05:36:23 PM PDT 24 8196222933 ps
T355 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3988547322 Jul 04 05:36:30 PM PDT 24 Jul 04 05:36:31 PM PDT 24 288459560 ps
T356 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1062802669 Jul 04 05:36:23 PM PDT 24 Jul 04 05:36:24 PM PDT 24 463550173 ps
T357 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.129759655 Jul 04 05:36:33 PM PDT 24 Jul 04 05:36:34 PM PDT 24 431846953 ps
T358 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.365014817 Jul 04 05:36:11 PM PDT 24 Jul 04 05:36:13 PM PDT 24 1212786529 ps
T359 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4052144945 Jul 04 05:36:04 PM PDT 24 Jul 04 05:36:06 PM PDT 24 778199905 ps
T360 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2931374015 Jul 04 05:36:43 PM PDT 24 Jul 04 05:36:43 PM PDT 24 558827256 ps
T361 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3468567136 Jul 04 05:36:13 PM PDT 24 Jul 04 05:36:15 PM PDT 24 425429582 ps
T362 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1492104066 Jul 04 05:36:23 PM PDT 24 Jul 04 05:36:24 PM PDT 24 458545107 ps
T363 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3532670457 Jul 04 05:35:54 PM PDT 24 Jul 04 05:35:56 PM PDT 24 408358177 ps
T364 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2532476240 Jul 04 05:36:08 PM PDT 24 Jul 04 05:36:09 PM PDT 24 622109061 ps
T365 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2069451683 Jul 04 05:36:26 PM PDT 24 Jul 04 05:36:28 PM PDT 24 357778000 ps
T366 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4012515363 Jul 04 05:36:02 PM PDT 24 Jul 04 05:36:04 PM PDT 24 508606008 ps
T367 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1944660040 Jul 04 05:36:04 PM PDT 24 Jul 04 05:36:06 PM PDT 24 9264651626 ps
T368 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2753349658 Jul 04 05:36:32 PM PDT 24 Jul 04 05:36:33 PM PDT 24 288537414 ps
T369 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3150199498 Jul 04 05:36:41 PM PDT 24 Jul 04 05:36:42 PM PDT 24 453811588 ps
T370 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1063137471 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:32 PM PDT 24 349039139 ps
T371 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4172613841 Jul 04 05:36:26 PM PDT 24 Jul 04 05:36:33 PM PDT 24 8519861321 ps
T372 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2049605474 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:35 PM PDT 24 2257356891 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.407156313 Jul 04 05:35:57 PM PDT 24 Jul 04 05:36:17 PM PDT 24 13862104528 ps
T374 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1238334265 Jul 04 05:36:26 PM PDT 24 Jul 04 05:36:27 PM PDT 24 398271473 ps
T375 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.42236935 Jul 04 05:36:16 PM PDT 24 Jul 04 05:36:20 PM PDT 24 8815705635 ps
T376 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2797289614 Jul 04 05:36:35 PM PDT 24 Jul 04 05:36:36 PM PDT 24 428118056 ps
T377 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2898459310 Jul 04 05:36:25 PM PDT 24 Jul 04 05:36:27 PM PDT 24 450864977 ps
T378 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4037240627 Jul 04 05:36:11 PM PDT 24 Jul 04 05:36:13 PM PDT 24 491395663 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1230968469 Jul 04 05:36:07 PM PDT 24 Jul 04 05:36:08 PM PDT 24 736172484 ps
T379 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.915796212 Jul 04 05:36:04 PM PDT 24 Jul 04 05:36:07 PM PDT 24 1237208825 ps
T68 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1961476203 Jul 04 05:36:30 PM PDT 24 Jul 04 05:36:31 PM PDT 24 346888572 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.794731624 Jul 04 05:36:02 PM PDT 24 Jul 04 05:36:04 PM PDT 24 403315901 ps
T381 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1310805708 Jul 04 05:36:23 PM PDT 24 Jul 04 05:36:37 PM PDT 24 8500567487 ps
T382 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1434652630 Jul 04 05:36:29 PM PDT 24 Jul 04 05:36:32 PM PDT 24 918741383 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2656532388 Jul 04 05:36:16 PM PDT 24 Jul 04 05:36:18 PM PDT 24 1375278845 ps
T384 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3698682812 Jul 04 05:35:58 PM PDT 24 Jul 04 05:35:59 PM PDT 24 2607419305 ps
T385 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1053717757 Jul 04 05:36:18 PM PDT 24 Jul 04 05:36:19 PM PDT 24 424385610 ps
T386 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.798115156 Jul 04 05:36:28 PM PDT 24 Jul 04 05:36:29 PM PDT 24 466011370 ps
T69 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1074573999 Jul 04 05:36:01 PM PDT 24 Jul 04 05:36:04 PM PDT 24 5807362605 ps
T387 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4229359416 Jul 04 05:36:29 PM PDT 24 Jul 04 05:36:41 PM PDT 24 8064733652 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.372219853 Jul 04 05:36:03 PM PDT 24 Jul 04 05:36:04 PM PDT 24 341759618 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.753131488 Jul 04 05:36:11 PM PDT 24 Jul 04 05:36:19 PM PDT 24 7455658915 ps
T63 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.255314368 Jul 04 05:36:16 PM PDT 24 Jul 04 05:36:17 PM PDT 24 526623523 ps
T389 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3292858317 Jul 04 05:36:02 PM PDT 24 Jul 04 05:36:14 PM PDT 24 8035845856 ps
T390 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3643283502 Jul 04 05:36:25 PM PDT 24 Jul 04 05:36:27 PM PDT 24 445088916 ps
T391 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3426795583 Jul 04 05:36:39 PM PDT 24 Jul 04 05:36:40 PM PDT 24 443386021 ps
T392 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1664138576 Jul 04 05:36:30 PM PDT 24 Jul 04 05:36:32 PM PDT 24 403071534 ps
T393 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.729292363 Jul 04 05:36:10 PM PDT 24 Jul 04 05:36:11 PM PDT 24 918370193 ps
T394 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2123217397 Jul 04 05:36:16 PM PDT 24 Jul 04 05:36:17 PM PDT 24 454733491 ps
T395 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.134783548 Jul 04 05:36:37 PM PDT 24 Jul 04 05:36:38 PM PDT 24 476649496 ps
T396 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.728105990 Jul 04 05:36:08 PM PDT 24 Jul 04 05:36:09 PM PDT 24 436419842 ps
T64 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2014343993 Jul 04 05:35:57 PM PDT 24 Jul 04 05:35:58 PM PDT 24 570277045 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2223510885 Jul 04 05:36:01 PM PDT 24 Jul 04 05:36:03 PM PDT 24 449102958 ps
T398 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2295411512 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:33 PM PDT 24 466469792 ps
T399 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1254544828 Jul 04 05:36:25 PM PDT 24 Jul 04 05:36:26 PM PDT 24 592083746 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1392366972 Jul 04 05:36:34 PM PDT 24 Jul 04 05:36:37 PM PDT 24 475667459 ps
T401 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2730522202 Jul 04 05:36:02 PM PDT 24 Jul 04 05:36:05 PM PDT 24 904590633 ps
T402 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1495763426 Jul 04 05:36:28 PM PDT 24 Jul 04 05:36:29 PM PDT 24 362804136 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3669571601 Jul 04 05:36:02 PM PDT 24 Jul 04 05:36:04 PM PDT 24 531557156 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.726328327 Jul 04 05:36:08 PM PDT 24 Jul 04 05:36:10 PM PDT 24 4266564028 ps
T405 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1531744157 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:32 PM PDT 24 599148389 ps
T406 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.958794249 Jul 04 05:36:31 PM PDT 24 Jul 04 05:36:34 PM PDT 24 467465185 ps
T407 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.799481269 Jul 04 05:36:43 PM PDT 24 Jul 04 05:36:44 PM PDT 24 406801186 ps
T408 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1541754668 Jul 04 05:36:37 PM PDT 24 Jul 04 05:36:38 PM PDT 24 422656967 ps
T409 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1189102445 Jul 04 05:36:37 PM PDT 24 Jul 04 05:36:38 PM PDT 24 342748615 ps
T410 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3568516491 Jul 04 05:36:09 PM PDT 24 Jul 04 05:36:10 PM PDT 24 511479840 ps
T411 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.426332127 Jul 04 05:36:07 PM PDT 24 Jul 04 05:36:10 PM PDT 24 2241199441 ps
T412 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.415185144 Jul 04 05:36:24 PM PDT 24 Jul 04 05:36:24 PM PDT 24 488923873 ps
T413 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3477797807 Jul 04 05:36:04 PM PDT 24 Jul 04 05:36:06 PM PDT 24 2118253397 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3120865588 Jul 04 05:36:10 PM PDT 24 Jul 04 05:36:10 PM PDT 24 352168754 ps
T415 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.279363993 Jul 04 05:36:32 PM PDT 24 Jul 04 05:36:34 PM PDT 24 566963219 ps
T416 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2730900810 Jul 04 05:36:26 PM PDT 24 Jul 04 05:36:31 PM PDT 24 3932083751 ps

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3374686043
Short name T1
Test name
Test status
Simulation time 206706888805 ps
CPU time 380.24 seconds
Started Jul 04 05:35:16 PM PDT 24
Finished Jul 04 05:41:36 PM PDT 24
Peak memory 210676 kb
Host smart-cf8ccb7c-df7f-4fe9-83aa-82f91044f068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374686043 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3374686043
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1691401922
Short name T5
Test name
Test status
Simulation time 17827879566 ps
CPU time 6.67 seconds
Started Jul 04 05:35:16 PM PDT 24
Finished Jul 04 05:35:23 PM PDT 24
Peak memory 196916 kb
Host smart-24f06276-8d12-43ff-9be8-36680bd86c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691401922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1691401922
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.538128876
Short name T31
Test name
Test status
Simulation time 142807901952 ps
CPU time 376.55 seconds
Started Jul 04 05:35:49 PM PDT 24
Finished Jul 04 05:42:06 PM PDT 24
Peak memory 214524 kb
Host smart-d00a7ad0-a154-4144-ab64-b38a9b23a1d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538128876 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.538128876
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2762672747
Short name T33
Test name
Test status
Simulation time 7959662024 ps
CPU time 6.58 seconds
Started Jul 04 05:36:27 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 198312 kb
Host smart-92c29620-1e14-4816-b671-c18c4ec28565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762672747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2762672747
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2532592330
Short name T134
Test name
Test status
Simulation time 214890949189 ps
CPU time 312.19 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:40:36 PM PDT 24
Peak memory 198156 kb
Host smart-fcc23e88-7101-4526-aede-ede3e133b85a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532592330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2532592330
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1957217137
Short name T42
Test name
Test status
Simulation time 719952797506 ps
CPU time 287.28 seconds
Started Jul 04 05:35:00 PM PDT 24
Finished Jul 04 05:39:48 PM PDT 24
Peak memory 201376 kb
Host smart-521d4336-5ff3-4062-8fe9-91fadd6aaf2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957217137 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1957217137
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.107458274
Short name T159
Test name
Test status
Simulation time 440880604431 ps
CPU time 624.27 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:45:35 PM PDT 24
Peak memory 214028 kb
Host smart-714da3c4-2073-4c50-80eb-777ed9ce267a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107458274 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.107458274
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2295400622
Short name T92
Test name
Test status
Simulation time 99525146035 ps
CPU time 574.39 seconds
Started Jul 04 05:35:52 PM PDT 24
Finished Jul 04 05:45:27 PM PDT 24
Peak memory 211480 kb
Host smart-ed9b086d-db0c-44f5-8e35-28da48c74a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295400622 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2295400622
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1751490551
Short name T3
Test name
Test status
Simulation time 234211296315 ps
CPU time 79.83 seconds
Started Jul 04 05:35:22 PM PDT 24
Finished Jul 04 05:36:42 PM PDT 24
Peak memory 191788 kb
Host smart-5e906ed9-b5eb-4d47-acd2-d7d3fc836297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751490551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1751490551
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.291249837
Short name T99
Test name
Test status
Simulation time 39595027357 ps
CPU time 152.84 seconds
Started Jul 04 05:35:02 PM PDT 24
Finished Jul 04 05:37:35 PM PDT 24
Peak memory 198596 kb
Host smart-64836258-60c1-4f7f-9b51-d7b76137ee31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291249837 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.291249837
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.555608466
Short name T55
Test name
Test status
Simulation time 228468237615 ps
CPU time 449.19 seconds
Started Jul 04 05:35:21 PM PDT 24
Finished Jul 04 05:42:51 PM PDT 24
Peak memory 202772 kb
Host smart-376c978c-001d-4d18-8e77-3f69b6ad51c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555608466 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.555608466
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2316433451
Short name T132
Test name
Test status
Simulation time 75894300718 ps
CPU time 403.44 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:42:07 PM PDT 24
Peak memory 202576 kb
Host smart-5ad575bc-a0d5-43d7-ab5f-65e3c310752a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316433451 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2316433451
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2053623897
Short name T14
Test name
Test status
Simulation time 4556720546 ps
CPU time 1.46 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:35:03 PM PDT 24
Peak memory 215588 kb
Host smart-f2d5eaeb-355a-4602-8009-1c8b15f73a30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053623897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2053623897
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1019297992
Short name T113
Test name
Test status
Simulation time 126844128708 ps
CPU time 40.3 seconds
Started Jul 04 05:35:00 PM PDT 24
Finished Jul 04 05:35:41 PM PDT 24
Peak memory 198232 kb
Host smart-3b880318-3d6e-477d-8d2b-1db967c809ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019297992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1019297992
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1471393587
Short name T76
Test name
Test status
Simulation time 233514274534 ps
CPU time 308.65 seconds
Started Jul 04 05:35:13 PM PDT 24
Finished Jul 04 05:40:22 PM PDT 24
Peak memory 193108 kb
Host smart-f5b97184-246e-4fe6-9b2d-cc2487077ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471393587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1471393587
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1480785493
Short name T109
Test name
Test status
Simulation time 249785668963 ps
CPU time 45.68 seconds
Started Jul 04 05:35:41 PM PDT 24
Finished Jul 04 05:36:27 PM PDT 24
Peak memory 198204 kb
Host smart-3ce872e7-27e7-489a-a6d7-e3fe7eaddca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480785493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1480785493
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3168731465
Short name T41
Test name
Test status
Simulation time 157841798895 ps
CPU time 335.86 seconds
Started Jul 04 05:35:00 PM PDT 24
Finished Jul 04 05:40:37 PM PDT 24
Peak memory 201628 kb
Host smart-75a1a3e8-3f2e-4706-926c-7071ae59ccf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168731465 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3168731465
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2482233315
Short name T11
Test name
Test status
Simulation time 38091159794 ps
CPU time 51.59 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:36:03 PM PDT 24
Peak memory 184504 kb
Host smart-3dd110d3-e2b8-43e6-a615-1df1897e9d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482233315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2482233315
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3089255931
Short name T102
Test name
Test status
Simulation time 48503157044 ps
CPU time 349.13 seconds
Started Jul 04 05:35:42 PM PDT 24
Finished Jul 04 05:41:31 PM PDT 24
Peak memory 214040 kb
Host smart-f7c93e16-33c1-4d21-9867-969e2bf79037
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089255931 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3089255931
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2634163915
Short name T105
Test name
Test status
Simulation time 105772653338 ps
CPU time 34.94 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:35:46 PM PDT 24
Peak memory 198280 kb
Host smart-7a396f07-5d4f-44ca-af4a-f3b68a3eb1d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634163915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2634163915
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2870302804
Short name T162
Test name
Test status
Simulation time 647934882685 ps
CPU time 594.1 seconds
Started Jul 04 05:35:03 PM PDT 24
Finished Jul 04 05:44:57 PM PDT 24
Peak memory 207024 kb
Host smart-9a15000a-d69c-4397-89c1-887461e45eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870302804 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2870302804
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3002202708
Short name T124
Test name
Test status
Simulation time 24793253174 ps
CPU time 195.46 seconds
Started Jul 04 05:35:24 PM PDT 24
Finished Jul 04 05:38:40 PM PDT 24
Peak memory 206824 kb
Host smart-a58db7cc-8030-41e0-9659-137392d4319b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002202708 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3002202708
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.256815463
Short name T118
Test name
Test status
Simulation time 251262381311 ps
CPU time 318.41 seconds
Started Jul 04 05:35:34 PM PDT 24
Finished Jul 04 05:40:52 PM PDT 24
Peak memory 210248 kb
Host smart-27ad3e53-f737-4df2-9a24-75016b7012e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256815463 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.256815463
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2002841867
Short name T119
Test name
Test status
Simulation time 219634931950 ps
CPU time 333.4 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:41:24 PM PDT 24
Peak memory 192940 kb
Host smart-da48d922-8926-4175-8274-9af1d03b8978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002841867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2002841867
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3776796349
Short name T133
Test name
Test status
Simulation time 201985392524 ps
CPU time 387.58 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:41:37 PM PDT 24
Peak memory 202896 kb
Host smart-3d4f53cc-0845-4f32-be3e-6f1fe3b56a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776796349 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3776796349
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.857316843
Short name T127
Test name
Test status
Simulation time 345554537811 ps
CPU time 90.48 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:36:40 PM PDT 24
Peak memory 184696 kb
Host smart-3ccf44fe-e76c-424c-836d-e33dc536ecc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857316843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.857316843
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2902200796
Short name T94
Test name
Test status
Simulation time 62869703904 ps
CPU time 518.94 seconds
Started Jul 04 05:35:49 PM PDT 24
Finished Jul 04 05:44:28 PM PDT 24
Peak memory 210344 kb
Host smart-6cdc8abe-e444-45d0-b9db-a7ff9b7c3fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902200796 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2902200796
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3857383693
Short name T101
Test name
Test status
Simulation time 44825266934 ps
CPU time 322.01 seconds
Started Jul 04 05:35:49 PM PDT 24
Finished Jul 04 05:41:11 PM PDT 24
Peak memory 206804 kb
Host smart-60d704c1-c4e6-44ac-9459-52cc6d3cadfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857383693 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3857383693
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1086313799
Short name T110
Test name
Test status
Simulation time 137824025445 ps
CPU time 25.02 seconds
Started Jul 04 05:35:22 PM PDT 24
Finished Jul 04 05:35:48 PM PDT 24
Peak memory 184192 kb
Host smart-e80f5f96-d935-49a4-bbe0-a4c1842a63f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086313799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1086313799
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2851230203
Short name T125
Test name
Test status
Simulation time 10642471888 ps
CPU time 16.29 seconds
Started Jul 04 05:35:19 PM PDT 24
Finished Jul 04 05:35:36 PM PDT 24
Peak memory 184596 kb
Host smart-46628626-500a-46e7-8183-8944646597fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851230203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2851230203
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2251046042
Short name T115
Test name
Test status
Simulation time 72101446252 ps
CPU time 53.55 seconds
Started Jul 04 05:35:55 PM PDT 24
Finished Jul 04 05:36:49 PM PDT 24
Peak memory 184216 kb
Host smart-c0c116a4-39b1-4aba-8196-8c7450fd572e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251046042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2251046042
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3685432150
Short name T140
Test name
Test status
Simulation time 5576898626 ps
CPU time 2.35 seconds
Started Jul 04 05:35:12 PM PDT 24
Finished Jul 04 05:35:15 PM PDT 24
Peak memory 192536 kb
Host smart-2c8d837e-ac1f-4804-8425-7fe906311bf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685432150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3685432150
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2573848813
Short name T8
Test name
Test status
Simulation time 459523767944 ps
CPU time 157.2 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:38:01 PM PDT 24
Peak memory 193008 kb
Host smart-a60c8b0f-de43-4f1e-8cc8-bf7977635f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573848813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2573848813
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1837694103
Short name T142
Test name
Test status
Simulation time 265287496075 ps
CPU time 341.58 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:41:32 PM PDT 24
Peak memory 193032 kb
Host smart-a5af02ea-e04c-45ac-a8a7-9a4c9593a9a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837694103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1837694103
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3967417433
Short name T57
Test name
Test status
Simulation time 468250265 ps
CPU time 1.25 seconds
Started Jul 04 05:36:04 PM PDT 24
Finished Jul 04 05:36:05 PM PDT 24
Peak memory 193084 kb
Host smart-e6ef77f4-dbb7-4262-9af5-c742fc4c4c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967417433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3967417433
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3811176536
Short name T117
Test name
Test status
Simulation time 48064612810 ps
CPU time 351.21 seconds
Started Jul 04 05:35:26 PM PDT 24
Finished Jul 04 05:41:17 PM PDT 24
Peak memory 199552 kb
Host smart-2fb8c001-d3c2-403f-9070-7d35fe6e8805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811176536 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3811176536
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1581148958
Short name T44
Test name
Test status
Simulation time 163423528577 ps
CPU time 200.24 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:39:11 PM PDT 24
Peak memory 192952 kb
Host smart-09abaac8-dd88-4cf1-a3e8-a6ab54d21b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581148958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1581148958
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3766447272
Short name T157
Test name
Test status
Simulation time 215366369231 ps
CPU time 84.6 seconds
Started Jul 04 05:35:03 PM PDT 24
Finished Jul 04 05:36:28 PM PDT 24
Peak memory 192988 kb
Host smart-4edb1550-f11e-4081-b61b-739fa4012f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766447272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3766447272
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2045140693
Short name T28
Test name
Test status
Simulation time 885518877815 ps
CPU time 677.68 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:46:27 PM PDT 24
Peak memory 214752 kb
Host smart-6a88bae5-4d7d-495a-8a42-301c98978506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045140693 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2045140693
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2492829384
Short name T107
Test name
Test status
Simulation time 159166880703 ps
CPU time 100.15 seconds
Started Jul 04 05:35:39 PM PDT 24
Finished Jul 04 05:37:19 PM PDT 24
Peak memory 191928 kb
Host smart-1d3d9b16-1a4e-4e98-8162-b9a3f5b90c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492829384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2492829384
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1634846753
Short name T50
Test name
Test status
Simulation time 130632978070 ps
CPU time 43.81 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:36:07 PM PDT 24
Peak memory 192952 kb
Host smart-aa177d24-018e-45ee-89bb-0a3e7300fab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634846753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1634846753
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2872045215
Short name T123
Test name
Test status
Simulation time 276889420395 ps
CPU time 31.23 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:41 PM PDT 24
Peak memory 192952 kb
Host smart-a298e907-1fe9-41a6-bd81-b59b29816cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872045215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2872045215
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1933616837
Short name T70
Test name
Test status
Simulation time 71924610865 ps
CPU time 141.08 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:38:11 PM PDT 24
Peak memory 206808 kb
Host smart-d070f487-6f53-48e3-aa74-e11bb03f0634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933616837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1933616837
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2971865483
Short name T145
Test name
Test status
Simulation time 117982226027 ps
CPU time 45.07 seconds
Started Jul 04 05:35:05 PM PDT 24
Finished Jul 04 05:35:50 PM PDT 24
Peak memory 192908 kb
Host smart-29c25de5-eb19-40a3-8861-33f78cf4092b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971865483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2971865483
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3213198446
Short name T22
Test name
Test status
Simulation time 25816373423 ps
CPU time 55.33 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:36:07 PM PDT 24
Peak memory 198560 kb
Host smart-6dc758db-99ce-4cc4-b16d-b8605ed4280c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213198446 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3213198446
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2305898488
Short name T39
Test name
Test status
Simulation time 64800089749 ps
CPU time 152.91 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:37:34 PM PDT 24
Peak memory 198816 kb
Host smart-6fdff23e-bc2c-4994-bc57-538aa70527dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305898488 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2305898488
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3370922203
Short name T130
Test name
Test status
Simulation time 211502756510 ps
CPU time 308.24 seconds
Started Jul 04 05:35:04 PM PDT 24
Finished Jul 04 05:40:13 PM PDT 24
Peak memory 192712 kb
Host smart-dfa58ce6-ef7e-4fcc-b3ec-50577168be53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370922203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3370922203
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3166545573
Short name T168
Test name
Test status
Simulation time 630460677482 ps
CPU time 932.03 seconds
Started Jul 04 05:35:43 PM PDT 24
Finished Jul 04 05:51:15 PM PDT 24
Peak memory 192492 kb
Host smart-c234610a-54f2-4bc5-acc4-bf8eb54ef8a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166545573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3166545573
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4275629249
Short name T128
Test name
Test status
Simulation time 156731541241 ps
CPU time 207.32 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:38:39 PM PDT 24
Peak memory 192904 kb
Host smart-caf109c2-bdea-4f10-8b6e-e47062f42a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275629249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4275629249
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3524190273
Short name T95
Test name
Test status
Simulation time 55615151848 ps
CPU time 558.5 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:44:29 PM PDT 24
Peak memory 211044 kb
Host smart-dc23102a-0dad-4781-9b9f-b8e17d776d01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524190273 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3524190273
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3495101196
Short name T98
Test name
Test status
Simulation time 38799670018 ps
CPU time 273.1 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:39:35 PM PDT 24
Peak memory 206740 kb
Host smart-0aef3017-3552-4f72-bf75-29ff7a40be97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495101196 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3495101196
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2163223631
Short name T19
Test name
Test status
Simulation time 677532659053 ps
CPU time 489.95 seconds
Started Jul 04 05:35:21 PM PDT 24
Finished Jul 04 05:43:31 PM PDT 24
Peak memory 198260 kb
Host smart-27fa82b6-ecb4-411f-a625-c30ddc7dbe16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163223631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2163223631
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1034859115
Short name T164
Test name
Test status
Simulation time 143574846315 ps
CPU time 104.99 seconds
Started Jul 04 05:35:55 PM PDT 24
Finished Jul 04 05:37:40 PM PDT 24
Peak memory 198228 kb
Host smart-f17a0d88-c3a9-4720-9277-c8c51b3b62e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034859115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1034859115
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.699673972
Short name T30
Test name
Test status
Simulation time 222372466466 ps
CPU time 914.96 seconds
Started Jul 04 05:35:55 PM PDT 24
Finished Jul 04 05:51:10 PM PDT 24
Peak memory 210716 kb
Host smart-5f07e55c-30cb-4a68-bded-0aae92f92c41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699673972 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.699673972
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2486037023
Short name T96
Test name
Test status
Simulation time 183955377148 ps
CPU time 679.22 seconds
Started Jul 04 05:35:41 PM PDT 24
Finished Jul 04 05:47:01 PM PDT 24
Peak memory 214496 kb
Host smart-24ab2043-ba40-4084-85ce-561e33eaa354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486037023 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2486037023
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.945606583
Short name T131
Test name
Test status
Simulation time 56267701405 ps
CPU time 19.79 seconds
Started Jul 04 05:35:53 PM PDT 24
Finished Jul 04 05:36:13 PM PDT 24
Peak memory 198248 kb
Host smart-72a11e56-a02f-4ead-902d-2388a24ca117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945606583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.945606583
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.4027737420
Short name T13
Test name
Test status
Simulation time 66690190387 ps
CPU time 80.29 seconds
Started Jul 04 05:35:35 PM PDT 24
Finished Jul 04 05:36:56 PM PDT 24
Peak memory 191872 kb
Host smart-614858f7-caab-4448-bb04-380343aec832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027737420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.4027737420
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2994322415
Short name T174
Test name
Test status
Simulation time 70589713956 ps
CPU time 125.95 seconds
Started Jul 04 05:35:43 PM PDT 24
Finished Jul 04 05:37:49 PM PDT 24
Peak memory 198476 kb
Host smart-5a566070-0b1c-4abc-9884-5c9357dbe2c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994322415 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2994322415
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.123366282
Short name T149
Test name
Test status
Simulation time 183936626355 ps
CPU time 96.41 seconds
Started Jul 04 05:35:45 PM PDT 24
Finished Jul 04 05:37:22 PM PDT 24
Peak memory 193036 kb
Host smart-688eb4ca-c94a-4ae8-be2f-732ca7ab2211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123366282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.123366282
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1791610184
Short name T93
Test name
Test status
Simulation time 17190638119 ps
CPU time 135.51 seconds
Started Jul 04 05:35:56 PM PDT 24
Finished Jul 04 05:38:12 PM PDT 24
Peak memory 198592 kb
Host smart-efce3ccb-fd14-4967-89c8-d60983afbe2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791610184 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1791610184
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.948293409
Short name T161
Test name
Test status
Simulation time 72461084805 ps
CPU time 218.43 seconds
Started Jul 04 05:35:19 PM PDT 24
Finished Jul 04 05:38:58 PM PDT 24
Peak memory 207704 kb
Host smart-f7e9a259-aa3e-4f1d-a4d0-eff6c6121780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948293409 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.948293409
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1511514500
Short name T146
Test name
Test status
Simulation time 266424980772 ps
CPU time 368.85 seconds
Started Jul 04 05:34:59 PM PDT 24
Finished Jul 04 05:41:08 PM PDT 24
Peak memory 193020 kb
Host smart-d3c27029-4e28-4d28-8f3b-007a12de69ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511514500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1511514500
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.4026057456
Short name T152
Test name
Test status
Simulation time 12651509477 ps
CPU time 21.09 seconds
Started Jul 04 05:35:19 PM PDT 24
Finished Jul 04 05:35:41 PM PDT 24
Peak memory 192864 kb
Host smart-48a5faaa-a532-4abd-a491-a1aed57a8105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026057456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.4026057456
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1883360691
Short name T136
Test name
Test status
Simulation time 496698910 ps
CPU time 0.76 seconds
Started Jul 04 05:35:30 PM PDT 24
Finished Jul 04 05:35:31 PM PDT 24
Peak memory 196764 kb
Host smart-916b871a-05a9-4613-a6c8-dfc6e509a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883360691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1883360691
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2965870891
Short name T160
Test name
Test status
Simulation time 30916345469 ps
CPU time 118.16 seconds
Started Jul 04 05:35:56 PM PDT 24
Finished Jul 04 05:37:54 PM PDT 24
Peak memory 206760 kb
Host smart-fc31c4fc-1b9f-43a5-bf4a-f4488cc15535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965870891 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2965870891
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4143736744
Short name T111
Test name
Test status
Simulation time 512761064 ps
CPU time 0.77 seconds
Started Jul 04 05:35:24 PM PDT 24
Finished Jul 04 05:35:25 PM PDT 24
Peak memory 196640 kb
Host smart-a1096161-d7d1-40ce-a7c3-7ade49e5cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143736744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4143736744
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1772770025
Short name T120
Test name
Test status
Simulation time 191152351351 ps
CPU time 136.7 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:38:07 PM PDT 24
Peak memory 192876 kb
Host smart-cf7c1be9-af78-4c7f-aee7-8a4d644eed5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772770025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1772770025
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.643558168
Short name T114
Test name
Test status
Simulation time 139831991677 ps
CPU time 213.5 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:39:36 PM PDT 24
Peak memory 191792 kb
Host smart-45a9aa29-7e86-4cf6-b682-44ac1bd31afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643558168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.643558168
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2087177674
Short name T180
Test name
Test status
Simulation time 17186899209 ps
CPU time 75.35 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:36:26 PM PDT 24
Peak memory 214596 kb
Host smart-254a3fa2-f892-4363-892e-0f902db82f8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087177674 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2087177674
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1095279537
Short name T46
Test name
Test status
Simulation time 420051343 ps
CPU time 0.74 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:12 PM PDT 24
Peak memory 196712 kb
Host smart-eecdb903-def0-417b-aeef-809e82ca4ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095279537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1095279537
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.4167760564
Short name T166
Test name
Test status
Simulation time 296129482907 ps
CPU time 111.29 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:37:02 PM PDT 24
Peak memory 191904 kb
Host smart-656b59ff-f24d-4fcf-bb00-154f488a89d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167760564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.4167760564
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1635062201
Short name T175
Test name
Test status
Simulation time 186888324789 ps
CPU time 64.52 seconds
Started Jul 04 05:35:19 PM PDT 24
Finished Jul 04 05:36:24 PM PDT 24
Peak memory 192988 kb
Host smart-36fd7961-d246-45e0-bd1a-ef9ac461f7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635062201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1635062201
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2413798074
Short name T100
Test name
Test status
Simulation time 4946663212 ps
CPU time 29.67 seconds
Started Jul 04 05:35:20 PM PDT 24
Finished Jul 04 05:35:49 PM PDT 24
Peak memory 214976 kb
Host smart-7c3bf67b-29c8-44d9-b140-1649cbd33f5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413798074 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2413798074
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3681969920
Short name T97
Test name
Test status
Simulation time 57654215756 ps
CPU time 424.99 seconds
Started Jul 04 05:35:20 PM PDT 24
Finished Jul 04 05:42:26 PM PDT 24
Peak memory 206808 kb
Host smart-fe9e8656-088c-4254-9e82-57c120491f3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681969920 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3681969920
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.274751524
Short name T106
Test name
Test status
Simulation time 146091350967 ps
CPU time 47.33 seconds
Started Jul 04 05:35:34 PM PDT 24
Finished Jul 04 05:36:21 PM PDT 24
Peak memory 192796 kb
Host smart-a3b224d6-6086-458e-908f-fdb4e9efafea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274751524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.274751524
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1856208760
Short name T75
Test name
Test status
Simulation time 527067520 ps
CPU time 0.76 seconds
Started Jul 04 05:35:29 PM PDT 24
Finished Jul 04 05:35:30 PM PDT 24
Peak memory 196700 kb
Host smart-a6da5c94-18aa-4597-8760-ec0880c46b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856208760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1856208760
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1496468373
Short name T156
Test name
Test status
Simulation time 431227184 ps
CPU time 0.88 seconds
Started Jul 04 05:35:34 PM PDT 24
Finished Jul 04 05:35:35 PM PDT 24
Peak memory 196680 kb
Host smart-a37b29dc-e931-494f-b986-029e27e1954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496468373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1496468373
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.241575363
Short name T138
Test name
Test status
Simulation time 449965878 ps
CPU time 0.71 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:11 PM PDT 24
Peak memory 196752 kb
Host smart-e0953497-2159-47f0-84bb-9575b0de3a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241575363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.241575363
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.794688987
Short name T104
Test name
Test status
Simulation time 395336224 ps
CPU time 1.2 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:10 PM PDT 24
Peak memory 196648 kb
Host smart-ffc40309-77a6-413b-8898-f3ee4f5d2de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794688987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.794688987
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2259282566
Short name T122
Test name
Test status
Simulation time 466753357 ps
CPU time 0.68 seconds
Started Jul 04 05:34:59 PM PDT 24
Finished Jul 04 05:35:00 PM PDT 24
Peak memory 196708 kb
Host smart-4ff7a726-e81c-4c5b-9e97-81a0dd50489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259282566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2259282566
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3282437150
Short name T153
Test name
Test status
Simulation time 605216288 ps
CPU time 0.89 seconds
Started Jul 04 05:35:05 PM PDT 24
Finished Jul 04 05:35:06 PM PDT 24
Peak memory 196524 kb
Host smart-b09b98bb-5f9b-4d47-8b85-6c85047cf7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282437150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3282437150
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.36253773
Short name T121
Test name
Test status
Simulation time 410990035 ps
CPU time 1.13 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:35:13 PM PDT 24
Peak memory 196664 kb
Host smart-01d3f02b-7cb5-4298-9ba3-d872ced3a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36253773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.36253773
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3489963825
Short name T73
Test name
Test status
Simulation time 76675164104 ps
CPU time 161.21 seconds
Started Jul 04 05:35:14 PM PDT 24
Finished Jul 04 05:37:55 PM PDT 24
Peak memory 207488 kb
Host smart-689cf779-d51e-426e-b8d1-4acd87a35c0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489963825 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3489963825
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1943727920
Short name T108
Test name
Test status
Simulation time 432576597 ps
CPU time 1.25 seconds
Started Jul 04 05:35:26 PM PDT 24
Finished Jul 04 05:35:27 PM PDT 24
Peak memory 196664 kb
Host smart-17d059ce-bbdc-41ac-a3a1-06b9411a2f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943727920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1943727920
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1233121581
Short name T141
Test name
Test status
Simulation time 586119793 ps
CPU time 0.8 seconds
Started Jul 04 05:35:17 PM PDT 24
Finished Jul 04 05:35:18 PM PDT 24
Peak memory 196688 kb
Host smart-eda79b7c-b8c2-46eb-9c32-4728c78ba4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233121581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1233121581
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1190514719
Short name T139
Test name
Test status
Simulation time 175301339322 ps
CPU time 27 seconds
Started Jul 04 05:35:21 PM PDT 24
Finished Jul 04 05:35:48 PM PDT 24
Peak memory 191860 kb
Host smart-5c3100d6-477f-498a-94e2-ccd5332854fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190514719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1190514719
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1001038594
Short name T147
Test name
Test status
Simulation time 396548528 ps
CPU time 1.06 seconds
Started Jul 04 05:35:20 PM PDT 24
Finished Jul 04 05:35:21 PM PDT 24
Peak memory 196672 kb
Host smart-2e8d062a-7c8d-46f4-8e6e-64d14786e3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001038594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1001038594
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3533767717
Short name T112
Test name
Test status
Simulation time 418441413 ps
CPU time 0.76 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:35:51 PM PDT 24
Peak memory 196644 kb
Host smart-7d18d98b-eb89-4618-9e3a-571b1db193f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533767717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3533767717
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2270634690
Short name T126
Test name
Test status
Simulation time 82221418454 ps
CPU time 30.52 seconds
Started Jul 04 05:35:52 PM PDT 24
Finished Jul 04 05:36:23 PM PDT 24
Peak memory 191888 kb
Host smart-8604dbd8-4924-4164-93d4-eb751c8f65cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270634690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2270634690
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3666449989
Short name T53
Test name
Test status
Simulation time 334940340 ps
CPU time 1.06 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:11 PM PDT 24
Peak memory 196516 kb
Host smart-4e704d7f-d3db-4cee-a064-97dd15507899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666449989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3666449989
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3432806512
Short name T116
Test name
Test status
Simulation time 555379816 ps
CPU time 1.04 seconds
Started Jul 04 05:35:02 PM PDT 24
Finished Jul 04 05:35:04 PM PDT 24
Peak memory 196652 kb
Host smart-2418e91a-af2c-465d-b7e1-12b7c321457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432806512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3432806512
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1239192800
Short name T155
Test name
Test status
Simulation time 48278208858 ps
CPU time 54.87 seconds
Started Jul 04 05:35:37 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 191912 kb
Host smart-d9668c72-e67a-46c8-a60a-a6b8602a9f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239192800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1239192800
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3307157498
Short name T129
Test name
Test status
Simulation time 479629979 ps
CPU time 0.78 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:35:02 PM PDT 24
Peak memory 196672 kb
Host smart-61c30216-9238-4718-9174-37d5581020c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307157498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3307157498
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1972226972
Short name T7
Test name
Test status
Simulation time 566715025 ps
CPU time 0.75 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:11 PM PDT 24
Peak memory 196728 kb
Host smart-774ae3b4-23dc-4744-88b9-d3fe67cb85a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972226972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1972226972
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1507709065
Short name T135
Test name
Test status
Simulation time 381906236 ps
CPU time 1.08 seconds
Started Jul 04 05:35:15 PM PDT 24
Finished Jul 04 05:35:16 PM PDT 24
Peak memory 196644 kb
Host smart-42950bb5-4a92-4b8d-9b49-a73e7ab821e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507709065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1507709065
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.4259522065
Short name T103
Test name
Test status
Simulation time 381509981 ps
CPU time 1.21 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:35:25 PM PDT 24
Peak memory 196492 kb
Host smart-107db1ab-bf92-4635-8fa1-bb957e8f55df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259522065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.4259522065
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.868245608
Short name T150
Test name
Test status
Simulation time 414050465 ps
CPU time 1.21 seconds
Started Jul 04 05:35:19 PM PDT 24
Finished Jul 04 05:35:20 PM PDT 24
Peak memory 196540 kb
Host smart-0ee0a717-4e0c-49c8-84fa-f6c65fa6753e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868245608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.868245608
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2082475451
Short name T169
Test name
Test status
Simulation time 94379969129 ps
CPU time 32.59 seconds
Started Jul 04 05:35:16 PM PDT 24
Finished Jul 04 05:35:49 PM PDT 24
Peak memory 198280 kb
Host smart-7131aea1-4c2e-4cb7-8826-89cb386d44c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082475451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2082475451
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1920540321
Short name T144
Test name
Test status
Simulation time 63333793605 ps
CPU time 46.18 seconds
Started Jul 04 05:35:06 PM PDT 24
Finished Jul 04 05:35:52 PM PDT 24
Peak memory 191900 kb
Host smart-f8ac2de7-c41e-443e-818c-74c4d3345f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920540321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1920540321
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3408881488
Short name T151
Test name
Test status
Simulation time 586308156 ps
CPU time 1.38 seconds
Started Jul 04 05:35:29 PM PDT 24
Finished Jul 04 05:35:30 PM PDT 24
Peak memory 196692 kb
Host smart-4e6e5717-42a0-48ce-9989-b45da3499c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408881488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3408881488
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.4115673656
Short name T10
Test name
Test status
Simulation time 78285072633 ps
CPU time 211.1 seconds
Started Jul 04 05:35:51 PM PDT 24
Finished Jul 04 05:39:22 PM PDT 24
Peak memory 206736 kb
Host smart-14131bda-ae65-4f81-88e2-69d9e0eb5cf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115673656 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.4115673656
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.409831647
Short name T148
Test name
Test status
Simulation time 61226303672 ps
CPU time 28.02 seconds
Started Jul 04 05:35:58 PM PDT 24
Finished Jul 04 05:36:26 PM PDT 24
Peak memory 191940 kb
Host smart-4d75bad0-cea2-4b9d-a5d8-e36df6f9aa02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409831647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.409831647
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3501367539
Short name T154
Test name
Test status
Simulation time 426934502 ps
CPU time 0.95 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:35:24 PM PDT 24
Peak memory 196612 kb
Host smart-b0ad7952-2adf-46cc-aab7-ac646bd2bb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501367539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3501367539
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3021949819
Short name T137
Test name
Test status
Simulation time 646982826352 ps
CPU time 902.71 seconds
Started Jul 04 05:35:16 PM PDT 24
Finished Jul 04 05:50:19 PM PDT 24
Peak memory 198200 kb
Host smart-f23113b2-eb93-4ee2-9be3-aba59a7de6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021949819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3021949819
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2797951008
Short name T165
Test name
Test status
Simulation time 451242374 ps
CPU time 0.75 seconds
Started Jul 04 05:35:22 PM PDT 24
Finished Jul 04 05:35:23 PM PDT 24
Peak memory 196584 kb
Host smart-ff7753e2-b39a-43a1-bfab-0fe5aaa033b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797951008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2797951008
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1259989867
Short name T40
Test name
Test status
Simulation time 84247794525 ps
CPU time 107.18 seconds
Started Jul 04 05:35:42 PM PDT 24
Finished Jul 04 05:37:29 PM PDT 24
Peak memory 214928 kb
Host smart-c4d96088-bcb8-4d6f-9574-5f62bf96cda7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259989867 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1259989867
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.951720895
Short name T193
Test name
Test status
Simulation time 362546053 ps
CPU time 1.22 seconds
Started Jul 04 05:35:51 PM PDT 24
Finished Jul 04 05:35:53 PM PDT 24
Peak memory 196628 kb
Host smart-89ad049b-5d90-4451-bfbb-d757b4aada16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951720895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.951720895
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1910094860
Short name T200
Test name
Test status
Simulation time 4084006715 ps
CPU time 5.67 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:36 PM PDT 24
Peak memory 197628 kb
Host smart-c4ff054f-bb37-4aaf-899c-e17307a08f84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910094860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1910094860
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2855881229
Short name T12
Test name
Test status
Simulation time 87312681714 ps
CPU time 182.96 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:38:13 PM PDT 24
Peak memory 206796 kb
Host smart-c5b5a88b-19e8-4172-884a-6595acfb70bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855881229 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2855881229
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1043408529
Short name T71
Test name
Test status
Simulation time 229656752536 ps
CPU time 247.98 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:39:19 PM PDT 24
Peak memory 209024 kb
Host smart-823d0d6d-b4da-4751-af7b-c8480db3ab6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043408529 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1043408529
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1395377781
Short name T183
Test name
Test status
Simulation time 525867000460 ps
CPU time 362.43 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:41:13 PM PDT 24
Peak memory 192952 kb
Host smart-5e2f1e64-3a9e-4355-8314-a735039d50ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395377781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1395377781
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3874542175
Short name T181
Test name
Test status
Simulation time 359182656 ps
CPU time 0.73 seconds
Started Jul 04 05:35:17 PM PDT 24
Finished Jul 04 05:35:18 PM PDT 24
Peak memory 196656 kb
Host smart-c4c3502e-4a52-46a4-bcac-5e0402ad4d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874542175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3874542175
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1592919539
Short name T143
Test name
Test status
Simulation time 444509213 ps
CPU time 0.67 seconds
Started Jul 04 05:35:16 PM PDT 24
Finished Jul 04 05:35:17 PM PDT 24
Peak memory 196736 kb
Host smart-01e2b113-f313-4048-bacf-7a21ed5ac87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592919539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1592919539
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2602283455
Short name T74
Test name
Test status
Simulation time 517625926 ps
CPU time 1.37 seconds
Started Jul 04 05:35:42 PM PDT 24
Finished Jul 04 05:35:43 PM PDT 24
Peak memory 196656 kb
Host smart-a1f1b102-657d-4d13-b5d7-c9f259bb1f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602283455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2602283455
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3495193325
Short name T182
Test name
Test status
Simulation time 491785840 ps
CPU time 1.28 seconds
Started Jul 04 05:35:43 PM PDT 24
Finished Jul 04 05:35:44 PM PDT 24
Peak memory 196616 kb
Host smart-15f50498-147c-4587-9636-ba45f7d8c32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495193325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3495193325
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.629404014
Short name T188
Test name
Test status
Simulation time 414567967 ps
CPU time 0.68 seconds
Started Jul 04 05:35:43 PM PDT 24
Finished Jul 04 05:35:43 PM PDT 24
Peak memory 196608 kb
Host smart-7d15e29b-21fc-4aca-8eb6-bb9cefafc617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629404014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.629404014
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.791421144
Short name T178
Test name
Test status
Simulation time 523188160 ps
CPU time 0.71 seconds
Started Jul 04 05:35:53 PM PDT 24
Finished Jul 04 05:35:54 PM PDT 24
Peak memory 196656 kb
Host smart-f047eea1-af05-4519-87f4-ca2ec215e150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791421144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.791421144
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.638504969
Short name T189
Test name
Test status
Simulation time 516844711 ps
CPU time 1.07 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:35:52 PM PDT 24
Peak memory 196740 kb
Host smart-6715d6c6-b83f-4153-904f-989061c150c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638504969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.638504969
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2267151445
Short name T173
Test name
Test status
Simulation time 388897996 ps
CPU time 1.18 seconds
Started Jul 04 05:36:00 PM PDT 24
Finished Jul 04 05:36:01 PM PDT 24
Peak memory 196656 kb
Host smart-311ef508-575d-44f4-b453-913429a78db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267151445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2267151445
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2727662371
Short name T177
Test name
Test status
Simulation time 566023331 ps
CPU time 0.76 seconds
Started Jul 04 05:35:00 PM PDT 24
Finished Jul 04 05:35:00 PM PDT 24
Peak memory 196620 kb
Host smart-28a835ed-6616-4fcb-8a8a-4a56d6eea6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727662371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2727662371
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1724647281
Short name T176
Test name
Test status
Simulation time 342957065010 ps
CPU time 433.95 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:42:26 PM PDT 24
Peak memory 191892 kb
Host smart-c28e5b42-be58-4430-bbc5-b551ee13913a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724647281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1724647281
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3098250692
Short name T179
Test name
Test status
Simulation time 508338822 ps
CPU time 0.94 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:11 PM PDT 24
Peak memory 196652 kb
Host smart-f7829fc5-0c21-43f0-a56d-e1ddc68aece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098250692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3098250692
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1239182724
Short name T190
Test name
Test status
Simulation time 485961667 ps
CPU time 1.01 seconds
Started Jul 04 05:35:20 PM PDT 24
Finished Jul 04 05:35:21 PM PDT 24
Peak memory 196656 kb
Host smart-8ccb3df3-96b5-4be4-a9ff-bb953ece0d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239182724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1239182724
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3368376743
Short name T187
Test name
Test status
Simulation time 532030605 ps
CPU time 1.39 seconds
Started Jul 04 05:35:22 PM PDT 24
Finished Jul 04 05:35:23 PM PDT 24
Peak memory 196640 kb
Host smart-a1ef4906-d341-4b22-b5f2-e024ec26e822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368376743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3368376743
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.4071848863
Short name T172
Test name
Test status
Simulation time 37262581451 ps
CPU time 169.89 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:38:13 PM PDT 24
Peak memory 198560 kb
Host smart-df0b988e-587e-4e74-aeed-58c675165cdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071848863 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.4071848863
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2890862010
Short name T194
Test name
Test status
Simulation time 240073687423 ps
CPU time 77.67 seconds
Started Jul 04 05:35:29 PM PDT 24
Finished Jul 04 05:36:47 PM PDT 24
Peak memory 192936 kb
Host smart-a5fd22a1-e2fa-4552-baa8-367db267317a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890862010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2890862010
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1017783676
Short name T185
Test name
Test status
Simulation time 532890801 ps
CPU time 0.7 seconds
Started Jul 04 05:35:52 PM PDT 24
Finished Jul 04 05:35:52 PM PDT 24
Peak memory 196696 kb
Host smart-5b3d4587-ae56-451d-9bbd-b1360e5a47de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017783676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1017783676
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.4195879471
Short name T167
Test name
Test status
Simulation time 386332884 ps
CPU time 1.2 seconds
Started Jul 04 05:35:59 PM PDT 24
Finished Jul 04 05:36:00 PM PDT 24
Peak memory 196740 kb
Host smart-0b936131-11ef-457e-97be-eef096d3d3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195879471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.4195879471
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3560435013
Short name T158
Test name
Test status
Simulation time 374116467 ps
CPU time 1.01 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:11 PM PDT 24
Peak memory 196644 kb
Host smart-8ce6be92-78a8-40bf-8067-96f4cb2201f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560435013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3560435013
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2847552883
Short name T170
Test name
Test status
Simulation time 41510914146 ps
CPU time 87.79 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:36:40 PM PDT 24
Peak memory 206836 kb
Host smart-087133b7-137e-4b2f-b1fb-9f2593cdb949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847552883 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2847552883
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2009341871
Short name T337
Test name
Test status
Simulation time 513127250 ps
CPU time 1.05 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:03 PM PDT 24
Peak memory 193152 kb
Host smart-98a70dc6-00db-4763-a64a-5edde674cacb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009341871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2009341871
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.407156313
Short name T373
Test name
Test status
Simulation time 13862104528 ps
CPU time 19.16 seconds
Started Jul 04 05:35:57 PM PDT 24
Finished Jul 04 05:36:17 PM PDT 24
Peak memory 196252 kb
Host smart-04cb0d50-d19c-43a2-84b4-1f706ad6c287
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407156313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.407156313
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3924584465
Short name T300
Test name
Test status
Simulation time 678835840 ps
CPU time 0.79 seconds
Started Jul 04 05:35:56 PM PDT 24
Finished Jul 04 05:35:57 PM PDT 24
Peak memory 192968 kb
Host smart-62817af1-f466-420c-8a75-18e8671a1470
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924584465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3924584465
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1716081383
Short name T325
Test name
Test status
Simulation time 496119819 ps
CPU time 0.81 seconds
Started Jul 04 05:35:59 PM PDT 24
Finished Jul 04 05:36:00 PM PDT 24
Peak memory 195224 kb
Host smart-272d8b9b-c03d-41a3-985b-9e139215a833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716081383 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1716081383
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.996688652
Short name T32
Test name
Test status
Simulation time 302678344 ps
CPU time 0.85 seconds
Started Jul 04 05:35:56 PM PDT 24
Finished Jul 04 05:35:57 PM PDT 24
Peak memory 193164 kb
Host smart-2fac4e05-e779-4f80-8e2b-88fea1236a23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996688652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.996688652
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3619696785
Short name T298
Test name
Test status
Simulation time 418437934 ps
CPU time 0.67 seconds
Started Jul 04 05:35:59 PM PDT 24
Finished Jul 04 05:36:00 PM PDT 24
Peak memory 192944 kb
Host smart-decfe1a7-225d-4dee-a4c4-a762f70c4020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619696785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3619696785
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2191876736
Short name T294
Test name
Test status
Simulation time 514231067 ps
CPU time 1.22 seconds
Started Jul 04 05:35:57 PM PDT 24
Finished Jul 04 05:35:58 PM PDT 24
Peak memory 183628 kb
Host smart-8d2f9f6e-8e88-4859-84ed-99f411057d64
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191876736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2191876736
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3039530812
Short name T304
Test name
Test status
Simulation time 329058017 ps
CPU time 0.58 seconds
Started Jul 04 05:35:55 PM PDT 24
Finished Jul 04 05:35:55 PM PDT 24
Peak memory 183716 kb
Host smart-54fb668c-bd83-42b3-9a40-d4330e75297c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039530812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3039530812
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1531093314
Short name T83
Test name
Test status
Simulation time 2526366972 ps
CPU time 2.1 seconds
Started Jul 04 05:35:56 PM PDT 24
Finished Jul 04 05:35:59 PM PDT 24
Peak memory 195124 kb
Host smart-7d6dabca-e735-4ec1-9b78-0ed76d09c6f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531093314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1531093314
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.220413386
Short name T305
Test name
Test status
Simulation time 703102675 ps
CPU time 1.54 seconds
Started Jul 04 05:35:55 PM PDT 24
Finished Jul 04 05:35:56 PM PDT 24
Peak memory 198612 kb
Host smart-543cb43a-ed59-4f8f-ad5f-407fc8fed3a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220413386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.220413386
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.617540162
Short name T352
Test name
Test status
Simulation time 8517020087 ps
CPU time 12.6 seconds
Started Jul 04 05:36:01 PM PDT 24
Finished Jul 04 05:36:15 PM PDT 24
Peak memory 198228 kb
Host smart-9d48ebe9-e683-4997-8e92-5a1dadbdc311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617540162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.617540162
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2014343993
Short name T64
Test name
Test status
Simulation time 570277045 ps
CPU time 0.83 seconds
Started Jul 04 05:35:57 PM PDT 24
Finished Jul 04 05:35:58 PM PDT 24
Peak memory 193840 kb
Host smart-cd014531-76ce-49f9-99e0-0112eddd5c37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014343993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2014343993
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1603178116
Short name T56
Test name
Test status
Simulation time 12406457759 ps
CPU time 17.6 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:20 PM PDT 24
Peak memory 192212 kb
Host smart-e7db1bb8-e57b-42f2-94fe-c689907690ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603178116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1603178116
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.463455043
Short name T296
Test name
Test status
Simulation time 751405001 ps
CPU time 0.71 seconds
Started Jul 04 05:35:58 PM PDT 24
Finished Jul 04 05:35:59 PM PDT 24
Peak memory 183776 kb
Host smart-479eb87e-ac53-4c84-bfc7-dcb5cce14256
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463455043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.463455043
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2020804796
Short name T327
Test name
Test status
Simulation time 461224646 ps
CPU time 1.29 seconds
Started Jul 04 05:36:10 PM PDT 24
Finished Jul 04 05:36:11 PM PDT 24
Peak memory 196016 kb
Host smart-496885bd-1663-44b5-9315-ab4fef3b0c6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020804796 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2020804796
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4211597240
Short name T309
Test name
Test status
Simulation time 457281794 ps
CPU time 1.25 seconds
Started Jul 04 05:35:59 PM PDT 24
Finished Jul 04 05:36:01 PM PDT 24
Peak memory 193276 kb
Host smart-c5dc9dcd-5291-40ee-9443-b8914366acd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211597240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.4211597240
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2223510885
Short name T397
Test name
Test status
Simulation time 449102958 ps
CPU time 1.23 seconds
Started Jul 04 05:36:01 PM PDT 24
Finished Jul 04 05:36:03 PM PDT 24
Peak memory 192924 kb
Host smart-dbd454e8-b7d7-4b19-a201-d71e2ba6d5f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223510885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2223510885
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3532670457
Short name T363
Test name
Test status
Simulation time 408358177 ps
CPU time 1.03 seconds
Started Jul 04 05:35:54 PM PDT 24
Finished Jul 04 05:35:56 PM PDT 24
Peak memory 183636 kb
Host smart-e9a1b7c2-45b6-459f-a9fd-c2bd770311d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532670457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3532670457
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1335972693
Short name T297
Test name
Test status
Simulation time 281220673 ps
CPU time 0.9 seconds
Started Jul 04 05:35:57 PM PDT 24
Finished Jul 04 05:35:58 PM PDT 24
Peak memory 183664 kb
Host smart-d3302b4e-6acc-4843-a3e6-06ba9520badf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335972693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1335972693
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3698682812
Short name T384
Test name
Test status
Simulation time 2607419305 ps
CPU time 1.12 seconds
Started Jul 04 05:35:58 PM PDT 24
Finished Jul 04 05:35:59 PM PDT 24
Peak memory 192032 kb
Host smart-ff7719d9-5ba4-468f-8150-08e46c050e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698682812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3698682812
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2730522202
Short name T401
Test name
Test status
Simulation time 904590633 ps
CPU time 2.87 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:05 PM PDT 24
Peak memory 198508 kb
Host smart-e014ea17-cea6-4926-9a70-25f71d0f4a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730522202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2730522202
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4167239664
Short name T36
Test name
Test status
Simulation time 4264353023 ps
CPU time 6.37 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:08 PM PDT 24
Peak memory 197832 kb
Host smart-030bac13-fb56-42a8-8508-f01b16e401f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167239664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.4167239664
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1254544828
Short name T399
Test name
Test status
Simulation time 592083746 ps
CPU time 1.09 seconds
Started Jul 04 05:36:25 PM PDT 24
Finished Jul 04 05:36:26 PM PDT 24
Peak memory 196636 kb
Host smart-8fc7282f-3962-4e04-8478-6c3f9c2a17c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254544828 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1254544828
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3486932670
Short name T61
Test name
Test status
Simulation time 492091088 ps
CPU time 0.8 seconds
Started Jul 04 05:36:24 PM PDT 24
Finished Jul 04 05:36:25 PM PDT 24
Peak memory 192976 kb
Host smart-3d88a092-354d-4a22-9f88-91035dc43a78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486932670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3486932670
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1074172235
Short name T285
Test name
Test status
Simulation time 317663683 ps
CPU time 0.74 seconds
Started Jul 04 05:36:25 PM PDT 24
Finished Jul 04 05:36:26 PM PDT 24
Peak memory 183712 kb
Host smart-27fffe04-40c9-44e2-9c2b-5e4ef68c1cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074172235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1074172235
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1014339552
Short name T79
Test name
Test status
Simulation time 1750974243 ps
CPU time 3.18 seconds
Started Jul 04 05:36:24 PM PDT 24
Finished Jul 04 05:36:28 PM PDT 24
Peak memory 193056 kb
Host smart-50e1bc1d-5f91-4b65-a729-eed59e1c6129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014339552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1014339552
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3643283502
Short name T390
Test name
Test status
Simulation time 445088916 ps
CPU time 2.48 seconds
Started Jul 04 05:36:25 PM PDT 24
Finished Jul 04 05:36:27 PM PDT 24
Peak memory 198552 kb
Host smart-5ea19106-5ca1-446f-ac78-e846b9e5021b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643283502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3643283502
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.4172613841
Short name T371
Test name
Test status
Simulation time 8519861321 ps
CPU time 6.66 seconds
Started Jul 04 05:36:26 PM PDT 24
Finished Jul 04 05:36:33 PM PDT 24
Peak memory 198280 kb
Host smart-acd96853-524a-499a-9aa8-6e27d9eb4efe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172613841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.4172613841
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1595734158
Short name T289
Test name
Test status
Simulation time 562164450 ps
CPU time 0.85 seconds
Started Jul 04 05:36:33 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 196860 kb
Host smart-5d929faf-ff36-4c8a-935a-f884121389d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595734158 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1595734158
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.415185144
Short name T412
Test name
Test status
Simulation time 488923873 ps
CPU time 0.62 seconds
Started Jul 04 05:36:24 PM PDT 24
Finished Jul 04 05:36:24 PM PDT 24
Peak memory 193148 kb
Host smart-7dd034c5-00d1-4df6-a0f1-1315127a3253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415185144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.415185144
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1062802669
Short name T356
Test name
Test status
Simulation time 463550173 ps
CPU time 0.7 seconds
Started Jul 04 05:36:23 PM PDT 24
Finished Jul 04 05:36:24 PM PDT 24
Peak memory 183704 kb
Host smart-6cbefd0f-37f7-47ec-9a80-1aec2cd98a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062802669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1062802669
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3413847234
Short name T81
Test name
Test status
Simulation time 1957421715 ps
CPU time 1.66 seconds
Started Jul 04 05:36:21 PM PDT 24
Finished Jul 04 05:36:23 PM PDT 24
Peak memory 193912 kb
Host smart-63e13819-317a-4f5d-8872-312dddcdbb22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413847234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3413847234
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.749042933
Short name T292
Test name
Test status
Simulation time 1624151508 ps
CPU time 2.47 seconds
Started Jul 04 05:36:27 PM PDT 24
Finished Jul 04 05:36:29 PM PDT 24
Peak memory 198588 kb
Host smart-2d700038-19ac-4be9-beae-320f5e7cd54d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749042933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.749042933
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1310805708
Short name T381
Test name
Test status
Simulation time 8500567487 ps
CPU time 13.87 seconds
Started Jul 04 05:36:23 PM PDT 24
Finished Jul 04 05:36:37 PM PDT 24
Peak memory 198232 kb
Host smart-8a7fa51d-114f-41a1-bd0d-b525ebf8257c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310805708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1310805708
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1495763426
Short name T402
Test name
Test status
Simulation time 362804136 ps
CPU time 0.8 seconds
Started Jul 04 05:36:28 PM PDT 24
Finished Jul 04 05:36:29 PM PDT 24
Peak memory 196476 kb
Host smart-c73d3d16-2d4a-4a6d-9cc5-6c126eb8fad1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495763426 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1495763426
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1492104066
Short name T362
Test name
Test status
Simulation time 458545107 ps
CPU time 0.78 seconds
Started Jul 04 05:36:23 PM PDT 24
Finished Jul 04 05:36:24 PM PDT 24
Peak memory 193300 kb
Host smart-dc5c55ea-e493-4376-b544-3f8b458c9254
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492104066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1492104066
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.749637204
Short name T353
Test name
Test status
Simulation time 364878485 ps
CPU time 0.68 seconds
Started Jul 04 05:36:23 PM PDT 24
Finished Jul 04 05:36:24 PM PDT 24
Peak memory 183732 kb
Host smart-a7e79e6b-06b2-4027-adfb-956634011ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749637204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.749637204
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3117441788
Short name T347
Test name
Test status
Simulation time 2205729287 ps
CPU time 3.54 seconds
Started Jul 04 05:36:24 PM PDT 24
Finished Jul 04 05:36:28 PM PDT 24
Peak memory 193888 kb
Host smart-219a6eb3-b6ac-489e-b896-98ac57ffaae0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117441788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3117441788
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2898459310
Short name T377
Test name
Test status
Simulation time 450864977 ps
CPU time 1.52 seconds
Started Jul 04 05:36:25 PM PDT 24
Finished Jul 04 05:36:27 PM PDT 24
Peak memory 198628 kb
Host smart-f1eb3a9c-e161-4a11-a060-784a89466f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898459310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2898459310
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1337229475
Short name T338
Test name
Test status
Simulation time 8334573481 ps
CPU time 11.59 seconds
Started Jul 04 05:36:27 PM PDT 24
Finished Jul 04 05:36:39 PM PDT 24
Peak memory 198108 kb
Host smart-ea33be7f-f605-4aca-b194-d7f7db9fb369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337229475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1337229475
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1238334265
Short name T374
Test name
Test status
Simulation time 398271473 ps
CPU time 1.22 seconds
Started Jul 04 05:36:26 PM PDT 24
Finished Jul 04 05:36:27 PM PDT 24
Peak memory 196040 kb
Host smart-41adb727-d400-4bdf-97db-e4c67d6e48a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238334265 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1238334265
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.798115156
Short name T386
Test name
Test status
Simulation time 466011370 ps
CPU time 1.32 seconds
Started Jul 04 05:36:28 PM PDT 24
Finished Jul 04 05:36:29 PM PDT 24
Peak memory 193224 kb
Host smart-157bc8ba-5743-4d26-a3e0-262365ff6cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798115156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.798115156
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2249334709
Short name T299
Test name
Test status
Simulation time 506736157 ps
CPU time 0.68 seconds
Started Jul 04 05:36:33 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 183596 kb
Host smart-1fb5b1b6-770a-45a7-a63a-ec238bb77cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249334709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2249334709
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3131584810
Short name T313
Test name
Test status
Simulation time 2436469528 ps
CPU time 1.85 seconds
Started Jul 04 05:36:28 PM PDT 24
Finished Jul 04 05:36:30 PM PDT 24
Peak memory 192020 kb
Host smart-c840c953-4da0-4962-978f-7b2a4429ca07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131584810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3131584810
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2069451683
Short name T365
Test name
Test status
Simulation time 357778000 ps
CPU time 1.57 seconds
Started Jul 04 05:36:26 PM PDT 24
Finished Jul 04 05:36:28 PM PDT 24
Peak memory 198604 kb
Host smart-5b43d502-c47a-46b8-9fee-126c40bbd074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069451683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2069451683
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3029991565
Short name T301
Test name
Test status
Simulation time 628709734 ps
CPU time 0.87 seconds
Started Jul 04 05:36:32 PM PDT 24
Finished Jul 04 05:36:33 PM PDT 24
Peak memory 196300 kb
Host smart-1d043c20-89ed-4988-af6a-4100e6d8245e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029991565 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3029991565
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1961476203
Short name T68
Test name
Test status
Simulation time 346888572 ps
CPU time 0.71 seconds
Started Jul 04 05:36:30 PM PDT 24
Finished Jul 04 05:36:31 PM PDT 24
Peak memory 193212 kb
Host smart-94917c14-de46-4dc9-bd63-fb915772b2af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961476203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1961476203
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1664138576
Short name T392
Test name
Test status
Simulation time 403071534 ps
CPU time 1.1 seconds
Started Jul 04 05:36:30 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 183708 kb
Host smart-3dc1be3f-56f3-4dbb-8229-281bce6602d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664138576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1664138576
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2049605474
Short name T372
Test name
Test status
Simulation time 2257356891 ps
CPU time 3.42 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:35 PM PDT 24
Peak memory 194004 kb
Host smart-7cb20a93-eb76-4ece-b8c6-5e3f8994e522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049605474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2049605474
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.23640964
Short name T312
Test name
Test status
Simulation time 465088648 ps
CPU time 1.39 seconds
Started Jul 04 05:36:22 PM PDT 24
Finished Jul 04 05:36:23 PM PDT 24
Peak memory 198488 kb
Host smart-3747b5d5-8fc8-40aa-9d10-c35364ae6360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23640964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.23640964
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2730900810
Short name T416
Test name
Test status
Simulation time 3932083751 ps
CPU time 5.74 seconds
Started Jul 04 05:36:26 PM PDT 24
Finished Jul 04 05:36:31 PM PDT 24
Peak memory 196780 kb
Host smart-edd168c3-723b-47f2-8b84-df48e875f896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730900810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2730900810
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.761647379
Short name T279
Test name
Test status
Simulation time 383007762 ps
CPU time 1.16 seconds
Started Jul 04 05:36:30 PM PDT 24
Finished Jul 04 05:36:31 PM PDT 24
Peak memory 195524 kb
Host smart-9b19b317-5297-4fde-9341-0b91ac9c899f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761647379 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.761647379
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1516154031
Short name T341
Test name
Test status
Simulation time 528488222 ps
CPU time 1.39 seconds
Started Jul 04 05:36:32 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 192968 kb
Host smart-0c4f2e11-652b-4419-aff2-20592f6ceccd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516154031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1516154031
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.129759655
Short name T357
Test name
Test status
Simulation time 431846953 ps
CPU time 0.61 seconds
Started Jul 04 05:36:33 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 183736 kb
Host smart-aa6ecd77-c760-42a6-a1ff-6167b59d3674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129759655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.129759655
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1527945621
Short name T84
Test name
Test status
Simulation time 1213656949 ps
CPU time 2.07 seconds
Started Jul 04 05:36:30 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 193668 kb
Host smart-4b3b8b6d-177d-425f-8c34-eec779180f04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527945621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1527945621
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.279363993
Short name T415
Test name
Test status
Simulation time 566963219 ps
CPU time 1.57 seconds
Started Jul 04 05:36:32 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 198612 kb
Host smart-f5ac3c9c-9255-41e7-a2ea-d502760ba3f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279363993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.279363993
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4229359416
Short name T387
Test name
Test status
Simulation time 8064733652 ps
CPU time 12.23 seconds
Started Jul 04 05:36:29 PM PDT 24
Finished Jul 04 05:36:41 PM PDT 24
Peak memory 198104 kb
Host smart-6d943306-a7c1-4708-bae4-6df43ceab8ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229359416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4229359416
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1727039770
Short name T311
Test name
Test status
Simulation time 591695228 ps
CPU time 1.18 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:33 PM PDT 24
Peak memory 196356 kb
Host smart-4ee5bc25-9c8a-45aa-ba81-08f14591bc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727039770 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1727039770
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.314750279
Short name T58
Test name
Test status
Simulation time 546557891 ps
CPU time 1.35 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:33 PM PDT 24
Peak memory 193260 kb
Host smart-5d5dc052-3e8d-497c-a1e7-c33e368f9cab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314750279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.314750279
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.521780308
Short name T318
Test name
Test status
Simulation time 357557919 ps
CPU time 1.09 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 183700 kb
Host smart-18722a0f-5d12-4d04-aaf3-7ef55d3842ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521780308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.521780308
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1434652630
Short name T382
Test name
Test status
Simulation time 918741383 ps
CPU time 2.73 seconds
Started Jul 04 05:36:29 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 194048 kb
Host smart-73fe56b7-3f1b-4558-be0d-a4ecee07f442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434652630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1434652630
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.958794249
Short name T406
Test name
Test status
Simulation time 467465185 ps
CPU time 2.81 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 198620 kb
Host smart-b97ed91c-ca1a-4cf6-bce0-6bc712085676
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958794249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.958794249
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3194190256
Short name T197
Test name
Test status
Simulation time 4347878641 ps
CPU time 3.97 seconds
Started Jul 04 05:36:29 PM PDT 24
Finished Jul 04 05:36:33 PM PDT 24
Peak memory 197904 kb
Host smart-3e2817bd-87aa-42db-9f68-53be444415d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194190256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3194190256
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1531744157
Short name T405
Test name
Test status
Simulation time 599148389 ps
CPU time 0.89 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 197028 kb
Host smart-f16d290a-9691-4d21-894c-228acfed23f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531744157 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1531744157
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1124512072
Short name T290
Test name
Test status
Simulation time 463724593 ps
CPU time 0.73 seconds
Started Jul 04 05:36:33 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 192044 kb
Host smart-a690e6ff-9a89-4415-9132-04e308083630
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124512072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1124512072
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3047918322
Short name T295
Test name
Test status
Simulation time 504783916 ps
CPU time 1.21 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 183720 kb
Host smart-31cc95ee-d160-461c-953b-eafe6abed458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047918322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3047918322
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2690922884
Short name T85
Test name
Test status
Simulation time 2526083305 ps
CPU time 5.27 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:37 PM PDT 24
Peak memory 193896 kb
Host smart-6fa127fb-741b-41bf-a0a1-c487ca0edbf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690922884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2690922884
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2734469668
Short name T319
Test name
Test status
Simulation time 598247570 ps
CPU time 2.3 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 198576 kb
Host smart-234a66b9-60cd-40c3-afbb-2a4fbbb6dac7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734469668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2734469668
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2181862119
Short name T198
Test name
Test status
Simulation time 8618569693 ps
CPU time 6.56 seconds
Started Jul 04 05:36:30 PM PDT 24
Finished Jul 04 05:36:37 PM PDT 24
Peak memory 198204 kb
Host smart-07c63a2a-c591-4a3f-b1d8-7269b6133125
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181862119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2181862119
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3735473291
Short name T334
Test name
Test status
Simulation time 500107296 ps
CPU time 0.87 seconds
Started Jul 04 05:36:32 PM PDT 24
Finished Jul 04 05:36:33 PM PDT 24
Peak memory 196632 kb
Host smart-4599ae79-ba96-4685-87c5-9c5d1dc4a175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735473291 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3735473291
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3092200982
Short name T286
Test name
Test status
Simulation time 462876934 ps
CPU time 0.85 seconds
Started Jul 04 05:36:29 PM PDT 24
Finished Jul 04 05:36:30 PM PDT 24
Peak memory 192948 kb
Host smart-b3ce5622-302e-4d9e-a5a7-04e434ed75cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092200982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3092200982
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2652972832
Short name T335
Test name
Test status
Simulation time 429908108 ps
CPU time 1.18 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 183680 kb
Host smart-6d94a642-9283-46e8-bba9-d08be57e181a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652972832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2652972832
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4039512332
Short name T82
Test name
Test status
Simulation time 3097043811 ps
CPU time 2.12 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 194200 kb
Host smart-ff94bc87-ca96-4473-b7e7-2b6fcadc58a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039512332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.4039512332
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3671568976
Short name T344
Test name
Test status
Simulation time 921721367 ps
CPU time 1.95 seconds
Started Jul 04 05:36:32 PM PDT 24
Finished Jul 04 05:36:35 PM PDT 24
Peak memory 198472 kb
Host smart-88a6d144-228a-4808-93dd-83f1ecff6f92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671568976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3671568976
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2797289614
Short name T376
Test name
Test status
Simulation time 428118056 ps
CPU time 0.8 seconds
Started Jul 04 05:36:35 PM PDT 24
Finished Jul 04 05:36:36 PM PDT 24
Peak memory 195724 kb
Host smart-a463381d-627c-4ed5-a108-28fb9db54af4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797289614 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2797289614
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3969645504
Short name T34
Test name
Test status
Simulation time 375049263 ps
CPU time 0.64 seconds
Started Jul 04 05:36:30 PM PDT 24
Finished Jul 04 05:36:31 PM PDT 24
Peak memory 192948 kb
Host smart-8a630066-42fb-44be-ba38-155e944b1e89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969645504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3969645504
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3988547322
Short name T355
Test name
Test status
Simulation time 288459560 ps
CPU time 0.63 seconds
Started Jul 04 05:36:30 PM PDT 24
Finished Jul 04 05:36:31 PM PDT 24
Peak memory 183724 kb
Host smart-a5aead3b-d11c-497c-87d4-9791170fa07f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988547322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3988547322
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2335231040
Short name T349
Test name
Test status
Simulation time 2675568775 ps
CPU time 3.85 seconds
Started Jul 04 05:36:29 PM PDT 24
Finished Jul 04 05:36:33 PM PDT 24
Peak memory 194560 kb
Host smart-482d2047-ed79-40a1-9e80-62ee97e45865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335231040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2335231040
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1392366972
Short name T400
Test name
Test status
Simulation time 475667459 ps
CPU time 2.09 seconds
Started Jul 04 05:36:34 PM PDT 24
Finished Jul 04 05:36:37 PM PDT 24
Peak memory 198512 kb
Host smart-67dcf6c9-33f4-4cce-bd6f-eabd63bb45d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392366972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1392366972
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3355229761
Short name T328
Test name
Test status
Simulation time 4469072826 ps
CPU time 2.7 seconds
Started Jul 04 05:36:29 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 197584 kb
Host smart-27c43708-fb71-4a0d-9ed6-e63df6b2035c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355229761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3355229761
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2793909186
Short name T316
Test name
Test status
Simulation time 535895708 ps
CPU time 1.3 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 193260 kb
Host smart-ca0b57ef-3b0e-4c35-bdf1-3ba8389c24fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793909186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2793909186
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1102041545
Short name T37
Test name
Test status
Simulation time 7117086816 ps
CPU time 8.82 seconds
Started Jul 04 05:36:07 PM PDT 24
Finished Jul 04 05:36:16 PM PDT 24
Peak memory 192112 kb
Host smart-e17af2e9-e9b6-4d79-bba8-84e54a4e4800
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102041545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1102041545
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.915796212
Short name T379
Test name
Test status
Simulation time 1237208825 ps
CPU time 2.51 seconds
Started Jul 04 05:36:04 PM PDT 24
Finished Jul 04 05:36:07 PM PDT 24
Peak memory 193180 kb
Host smart-31208813-ed99-43a7-8a5e-ecbf23060f0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915796212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.915796212
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4012515363
Short name T366
Test name
Test status
Simulation time 508606008 ps
CPU time 0.99 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 196104 kb
Host smart-dde96846-ae19-47af-959b-3eda5eebd5c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012515363 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.4012515363
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4189233866
Short name T322
Test name
Test status
Simulation time 366051683 ps
CPU time 0.63 seconds
Started Jul 04 05:36:04 PM PDT 24
Finished Jul 04 05:36:05 PM PDT 24
Peak memory 192924 kb
Host smart-433c0618-2d22-4565-bfcd-d2a2802b084e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189233866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.4189233866
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4120898005
Short name T288
Test name
Test status
Simulation time 372652228 ps
CPU time 0.67 seconds
Started Jul 04 05:36:07 PM PDT 24
Finished Jul 04 05:36:08 PM PDT 24
Peak memory 183516 kb
Host smart-5caeeeae-3fed-442a-8d37-b8c467a0eb95
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120898005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.4120898005
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2392183068
Short name T340
Test name
Test status
Simulation time 319524827 ps
CPU time 0.64 seconds
Started Jul 04 05:36:04 PM PDT 24
Finished Jul 04 05:36:05 PM PDT 24
Peak memory 183676 kb
Host smart-029c5abe-3b2f-4abc-9002-88310a7c13a7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392183068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2392183068
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3477797807
Short name T413
Test name
Test status
Simulation time 2118253397 ps
CPU time 1.81 seconds
Started Jul 04 05:36:04 PM PDT 24
Finished Jul 04 05:36:06 PM PDT 24
Peak memory 183896 kb
Host smart-00e2ed2e-1508-420f-beed-8a6288ff2216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477797807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3477797807
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3329126023
Short name T287
Test name
Test status
Simulation time 336607448 ps
CPU time 1.96 seconds
Started Jul 04 05:36:05 PM PDT 24
Finished Jul 04 05:36:07 PM PDT 24
Peak memory 198608 kb
Host smart-1e755664-73f7-4cf3-84b6-285b664a63e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329126023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3329126023
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3292858317
Short name T389
Test name
Test status
Simulation time 8035845856 ps
CPU time 11.54 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:14 PM PDT 24
Peak memory 198292 kb
Host smart-f45b0299-b763-45a7-9a67-26a10924a234
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292858317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3292858317
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.202915902
Short name T302
Test name
Test status
Simulation time 460776166 ps
CPU time 0.75 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 183744 kb
Host smart-3160e701-98a2-48b7-8f06-8292cd5b2ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202915902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.202915902
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2511298624
Short name T339
Test name
Test status
Simulation time 486560674 ps
CPU time 1.45 seconds
Started Jul 04 05:36:35 PM PDT 24
Finished Jul 04 05:36:37 PM PDT 24
Peak memory 192816 kb
Host smart-681acab6-9b07-40e2-bc9d-12768e5823a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511298624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2511298624
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1063137471
Short name T370
Test name
Test status
Simulation time 349039139 ps
CPU time 0.65 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:32 PM PDT 24
Peak memory 183704 kb
Host smart-c7879654-9903-4e9a-9914-774f157d2955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063137471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1063137471
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2753349658
Short name T368
Test name
Test status
Simulation time 288537414 ps
CPU time 0.64 seconds
Started Jul 04 05:36:32 PM PDT 24
Finished Jul 04 05:36:33 PM PDT 24
Peak memory 183704 kb
Host smart-35da98fe-c4a7-4509-9ef3-7d20a439a622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753349658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2753349658
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2295411512
Short name T398
Test name
Test status
Simulation time 466469792 ps
CPU time 0.87 seconds
Started Jul 04 05:36:31 PM PDT 24
Finished Jul 04 05:36:33 PM PDT 24
Peak memory 183720 kb
Host smart-a05f8ae5-669d-43ea-9a18-e6b34b97c9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295411512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2295411512
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.116574648
Short name T321
Test name
Test status
Simulation time 518865305 ps
CPU time 1.31 seconds
Started Jul 04 05:36:32 PM PDT 24
Finished Jul 04 05:36:34 PM PDT 24
Peak memory 192940 kb
Host smart-eae4471b-f252-4254-a609-66e2f3d52f83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116574648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.116574648
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1507562388
Short name T291
Test name
Test status
Simulation time 318970117 ps
CPU time 0.97 seconds
Started Jul 04 05:36:40 PM PDT 24
Finished Jul 04 05:36:42 PM PDT 24
Peak memory 183728 kb
Host smart-835248be-3950-45c0-839f-dbc1ee0a3c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507562388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1507562388
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.786021483
Short name T310
Test name
Test status
Simulation time 356759283 ps
CPU time 0.79 seconds
Started Jul 04 05:36:38 PM PDT 24
Finished Jul 04 05:36:39 PM PDT 24
Peak memory 183704 kb
Host smart-883b1833-f85b-4c8b-a017-a254e1cf662c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786021483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.786021483
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1541754668
Short name T408
Test name
Test status
Simulation time 422656967 ps
CPU time 0.61 seconds
Started Jul 04 05:36:37 PM PDT 24
Finished Jul 04 05:36:38 PM PDT 24
Peak memory 192908 kb
Host smart-878bee2c-c2d0-43a6-8730-f89cc4dd7add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541754668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1541754668
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.816343118
Short name T284
Test name
Test status
Simulation time 440382690 ps
CPU time 1.25 seconds
Started Jul 04 05:36:43 PM PDT 24
Finished Jul 04 05:36:44 PM PDT 24
Peak memory 192924 kb
Host smart-9d1dbec8-c2f8-4f97-8c4d-34b74491db54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816343118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.816343118
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2706931531
Short name T66
Test name
Test status
Simulation time 526415267 ps
CPU time 1.18 seconds
Started Jul 04 05:36:03 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 194336 kb
Host smart-e95cf175-9ac2-480e-9b9e-0eaec632533f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706931531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2706931531
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1074573999
Short name T69
Test name
Test status
Simulation time 5807362605 ps
CPU time 2.1 seconds
Started Jul 04 05:36:01 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 196348 kb
Host smart-305022ca-0545-41a9-bc31-3983d8783280
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074573999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1074573999
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4052144945
Short name T359
Test name
Test status
Simulation time 778199905 ps
CPU time 1.07 seconds
Started Jul 04 05:36:04 PM PDT 24
Finished Jul 04 05:36:06 PM PDT 24
Peak memory 183776 kb
Host smart-900f57d3-aa2b-4c38-b157-6f351978a2da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052144945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4052144945
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3669571601
Short name T403
Test name
Test status
Simulation time 531557156 ps
CPU time 1.41 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 196316 kb
Host smart-088d2f80-6d11-4363-b065-0c010f1ff0aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669571601 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3669571601
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1775473733
Short name T65
Test name
Test status
Simulation time 312257075 ps
CPU time 1.11 seconds
Started Jul 04 05:36:10 PM PDT 24
Finished Jul 04 05:36:11 PM PDT 24
Peak memory 193144 kb
Host smart-c25f064a-7a09-4ead-b4f4-3df844e2548f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775473733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1775473733
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.372219853
Short name T388
Test name
Test status
Simulation time 341759618 ps
CPU time 0.62 seconds
Started Jul 04 05:36:03 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 183700 kb
Host smart-bee13778-f4c9-4c7b-a0e8-f48d25f9dd4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372219853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.372219853
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1408897884
Short name T314
Test name
Test status
Simulation time 464467675 ps
CPU time 0.72 seconds
Started Jul 04 05:36:03 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 183644 kb
Host smart-a72c696d-89d2-4ee1-8536-d4ffe30f8ac2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408897884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1408897884
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.794731624
Short name T380
Test name
Test status
Simulation time 403315901 ps
CPU time 1.15 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 183692 kb
Host smart-3fc33627-91c3-4c22-8662-3d079963ce62
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794731624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.794731624
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.927290989
Short name T324
Test name
Test status
Simulation time 1313045198 ps
CPU time 1.36 seconds
Started Jul 04 05:36:03 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 192964 kb
Host smart-931e5f98-299c-44f5-af26-39127037a659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927290989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.927290989
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.358840110
Short name T348
Test name
Test status
Simulation time 549734792 ps
CPU time 2 seconds
Started Jul 04 05:36:05 PM PDT 24
Finished Jul 04 05:36:07 PM PDT 24
Peak memory 198588 kb
Host smart-d081a726-eb20-48d3-96e8-ed35691d2cc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358840110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.358840110
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1944660040
Short name T367
Test name
Test status
Simulation time 9264651626 ps
CPU time 1.8 seconds
Started Jul 04 05:36:04 PM PDT 24
Finished Jul 04 05:36:06 PM PDT 24
Peak memory 198144 kb
Host smart-b8c06ed1-dc8a-425d-b585-050e8e05468c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944660040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1944660040
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.717512527
Short name T276
Test name
Test status
Simulation time 380904420 ps
CPU time 0.69 seconds
Started Jul 04 05:36:39 PM PDT 24
Finished Jul 04 05:36:40 PM PDT 24
Peak memory 192928 kb
Host smart-1c96676d-a215-47de-b481-d52095770d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717512527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.717512527
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.4232173943
Short name T343
Test name
Test status
Simulation time 501729676 ps
CPU time 0.79 seconds
Started Jul 04 05:36:40 PM PDT 24
Finished Jul 04 05:36:41 PM PDT 24
Peak memory 183720 kb
Host smart-498c90e8-0a09-46b0-ab61-053052193fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232173943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.4232173943
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1775624069
Short name T320
Test name
Test status
Simulation time 509291741 ps
CPU time 0.8 seconds
Started Jul 04 05:36:39 PM PDT 24
Finished Jul 04 05:36:40 PM PDT 24
Peak memory 183672 kb
Host smart-8f79b8c5-24d0-440d-94a1-28fb3c329d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775624069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1775624069
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.163207785
Short name T315
Test name
Test status
Simulation time 426649711 ps
CPU time 0.72 seconds
Started Jul 04 05:36:39 PM PDT 24
Finished Jul 04 05:36:40 PM PDT 24
Peak memory 183708 kb
Host smart-5dc4c799-ad08-4d79-b56f-eed3f3497761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163207785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.163207785
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3541020194
Short name T330
Test name
Test status
Simulation time 505408096 ps
CPU time 0.66 seconds
Started Jul 04 05:36:41 PM PDT 24
Finished Jul 04 05:36:42 PM PDT 24
Peak memory 183584 kb
Host smart-3d3d5bf5-3670-496e-b6e5-3f0ec674dda1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541020194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3541020194
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3243117864
Short name T306
Test name
Test status
Simulation time 372401511 ps
CPU time 0.59 seconds
Started Jul 04 05:36:40 PM PDT 24
Finished Jul 04 05:36:41 PM PDT 24
Peak memory 183700 kb
Host smart-b61e4b50-5e15-4621-a576-7b86dc858ea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243117864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3243117864
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.782104465
Short name T283
Test name
Test status
Simulation time 340195061 ps
CPU time 1.01 seconds
Started Jul 04 05:36:41 PM PDT 24
Finished Jul 04 05:36:42 PM PDT 24
Peak memory 183732 kb
Host smart-2f5de520-d4c5-400a-abe3-32262472d0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782104465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.782104465
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1594768218
Short name T293
Test name
Test status
Simulation time 546174243 ps
CPU time 0.72 seconds
Started Jul 04 05:36:39 PM PDT 24
Finished Jul 04 05:36:40 PM PDT 24
Peak memory 183712 kb
Host smart-2d37b94b-e37a-4662-96b2-10195fb00b56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594768218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1594768218
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1703494053
Short name T342
Test name
Test status
Simulation time 318955906 ps
CPU time 0.87 seconds
Started Jul 04 05:36:38 PM PDT 24
Finished Jul 04 05:36:39 PM PDT 24
Peak memory 183700 kb
Host smart-bfd82ba8-d1bf-4d1d-b9c1-813f7665246e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703494053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1703494053
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1171508661
Short name T280
Test name
Test status
Simulation time 408217726 ps
CPU time 1.06 seconds
Started Jul 04 05:36:38 PM PDT 24
Finished Jul 04 05:36:39 PM PDT 24
Peak memory 183992 kb
Host smart-a04c2f45-f622-482d-8e41-b737726ac94e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171508661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1171508661
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1230968469
Short name T67
Test name
Test status
Simulation time 736172484 ps
CPU time 0.73 seconds
Started Jul 04 05:36:07 PM PDT 24
Finished Jul 04 05:36:08 PM PDT 24
Peak memory 193204 kb
Host smart-5cdc213b-9f5b-4396-98b5-c28696568e7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230968469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1230968469
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.753131488
Short name T62
Test name
Test status
Simulation time 7455658915 ps
CPU time 7.31 seconds
Started Jul 04 05:36:11 PM PDT 24
Finished Jul 04 05:36:19 PM PDT 24
Peak memory 196372 kb
Host smart-0c5be47c-462f-49a6-bf58-4bcd27ade970
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753131488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.753131488
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.729292363
Short name T393
Test name
Test status
Simulation time 918370193 ps
CPU time 0.87 seconds
Started Jul 04 05:36:10 PM PDT 24
Finished Jul 04 05:36:11 PM PDT 24
Peak memory 183760 kb
Host smart-f6e2ca29-a363-455d-9f29-22df907c8c5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729292363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.729292363
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4037240627
Short name T378
Test name
Test status
Simulation time 491395663 ps
CPU time 1.37 seconds
Started Jul 04 05:36:11 PM PDT 24
Finished Jul 04 05:36:13 PM PDT 24
Peak memory 196792 kb
Host smart-c708a590-4c7c-4106-afcd-077dcf05dc6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037240627 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.4037240627
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2021496597
Short name T278
Test name
Test status
Simulation time 407435518 ps
CPU time 1.26 seconds
Started Jul 04 05:36:13 PM PDT 24
Finished Jul 04 05:36:14 PM PDT 24
Peak memory 193148 kb
Host smart-e8c90f60-46de-4031-b233-ebc67dcc6fe7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021496597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2021496597
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.728105990
Short name T396
Test name
Test status
Simulation time 436419842 ps
CPU time 0.67 seconds
Started Jul 04 05:36:08 PM PDT 24
Finished Jul 04 05:36:09 PM PDT 24
Peak memory 183704 kb
Host smart-2a3cd62f-29f2-44a9-8a60-dc68897809ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728105990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.728105990
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3120865588
Short name T414
Test name
Test status
Simulation time 352168754 ps
CPU time 0.74 seconds
Started Jul 04 05:36:10 PM PDT 24
Finished Jul 04 05:36:10 PM PDT 24
Peak memory 183620 kb
Host smart-fc242b75-e6c7-4d0a-994f-0722efa8b7d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120865588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3120865588
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3568516491
Short name T410
Test name
Test status
Simulation time 511479840 ps
CPU time 0.7 seconds
Started Jul 04 05:36:09 PM PDT 24
Finished Jul 04 05:36:10 PM PDT 24
Peak memory 183704 kb
Host smart-a9927a16-87f6-4845-b584-763fbbf862cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568516491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3568516491
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.426332127
Short name T411
Test name
Test status
Simulation time 2241199441 ps
CPU time 2.27 seconds
Started Jul 04 05:36:07 PM PDT 24
Finished Jul 04 05:36:10 PM PDT 24
Peak memory 195132 kb
Host smart-339c3013-7b9e-456d-81fe-a24bd44a1dcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426332127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.426332127
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1052519609
Short name T281
Test name
Test status
Simulation time 536714475 ps
CPU time 2.71 seconds
Started Jul 04 05:36:04 PM PDT 24
Finished Jul 04 05:36:07 PM PDT 24
Peak memory 198612 kb
Host smart-d0f2bbc0-a331-42b9-9537-655739cc2f56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052519609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1052519609
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1921320775
Short name T35
Test name
Test status
Simulation time 7995921052 ps
CPU time 12.61 seconds
Started Jul 04 05:36:04 PM PDT 24
Finished Jul 04 05:36:17 PM PDT 24
Peak memory 198152 kb
Host smart-c0801201-4118-4f1f-a670-d44e7f6df70d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921320775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1921320775
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.134783548
Short name T395
Test name
Test status
Simulation time 476649496 ps
CPU time 1.15 seconds
Started Jul 04 05:36:37 PM PDT 24
Finished Jul 04 05:36:38 PM PDT 24
Peak memory 192924 kb
Host smart-f3a1a3d1-b364-476b-b271-0d81e5e50f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134783548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.134783548
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1189102445
Short name T409
Test name
Test status
Simulation time 342748615 ps
CPU time 0.69 seconds
Started Jul 04 05:36:37 PM PDT 24
Finished Jul 04 05:36:38 PM PDT 24
Peak memory 183720 kb
Host smart-e6c47b9e-bfdf-4cc7-b567-aa4ec3376151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189102445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1189102445
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3067871393
Short name T350
Test name
Test status
Simulation time 283306707 ps
CPU time 0.71 seconds
Started Jul 04 05:36:36 PM PDT 24
Finished Jul 04 05:36:38 PM PDT 24
Peak memory 192928 kb
Host smart-1b0e383f-0a8d-477b-8226-5a529b102392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067871393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3067871393
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2931374015
Short name T360
Test name
Test status
Simulation time 558827256 ps
CPU time 0.65 seconds
Started Jul 04 05:36:43 PM PDT 24
Finished Jul 04 05:36:43 PM PDT 24
Peak memory 183704 kb
Host smart-703bb881-d8e1-44d4-9272-4b3a9b38bd96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931374015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2931374015
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.799481269
Short name T407
Test name
Test status
Simulation time 406801186 ps
CPU time 1.19 seconds
Started Jul 04 05:36:43 PM PDT 24
Finished Jul 04 05:36:44 PM PDT 24
Peak memory 192924 kb
Host smart-c49b1f16-6cd7-4c06-8bd8-46913720bf88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799481269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.799481269
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1569994924
Short name T346
Test name
Test status
Simulation time 502913541 ps
CPU time 0.89 seconds
Started Jul 04 05:36:38 PM PDT 24
Finished Jul 04 05:36:39 PM PDT 24
Peak memory 183720 kb
Host smart-055eee77-b3fd-46a8-83c4-f02bfb883cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569994924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1569994924
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1715902284
Short name T329
Test name
Test status
Simulation time 446500462 ps
CPU time 0.83 seconds
Started Jul 04 05:36:41 PM PDT 24
Finished Jul 04 05:36:42 PM PDT 24
Peak memory 183732 kb
Host smart-9e9793db-acb7-4aa4-9128-cf8f15a8a22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715902284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1715902284
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3426795583
Short name T391
Test name
Test status
Simulation time 443386021 ps
CPU time 0.75 seconds
Started Jul 04 05:36:39 PM PDT 24
Finished Jul 04 05:36:40 PM PDT 24
Peak memory 183724 kb
Host smart-bb1ff920-473d-473e-aa19-3f97fc52e169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426795583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3426795583
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1351585395
Short name T345
Test name
Test status
Simulation time 421208296 ps
CPU time 1.12 seconds
Started Jul 04 05:36:37 PM PDT 24
Finished Jul 04 05:36:38 PM PDT 24
Peak memory 192888 kb
Host smart-7341c5e7-29db-416e-95df-2b8dc9cb1e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351585395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1351585395
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3150199498
Short name T369
Test name
Test status
Simulation time 453811588 ps
CPU time 1.2 seconds
Started Jul 04 05:36:41 PM PDT 24
Finished Jul 04 05:36:42 PM PDT 24
Peak memory 183708 kb
Host smart-d1835b58-3694-4c75-8ac3-9ca4488e1ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150199498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3150199498
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2532476240
Short name T364
Test name
Test status
Simulation time 622109061 ps
CPU time 0.93 seconds
Started Jul 04 05:36:08 PM PDT 24
Finished Jul 04 05:36:09 PM PDT 24
Peak memory 196096 kb
Host smart-0bc58a11-91ac-4471-8977-c1327381dd86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532476240 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2532476240
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1459813122
Short name T336
Test name
Test status
Simulation time 433620789 ps
CPU time 1.22 seconds
Started Jul 04 05:36:07 PM PDT 24
Finished Jul 04 05:36:09 PM PDT 24
Peak memory 193332 kb
Host smart-aecb2d81-9a44-4888-9bb9-af845daac456
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459813122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1459813122
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1485420546
Short name T351
Test name
Test status
Simulation time 519229634 ps
CPU time 1.44 seconds
Started Jul 04 05:36:12 PM PDT 24
Finished Jul 04 05:36:13 PM PDT 24
Peak memory 183704 kb
Host smart-89d7c650-8780-4ffe-80d4-3eb68fce2569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485420546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1485420546
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.365014817
Short name T358
Test name
Test status
Simulation time 1212786529 ps
CPU time 1.95 seconds
Started Jul 04 05:36:11 PM PDT 24
Finished Jul 04 05:36:13 PM PDT 24
Peak memory 193588 kb
Host smart-b65a95b5-3622-4d28-84ea-c2a7fc069769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365014817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.365014817
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.487424811
Short name T332
Test name
Test status
Simulation time 293606441 ps
CPU time 1.47 seconds
Started Jul 04 05:36:11 PM PDT 24
Finished Jul 04 05:36:12 PM PDT 24
Peak memory 198648 kb
Host smart-71f23246-67ea-40a3-a9c1-0f15d03de187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487424811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.487424811
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1710613420
Short name T199
Test name
Test status
Simulation time 7719508473 ps
CPU time 6.9 seconds
Started Jul 04 05:36:09 PM PDT 24
Finished Jul 04 05:36:16 PM PDT 24
Peak memory 198024 kb
Host smart-187cf7c5-d31f-4e5b-9c89-2b41ae8dbc6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710613420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1710613420
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3566062785
Short name T326
Test name
Test status
Simulation time 548522437 ps
CPU time 0.9 seconds
Started Jul 04 05:36:21 PM PDT 24
Finished Jul 04 05:36:22 PM PDT 24
Peak memory 198308 kb
Host smart-36ffc328-1370-467f-951a-b6cc71bbba6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566062785 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3566062785
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3052842267
Short name T60
Test name
Test status
Simulation time 465703514 ps
CPU time 0.74 seconds
Started Jul 04 05:36:10 PM PDT 24
Finished Jul 04 05:36:11 PM PDT 24
Peak memory 193148 kb
Host smart-2933f008-5461-42c3-88eb-f3272308b68d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052842267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3052842267
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3853311902
Short name T275
Test name
Test status
Simulation time 283512547 ps
CPU time 0.69 seconds
Started Jul 04 05:36:12 PM PDT 24
Finished Jul 04 05:36:13 PM PDT 24
Peak memory 183712 kb
Host smart-e1bf84aa-5718-4171-a569-703e20280579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853311902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3853311902
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.279987979
Short name T317
Test name
Test status
Simulation time 2502303135 ps
CPU time 2.31 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:18 PM PDT 24
Peak memory 194088 kb
Host smart-d551129a-f2c7-43a8-ba68-1b9b8659c94a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279987979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.279987979
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3468567136
Short name T361
Test name
Test status
Simulation time 425429582 ps
CPU time 2.06 seconds
Started Jul 04 05:36:13 PM PDT 24
Finished Jul 04 05:36:15 PM PDT 24
Peak memory 198600 kb
Host smart-363b5292-fa59-4dc4-966f-b24bdf4222e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468567136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3468567136
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.726328327
Short name T404
Test name
Test status
Simulation time 4266564028 ps
CPU time 2.22 seconds
Started Jul 04 05:36:08 PM PDT 24
Finished Jul 04 05:36:10 PM PDT 24
Peak memory 198012 kb
Host smart-40e0d17a-13bc-4bb3-8044-e8904ad9ee18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726328327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.726328327
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1053717757
Short name T385
Test name
Test status
Simulation time 424385610 ps
CPU time 0.81 seconds
Started Jul 04 05:36:18 PM PDT 24
Finished Jul 04 05:36:19 PM PDT 24
Peak memory 196508 kb
Host smart-d481364d-f18b-4996-8430-693793d4ec3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053717757 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1053717757
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.255314368
Short name T63
Test name
Test status
Simulation time 526623523 ps
CPU time 0.96 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:17 PM PDT 24
Peak memory 193140 kb
Host smart-ffee3916-98a1-4556-99d5-e9ea6e7a674f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255314368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.255314368
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1445990057
Short name T277
Test name
Test status
Simulation time 340679904 ps
CPU time 0.71 seconds
Started Jul 04 05:36:15 PM PDT 24
Finished Jul 04 05:36:16 PM PDT 24
Peak memory 192940 kb
Host smart-f1fbc400-0229-452c-b4a7-1fbc4ab53762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445990057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1445990057
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1953354512
Short name T80
Test name
Test status
Simulation time 1076504857 ps
CPU time 1.03 seconds
Started Jul 04 05:36:18 PM PDT 24
Finished Jul 04 05:36:20 PM PDT 24
Peak memory 193652 kb
Host smart-07bbb833-2131-4a10-a75a-1901260c3f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953354512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1953354512
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.666834074
Short name T333
Test name
Test status
Simulation time 349942623 ps
CPU time 2.01 seconds
Started Jul 04 05:36:20 PM PDT 24
Finished Jul 04 05:36:22 PM PDT 24
Peak memory 198516 kb
Host smart-80211751-3283-4ea5-9544-aeecceb0f54d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666834074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.666834074
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2796633029
Short name T201
Test name
Test status
Simulation time 8196222933 ps
CPU time 6.65 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:23 PM PDT 24
Peak memory 198156 kb
Host smart-d5629255-4f83-4872-874c-a1eebfdabdcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796633029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2796633029
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3212706750
Short name T282
Test name
Test status
Simulation time 557461902 ps
CPU time 1.03 seconds
Started Jul 04 05:36:17 PM PDT 24
Finished Jul 04 05:36:18 PM PDT 24
Peak memory 195808 kb
Host smart-e7524690-9798-4fa2-b58b-fb431f15208a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212706750 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3212706750
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1159142287
Short name T59
Test name
Test status
Simulation time 305973670 ps
CPU time 0.9 seconds
Started Jul 04 05:36:15 PM PDT 24
Finished Jul 04 05:36:16 PM PDT 24
Peak memory 193000 kb
Host smart-543b876b-1188-426e-a3e4-712e1f12ae3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159142287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1159142287
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.97037345
Short name T308
Test name
Test status
Simulation time 423349161 ps
CPU time 1.13 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:18 PM PDT 24
Peak memory 183736 kb
Host smart-87980c8d-b8ee-4285-b62e-53a697ec12e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97037345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.97037345
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1845884810
Short name T38
Test name
Test status
Simulation time 2561721855 ps
CPU time 2.09 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:19 PM PDT 24
Peak memory 194108 kb
Host smart-4440f133-1a31-4c3a-b891-3640042376d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845884810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1845884810
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2068345029
Short name T323
Test name
Test status
Simulation time 405536684 ps
CPU time 1.28 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:18 PM PDT 24
Peak memory 198548 kb
Host smart-05527c23-7c05-4ec9-9f3c-de70e866d6de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068345029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2068345029
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2253646865
Short name T354
Test name
Test status
Simulation time 3928722104 ps
CPU time 4.03 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:20 PM PDT 24
Peak memory 196804 kb
Host smart-5d0d23d3-19b5-4b3b-9109-50dfcdc0a95a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253646865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2253646865
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.342303390
Short name T303
Test name
Test status
Simulation time 604926082 ps
CPU time 1.5 seconds
Started Jul 04 05:36:27 PM PDT 24
Finished Jul 04 05:36:29 PM PDT 24
Peak memory 196656 kb
Host smart-cd9f3878-9f3f-48ed-b222-23ccf765c22b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342303390 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.342303390
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2123217397
Short name T394
Test name
Test status
Simulation time 454733491 ps
CPU time 0.72 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:17 PM PDT 24
Peak memory 192972 kb
Host smart-0939ce67-ec09-4554-8b20-7c6659cfe92c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123217397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2123217397
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2801057571
Short name T307
Test name
Test status
Simulation time 366283432 ps
CPU time 0.62 seconds
Started Jul 04 05:36:17 PM PDT 24
Finished Jul 04 05:36:18 PM PDT 24
Peak memory 192940 kb
Host smart-4e10911b-ac64-4a83-a846-b4a5dab1fdf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801057571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2801057571
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2656532388
Short name T383
Test name
Test status
Simulation time 1375278845 ps
CPU time 1.55 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:18 PM PDT 24
Peak memory 192992 kb
Host smart-b1304758-b37c-4443-b405-792144c03a16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656532388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2656532388
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3582648284
Short name T331
Test name
Test status
Simulation time 453397060 ps
CPU time 2.07 seconds
Started Jul 04 05:36:20 PM PDT 24
Finished Jul 04 05:36:22 PM PDT 24
Peak memory 198512 kb
Host smart-372c9c5a-88c5-476d-8704-466a15e33cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582648284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3582648284
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.42236935
Short name T375
Test name
Test status
Simulation time 8815705635 ps
CPU time 3.84 seconds
Started Jul 04 05:36:16 PM PDT 24
Finished Jul 04 05:36:20 PM PDT 24
Peak memory 198140 kb
Host smart-99c2b569-fbb8-4c65-94ca-27c6de972bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42236935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_i
ntg_err.42236935
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2113716630
Short name T217
Test name
Test status
Simulation time 15738645963 ps
CPU time 14.33 seconds
Started Jul 04 05:35:02 PM PDT 24
Finished Jul 04 05:35:16 PM PDT 24
Peak memory 191056 kb
Host smart-8f957115-8ad7-49f7-aeb6-19e4d613f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113716630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2113716630
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.980509131
Short name T269
Test name
Test status
Simulation time 500533258 ps
CPU time 1.29 seconds
Started Jul 04 05:35:02 PM PDT 24
Finished Jul 04 05:35:03 PM PDT 24
Peak memory 195692 kb
Host smart-ad66f883-5b56-4463-b978-e08ced53724e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980509131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.980509131
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3908834033
Short name T225
Test name
Test status
Simulation time 34342226453 ps
CPU time 22.75 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:35:24 PM PDT 24
Peak memory 196900 kb
Host smart-e39a549e-f615-4601-a4b3-ea78117f8bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908834033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3908834033
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2535244031
Short name T17
Test name
Test status
Simulation time 4219872354 ps
CPU time 2.13 seconds
Started Jul 04 05:35:02 PM PDT 24
Finished Jul 04 05:35:04 PM PDT 24
Peak memory 215340 kb
Host smart-66bc2814-4f52-4b47-b131-c0e64d8c7172
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535244031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2535244031
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1852162279
Short name T25
Test name
Test status
Simulation time 544379280 ps
CPU time 0.7 seconds
Started Jul 04 05:35:04 PM PDT 24
Finished Jul 04 05:35:05 PM PDT 24
Peak memory 191836 kb
Host smart-e985ac99-dc22-47c9-b376-f5f05accfeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852162279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1852162279
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3882932496
Short name T191
Test name
Test status
Simulation time 678327780 ps
CPU time 0.66 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:09 PM PDT 24
Peak memory 196604 kb
Host smart-9a841016-17b6-4348-be81-6478c4e23589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882932496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3882932496
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1231988314
Short name T239
Test name
Test status
Simulation time 44851100167 ps
CPU time 45.33 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:55 PM PDT 24
Peak memory 191892 kb
Host smart-b4e84175-99ad-461a-909f-da2cc0349fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231988314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1231988314
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.546127779
Short name T216
Test name
Test status
Simulation time 607063326 ps
CPU time 0.88 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:11 PM PDT 24
Peak memory 191820 kb
Host smart-c25abffa-58d3-4a82-9e03-88fa4849ab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546127779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.546127779
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2789491181
Short name T202
Test name
Test status
Simulation time 27622424368 ps
CPU time 10.4 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:21 PM PDT 24
Peak memory 196928 kb
Host smart-843a40d3-da1f-4242-88e6-9ad164cbcfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789491181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2789491181
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3720635055
Short name T260
Test name
Test status
Simulation time 484117535 ps
CPU time 0.94 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:35:12 PM PDT 24
Peak memory 191856 kb
Host smart-b205fc37-2a8b-4c97-be6f-7e4f5fbde90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720635055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3720635055
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1197920731
Short name T248
Test name
Test status
Simulation time 22306930089 ps
CPU time 9.51 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:20 PM PDT 24
Peak memory 191892 kb
Host smart-ad41f07c-5849-4132-9fd8-9878fd6fbe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197920731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1197920731
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3376885124
Short name T232
Test name
Test status
Simulation time 547347178 ps
CPU time 1.31 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:12 PM PDT 24
Peak memory 191864 kb
Host smart-6ec6ec4e-f63b-4dc4-ae9b-e1d4d60564b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376885124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3376885124
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1308063429
Short name T267
Test name
Test status
Simulation time 10050072589 ps
CPU time 13.71 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:35:25 PM PDT 24
Peak memory 191928 kb
Host smart-e6674380-a3bc-49fa-bc03-90ba1cbe7022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308063429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1308063429
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2267150936
Short name T77
Test name
Test status
Simulation time 490878399 ps
CPU time 1.24 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:11 PM PDT 24
Peak memory 191728 kb
Host smart-2ba34a6b-6cf5-4d64-b3cf-559cb281a266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267150936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2267150936
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3180236164
Short name T52
Test name
Test status
Simulation time 16026305871 ps
CPU time 1.84 seconds
Started Jul 04 05:35:10 PM PDT 24
Finished Jul 04 05:35:13 PM PDT 24
Peak memory 191876 kb
Host smart-229d41f9-794a-4a0e-b20e-0722df20db1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180236164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3180236164
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1813727421
Short name T27
Test name
Test status
Simulation time 611906815 ps
CPU time 0.71 seconds
Started Jul 04 05:35:08 PM PDT 24
Finished Jul 04 05:35:09 PM PDT 24
Peak memory 191852 kb
Host smart-38b2a221-1c4d-400a-8f6c-f56d160eedeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813727421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1813727421
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1174320409
Short name T238
Test name
Test status
Simulation time 37492112376 ps
CPU time 12.62 seconds
Started Jul 04 05:35:20 PM PDT 24
Finished Jul 04 05:35:33 PM PDT 24
Peak memory 191928 kb
Host smart-ecbe5af0-4c03-48f8-a6e2-71cf35c1de02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174320409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1174320409
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3805871091
Short name T241
Test name
Test status
Simulation time 427833422 ps
CPU time 0.72 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:35:12 PM PDT 24
Peak memory 196672 kb
Host smart-ebc4b0b2-f421-4121-97f8-58a17c45ac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805871091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3805871091
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1820112874
Short name T9
Test name
Test status
Simulation time 16905308669 ps
CPU time 18.29 seconds
Started Jul 04 05:35:19 PM PDT 24
Finished Jul 04 05:35:38 PM PDT 24
Peak memory 196776 kb
Host smart-45b13261-59c6-4158-a640-50f44c5cb91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820112874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1820112874
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.513455654
Short name T29
Test name
Test status
Simulation time 494374034 ps
CPU time 1.17 seconds
Started Jul 04 05:35:15 PM PDT 24
Finished Jul 04 05:35:17 PM PDT 24
Peak memory 191864 kb
Host smart-b2b738f9-3c93-4edc-aeb2-4f873d5d10fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513455654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.513455654
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3975117165
Short name T253
Test name
Test status
Simulation time 35599577117 ps
CPU time 53.73 seconds
Started Jul 04 05:35:26 PM PDT 24
Finished Jul 04 05:36:20 PM PDT 24
Peak memory 191916 kb
Host smart-e4268d2b-b2f5-409b-af0a-7911f39e3d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975117165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3975117165
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2805010256
Short name T245
Test name
Test status
Simulation time 535079211 ps
CPU time 0.77 seconds
Started Jul 04 05:35:17 PM PDT 24
Finished Jul 04 05:35:17 PM PDT 24
Peak memory 191852 kb
Host smart-44ba9722-12a0-41e7-afe2-27f99f342e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805010256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2805010256
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3408091395
Short name T24
Test name
Test status
Simulation time 17842181352 ps
CPU time 26.95 seconds
Started Jul 04 05:35:18 PM PDT 24
Finished Jul 04 05:35:46 PM PDT 24
Peak memory 196912 kb
Host smart-e9347898-dcd2-481d-8ee5-aad62cef096b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408091395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3408091395
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3108145264
Short name T265
Test name
Test status
Simulation time 414260467 ps
CPU time 1.11 seconds
Started Jul 04 05:35:18 PM PDT 24
Finished Jul 04 05:35:20 PM PDT 24
Peak memory 191716 kb
Host smart-373ee3ce-55d6-4252-9f23-e7f9398a08a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108145264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3108145264
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.944559873
Short name T243
Test name
Test status
Simulation time 15942638908 ps
CPU time 6.2 seconds
Started Jul 04 05:35:18 PM PDT 24
Finished Jul 04 05:35:24 PM PDT 24
Peak memory 196924 kb
Host smart-3d465149-c119-4e8e-a67e-62e45bd14ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944559873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.944559873
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1555129488
Short name T47
Test name
Test status
Simulation time 560541050 ps
CPU time 1.01 seconds
Started Jul 04 05:35:15 PM PDT 24
Finished Jul 04 05:35:17 PM PDT 24
Peak memory 191856 kb
Host smart-1e322885-22d1-4023-baac-6ccbc222c52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555129488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1555129488
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1418735249
Short name T91
Test name
Test status
Simulation time 30344335222 ps
CPU time 39.16 seconds
Started Jul 04 05:35:00 PM PDT 24
Finished Jul 04 05:35:39 PM PDT 24
Peak memory 191908 kb
Host smart-af6b6fb1-c701-4f44-a68d-641b64a0c985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418735249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1418735249
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.987112695
Short name T16
Test name
Test status
Simulation time 4039254364 ps
CPU time 6.02 seconds
Started Jul 04 05:35:05 PM PDT 24
Finished Jul 04 05:35:11 PM PDT 24
Peak memory 215656 kb
Host smart-576de3fa-04a8-43c6-b99d-4b0937af2d37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987112695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.987112695
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3244850696
Short name T214
Test name
Test status
Simulation time 393638077 ps
CPU time 1.16 seconds
Started Jul 04 05:35:03 PM PDT 24
Finished Jul 04 05:35:04 PM PDT 24
Peak memory 196660 kb
Host smart-f7222469-6ebc-4348-859b-1978c28be24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244850696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3244850696
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.251325295
Short name T86
Test name
Test status
Simulation time 558389283 ps
CPU time 1.43 seconds
Started Jul 04 05:35:14 PM PDT 24
Finished Jul 04 05:35:16 PM PDT 24
Peak memory 191836 kb
Host smart-72a0b255-0966-4f0f-9efb-02cab4e0ca2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251325295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.251325295
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3028676493
Short name T224
Test name
Test status
Simulation time 721305682 ps
CPU time 0.91 seconds
Started Jul 04 05:35:18 PM PDT 24
Finished Jul 04 05:35:19 PM PDT 24
Peak memory 196540 kb
Host smart-5505fbaf-e2a8-4b70-8b3f-2b42c6a35bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028676493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3028676493
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1021071809
Short name T43
Test name
Test status
Simulation time 508137946 ps
CPU time 1.23 seconds
Started Jul 04 05:35:18 PM PDT 24
Finished Jul 04 05:35:19 PM PDT 24
Peak memory 191828 kb
Host smart-ca8e359d-5359-4b8e-afe4-d33ae46a7ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021071809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1021071809
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_jump.4207465042
Short name T196
Test name
Test status
Simulation time 513195779 ps
CPU time 0.94 seconds
Started Jul 04 05:35:17 PM PDT 24
Finished Jul 04 05:35:18 PM PDT 24
Peak memory 196644 kb
Host smart-953cbffe-6353-413e-bdba-77c097425442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207465042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.4207465042
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1314205402
Short name T206
Test name
Test status
Simulation time 35048994598 ps
CPU time 27.24 seconds
Started Jul 04 05:35:19 PM PDT 24
Finished Jul 04 05:35:46 PM PDT 24
Peak memory 191928 kb
Host smart-38937bcc-9ad8-4cf4-8636-e566cd3833e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314205402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1314205402
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4197264911
Short name T230
Test name
Test status
Simulation time 578643972 ps
CPU time 0.99 seconds
Started Jul 04 05:35:17 PM PDT 24
Finished Jul 04 05:35:18 PM PDT 24
Peak memory 191860 kb
Host smart-47dcaba4-405f-4269-a3e6-9bfff4a09744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197264911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4197264911
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.96113174
Short name T88
Test name
Test status
Simulation time 24626757020 ps
CPU time 26.22 seconds
Started Jul 04 05:35:17 PM PDT 24
Finished Jul 04 05:35:43 PM PDT 24
Peak memory 191928 kb
Host smart-044bae1b-aad9-43d0-856d-0b89a0fb3e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96113174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.96113174
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1716365801
Short name T223
Test name
Test status
Simulation time 430560163 ps
CPU time 1.22 seconds
Started Jul 04 05:35:22 PM PDT 24
Finished Jul 04 05:35:24 PM PDT 24
Peak memory 191844 kb
Host smart-0603fe3b-88b3-43b2-b349-2ec87c39e7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716365801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1716365801
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.39348406
Short name T205
Test name
Test status
Simulation time 53548869940 ps
CPU time 19.39 seconds
Started Jul 04 05:35:19 PM PDT 24
Finished Jul 04 05:35:39 PM PDT 24
Peak memory 196924 kb
Host smart-281d3385-ec85-47d6-ae98-75b114827d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39348406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.39348406
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.747600814
Short name T212
Test name
Test status
Simulation time 361767086 ps
CPU time 0.82 seconds
Started Jul 04 05:35:26 PM PDT 24
Finished Jul 04 05:35:27 PM PDT 24
Peak memory 191856 kb
Host smart-3c77f4bd-399d-429e-97c0-4ff12d46a418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747600814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.747600814
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4064864691
Short name T213
Test name
Test status
Simulation time 16905395454 ps
CPU time 11.13 seconds
Started Jul 04 05:35:21 PM PDT 24
Finished Jul 04 05:35:32 PM PDT 24
Peak memory 196928 kb
Host smart-cae1d150-ea75-4ffa-8c4c-cdfec235e751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064864691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4064864691
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3876252049
Short name T250
Test name
Test status
Simulation time 492219547 ps
CPU time 1.11 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:35:24 PM PDT 24
Peak memory 196676 kb
Host smart-964cd391-6d6a-47f3-b598-f88175ccb1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876252049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3876252049
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.355861956
Short name T262
Test name
Test status
Simulation time 35343033341 ps
CPU time 46.75 seconds
Started Jul 04 05:35:22 PM PDT 24
Finished Jul 04 05:36:09 PM PDT 24
Peak memory 191896 kb
Host smart-0dde9688-994d-45b1-aa79-1105a335a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355861956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.355861956
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1842885344
Short name T49
Test name
Test status
Simulation time 524300609 ps
CPU time 0.97 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:35:24 PM PDT 24
Peak memory 191824 kb
Host smart-c9ced858-ef1f-4dab-86be-3b0ef58f93d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842885344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1842885344
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1351715025
Short name T234
Test name
Test status
Simulation time 37285034857 ps
CPU time 51.17 seconds
Started Jul 04 05:35:21 PM PDT 24
Finished Jul 04 05:36:12 PM PDT 24
Peak memory 191888 kb
Host smart-ea150ccc-c687-4d10-93c9-2650a22da932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351715025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1351715025
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2357458773
Short name T227
Test name
Test status
Simulation time 496587123 ps
CPU time 1.05 seconds
Started Jul 04 05:35:22 PM PDT 24
Finished Jul 04 05:35:24 PM PDT 24
Peak memory 191824 kb
Host smart-3a1cc71f-8b00-4536-abbf-a4b9e7dfa854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357458773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2357458773
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.765332213
Short name T247
Test name
Test status
Simulation time 48793441934 ps
CPU time 65.6 seconds
Started Jul 04 05:35:22 PM PDT 24
Finished Jul 04 05:36:27 PM PDT 24
Peak memory 191896 kb
Host smart-e28dc48c-eb31-453f-bcfc-0d8ed2daf3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765332213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.765332213
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1275815777
Short name T72
Test name
Test status
Simulation time 464823931 ps
CPU time 0.75 seconds
Started Jul 04 05:35:23 PM PDT 24
Finished Jul 04 05:35:24 PM PDT 24
Peak memory 191884 kb
Host smart-28b6a968-0572-402c-84ab-dd3a375399ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275815777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1275815777
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_jump.398744666
Short name T186
Test name
Test status
Simulation time 506949708 ps
CPU time 1.19 seconds
Started Jul 04 05:35:22 PM PDT 24
Finished Jul 04 05:35:23 PM PDT 24
Peak memory 196708 kb
Host smart-fc1f443e-5d90-4db1-bfd2-fcee5186443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398744666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.398744666
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1554783897
Short name T21
Test name
Test status
Simulation time 26121097867 ps
CPU time 37.7 seconds
Started Jul 04 05:35:21 PM PDT 24
Finished Jul 04 05:35:59 PM PDT 24
Peak memory 191912 kb
Host smart-9ccf9451-c9fc-46c0-9c78-d21df67f5628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554783897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1554783897
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4016077078
Short name T236
Test name
Test status
Simulation time 405426421 ps
CPU time 0.83 seconds
Started Jul 04 05:35:21 PM PDT 24
Finished Jul 04 05:35:22 PM PDT 24
Peak memory 191816 kb
Host smart-8d6a31a0-827a-442d-995c-bef16be08fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016077078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4016077078
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_jump.79792374
Short name T195
Test name
Test status
Simulation time 570527980 ps
CPU time 0.65 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:35:02 PM PDT 24
Peak memory 196616 kb
Host smart-cac9b397-cd14-487f-9ee4-45c9736813db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79792374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.79792374
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3881725129
Short name T263
Test name
Test status
Simulation time 28096952643 ps
CPU time 8.06 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:35:09 PM PDT 24
Peak memory 191888 kb
Host smart-bccda80d-8330-430e-a755-8d25f70fa5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881725129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3881725129
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1313964806
Short name T18
Test name
Test status
Simulation time 7631918787 ps
CPU time 3.59 seconds
Started Jul 04 05:35:02 PM PDT 24
Finished Jul 04 05:35:06 PM PDT 24
Peak memory 215764 kb
Host smart-e4ea2e07-eb9e-4e8e-8676-e4a9be93a7bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313964806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1313964806
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1378923732
Short name T87
Test name
Test status
Simulation time 534212242 ps
CPU time 0.81 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:35:02 PM PDT 24
Peak memory 191836 kb
Host smart-8f5da3c4-f363-4569-b9d6-279c40392f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378923732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1378923732
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2280479332
Short name T220
Test name
Test status
Simulation time 13365821380 ps
CPU time 19.63 seconds
Started Jul 04 05:35:30 PM PDT 24
Finished Jul 04 05:35:50 PM PDT 24
Peak memory 191880 kb
Host smart-2cad1564-08b0-4cac-ae06-130e2ab88509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280479332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2280479332
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3477234954
Short name T203
Test name
Test status
Simulation time 494689476 ps
CPU time 1.29 seconds
Started Jul 04 05:35:21 PM PDT 24
Finished Jul 04 05:35:22 PM PDT 24
Peak memory 196712 kb
Host smart-2d51850e-b117-4d77-a457-8746d5fd1fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477234954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3477234954
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1732158639
Short name T215
Test name
Test status
Simulation time 33357992754 ps
CPU time 17.43 seconds
Started Jul 04 05:35:29 PM PDT 24
Finished Jul 04 05:35:47 PM PDT 24
Peak memory 191920 kb
Host smart-9efffff2-04f8-437b-8b2f-c78047a4b425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732158639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1732158639
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1542053626
Short name T271
Test name
Test status
Simulation time 501780362 ps
CPU time 1.25 seconds
Started Jul 04 05:35:29 PM PDT 24
Finished Jul 04 05:35:31 PM PDT 24
Peak memory 191868 kb
Host smart-8673f5b6-cc1b-4bd6-b62e-5e4a9f80478a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542053626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1542053626
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.41598709
Short name T184
Test name
Test status
Simulation time 230200013714 ps
CPU time 88.66 seconds
Started Jul 04 05:35:32 PM PDT 24
Finished Jul 04 05:37:01 PM PDT 24
Peak memory 198260 kb
Host smart-24a410ff-8abe-4712-a6e5-160a404e550f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41598709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_al
l.41598709
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.70902252
Short name T274
Test name
Test status
Simulation time 21227291666 ps
CPU time 8.54 seconds
Started Jul 04 05:35:30 PM PDT 24
Finished Jul 04 05:35:39 PM PDT 24
Peak memory 196884 kb
Host smart-fe40ad7b-2513-4956-b221-0c274282fcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70902252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.70902252
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2680375635
Short name T233
Test name
Test status
Simulation time 531886349 ps
CPU time 0.76 seconds
Started Jul 04 05:35:27 PM PDT 24
Finished Jul 04 05:35:28 PM PDT 24
Peak memory 196716 kb
Host smart-d4726a01-fb50-4525-824a-1f3d07523f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680375635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2680375635
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3385762050
Short name T48
Test name
Test status
Simulation time 33654994483 ps
CPU time 11.78 seconds
Started Jul 04 05:35:41 PM PDT 24
Finished Jul 04 05:35:53 PM PDT 24
Peak memory 191916 kb
Host smart-afc8d873-4542-44de-b180-c67fe6135ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385762050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3385762050
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2533964461
Short name T209
Test name
Test status
Simulation time 515305498 ps
CPU time 0.88 seconds
Started Jul 04 05:35:36 PM PDT 24
Finished Jul 04 05:35:37 PM PDT 24
Peak memory 191840 kb
Host smart-8c8495b9-5fb6-427c-a0a6-ead61f2f09bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533964461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2533964461
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.505214844
Short name T244
Test name
Test status
Simulation time 45086088250 ps
CPU time 60.21 seconds
Started Jul 04 05:35:38 PM PDT 24
Finished Jul 04 05:36:38 PM PDT 24
Peak memory 191916 kb
Host smart-29f22a72-791f-424b-8371-260c6b6ab155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505214844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.505214844
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.644430086
Short name T240
Test name
Test status
Simulation time 584455986 ps
CPU time 1.04 seconds
Started Jul 04 05:35:36 PM PDT 24
Finished Jul 04 05:35:37 PM PDT 24
Peak memory 196696 kb
Host smart-95a699ba-022e-459c-be2a-112bdfbe4e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644430086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.644430086
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1404592113
Short name T192
Test name
Test status
Simulation time 484321097 ps
CPU time 0.73 seconds
Started Jul 04 05:35:41 PM PDT 24
Finished Jul 04 05:35:42 PM PDT 24
Peak memory 196640 kb
Host smart-014ce0dc-c428-4c6e-a4e4-b905346628ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404592113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1404592113
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2921892040
Short name T259
Test name
Test status
Simulation time 19880193044 ps
CPU time 28.49 seconds
Started Jul 04 05:35:38 PM PDT 24
Finished Jul 04 05:36:07 PM PDT 24
Peak memory 196772 kb
Host smart-ddd6324c-1dac-44c3-ab0c-1b12c41bd4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921892040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2921892040
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3320402074
Short name T219
Test name
Test status
Simulation time 360922522 ps
CPU time 1.04 seconds
Started Jul 04 05:35:34 PM PDT 24
Finished Jul 04 05:35:35 PM PDT 24
Peak memory 196704 kb
Host smart-18c573d8-4bd1-4732-8d4e-4df506ded17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320402074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3320402074
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1082683179
Short name T6
Test name
Test status
Simulation time 29412380362 ps
CPU time 44.35 seconds
Started Jul 04 05:35:43 PM PDT 24
Finished Jul 04 05:36:28 PM PDT 24
Peak memory 191844 kb
Host smart-1cc712c6-19d7-454d-aaeb-f8e3acbd2e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082683179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1082683179
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1916370872
Short name T257
Test name
Test status
Simulation time 450353951 ps
CPU time 0.65 seconds
Started Jul 04 05:35:41 PM PDT 24
Finished Jul 04 05:35:42 PM PDT 24
Peak memory 191840 kb
Host smart-4f0ff317-5422-454b-b3a2-fabef88fdf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916370872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1916370872
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1636007755
Short name T235
Test name
Test status
Simulation time 34728996031 ps
CPU time 13.28 seconds
Started Jul 04 05:35:42 PM PDT 24
Finished Jul 04 05:35:55 PM PDT 24
Peak memory 196832 kb
Host smart-ac9e21ae-ef38-4398-acb9-cee90cf33897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636007755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1636007755
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2932275642
Short name T258
Test name
Test status
Simulation time 461627139 ps
CPU time 1.23 seconds
Started Jul 04 05:35:43 PM PDT 24
Finished Jul 04 05:35:45 PM PDT 24
Peak memory 191812 kb
Host smart-c1f18363-188a-4f13-8e19-26fabd9fd69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932275642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2932275642
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1169569446
Short name T2
Test name
Test status
Simulation time 598092409 ps
CPU time 1.57 seconds
Started Jul 04 05:35:43 PM PDT 24
Finished Jul 04 05:35:45 PM PDT 24
Peak memory 196612 kb
Host smart-f67dc754-2854-42c6-9a9b-29c7b31d3a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169569446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1169569446
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1951132914
Short name T218
Test name
Test status
Simulation time 22713898350 ps
CPU time 7.93 seconds
Started Jul 04 05:35:43 PM PDT 24
Finished Jul 04 05:35:51 PM PDT 24
Peak memory 191888 kb
Host smart-2c2d0ecf-2cf2-45a1-8d87-b015de5d1258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951132914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1951132914
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3595019629
Short name T254
Test name
Test status
Simulation time 466283072 ps
CPU time 1.15 seconds
Started Jul 04 05:35:42 PM PDT 24
Finished Jul 04 05:35:43 PM PDT 24
Peak memory 191860 kb
Host smart-094d62e3-a4f8-4f46-b162-4beda0b1f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595019629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3595019629
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1505485480
Short name T20
Test name
Test status
Simulation time 456729213 ps
CPU time 0.69 seconds
Started Jul 04 05:35:42 PM PDT 24
Finished Jul 04 05:35:43 PM PDT 24
Peak memory 196644 kb
Host smart-c6de30fd-0474-4181-8b65-56a4fcca1d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505485480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1505485480
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.766670873
Short name T210
Test name
Test status
Simulation time 3543603522 ps
CPU time 1.45 seconds
Started Jul 04 05:35:45 PM PDT 24
Finished Jul 04 05:35:47 PM PDT 24
Peak memory 196740 kb
Host smart-7a7278ad-dbaa-4b3c-a86f-cda3e2c9f083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766670873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.766670873
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.33549048
Short name T90
Test name
Test status
Simulation time 406418868 ps
CPU time 1.11 seconds
Started Jul 04 05:35:40 PM PDT 24
Finished Jul 04 05:35:42 PM PDT 24
Peak memory 191860 kb
Host smart-c259b380-fd61-49da-909d-7d1002a5f2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33549048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.33549048
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3053638878
Short name T26
Test name
Test status
Simulation time 6420605263 ps
CPU time 9.68 seconds
Started Jul 04 05:35:02 PM PDT 24
Finished Jul 04 05:35:12 PM PDT 24
Peak memory 191908 kb
Host smart-c59734eb-dd16-434d-9a97-ec1b75667218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053638878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3053638878
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3123759239
Short name T15
Test name
Test status
Simulation time 4189547209 ps
CPU time 2.37 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:35:03 PM PDT 24
Peak memory 215324 kb
Host smart-978def97-187b-4929-bde4-c8010ab07909
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123759239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3123759239
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2433899303
Short name T51
Test name
Test status
Simulation time 383104082 ps
CPU time 0.92 seconds
Started Jul 04 05:35:00 PM PDT 24
Finished Jul 04 05:35:01 PM PDT 24
Peak memory 191812 kb
Host smart-7c00ce39-4bb8-493f-bf1c-698a4f6982f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433899303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2433899303
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3248315156
Short name T171
Test name
Test status
Simulation time 410525575 ps
CPU time 0.89 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:35:51 PM PDT 24
Peak memory 196736 kb
Host smart-968be66e-621c-47cf-b307-94d8f08c01c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248315156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3248315156
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2190800500
Short name T45
Test name
Test status
Simulation time 22467821763 ps
CPU time 7.73 seconds
Started Jul 04 05:35:53 PM PDT 24
Finished Jul 04 05:36:02 PM PDT 24
Peak memory 196876 kb
Host smart-a32dc5a2-95be-4eab-b3fe-7d48d4f24af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190800500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2190800500
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3082067281
Short name T226
Test name
Test status
Simulation time 523975846 ps
CPU time 0.73 seconds
Started Jul 04 05:35:52 PM PDT 24
Finished Jul 04 05:35:53 PM PDT 24
Peak memory 191820 kb
Host smart-a06398fe-5e46-4946-88ff-3100ccf371b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082067281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3082067281
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.166355332
Short name T221
Test name
Test status
Simulation time 18362955728 ps
CPU time 14.29 seconds
Started Jul 04 05:35:51 PM PDT 24
Finished Jul 04 05:36:06 PM PDT 24
Peak memory 191908 kb
Host smart-bd21ff03-7bb7-44c8-a180-ea93e52d4886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166355332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.166355332
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1383888730
Short name T54
Test name
Test status
Simulation time 490150820 ps
CPU time 1.13 seconds
Started Jul 04 05:35:49 PM PDT 24
Finished Jul 04 05:35:50 PM PDT 24
Peak memory 191812 kb
Host smart-23f0a95c-c49a-4cbf-b4dc-f9ba60ad3e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383888730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1383888730
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_jump.4216783253
Short name T89
Test name
Test status
Simulation time 346201090 ps
CPU time 0.98 seconds
Started Jul 04 05:35:52 PM PDT 24
Finished Jul 04 05:35:53 PM PDT 24
Peak memory 196504 kb
Host smart-f34fab80-9840-435f-8a26-dc253462b40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216783253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.4216783253
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1363102046
Short name T273
Test name
Test status
Simulation time 38505392397 ps
CPU time 28.22 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:36:18 PM PDT 24
Peak memory 191896 kb
Host smart-3206a57e-074e-47e7-9563-d626ef5ab720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363102046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1363102046
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3826890053
Short name T264
Test name
Test status
Simulation time 338619754 ps
CPU time 1.11 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:35:52 PM PDT 24
Peak memory 191832 kb
Host smart-2aeebcde-3c96-4477-a729-4a213e82322b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826890053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3826890053
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1734759209
Short name T222
Test name
Test status
Simulation time 17584497223 ps
CPU time 13.36 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 191900 kb
Host smart-4d336d23-f3d7-4bea-9c0f-9c712b23ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734759209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1734759209
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3462648078
Short name T231
Test name
Test status
Simulation time 376272987 ps
CPU time 0.99 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:35:52 PM PDT 24
Peak memory 191820 kb
Host smart-bc8f8b15-7bd5-4571-a64e-c5a9d25edd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462648078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3462648078
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3236587639
Short name T207
Test name
Test status
Simulation time 1697428957 ps
CPU time 2.75 seconds
Started Jul 04 05:35:51 PM PDT 24
Finished Jul 04 05:35:54 PM PDT 24
Peak memory 191820 kb
Host smart-0f2d96ce-f892-4a05-b9e6-f7b12d7d5f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236587639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3236587639
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1891645895
Short name T163
Test name
Test status
Simulation time 437425942 ps
CPU time 0.85 seconds
Started Jul 04 05:35:52 PM PDT 24
Finished Jul 04 05:35:53 PM PDT 24
Peak memory 191864 kb
Host smart-767b13de-117f-4393-bd89-7a2a5f56426b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891645895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1891645895
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3222246521
Short name T249
Test name
Test status
Simulation time 37653579544 ps
CPU time 14.54 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:36:05 PM PDT 24
Peak memory 196912 kb
Host smart-ae6b4076-281a-4632-9c42-e79abbea14d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222246521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3222246521
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3706354349
Short name T242
Test name
Test status
Simulation time 496109659 ps
CPU time 0.74 seconds
Started Jul 04 05:35:50 PM PDT 24
Finished Jul 04 05:35:51 PM PDT 24
Peak memory 196700 kb
Host smart-1cfa6799-ad49-4923-91a7-8364084c0028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706354349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3706354349
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2355866108
Short name T23
Test name
Test status
Simulation time 44933900038 ps
CPU time 11.78 seconds
Started Jul 04 05:35:53 PM PDT 24
Finished Jul 04 05:36:05 PM PDT 24
Peak memory 191880 kb
Host smart-a4b53ffd-f51d-4d65-a4be-10b9076bc62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355866108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2355866108
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3584147948
Short name T266
Test name
Test status
Simulation time 459275197 ps
CPU time 1.25 seconds
Started Jul 04 05:35:51 PM PDT 24
Finished Jul 04 05:35:53 PM PDT 24
Peak memory 196672 kb
Host smart-1f2ed081-c520-4db4-9843-67d5029ba872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584147948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3584147948
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2440806825
Short name T268
Test name
Test status
Simulation time 32615032306 ps
CPU time 48.45 seconds
Started Jul 04 05:35:56 PM PDT 24
Finished Jul 04 05:36:45 PM PDT 24
Peak memory 191884 kb
Host smart-c1ccde64-6058-4c0d-ba05-7e241ac0f1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440806825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2440806825
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4034211020
Short name T237
Test name
Test status
Simulation time 374431949 ps
CPU time 1.12 seconds
Started Jul 04 05:35:56 PM PDT 24
Finished Jul 04 05:35:58 PM PDT 24
Peak memory 196628 kb
Host smart-a166a3be-286f-4ea7-927d-6c988834a92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034211020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4034211020
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2704849023
Short name T4
Test name
Test status
Simulation time 24457733726 ps
CPU time 9.77 seconds
Started Jul 04 05:35:56 PM PDT 24
Finished Jul 04 05:36:06 PM PDT 24
Peak memory 196892 kb
Host smart-92ffa520-d485-4e6c-9a9a-c72026efb6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704849023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2704849023
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1623148891
Short name T228
Test name
Test status
Simulation time 500672216 ps
CPU time 1.35 seconds
Started Jul 04 05:36:02 PM PDT 24
Finished Jul 04 05:36:04 PM PDT 24
Peak memory 191716 kb
Host smart-fa8ab8c6-b2fb-44f3-bc76-70d09a65d2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623148891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1623148891
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1414415372
Short name T78
Test name
Test status
Simulation time 397884658 ps
CPU time 0.71 seconds
Started Jul 04 05:35:59 PM PDT 24
Finished Jul 04 05:36:01 PM PDT 24
Peak memory 196668 kb
Host smart-046c6c94-3abd-403c-aebb-d918ecb61c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414415372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1414415372
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4151193407
Short name T261
Test name
Test status
Simulation time 9979390787 ps
CPU time 16.34 seconds
Started Jul 04 05:35:57 PM PDT 24
Finished Jul 04 05:36:13 PM PDT 24
Peak memory 196912 kb
Host smart-3ff45a47-0451-4bc2-af61-750b87566928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151193407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4151193407
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2911596151
Short name T211
Test name
Test status
Simulation time 412556233 ps
CPU time 1.11 seconds
Started Jul 04 05:35:56 PM PDT 24
Finished Jul 04 05:35:57 PM PDT 24
Peak memory 196620 kb
Host smart-8bbfcdb4-1202-4226-9941-646f9baef81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911596151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2911596151
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.809138599
Short name T256
Test name
Test status
Simulation time 50241634663 ps
CPU time 18.26 seconds
Started Jul 04 05:35:00 PM PDT 24
Finished Jul 04 05:35:18 PM PDT 24
Peak memory 191916 kb
Host smart-fb6c66a9-ba84-4a48-804c-26a9a1c6acf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809138599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.809138599
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3150552543
Short name T272
Test name
Test status
Simulation time 530606597 ps
CPU time 1.31 seconds
Started Jul 04 05:35:01 PM PDT 24
Finished Jul 04 05:35:03 PM PDT 24
Peak memory 191848 kb
Host smart-15cb2ff6-7597-4e92-bd72-2ece7952ab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150552543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3150552543
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2500515344
Short name T208
Test name
Test status
Simulation time 38175112968 ps
CPU time 9.63 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:19 PM PDT 24
Peak memory 191920 kb
Host smart-09e2ef33-6049-4687-be44-a9a7c924e0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500515344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2500515344
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.186486383
Short name T229
Test name
Test status
Simulation time 583898119 ps
CPU time 1.57 seconds
Started Jul 04 05:35:03 PM PDT 24
Finished Jul 04 05:35:05 PM PDT 24
Peak memory 196648 kb
Host smart-847ee24a-26ce-4e78-bf4b-92e2cfd78bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186486383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.186486383
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1716050736
Short name T270
Test name
Test status
Simulation time 19395746519 ps
CPU time 8.17 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:18 PM PDT 24
Peak memory 196900 kb
Host smart-4b88ca1d-6487-4768-aa79-2cbcebd0b1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716050736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1716050736
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1619649611
Short name T252
Test name
Test status
Simulation time 379794511 ps
CPU time 0.76 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:10 PM PDT 24
Peak memory 196676 kb
Host smart-d0c4467b-bc93-4039-a50d-30cd5cb0dec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619649611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1619649611
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3843488547
Short name T255
Test name
Test status
Simulation time 37638682033 ps
CPU time 51.04 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:36:00 PM PDT 24
Peak memory 191840 kb
Host smart-58c9a950-dc94-453b-a84e-f40fab5c0728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843488547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3843488547
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2206058658
Short name T246
Test name
Test status
Simulation time 605942476 ps
CPU time 0.72 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:10 PM PDT 24
Peak memory 191864 kb
Host smart-41d9b78c-cd67-4580-9a90-444d780ccdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206058658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2206058658
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.530955339
Short name T251
Test name
Test status
Simulation time 36586826089 ps
CPU time 13.32 seconds
Started Jul 04 05:35:09 PM PDT 24
Finished Jul 04 05:35:23 PM PDT 24
Peak memory 191888 kb
Host smart-b7626571-46a3-409f-a37f-01a0b8324162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530955339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.530955339
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2451241342
Short name T204
Test name
Test status
Simulation time 387714718 ps
CPU time 0.7 seconds
Started Jul 04 05:35:11 PM PDT 24
Finished Jul 04 05:35:12 PM PDT 24
Peak memory 196668 kb
Host smart-92f61129-2fa3-4ceb-89b8-d3647473e614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451241342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2451241342
Directory /workspace/9.aon_timer_smoke/latest
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