Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.27	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	3	170	98.27

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	39291	1		T1	202		T2	153		T3	185
bark[1]	208	1		T2	30		T97	21		T159	5
bark[2]	409	1		T167	73		T100	21		T82	45
bark[3]	367	1		T3	26		T11	14		T90	21
bark[4]	300	1		T45	21		T97	21		T163	26
bark[5]	892	1		T38	71		T39	26		T23	21
bark[6]	829	1		T6	40		T15	251		T185	42
bark[7]	572	1		T92	197		T122	14		T150	81
bark[8]	385	1		T13	21		T50	14		T106	26
bark[9]	611	1		T7	31		T13	86		T135	21
bark[10]	381	1		T15	21		T42	26		T128	21
bark[11]	574	1		T3	21		T6	21		T112	14
bark[12]	635	1		T2	31		T7	47		T45	31
bark[13]	610	1		T7	21		T52	14		T29	26
bark[14]	786	1		T45	21		T39	5		T21	14
bark[15]	385	1		T145	21		T97	21		T146	14
bark[16]	889	1		T6	21		T51	26		T90	26
bark[17]	307	1		T106	21		T42	7		T183	14
bark[18]	989	1		T3	62		T11	51		T13	221
bark[19]	656	1		T2	21		T15	7		T128	35
bark[20]	978	1		T13	26		T159	111		T143	21
bark[21]	717	1		T1	30		T6	21		T133	14
bark[22]	859	1		T2	21		T30	14		T23	54
bark[23]	303	1		T6	52		T115	62		T188	14
bark[24]	318	1		T23	30		T158	21		T136	21
bark[25]	966	1		T39	21		T90	21		T43	192
bark[26]	467	1		T92	21		T145	48		T147	14
bark[27]	433	1		T89	14		T132	21		T107	21
bark[28]	889	1		T3	21		T45	40		T15	21
bark[29]	758	1		T29	21		T42	21		T150	26
bark[30]	839	1		T10	21		T88	14		T41	221
bark[31]	368	1		T10	52		T51	21		T25	14
bark_0	5065	1		T1	25		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	38853	1		T1	201		T2	152		T3	184
bite[1]	508	1		T115	59		T135	21		T162	65
bite[2]	736	1		T3	26		T88	13		T15	123
bite[3]	403	1		T1	30		T7	21		T106	21
bite[4]	432	1		T13	26		T112	13		T128	21
bite[5]	558	1		T7	31		T15	21		T114	13
bite[6]	712	1		T3	21		T13	85		T15	6
bite[7]	409	1		T38	70		T51	26		T42	21
bite[8]	814	1		T39	4		T29	26		T42	13
bite[9]	881	1		T51	21		T42	215		T128	35
bite[10]	820	1		T2	31		T39	21		T42	25
bite[11]	472	1		T2	30		T50	13		T133	13
bite[12]	479	1		T2	21		T6	51		T10	52
bite[13]	224	1		T45	31		T89	13		T42	6
bite[14]	980	1		T2	21		T90	21		T41	264
bite[15]	910	1		T45	21		T109	21		T93	40
bite[16]	1045	1		T30	13		T45	40		T41	220
bite[17]	250	1		T6	21		T15	21		T29	21
bite[18]	938	1		T6	21		T11	13		T13	220
bite[19]	206	1		T3	62		T106	26		T21	13
bite[20]	932	1		T3	21		T52	13		T179	13
bite[21]	470	1		T6	21		T13	21		T185	42
bite[22]	615	1		T10	21		T106	21		T43	136
bite[23]	673	1		T15	250		T39	25		T172	13
bite[24]	792	1		T145	21		T135	461		T113	21
bite[25]	343	1		T6	40		T25	13		T29	21
bite[26]	766	1		T7	47		T42	31		T159	21
bite[27]	263	1		T97	43		T189	21		T166	65
bite[28]	418	1		T39	225		T92	6		T135	21
bite[29]	731	1		T163	73		T111	13		T107	21
bite[30]	479	1		T113	21		T137	21		T165	66
bite[31]	237	1		T6	21		T11	51		T90	21
bite_0	5687	1		T1	26		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	51269	1		T1	229		T2	194		T3	303
auto[1]	11767	1		T1	28		T2	69		T3	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	28	1		T166	28		-	-		-	-
prescale[0]	1323	1		T15	38		T39	2		T43	129
prescale[1]	1313	1		T6	19		T15	90		T90	19
prescale[2]	1241	1		T6	88		T11	23		T15	82
prescale[3]	927	1		T6	38		T7	36		T38	36
prescale[4]	993	1		T6	2		T10	14		T11	38
prescale[5]	1280	1		T2	9		T6	78		T45	19
prescale[6]	1212	1		T3	36		T10	24		T13	2
prescale[7]	1503	1		T6	156		T13	28		T15	2
prescale[8]	1679	1		T3	62		T6	136		T45	9
prescale[9]	655	1		T23	37		T43	45		T173	2
prescale[10]	1160	1		T2	23		T38	36		T39	19
prescale[11]	833	1		T3	36		T10	19		T15	109
prescale[12]	1518	1		T1	69		T6	19		T38	2
prescale[13]	645	1		T3	23		T15	2		T38	40
prescale[14]	1209	1		T6	103		T48	9		T40	2
prescale[15]	1196	1		T6	21		T15	19		T38	24
prescale[16]	1009	1		T7	33		T15	19		T23	2
prescale[17]	1286	1		T6	28		T15	9		T23	47
prescale[18]	802	1		T15	2		T185	19		T23	40
prescale[19]	639	1		T13	9		T40	2		T90	23
prescale[20]	1063	1		T45	23		T15	77		T23	85
prescale[21]	1605	1		T3	57		T6	80		T10	36
prescale[22]	929	1		T11	19		T15	57		T39	19
prescale[23]	1501	1		T45	40		T15	21		T40	2
prescale[24]	847	1		T2	53		T3	24		T46	9
prescale[25]	744	1		T6	38		T45	54		T90	9
prescale[26]	1096	1		T11	66		T38	123		T40	2
prescale[27]	567	1		T6	28		T38	2		T40	4
prescale[28]	1286	1		T13	25		T15	19		T38	2
prescale[29]	725	1		T6	40		T13	53		T199	9
prescale[30]	1027	1		T23	21		T43	19		T92	2
prescale[31]	1245	1		T6	120		T7	19		T10	32
prescale_0	27978	1		T1	188		T2	178		T3	84

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	47984	1		T1	173		T2	69		T3	222
auto[1]	15052	1		T1	84		T2	194		T3	100

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	63036	1		T1	257		T2	263		T3	322

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	37013	1		T1	234		T2	155		T3	228
wkup[1]	376	1		T2	21		T10	21		T106	15
wkup[2]	230	1		T13	30		T112	15		T106	21
wkup[3]	314	1		T6	21		T39	21		T42	26
wkup[4]	513	1		T13	8		T39	8		T42	21
wkup[5]	299	1		T51	21		T90	21		T41	35
wkup[6]	248	1		T6	21		T41	21		T42	42
wkup[7]	248	1		T38	21		T29	26		T183	15
wkup[8]	433	1		T6	29		T30	15		T39	30
wkup[9]	158	1		T52	15		T42	21		T92	8
wkup[10]	226	1		T128	21		T132	26		T76	21
wkup[11]	366	1		T135	30		T150	21		T167	21
wkup[12]	266	1		T45	21		T173	21		T167	20
wkup[13]	230	1		T135	21		T166	51		T129	30
wkup[14]	296	1		T13	26		T39	21		T23	26
wkup[15]	351	1		T21	15		T76	21		T150	21
wkup[16]	390	1		T2	21		T3	26		T6	21
wkup[17]	392	1		T15	21		T90	21		T29	21
wkup[18]	311	1		T42	21		T150	21		T162	51
wkup[19]	269	1		T88	15		T23	21		T92	21
wkup[20]	426	1		T11	30		T41	8		T92	21
wkup[21]	384	1		T15	47		T185	21		T42	26
wkup[22]	458	1		T15	21		T128	21		T43	35
wkup[23]	592	1		T45	31		T89	15		T15	21
wkup[24]	414	1		T11	30		T185	26		T23	21
wkup[25]	499	1		T42	21		T92	26		T159	21
wkup[26]	279	1		T43	21		T92	21		T150	21
wkup[27]	399	1		T3	21		T107	21		T109	21
wkup[28]	332	1		T3	21		T15	21		T38	21
wkup[29]	363	1		T6	21		T13	21		T45	21
wkup[30]	308	1		T6	21		T13	21		T45	21
wkup[31]	143	1		T23	21		T82	8		T136	21
wkup[32]	412	1		T114	15		T159	30		T166	21
wkup[33]	273	1		T7	26		T106	21		T170	15
wkup[34]	343	1		T6	21		T7	21		T11	15
wkup[35]	356	1		T106	26		T23	21		T92	30
wkup[36]	206	1		T6	42		T10	21		T41	21
wkup[37]	308	1		T15	30		T38	39		T39	21
wkup[38]	273	1		T3	21		T39	6		T150	26
wkup[39]	424	1		T6	21		T15	8		T39	21
wkup[40]	408	1		T6	30		T135	8		T150	21
wkup[41]	455	1		T15	21		T23	21		T42	31
wkup[42]	223	1		T7	21		T13	21		T15	21
wkup[43]	319	1		T145	30		T113	21		T82	30
wkup[44]	393	1		T90	26		T132	30		T135	21
wkup[45]	422	1		T15	21		T41	39		T43	21
wkup[46]	489	1		T2	31		T6	26		T39	21
wkup[47]	366	1		T6	21		T7	31		T11	21
wkup[48]	237	1		T106	26		T42	21		T135	8
wkup[49]	302	1		T6	21		T10	21		T45	21
wkup[50]	403	1		T6	21		T39	21		T23	21
wkup[51]	371	1		T6	21		T15	21		T23	21
wkup[52]	373	1		T6	42		T23	30		T41	39
wkup[53]	370	1		T23	21		T41	21		T115	39
wkup[54]	469	1		T13	21		T15	42		T51	26
wkup[55]	209	1		T15	21		T113	21		T84	30
wkup[56]	364	1		T13	21		T38	21		T42	21
wkup[57]	422	1		T2	30		T42	8		T92	21
wkup[58]	316	1		T42	21		T135	21		T173	21
wkup[59]	404	1		T15	21		T106	21		T29	21
wkup[60]	480	1		T39	21		T50	15		T23	36
wkup[61]	452	1		T23	21		T29	21		T43	21
wkup[62]	320	1		T6	40		T133	15		T29	15
wkup[63]	353	1		T128	35		T43	21		T142	15
wkup_0	3995	1		T1	23		T2	5		T3	5