Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
3822 |
1 |
|
T1 |
24 |
|
T2 |
29 |
|
T3 |
28 |
all_pins[1] |
3822 |
1 |
|
T1 |
24 |
|
T2 |
29 |
|
T3 |
28 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
5311 |
1 |
|
T1 |
32 |
|
T2 |
38 |
|
T3 |
41 |
values[0x1] |
2333 |
1 |
|
T1 |
16 |
|
T2 |
20 |
|
T3 |
15 |
transitions[0x0=>0x1] |
1841 |
1 |
|
T1 |
13 |
|
T2 |
16 |
|
T3 |
14 |
transitions[0x1=>0x0] |
1785 |
1 |
|
T1 |
12 |
|
T2 |
16 |
|
T3 |
14 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
3092 |
1 |
|
T1 |
18 |
|
T2 |
21 |
|
T3 |
24 |
all_pins[0] |
values[0x1] |
730 |
1 |
|
T1 |
6 |
|
T2 |
8 |
|
T3 |
4 |
all_pins[0] |
transitions[0x0=>0x1] |
399 |
1 |
|
T1 |
4 |
|
T2 |
5 |
|
T3 |
3 |
all_pins[0] |
transitions[0x1=>0x0] |
1272 |
1 |
|
T1 |
8 |
|
T2 |
9 |
|
T3 |
10 |
all_pins[1] |
values[0x0] |
2219 |
1 |
|
T1 |
14 |
|
T2 |
17 |
|
T3 |
17 |
all_pins[1] |
values[0x1] |
1603 |
1 |
|
T1 |
10 |
|
T2 |
12 |
|
T3 |
11 |
all_pins[1] |
transitions[0x0=>0x1] |
1442 |
1 |
|
T1 |
9 |
|
T2 |
11 |
|
T3 |
11 |
all_pins[1] |
transitions[0x1=>0x0] |
513 |
1 |
|
T1 |
4 |
|
T2 |
7 |
|
T3 |
4 |