Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.24 99.33 93.67 100.00 98.40 99.51 56.53


Total test records in report: 425
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T280 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.553765811 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:29 PM PDT 24 586808681 ps
T281 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3630243060 Jul 05 05:16:05 PM PDT 24 Jul 05 05:16:06 PM PDT 24 569430294 ps
T37 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3696640582 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:17 PM PDT 24 6297767963 ps
T31 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1653581962 Jul 05 05:16:06 PM PDT 24 Jul 05 05:16:09 PM PDT 24 1441260584 ps
T282 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.261167118 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:17 PM PDT 24 1089947150 ps
T283 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3946837302 Jul 05 05:16:27 PM PDT 24 Jul 05 05:16:29 PM PDT 24 290362716 ps
T284 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3296332791 Jul 05 05:15:59 PM PDT 24 Jul 05 05:16:01 PM PDT 24 464968933 ps
T285 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.882753937 Jul 05 05:16:23 PM PDT 24 Jul 05 05:16:26 PM PDT 24 508363528 ps
T32 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.162564650 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:18 PM PDT 24 2004003268 ps
T286 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2826181362 Jul 05 05:16:18 PM PDT 24 Jul 05 05:16:20 PM PDT 24 489576956 ps
T287 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1779334236 Jul 05 05:16:39 PM PDT 24 Jul 05 05:16:41 PM PDT 24 576275954 ps
T33 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.76551458 Jul 05 05:16:17 PM PDT 24 Jul 05 05:16:20 PM PDT 24 480116796 ps
T34 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.603410018 Jul 05 05:16:15 PM PDT 24 Jul 05 05:16:20 PM PDT 24 8626251571 ps
T288 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2634942870 Jul 05 05:16:24 PM PDT 24 Jul 05 05:16:27 PM PDT 24 379521863 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1341150993 Jul 05 05:16:04 PM PDT 24 Jul 05 05:16:06 PM PDT 24 910001047 ps
T289 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4008018788 Jul 05 05:16:15 PM PDT 24 Jul 05 05:16:19 PM PDT 24 473602711 ps
T290 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2891132508 Jul 05 05:16:25 PM PDT 24 Jul 05 05:16:28 PM PDT 24 673609198 ps
T35 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1706779907 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:25 PM PDT 24 8599699267 ps
T291 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.933638092 Jul 05 05:16:38 PM PDT 24 Jul 05 05:16:39 PM PDT 24 382370430 ps
T69 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2435131276 Jul 05 05:16:15 PM PDT 24 Jul 05 05:16:20 PM PDT 24 2491340684 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.282781790 Jul 05 05:16:10 PM PDT 24 Jul 05 05:16:11 PM PDT 24 386792921 ps
T293 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1496843560 Jul 05 05:16:16 PM PDT 24 Jul 05 05:16:19 PM PDT 24 475291211 ps
T36 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4284465615 Jul 05 05:16:21 PM PDT 24 Jul 05 05:16:26 PM PDT 24 4281278751 ps
T294 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4272062536 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:25 PM PDT 24 321394992 ps
T70 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4254102844 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:28 PM PDT 24 375016458 ps
T295 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.697822050 Jul 05 05:16:34 PM PDT 24 Jul 05 05:16:36 PM PDT 24 389297539 ps
T296 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.627005594 Jul 05 05:16:12 PM PDT 24 Jul 05 05:16:15 PM PDT 24 539394044 ps
T297 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2975141787 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:23 PM PDT 24 379599337 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4198841061 Jul 05 05:16:21 PM PDT 24 Jul 05 05:16:24 PM PDT 24 394088940 ps
T299 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2941644949 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:21 PM PDT 24 4644291087 ps
T71 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1317499053 Jul 05 05:16:38 PM PDT 24 Jul 05 05:16:40 PM PDT 24 1462802381 ps
T300 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2441995848 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:35 PM PDT 24 8617899841 ps
T301 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3563568152 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:22 PM PDT 24 382156296 ps
T302 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.729303501 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:23 PM PDT 24 379550668 ps
T303 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2714395189 Jul 05 05:16:32 PM PDT 24 Jul 05 05:16:34 PM PDT 24 416370259 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2506910431 Jul 05 05:16:07 PM PDT 24 Jul 05 05:16:08 PM PDT 24 634297212 ps
T72 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3372598963 Jul 05 05:16:24 PM PDT 24 Jul 05 05:16:29 PM PDT 24 3143470182 ps
T305 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1540999303 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:23 PM PDT 24 528913415 ps
T306 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2511808465 Jul 05 05:16:07 PM PDT 24 Jul 05 05:16:09 PM PDT 24 400133665 ps
T73 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1559752889 Jul 05 05:16:12 PM PDT 24 Jul 05 05:16:15 PM PDT 24 489540376 ps
T307 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3858561912 Jul 05 05:16:08 PM PDT 24 Jul 05 05:16:09 PM PDT 24 288818815 ps
T74 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1559046465 Jul 05 05:16:14 PM PDT 24 Jul 05 05:16:17 PM PDT 24 1259582585 ps
T308 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.230208253 Jul 05 05:16:36 PM PDT 24 Jul 05 05:16:38 PM PDT 24 321737224 ps
T309 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.28076252 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:16 PM PDT 24 485266132 ps
T310 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1231910814 Jul 05 05:16:28 PM PDT 24 Jul 05 05:16:31 PM PDT 24 400588869 ps
T311 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3861964484 Jul 05 05:16:01 PM PDT 24 Jul 05 05:16:02 PM PDT 24 333535652 ps
T312 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2750846865 Jul 05 05:16:25 PM PDT 24 Jul 05 05:16:29 PM PDT 24 373965656 ps
T313 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3635427345 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:15 PM PDT 24 479520790 ps
T314 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.583715190 Jul 05 05:16:21 PM PDT 24 Jul 05 05:16:26 PM PDT 24 861728138 ps
T315 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2042145627 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:17 PM PDT 24 377044070 ps
T316 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2536766196 Jul 05 05:16:28 PM PDT 24 Jul 05 05:16:31 PM PDT 24 387619902 ps
T317 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2428226550 Jul 05 05:16:06 PM PDT 24 Jul 05 05:16:08 PM PDT 24 459624295 ps
T75 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.139691364 Jul 05 05:16:17 PM PDT 24 Jul 05 05:16:19 PM PDT 24 1462735921 ps
T318 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4294474792 Jul 05 05:16:24 PM PDT 24 Jul 05 05:16:28 PM PDT 24 453810838 ps
T319 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4213780061 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:26 PM PDT 24 619188605 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1821439897 Jul 05 05:16:08 PM PDT 24 Jul 05 05:16:11 PM PDT 24 579837855 ps
T59 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1704167850 Jul 05 05:16:15 PM PDT 24 Jul 05 05:16:19 PM PDT 24 479490869 ps
T60 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2906614291 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:25 PM PDT 24 377846139 ps
T320 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3156089870 Jul 05 05:16:34 PM PDT 24 Jul 05 05:16:37 PM PDT 24 522619929 ps
T321 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1288507456 Jul 05 05:16:31 PM PDT 24 Jul 05 05:16:33 PM PDT 24 349849817 ps
T322 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1776280557 Jul 05 05:16:27 PM PDT 24 Jul 05 05:16:29 PM PDT 24 424818467 ps
T323 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2696087234 Jul 05 05:16:17 PM PDT 24 Jul 05 05:16:20 PM PDT 24 350370394 ps
T324 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2460927230 Jul 05 05:16:12 PM PDT 24 Jul 05 05:16:20 PM PDT 24 8298914148 ps
T325 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.769388763 Jul 05 05:16:33 PM PDT 24 Jul 05 05:16:35 PM PDT 24 299790266 ps
T326 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3897309443 Jul 05 05:16:14 PM PDT 24 Jul 05 05:16:17 PM PDT 24 409164811 ps
T327 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3252609451 Jul 05 05:16:21 PM PDT 24 Jul 05 05:16:30 PM PDT 24 4403394028 ps
T328 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1818225083 Jul 05 05:16:44 PM PDT 24 Jul 05 05:16:46 PM PDT 24 396191801 ps
T329 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4013405304 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:25 PM PDT 24 2693437185 ps
T330 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2550420628 Jul 05 05:16:15 PM PDT 24 Jul 05 05:16:20 PM PDT 24 8874186947 ps
T61 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1459097465 Jul 05 05:16:08 PM PDT 24 Jul 05 05:16:09 PM PDT 24 315583169 ps
T331 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.806172063 Jul 05 05:16:19 PM PDT 24 Jul 05 05:16:21 PM PDT 24 439384232 ps
T332 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3108266961 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:24 PM PDT 24 2219195813 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3694008555 Jul 05 05:16:02 PM PDT 24 Jul 05 05:16:04 PM PDT 24 1411308107 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1894836905 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:26 PM PDT 24 2328314029 ps
T65 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3597363275 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:16 PM PDT 24 312233667 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2932936322 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:19 PM PDT 24 12241682435 ps
T334 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.673009366 Jul 05 05:16:23 PM PDT 24 Jul 05 05:16:26 PM PDT 24 328346142 ps
T335 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1570529575 Jul 05 05:16:19 PM PDT 24 Jul 05 05:16:23 PM PDT 24 9062654792 ps
T336 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3376886354 Jul 05 05:16:25 PM PDT 24 Jul 05 05:16:28 PM PDT 24 496611664 ps
T337 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2045414372 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:29 PM PDT 24 441565030 ps
T338 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2499406971 Jul 05 05:16:05 PM PDT 24 Jul 05 05:16:06 PM PDT 24 509353669 ps
T339 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2356337553 Jul 05 05:16:18 PM PDT 24 Jul 05 05:16:20 PM PDT 24 1537346937 ps
T340 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1453947065 Jul 05 05:16:12 PM PDT 24 Jul 05 05:16:14 PM PDT 24 428776957 ps
T341 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2896554112 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:33 PM PDT 24 9234695165 ps
T342 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4192291803 Jul 05 05:16:23 PM PDT 24 Jul 05 05:16:26 PM PDT 24 524428442 ps
T343 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2020749368 Jul 05 05:16:15 PM PDT 24 Jul 05 05:16:17 PM PDT 24 422059118 ps
T344 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2950226585 Jul 05 05:16:18 PM PDT 24 Jul 05 05:16:20 PM PDT 24 274396312 ps
T345 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3015097811 Jul 05 05:16:23 PM PDT 24 Jul 05 05:16:26 PM PDT 24 604901213 ps
T346 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1660070971 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:26 PM PDT 24 490130924 ps
T347 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1252292417 Jul 05 05:16:39 PM PDT 24 Jul 05 05:16:41 PM PDT 24 429028111 ps
T348 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3198050218 Jul 05 05:16:09 PM PDT 24 Jul 05 05:16:12 PM PDT 24 439249709 ps
T349 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.389851143 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:18 PM PDT 24 4733849269 ps
T350 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3629421570 Jul 05 05:16:19 PM PDT 24 Jul 05 05:16:23 PM PDT 24 897289877 ps
T351 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2726283930 Jul 05 05:16:16 PM PDT 24 Jul 05 05:16:19 PM PDT 24 350595495 ps
T352 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2558867042 Jul 05 05:16:36 PM PDT 24 Jul 05 05:16:38 PM PDT 24 514527731 ps
T353 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.135487981 Jul 05 05:16:29 PM PDT 24 Jul 05 05:16:31 PM PDT 24 311095101 ps
T354 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2279612404 Jul 05 05:16:06 PM PDT 24 Jul 05 05:16:07 PM PDT 24 413075373 ps
T355 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2500647035 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:23 PM PDT 24 507891723 ps
T356 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4107500502 Jul 05 05:16:16 PM PDT 24 Jul 05 05:16:19 PM PDT 24 827949377 ps
T357 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1757440134 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:29 PM PDT 24 404596775 ps
T358 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2447015440 Jul 05 05:16:27 PM PDT 24 Jul 05 05:16:30 PM PDT 24 430617598 ps
T359 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3097323610 Jul 05 05:16:14 PM PDT 24 Jul 05 05:16:17 PM PDT 24 851156679 ps
T360 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3143783840 Jul 05 05:16:14 PM PDT 24 Jul 05 05:16:17 PM PDT 24 416486457 ps
T361 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.959384925 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:26 PM PDT 24 396476293 ps
T362 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4268049326 Jul 05 05:16:21 PM PDT 24 Jul 05 05:16:24 PM PDT 24 325098240 ps
T363 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1751262836 Jul 05 05:16:23 PM PDT 24 Jul 05 05:16:26 PM PDT 24 406394798 ps
T364 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2910660896 Jul 05 05:16:21 PM PDT 24 Jul 05 05:16:24 PM PDT 24 277599154 ps
T365 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3869402818 Jul 05 05:16:09 PM PDT 24 Jul 05 05:16:11 PM PDT 24 354304070 ps
T366 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3113534320 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:29 PM PDT 24 298232023 ps
T367 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1907922276 Jul 05 05:16:27 PM PDT 24 Jul 05 05:16:30 PM PDT 24 264378672 ps
T368 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1776040986 Jul 05 05:16:01 PM PDT 24 Jul 05 05:16:03 PM PDT 24 520485370 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1955469627 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:16 PM PDT 24 612164296 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.696668811 Jul 05 05:16:24 PM PDT 24 Jul 05 05:16:28 PM PDT 24 1139029159 ps
T370 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4076904009 Jul 05 05:16:10 PM PDT 24 Jul 05 05:16:13 PM PDT 24 1205340840 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.18420234 Jul 05 05:16:00 PM PDT 24 Jul 05 05:16:01 PM PDT 24 407671126 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3288453626 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:25 PM PDT 24 567314401 ps
T373 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3221244853 Jul 05 05:16:19 PM PDT 24 Jul 05 05:16:21 PM PDT 24 522162665 ps
T374 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3416741141 Jul 05 05:16:14 PM PDT 24 Jul 05 05:16:20 PM PDT 24 4100443561 ps
T375 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2687157472 Jul 05 05:16:04 PM PDT 24 Jul 05 05:16:06 PM PDT 24 944994799 ps
T376 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.27378853 Jul 05 05:16:28 PM PDT 24 Jul 05 05:16:30 PM PDT 24 323126094 ps
T377 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2032984466 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:29 PM PDT 24 505257031 ps
T378 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1541140059 Jul 05 05:16:11 PM PDT 24 Jul 05 05:16:13 PM PDT 24 589321282 ps
T196 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1201605898 Jul 05 05:16:01 PM PDT 24 Jul 05 05:16:09 PM PDT 24 8616178736 ps
T379 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3078675988 Jul 05 05:16:17 PM PDT 24 Jul 05 05:16:20 PM PDT 24 334581604 ps
T380 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.63305163 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:29 PM PDT 24 377815813 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1712655624 Jul 05 05:16:03 PM PDT 24 Jul 05 05:16:09 PM PDT 24 5647107805 ps
T381 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3257670610 Jul 05 05:16:12 PM PDT 24 Jul 05 05:16:14 PM PDT 24 423434660 ps
T382 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1692006956 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:29 PM PDT 24 336664889 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2703214394 Jul 05 05:16:14 PM PDT 24 Jul 05 05:16:17 PM PDT 24 507744814 ps
T384 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2342730110 Jul 05 05:16:17 PM PDT 24 Jul 05 05:16:21 PM PDT 24 425521355 ps
T385 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3288329062 Jul 05 05:16:34 PM PDT 24 Jul 05 05:16:36 PM PDT 24 557945022 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4276248703 Jul 05 05:16:34 PM PDT 24 Jul 05 05:16:36 PM PDT 24 523461250 ps
T386 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2165248103 Jul 05 05:16:11 PM PDT 24 Jul 05 05:16:13 PM PDT 24 264689032 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1348937389 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:17 PM PDT 24 422857825 ps
T388 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1738822746 Jul 05 05:16:18 PM PDT 24 Jul 05 05:16:22 PM PDT 24 566931725 ps
T389 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1692885463 Jul 05 05:16:21 PM PDT 24 Jul 05 05:16:27 PM PDT 24 8546985247 ps
T390 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.215047548 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:23 PM PDT 24 4101969294 ps
T391 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3880003631 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:23 PM PDT 24 318948861 ps
T197 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1781637227 Jul 05 05:16:05 PM PDT 24 Jul 05 05:16:08 PM PDT 24 8907944351 ps
T392 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3050159704 Jul 05 05:16:18 PM PDT 24 Jul 05 05:16:22 PM PDT 24 1834655593 ps
T393 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.954807024 Jul 05 05:16:25 PM PDT 24 Jul 05 05:16:28 PM PDT 24 523938982 ps
T394 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3648109804 Jul 05 05:16:19 PM PDT 24 Jul 05 05:16:23 PM PDT 24 2000874154 ps
T395 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2326798165 Jul 05 05:16:21 PM PDT 24 Jul 05 05:16:25 PM PDT 24 1027257127 ps
T396 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3845228053 Jul 05 05:16:36 PM PDT 24 Jul 05 05:16:38 PM PDT 24 444648585 ps
T397 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.197277282 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:32 PM PDT 24 8643253359 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4211087144 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:32 PM PDT 24 4606098636 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3060518658 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:32 PM PDT 24 7084118390 ps
T400 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2373682235 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:26 PM PDT 24 598750269 ps
T401 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2868610567 Jul 05 05:16:14 PM PDT 24 Jul 05 05:16:17 PM PDT 24 381086690 ps
T402 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.869315736 Jul 05 05:16:11 PM PDT 24 Jul 05 05:16:14 PM PDT 24 987518551 ps
T403 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3567425425 Jul 05 05:16:35 PM PDT 24 Jul 05 05:16:38 PM PDT 24 475767139 ps
T198 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.173729503 Jul 05 05:16:22 PM PDT 24 Jul 05 05:16:28 PM PDT 24 3936754766 ps
T404 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2625439532 Jul 05 05:16:06 PM PDT 24 Jul 05 05:16:09 PM PDT 24 1289940986 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2924935870 Jul 05 05:16:34 PM PDT 24 Jul 05 05:16:37 PM PDT 24 607372890 ps
T406 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2063108487 Jul 05 05:16:14 PM PDT 24 Jul 05 05:16:17 PM PDT 24 560949246 ps
T407 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3253629091 Jul 05 05:16:29 PM PDT 24 Jul 05 05:16:31 PM PDT 24 404183494 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2421310940 Jul 05 05:16:03 PM PDT 24 Jul 05 05:16:05 PM PDT 24 698754685 ps
T409 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.18900140 Jul 05 05:16:13 PM PDT 24 Jul 05 05:16:16 PM PDT 24 1053254664 ps
T410 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1288047075 Jul 05 05:16:04 PM PDT 24 Jul 05 05:16:07 PM PDT 24 436589750 ps
T411 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1913624774 Jul 05 05:16:17 PM PDT 24 Jul 05 05:16:19 PM PDT 24 556358612 ps
T412 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1681017974 Jul 05 05:16:26 PM PDT 24 Jul 05 05:16:29 PM PDT 24 510120561 ps
T413 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2073934560 Jul 05 05:16:11 PM PDT 24 Jul 05 05:16:14 PM PDT 24 429284723 ps
T414 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2318144013 Jul 05 05:16:30 PM PDT 24 Jul 05 05:16:32 PM PDT 24 401764642 ps
T415 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2406019015 Jul 05 05:16:04 PM PDT 24 Jul 05 05:16:09 PM PDT 24 7149317470 ps
T416 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2642942113 Jul 05 05:16:20 PM PDT 24 Jul 05 05:16:23 PM PDT 24 429299403 ps
T417 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.212867129 Jul 05 05:16:27 PM PDT 24 Jul 05 05:16:29 PM PDT 24 505677816 ps
T418 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.761498712 Jul 05 05:16:11 PM PDT 24 Jul 05 05:16:15 PM PDT 24 2186293969 ps
T419 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3373419684 Jul 05 05:16:25 PM PDT 24 Jul 05 05:16:27 PM PDT 24 297425856 ps
T420 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.649788502 Jul 05 05:16:08 PM PDT 24 Jul 05 05:16:16 PM PDT 24 4132907105 ps
T64 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.545012407 Jul 05 05:16:10 PM PDT 24 Jul 05 05:16:12 PM PDT 24 529103859 ps
T421 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2341032267 Jul 05 05:16:16 PM PDT 24 Jul 05 05:16:19 PM PDT 24 528470994 ps
T422 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.271930658 Jul 05 05:16:34 PM PDT 24 Jul 05 05:16:37 PM PDT 24 2274471671 ps
T423 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.727744395 Jul 05 05:16:07 PM PDT 24 Jul 05 05:16:08 PM PDT 24 624637675 ps
T424 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2235069613 Jul 05 05:16:03 PM PDT 24 Jul 05 05:16:05 PM PDT 24 465996777 ps
T425 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.711882685 Jul 05 05:16:28 PM PDT 24 Jul 05 05:16:31 PM PDT 24 540571682 ps

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1285090814
Short name T6
Test name
Test status
Simulation time 217847934819 ps
CPU time 950.78 seconds
Started Jul 05 04:46:35 PM PDT 24
Finished Jul 05 05:02:26 PM PDT 24
Peak memory 209956 kb
Host smart-79b3bb31-7bf2-4548-9c16-df03009a9fd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285090814 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1285090814
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1757057762
Short name T16
Test name
Test status
Simulation time 8231484758 ps
CPU time 2.59 seconds
Started Jul 05 04:44:53 PM PDT 24
Finished Jul 05 04:44:56 PM PDT 24
Peak memory 215756 kb
Host smart-2bc26c67-8512-416d-877f-9f1b115dbdb8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757057762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1757057762
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3696016383
Short name T42
Test name
Test status
Simulation time 204649976339 ps
CPU time 219.91 seconds
Started Jul 05 04:45:45 PM PDT 24
Finished Jul 05 04:49:26 PM PDT 24
Peak memory 208864 kb
Host smart-8eaf071d-74df-457c-9477-31a06aca786e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696016383 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3696016383
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2342239115
Short name T2
Test name
Test status
Simulation time 31251359295 ps
CPU time 15.46 seconds
Started Jul 05 04:46:01 PM PDT 24
Finished Jul 05 04:46:17 PM PDT 24
Peak memory 192060 kb
Host smart-9084f5c4-e1d3-49e6-a4e4-0ff7e61ae1cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342239115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2342239115
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2006239596
Short name T55
Test name
Test status
Simulation time 142044841059 ps
CPU time 291.05 seconds
Started Jul 05 04:45:37 PM PDT 24
Finished Jul 05 04:50:29 PM PDT 24
Peak memory 206856 kb
Host smart-7dfdf8ed-9bb4-460d-a155-9e5fedc515fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006239596 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2006239596
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3769797488
Short name T56
Test name
Test status
Simulation time 229767614319 ps
CPU time 403.49 seconds
Started Jul 05 04:45:38 PM PDT 24
Finished Jul 05 04:52:22 PM PDT 24
Peak memory 210560 kb
Host smart-e355db96-bbdd-4086-bae6-7ec5b8d3a272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769797488 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3769797488
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1706779907
Short name T35
Test name
Test status
Simulation time 8599699267 ps
CPU time 3.32 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:25 PM PDT 24
Peak memory 198132 kb
Host smart-72f08b44-dbc3-4569-ae5d-072a4f3e273a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706779907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1706779907
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.433906933
Short name T135
Test name
Test status
Simulation time 419065038424 ps
CPU time 1140.34 seconds
Started Jul 05 04:45:04 PM PDT 24
Finished Jul 05 05:04:05 PM PDT 24
Peak memory 215004 kb
Host smart-18967b11-b51e-4116-8b37-8330579dc2ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433906933 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.433906933
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1328905654
Short name T85
Test name
Test status
Simulation time 440213692273 ps
CPU time 707.11 seconds
Started Jul 05 04:46:19 PM PDT 24
Finished Jul 05 04:58:06 PM PDT 24
Peak memory 206560 kb
Host smart-6f498d58-e345-49e7-92a1-863d3ed95bd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328905654 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1328905654
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.681492546
Short name T99
Test name
Test status
Simulation time 72268107559 ps
CPU time 537.1 seconds
Started Jul 05 04:44:44 PM PDT 24
Finished Jul 05 04:53:42 PM PDT 24
Peak memory 211456 kb
Host smart-efbe0683-64cb-4c1d-8f8e-b8fce92cc27c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681492546 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.681492546
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2224708669
Short name T129
Test name
Test status
Simulation time 82998731751 ps
CPU time 915.45 seconds
Started Jul 05 04:45:07 PM PDT 24
Finished Jul 05 05:00:23 PM PDT 24
Peak memory 209396 kb
Host smart-0e63870f-9524-4a98-8adb-8771b36a7d07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224708669 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2224708669
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2594157485
Short name T45
Test name
Test status
Simulation time 210250120885 ps
CPU time 167.05 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:48:17 PM PDT 24
Peak memory 193040 kb
Host smart-bc86feab-41f2-4a95-b1ad-b8ffcb523c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594157485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2594157485
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3277926306
Short name T86
Test name
Test status
Simulation time 612365050951 ps
CPU time 345.2 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:51:15 PM PDT 24
Peak memory 202048 kb
Host smart-e90d3d25-19af-4690-8750-88c3795ffedc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277926306 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3277926306
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2183041138
Short name T98
Test name
Test status
Simulation time 223827969566 ps
CPU time 229.11 seconds
Started Jul 05 04:50:44 PM PDT 24
Finished Jul 05 04:54:34 PM PDT 24
Peak memory 200712 kb
Host smart-c7c412d0-434d-403f-977c-442ea45cc408
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183041138 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2183041138
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.612675330
Short name T109
Test name
Test status
Simulation time 149500787793 ps
CPU time 86.61 seconds
Started Jul 05 04:45:16 PM PDT 24
Finished Jul 05 04:46:44 PM PDT 24
Peak memory 192612 kb
Host smart-35596131-ad14-4dee-b935-f8b389641e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612675330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.612675330
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.981080392
Short name T158
Test name
Test status
Simulation time 37400749112 ps
CPU time 365.07 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:51:35 PM PDT 24
Peak memory 199316 kb
Host smart-ccda05af-0326-4963-bd97-a56bc46adb25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981080392 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.981080392
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.155769092
Short name T81
Test name
Test status
Simulation time 761156536992 ps
CPU time 1494.41 seconds
Started Jul 05 04:46:26 PM PDT 24
Finished Jul 05 05:11:22 PM PDT 24
Peak memory 216272 kb
Host smart-310ece5c-fff7-434f-928f-cc752c4806b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155769092 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.155769092
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.509075699
Short name T78
Test name
Test status
Simulation time 142194687188 ps
CPU time 347.89 seconds
Started Jul 05 04:45:39 PM PDT 24
Finished Jul 05 04:51:28 PM PDT 24
Peak memory 202480 kb
Host smart-3f72aec0-125f-4ceb-a2f4-447580faf3f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509075699 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.509075699
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1746303589
Short name T150
Test name
Test status
Simulation time 69820748789 ps
CPU time 280.33 seconds
Started Jul 05 04:46:28 PM PDT 24
Finished Jul 05 04:51:09 PM PDT 24
Peak memory 200184 kb
Host smart-3c140f0a-60e1-4d4d-9cde-249a64c6dd3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746303589 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1746303589
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2106452526
Short name T120
Test name
Test status
Simulation time 277760132811 ps
CPU time 434.88 seconds
Started Jul 05 04:46:20 PM PDT 24
Finished Jul 05 04:53:35 PM PDT 24
Peak memory 202304 kb
Host smart-588870de-aacf-4511-804d-e345772f4db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106452526 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2106452526
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.111622086
Short name T29
Test name
Test status
Simulation time 555912665257 ps
CPU time 462.42 seconds
Started Jul 05 04:45:36 PM PDT 24
Finished Jul 05 04:53:19 PM PDT 24
Peak memory 198160 kb
Host smart-5f6f8afd-c938-418a-ab82-a73aa248b53e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111622086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.111622086
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2304553749
Short name T118
Test name
Test status
Simulation time 140711001492 ps
CPU time 53.49 seconds
Started Jul 05 04:45:15 PM PDT 24
Finished Jul 05 04:46:09 PM PDT 24
Peak memory 184416 kb
Host smart-5535a47a-474c-41e0-a774-c61b00ac44dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304553749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2304553749
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.192351873
Short name T77
Test name
Test status
Simulation time 509929735683 ps
CPU time 827.68 seconds
Started Jul 05 04:45:31 PM PDT 24
Finished Jul 05 04:59:20 PM PDT 24
Peak memory 207364 kb
Host smart-cccf9977-25b5-4d54-864c-095337880a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192351873 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.192351873
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.57856798
Short name T102
Test name
Test status
Simulation time 130463834993 ps
CPU time 186.37 seconds
Started Jul 05 04:45:44 PM PDT 24
Finished Jul 05 04:48:52 PM PDT 24
Peak memory 192928 kb
Host smart-ad2dfb3d-c26f-4972-af3c-a7a3d0b441ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57856798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_al
l.57856798
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3284782055
Short name T92
Test name
Test status
Simulation time 64930917641 ps
CPU time 136.4 seconds
Started Jul 05 04:45:39 PM PDT 24
Finished Jul 05 04:47:57 PM PDT 24
Peak memory 198676 kb
Host smart-64acda23-f1be-4e1d-a225-98de17152278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284782055 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3284782055
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1848005573
Short name T96
Test name
Test status
Simulation time 94817427253 ps
CPU time 346.91 seconds
Started Jul 05 04:46:09 PM PDT 24
Finished Jul 05 04:51:57 PM PDT 24
Peak memory 201912 kb
Host smart-9d57a254-1a9d-4cd7-b366-efb4eff49b65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848005573 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1848005573
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.4111107562
Short name T151
Test name
Test status
Simulation time 82517343955 ps
CPU time 117.06 seconds
Started Jul 05 04:46:08 PM PDT 24
Finished Jul 05 04:48:06 PM PDT 24
Peak memory 193048 kb
Host smart-c8dd93a2-1741-49ce-8c11-5a5248ea716c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111107562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.4111107562
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.207875571
Short name T113
Test name
Test status
Simulation time 195708048890 ps
CPU time 279.79 seconds
Started Jul 05 04:46:08 PM PDT 24
Finished Jul 05 04:50:48 PM PDT 24
Peak memory 198468 kb
Host smart-c7c5505c-c8bf-44b2-977a-e50a70d1f95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207875571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.207875571
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1597397310
Short name T162
Test name
Test status
Simulation time 44214345927 ps
CPU time 339.03 seconds
Started Jul 05 04:46:05 PM PDT 24
Finished Jul 05 04:51:45 PM PDT 24
Peak memory 207296 kb
Host smart-2eaaa35d-f3f8-4dd6-a92a-065f0f8e7b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597397310 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1597397310
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.576474457
Short name T149
Test name
Test status
Simulation time 139813694714 ps
CPU time 601.09 seconds
Started Jul 05 04:46:27 PM PDT 24
Finished Jul 05 04:56:29 PM PDT 24
Peak memory 204768 kb
Host smart-c2f741ad-363d-4157-a0c4-5a990ecad6a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576474457 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.576474457
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.150987336
Short name T128
Test name
Test status
Simulation time 57786934823 ps
CPU time 15.41 seconds
Started Jul 05 04:45:43 PM PDT 24
Finished Jul 05 04:46:00 PM PDT 24
Peak memory 193112 kb
Host smart-69a09939-e1b9-4b0d-9b20-27a7acd87087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150987336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.150987336
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1595427930
Short name T15
Test name
Test status
Simulation time 149050527818 ps
CPU time 776.42 seconds
Started Jul 05 04:46:15 PM PDT 24
Finished Jul 05 04:59:12 PM PDT 24
Peak memory 215040 kb
Host smart-738cb1e4-75b0-46f4-bd95-a265f910779d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595427930 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1595427930
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.32299313
Short name T107
Test name
Test status
Simulation time 137876953969 ps
CPU time 93.72 seconds
Started Jul 05 04:45:10 PM PDT 24
Finished Jul 05 04:46:45 PM PDT 24
Peak memory 193040 kb
Host smart-67a20ef1-9843-452d-9b3c-bf247dfb0df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32299313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all
.32299313
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1826760911
Short name T115
Test name
Test status
Simulation time 9020090041 ps
CPU time 4.25 seconds
Started Jul 05 04:45:30 PM PDT 24
Finished Jul 05 04:45:35 PM PDT 24
Peak memory 193080 kb
Host smart-a3f53f54-51dc-4900-a5ea-bca2fc4fe5f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826760911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1826760911
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1592334861
Short name T141
Test name
Test status
Simulation time 370807291865 ps
CPU time 106.57 seconds
Started Jul 05 04:45:32 PM PDT 24
Finished Jul 05 04:47:19 PM PDT 24
Peak memory 184216 kb
Host smart-e69cfdec-44fa-4d4c-ab9d-975b01efbc10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592334861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1592334861
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3204787128
Short name T97
Test name
Test status
Simulation time 347431366194 ps
CPU time 247.14 seconds
Started Jul 05 04:45:54 PM PDT 24
Finished Jul 05 04:50:02 PM PDT 24
Peak memory 198316 kb
Host smart-c1f7ec40-5a72-4cb8-97cf-2a448de0d896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204787128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3204787128
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1828151248
Short name T43
Test name
Test status
Simulation time 311626615029 ps
CPU time 835.17 seconds
Started Jul 05 04:46:08 PM PDT 24
Finished Jul 05 05:00:04 PM PDT 24
Peak memory 215036 kb
Host smart-8387c294-e130-4506-8533-85f2a17f50d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828151248 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1828151248
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.4024178738
Short name T155
Test name
Test status
Simulation time 319851951263 ps
CPU time 116.89 seconds
Started Jul 05 04:45:54 PM PDT 24
Finished Jul 05 04:47:52 PM PDT 24
Peak memory 193084 kb
Host smart-28784cc5-b445-49f2-86b8-d2904144ab0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024178738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.4024178738
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.4227865312
Short name T131
Test name
Test status
Simulation time 87794817903 ps
CPU time 182.01 seconds
Started Jul 05 04:45:53 PM PDT 24
Finished Jul 05 04:48:56 PM PDT 24
Peak memory 214284 kb
Host smart-599b54ea-50f4-4f38-af96-7d30ffed5bd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227865312 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.4227865312
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3739900262
Short name T95
Test name
Test status
Simulation time 10897691982 ps
CPU time 4.75 seconds
Started Jul 05 04:46:26 PM PDT 24
Finished Jul 05 04:46:32 PM PDT 24
Peak memory 192960 kb
Host smart-4d5a4025-244f-4c66-82a9-e656b78b2d06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739900262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3739900262
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3977446744
Short name T119
Test name
Test status
Simulation time 102856612814 ps
CPU time 80.88 seconds
Started Jul 05 04:46:36 PM PDT 24
Finished Jul 05 04:47:58 PM PDT 24
Peak memory 198168 kb
Host smart-b738ae35-fa01-4bdd-9fd6-9f2a082b8357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977446744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3977446744
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1570075424
Short name T152
Test name
Test status
Simulation time 258961881061 ps
CPU time 733.88 seconds
Started Jul 05 04:45:05 PM PDT 24
Finished Jul 05 04:57:20 PM PDT 24
Peak memory 207332 kb
Host smart-57eedf6d-4dbf-4d7c-b994-c0b3679ba6b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570075424 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1570075424
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3268242223
Short name T110
Test name
Test status
Simulation time 46214442462 ps
CPU time 72.18 seconds
Started Jul 05 04:44:47 PM PDT 24
Finished Jul 05 04:46:00 PM PDT 24
Peak memory 198212 kb
Host smart-78948f8b-b259-4fe5-90e3-67ed3b5612c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268242223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3268242223
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2533173116
Short name T82
Test name
Test status
Simulation time 106157529939 ps
CPU time 207.55 seconds
Started Jul 05 04:45:15 PM PDT 24
Finished Jul 05 04:48:43 PM PDT 24
Peak memory 200232 kb
Host smart-8d63a03c-0df5-43c9-b55c-d362a089d5d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533173116 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2533173116
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3548824096
Short name T93
Test name
Test status
Simulation time 271044804457 ps
CPU time 408.77 seconds
Started Jul 05 04:45:25 PM PDT 24
Finished Jul 05 04:52:14 PM PDT 24
Peak memory 193048 kb
Host smart-896c8c6f-d58d-4aac-9442-9a29c756610b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548824096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3548824096
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2558233914
Short name T80
Test name
Test status
Simulation time 365548511457 ps
CPU time 854.07 seconds
Started Jul 05 04:46:20 PM PDT 24
Finished Jul 05 05:00:34 PM PDT 24
Peak memory 208644 kb
Host smart-f823f25d-969a-4553-babb-ee4a735e6316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558233914 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2558233914
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.811413682
Short name T103
Test name
Test status
Simulation time 12034714880 ps
CPU time 88.5 seconds
Started Jul 05 04:44:52 PM PDT 24
Finished Jul 05 04:46:21 PM PDT 24
Peak memory 198648 kb
Host smart-7f4b9011-9e47-40ef-a4a7-7ff420a2b55e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811413682 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.811413682
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2334807145
Short name T79
Test name
Test status
Simulation time 275129300191 ps
CPU time 448.98 seconds
Started Jul 05 04:46:08 PM PDT 24
Finished Jul 05 04:53:37 PM PDT 24
Peak memory 203712 kb
Host smart-bad76c59-6d4a-4735-a407-b443e60adc8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334807145 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2334807145
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.780137929
Short name T121
Test name
Test status
Simulation time 222400510229 ps
CPU time 80.63 seconds
Started Jul 05 04:45:02 PM PDT 24
Finished Jul 05 04:46:23 PM PDT 24
Peak memory 191988 kb
Host smart-91f52f67-236e-4e12-a032-c55d6e9ab137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780137929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.780137929
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1965291709
Short name T166
Test name
Test status
Simulation time 47650973826 ps
CPU time 378.05 seconds
Started Jul 05 04:45:52 PM PDT 24
Finished Jul 05 04:52:11 PM PDT 24
Peak memory 199928 kb
Host smart-46805346-ec56-4e57-81cc-ed9a70536422
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965291709 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1965291709
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3166085506
Short name T156
Test name
Test status
Simulation time 111944040616 ps
CPU time 38.34 seconds
Started Jul 05 04:45:14 PM PDT 24
Finished Jul 05 04:45:53 PM PDT 24
Peak memory 198300 kb
Host smart-f8e87499-2fed-41ce-80fc-c8fe3190532d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166085506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3166085506
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1458511685
Short name T132
Test name
Test status
Simulation time 75231535223 ps
CPU time 77.8 seconds
Started Jul 05 04:44:53 PM PDT 24
Finished Jul 05 04:46:11 PM PDT 24
Peak memory 184704 kb
Host smart-2a0f3be7-575d-41a4-beba-52b5f9ae21bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458511685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1458511685
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.429684596
Short name T101
Test name
Test status
Simulation time 418405971861 ps
CPU time 218.92 seconds
Started Jul 05 04:45:39 PM PDT 24
Finished Jul 05 04:49:18 PM PDT 24
Peak memory 193060 kb
Host smart-c1cc0368-b6b4-4cc5-9fe5-f03ae8a4e973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429684596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.429684596
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2059427704
Short name T13
Test name
Test status
Simulation time 31723500334 ps
CPU time 240.26 seconds
Started Jul 05 04:46:02 PM PDT 24
Finished Jul 05 04:50:05 PM PDT 24
Peak memory 215032 kb
Host smart-44b82bf0-6e11-4578-a618-4406670b2007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059427704 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2059427704
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1284366014
Short name T51
Test name
Test status
Simulation time 31795085152 ps
CPU time 7.11 seconds
Started Jul 05 04:46:20 PM PDT 24
Finished Jul 05 04:46:27 PM PDT 24
Peak memory 191976 kb
Host smart-07788029-2107-4b4d-a95f-1eb09becd7f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284366014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1284366014
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.389223199
Short name T90
Test name
Test status
Simulation time 200633959916 ps
CPU time 241.57 seconds
Started Jul 05 04:45:22 PM PDT 24
Finished Jul 05 04:49:24 PM PDT 24
Peak memory 191992 kb
Host smart-e3dd38b5-85f5-4d4e-8219-69efeaab3058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389223199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.389223199
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3795810710
Short name T91
Test name
Test status
Simulation time 61547075175 ps
CPU time 401.21 seconds
Started Jul 05 04:45:21 PM PDT 24
Finished Jul 05 04:52:03 PM PDT 24
Peak memory 200912 kb
Host smart-e4ad137c-2e6f-4ff5-a4d8-ec5b64311fa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795810710 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3795810710
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3007041089
Short name T83
Test name
Test status
Simulation time 82313439458 ps
CPU time 165.91 seconds
Started Jul 05 04:45:44 PM PDT 24
Finished Jul 05 04:48:30 PM PDT 24
Peak memory 199356 kb
Host smart-227a6ce9-5e6f-4539-8df3-f6f597d550f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007041089 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3007041089
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3552455007
Short name T137
Test name
Test status
Simulation time 205177550006 ps
CPU time 259.16 seconds
Started Jul 05 04:45:20 PM PDT 24
Finished Jul 05 04:49:40 PM PDT 24
Peak memory 192948 kb
Host smart-f1fd6cbb-396d-441d-8a13-0fe010802045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552455007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3552455007
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1254415166
Short name T100
Test name
Test status
Simulation time 180838649788 ps
CPU time 266.06 seconds
Started Jul 05 04:45:54 PM PDT 24
Finished Jul 05 04:50:21 PM PDT 24
Peak memory 198344 kb
Host smart-7fda479f-052a-4d05-bf9c-261e2edcb90c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254415166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1254415166
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2214869189
Short name T41
Test name
Test status
Simulation time 615829532895 ps
CPU time 623.74 seconds
Started Jul 05 04:45:02 PM PDT 24
Finished Jul 05 04:55:27 PM PDT 24
Peak memory 214332 kb
Host smart-c09812f6-af43-48eb-974f-a23708ff2cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214869189 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2214869189
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2236211496
Short name T39
Test name
Test status
Simulation time 48748593228 ps
CPU time 145.34 seconds
Started Jul 05 04:45:15 PM PDT 24
Finished Jul 05 04:47:41 PM PDT 24
Peak memory 206844 kb
Host smart-4b0a8bc4-0176-46c6-9f1e-3aa60dd37898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236211496 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2236211496
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3883314651
Short name T154
Test name
Test status
Simulation time 30138259637 ps
CPU time 237.46 seconds
Started Jul 05 04:44:55 PM PDT 24
Finished Jul 05 04:48:53 PM PDT 24
Peak memory 206856 kb
Host smart-fe2d3d27-19b5-41d7-b589-0507e17feb45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883314651 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3883314651
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3181399087
Short name T76
Test name
Test status
Simulation time 51592793316 ps
CPU time 527.53 seconds
Started Jul 05 04:46:21 PM PDT 24
Finished Jul 05 04:55:09 PM PDT 24
Peak memory 214120 kb
Host smart-7200b187-4c73-4270-bbbc-2858125a370f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181399087 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3181399087
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4276248703
Short name T68
Test name
Test status
Simulation time 523461250 ps
CPU time 1.16 seconds
Started Jul 05 05:16:34 PM PDT 24
Finished Jul 05 05:16:36 PM PDT 24
Peak memory 194512 kb
Host smart-56da6f55-03be-4f81-b26c-557d6f9b1014
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276248703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4276248703
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.139691364
Short name T75
Test name
Test status
Simulation time 1462735921 ps
CPU time 1.1 seconds
Started Jul 05 05:16:17 PM PDT 24
Finished Jul 05 05:16:19 PM PDT 24
Peak memory 192940 kb
Host smart-6b0aa0c5-d113-49b3-89e8-33f8fd4a7b0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139691364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.139691364
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3869181673
Short name T136
Test name
Test status
Simulation time 148770522476 ps
CPU time 113.01 seconds
Started Jul 05 04:45:13 PM PDT 24
Finished Jul 05 04:47:06 PM PDT 24
Peak memory 193028 kb
Host smart-6f5907f0-709d-4300-93fc-1d6dd73d55af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869181673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3869181673
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.666430489
Short name T167
Test name
Test status
Simulation time 1046214137120 ps
CPU time 898.03 seconds
Started Jul 05 04:45:13 PM PDT 24
Finished Jul 05 05:00:11 PM PDT 24
Peak memory 214892 kb
Host smart-d1e48997-8273-4983-adb1-381310249c85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666430489 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.666430489
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4210546119
Short name T145
Test name
Test status
Simulation time 289663358690 ps
CPU time 99.23 seconds
Started Jul 05 04:44:54 PM PDT 24
Finished Jul 05 04:46:33 PM PDT 24
Peak memory 192004 kb
Host smart-d1413177-f4f5-4d33-a243-99e4c3cc3e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210546119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4210546119
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1394023298
Short name T23
Test name
Test status
Simulation time 111679462905 ps
CPU time 233.67 seconds
Started Jul 05 04:46:33 PM PDT 24
Finished Jul 05 04:50:27 PM PDT 24
Peak memory 214360 kb
Host smart-b4dce615-b77b-4583-96b3-0f729d9787af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394023298 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1394023298
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3573664279
Short name T143
Test name
Test status
Simulation time 244142134955 ps
CPU time 353.27 seconds
Started Jul 05 04:45:09 PM PDT 24
Finished Jul 05 04:51:03 PM PDT 24
Peak memory 192220 kb
Host smart-38a0dab4-c41c-4bf0-b6cc-90c890f63351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573664279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3573664279
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.282067113
Short name T165
Test name
Test status
Simulation time 322324868989 ps
CPU time 437.57 seconds
Started Jul 05 04:44:45 PM PDT 24
Finished Jul 05 04:52:04 PM PDT 24
Peak memory 191988 kb
Host smart-d9bf8221-56a6-4ca0-b66b-5a268d844e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282067113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.282067113
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.558676126
Short name T127
Test name
Test status
Simulation time 435910965307 ps
CPU time 100.76 seconds
Started Jul 05 04:45:37 PM PDT 24
Finished Jul 05 04:47:19 PM PDT 24
Peak memory 198352 kb
Host smart-95256f18-8b0a-4c3e-bc93-cf5460d8f5b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558676126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.558676126
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.472774101
Short name T106
Test name
Test status
Simulation time 91024089532 ps
CPU time 137.48 seconds
Started Jul 05 04:45:04 PM PDT 24
Finished Jul 05 04:47:22 PM PDT 24
Peak memory 191984 kb
Host smart-244cea2f-1bbf-4170-9c33-8498aa9ee96a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472774101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.472774101
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3828594690
Short name T159
Test name
Test status
Simulation time 39910346032 ps
CPU time 432.88 seconds
Started Jul 05 04:46:25 PM PDT 24
Finished Jul 05 04:53:39 PM PDT 24
Peak memory 214948 kb
Host smart-51264864-198d-40c0-8ad4-00cbafcedfd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828594690 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3828594690
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1851030718
Short name T84
Test name
Test status
Simulation time 82258096335 ps
CPU time 149.01 seconds
Started Jul 05 04:46:37 PM PDT 24
Finished Jul 05 04:49:07 PM PDT 24
Peak memory 199320 kb
Host smart-b072c6a6-2f0e-4794-9389-719101d7615b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851030718 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1851030718
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2332098881
Short name T124
Test name
Test status
Simulation time 384770268 ps
CPU time 1.13 seconds
Started Jul 05 04:45:23 PM PDT 24
Finished Jul 05 04:45:24 PM PDT 24
Peak memory 196632 kb
Host smart-745fc190-125b-4343-a025-d4dce0b25184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332098881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2332098881
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1994645932
Short name T133
Test name
Test status
Simulation time 578455062 ps
CPU time 0.74 seconds
Started Jul 05 04:45:35 PM PDT 24
Finished Jul 05 04:45:36 PM PDT 24
Peak memory 196768 kb
Host smart-bd13fc3e-ef5d-4e71-ab3f-03c9e4808b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994645932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1994645932
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4246391768
Short name T160
Test name
Test status
Simulation time 508845317 ps
CPU time 1.24 seconds
Started Jul 05 04:46:26 PM PDT 24
Finished Jul 05 04:46:29 PM PDT 24
Peak memory 196676 kb
Host smart-ac2d0db7-a527-4b98-9ea3-0b06573b5660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246391768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4246391768
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1448835370
Short name T11
Test name
Test status
Simulation time 291275643354 ps
CPU time 120.52 seconds
Started Jul 05 04:46:25 PM PDT 24
Finished Jul 05 04:48:26 PM PDT 24
Peak memory 192652 kb
Host smart-69f2739d-da1c-4b8f-abca-870bd34d430b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448835370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1448835370
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.307637191
Short name T153
Test name
Test status
Simulation time 544384785 ps
CPU time 0.77 seconds
Started Jul 05 04:44:55 PM PDT 24
Finished Jul 05 04:44:57 PM PDT 24
Peak memory 196744 kb
Host smart-93f47494-7d74-47f5-b700-8320d75f3ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307637191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.307637191
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3823150719
Short name T117
Test name
Test status
Simulation time 527906355 ps
CPU time 1.28 seconds
Started Jul 05 04:45:35 PM PDT 24
Finished Jul 05 04:45:37 PM PDT 24
Peak memory 196832 kb
Host smart-b97ee4fe-eca1-46f0-a94c-513bdff928b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823150719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3823150719
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2636651162
Short name T114
Test name
Test status
Simulation time 525438205 ps
CPU time 0.64 seconds
Started Jul 05 04:45:53 PM PDT 24
Finished Jul 05 04:45:54 PM PDT 24
Peak memory 196736 kb
Host smart-4db224bf-d60f-4beb-a69d-3435d71d4a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636651162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2636651162
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1569475071
Short name T3
Test name
Test status
Simulation time 323529668472 ps
CPU time 433.93 seconds
Started Jul 05 04:46:02 PM PDT 24
Finished Jul 05 04:53:18 PM PDT 24
Peak memory 193044 kb
Host smart-c5f42368-95f7-4818-84c3-dc892a55d47e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569475071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1569475071
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.61429506
Short name T94
Test name
Test status
Simulation time 574151750 ps
CPU time 1.34 seconds
Started Jul 05 04:46:09 PM PDT 24
Finished Jul 05 04:46:11 PM PDT 24
Peak memory 196740 kb
Host smart-353b9875-a9b1-48a5-9f0e-5f123a180161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61429506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.61429506
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2349118411
Short name T108
Test name
Test status
Simulation time 484504404 ps
CPU time 0.78 seconds
Started Jul 05 04:46:09 PM PDT 24
Finished Jul 05 04:46:11 PM PDT 24
Peak memory 196704 kb
Host smart-231a0bf4-1da8-4a5d-baf0-5b551a226b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349118411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2349118411
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1570802801
Short name T139
Test name
Test status
Simulation time 82746162226 ps
CPU time 31.42 seconds
Started Jul 05 04:46:19 PM PDT 24
Finished Jul 05 04:46:51 PM PDT 24
Peak memory 198244 kb
Host smart-329c9c56-c066-4a5c-b941-4856c8ed81f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570802801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1570802801
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3176846448
Short name T7
Test name
Test status
Simulation time 87955521999 ps
CPU time 15.96 seconds
Started Jul 05 04:46:17 PM PDT 24
Finished Jul 05 04:46:34 PM PDT 24
Peak memory 191884 kb
Host smart-306c6807-f792-4c81-8fdd-e00460305e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176846448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3176846448
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.252793248
Short name T146
Test name
Test status
Simulation time 511033996 ps
CPU time 0.77 seconds
Started Jul 05 04:46:37 PM PDT 24
Finished Jul 05 04:46:38 PM PDT 24
Peak memory 196568 kb
Host smart-c23cedfb-cbbb-4908-8dcb-9545ee555e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252793248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.252793248
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.671892698
Short name T116
Test name
Test status
Simulation time 469485606 ps
CPU time 0.71 seconds
Started Jul 05 04:46:34 PM PDT 24
Finished Jul 05 04:46:35 PM PDT 24
Peak memory 196744 kb
Host smart-6e46d65c-cdd0-43bb-b094-46cf21b09272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671892698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.671892698
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2016482157
Short name T169
Test name
Test status
Simulation time 53686753370 ps
CPU time 603.21 seconds
Started Jul 05 04:45:14 PM PDT 24
Finished Jul 05 04:55:18 PM PDT 24
Peak memory 211304 kb
Host smart-f5200ed3-10be-4dcf-9d08-d1340607fe60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016482157 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2016482157
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1757289022
Short name T175
Test name
Test status
Simulation time 37241241159 ps
CPU time 169.08 seconds
Started Jul 05 04:45:30 PM PDT 24
Finished Jul 05 04:48:20 PM PDT 24
Peak memory 206796 kb
Host smart-c2053869-040d-4feb-ab6f-ce07b4c35736
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757289022 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1757289022
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3400251631
Short name T88
Test name
Test status
Simulation time 387605578 ps
CPU time 1.16 seconds
Started Jul 05 04:45:37 PM PDT 24
Finished Jul 05 04:45:38 PM PDT 24
Peak memory 196744 kb
Host smart-2934c5d7-82b5-41ec-987a-88527b7293cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400251631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3400251631
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1207429695
Short name T10
Test name
Test status
Simulation time 221337427204 ps
CPU time 149.21 seconds
Started Jul 05 04:45:39 PM PDT 24
Finished Jul 05 04:48:09 PM PDT 24
Peak memory 191968 kb
Host smart-9bf18777-fa96-4b54-801e-620715d8ecb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207429695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1207429695
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.81068125
Short name T105
Test name
Test status
Simulation time 482419037 ps
CPU time 0.86 seconds
Started Jul 05 04:45:38 PM PDT 24
Finished Jul 05 04:45:39 PM PDT 24
Peak memory 196816 kb
Host smart-4c264ad1-57e8-4cac-8372-43e46decb6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81068125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.81068125
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4067771449
Short name T25
Test name
Test status
Simulation time 561068359 ps
CPU time 0.7 seconds
Started Jul 05 04:46:03 PM PDT 24
Finished Jul 05 04:46:05 PM PDT 24
Peak memory 196736 kb
Host smart-d7d4bc5f-d591-4533-8d63-e59ad1039b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067771449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4067771449
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1175923018
Short name T147
Test name
Test status
Simulation time 540146388 ps
CPU time 0.67 seconds
Started Jul 05 04:46:32 PM PDT 24
Finished Jul 05 04:46:33 PM PDT 24
Peak memory 196692 kb
Host smart-3bdb3cd4-7a47-4a46-934d-4eb511222581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175923018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1175923018
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.260971522
Short name T140
Test name
Test status
Simulation time 523020184 ps
CPU time 0.91 seconds
Started Jul 05 04:45:03 PM PDT 24
Finished Jul 05 04:45:05 PM PDT 24
Peak memory 196696 kb
Host smart-57a7958a-6dd3-43ce-ab48-a13bea7b3834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260971522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.260971522
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3776276465
Short name T30
Test name
Test status
Simulation time 404663484 ps
CPU time 0.78 seconds
Started Jul 05 04:45:54 PM PDT 24
Finished Jul 05 04:45:56 PM PDT 24
Peak memory 196772 kb
Host smart-042ed251-5f26-4b83-9eef-65b02e65875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776276465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3776276465
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3471720373
Short name T157
Test name
Test status
Simulation time 451023144 ps
CPU time 0.91 seconds
Started Jul 05 04:46:01 PM PDT 24
Finished Jul 05 04:46:03 PM PDT 24
Peak memory 196696 kb
Host smart-d5847024-2c5a-49ff-a5ae-bc55e16f5b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471720373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3471720373
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2675335017
Short name T184
Test name
Test status
Simulation time 40847993199 ps
CPU time 52.01 seconds
Started Jul 05 04:46:05 PM PDT 24
Finished Jul 05 04:46:58 PM PDT 24
Peak memory 198272 kb
Host smart-105f58c2-c658-4428-b7aa-7a5b63aae0dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675335017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2675335017
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3263755762
Short name T173
Test name
Test status
Simulation time 44386179096 ps
CPU time 204.36 seconds
Started Jul 05 04:46:18 PM PDT 24
Finished Jul 05 04:49:43 PM PDT 24
Peak memory 198556 kb
Host smart-66d3e8bd-e396-438c-a450-e2b70a32873b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263755762 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3263755762
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.669091455
Short name T142
Test name
Test status
Simulation time 535661091 ps
CPU time 0.78 seconds
Started Jul 05 04:44:44 PM PDT 24
Finished Jul 05 04:44:46 PM PDT 24
Peak memory 196768 kb
Host smart-03f13679-d05c-47c7-9b87-c4877c1179c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669091455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.669091455
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1273900138
Short name T50
Test name
Test status
Simulation time 387308021 ps
CPU time 1.19 seconds
Started Jul 05 04:46:00 PM PDT 24
Finished Jul 05 04:46:03 PM PDT 24
Peak memory 196728 kb
Host smart-327e006a-c8f3-4b4e-b07d-9456561c1481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273900138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1273900138
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4060879903
Short name T122
Test name
Test status
Simulation time 431678070 ps
CPU time 1.19 seconds
Started Jul 05 04:46:16 PM PDT 24
Finished Jul 05 04:46:17 PM PDT 24
Peak memory 196780 kb
Host smart-651e3f99-4583-484e-9441-156f45306dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060879903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4060879903
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1884858817
Short name T144
Test name
Test status
Simulation time 489405584 ps
CPU time 1.08 seconds
Started Jul 05 04:46:17 PM PDT 24
Finished Jul 05 04:46:19 PM PDT 24
Peak memory 196756 kb
Host smart-46ddc20a-bea7-4e20-abd5-9a81031f9e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884858817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1884858817
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.678736593
Short name T185
Test name
Test status
Simulation time 354506778771 ps
CPU time 264.06 seconds
Started Jul 05 04:46:35 PM PDT 24
Finished Jul 05 04:51:00 PM PDT 24
Peak memory 192904 kb
Host smart-0f618148-75a9-40af-908e-97d3660e90d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678736593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.678736593
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1113154605
Short name T134
Test name
Test status
Simulation time 442733674 ps
CPU time 0.91 seconds
Started Jul 05 04:45:13 PM PDT 24
Finished Jul 05 04:45:14 PM PDT 24
Peak memory 196760 kb
Host smart-e88039b7-9945-4728-83c6-94dd14061ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113154605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1113154605
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1186901310
Short name T138
Test name
Test status
Simulation time 486786155 ps
CPU time 1.28 seconds
Started Jul 05 04:45:15 PM PDT 24
Finished Jul 05 04:45:17 PM PDT 24
Peak memory 196728 kb
Host smart-e4a11c08-d7bf-4ab4-b78d-f8a7f4aa228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186901310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1186901310
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2406448171
Short name T177
Test name
Test status
Simulation time 482972604 ps
CPU time 1.25 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:45:32 PM PDT 24
Peak memory 196700 kb
Host smart-9e0c8b01-7451-45f0-8b73-62e0785da0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406448171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2406448171
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1826666949
Short name T163
Test name
Test status
Simulation time 6923975311 ps
CPU time 3.26 seconds
Started Jul 05 04:45:44 PM PDT 24
Finished Jul 05 04:45:48 PM PDT 24
Peak memory 198248 kb
Host smart-0a994ad9-674a-438c-b138-b20731449ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826666949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1826666949
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3766788313
Short name T192
Test name
Test status
Simulation time 592552598 ps
CPU time 1.47 seconds
Started Jul 05 04:45:45 PM PDT 24
Finished Jul 05 04:45:47 PM PDT 24
Peak memory 196708 kb
Host smart-a53b93e9-3f76-4627-ae1e-16b1b3d7da2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766788313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3766788313
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.220830158
Short name T161
Test name
Test status
Simulation time 169210508661 ps
CPU time 115.34 seconds
Started Jul 05 04:46:01 PM PDT 24
Finished Jul 05 04:47:57 PM PDT 24
Peak memory 198224 kb
Host smart-cd4d95d3-4941-494c-bec8-decafa1e949c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220830158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.220830158
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1238515357
Short name T125
Test name
Test status
Simulation time 585448872 ps
CPU time 0.83 seconds
Started Jul 05 04:46:05 PM PDT 24
Finished Jul 05 04:46:06 PM PDT 24
Peak memory 196688 kb
Host smart-426ea0f6-0f92-4a61-801d-3d363f6d13dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238515357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1238515357
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1046755392
Short name T104
Test name
Test status
Simulation time 379675174 ps
CPU time 1.17 seconds
Started Jul 05 04:46:08 PM PDT 24
Finished Jul 05 04:46:10 PM PDT 24
Peak memory 196712 kb
Host smart-ab2d546c-0410-41a4-b353-d164121afbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046755392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1046755392
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1765531392
Short name T111
Test name
Test status
Simulation time 494099019 ps
CPU time 0.89 seconds
Started Jul 05 04:46:27 PM PDT 24
Finished Jul 05 04:46:29 PM PDT 24
Peak memory 196724 kb
Host smart-dad2872b-bd6b-429d-8827-848df4162fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765531392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1765531392
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3862385422
Short name T188
Test name
Test status
Simulation time 606269172 ps
CPU time 1.56 seconds
Started Jul 05 04:44:44 PM PDT 24
Finished Jul 05 04:44:47 PM PDT 24
Peak memory 196696 kb
Host smart-935af40a-74d0-403e-ae31-0fae440dc1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862385422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3862385422
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.692951004
Short name T52
Test name
Test status
Simulation time 534416385 ps
CPU time 0.76 seconds
Started Jul 05 04:45:44 PM PDT 24
Finished Jul 05 04:45:46 PM PDT 24
Peak memory 196700 kb
Host smart-97f31a17-8699-483e-b343-9b04a910239e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692951004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.692951004
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4155240123
Short name T178
Test name
Test status
Simulation time 64192421256 ps
CPU time 478.31 seconds
Started Jul 05 04:45:45 PM PDT 24
Finished Jul 05 04:53:44 PM PDT 24
Peak memory 210820 kb
Host smart-9c23487e-20b8-411b-9912-f33ca1773661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155240123 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4155240123
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1427556050
Short name T123
Test name
Test status
Simulation time 323715869089 ps
CPU time 174.62 seconds
Started Jul 05 04:46:10 PM PDT 24
Finished Jul 05 04:49:05 PM PDT 24
Peak memory 198304 kb
Host smart-d791c6d0-cc3d-4241-ba26-b4197b586ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427556050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1427556050
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1135892309
Short name T181
Test name
Test status
Simulation time 629065008 ps
CPU time 1.51 seconds
Started Jul 05 04:46:12 PM PDT 24
Finished Jul 05 04:46:14 PM PDT 24
Peak memory 196704 kb
Host smart-95ee765c-5078-485f-9b20-2c2c6b74ba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135892309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1135892309
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1201605898
Short name T196
Test name
Test status
Simulation time 8616178736 ps
CPU time 7.01 seconds
Started Jul 05 05:16:01 PM PDT 24
Finished Jul 05 05:16:09 PM PDT 24
Peak memory 198088 kb
Host smart-7dd77620-be98-4ebf-83ed-087189c83c20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201605898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1201605898
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3914957538
Short name T126
Test name
Test status
Simulation time 600784028 ps
CPU time 0.77 seconds
Started Jul 05 04:45:14 PM PDT 24
Finished Jul 05 04:45:16 PM PDT 24
Peak memory 196692 kb
Host smart-1cccd60a-21d7-44fe-848a-293a4f5b91af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914957538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3914957538
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2094192479
Short name T130
Test name
Test status
Simulation time 389045801 ps
CPU time 1.13 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:45:31 PM PDT 24
Peak memory 196744 kb
Host smart-c66f7ac0-b36f-41a4-9230-fd2449f493bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094192479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2094192479
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3650708574
Short name T176
Test name
Test status
Simulation time 254018266377 ps
CPU time 102.55 seconds
Started Jul 05 04:45:30 PM PDT 24
Finished Jul 05 04:47:13 PM PDT 24
Peak memory 191940 kb
Host smart-897bed2b-224d-4e6e-95ef-5172ae54a795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650708574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3650708574
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4134078820
Short name T112
Test name
Test status
Simulation time 587824175 ps
CPU time 1.43 seconds
Started Jul 05 04:45:31 PM PDT 24
Finished Jul 05 04:45:33 PM PDT 24
Peak memory 196768 kb
Host smart-36772a09-7ca3-4821-bf65-ddb4558bd67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134078820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4134078820
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3661903662
Short name T190
Test name
Test status
Simulation time 583447619 ps
CPU time 0.83 seconds
Started Jul 05 04:45:39 PM PDT 24
Finished Jul 05 04:45:40 PM PDT 24
Peak memory 196652 kb
Host smart-2785c834-cc10-4d2a-a677-1ce5f7d1e390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661903662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3661903662
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1397918787
Short name T194
Test name
Test status
Simulation time 574715476 ps
CPU time 1.38 seconds
Started Jul 05 04:45:45 PM PDT 24
Finished Jul 05 04:45:47 PM PDT 24
Peak memory 196672 kb
Host smart-e374da1a-4667-4b23-8d0b-1e376c14a52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397918787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1397918787
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1617420998
Short name T183
Test name
Test status
Simulation time 421804188 ps
CPU time 1.24 seconds
Started Jul 05 04:44:55 PM PDT 24
Finished Jul 05 04:44:57 PM PDT 24
Peak memory 196668 kb
Host smart-f6543313-0829-4799-995d-cc466cf2dc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617420998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1617420998
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3097959007
Short name T171
Test name
Test status
Simulation time 555942247 ps
CPU time 0.8 seconds
Started Jul 05 04:46:01 PM PDT 24
Finished Jul 05 04:46:04 PM PDT 24
Peak memory 196700 kb
Host smart-a9c17793-c9a1-48ab-9611-51eb2e5cb0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097959007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3097959007
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3418575588
Short name T148
Test name
Test status
Simulation time 364562479493 ps
CPU time 500.86 seconds
Started Jul 05 04:46:16 PM PDT 24
Finished Jul 05 04:54:38 PM PDT 24
Peak memory 192976 kb
Host smart-dd641c32-814d-4640-9d2b-38a70c44a0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418575588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3418575588
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.4153431218
Short name T168
Test name
Test status
Simulation time 429728819 ps
CPU time 1.27 seconds
Started Jul 05 04:44:55 PM PDT 24
Finished Jul 05 04:44:57 PM PDT 24
Peak memory 196664 kb
Host smart-7065110b-36b4-46de-9930-72633833c1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153431218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.4153431218
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2785086765
Short name T89
Test name
Test status
Simulation time 549397707 ps
CPU time 0.72 seconds
Started Jul 05 04:46:19 PM PDT 24
Finished Jul 05 04:46:20 PM PDT 24
Peak memory 196728 kb
Host smart-a1bb7989-e380-4ece-9775-a9596675428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785086765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2785086765
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1489209909
Short name T191
Test name
Test status
Simulation time 473495014 ps
CPU time 0.95 seconds
Started Jul 05 04:46:25 PM PDT 24
Finished Jul 05 04:46:27 PM PDT 24
Peak memory 196728 kb
Host smart-3395d6da-df08-440d-be2e-9db2f92e4e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489209909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1489209909
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3385198208
Short name T189
Test name
Test status
Simulation time 143943426191 ps
CPU time 35.87 seconds
Started Jul 05 04:46:25 PM PDT 24
Finished Jul 05 04:47:02 PM PDT 24
Peak memory 192444 kb
Host smart-255aef86-120e-4097-9c11-1fbd6824cd21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385198208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3385198208
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3904441558
Short name T172
Test name
Test status
Simulation time 569786753 ps
CPU time 1.53 seconds
Started Jul 05 04:45:02 PM PDT 24
Finished Jul 05 04:45:04 PM PDT 24
Peak memory 196688 kb
Host smart-ae4807cd-1ab4-44b7-8754-e34c1cf79aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904441558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3904441558
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2577375575
Short name T164
Test name
Test status
Simulation time 483799110 ps
CPU time 0.73 seconds
Started Jul 05 04:45:09 PM PDT 24
Finished Jul 05 04:45:10 PM PDT 24
Peak memory 196684 kb
Host smart-f0bd3353-66c0-4977-bd58-4a83aaac4ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577375575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2577375575
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2406019015
Short name T415
Test name
Test status
Simulation time 7149317470 ps
CPU time 4.76 seconds
Started Jul 05 05:16:04 PM PDT 24
Finished Jul 05 05:16:09 PM PDT 24
Peak memory 192236 kb
Host smart-a27273aa-5dcd-4fa2-98d0-f70498044ec1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406019015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2406019015
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3694008555
Short name T62
Test name
Test status
Simulation time 1411308107 ps
CPU time 1.15 seconds
Started Jul 05 05:16:02 PM PDT 24
Finished Jul 05 05:16:04 PM PDT 24
Peak memory 193032 kb
Host smart-0e1f0b86-652a-42ce-a6a9-4d1de59a8e5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694008555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3694008555
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1776040986
Short name T368
Test name
Test status
Simulation time 520485370 ps
CPU time 0.94 seconds
Started Jul 05 05:16:01 PM PDT 24
Finished Jul 05 05:16:03 PM PDT 24
Peak memory 197324 kb
Host smart-7b3836bb-a993-4604-b1d7-9c1aca610891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776040986 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1776040986
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4198841061
Short name T298
Test name
Test status
Simulation time 394088940 ps
CPU time 0.83 seconds
Started Jul 05 05:16:21 PM PDT 24
Finished Jul 05 05:16:24 PM PDT 24
Peak memory 192048 kb
Host smart-3322731c-b3e8-4949-a84e-92aa7722eeff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198841061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4198841061
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.18420234
Short name T371
Test name
Test status
Simulation time 407671126 ps
CPU time 0.67 seconds
Started Jul 05 05:16:00 PM PDT 24
Finished Jul 05 05:16:01 PM PDT 24
Peak memory 183768 kb
Host smart-dda7c12c-7b96-4df0-a73e-719f391ccfae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18420234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.18420234
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3861964484
Short name T311
Test name
Test status
Simulation time 333535652 ps
CPU time 0.91 seconds
Started Jul 05 05:16:01 PM PDT 24
Finished Jul 05 05:16:02 PM PDT 24
Peak memory 183676 kb
Host smart-62b2c90a-b016-4109-8463-f4d06fb4cfe4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861964484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3861964484
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3858561912
Short name T307
Test name
Test status
Simulation time 288818815 ps
CPU time 0.73 seconds
Started Jul 05 05:16:08 PM PDT 24
Finished Jul 05 05:16:09 PM PDT 24
Peak memory 183644 kb
Host smart-95a6b3bd-8279-499a-945d-335731c00ef9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858561912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3858561912
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.869315736
Short name T402
Test name
Test status
Simulation time 987518551 ps
CPU time 1.53 seconds
Started Jul 05 05:16:11 PM PDT 24
Finished Jul 05 05:16:14 PM PDT 24
Peak memory 193596 kb
Host smart-46157835-af24-4a68-bb62-765d6284542c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869315736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.869315736
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3296332791
Short name T284
Test name
Test status
Simulation time 464968933 ps
CPU time 1.6 seconds
Started Jul 05 05:15:59 PM PDT 24
Finished Jul 05 05:16:01 PM PDT 24
Peak memory 198452 kb
Host smart-4c90d97e-7f60-4e38-b7f1-62c9bd0edcae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296332791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3296332791
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.727744395
Short name T423
Test name
Test status
Simulation time 624637675 ps
CPU time 0.77 seconds
Started Jul 05 05:16:07 PM PDT 24
Finished Jul 05 05:16:08 PM PDT 24
Peak memory 193240 kb
Host smart-c28267ef-5516-4dc7-a797-8d2f9df94c17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727744395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.727744395
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1712655624
Short name T67
Test name
Test status
Simulation time 5647107805 ps
CPU time 6.2 seconds
Started Jul 05 05:16:03 PM PDT 24
Finished Jul 05 05:16:09 PM PDT 24
Peak memory 195680 kb
Host smart-aa905515-d419-44c9-8f8b-9de71303c422
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712655624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1712655624
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2421310940
Short name T408
Test name
Test status
Simulation time 698754685 ps
CPU time 1.48 seconds
Started Jul 05 05:16:03 PM PDT 24
Finished Jul 05 05:16:05 PM PDT 24
Peak memory 183700 kb
Host smart-b8349ca5-37fd-4268-9b83-28ce654d3c54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421310940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2421310940
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2235069613
Short name T424
Test name
Test status
Simulation time 465996777 ps
CPU time 1.4 seconds
Started Jul 05 05:16:03 PM PDT 24
Finished Jul 05 05:16:05 PM PDT 24
Peak memory 196980 kb
Host smart-b3b196f6-3d96-49ed-9e67-f15c94f840b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235069613 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2235069613
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2279612404
Short name T354
Test name
Test status
Simulation time 413075373 ps
CPU time 0.72 seconds
Started Jul 05 05:16:06 PM PDT 24
Finished Jul 05 05:16:07 PM PDT 24
Peak memory 193084 kb
Host smart-c3837a9a-6c70-4437-b39c-d8ca506c650f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279612404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2279612404
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2634942870
Short name T288
Test name
Test status
Simulation time 379521863 ps
CPU time 1.05 seconds
Started Jul 05 05:16:24 PM PDT 24
Finished Jul 05 05:16:27 PM PDT 24
Peak memory 183712 kb
Host smart-51cc3de8-f095-4848-ad60-87d79a8a2d57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634942870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2634942870
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3880003631
Short name T391
Test name
Test status
Simulation time 318948861 ps
CPU time 0.99 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 183684 kb
Host smart-86d88a5b-983c-4a42-9b88-dc06a7e2da89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880003631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3880003631
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.729303501
Short name T302
Test name
Test status
Simulation time 379550668 ps
CPU time 1.13 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 183744 kb
Host smart-d5131d61-b8fb-4beb-9cbc-96bd9d444ae3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729303501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.729303501
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2625439532
Short name T404
Test name
Test status
Simulation time 1289940986 ps
CPU time 2.18 seconds
Started Jul 05 05:16:06 PM PDT 24
Finished Jul 05 05:16:09 PM PDT 24
Peak memory 193008 kb
Host smart-de5273aa-1af1-4155-9549-694aef0a75ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625439532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2625439532
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4294474792
Short name T318
Test name
Test status
Simulation time 453810838 ps
CPU time 2.24 seconds
Started Jul 05 05:16:24 PM PDT 24
Finished Jul 05 05:16:28 PM PDT 24
Peak memory 198584 kb
Host smart-a74d0ef4-896c-42dc-b1f2-1c03bc92f5cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294474792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4294474792
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.649788502
Short name T420
Test name
Test status
Simulation time 4132907105 ps
CPU time 6.89 seconds
Started Jul 05 05:16:08 PM PDT 24
Finished Jul 05 05:16:16 PM PDT 24
Peak memory 198508 kb
Host smart-ffa0f8d2-1f71-4110-bb0f-088f219198cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649788502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.649788502
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3156089870
Short name T320
Test name
Test status
Simulation time 522619929 ps
CPU time 1.55 seconds
Started Jul 05 05:16:34 PM PDT 24
Finished Jul 05 05:16:37 PM PDT 24
Peak memory 196260 kb
Host smart-96e35a23-848e-47b7-8fea-d3c59224f278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156089870 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3156089870
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3897309443
Short name T326
Test name
Test status
Simulation time 409164811 ps
CPU time 0.69 seconds
Started Jul 05 05:16:14 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 193020 kb
Host smart-4e418304-5ff9-4caf-a90c-ed4b9ca7c9e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897309443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3897309443
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1496843560
Short name T293
Test name
Test status
Simulation time 475291211 ps
CPU time 1.21 seconds
Started Jul 05 05:16:16 PM PDT 24
Finished Jul 05 05:16:19 PM PDT 24
Peak memory 192872 kb
Host smart-022f5673-33a5-4b54-9774-414c969047d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496843560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1496843560
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4008018788
Short name T289
Test name
Test status
Simulation time 473602711 ps
CPU time 2.72 seconds
Started Jul 05 05:16:15 PM PDT 24
Finished Jul 05 05:16:19 PM PDT 24
Peak memory 198604 kb
Host smart-d226eea0-e9a4-4f6b-bb46-0b1c65b0cb05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008018788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4008018788
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2441995848
Short name T300
Test name
Test status
Simulation time 8617899841 ps
CPU time 11.49 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:35 PM PDT 24
Peak memory 197564 kb
Host smart-ae1a46a2-2083-45fd-9ef1-ddafedae8cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441995848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2441995848
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2063108487
Short name T406
Test name
Test status
Simulation time 560949246 ps
CPU time 1.47 seconds
Started Jul 05 05:16:14 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 197392 kb
Host smart-f74b3502-7b23-4aaa-8505-bfb4163247c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063108487 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2063108487
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2868610567
Short name T401
Test name
Test status
Simulation time 381086690 ps
CPU time 0.73 seconds
Started Jul 05 05:16:14 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 193020 kb
Host smart-aeb9a9c0-1d3c-4e70-879d-560ca59430e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868610567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2868610567
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1818225083
Short name T328
Test name
Test status
Simulation time 396191801 ps
CPU time 1.14 seconds
Started Jul 05 05:16:44 PM PDT 24
Finished Jul 05 05:16:46 PM PDT 24
Peak memory 183772 kb
Host smart-7cb7ab3e-0557-4f72-a6fa-475a9ea3f8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818225083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1818225083
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2326798165
Short name T395
Test name
Test status
Simulation time 1027257127 ps
CPU time 1.7 seconds
Started Jul 05 05:16:21 PM PDT 24
Finished Jul 05 05:16:25 PM PDT 24
Peak memory 183820 kb
Host smart-60c51b68-c19e-47a9-a2e3-09ee4caff7f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326798165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2326798165
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3198050218
Short name T348
Test name
Test status
Simulation time 439249709 ps
CPU time 1.73 seconds
Started Jul 05 05:16:09 PM PDT 24
Finished Jul 05 05:16:12 PM PDT 24
Peak memory 198532 kb
Host smart-63b2c8aa-f79b-4dc5-a733-b2a0a5b0633c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198050218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3198050218
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.603410018
Short name T34
Test name
Test status
Simulation time 8626251571 ps
CPU time 2.7 seconds
Started Jul 05 05:16:15 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 198184 kb
Host smart-33fcfe72-a16e-4aa3-b1fe-de5a36f163f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603410018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.603410018
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.959384925
Short name T361
Test name
Test status
Simulation time 396476293 ps
CPU time 1.13 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 195472 kb
Host smart-248a0b9e-9deb-4822-96dc-dd6f71037c31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959384925 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.959384925
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3597363275
Short name T65
Test name
Test status
Simulation time 312233667 ps
CPU time 1.1 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:16 PM PDT 24
Peak memory 194012 kb
Host smart-54243e9e-ede9-43ff-8d98-93e2d084e10c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597363275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3597363275
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2642942113
Short name T416
Test name
Test status
Simulation time 429299403 ps
CPU time 1.26 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 192968 kb
Host smart-7d7a4515-a14b-4c57-b6de-8187e0c25362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642942113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2642942113
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4013405304
Short name T329
Test name
Test status
Simulation time 2693437185 ps
CPU time 3.96 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:25 PM PDT 24
Peak memory 193964 kb
Host smart-0cf49672-6308-4912-a90d-58a9864b4e4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013405304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.4013405304
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2042145627
Short name T315
Test name
Test status
Simulation time 377044070 ps
CPU time 1.77 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 198624 kb
Host smart-4096a8ec-19c7-47f6-92ae-22a997e6fb6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042145627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2042145627
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.173729503
Short name T198
Test name
Test status
Simulation time 3936754766 ps
CPU time 3.97 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:28 PM PDT 24
Peak memory 196128 kb
Host smart-03d8afca-d9da-4266-ad79-1725115058d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173729503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.173729503
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3221244853
Short name T373
Test name
Test status
Simulation time 522162665 ps
CPU time 0.98 seconds
Started Jul 05 05:16:19 PM PDT 24
Finished Jul 05 05:16:21 PM PDT 24
Peak memory 195476 kb
Host smart-2aeb094e-f98d-43b9-b148-652b08470459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221244853 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3221244853
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2906614291
Short name T60
Test name
Test status
Simulation time 377846139 ps
CPU time 0.7 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:25 PM PDT 24
Peak memory 192084 kb
Host smart-2034a9db-fd68-465c-aa03-41c29951b4ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906614291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2906614291
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4272062536
Short name T294
Test name
Test status
Simulation time 321394992 ps
CPU time 0.69 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:25 PM PDT 24
Peak memory 192856 kb
Host smart-4ac282fd-739d-4782-a2f8-bd5533323628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272062536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4272062536
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2356337553
Short name T339
Test name
Test status
Simulation time 1537346937 ps
CPU time 1.06 seconds
Started Jul 05 05:16:18 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 191920 kb
Host smart-6338444c-6583-454f-88ef-e6e8557c2eda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356337553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2356337553
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1738822746
Short name T388
Test name
Test status
Simulation time 566931725 ps
CPU time 2.38 seconds
Started Jul 05 05:16:18 PM PDT 24
Finished Jul 05 05:16:22 PM PDT 24
Peak memory 198668 kb
Host smart-795eea29-8497-4976-8150-4f442a36db09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738822746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1738822746
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1570529575
Short name T335
Test name
Test status
Simulation time 9062654792 ps
CPU time 2.17 seconds
Started Jul 05 05:16:19 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 198308 kb
Host smart-6b98aa99-6377-486d-b5a4-998a6880cdae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570529575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1570529575
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2341032267
Short name T421
Test name
Test status
Simulation time 528470994 ps
CPU time 1.02 seconds
Started Jul 05 05:16:16 PM PDT 24
Finished Jul 05 05:16:19 PM PDT 24
Peak memory 196304 kb
Host smart-25aef7cb-1839-425d-9c75-cbf8f5b673af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341032267 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2341032267
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1751262836
Short name T363
Test name
Test status
Simulation time 406394798 ps
CPU time 0.84 seconds
Started Jul 05 05:16:23 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 192916 kb
Host smart-d4f7f6ad-4c69-4747-8b1b-5665b2688903
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751262836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1751262836
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2826181362
Short name T286
Test name
Test status
Simulation time 489576956 ps
CPU time 0.87 seconds
Started Jul 05 05:16:18 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 183772 kb
Host smart-60ef6814-4240-4ed5-b158-f32011300be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826181362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2826181362
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3108266961
Short name T332
Test name
Test status
Simulation time 2219195813 ps
CPU time 3.24 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:24 PM PDT 24
Peak memory 195036 kb
Host smart-9b7a9111-efc6-49ff-bae9-7d39faea3a6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108266961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3108266961
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4213780061
Short name T319
Test name
Test status
Simulation time 619188605 ps
CPU time 2 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 198528 kb
Host smart-35d1e488-2f0c-46b1-917e-47cfd336b109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213780061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.4213780061
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1692885463
Short name T389
Test name
Test status
Simulation time 8546985247 ps
CPU time 3.58 seconds
Started Jul 05 05:16:21 PM PDT 24
Finished Jul 05 05:16:27 PM PDT 24
Peak memory 198304 kb
Host smart-9f9f237b-504e-4f87-83eb-573b56a62bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692885463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1692885463
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.76551458
Short name T33
Test name
Test status
Simulation time 480116796 ps
CPU time 1.34 seconds
Started Jul 05 05:16:17 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 196640 kb
Host smart-7738b3e5-c902-4b96-b7e3-109818cd8721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76551458 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.76551458
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3015097811
Short name T345
Test name
Test status
Simulation time 604901213 ps
CPU time 0.65 seconds
Started Jul 05 05:16:23 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 192916 kb
Host smart-efc4feef-4528-4635-b7a8-88c2448ba0ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015097811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3015097811
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2910660896
Short name T364
Test name
Test status
Simulation time 277599154 ps
CPU time 1 seconds
Started Jul 05 05:16:21 PM PDT 24
Finished Jul 05 05:16:24 PM PDT 24
Peak memory 183764 kb
Host smart-d2f8c237-5f1b-4e10-bcb1-6c5b6284a15c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910660896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2910660896
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1894836905
Short name T333
Test name
Test status
Simulation time 2328314029 ps
CPU time 3.69 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 195140 kb
Host smart-5692cdf8-a767-45a9-bffc-6cf02162ec5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894836905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1894836905
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2975141787
Short name T297
Test name
Test status
Simulation time 379599337 ps
CPU time 1.73 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 198656 kb
Host smart-67fa6716-2a85-4aaf-b0a3-3b619ff17155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975141787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2975141787
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1913624774
Short name T411
Test name
Test status
Simulation time 556358612 ps
CPU time 1.03 seconds
Started Jul 05 05:16:17 PM PDT 24
Finished Jul 05 05:16:19 PM PDT 24
Peak memory 196028 kb
Host smart-936f637d-29f7-438a-9770-d090b643e32f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913624774 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1913624774
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4268049326
Short name T362
Test name
Test status
Simulation time 325098240 ps
CPU time 1.09 seconds
Started Jul 05 05:16:21 PM PDT 24
Finished Jul 05 05:16:24 PM PDT 24
Peak memory 194008 kb
Host smart-52b85eaf-89e7-48c4-9987-a0ed0222d2a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268049326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4268049326
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3563568152
Short name T301
Test name
Test status
Simulation time 382156296 ps
CPU time 1.02 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:22 PM PDT 24
Peak memory 183780 kb
Host smart-2e9cfe8a-a77b-4182-95ef-1762ba1ff7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563568152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3563568152
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3050159704
Short name T392
Test name
Test status
Simulation time 1834655593 ps
CPU time 2.6 seconds
Started Jul 05 05:16:18 PM PDT 24
Finished Jul 05 05:16:22 PM PDT 24
Peak memory 194776 kb
Host smart-a91e930b-a6d1-499d-b261-d775368c38de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050159704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3050159704
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2342730110
Short name T384
Test name
Test status
Simulation time 425521355 ps
CPU time 2.57 seconds
Started Jul 05 05:16:17 PM PDT 24
Finished Jul 05 05:16:21 PM PDT 24
Peak memory 198592 kb
Host smart-056f2347-ba1c-463a-adc7-254200342b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342730110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2342730110
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2896554112
Short name T341
Test name
Test status
Simulation time 9234695165 ps
CPU time 8.15 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:33 PM PDT 24
Peak memory 198112 kb
Host smart-6fe74385-9383-46f7-ad8b-93bf0e1648dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896554112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2896554112
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3288453626
Short name T372
Test name
Test status
Simulation time 567314401 ps
CPU time 1.08 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:25 PM PDT 24
Peak memory 196884 kb
Host smart-a16c3500-5c2c-418f-8d83-5abcdc8f332c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288453626 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3288453626
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2950226585
Short name T344
Test name
Test status
Simulation time 274396312 ps
CPU time 0.74 seconds
Started Jul 05 05:16:18 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 193016 kb
Host smart-6395b8d0-54c7-48a9-bc32-78947840592e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950226585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2950226585
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1660070971
Short name T346
Test name
Test status
Simulation time 490130924 ps
CPU time 1.23 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 192956 kb
Host smart-e986009f-21aa-4aa3-a4ca-3ea212b5ad7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660070971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1660070971
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3648109804
Short name T394
Test name
Test status
Simulation time 2000874154 ps
CPU time 3.09 seconds
Started Jul 05 05:16:19 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 192032 kb
Host smart-f3f85dcc-4020-4c1f-a080-924580a9f72c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648109804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3648109804
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2373682235
Short name T400
Test name
Test status
Simulation time 598750269 ps
CPU time 1.19 seconds
Started Jul 05 05:16:22 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 198352 kb
Host smart-7ad2059e-f470-40c3-bbf4-80c3a705dee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373682235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2373682235
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4284465615
Short name T36
Test name
Test status
Simulation time 4281278751 ps
CPU time 3.45 seconds
Started Jul 05 05:16:21 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 197792 kb
Host smart-34fa584a-2af4-45b1-b60a-7eb53e496389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284465615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.4284465615
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2045414372
Short name T337
Test name
Test status
Simulation time 441565030 ps
CPU time 0.78 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 195244 kb
Host smart-38a47af5-d56b-4dd0-96b5-2c5b93c43e4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045414372 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2045414372
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.673009366
Short name T334
Test name
Test status
Simulation time 328346142 ps
CPU time 0.7 seconds
Started Jul 05 05:16:23 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 193028 kb
Host smart-48743c28-8642-4f58-a9e1-b2224c7ba006
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673009366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.673009366
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.954807024
Short name T393
Test name
Test status
Simulation time 523938982 ps
CPU time 0.69 seconds
Started Jul 05 05:16:25 PM PDT 24
Finished Jul 05 05:16:28 PM PDT 24
Peak memory 192968 kb
Host smart-c0bbb0b1-845c-407f-9085-b85abedfc44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954807024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.954807024
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1317499053
Short name T71
Test name
Test status
Simulation time 1462802381 ps
CPU time 0.79 seconds
Started Jul 05 05:16:38 PM PDT 24
Finished Jul 05 05:16:40 PM PDT 24
Peak memory 193544 kb
Host smart-a6e4f761-31cc-4897-a3ca-5217fae3a0e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317499053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1317499053
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3629421570
Short name T350
Test name
Test status
Simulation time 897289877 ps
CPU time 2.74 seconds
Started Jul 05 05:16:19 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 198672 kb
Host smart-57339d20-4e6f-4aca-ae96-0e9894cc6e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629421570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3629421570
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3252609451
Short name T327
Test name
Test status
Simulation time 4403394028 ps
CPU time 7.03 seconds
Started Jul 05 05:16:21 PM PDT 24
Finished Jul 05 05:16:30 PM PDT 24
Peak memory 197704 kb
Host smart-d00e52ae-c2f9-416c-88c1-dcc77638e223
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252609451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3252609451
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.711882685
Short name T425
Test name
Test status
Simulation time 540571682 ps
CPU time 0.73 seconds
Started Jul 05 05:16:28 PM PDT 24
Finished Jul 05 05:16:31 PM PDT 24
Peak memory 196356 kb
Host smart-2af9faef-57ea-41f7-bd64-eff196b1a3af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711882685 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.711882685
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4254102844
Short name T70
Test name
Test status
Simulation time 375016458 ps
CPU time 0.67 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:28 PM PDT 24
Peak memory 191980 kb
Host smart-f7f1e786-65f2-4d98-bdd9-195c79b40554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254102844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4254102844
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2536766196
Short name T316
Test name
Test status
Simulation time 387619902 ps
CPU time 0.69 seconds
Started Jul 05 05:16:28 PM PDT 24
Finished Jul 05 05:16:31 PM PDT 24
Peak memory 183708 kb
Host smart-9742d072-53d3-4ff4-86f4-335bc3393b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536766196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2536766196
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3372598963
Short name T72
Test name
Test status
Simulation time 3143470182 ps
CPU time 2.47 seconds
Started Jul 05 05:16:24 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 184028 kb
Host smart-6c5bc62a-7caf-49f7-8ee4-436ccc64108b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372598963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3372598963
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2891132508
Short name T290
Test name
Test status
Simulation time 673609198 ps
CPU time 1.49 seconds
Started Jul 05 05:16:25 PM PDT 24
Finished Jul 05 05:16:28 PM PDT 24
Peak memory 198672 kb
Host smart-12d4b2c1-496e-4e5a-be5f-ea35e67ce091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891132508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2891132508
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.197277282
Short name T397
Test name
Test status
Simulation time 8643253359 ps
CPU time 4.12 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:32 PM PDT 24
Peak memory 198108 kb
Host smart-e692521b-7b19-4b09-a7d9-78461fec21b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197277282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.197277282
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2506910431
Short name T304
Test name
Test status
Simulation time 634297212 ps
CPU time 0.9 seconds
Started Jul 05 05:16:07 PM PDT 24
Finished Jul 05 05:16:08 PM PDT 24
Peak memory 193264 kb
Host smart-d85dc0f9-609f-4b1c-bff5-dc536af82010
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506910431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2506910431
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3060518658
Short name T399
Test name
Test status
Simulation time 7084118390 ps
CPU time 10.21 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:32 PM PDT 24
Peak memory 192236 kb
Host smart-e00ff9a2-4770-43f5-b42d-64e724b4cbcb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060518658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3060518658
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1341150993
Short name T57
Test name
Test status
Simulation time 910001047 ps
CPU time 0.91 seconds
Started Jul 05 05:16:04 PM PDT 24
Finished Jul 05 05:16:06 PM PDT 24
Peak memory 193032 kb
Host smart-f5d61527-eb8d-4d7e-9f68-00a9e092d9c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341150993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1341150993
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2924935870
Short name T405
Test name
Test status
Simulation time 607372890 ps
CPU time 1.47 seconds
Started Jul 05 05:16:34 PM PDT 24
Finished Jul 05 05:16:37 PM PDT 24
Peak memory 196576 kb
Host smart-de50efaa-686d-4f7c-bc3c-c6d390b7a5c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924935870 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2924935870
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2499406971
Short name T338
Test name
Test status
Simulation time 509353669 ps
CPU time 0.72 seconds
Started Jul 05 05:16:05 PM PDT 24
Finished Jul 05 05:16:06 PM PDT 24
Peak memory 192084 kb
Host smart-beee7b2d-7f44-4902-875d-06a39d9f4892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499406971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2499406971
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.553765811
Short name T280
Test name
Test status
Simulation time 586808681 ps
CPU time 0.63 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 183728 kb
Host smart-81e83bd9-a288-4a88-9681-6b10c607aa17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553765811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.553765811
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2500647035
Short name T355
Test name
Test status
Simulation time 507891723 ps
CPU time 0.85 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 183684 kb
Host smart-8aaf5547-9295-4d84-9dbc-4ac07ecda5e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500647035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2500647035
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.282781790
Short name T292
Test name
Test status
Simulation time 386792921 ps
CPU time 0.68 seconds
Started Jul 05 05:16:10 PM PDT 24
Finished Jul 05 05:16:11 PM PDT 24
Peak memory 183708 kb
Host smart-13830a11-c5dd-425f-b664-3e96b6940659
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282781790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.282781790
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.271930658
Short name T422
Test name
Test status
Simulation time 2274471671 ps
CPU time 2.21 seconds
Started Jul 05 05:16:34 PM PDT 24
Finished Jul 05 05:16:37 PM PDT 24
Peak memory 193680 kb
Host smart-59792be4-0b69-46ff-a5a9-4b17f88c36bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271930658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.271930658
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1288047075
Short name T410
Test name
Test status
Simulation time 436589750 ps
CPU time 2.17 seconds
Started Jul 05 05:16:04 PM PDT 24
Finished Jul 05 05:16:07 PM PDT 24
Peak memory 198540 kb
Host smart-8d96e1b6-253e-4d89-ae2c-a2c5fbc8c7b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288047075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1288047075
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1781637227
Short name T197
Test name
Test status
Simulation time 8907944351 ps
CPU time 2.86 seconds
Started Jul 05 05:16:05 PM PDT 24
Finished Jul 05 05:16:08 PM PDT 24
Peak memory 198172 kb
Host smart-51d821a7-47c2-42cf-a6d9-6fca1cc77dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781637227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1781637227
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3946837302
Short name T283
Test name
Test status
Simulation time 290362716 ps
CPU time 0.66 seconds
Started Jul 05 05:16:27 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 193000 kb
Host smart-1974a860-eba3-432d-be72-2dcafb50be5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946837302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3946837302
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.230208253
Short name T308
Test name
Test status
Simulation time 321737224 ps
CPU time 1.02 seconds
Started Jul 05 05:16:36 PM PDT 24
Finished Jul 05 05:16:38 PM PDT 24
Peak memory 192968 kb
Host smart-3872e522-5b54-4f88-867e-fa2d3d5e8ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230208253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.230208253
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.63305163
Short name T380
Test name
Test status
Simulation time 377815813 ps
CPU time 0.89 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 183760 kb
Host smart-7bfd2731-7b4e-4421-a7a5-356461f10b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63305163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.63305163
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3376886354
Short name T336
Test name
Test status
Simulation time 496611664 ps
CPU time 0.71 seconds
Started Jul 05 05:16:25 PM PDT 24
Finished Jul 05 05:16:28 PM PDT 24
Peak memory 183756 kb
Host smart-09148618-5ef3-433b-970a-c0dda56142e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376886354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3376886354
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2750846865
Short name T312
Test name
Test status
Simulation time 373965656 ps
CPU time 1.09 seconds
Started Jul 05 05:16:25 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 183644 kb
Host smart-6e544d5a-a11d-4063-92d4-1745448e9bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750846865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2750846865
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1779334236
Short name T287
Test name
Test status
Simulation time 576275954 ps
CPU time 0.58 seconds
Started Jul 05 05:16:39 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 183756 kb
Host smart-b0ec08ea-b6cf-4883-ad0e-bc91a3a79d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779334236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1779334236
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1757440134
Short name T357
Test name
Test status
Simulation time 404596775 ps
CPU time 1.12 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 183648 kb
Host smart-58cb397c-ab05-4d05-9d79-a9797a1efb6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757440134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1757440134
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3373419684
Short name T419
Test name
Test status
Simulation time 297425856 ps
CPU time 0.95 seconds
Started Jul 05 05:16:25 PM PDT 24
Finished Jul 05 05:16:27 PM PDT 24
Peak memory 192864 kb
Host smart-bced9edc-a709-4316-97ac-f35f10f1fa25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373419684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3373419684
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1692006956
Short name T382
Test name
Test status
Simulation time 336664889 ps
CPU time 0.64 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 183652 kb
Host smart-13d5daa3-d795-4c3a-be47-bcf8885ada52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692006956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1692006956
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2558867042
Short name T352
Test name
Test status
Simulation time 514527731 ps
CPU time 1.27 seconds
Started Jul 05 05:16:36 PM PDT 24
Finished Jul 05 05:16:38 PM PDT 24
Peak memory 183752 kb
Host smart-f60b40e1-4910-477c-9ff8-0a4be23bd825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558867042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2558867042
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1955469627
Short name T63
Test name
Test status
Simulation time 612164296 ps
CPU time 1.36 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:16 PM PDT 24
Peak memory 183820 kb
Host smart-e72b1402-17a8-4d27-811e-f87b5c7a96bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955469627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1955469627
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3696640582
Short name T37
Test name
Test status
Simulation time 6297767963 ps
CPU time 2.28 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 195616 kb
Host smart-5aa0b746-5c2d-4481-8dd0-366d8ee0891b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696640582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3696640582
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.696668811
Short name T369
Test name
Test status
Simulation time 1139029159 ps
CPU time 1.79 seconds
Started Jul 05 05:16:24 PM PDT 24
Finished Jul 05 05:16:28 PM PDT 24
Peak memory 183760 kb
Host smart-6944f2ed-359a-4836-9013-adb1b084eb05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696668811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.696668811
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1540999303
Short name T305
Test name
Test status
Simulation time 528913415 ps
CPU time 1.06 seconds
Started Jul 05 05:16:20 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 198432 kb
Host smart-1d000d58-039a-4e1c-93b3-12517a7d9dcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540999303 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1540999303
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4192291803
Short name T342
Test name
Test status
Simulation time 524428442 ps
CPU time 0.67 seconds
Started Jul 05 05:16:23 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 192988 kb
Host smart-59ab4ef8-7aeb-4aa1-88dd-72bfca263490
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192291803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4192291803
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3630243060
Short name T281
Test name
Test status
Simulation time 569430294 ps
CPU time 0.67 seconds
Started Jul 05 05:16:05 PM PDT 24
Finished Jul 05 05:16:06 PM PDT 24
Peak memory 183736 kb
Host smart-b6816f96-95d8-464b-a378-f8e6ba69a160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630243060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3630243060
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2511808465
Short name T306
Test name
Test status
Simulation time 400133665 ps
CPU time 1.05 seconds
Started Jul 05 05:16:07 PM PDT 24
Finished Jul 05 05:16:09 PM PDT 24
Peak memory 183664 kb
Host smart-e659dc6d-c9a8-409b-b9a9-836d659252bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511808465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2511808465
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2165248103
Short name T386
Test name
Test status
Simulation time 264689032 ps
CPU time 0.87 seconds
Started Jul 05 05:16:11 PM PDT 24
Finished Jul 05 05:16:13 PM PDT 24
Peak memory 183736 kb
Host smart-387e1a49-bfe6-437d-be22-9d3882525192
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165248103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2165248103
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1653581962
Short name T31
Test name
Test status
Simulation time 1441260584 ps
CPU time 2.45 seconds
Started Jul 05 05:16:06 PM PDT 24
Finished Jul 05 05:16:09 PM PDT 24
Peak memory 183708 kb
Host smart-1dffb6c2-7448-4065-ade2-3e74be54a425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653581962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1653581962
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2687157472
Short name T375
Test name
Test status
Simulation time 944994799 ps
CPU time 1.59 seconds
Started Jul 05 05:16:04 PM PDT 24
Finished Jul 05 05:16:06 PM PDT 24
Peak memory 198644 kb
Host smart-d1485698-5d30-4b3c-b5fe-9b30d120dc21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687157472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2687157472
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4211087144
Short name T398
Test name
Test status
Simulation time 4606098636 ps
CPU time 4.23 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:32 PM PDT 24
Peak memory 197908 kb
Host smart-fb8aae86-227e-4d5e-b4fd-d6e6796c34fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211087144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.4211087144
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1907922276
Short name T367
Test name
Test status
Simulation time 264378672 ps
CPU time 0.93 seconds
Started Jul 05 05:16:27 PM PDT 24
Finished Jul 05 05:16:30 PM PDT 24
Peak memory 192972 kb
Host smart-51c7aa21-d70a-4630-b5bb-6e72936af033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907922276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1907922276
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1231910814
Short name T310
Test name
Test status
Simulation time 400588869 ps
CPU time 1.14 seconds
Started Jul 05 05:16:28 PM PDT 24
Finished Jul 05 05:16:31 PM PDT 24
Peak memory 183760 kb
Host smart-b2ca6253-e165-44c9-8a1a-4d3487eb6ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231910814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1231910814
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.27378853
Short name T376
Test name
Test status
Simulation time 323126094 ps
CPU time 0.68 seconds
Started Jul 05 05:16:28 PM PDT 24
Finished Jul 05 05:16:30 PM PDT 24
Peak memory 183772 kb
Host smart-054ba83a-8f8d-4203-ab05-82caa1805dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27378853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.27378853
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.212867129
Short name T417
Test name
Test status
Simulation time 505677816 ps
CPU time 0.87 seconds
Started Jul 05 05:16:27 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 183696 kb
Host smart-821dd228-c671-4b95-a280-e12c0e1852f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212867129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.212867129
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.135487981
Short name T353
Test name
Test status
Simulation time 311095101 ps
CPU time 0.79 seconds
Started Jul 05 05:16:29 PM PDT 24
Finished Jul 05 05:16:31 PM PDT 24
Peak memory 192976 kb
Host smart-64f7ce1f-7a8d-4c16-9599-41af07e0ad36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135487981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.135487981
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.882753937
Short name T285
Test name
Test status
Simulation time 508363528 ps
CPU time 0.87 seconds
Started Jul 05 05:16:23 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 183708 kb
Host smart-6a66f5ad-7c53-4cde-89d2-55ed92b9bc71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882753937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.882753937
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3253629091
Short name T407
Test name
Test status
Simulation time 404183494 ps
CPU time 0.66 seconds
Started Jul 05 05:16:29 PM PDT 24
Finished Jul 05 05:16:31 PM PDT 24
Peak memory 183752 kb
Host smart-752350f0-d996-44a8-8a72-5639cc508159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253629091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3253629091
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1681017974
Short name T412
Test name
Test status
Simulation time 510120561 ps
CPU time 0.9 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 192976 kb
Host smart-02ea4d71-ae1a-4e5c-b836-5e323b8222b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681017974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1681017974
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3113534320
Short name T366
Test name
Test status
Simulation time 298232023 ps
CPU time 0.96 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 192968 kb
Host smart-770fe388-2536-433e-9bbb-21e94008d69c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113534320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3113534320
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1252292417
Short name T347
Test name
Test status
Simulation time 429028111 ps
CPU time 0.69 seconds
Started Jul 05 05:16:39 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 183756 kb
Host smart-c3bd6502-d57a-43b3-ace3-e27e8769ed0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252292417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1252292417
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1821439897
Short name T58
Test name
Test status
Simulation time 579837855 ps
CPU time 1.79 seconds
Started Jul 05 05:16:08 PM PDT 24
Finished Jul 05 05:16:11 PM PDT 24
Peak memory 183896 kb
Host smart-304eac91-8cd9-41d4-ad01-36d2f3940d08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821439897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1821439897
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2932936322
Short name T66
Test name
Test status
Simulation time 12241682435 ps
CPU time 5.2 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:19 PM PDT 24
Peak memory 192216 kb
Host smart-521e4a21-4206-4507-96f8-bf25f41da9c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932936322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2932936322
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3097323610
Short name T359
Test name
Test status
Simulation time 851156679 ps
CPU time 0.85 seconds
Started Jul 05 05:16:14 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 183804 kb
Host smart-49605413-ff8b-4ad3-8e55-6cee0d130256
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097323610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3097323610
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1348937389
Short name T387
Test name
Test status
Simulation time 422857825 ps
CPU time 1.24 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 196372 kb
Host smart-a57bcea9-4a04-4c29-bffa-c0329c8aad50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348937389 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1348937389
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.806172063
Short name T331
Test name
Test status
Simulation time 439384232 ps
CPU time 1.14 seconds
Started Jul 05 05:16:19 PM PDT 24
Finished Jul 05 05:16:21 PM PDT 24
Peak memory 193196 kb
Host smart-59676ee0-a494-43ae-ad56-dba7c20c1fd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806172063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.806172063
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.697822050
Short name T295
Test name
Test status
Simulation time 389297539 ps
CPU time 0.64 seconds
Started Jul 05 05:16:34 PM PDT 24
Finished Jul 05 05:16:36 PM PDT 24
Peak memory 183752 kb
Host smart-aaf33420-37ff-4a9a-812c-0317a400bb87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697822050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.697822050
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3078675988
Short name T379
Test name
Test status
Simulation time 334581604 ps
CPU time 0.87 seconds
Started Jul 05 05:16:17 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 183572 kb
Host smart-2d67ef21-61a2-478f-be2c-1bd2d5f6d08b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078675988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3078675988
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3143783840
Short name T360
Test name
Test status
Simulation time 416486457 ps
CPU time 1.18 seconds
Started Jul 05 05:16:14 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 183736 kb
Host smart-5b86677e-d5f6-4b9f-85fe-b7b96124583e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143783840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3143783840
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4076904009
Short name T370
Test name
Test status
Simulation time 1205340840 ps
CPU time 2.41 seconds
Started Jul 05 05:16:10 PM PDT 24
Finished Jul 05 05:16:13 PM PDT 24
Peak memory 193044 kb
Host smart-b7d1b575-5dd4-4436-ab20-f3816fd7ea95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076904009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4076904009
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2428226550
Short name T317
Test name
Test status
Simulation time 459624295 ps
CPU time 1.79 seconds
Started Jul 05 05:16:06 PM PDT 24
Finished Jul 05 05:16:08 PM PDT 24
Peak memory 198548 kb
Host smart-36869ccc-dd30-4130-bb59-b0b80a0463eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428226550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2428226550
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2460927230
Short name T324
Test name
Test status
Simulation time 8298914148 ps
CPU time 7.74 seconds
Started Jul 05 05:16:12 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 198364 kb
Host smart-b547f1b4-1a26-440a-be2b-fc7ee86e8608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460927230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2460927230
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.933638092
Short name T291
Test name
Test status
Simulation time 382370430 ps
CPU time 0.63 seconds
Started Jul 05 05:16:38 PM PDT 24
Finished Jul 05 05:16:39 PM PDT 24
Peak memory 192972 kb
Host smart-24c88a43-c466-4a11-9255-d014f6211fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933638092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.933638092
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3567425425
Short name T403
Test name
Test status
Simulation time 475767139 ps
CPU time 1.26 seconds
Started Jul 05 05:16:35 PM PDT 24
Finished Jul 05 05:16:38 PM PDT 24
Peak memory 192968 kb
Host smart-ed18a5fd-d146-475a-82dd-45e21e5b37cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567425425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3567425425
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2447015440
Short name T358
Test name
Test status
Simulation time 430617598 ps
CPU time 1.12 seconds
Started Jul 05 05:16:27 PM PDT 24
Finished Jul 05 05:16:30 PM PDT 24
Peak memory 183748 kb
Host smart-744a6de4-de74-4c9d-b1f8-4c31de626f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447015440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2447015440
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3845228053
Short name T396
Test name
Test status
Simulation time 444648585 ps
CPU time 0.82 seconds
Started Jul 05 05:16:36 PM PDT 24
Finished Jul 05 05:16:38 PM PDT 24
Peak memory 183752 kb
Host smart-b5aef8eb-6ae2-4898-9f71-4974f9060d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845228053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3845228053
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1776280557
Short name T322
Test name
Test status
Simulation time 424818467 ps
CPU time 0.68 seconds
Started Jul 05 05:16:27 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 192968 kb
Host smart-ac3354c1-7032-4fae-bf76-519484899c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776280557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1776280557
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2032984466
Short name T377
Test name
Test status
Simulation time 505257031 ps
CPU time 0.81 seconds
Started Jul 05 05:16:26 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 183732 kb
Host smart-884d0f59-2807-4170-9bd4-16b63605444a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032984466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2032984466
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2714395189
Short name T303
Test name
Test status
Simulation time 416370259 ps
CPU time 1.03 seconds
Started Jul 05 05:16:32 PM PDT 24
Finished Jul 05 05:16:34 PM PDT 24
Peak memory 192964 kb
Host smart-367554b4-becf-4f5a-9d93-59f42981c47a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714395189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2714395189
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.769388763
Short name T325
Test name
Test status
Simulation time 299790266 ps
CPU time 0.99 seconds
Started Jul 05 05:16:33 PM PDT 24
Finished Jul 05 05:16:35 PM PDT 24
Peak memory 183636 kb
Host smart-d58f105c-bac5-46eb-aff4-d219fca47c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769388763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.769388763
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2318144013
Short name T414
Test name
Test status
Simulation time 401764642 ps
CPU time 0.7 seconds
Started Jul 05 05:16:30 PM PDT 24
Finished Jul 05 05:16:32 PM PDT 24
Peak memory 183752 kb
Host smart-8033f7fb-2c1e-44d3-b919-80a736fb36b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318144013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2318144013
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1288507456
Short name T321
Test name
Test status
Simulation time 349849817 ps
CPU time 0.98 seconds
Started Jul 05 05:16:31 PM PDT 24
Finished Jul 05 05:16:33 PM PDT 24
Peak memory 192936 kb
Host smart-23cc12d1-871c-4271-96dd-58c240291d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288507456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1288507456
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.627005594
Short name T296
Test name
Test status
Simulation time 539394044 ps
CPU time 0.83 seconds
Started Jul 05 05:16:12 PM PDT 24
Finished Jul 05 05:16:15 PM PDT 24
Peak memory 195992 kb
Host smart-4738b016-9941-43fc-8de4-30751e018e21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627005594 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.627005594
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1459097465
Short name T61
Test name
Test status
Simulation time 315583169 ps
CPU time 0.68 seconds
Started Jul 05 05:16:08 PM PDT 24
Finished Jul 05 05:16:09 PM PDT 24
Peak memory 191980 kb
Host smart-d36c25b0-708e-41b6-9bc6-56177147db92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459097465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1459097465
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3257670610
Short name T381
Test name
Test status
Simulation time 423434660 ps
CPU time 1.14 seconds
Started Jul 05 05:16:12 PM PDT 24
Finished Jul 05 05:16:14 PM PDT 24
Peak memory 192916 kb
Host smart-960aaa98-f934-49f1-81c8-5158f161d0f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257670610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3257670610
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2435131276
Short name T69
Test name
Test status
Simulation time 2491340684 ps
CPU time 3.39 seconds
Started Jul 05 05:16:15 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 195200 kb
Host smart-437c7b36-11be-402d-97d8-dc89f2891500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435131276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2435131276
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2073934560
Short name T413
Test name
Test status
Simulation time 429284723 ps
CPU time 1.93 seconds
Started Jul 05 05:16:11 PM PDT 24
Finished Jul 05 05:16:14 PM PDT 24
Peak memory 198644 kb
Host smart-935846d5-d029-45c8-86b2-f03aa0846a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073934560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2073934560
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.215047548
Short name T390
Test name
Test status
Simulation time 4101969294 ps
CPU time 7.18 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:23 PM PDT 24
Peak memory 198112 kb
Host smart-a4d1b7ad-2dc7-4157-8233-48ecdb09a6b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215047548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.215047548
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3288329062
Short name T385
Test name
Test status
Simulation time 557945022 ps
CPU time 1.02 seconds
Started Jul 05 05:16:34 PM PDT 24
Finished Jul 05 05:16:36 PM PDT 24
Peak memory 197480 kb
Host smart-449e9405-c81a-4604-945a-928dccab58fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288329062 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3288329062
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1559752889
Short name T73
Test name
Test status
Simulation time 489540376 ps
CPU time 1.26 seconds
Started Jul 05 05:16:12 PM PDT 24
Finished Jul 05 05:16:15 PM PDT 24
Peak memory 193208 kb
Host smart-b6506d5a-e6cb-4d9b-b8a6-206b23f49b68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559752889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1559752889
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3635427345
Short name T313
Test name
Test status
Simulation time 479520790 ps
CPU time 0.87 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:15 PM PDT 24
Peak memory 183756 kb
Host smart-be47d759-38ca-4b82-a987-d03cd84c3710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635427345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3635427345
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1559046465
Short name T74
Test name
Test status
Simulation time 1259582585 ps
CPU time 1.23 seconds
Started Jul 05 05:16:14 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 193008 kb
Host smart-693285f3-e4ee-4d5d-8d37-0fc5f293897b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559046465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1559046465
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.261167118
Short name T282
Test name
Test status
Simulation time 1089947150 ps
CPU time 1.71 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 198544 kb
Host smart-2f7bea54-7b6e-43b8-a0c2-c700c199b7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261167118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.261167118
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.389851143
Short name T349
Test name
Test status
Simulation time 4733849269 ps
CPU time 2.78 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:18 PM PDT 24
Peak memory 197744 kb
Host smart-123713a8-7683-4669-9629-a0e7b8210d12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389851143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.389851143
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1453947065
Short name T340
Test name
Test status
Simulation time 428776957 ps
CPU time 1.36 seconds
Started Jul 05 05:16:12 PM PDT 24
Finished Jul 05 05:16:14 PM PDT 24
Peak memory 196432 kb
Host smart-f565a5e1-c3ac-45f3-838b-e9a5711bca7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453947065 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1453947065
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1704167850
Short name T59
Test name
Test status
Simulation time 479490869 ps
CPU time 1.36 seconds
Started Jul 05 05:16:15 PM PDT 24
Finished Jul 05 05:16:19 PM PDT 24
Peak memory 193244 kb
Host smart-3b32226c-2146-403b-8fc3-22632f217cb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704167850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1704167850
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2696087234
Short name T323
Test name
Test status
Simulation time 350370394 ps
CPU time 1.07 seconds
Started Jul 05 05:16:17 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 183640 kb
Host smart-93539452-1059-4bd1-a7c4-02c0bc343202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696087234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2696087234
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.18900140
Short name T409
Test name
Test status
Simulation time 1053254664 ps
CPU time 0.9 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:16 PM PDT 24
Peak memory 192936 kb
Host smart-73bf6b06-c8dd-4bb2-a88c-ed29dfe88b08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18900140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_t
imer_same_csr_outstanding.18900140
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4107500502
Short name T356
Test name
Test status
Simulation time 827949377 ps
CPU time 1.3 seconds
Started Jul 05 05:16:16 PM PDT 24
Finished Jul 05 05:16:19 PM PDT 24
Peak memory 198596 kb
Host smart-b615775b-da72-4cb1-8c79-8ab4a3075cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107500502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.4107500502
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2550420628
Short name T330
Test name
Test status
Simulation time 8874186947 ps
CPU time 2.19 seconds
Started Jul 05 05:16:15 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 198296 kb
Host smart-5c0ab249-c920-4a9d-ad2c-ab77436e2b8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550420628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2550420628
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2020749368
Short name T343
Test name
Test status
Simulation time 422059118 ps
CPU time 0.89 seconds
Started Jul 05 05:16:15 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 195520 kb
Host smart-de87f0a9-b842-4cd9-a26c-cc2a3942723a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020749368 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2020749368
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.28076252
Short name T309
Test name
Test status
Simulation time 485266132 ps
CPU time 0.66 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:16 PM PDT 24
Peak memory 193324 kb
Host smart-c4568559-0bfc-4d45-9428-dda18c57bb3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28076252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.28076252
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3869402818
Short name T365
Test name
Test status
Simulation time 354304070 ps
CPU time 1.1 seconds
Started Jul 05 05:16:09 PM PDT 24
Finished Jul 05 05:16:11 PM PDT 24
Peak memory 183752 kb
Host smart-cc144c24-38f8-4644-bba6-b9aba2d47892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869402818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3869402818
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.761498712
Short name T418
Test name
Test status
Simulation time 2186293969 ps
CPU time 2.76 seconds
Started Jul 05 05:16:11 PM PDT 24
Finished Jul 05 05:16:15 PM PDT 24
Peak memory 193816 kb
Host smart-6930dea1-e1d7-4497-907d-f21869eaa39c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761498712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.761498712
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.583715190
Short name T314
Test name
Test status
Simulation time 861728138 ps
CPU time 2.14 seconds
Started Jul 05 05:16:21 PM PDT 24
Finished Jul 05 05:16:26 PM PDT 24
Peak memory 198648 kb
Host smart-fc3f8f32-516b-475b-9df2-429f54da0339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583715190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.583715190
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2941644949
Short name T299
Test name
Test status
Simulation time 4644291087 ps
CPU time 6.77 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:21 PM PDT 24
Peak memory 198060 kb
Host smart-e9c82e08-eb02-4b34-a4db-df90bb3ebb75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941644949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2941644949
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1541140059
Short name T378
Test name
Test status
Simulation time 589321282 ps
CPU time 1.11 seconds
Started Jul 05 05:16:11 PM PDT 24
Finished Jul 05 05:16:13 PM PDT 24
Peak memory 196096 kb
Host smart-1fa5fb28-6491-4db3-9a7f-79cc91683d5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541140059 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1541140059
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.545012407
Short name T64
Test name
Test status
Simulation time 529103859 ps
CPU time 0.77 seconds
Started Jul 05 05:16:10 PM PDT 24
Finished Jul 05 05:16:12 PM PDT 24
Peak memory 194060 kb
Host smart-dd3e21fc-4eb6-4cd4-877a-5a1516c08d39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545012407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.545012407
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2703214394
Short name T383
Test name
Test status
Simulation time 507744814 ps
CPU time 0.7 seconds
Started Jul 05 05:16:14 PM PDT 24
Finished Jul 05 05:16:17 PM PDT 24
Peak memory 183712 kb
Host smart-232500af-5fb0-4a31-b4d5-b692d579ec86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703214394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2703214394
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.162564650
Short name T32
Test name
Test status
Simulation time 2004003268 ps
CPU time 3.2 seconds
Started Jul 05 05:16:13 PM PDT 24
Finished Jul 05 05:16:18 PM PDT 24
Peak memory 193944 kb
Host smart-18847c43-b2da-4feb-a68e-42ae66dd7cf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162564650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.162564650
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2726283930
Short name T351
Test name
Test status
Simulation time 350595495 ps
CPU time 1.25 seconds
Started Jul 05 05:16:16 PM PDT 24
Finished Jul 05 05:16:19 PM PDT 24
Peak memory 198644 kb
Host smart-f7b4dcb6-6776-4fe6-9374-4782e600ce9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726283930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2726283930
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3416741141
Short name T374
Test name
Test status
Simulation time 4100443561 ps
CPU time 3.98 seconds
Started Jul 05 05:16:14 PM PDT 24
Finished Jul 05 05:16:20 PM PDT 24
Peak memory 197940 kb
Host smart-c296a9fb-d774-4014-97c9-7594ead39a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416741141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3416741141
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2821249601
Short name T277
Test name
Test status
Simulation time 10821396820 ps
CPU time 16.92 seconds
Started Jul 05 04:44:45 PM PDT 24
Finished Jul 05 04:45:02 PM PDT 24
Peak memory 192212 kb
Host smart-cb389add-05dd-4c61-9904-b530dde75880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821249601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2821249601
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2563821226
Short name T20
Test name
Test status
Simulation time 8199413984 ps
CPU time 6.81 seconds
Started Jul 05 04:44:46 PM PDT 24
Finished Jul 05 04:44:54 PM PDT 24
Peak memory 215768 kb
Host smart-7b469278-cae9-4393-837c-4ac5db6ac3bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563821226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2563821226
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2540389655
Short name T273
Test name
Test status
Simulation time 515291283 ps
CPU time 0.94 seconds
Started Jul 05 04:44:46 PM PDT 24
Finished Jul 05 04:44:48 PM PDT 24
Peak memory 191844 kb
Host smart-4f992d61-0bad-47c4-8dfd-0235969fb2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540389655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2540389655
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.12870153
Short name T235
Test name
Test status
Simulation time 31867253713 ps
CPU time 10.16 seconds
Started Jul 05 04:44:46 PM PDT 24
Finished Jul 05 04:44:58 PM PDT 24
Peak memory 196968 kb
Host smart-589a753d-3937-4215-9296-577d645a528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12870153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.12870153
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.199612087
Short name T18
Test name
Test status
Simulation time 4521224326 ps
CPU time 3.79 seconds
Started Jul 05 04:44:44 PM PDT 24
Finished Jul 05 04:44:49 PM PDT 24
Peak memory 215692 kb
Host smart-920e8eeb-6e34-42cc-aa75-b9905fc414ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199612087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.199612087
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.545701148
Short name T261
Test name
Test status
Simulation time 563476436 ps
CPU time 0.84 seconds
Started Jul 05 04:44:45 PM PDT 24
Finished Jul 05 04:44:47 PM PDT 24
Peak memory 196712 kb
Host smart-aceaddb1-e967-435a-b3ce-fe0641de4cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545701148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.545701148
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2099756723
Short name T38
Test name
Test status
Simulation time 245972740465 ps
CPU time 334.37 seconds
Started Jul 05 04:44:45 PM PDT 24
Finished Jul 05 04:50:21 PM PDT 24
Peak memory 214200 kb
Host smart-c55f47c4-1889-4d82-95ca-4c7f54bd316b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099756723 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2099756723
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.620680187
Short name T47
Test name
Test status
Simulation time 54212206995 ps
CPU time 18.32 seconds
Started Jul 05 04:45:09 PM PDT 24
Finished Jul 05 04:45:27 PM PDT 24
Peak memory 191992 kb
Host smart-b4c13abb-f9c7-4347-b84e-5ac42026c347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620680187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.620680187
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1556021508
Short name T240
Test name
Test status
Simulation time 605016349 ps
CPU time 1.4 seconds
Started Jul 05 04:45:20 PM PDT 24
Finished Jul 05 04:45:22 PM PDT 24
Peak memory 196668 kb
Host smart-74881152-87aa-482b-a2c9-05a419343571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556021508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1556021508
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_jump.980444459
Short name T195
Test name
Test status
Simulation time 430224889 ps
CPU time 0.74 seconds
Started Jul 05 04:45:16 PM PDT 24
Finished Jul 05 04:45:17 PM PDT 24
Peak memory 196660 kb
Host smart-069233af-1019-4c87-b966-5bcd01c03f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980444459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.980444459
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.928261892
Short name T224
Test name
Test status
Simulation time 3714919392 ps
CPU time 3.21 seconds
Started Jul 05 04:45:14 PM PDT 24
Finished Jul 05 04:45:18 PM PDT 24
Peak memory 191864 kb
Host smart-d43f5367-ea3c-4cc4-b8fd-95371dae5c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928261892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.928261892
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1710691000
Short name T254
Test name
Test status
Simulation time 619261911 ps
CPU time 0.8 seconds
Started Jul 05 04:45:14 PM PDT 24
Finished Jul 05 04:45:16 PM PDT 24
Peak memory 191920 kb
Host smart-4158f6fe-7a40-4b12-8639-ccbdb527b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710691000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1710691000
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.38612589
Short name T236
Test name
Test status
Simulation time 23282519628 ps
CPU time 12.47 seconds
Started Jul 05 04:45:13 PM PDT 24
Finished Jul 05 04:45:26 PM PDT 24
Peak memory 196964 kb
Host smart-e04acce0-e612-4218-9cd0-6f447c0b1eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38612589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.38612589
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3317325110
Short name T231
Test name
Test status
Simulation time 612209044 ps
CPU time 0.85 seconds
Started Jul 05 04:45:13 PM PDT 24
Finished Jul 05 04:45:14 PM PDT 24
Peak memory 196596 kb
Host smart-9c4fa51a-ace1-41cd-9b29-025259fa9fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317325110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3317325110
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1464506493
Short name T174
Test name
Test status
Simulation time 532764182 ps
CPU time 1.26 seconds
Started Jul 05 04:45:14 PM PDT 24
Finished Jul 05 04:45:16 PM PDT 24
Peak memory 196800 kb
Host smart-08e2b452-530e-4bbf-a069-515eb91ec437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464506493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1464506493
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1483880689
Short name T272
Test name
Test status
Simulation time 10815419257 ps
CPU time 4.19 seconds
Started Jul 05 04:45:14 PM PDT 24
Finished Jul 05 04:45:19 PM PDT 24
Peak memory 191988 kb
Host smart-cbb85b5b-7b21-4b1c-825d-13e10d1d9b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483880689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1483880689
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3876770085
Short name T223
Test name
Test status
Simulation time 604921070 ps
CPU time 0.72 seconds
Started Jul 05 04:45:14 PM PDT 24
Finished Jul 05 04:45:16 PM PDT 24
Peak memory 196648 kb
Host smart-13c90fd2-3d98-414f-9e28-66c109847188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876770085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3876770085
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3540724255
Short name T241
Test name
Test status
Simulation time 16182680759 ps
CPU time 6.43 seconds
Started Jul 05 04:45:13 PM PDT 24
Finished Jul 05 04:45:20 PM PDT 24
Peak memory 191988 kb
Host smart-f132694c-741e-4b25-9c7c-455bc24f249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540724255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3540724255
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2644111510
Short name T211
Test name
Test status
Simulation time 476719507 ps
CPU time 0.74 seconds
Started Jul 05 04:45:16 PM PDT 24
Finished Jul 05 04:45:18 PM PDT 24
Peak memory 196692 kb
Host smart-20021294-bf02-41f6-b247-afb0f965c582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644111510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2644111510
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.949275179
Short name T204
Test name
Test status
Simulation time 11812234680 ps
CPU time 17.91 seconds
Started Jul 05 04:45:24 PM PDT 24
Finished Jul 05 04:45:43 PM PDT 24
Peak memory 196880 kb
Host smart-829e680a-6067-4457-b9e7-92566cf6dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949275179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.949275179
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2501141938
Short name T243
Test name
Test status
Simulation time 420286772 ps
CPU time 0.83 seconds
Started Jul 05 04:45:25 PM PDT 24
Finished Jul 05 04:45:26 PM PDT 24
Peak memory 196752 kb
Host smart-6a894593-3dd1-4cfc-8246-b5aa9370bfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501141938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2501141938
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.547366171
Short name T227
Test name
Test status
Simulation time 51975744977 ps
CPU time 66.33 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:46:37 PM PDT 24
Peak memory 191988 kb
Host smart-c66b3914-f17c-4beb-84a2-56e809d50154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547366171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.547366171
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2473419178
Short name T279
Test name
Test status
Simulation time 568167450 ps
CPU time 1.44 seconds
Started Jul 05 04:45:22 PM PDT 24
Finished Jul 05 04:45:24 PM PDT 24
Peak memory 196684 kb
Host smart-be7872c3-0daf-400b-8296-57f7147c90f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473419178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2473419178
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.596899323
Short name T214
Test name
Test status
Simulation time 4920315241 ps
CPU time 7.84 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:45:38 PM PDT 24
Peak memory 191880 kb
Host smart-24980440-030a-4fe6-9750-7c9e31ec7928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596899323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.596899323
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3203827151
Short name T53
Test name
Test status
Simulation time 367862854 ps
CPU time 0.69 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:45:30 PM PDT 24
Peak memory 196744 kb
Host smart-53f91c66-9f5e-43e3-aae2-56f44651ca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203827151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3203827151
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3154435100
Short name T256
Test name
Test status
Simulation time 18405344093 ps
CPU time 8.53 seconds
Started Jul 05 04:45:30 PM PDT 24
Finished Jul 05 04:45:39 PM PDT 24
Peak memory 191880 kb
Host smart-3550e265-b079-4651-9491-ab634d55e499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154435100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3154435100
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1467150642
Short name T9
Test name
Test status
Simulation time 564597608 ps
CPU time 0.96 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:45:31 PM PDT 24
Peak memory 196756 kb
Host smart-d5dc525c-ae48-453f-a545-174923c80f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467150642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1467150642
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1578852419
Short name T216
Test name
Test status
Simulation time 2221002237 ps
CPU time 2.14 seconds
Started Jul 05 04:45:31 PM PDT 24
Finished Jul 05 04:45:34 PM PDT 24
Peak memory 196616 kb
Host smart-2b363af9-5e75-42dd-a00b-4d1c2b2a199c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578852419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1578852419
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.49320062
Short name T200
Test name
Test status
Simulation time 370875507 ps
CPU time 0.72 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:45:31 PM PDT 24
Peak memory 191924 kb
Host smart-e0620782-f5e9-4eac-a900-043a491db19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49320062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.49320062
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1468664107
Short name T271
Test name
Test status
Simulation time 16646577799 ps
CPU time 20.1 seconds
Started Jul 05 04:44:45 PM PDT 24
Finished Jul 05 04:45:06 PM PDT 24
Peak memory 191976 kb
Host smart-f6684fb7-bc1a-4a37-ade4-177fb2da75cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468664107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1468664107
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3419261287
Short name T17
Test name
Test status
Simulation time 8040454556 ps
CPU time 6.61 seconds
Started Jul 05 04:44:54 PM PDT 24
Finished Jul 05 04:45:01 PM PDT 24
Peak memory 215744 kb
Host smart-8193ab9f-3879-410d-b3df-3832ae3f874d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419261287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3419261287
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2284669234
Short name T220
Test name
Test status
Simulation time 531366352 ps
CPU time 1.31 seconds
Started Jul 05 04:44:45 PM PDT 24
Finished Jul 05 04:44:48 PM PDT 24
Peak memory 191880 kb
Host smart-dc351cc9-2cdd-481b-a12f-c37c90786919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284669234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2284669234
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3131215111
Short name T267
Test name
Test status
Simulation time 61331098214 ps
CPU time 87.07 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:46:56 PM PDT 24
Peak memory 196920 kb
Host smart-7a8558c6-fe77-4268-819c-2da69df73196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131215111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3131215111
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3378173027
Short name T218
Test name
Test status
Simulation time 392169583 ps
CPU time 0.65 seconds
Started Jul 05 04:45:29 PM PDT 24
Finished Jul 05 04:45:30 PM PDT 24
Peak memory 191872 kb
Host smart-894b7753-0ea3-49e7-b8a3-3366875daf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378173027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3378173027
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.184676386
Short name T266
Test name
Test status
Simulation time 26029638077 ps
CPU time 19.44 seconds
Started Jul 05 04:45:37 PM PDT 24
Finished Jul 05 04:45:57 PM PDT 24
Peak memory 191924 kb
Host smart-13268313-5465-41d3-a96b-dcfe6fd9885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184676386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.184676386
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1394941863
Short name T44
Test name
Test status
Simulation time 486882787 ps
CPU time 1.26 seconds
Started Jul 05 04:45:39 PM PDT 24
Finished Jul 05 04:45:41 PM PDT 24
Peak memory 191856 kb
Host smart-79c0992e-08d8-4f3f-bf87-a9361f68e0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394941863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1394941863
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_jump.958070694
Short name T179
Test name
Test status
Simulation time 583239970 ps
CPU time 0.98 seconds
Started Jul 05 04:45:37 PM PDT 24
Finished Jul 05 04:45:38 PM PDT 24
Peak memory 196608 kb
Host smart-faf8aeef-a1bd-4193-a281-9c84671981c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958070694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.958070694
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3124484457
Short name T14
Test name
Test status
Simulation time 6126932990 ps
CPU time 8.52 seconds
Started Jul 05 04:45:39 PM PDT 24
Finished Jul 05 04:45:49 PM PDT 24
Peak memory 191988 kb
Host smart-ed120b90-b05c-4db4-82fd-b4cbcf0c5746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124484457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3124484457
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1888096936
Short name T205
Test name
Test status
Simulation time 542104015 ps
CPU time 0.79 seconds
Started Jul 05 04:45:43 PM PDT 24
Finished Jul 05 04:45:44 PM PDT 24
Peak memory 191884 kb
Host smart-c37b7f51-f417-46a8-b86a-3c9f7a4c7dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888096936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1888096936
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2626574263
Short name T242
Test name
Test status
Simulation time 9223083913 ps
CPU time 13.84 seconds
Started Jul 05 04:45:38 PM PDT 24
Finished Jul 05 04:45:52 PM PDT 24
Peak memory 191992 kb
Host smart-66d12d60-1379-486d-9725-3a02ae11cfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626574263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2626574263
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.817692121
Short name T27
Test name
Test status
Simulation time 371530053 ps
CPU time 1.21 seconds
Started Jul 05 04:45:39 PM PDT 24
Finished Jul 05 04:45:41 PM PDT 24
Peak memory 191920 kb
Host smart-56cb010d-5d11-43ee-9fb1-9d707f8f430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817692121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.817692121
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.819233739
Short name T233
Test name
Test status
Simulation time 4004012588 ps
CPU time 6.19 seconds
Started Jul 05 04:45:37 PM PDT 24
Finished Jul 05 04:45:44 PM PDT 24
Peak memory 191956 kb
Host smart-1ac75ad9-5909-471d-b700-10c8366f4688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819233739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.819233739
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1254594906
Short name T244
Test name
Test status
Simulation time 362564692 ps
CPU time 0.7 seconds
Started Jul 05 04:45:37 PM PDT 24
Finished Jul 05 04:45:38 PM PDT 24
Peak memory 196588 kb
Host smart-e236ecf8-9e55-4a27-a284-3890a715507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254594906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1254594906
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1914233881
Short name T49
Test name
Test status
Simulation time 55548772775 ps
CPU time 42.72 seconds
Started Jul 05 04:45:45 PM PDT 24
Finished Jul 05 04:46:29 PM PDT 24
Peak memory 191976 kb
Host smart-d826dd66-fb6e-49b9-b8f8-535f4d9d46a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914233881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1914233881
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2279771769
Short name T248
Test name
Test status
Simulation time 615798404 ps
CPU time 0.75 seconds
Started Jul 05 04:45:44 PM PDT 24
Finished Jul 05 04:45:46 PM PDT 24
Peak memory 191812 kb
Host smart-bb3fd62c-764c-42f5-8398-b1e38f44482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279771769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2279771769
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.792921340
Short name T229
Test name
Test status
Simulation time 59117082774 ps
CPU time 87.34 seconds
Started Jul 05 04:45:45 PM PDT 24
Finished Jul 05 04:47:14 PM PDT 24
Peak memory 196972 kb
Host smart-3e177626-7dd3-4004-8894-5c1738764e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792921340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.792921340
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2025085291
Short name T274
Test name
Test status
Simulation time 564215052 ps
CPU time 1.42 seconds
Started Jul 05 04:45:44 PM PDT 24
Finished Jul 05 04:45:46 PM PDT 24
Peak memory 191900 kb
Host smart-af43ff06-a081-4ba4-9b24-57bd4447eda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025085291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2025085291
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1770326216
Short name T263
Test name
Test status
Simulation time 26585543683 ps
CPU time 20.37 seconds
Started Jul 05 04:45:43 PM PDT 24
Finished Jul 05 04:46:05 PM PDT 24
Peak memory 191880 kb
Host smart-60448e57-572e-4ef0-8190-b681416a874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770326216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1770326216
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2277837151
Short name T225
Test name
Test status
Simulation time 600691571 ps
CPU time 0.64 seconds
Started Jul 05 04:45:46 PM PDT 24
Finished Jul 05 04:45:47 PM PDT 24
Peak memory 191900 kb
Host smart-ace52afd-fd09-4ee9-933d-e519214b6dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277837151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2277837151
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3067196228
Short name T24
Test name
Test status
Simulation time 2781757335 ps
CPU time 1.16 seconds
Started Jul 05 04:45:54 PM PDT 24
Finished Jul 05 04:45:56 PM PDT 24
Peak memory 191992 kb
Host smart-26a652e2-ee69-4cce-9491-ddc7cfb238ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067196228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3067196228
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1322230554
Short name T54
Test name
Test status
Simulation time 452492792 ps
CPU time 1.28 seconds
Started Jul 05 04:45:53 PM PDT 24
Finished Jul 05 04:45:56 PM PDT 24
Peak memory 191888 kb
Host smart-df6cdc68-9b9c-4a6d-a25b-6b0b7bba2300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322230554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1322230554
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2081727441
Short name T278
Test name
Test status
Simulation time 49582912331 ps
CPU time 63.89 seconds
Started Jul 05 04:45:53 PM PDT 24
Finished Jul 05 04:46:58 PM PDT 24
Peak memory 191972 kb
Host smart-a6be0fa1-c1f0-4656-9b19-42a8329c9d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081727441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2081727441
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4039002203
Short name T275
Test name
Test status
Simulation time 377612303 ps
CPU time 1.11 seconds
Started Jul 05 04:45:54 PM PDT 24
Finished Jul 05 04:45:56 PM PDT 24
Peak memory 191920 kb
Host smart-043de655-e30e-4e30-99f9-9d086bcecb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039002203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4039002203
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1486299214
Short name T199
Test name
Test status
Simulation time 56150721039 ps
CPU time 7.93 seconds
Started Jul 05 04:44:55 PM PDT 24
Finished Jul 05 04:45:04 PM PDT 24
Peak memory 191980 kb
Host smart-ea33ea00-6967-43e3-8b87-0e899a246395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486299214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1486299214
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3501000013
Short name T247
Test name
Test status
Simulation time 373303434 ps
CPU time 0.82 seconds
Started Jul 05 04:44:55 PM PDT 24
Finished Jul 05 04:44:57 PM PDT 24
Peak memory 191904 kb
Host smart-957251ed-3de6-4bd1-97fd-6dda14c3f25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501000013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3501000013
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3376878857
Short name T260
Test name
Test status
Simulation time 25069599234 ps
CPU time 11.03 seconds
Started Jul 05 04:45:51 PM PDT 24
Finished Jul 05 04:46:03 PM PDT 24
Peak memory 191868 kb
Host smart-b657689b-8c8c-4da6-91f5-71e64e2b4092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376878857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3376878857
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3837726833
Short name T262
Test name
Test status
Simulation time 553159211 ps
CPU time 1.45 seconds
Started Jul 05 04:45:54 PM PDT 24
Finished Jul 05 04:45:56 PM PDT 24
Peak memory 191900 kb
Host smart-8d80561f-ce16-4014-aa22-953730539595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837726833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3837726833
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.292333378
Short name T186
Test name
Test status
Simulation time 12010450538 ps
CPU time 94.72 seconds
Started Jul 05 04:46:00 PM PDT 24
Finished Jul 05 04:47:36 PM PDT 24
Peak memory 206816 kb
Host smart-a470c1e0-d3df-41e1-b4d8-eda6fa449b65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292333378 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.292333378
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.756025938
Short name T250
Test name
Test status
Simulation time 25055481942 ps
CPU time 10.68 seconds
Started Jul 05 04:46:01 PM PDT 24
Finished Jul 05 04:46:13 PM PDT 24
Peak memory 191940 kb
Host smart-bcc2e79e-4f8e-4d66-8c0d-55ff844afb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756025938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.756025938
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2687288667
Short name T208
Test name
Test status
Simulation time 440607228 ps
CPU time 0.79 seconds
Started Jul 05 04:46:02 PM PDT 24
Finished Jul 05 04:46:05 PM PDT 24
Peak memory 191808 kb
Host smart-6970d438-570f-46de-b0e7-58be92a8f38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687288667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2687288667
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1310657116
Short name T239
Test name
Test status
Simulation time 19320053259 ps
CPU time 7.93 seconds
Started Jul 05 04:46:07 PM PDT 24
Finished Jul 05 04:46:15 PM PDT 24
Peak memory 191952 kb
Host smart-5aa5fa38-52ba-46b5-bcf3-8926bde8d1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310657116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1310657116
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1852978236
Short name T207
Test name
Test status
Simulation time 372429650 ps
CPU time 1.1 seconds
Started Jul 05 04:46:02 PM PDT 24
Finished Jul 05 04:46:05 PM PDT 24
Peak memory 196652 kb
Host smart-23318fd8-d4b8-4258-8e5e-48875f2d6b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852978236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1852978236
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.691105559
Short name T257
Test name
Test status
Simulation time 11889284333 ps
CPU time 5.07 seconds
Started Jul 05 04:46:02 PM PDT 24
Finished Jul 05 04:46:09 PM PDT 24
Peak memory 191908 kb
Host smart-d9a1fad2-643e-4ac9-a2c5-beef28a8abad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691105559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.691105559
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.124285432
Short name T276
Test name
Test status
Simulation time 474707120 ps
CPU time 0.75 seconds
Started Jul 05 04:46:01 PM PDT 24
Finished Jul 05 04:46:04 PM PDT 24
Peak memory 191924 kb
Host smart-64424728-d3bf-42c8-9c19-0ba7634ae1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124285432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.124285432
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.421893562
Short name T48
Test name
Test status
Simulation time 18764193846 ps
CPU time 14.41 seconds
Started Jul 05 04:46:09 PM PDT 24
Finished Jul 05 04:46:24 PM PDT 24
Peak memory 191952 kb
Host smart-d1159778-23b1-403e-b61e-5168917f1445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421893562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.421893562
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4091172828
Short name T87
Test name
Test status
Simulation time 593771598 ps
CPU time 1 seconds
Started Jul 05 04:46:00 PM PDT 24
Finished Jul 05 04:46:03 PM PDT 24
Peak memory 191916 kb
Host smart-2ded88d8-9216-4ecc-aeac-524ac88c6ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091172828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4091172828
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1783458214
Short name T40
Test name
Test status
Simulation time 57965725507 ps
CPU time 227.44 seconds
Started Jul 05 04:46:01 PM PDT 24
Finished Jul 05 04:49:50 PM PDT 24
Peak memory 198876 kb
Host smart-0d213dd5-7ebd-4eb1-98cf-890e61bfece0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783458214 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1783458214
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.298268336
Short name T28
Test name
Test status
Simulation time 2772969036 ps
CPU time 1.26 seconds
Started Jul 05 04:46:07 PM PDT 24
Finished Jul 05 04:46:09 PM PDT 24
Peak memory 191952 kb
Host smart-18dcee76-3b1e-4dc7-9178-a440da9b49bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298268336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.298268336
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.4220442320
Short name T215
Test name
Test status
Simulation time 499082671 ps
CPU time 1.29 seconds
Started Jul 05 04:46:09 PM PDT 24
Finished Jul 05 04:46:11 PM PDT 24
Peak memory 191880 kb
Host smart-aec0c6a2-8eed-4b36-94c9-ff3da0965d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220442320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.4220442320
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1588982724
Short name T187
Test name
Test status
Simulation time 270672037834 ps
CPU time 89.32 seconds
Started Jul 05 04:46:11 PM PDT 24
Finished Jul 05 04:47:41 PM PDT 24
Peak memory 193080 kb
Host smart-864c8365-0a62-4c3f-baf2-ff7094dce825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588982724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1588982724
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1930889665
Short name T255
Test name
Test status
Simulation time 30225643429 ps
CPU time 12.12 seconds
Started Jul 05 04:46:07 PM PDT 24
Finished Jul 05 04:46:20 PM PDT 24
Peak memory 191856 kb
Host smart-3159ab2d-0ed4-45fa-9c60-9814dd9a49a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930889665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1930889665
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3462496053
Short name T206
Test name
Test status
Simulation time 474234540 ps
CPU time 0.75 seconds
Started Jul 05 04:46:12 PM PDT 24
Finished Jul 05 04:46:13 PM PDT 24
Peak memory 191900 kb
Host smart-98655076-21fe-4abc-bf38-0c5e911973d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462496053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3462496053
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3824403351
Short name T269
Test name
Test status
Simulation time 40303639052 ps
CPU time 14.03 seconds
Started Jul 05 04:46:09 PM PDT 24
Finished Jul 05 04:46:24 PM PDT 24
Peak memory 196876 kb
Host smart-870b1fed-40ba-4a1d-bdc9-7116564491f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824403351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3824403351
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1260735447
Short name T221
Test name
Test status
Simulation time 552577549 ps
CPU time 0.83 seconds
Started Jul 05 04:46:08 PM PDT 24
Finished Jul 05 04:46:10 PM PDT 24
Peak memory 191868 kb
Host smart-b4248918-6e4b-47ab-8208-a5728c3f0c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260735447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1260735447
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1812916943
Short name T180
Test name
Test status
Simulation time 207863488135 ps
CPU time 284.47 seconds
Started Jul 05 04:46:06 PM PDT 24
Finished Jul 05 04:50:51 PM PDT 24
Peak memory 192212 kb
Host smart-9e438c40-107b-4f93-b584-b952a00a2da9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812916943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1812916943
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2227281512
Short name T232
Test name
Test status
Simulation time 12404992254 ps
CPU time 5.29 seconds
Started Jul 05 04:46:09 PM PDT 24
Finished Jul 05 04:46:15 PM PDT 24
Peak memory 191876 kb
Host smart-ab9b7311-6b28-4fc9-bd35-5fe95e289a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227281512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2227281512
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3591641687
Short name T4
Test name
Test status
Simulation time 604929942 ps
CPU time 0.92 seconds
Started Jul 05 04:46:07 PM PDT 24
Finished Jul 05 04:46:08 PM PDT 24
Peak memory 196692 kb
Host smart-f9b239c4-9c69-4b65-9f3f-cce2351acef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591641687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3591641687
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.936892756
Short name T193
Test name
Test status
Simulation time 418544722 ps
CPU time 0.77 seconds
Started Jul 05 04:46:17 PM PDT 24
Finished Jul 05 04:46:19 PM PDT 24
Peak memory 196804 kb
Host smart-aeedad08-ec5e-4994-af03-9fb7409faeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936892756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.936892756
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2044346887
Short name T265
Test name
Test status
Simulation time 23111154798 ps
CPU time 36.9 seconds
Started Jul 05 04:46:07 PM PDT 24
Finished Jul 05 04:46:44 PM PDT 24
Peak memory 191828 kb
Host smart-ca388abf-3d31-4b6c-a657-e00aa70e67af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044346887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2044346887
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.848923549
Short name T22
Test name
Test status
Simulation time 604563240 ps
CPU time 1.48 seconds
Started Jul 05 04:46:17 PM PDT 24
Finished Jul 05 04:46:19 PM PDT 24
Peak memory 196696 kb
Host smart-d58baf28-38cd-4e06-8f10-3ed6e36e178b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848923549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.848923549
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.720093610
Short name T252
Test name
Test status
Simulation time 5689410332 ps
CPU time 9.07 seconds
Started Jul 05 04:44:50 PM PDT 24
Finished Jul 05 04:45:00 PM PDT 24
Peak memory 196972 kb
Host smart-eb485d7c-38f3-43fd-899f-97475d64f115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720093610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.720093610
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1466634692
Short name T19
Test name
Test status
Simulation time 3796301433 ps
CPU time 5.84 seconds
Started Jul 05 04:45:03 PM PDT 24
Finished Jul 05 04:45:10 PM PDT 24
Peak memory 215324 kb
Host smart-b1ae1b17-7417-4b99-9423-a9f352227cb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466634692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1466634692
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.267863928
Short name T203
Test name
Test status
Simulation time 480397470 ps
CPU time 1.23 seconds
Started Jul 05 04:44:56 PM PDT 24
Finished Jul 05 04:44:57 PM PDT 24
Peak memory 191920 kb
Host smart-f03d308b-d738-40f4-adeb-e03f99ae082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267863928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.267863928
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2107396195
Short name T212
Test name
Test status
Simulation time 24647145005 ps
CPU time 9.95 seconds
Started Jul 05 04:46:19 PM PDT 24
Finished Jul 05 04:46:29 PM PDT 24
Peak memory 197000 kb
Host smart-c4601b67-550e-4fb5-8a2b-9c53ee903d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107396195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2107396195
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.343580965
Short name T230
Test name
Test status
Simulation time 551103930 ps
CPU time 0.8 seconds
Started Jul 05 04:46:21 PM PDT 24
Finished Jul 05 04:46:22 PM PDT 24
Peak memory 191848 kb
Host smart-c2ec239f-2cdb-4972-bd2f-43688d05ec0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343580965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.343580965
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.961035805
Short name T251
Test name
Test status
Simulation time 18460524370 ps
CPU time 7.45 seconds
Started Jul 05 04:46:17 PM PDT 24
Finished Jul 05 04:46:25 PM PDT 24
Peak memory 196924 kb
Host smart-b2879042-1fc6-48b7-8a2d-d438633df778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961035805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.961035805
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.4120344309
Short name T217
Test name
Test status
Simulation time 459396282 ps
CPU time 1.08 seconds
Started Jul 05 04:46:18 PM PDT 24
Finished Jul 05 04:46:20 PM PDT 24
Peak memory 191808 kb
Host smart-26db01fc-7590-4966-8433-e9ff44c54542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120344309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4120344309
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2878610867
Short name T226
Test name
Test status
Simulation time 14767064133 ps
CPU time 21.65 seconds
Started Jul 05 04:46:17 PM PDT 24
Finished Jul 05 04:46:39 PM PDT 24
Peak memory 191876 kb
Host smart-4174d7a4-f9e8-48ff-8130-63f3f16df0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878610867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2878610867
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2605343867
Short name T234
Test name
Test status
Simulation time 380859852 ps
CPU time 0.73 seconds
Started Jul 05 04:46:17 PM PDT 24
Finished Jul 05 04:46:19 PM PDT 24
Peak memory 196764 kb
Host smart-33bb1a76-6b29-409b-a424-5eec4b7b2e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605343867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2605343867
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.95665726
Short name T264
Test name
Test status
Simulation time 18240659802 ps
CPU time 6.82 seconds
Started Jul 05 04:46:18 PM PDT 24
Finished Jul 05 04:46:25 PM PDT 24
Peak memory 191888 kb
Host smart-bbc0989a-182b-4561-a9a1-082c080b0ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95665726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.95665726
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.411132165
Short name T253
Test name
Test status
Simulation time 611478035 ps
CPU time 1.53 seconds
Started Jul 05 04:46:21 PM PDT 24
Finished Jul 05 04:46:23 PM PDT 24
Peak memory 191844 kb
Host smart-b610bfb9-2e6a-42f9-85fd-f69ad0b209da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411132165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.411132165
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.4070712694
Short name T219
Test name
Test status
Simulation time 4215496764 ps
CPU time 7.3 seconds
Started Jul 05 04:46:28 PM PDT 24
Finished Jul 05 04:46:36 PM PDT 24
Peak memory 191952 kb
Host smart-ea8e9ca3-4bdc-4379-be1b-122ce7687c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070712694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.4070712694
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3482126098
Short name T8
Test name
Test status
Simulation time 448557529 ps
CPU time 0.75 seconds
Started Jul 05 04:46:28 PM PDT 24
Finished Jul 05 04:46:30 PM PDT 24
Peak memory 191900 kb
Host smart-1c5fa53a-d639-4540-91e6-4c17a16719bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482126098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3482126098
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3353090888
Short name T222
Test name
Test status
Simulation time 3812639808 ps
CPU time 5.75 seconds
Started Jul 05 04:46:24 PM PDT 24
Finished Jul 05 04:46:31 PM PDT 24
Peak memory 191972 kb
Host smart-4650e623-0726-4f4d-b559-8d054bb42495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353090888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3353090888
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3137190364
Short name T5
Test name
Test status
Simulation time 392630535 ps
CPU time 1.15 seconds
Started Jul 05 04:46:26 PM PDT 24
Finished Jul 05 04:46:28 PM PDT 24
Peak memory 196684 kb
Host smart-0f0a05a9-9a39-4bbd-b766-717c2796f970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137190364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3137190364
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3564581538
Short name T170
Test name
Test status
Simulation time 428533078 ps
CPU time 0.6 seconds
Started Jul 05 04:46:25 PM PDT 24
Finished Jul 05 04:46:26 PM PDT 24
Peak memory 196732 kb
Host smart-0e2127b4-f972-434f-8190-6e8a8a20555f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564581538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3564581538
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.908108114
Short name T258
Test name
Test status
Simulation time 8380744260 ps
CPU time 3.55 seconds
Started Jul 05 04:46:24 PM PDT 24
Finished Jul 05 04:46:28 PM PDT 24
Peak memory 191988 kb
Host smart-24a217e1-7799-4650-aeb6-d1429c9ab14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908108114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.908108114
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2148133911
Short name T201
Test name
Test status
Simulation time 415241825 ps
CPU time 1.2 seconds
Started Jul 05 04:46:26 PM PDT 24
Finished Jul 05 04:46:28 PM PDT 24
Peak memory 191924 kb
Host smart-b0d0434e-f111-4e25-aee9-6839eb98da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148133911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2148133911
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.741820727
Short name T237
Test name
Test status
Simulation time 18534139377 ps
CPU time 15.07 seconds
Started Jul 05 04:46:36 PM PDT 24
Finished Jul 05 04:46:53 PM PDT 24
Peak memory 191824 kb
Host smart-617c4cde-12be-49fe-a137-3605b0f0ef97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741820727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.741820727
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1417536959
Short name T238
Test name
Test status
Simulation time 361970506 ps
CPU time 1.12 seconds
Started Jul 05 04:46:26 PM PDT 24
Finished Jul 05 04:46:28 PM PDT 24
Peak memory 191900 kb
Host smart-fd941f03-b645-45c2-a8f4-3e006ddb4f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417536959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1417536959
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2575655104
Short name T249
Test name
Test status
Simulation time 13289500824 ps
CPU time 2.62 seconds
Started Jul 05 04:46:33 PM PDT 24
Finished Jul 05 04:46:36 PM PDT 24
Peak memory 191976 kb
Host smart-ce764f66-ad7f-4dca-9fda-84fab82646e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575655104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2575655104
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2607683607
Short name T26
Test name
Test status
Simulation time 556845530 ps
CPU time 0.79 seconds
Started Jul 05 04:46:35 PM PDT 24
Finished Jul 05 04:46:37 PM PDT 24
Peak memory 196752 kb
Host smart-1eb80c1b-26f9-4c41-af46-ff7416d1241b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607683607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2607683607
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2165507952
Short name T268
Test name
Test status
Simulation time 11453683431 ps
CPU time 9.14 seconds
Started Jul 05 04:46:37 PM PDT 24
Finished Jul 05 04:46:47 PM PDT 24
Peak memory 191916 kb
Host smart-2e92ebcc-cf79-4ac4-b31d-6f3a797b417d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165507952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2165507952
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3060249825
Short name T209
Test name
Test status
Simulation time 426763877 ps
CPU time 1.15 seconds
Started Jul 05 04:46:34 PM PDT 24
Finished Jul 05 04:46:36 PM PDT 24
Peak memory 191880 kb
Host smart-76fd1870-7453-427d-8c78-f3f1d83f3675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060249825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3060249825
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.762098180
Short name T228
Test name
Test status
Simulation time 15799734121 ps
CPU time 24.47 seconds
Started Jul 05 04:45:02 PM PDT 24
Finished Jul 05 04:45:26 PM PDT 24
Peak memory 191980 kb
Host smart-e32e9c88-5d46-4adc-8af2-89d72f728a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762098180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.762098180
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2601207261
Short name T12
Test name
Test status
Simulation time 622164400 ps
CPU time 0.77 seconds
Started Jul 05 04:44:59 PM PDT 24
Finished Jul 05 04:45:01 PM PDT 24
Peak memory 191924 kb
Host smart-24f59fed-6b2e-4e01-b859-3044e5afa171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601207261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2601207261
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1342638325
Short name T202
Test name
Test status
Simulation time 17971864274 ps
CPU time 7.04 seconds
Started Jul 05 04:45:01 PM PDT 24
Finished Jul 05 04:45:09 PM PDT 24
Peak memory 196980 kb
Host smart-4b7478c0-0070-4e07-b1e1-b06e9c448b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342638325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1342638325
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.82833353
Short name T213
Test name
Test status
Simulation time 458917137 ps
CPU time 0.93 seconds
Started Jul 05 04:45:00 PM PDT 24
Finished Jul 05 04:45:01 PM PDT 24
Peak memory 191828 kb
Host smart-cd59d648-e707-4b53-8f71-0e885642efcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82833353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.82833353
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3058440268
Short name T182
Test name
Test status
Simulation time 406941029 ps
CPU time 1.24 seconds
Started Jul 05 04:45:09 PM PDT 24
Finished Jul 05 04:45:11 PM PDT 24
Peak memory 196708 kb
Host smart-a0134b46-0cba-43ea-8df8-34495073a67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058440268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3058440268
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2432455834
Short name T246
Test name
Test status
Simulation time 9779703687 ps
CPU time 13.81 seconds
Started Jul 05 04:45:11 PM PDT 24
Finished Jul 05 04:45:25 PM PDT 24
Peak memory 196864 kb
Host smart-8284c9ca-7bd1-4a76-b818-6d901cbdcd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432455834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2432455834
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3879813462
Short name T259
Test name
Test status
Simulation time 594215328 ps
CPU time 0.64 seconds
Started Jul 05 04:45:13 PM PDT 24
Finished Jul 05 04:45:15 PM PDT 24
Peak memory 191888 kb
Host smart-88a1338e-c982-43ed-a32f-b372eeb5116b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879813462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3879813462
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1682319346
Short name T21
Test name
Test status
Simulation time 530908050 ps
CPU time 0.96 seconds
Started Jul 05 04:45:10 PM PDT 24
Finished Jul 05 04:45:11 PM PDT 24
Peak memory 196652 kb
Host smart-9afdace5-a616-48fc-b636-782dfeb323d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682319346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1682319346
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2297184931
Short name T245
Test name
Test status
Simulation time 53821022627 ps
CPU time 19.5 seconds
Started Jul 05 04:45:15 PM PDT 24
Finished Jul 05 04:45:35 PM PDT 24
Peak memory 191948 kb
Host smart-ae94eec2-5bd3-49f4-a792-63a5fa160a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297184931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2297184931
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2934251510
Short name T270
Test name
Test status
Simulation time 368952093 ps
CPU time 0.84 seconds
Started Jul 05 04:45:07 PM PDT 24
Finished Jul 05 04:45:09 PM PDT 24
Peak memory 196972 kb
Host smart-00104fe1-937c-42f1-b56f-4f8799dab60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934251510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2934251510
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.922612501
Short name T46
Test name
Test status
Simulation time 31642168761 ps
CPU time 11.42 seconds
Started Jul 05 04:45:07 PM PDT 24
Finished Jul 05 04:45:19 PM PDT 24
Peak memory 192212 kb
Host smart-2fa3703e-542b-4d02-b28c-04317f608fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922612501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.922612501
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2904291437
Short name T210
Test name
Test status
Simulation time 418135567 ps
CPU time 1.13 seconds
Started Jul 05 04:45:10 PM PDT 24
Finished Jul 05 04:45:12 PM PDT 24
Peak memory 191884 kb
Host smart-51996552-a4b9-4bb6-acd2-c3a130b76d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904291437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2904291437
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3908523104
Short name T1
Test name
Test status
Simulation time 100814299489 ps
CPU time 37.98 seconds
Started Jul 05 04:45:06 PM PDT 24
Finished Jul 05 04:45:45 PM PDT 24
Peak memory 192952 kb
Host smart-7d650930-9ea8-4559-8c3a-e542ac0575f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908523104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3908523104
Directory /workspace/9.aon_timer_stress_all/latest
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