Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	31131	1		T1	1375		T3	203		T5	11
bark[1]	204	1		T171	14		T101	21		T112	30
bark[2]	1343	1		T20	21		T42	277		T179	14
bark[3]	328	1		T1	21		T19	42		T40	26
bark[4]	581	1		T2	14		T15	234		T41	26
bark[5]	271	1		T77	21		T43	172		T111	14
bark[6]	736	1		T1	68		T3	21		T155	21
bark[7]	438	1		T1	43		T80	21		T112	23
bark[8]	901	1		T27	52		T40	26		T41	584
bark[9]	772	1		T41	7		T118	21		T155	49
bark[10]	789	1		T19	21		T20	26		T40	150
bark[11]	421	1		T1	21		T10	14		T31	124
bark[12]	253	1		T42	52		T125	14		T53	21
bark[13]	366	1		T25	14		T148	47		T128	14
bark[14]	732	1		T23	14		T20	26		T131	26
bark[15]	213	1		T1	26		T3	35		T134	14
bark[16]	394	1		T1	47		T77	31		T118	21
bark[17]	435	1		T3	21		T12	56		T79	14
bark[18]	830	1		T92	14		T172	21		T50	162
bark[19]	272	1		T28	26		T118	57		T44	21
bark[20]	863	1		T20	21		T159	14		T160	26
bark[21]	1278	1		T32	14		T27	208		T40	21
bark[22]	1207	1		T31	21		T20	30		T28	224
bark[23]	310	1		T1	21		T27	180		T43	21
bark[24]	427	1		T12	35		T24	14		T152	21
bark[25]	474	1		T11	14		T75	14		T77	51
bark[26]	489	1		T12	26		T95	21		T153	14
bark[27]	514	1		T1	21		T12	21		T20	21
bark[28]	500	1		T4	14		T12	21		T104	21
bark[29]	419	1		T6	14		T20	38		T42	93
bark[30]	502	1		T3	21		T28	30		T152	21
bark[31]	382	1		T15	220		T103	14		T106	30
bark_0	4834	1		T1	63		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30897	1		T1	1368		T3	202		T5	10
bite[1]	732	1		T92	13		T23	13		T28	128
bite[2]	875	1		T1	21		T15	233		T103	13
bite[3]	395	1		T77	31		T101	21		T105	21
bite[4]	326	1		T40	21		T42	92		T106	22
bite[5]	607	1		T3	21		T25	13		T27	120
bite[6]	463	1		T1	26		T32	13		T112	21
bite[7]	743	1		T1	42		T15	21		T106	21
bite[8]	418	1		T31	21		T20	26		T44	21
bite[9]	501	1		T1	21		T20	21		T28	30
bite[10]	600	1		T15	198		T27	179		T148	47
bite[11]	435	1		T12	25		T41	26		T42	26
bite[12]	572	1		T3	21		T27	86		T42	276
bite[13]	1098	1		T1	67		T80	13		T118	21
bite[14]	737	1		T1	21		T28	223		T44	129
bite[15]	748	1		T19	63		T40	25		T131	26
bite[16]	170	1		T1	26		T40	25		T134	13
bite[17]	763	1		T41	6		T53	34		T99	13
bite[18]	770	1		T3	35		T12	21		T80	21
bite[19]	358	1		T27	51		T79	13		T118	42
bite[20]	905	1		T20	51		T40	149		T144	21
bite[21]	160	1		T1	21		T20	38		T122	21
bite[22]	359	1		T24	13		T48	13		T95	42
bite[23]	304	1		T148	30		T171	13		T101	21
bite[24]	233	1		T31	123		T128	13		T96	21
bite[25]	1106	1		T11	13		T41	583		T101	83
bite[26]	600	1		T2	13		T12	35		T148	63
bite[27]	350	1		T4	13		T6	13		T12	21
bite[28]	636	1		T3	21		T28	26		T159	13
bite[29]	187	1		T20	26		T42	21		T160	26
bite[30]	614	1		T1	21		T10	13		T12	55
bite[31]	521	1		T42	25		T179	13		T118	57
bite_0	5426	1		T1	72		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	45593	1		T1	1706		T2	21		T3	308
auto[1]	8016	1		T12	153		T15	283		T20	19

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1237	1		T1	77		T3	28		T12	35
prescale[1]	980	1		T1	110		T3	19		T31	125
prescale[2]	425	1		T27	2		T43	2		T172	19
prescale[3]	627	1		T15	19		T80	33		T43	19
prescale[4]	978	1		T1	165		T91	9		T31	36
prescale[5]	910	1		T1	19		T20	19		T41	79
prescale[6]	1063	1		T1	53		T31	202		T28	19
prescale[7]	768	1		T31	43		T26	9		T77	19
prescale[8]	925	1		T1	19		T12	62		T13	9
prescale[9]	914	1		T1	110		T3	19		T19	19
prescale[10]	772	1		T12	77		T31	49		T27	2
prescale[11]	1179	1		T1	83		T31	24		T27	2
prescale[12]	1172	1		T1	19		T9	9		T15	137
prescale[13]	694	1		T1	109		T28	2		T40	2
prescale[14]	884	1		T8	9		T27	2		T160	47
prescale[15]	874	1		T1	2		T3	46		T41	2
prescale[16]	959	1		T1	19		T3	53		T76	9
prescale[17]	748	1		T1	19		T28	2		T40	123
prescale[18]	493	1		T1	46		T3	19		T42	66
prescale[19]	607	1		T7	9		T27	9		T42	21
prescale[20]	1066	1		T1	124		T12	101		T27	66
prescale[21]	809	1		T19	19		T27	34		T28	120
prescale[22]	957	1		T1	187		T19	74		T28	120
prescale[23]	814	1		T1	78		T12	2		T15	2
prescale[24]	851	1		T14	9		T28	2		T40	95
prescale[25]	675	1		T1	40		T27	2		T40	2
prescale[26]	529	1		T1	29		T15	45		T31	2
prescale[27]	830	1		T1	119		T19	19		T28	77
prescale[28]	646	1		T15	45		T40	45		T41	38
prescale[29]	1427	1		T15	2		T28	9		T40	54
prescale[30]	687	1		T15	66		T31	9		T28	2
prescale[31]	756	1		T1	28		T15	47		T31	2
prescale_0	26353	1		T1	251		T2	21		T3	124

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40528	1		T1	1401		T2	9		T3	212
auto[1]	13081	1		T1	305		T2	12		T3	96

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	53609	1		T1	1706		T2	21		T3	308

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	31926	1		T1	1114		T2	1		T3	205
wkup[1]	355	1		T1	21		T19	21		T27	26
wkup[2]	541	1		T1	98		T31	30		T101	21
wkup[3]	244	1		T1	45		T15	36		T31	30
wkup[4]	356	1		T1	21		T20	47		T41	8
wkup[5]	218	1		T12	15		T172	21		T174	15
wkup[6]	321	1		T12	21		T31	21		T28	30
wkup[7]	181	1		T1	21		T42	21		T45	21
wkup[8]	325	1		T19	21		T27	51		T28	21
wkup[9]	380	1		T1	21		T92	15		T20	21
wkup[10]	144	1		T41	21		T127	21		T86	30
wkup[11]	252	1		T3	21		T118	21		T44	21
wkup[12]	199	1		T1	8		T27	30		T77	21
wkup[13]	283	1		T43	21		T112	21		T45	21
wkup[14]	189	1		T50	21		T81	21		T168	42
wkup[15]	348	1		T40	21		T148	21		T41	30
wkup[16]	298	1		T15	21		T96	21		T144	21
wkup[17]	176	1		T31	21		T28	21		T77	30
wkup[18]	428	1		T1	21		T12	30		T23	15
wkup[19]	284	1		T15	30		T28	21		T81	21
wkup[20]	183	1		T25	15		T28	26		T43	21
wkup[21]	198	1		T27	21		T41	21		T152	21
wkup[22]	314	1		T1	21		T6	15		T31	21
wkup[23]	170	1		T4	15		T40	21		T43	21
wkup[24]	296	1		T31	63		T171	15		T43	21
wkup[25]	348	1		T1	42		T148	21		T42	21
wkup[26]	199	1		T10	15		T31	21		T27	42
wkup[27]	300	1		T40	21		T43	60		T160	21
wkup[28]	240	1		T11	15		T15	44		T24	15
wkup[29]	201	1		T105	30		T144	30		T95	21
wkup[30]	235	1		T31	21		T27	21		T148	21
wkup[31]	242	1		T19	21		T27	21		T28	30
wkup[32]	251	1		T15	26		T75	15		T77	21
wkup[33]	280	1		T1	21		T12	20		T148	30
wkup[34]	221	1		T1	29		T12	35		T101	21
wkup[35]	344	1		T1	21		T15	21		T31	21
wkup[36]	302	1		T77	31		T42	21		T160	24
wkup[37]	207	1		T118	21		T104	21		T161	21
wkup[38]	326	1		T12	21		T31	51		T144	21
wkup[39]	318	1		T41	26		T103	15		T155	30
wkup[40]	270	1		T1	42		T27	21		T179	15
wkup[41]	254	1		T12	21		T20	30		T41	21
wkup[42]	638	1		T15	42		T31	42		T41	21
wkup[43]	412	1		T3	21		T12	21		T160	21
wkup[44]	327	1		T28	21		T96	21		T105	21
wkup[45]	176	1		T50	21		T161	21		T81	21
wkup[46]	417	1		T19	21		T42	21		T155	21
wkup[47]	186	1		T15	21		T172	21		T81	21
wkup[48]	186	1		T185	35		T81	8		T86	34
wkup[49]	186	1		T20	21		T40	21		T105	39
wkup[50]	226	1		T152	21		T50	21		T161	35
wkup[51]	308	1		T1	26		T31	21		T20	26
wkup[52]	190	1		T15	21		T28	21		T80	21
wkup[53]	365	1		T1	21		T41	30		T101	30
wkup[54]	320	1		T15	15		T31	21		T20	21
wkup[55]	278	1		T15	21		T80	30		T41	21
wkup[56]	290	1		T1	21		T28	30		T42	26
wkup[57]	311	1		T2	15		T3	21		T50	26
wkup[58]	325	1		T15	35		T31	21		T43	21
wkup[59]	262	1		T3	35		T31	21		T159	15
wkup[60]	321	1		T1	21		T15	21		T112	21
wkup[61]	277	1		T40	21		T169	42		T151	21
wkup[62]	378	1		T1	26		T155	21		T43	51
wkup[63]	302	1		T27	29		T40	15		T44	21
wkup_0	3781	1		T1	45		T2	5		T3	5