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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.28 99.33 93.67 100.00 98.40 99.51 50.78


Total test records in report: 422
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T39 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.226037701 Jul 06 06:31:55 PM PDT 24 Jul 06 06:31:57 PM PDT 24 508845237 ps
T34 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2616185129 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:07 PM PDT 24 1206570261 ps
T284 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.813366634 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:06 PM PDT 24 460451429 ps
T197 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2343536124 Jul 06 06:31:55 PM PDT 24 Jul 06 06:31:56 PM PDT 24 649768158 ps
T35 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1242155050 Jul 06 06:32:15 PM PDT 24 Jul 06 06:32:19 PM PDT 24 1183836005 ps
T285 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3367303323 Jul 06 06:32:16 PM PDT 24 Jul 06 06:32:17 PM PDT 24 471896854 ps
T54 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1876070291 Jul 06 06:32:14 PM PDT 24 Jul 06 06:32:16 PM PDT 24 282432607 ps
T286 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2391134824 Jul 06 06:32:19 PM PDT 24 Jul 06 06:32:20 PM PDT 24 272725811 ps
T287 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3939637168 Jul 06 06:32:04 PM PDT 24 Jul 06 06:32:06 PM PDT 24 473673566 ps
T198 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.402984857 Jul 06 06:32:15 PM PDT 24 Jul 06 06:32:17 PM PDT 24 521658182 ps
T288 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2889886039 Jul 06 06:31:58 PM PDT 24 Jul 06 06:32:01 PM PDT 24 430674825 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4064418417 Jul 06 06:31:55 PM PDT 24 Jul 06 06:31:57 PM PDT 24 1339652071 ps
T36 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2550243439 Jul 06 06:32:07 PM PDT 24 Jul 06 06:32:11 PM PDT 24 8143133061 ps
T195 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4178473638 Jul 06 06:32:04 PM PDT 24 Jul 06 06:32:05 PM PDT 24 379969801 ps
T55 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3884510198 Jul 06 06:31:53 PM PDT 24 Jul 06 06:31:55 PM PDT 24 470390208 ps
T196 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.950767316 Jul 06 06:32:10 PM PDT 24 Jul 06 06:32:11 PM PDT 24 440850822 ps
T289 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1893625818 Jul 06 06:32:21 PM PDT 24 Jul 06 06:32:22 PM PDT 24 458673105 ps
T290 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3714863643 Jul 06 06:32:13 PM PDT 24 Jul 06 06:32:14 PM PDT 24 371730951 ps
T56 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.717300766 Jul 06 06:31:50 PM PDT 24 Jul 06 06:32:01 PM PDT 24 13359011990 ps
T37 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3218803895 Jul 06 06:32:00 PM PDT 24 Jul 06 06:32:05 PM PDT 24 8672048305 ps
T57 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2782688216 Jul 06 06:31:54 PM PDT 24 Jul 06 06:32:01 PM PDT 24 2854784118 ps
T38 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1460624033 Jul 06 06:31:57 PM PDT 24 Jul 06 06:32:00 PM PDT 24 8597219960 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2812727452 Jul 06 06:32:00 PM PDT 24 Jul 06 06:32:10 PM PDT 24 12752805323 ps
T291 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3081056746 Jul 06 06:31:54 PM PDT 24 Jul 06 06:31:55 PM PDT 24 324787602 ps
T292 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2650570110 Jul 06 06:32:02 PM PDT 24 Jul 06 06:32:03 PM PDT 24 434150291 ps
T293 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3058669370 Jul 06 06:32:43 PM PDT 24 Jul 06 06:32:44 PM PDT 24 378021578 ps
T294 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1994747821 Jul 06 06:31:53 PM PDT 24 Jul 06 06:31:54 PM PDT 24 353170600 ps
T59 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1892880156 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:05 PM PDT 24 369797245 ps
T295 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2100619926 Jul 06 06:32:17 PM PDT 24 Jul 06 06:32:18 PM PDT 24 491969697 ps
T296 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2950962628 Jul 06 06:32:13 PM PDT 24 Jul 06 06:32:19 PM PDT 24 4275795929 ps
T297 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3191799110 Jul 06 06:31:53 PM PDT 24 Jul 06 06:31:57 PM PDT 24 7231359727 ps
T298 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1675228181 Jul 06 06:31:59 PM PDT 24 Jul 06 06:32:04 PM PDT 24 4682434651 ps
T299 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2567796321 Jul 06 06:32:02 PM PDT 24 Jul 06 06:32:03 PM PDT 24 509493563 ps
T300 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1690386564 Jul 06 06:32:06 PM PDT 24 Jul 06 06:32:08 PM PDT 24 8593655163 ps
T301 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3096002222 Jul 06 06:32:11 PM PDT 24 Jul 06 06:32:14 PM PDT 24 614494459 ps
T302 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2035356133 Jul 06 06:31:55 PM PDT 24 Jul 06 06:31:56 PM PDT 24 293096046 ps
T303 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3209877150 Jul 06 06:32:11 PM PDT 24 Jul 06 06:32:12 PM PDT 24 461454360 ps
T304 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2043426216 Jul 06 06:32:15 PM PDT 24 Jul 06 06:32:16 PM PDT 24 313975511 ps
T305 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2144396649 Jul 06 06:32:16 PM PDT 24 Jul 06 06:32:18 PM PDT 24 431914059 ps
T71 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.597368148 Jul 06 06:32:02 PM PDT 24 Jul 06 06:32:04 PM PDT 24 452444661 ps
T306 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2784143703 Jul 06 06:32:21 PM PDT 24 Jul 06 06:32:22 PM PDT 24 470818467 ps
T307 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1887015027 Jul 06 06:32:05 PM PDT 24 Jul 06 06:32:09 PM PDT 24 8245944365 ps
T308 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2457558834 Jul 06 06:32:02 PM PDT 24 Jul 06 06:32:04 PM PDT 24 481123039 ps
T309 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.602674206 Jul 06 06:32:11 PM PDT 24 Jul 06 06:32:13 PM PDT 24 4327475161 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.430446160 Jul 06 06:31:58 PM PDT 24 Jul 06 06:31:59 PM PDT 24 295762097 ps
T310 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1587115983 Jul 06 06:31:57 PM PDT 24 Jul 06 06:32:00 PM PDT 24 661377878 ps
T311 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.599372891 Jul 06 06:32:19 PM PDT 24 Jul 06 06:32:20 PM PDT 24 364021515 ps
T312 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3167850794 Jul 06 06:32:14 PM PDT 24 Jul 06 06:32:16 PM PDT 24 448451596 ps
T72 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.753086573 Jul 06 06:31:57 PM PDT 24 Jul 06 06:32:00 PM PDT 24 1517405035 ps
T313 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1008664667 Jul 06 06:32:02 PM PDT 24 Jul 06 06:32:04 PM PDT 24 442107704 ps
T73 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.26464744 Jul 06 06:32:12 PM PDT 24 Jul 06 06:32:13 PM PDT 24 1810293183 ps
T314 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3450771079 Jul 06 06:31:54 PM PDT 24 Jul 06 06:31:55 PM PDT 24 529310040 ps
T74 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2779974646 Jul 06 06:32:05 PM PDT 24 Jul 06 06:32:07 PM PDT 24 1399976850 ps
T315 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3620637305 Jul 06 06:32:04 PM PDT 24 Jul 06 06:32:05 PM PDT 24 1601115244 ps
T316 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.115924644 Jul 06 06:32:15 PM PDT 24 Jul 06 06:32:18 PM PDT 24 440043991 ps
T317 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.181779998 Jul 06 06:32:22 PM PDT 24 Jul 06 06:32:23 PM PDT 24 445005509 ps
T318 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4236974824 Jul 06 06:31:49 PM PDT 24 Jul 06 06:31:52 PM PDT 24 655888743 ps
T319 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1209102086 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:06 PM PDT 24 4394449342 ps
T320 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4124728477 Jul 06 06:32:22 PM PDT 24 Jul 06 06:32:24 PM PDT 24 407874878 ps
T321 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1567905763 Jul 06 06:32:22 PM PDT 24 Jul 06 06:32:23 PM PDT 24 489030233 ps
T322 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3913541034 Jul 06 06:31:58 PM PDT 24 Jul 06 06:32:00 PM PDT 24 357631343 ps
T323 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1261868163 Jul 06 06:32:14 PM PDT 24 Jul 06 06:32:16 PM PDT 24 394523459 ps
T324 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3414829803 Jul 06 06:31:52 PM PDT 24 Jul 06 06:31:53 PM PDT 24 942071056 ps
T325 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2415769928 Jul 06 06:32:17 PM PDT 24 Jul 06 06:32:19 PM PDT 24 494718329 ps
T61 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3196071757 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:05 PM PDT 24 754778711 ps
T326 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2131464588 Jul 06 06:31:51 PM PDT 24 Jul 06 06:31:52 PM PDT 24 510008048 ps
T327 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.989374236 Jul 06 06:32:20 PM PDT 24 Jul 06 06:32:21 PM PDT 24 530557829 ps
T328 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1848347184 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:05 PM PDT 24 1212324063 ps
T62 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2835619452 Jul 06 06:32:08 PM PDT 24 Jul 06 06:32:09 PM PDT 24 382723728 ps
T329 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2670915483 Jul 06 06:31:50 PM PDT 24 Jul 06 06:31:51 PM PDT 24 473354293 ps
T330 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3388079097 Jul 06 06:32:06 PM PDT 24 Jul 06 06:32:08 PM PDT 24 486559073 ps
T331 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1664300352 Jul 06 06:32:17 PM PDT 24 Jul 06 06:32:19 PM PDT 24 340206248 ps
T332 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3946286615 Jul 06 06:32:09 PM PDT 24 Jul 06 06:32:11 PM PDT 24 512205542 ps
T333 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3331295406 Jul 06 06:32:08 PM PDT 24 Jul 06 06:32:10 PM PDT 24 457892437 ps
T334 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3125184448 Jul 06 06:32:07 PM PDT 24 Jul 06 06:32:08 PM PDT 24 424333232 ps
T335 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2072275435 Jul 06 06:32:10 PM PDT 24 Jul 06 06:32:16 PM PDT 24 4147603027 ps
T336 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.52085324 Jul 06 06:32:18 PM PDT 24 Jul 06 06:32:19 PM PDT 24 304204157 ps
T337 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2825885265 Jul 06 06:32:16 PM PDT 24 Jul 06 06:32:17 PM PDT 24 564587124 ps
T338 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.505213576 Jul 06 06:31:59 PM PDT 24 Jul 06 06:32:03 PM PDT 24 1974397878 ps
T339 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1247059799 Jul 06 06:31:58 PM PDT 24 Jul 06 06:31:59 PM PDT 24 467131444 ps
T63 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3069505826 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:04 PM PDT 24 453634335 ps
T340 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2897960562 Jul 06 06:31:54 PM PDT 24 Jul 06 06:31:55 PM PDT 24 627359658 ps
T341 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1057120613 Jul 06 06:32:01 PM PDT 24 Jul 06 06:32:06 PM PDT 24 2137868382 ps
T342 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1393583407 Jul 06 06:32:18 PM PDT 24 Jul 06 06:32:19 PM PDT 24 523466255 ps
T343 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2083035337 Jul 06 06:32:04 PM PDT 24 Jul 06 06:32:05 PM PDT 24 474611734 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2421906528 Jul 06 06:32:01 PM PDT 24 Jul 06 06:32:20 PM PDT 24 7372102002 ps
T345 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.888217508 Jul 06 06:32:17 PM PDT 24 Jul 06 06:32:18 PM PDT 24 503022904 ps
T346 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3692661553 Jul 06 06:32:10 PM PDT 24 Jul 06 06:32:13 PM PDT 24 4521313717 ps
T347 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1026166874 Jul 06 06:32:14 PM PDT 24 Jul 06 06:32:15 PM PDT 24 335904392 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1872353399 Jul 06 06:31:54 PM PDT 24 Jul 06 06:31:55 PM PDT 24 582664763 ps
T348 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2653819509 Jul 06 06:32:02 PM PDT 24 Jul 06 06:32:03 PM PDT 24 443792616 ps
T349 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2160725006 Jul 06 06:31:50 PM PDT 24 Jul 06 06:31:52 PM PDT 24 1458844769 ps
T350 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2988129062 Jul 06 06:32:11 PM PDT 24 Jul 06 06:32:13 PM PDT 24 1007550058 ps
T351 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2405226916 Jul 06 06:32:08 PM PDT 24 Jul 06 06:32:10 PM PDT 24 1210835550 ps
T352 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1987042678 Jul 06 06:32:09 PM PDT 24 Jul 06 06:32:11 PM PDT 24 403413965 ps
T353 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.732126664 Jul 06 06:32:04 PM PDT 24 Jul 06 06:32:06 PM PDT 24 333491188 ps
T354 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2763401267 Jul 06 06:32:14 PM PDT 24 Jul 06 06:32:15 PM PDT 24 422573539 ps
T355 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1864367542 Jul 06 06:32:16 PM PDT 24 Jul 06 06:32:18 PM PDT 24 310013908 ps
T356 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.465695626 Jul 06 06:32:12 PM PDT 24 Jul 06 06:32:20 PM PDT 24 8478029924 ps
T193 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.850548938 Jul 06 06:31:49 PM PDT 24 Jul 06 06:32:02 PM PDT 24 8287539861 ps
T357 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2040457443 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:04 PM PDT 24 428658353 ps
T358 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2281117853 Jul 06 06:32:01 PM PDT 24 Jul 06 06:32:15 PM PDT 24 8522337612 ps
T359 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1818442489 Jul 06 06:32:11 PM PDT 24 Jul 06 06:32:13 PM PDT 24 2668705011 ps
T360 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2040227191 Jul 06 06:32:14 PM PDT 24 Jul 06 06:32:15 PM PDT 24 462578816 ps
T361 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2640829790 Jul 06 06:32:19 PM PDT 24 Jul 06 06:32:21 PM PDT 24 423410346 ps
T68 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1757348481 Jul 06 06:32:10 PM PDT 24 Jul 06 06:32:12 PM PDT 24 519411829 ps
T362 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.704911468 Jul 06 06:32:05 PM PDT 24 Jul 06 06:32:12 PM PDT 24 4267575626 ps
T363 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1574088156 Jul 06 06:31:45 PM PDT 24 Jul 06 06:31:48 PM PDT 24 374211719 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1542525905 Jul 06 06:31:53 PM PDT 24 Jul 06 06:31:54 PM PDT 24 674962628 ps
T364 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1590601753 Jul 06 06:32:21 PM PDT 24 Jul 06 06:32:22 PM PDT 24 507327593 ps
T365 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3401053389 Jul 06 06:32:09 PM PDT 24 Jul 06 06:32:09 PM PDT 24 389217954 ps
T366 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1039176627 Jul 06 06:31:49 PM PDT 24 Jul 06 06:31:53 PM PDT 24 8174123138 ps
T367 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1052443 Jul 06 06:32:11 PM PDT 24 Jul 06 06:32:12 PM PDT 24 358051442 ps
T194 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.173114162 Jul 06 06:32:13 PM PDT 24 Jul 06 06:32:18 PM PDT 24 8932474867 ps
T368 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3025730160 Jul 06 06:31:59 PM PDT 24 Jul 06 06:32:00 PM PDT 24 311168138 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.692217731 Jul 06 06:31:55 PM PDT 24 Jul 06 06:32:09 PM PDT 24 8488473336 ps
T370 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1669836922 Jul 06 06:31:50 PM PDT 24 Jul 06 06:31:51 PM PDT 24 469285390 ps
T371 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1280611797 Jul 06 06:32:08 PM PDT 24 Jul 06 06:32:09 PM PDT 24 299092024 ps
T372 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2224716967 Jul 06 06:32:08 PM PDT 24 Jul 06 06:32:09 PM PDT 24 517865366 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.181112977 Jul 06 06:31:52 PM PDT 24 Jul 06 06:31:53 PM PDT 24 474336396 ps
T374 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2314051848 Jul 06 06:31:55 PM PDT 24 Jul 06 06:31:57 PM PDT 24 942469790 ps
T375 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3309529279 Jul 06 06:31:54 PM PDT 24 Jul 06 06:31:55 PM PDT 24 444873559 ps
T376 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2589208288 Jul 06 06:32:14 PM PDT 24 Jul 06 06:32:18 PM PDT 24 1535510037 ps
T377 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.100154355 Jul 06 06:32:13 PM PDT 24 Jul 06 06:32:15 PM PDT 24 520610915 ps
T378 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1394042964 Jul 06 06:32:10 PM PDT 24 Jul 06 06:32:11 PM PDT 24 503395212 ps
T379 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2333690852 Jul 06 06:32:00 PM PDT 24 Jul 06 06:32:01 PM PDT 24 546473889 ps
T67 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.873499407 Jul 06 06:32:01 PM PDT 24 Jul 06 06:32:03 PM PDT 24 498758032 ps
T380 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3027410573 Jul 06 06:32:06 PM PDT 24 Jul 06 06:32:09 PM PDT 24 511430230 ps
T381 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.906444068 Jul 06 06:31:57 PM PDT 24 Jul 06 06:32:00 PM PDT 24 1532343511 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2669742404 Jul 06 06:32:01 PM PDT 24 Jul 06 06:32:02 PM PDT 24 1180347221 ps
T383 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3022527299 Jul 06 06:31:58 PM PDT 24 Jul 06 06:31:59 PM PDT 24 283804962 ps
T384 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2962834542 Jul 06 06:31:53 PM PDT 24 Jul 06 06:31:56 PM PDT 24 5542784685 ps
T69 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1518605689 Jul 06 06:32:13 PM PDT 24 Jul 06 06:32:14 PM PDT 24 441564206 ps
T385 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2833457805 Jul 06 06:32:07 PM PDT 24 Jul 06 06:32:08 PM PDT 24 411501473 ps
T386 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3665711008 Jul 06 06:32:01 PM PDT 24 Jul 06 06:32:03 PM PDT 24 581214425 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1866906617 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:05 PM PDT 24 444605709 ps
T388 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2671806682 Jul 06 06:32:10 PM PDT 24 Jul 06 06:32:11 PM PDT 24 533996258 ps
T65 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3770084223 Jul 06 06:32:03 PM PDT 24 Jul 06 06:32:04 PM PDT 24 354260196 ps
T389 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1979735357 Jul 06 06:32:09 PM PDT 24 Jul 06 06:32:12 PM PDT 24 542785244 ps
T390 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.595127408 Jul 06 06:31:49 PM PDT 24 Jul 06 06:31:51 PM PDT 24 594597268 ps
T391 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2852229259 Jul 06 06:31:55 PM PDT 24 Jul 06 06:31:56 PM PDT 24 315516951 ps
T392 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.131135643 Jul 06 06:32:07 PM PDT 24 Jul 06 06:32:09 PM PDT 24 568254291 ps
T393 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4071472208 Jul 06 06:31:58 PM PDT 24 Jul 06 06:31:59 PM PDT 24 527556604 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4092531053 Jul 06 06:32:00 PM PDT 24 Jul 06 06:32:02 PM PDT 24 318822015 ps
T395 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2517399090 Jul 06 06:31:50 PM PDT 24 Jul 06 06:31:51 PM PDT 24 388332935 ps
T396 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.558553063 Jul 06 06:32:13 PM PDT 24 Jul 06 06:32:14 PM PDT 24 377284933 ps
T397 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3230133912 Jul 06 06:32:11 PM PDT 24 Jul 06 06:32:12 PM PDT 24 440820529 ps
T398 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.364571349 Jul 06 06:32:15 PM PDT 24 Jul 06 06:32:18 PM PDT 24 2335687342 ps
T399 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2433478930 Jul 06 06:32:11 PM PDT 24 Jul 06 06:32:12 PM PDT 24 361408669 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.38132316 Jul 06 06:32:11 PM PDT 24 Jul 06 06:32:12 PM PDT 24 485775833 ps
T401 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.281284332 Jul 06 06:32:16 PM PDT 24 Jul 06 06:32:17 PM PDT 24 472965056 ps
T402 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2541465198 Jul 06 06:32:12 PM PDT 24 Jul 06 06:32:13 PM PDT 24 340498428 ps
T403 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2540144993 Jul 06 06:32:04 PM PDT 24 Jul 06 06:32:05 PM PDT 24 361773303 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1187692575 Jul 06 06:31:52 PM PDT 24 Jul 06 06:31:53 PM PDT 24 366766518 ps
T405 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2006700230 Jul 06 06:32:06 PM PDT 24 Jul 06 06:32:18 PM PDT 24 8080652554 ps
T406 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2358348087 Jul 06 06:31:57 PM PDT 24 Jul 06 06:31:58 PM PDT 24 440591543 ps
T407 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1622803019 Jul 06 06:31:58 PM PDT 24 Jul 06 06:31:59 PM PDT 24 498713551 ps
T408 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2434827046 Jul 06 06:32:13 PM PDT 24 Jul 06 06:32:14 PM PDT 24 375491565 ps
T409 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3549711932 Jul 06 06:32:15 PM PDT 24 Jul 06 06:32:16 PM PDT 24 374058099 ps
T410 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2350938856 Jul 06 06:31:54 PM PDT 24 Jul 06 06:31:57 PM PDT 24 662341589 ps
T411 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.575486853 Jul 06 06:32:18 PM PDT 24 Jul 06 06:32:19 PM PDT 24 373598402 ps
T412 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1466327130 Jul 06 06:32:13 PM PDT 24 Jul 06 06:32:15 PM PDT 24 2449246804 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1088977588 Jul 06 06:32:01 PM PDT 24 Jul 06 06:32:04 PM PDT 24 473561558 ps
T414 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3013557324 Jul 06 06:32:04 PM PDT 24 Jul 06 06:32:06 PM PDT 24 445673849 ps
T415 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.283501556 Jul 06 06:32:18 PM PDT 24 Jul 06 06:32:19 PM PDT 24 522394193 ps
T416 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1804797343 Jul 06 06:32:19 PM PDT 24 Jul 06 06:32:20 PM PDT 24 462433578 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1283880338 Jul 06 06:31:56 PM PDT 24 Jul 06 06:31:57 PM PDT 24 384717687 ps
T418 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3331894803 Jul 06 06:32:09 PM PDT 24 Jul 06 06:32:12 PM PDT 24 1788330099 ps
T419 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.906511350 Jul 06 06:32:12 PM PDT 24 Jul 06 06:32:13 PM PDT 24 422348259 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2166760453 Jul 06 06:31:49 PM PDT 24 Jul 06 06:31:51 PM PDT 24 511289672 ps
T421 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2036889047 Jul 06 06:32:18 PM PDT 24 Jul 06 06:32:19 PM PDT 24 354542682 ps
T422 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3128421394 Jul 06 06:32:02 PM PDT 24 Jul 06 06:32:05 PM PDT 24 588894298 ps

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3219235163
Short name T1
Test name
Test status
Simulation time 658026272394 ps
CPU time 409.98 seconds
Started Jul 06 05:18:56 PM PDT 24
Finished Jul 06 05:25:47 PM PDT 24
Peak memory 210888 kb
Host smart-89e2add2-2797-4de2-b4c4-a7e30df3018b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219235163 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3219235163
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1402199789
Short name T31
Test name
Test status
Simulation time 436679283858 ps
CPU time 197.99 seconds
Started Jul 06 05:18:54 PM PDT 24
Finished Jul 06 05:22:13 PM PDT 24
Peak memory 214304 kb
Host smart-f6916695-ad4b-4722-93dc-80a9ed5ca333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402199789 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1402199789
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3437397133
Short name T20
Test name
Test status
Simulation time 16538253512 ps
CPU time 2.45 seconds
Started Jul 06 05:18:55 PM PDT 24
Finished Jul 06 05:18:58 PM PDT 24
Peak memory 198316 kb
Host smart-134d7280-c731-4a00-9a57-9d62fe476574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437397133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3437397133
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1876070291
Short name T54
Test name
Test status
Simulation time 282432607 ps
CPU time 0.92 seconds
Started Jul 06 06:32:14 PM PDT 24
Finished Jul 06 06:32:16 PM PDT 24
Peak memory 193236 kb
Host smart-8ce556ac-53f0-4c67-ab28-1acc2da5d659
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876070291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1876070291
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4274691295
Short name T22
Test name
Test status
Simulation time 7798769935 ps
CPU time 4.23 seconds
Started Jul 06 05:18:16 PM PDT 24
Finished Jul 06 05:18:21 PM PDT 24
Peak memory 215800 kb
Host smart-1201035f-ac6f-40f1-9b7d-3a3b4243f568
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274691295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4274691295
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.686678406
Short name T81
Test name
Test status
Simulation time 317944297278 ps
CPU time 373.68 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:25:01 PM PDT 24
Peak memory 213952 kb
Host smart-174f72cd-fe83-4993-84c2-20786ce61ab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686678406 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.686678406
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.931146143
Short name T3
Test name
Test status
Simulation time 286389731525 ps
CPU time 94.95 seconds
Started Jul 06 05:18:15 PM PDT 24
Finished Jul 06 05:19:50 PM PDT 24
Peak memory 193092 kb
Host smart-36c9d1b5-c143-42e8-a0cd-bf3ff7dad88a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931146143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.931146143
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2299930149
Short name T93
Test name
Test status
Simulation time 187752405986 ps
CPU time 599.72 seconds
Started Jul 06 05:19:00 PM PDT 24
Finished Jul 06 05:29:01 PM PDT 24
Peak memory 205124 kb
Host smart-c5afce32-cbe1-4822-8514-ac8faecf1108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299930149 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2299930149
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1452017827
Short name T88
Test name
Test status
Simulation time 432874818492 ps
CPU time 787.78 seconds
Started Jul 06 05:18:28 PM PDT 24
Finished Jul 06 05:31:36 PM PDT 24
Peak memory 215016 kb
Host smart-6e340b2c-5fd9-4da7-b8a2-5ab9dffd8039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452017827 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1452017827
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.53384383
Short name T27
Test name
Test status
Simulation time 49614090919 ps
CPU time 264.54 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:23:06 PM PDT 24
Peak memory 206848 kb
Host smart-fba2ac96-9774-485b-a197-6a4866a2b28e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53384383 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.53384383
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1369363949
Short name T130
Test name
Test status
Simulation time 161802135521 ps
CPU time 351.44 seconds
Started Jul 06 05:18:32 PM PDT 24
Finished Jul 06 05:24:24 PM PDT 24
Peak memory 206756 kb
Host smart-946c7662-8b0e-45c5-b23f-a615a5b854aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369363949 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1369363949
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1238054586
Short name T108
Test name
Test status
Simulation time 49839932239 ps
CPU time 520.29 seconds
Started Jul 06 05:18:53 PM PDT 24
Finished Jul 06 05:27:34 PM PDT 24
Peak memory 214076 kb
Host smart-3c555266-91b8-49d2-9a47-636f658b6238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238054586 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1238054586
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3450445000
Short name T42
Test name
Test status
Simulation time 132628586367 ps
CPU time 506.34 seconds
Started Jul 06 05:18:28 PM PDT 24
Finished Jul 06 05:26:55 PM PDT 24
Peak memory 211984 kb
Host smart-56cefed2-2143-420c-bf12-8764dd7f6bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450445000 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3450445000
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1078229993
Short name T50
Test name
Test status
Simulation time 261026379847 ps
CPU time 567.29 seconds
Started Jul 06 05:19:06 PM PDT 24
Finished Jul 06 05:28:35 PM PDT 24
Peak memory 214152 kb
Host smart-4c3d06c1-958e-44c9-aad1-edf1ceba5682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078229993 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1078229993
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3808169801
Short name T113
Test name
Test status
Simulation time 43316516330 ps
CPU time 363.03 seconds
Started Jul 06 05:18:31 PM PDT 24
Finished Jul 06 05:24:35 PM PDT 24
Peak memory 214228 kb
Host smart-4261ce0b-1398-4ebc-804c-3d8151f90adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808169801 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3808169801
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1111109384
Short name T98
Test name
Test status
Simulation time 248344778712 ps
CPU time 177.74 seconds
Started Jul 06 05:18:30 PM PDT 24
Finished Jul 06 05:21:28 PM PDT 24
Peak memory 192496 kb
Host smart-4c275c5d-b2f5-49e3-9c59-852c5394508f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111109384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1111109384
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2550243439
Short name T36
Test name
Test status
Simulation time 8143133061 ps
CPU time 3.89 seconds
Started Jul 06 06:32:07 PM PDT 24
Finished Jul 06 06:32:11 PM PDT 24
Peak memory 198292 kb
Host smart-5dc90278-600c-4cdb-836d-6aa1be1ad6dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550243439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2550243439
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1345553360
Short name T95
Test name
Test status
Simulation time 279133772633 ps
CPU time 241.95 seconds
Started Jul 06 05:18:49 PM PDT 24
Finished Jul 06 05:22:51 PM PDT 24
Peak memory 193096 kb
Host smart-f2e52186-c0b5-4ec1-9ee8-1de1ff9a0f63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345553360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1345553360
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3220183802
Short name T118
Test name
Test status
Simulation time 84491393273 ps
CPU time 59.03 seconds
Started Jul 06 05:18:51 PM PDT 24
Finished Jul 06 05:19:51 PM PDT 24
Peak memory 198328 kb
Host smart-0d1da9cf-85bf-4649-9898-3bcc621c9a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220183802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3220183802
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1851237302
Short name T83
Test name
Test status
Simulation time 259961587387 ps
CPU time 563.71 seconds
Started Jul 06 05:18:59 PM PDT 24
Finished Jul 06 05:28:23 PM PDT 24
Peak memory 204836 kb
Host smart-80291827-9027-4714-a34a-7334c8695561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851237302 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1851237302
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3287369596
Short name T97
Test name
Test status
Simulation time 81994767546 ps
CPU time 122.72 seconds
Started Jul 06 05:18:43 PM PDT 24
Finished Jul 06 05:20:46 PM PDT 24
Peak memory 191996 kb
Host smart-21ea733b-bc5d-407a-989f-e0299c5596a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287369596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3287369596
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1448607641
Short name T122
Test name
Test status
Simulation time 101993954806 ps
CPU time 834.32 seconds
Started Jul 06 05:19:05 PM PDT 24
Finished Jul 06 05:33:01 PM PDT 24
Peak memory 208396 kb
Host smart-c8815e49-8330-4134-876e-cbdd3d285753
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448607641 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1448607641
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3830489577
Short name T136
Test name
Test status
Simulation time 170830148259 ps
CPU time 342.56 seconds
Started Jul 06 05:18:33 PM PDT 24
Finished Jul 06 05:24:16 PM PDT 24
Peak memory 206836 kb
Host smart-79b1beb8-d875-41b0-a692-1320d24eb8f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830489577 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3830489577
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.693011765
Short name T87
Test name
Test status
Simulation time 140745711198 ps
CPU time 258.33 seconds
Started Jul 06 05:18:11 PM PDT 24
Finished Jul 06 05:22:29 PM PDT 24
Peak memory 214980 kb
Host smart-f236919a-7fe4-4087-ac94-68527dd67ed0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693011765 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.693011765
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.958169480
Short name T110
Test name
Test status
Simulation time 68103850855 ps
CPU time 55.6 seconds
Started Jul 06 05:18:46 PM PDT 24
Finished Jul 06 05:19:42 PM PDT 24
Peak memory 193036 kb
Host smart-81a82e4f-6466-4bb1-acfb-cb96375a2136
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958169480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.958169480
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1652007468
Short name T12
Test name
Test status
Simulation time 12059049253 ps
CPU time 86.68 seconds
Started Jul 06 05:18:11 PM PDT 24
Finished Jul 06 05:19:38 PM PDT 24
Peak memory 206828 kb
Host smart-9a73e261-5108-46cf-9cbe-04e2b301953a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652007468 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1652007468
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.126131584
Short name T94
Test name
Test status
Simulation time 221604568229 ps
CPU time 41.51 seconds
Started Jul 06 05:18:30 PM PDT 24
Finished Jul 06 05:19:12 PM PDT 24
Peak memory 191968 kb
Host smart-e2fb8ced-00b9-411a-9e5a-d69ed25c0df7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126131584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.126131584
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2360175277
Short name T161
Test name
Test status
Simulation time 323918094294 ps
CPU time 502.68 seconds
Started Jul 06 05:18:31 PM PDT 24
Finished Jul 06 05:26:54 PM PDT 24
Peak memory 198164 kb
Host smart-f5fcf473-3c4a-46d2-a9ce-1b004325c9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360175277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2360175277
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2280847579
Short name T86
Test name
Test status
Simulation time 44329723473 ps
CPU time 324.75 seconds
Started Jul 06 05:18:16 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 198960 kb
Host smart-f305aaf3-5df3-46b3-a984-84c10e8ade9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280847579 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2280847579
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3079764155
Short name T80
Test name
Test status
Simulation time 66630548108 ps
CPU time 14.23 seconds
Started Jul 06 05:18:26 PM PDT 24
Finished Jul 06 05:18:41 PM PDT 24
Peak memory 198332 kb
Host smart-18de43f7-2e9a-49ec-a27d-09deb0c314d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079764155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3079764155
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3946404256
Short name T101
Test name
Test status
Simulation time 330202138392 ps
CPU time 457.88 seconds
Started Jul 06 05:19:03 PM PDT 24
Finished Jul 06 05:26:42 PM PDT 24
Peak memory 193020 kb
Host smart-0f90baea-8e45-4af8-9611-a082bb48dfba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946404256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3946404256
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1017826249
Short name T129
Test name
Test status
Simulation time 67818018253 ps
CPU time 288.39 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:23:36 PM PDT 24
Peak memory 208328 kb
Host smart-1aedef9e-efce-4b54-9932-824c3b16ea5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017826249 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1017826249
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.66029075
Short name T107
Test name
Test status
Simulation time 37319812680 ps
CPU time 374.51 seconds
Started Jul 06 05:18:56 PM PDT 24
Finished Jul 06 05:25:11 PM PDT 24
Peak memory 207848 kb
Host smart-4d6e55df-235a-4cbd-8b92-dff1058ed68b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66029075 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.66029075
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3827235406
Short name T114
Test name
Test status
Simulation time 171816113362 ps
CPU time 91.69 seconds
Started Jul 06 05:18:30 PM PDT 24
Finished Jul 06 05:20:02 PM PDT 24
Peak memory 193080 kb
Host smart-29709a60-bb02-4b73-bb04-fe28e38e6530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827235406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3827235406
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3647703115
Short name T151
Test name
Test status
Simulation time 300475855438 ps
CPU time 103.24 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:20:25 PM PDT 24
Peak memory 193064 kb
Host smart-847de170-1f4a-4be0-a3c5-2281f994d72b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647703115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3647703115
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.134848858
Short name T120
Test name
Test status
Simulation time 77925563753 ps
CPU time 113.12 seconds
Started Jul 06 05:18:59 PM PDT 24
Finished Jul 06 05:20:52 PM PDT 24
Peak memory 192976 kb
Host smart-89a63076-d6ff-4104-ab0f-26330cc38ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134848858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.134848858
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.411468148
Short name T44
Test name
Test status
Simulation time 272300764121 ps
CPU time 351.87 seconds
Started Jul 06 05:18:46 PM PDT 24
Finished Jul 06 05:24:39 PM PDT 24
Peak memory 202188 kb
Host smart-95d07bee-77bc-471f-a509-27e976efad5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411468148 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.411468148
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.629943539
Short name T157
Test name
Test status
Simulation time 9522347877 ps
CPU time 63.18 seconds
Started Jul 06 05:18:46 PM PDT 24
Finished Jul 06 05:19:50 PM PDT 24
Peak memory 214976 kb
Host smart-890db979-23de-4c69-b775-2276dbcf75b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629943539 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.629943539
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1941617500
Short name T99
Test name
Test status
Simulation time 120226993816 ps
CPU time 22.27 seconds
Started Jul 06 05:18:58 PM PDT 24
Finished Jul 06 05:19:21 PM PDT 24
Peak memory 191992 kb
Host smart-0d6abe1c-e64b-4915-bec6-382238fc7412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941617500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1941617500
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3681180648
Short name T43
Test name
Test status
Simulation time 43621856552 ps
CPU time 416.9 seconds
Started Jul 06 05:18:49 PM PDT 24
Finished Jul 06 05:25:47 PM PDT 24
Peak memory 200292 kb
Host smart-e952d07d-db90-4b12-8487-8391e78ce9c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681180648 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3681180648
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3235796300
Short name T100
Test name
Test status
Simulation time 95951932634 ps
CPU time 38.15 seconds
Started Jul 06 05:18:52 PM PDT 24
Finished Jul 06 05:19:31 PM PDT 24
Peak memory 191884 kb
Host smart-03731080-9456-4914-8e26-6563330e8837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235796300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3235796300
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.317017706
Short name T109
Test name
Test status
Simulation time 108645304193 ps
CPU time 13.52 seconds
Started Jul 06 05:18:54 PM PDT 24
Finished Jul 06 05:19:08 PM PDT 24
Peak memory 193064 kb
Host smart-62413452-e49d-4d00-a8b3-efc25ecb83df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317017706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.317017706
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2446105641
Short name T126
Test name
Test status
Simulation time 225884298165 ps
CPU time 156.24 seconds
Started Jul 06 05:18:08 PM PDT 24
Finished Jul 06 05:20:44 PM PDT 24
Peak memory 198356 kb
Host smart-6aa6bcd4-f634-4fc1-a6bc-0bc2e85ae082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446105641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2446105641
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2840204324
Short name T104
Test name
Test status
Simulation time 51720695384 ps
CPU time 19.2 seconds
Started Jul 06 05:18:33 PM PDT 24
Finished Jul 06 05:18:52 PM PDT 24
Peak memory 198340 kb
Host smart-485aa24b-61c5-4e82-badc-27adcef3211a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840204324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2840204324
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1619543075
Short name T15
Test name
Test status
Simulation time 103695435236 ps
CPU time 212.83 seconds
Started Jul 06 05:18:15 PM PDT 24
Finished Jul 06 05:21:48 PM PDT 24
Peak memory 214200 kb
Host smart-b639b39d-00bb-4db7-a538-63d646ac5adf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619543075 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1619543075
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.956411873
Short name T155
Test name
Test status
Simulation time 289911878162 ps
CPU time 446.23 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:26:14 PM PDT 24
Peak memory 184392 kb
Host smart-a30102d4-6710-45aa-ba39-69078effe777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956411873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.956411873
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2309521945
Short name T40
Test name
Test status
Simulation time 52982867723 ps
CPU time 583.43 seconds
Started Jul 06 05:18:21 PM PDT 24
Finished Jul 06 05:28:05 PM PDT 24
Peak memory 211152 kb
Host smart-f9ec2c4f-0e56-4d1d-8a41-06d7796434f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309521945 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2309521945
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1723249353
Short name T102
Test name
Test status
Simulation time 209988399525 ps
CPU time 70.47 seconds
Started Jul 06 05:18:09 PM PDT 24
Finished Jul 06 05:19:20 PM PDT 24
Peak memory 198304 kb
Host smart-ad7ea0c9-db0a-4d3d-9d51-b8e69a2b81b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723249353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1723249353
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2444365169
Short name T144
Test name
Test status
Simulation time 67685755063 ps
CPU time 278.55 seconds
Started Jul 06 05:18:26 PM PDT 24
Finished Jul 06 05:23:05 PM PDT 24
Peak memory 208300 kb
Host smart-4c145fdd-58a7-4503-a07d-989061b27670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444365169 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2444365169
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1961788035
Short name T112
Test name
Test status
Simulation time 178479611380 ps
CPU time 276.44 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:23:17 PM PDT 24
Peak memory 193056 kb
Host smart-2145fb44-593d-400d-89b7-3cc25ac07ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961788035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1961788035
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2064303049
Short name T105
Test name
Test status
Simulation time 232355041377 ps
CPU time 342.87 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:24:30 PM PDT 24
Peak memory 192980 kb
Host smart-0fa253e3-5948-40bb-8e4e-9b0c179bc560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064303049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2064303049
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.4176829581
Short name T124
Test name
Test status
Simulation time 129545996588 ps
CPU time 51.93 seconds
Started Jul 06 05:18:49 PM PDT 24
Finished Jul 06 05:19:42 PM PDT 24
Peak memory 198312 kb
Host smart-1fa88cc8-5d68-4714-b24a-9fcdd1e6d343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176829581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.4176829581
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1475548881
Short name T127
Test name
Test status
Simulation time 459532720847 ps
CPU time 164.21 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:21:33 PM PDT 24
Peak memory 198356 kb
Host smart-c81c944a-6823-458a-beac-d5b41de2eb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475548881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1475548881
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1525973659
Short name T28
Test name
Test status
Simulation time 88149390374 ps
CPU time 361.18 seconds
Started Jul 06 05:18:53 PM PDT 24
Finished Jul 06 05:24:55 PM PDT 24
Peak memory 210412 kb
Host smart-77e2e45b-3ba4-4701-a8b8-ef08999e85b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525973659 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1525973659
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2054966459
Short name T53
Test name
Test status
Simulation time 325225348902 ps
CPU time 242.71 seconds
Started Jul 06 05:19:05 PM PDT 24
Finished Jul 06 05:23:09 PM PDT 24
Peak memory 193068 kb
Host smart-ccdfdf84-7e67-4d5a-a3e1-57403e3caad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054966459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2054966459
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1598493276
Short name T131
Test name
Test status
Simulation time 178370245505 ps
CPU time 202.45 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:22:10 PM PDT 24
Peak memory 198336 kb
Host smart-801cb484-c772-4a89-89b1-e7709ff2e6d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598493276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1598493276
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.785927875
Short name T148
Test name
Test status
Simulation time 528991979448 ps
CPU time 76.05 seconds
Started Jul 06 05:18:38 PM PDT 24
Finished Jul 06 05:19:54 PM PDT 24
Peak memory 198344 kb
Host smart-1e24dd1d-9486-4e86-b031-0b5c47736490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785927875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.785927875
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3884510198
Short name T55
Test name
Test status
Simulation time 470390208 ps
CPU time 0.81 seconds
Started Jul 06 06:31:53 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 183820 kb
Host smart-a1777366-5822-45ec-94a5-9c261bf04613
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884510198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3884510198
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1060333488
Short name T77
Test name
Test status
Simulation time 134097180761 ps
CPU time 204.52 seconds
Started Jul 06 05:18:32 PM PDT 24
Finished Jul 06 05:21:57 PM PDT 24
Peak memory 192972 kb
Host smart-9ec409a2-5bd6-4ee4-8ac3-e0e737cd7761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060333488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1060333488
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2198850142
Short name T106
Test name
Test status
Simulation time 90948399421 ps
CPU time 35.95 seconds
Started Jul 06 05:19:04 PM PDT 24
Finished Jul 06 05:19:42 PM PDT 24
Peak memory 191960 kb
Host smart-517c5c4c-d32a-41dd-afa6-acec7fcdfc2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198850142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2198850142
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3022338590
Short name T96
Test name
Test status
Simulation time 231094253504 ps
CPU time 24 seconds
Started Jul 06 05:18:20 PM PDT 24
Finished Jul 06 05:18:44 PM PDT 24
Peak memory 198332 kb
Host smart-e1ba5190-0dbe-4140-8982-f2ca2f0339e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022338590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3022338590
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2179738904
Short name T41
Test name
Test status
Simulation time 31752111584 ps
CPU time 163.89 seconds
Started Jul 06 05:18:22 PM PDT 24
Finished Jul 06 05:21:06 PM PDT 24
Peak memory 206784 kb
Host smart-6d1860be-a2cc-41c5-a037-18fa8872a110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179738904 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2179738904
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1263945852
Short name T140
Test name
Test status
Simulation time 95691071277 ps
CPU time 36.42 seconds
Started Jul 06 05:18:20 PM PDT 24
Finished Jul 06 05:18:57 PM PDT 24
Peak memory 191972 kb
Host smart-40dd1c95-cc7f-450e-9881-1d23c244dc71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263945852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1263945852
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1506037774
Short name T168
Test name
Test status
Simulation time 52089298825 ps
CPU time 540.67 seconds
Started Jul 06 05:18:34 PM PDT 24
Finished Jul 06 05:27:35 PM PDT 24
Peak memory 210864 kb
Host smart-3a6b0b1a-7096-478f-90fc-2cdb3ba9fae4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506037774 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1506037774
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.428782985
Short name T143
Test name
Test status
Simulation time 115341824711 ps
CPU time 586.34 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:28:28 PM PDT 24
Peak memory 204960 kb
Host smart-18794bc3-526e-4ae1-86a8-dc97d68ab799
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428782985 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.428782985
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.748193877
Short name T90
Test name
Test status
Simulation time 142821847882 ps
CPU time 275.48 seconds
Started Jul 06 05:18:29 PM PDT 24
Finished Jul 06 05:23:05 PM PDT 24
Peak memory 201048 kb
Host smart-dfa0b6aa-2ab7-42da-8771-12c9a7766741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748193877 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.748193877
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2705383035
Short name T169
Test name
Test status
Simulation time 85352178045 ps
CPU time 228.74 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:22:36 PM PDT 24
Peak memory 200820 kb
Host smart-1f5cfa33-9089-4da7-a96a-3eb5a06537f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705383035 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2705383035
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2903364112
Short name T163
Test name
Test status
Simulation time 104338405341 ps
CPU time 33.28 seconds
Started Jul 06 05:18:44 PM PDT 24
Finished Jul 06 05:19:18 PM PDT 24
Peak memory 191988 kb
Host smart-2328fdc6-e333-416b-a241-84e58dd030ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903364112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2903364112
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3497727581
Short name T152
Test name
Test status
Simulation time 70233182920 ps
CPU time 18.54 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:19:07 PM PDT 24
Peak memory 191956 kb
Host smart-278d68a0-f745-46e8-84b4-ed6b72af6015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497727581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3497727581
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2705261824
Short name T132
Test name
Test status
Simulation time 145471445097 ps
CPU time 65.63 seconds
Started Jul 06 05:18:49 PM PDT 24
Finished Jul 06 05:19:55 PM PDT 24
Peak memory 198172 kb
Host smart-0e1529d8-d188-4667-98a7-d33a58188579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705261824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2705261824
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.959795275
Short name T141
Test name
Test status
Simulation time 31360660880 ps
CPU time 232.89 seconds
Started Jul 06 05:18:50 PM PDT 24
Finished Jul 06 05:22:43 PM PDT 24
Peak memory 214976 kb
Host smart-3d136861-941c-4388-908d-667b900c7787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959795275 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.959795275
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3977331922
Short name T84
Test name
Test status
Simulation time 350079970813 ps
CPU time 715.79 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:30:37 PM PDT 24
Peak memory 214876 kb
Host smart-dd45367d-76dd-4d27-8cd8-b6234736904e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977331922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3977331922
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3502102063
Short name T125
Test name
Test status
Simulation time 577892843 ps
CPU time 0.86 seconds
Started Jul 06 05:18:54 PM PDT 24
Finished Jul 06 05:18:56 PM PDT 24
Peak memory 196668 kb
Host smart-41592cd4-7a52-414d-b8b5-e029ea55583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502102063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3502102063
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3268362129
Short name T156
Test name
Test status
Simulation time 74063471154 ps
CPU time 178.54 seconds
Started Jul 06 05:18:43 PM PDT 24
Finished Jul 06 05:21:42 PM PDT 24
Peak memory 199264 kb
Host smart-3905db4f-a537-4b82-b8cf-7531080b139f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268362129 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3268362129
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2745596835
Short name T138
Test name
Test status
Simulation time 370067863 ps
CPU time 1.14 seconds
Started Jul 06 05:19:09 PM PDT 24
Finished Jul 06 05:19:10 PM PDT 24
Peak memory 196708 kb
Host smart-7ac61957-fda3-4502-8045-0a3f0b2a4e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745596835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2745596835
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3466690047
Short name T150
Test name
Test status
Simulation time 362924153 ps
CPU time 1.15 seconds
Started Jul 06 05:19:06 PM PDT 24
Finished Jul 06 05:19:08 PM PDT 24
Peak memory 196788 kb
Host smart-2cc383df-9fcd-4855-87cd-31db57570143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466690047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3466690047
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1071041549
Short name T82
Test name
Test status
Simulation time 64770205945 ps
CPU time 355.33 seconds
Started Jul 06 05:18:40 PM PDT 24
Finished Jul 06 05:24:36 PM PDT 24
Peak memory 198800 kb
Host smart-f81c5b2d-7251-4209-be6f-adafae541d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071041549 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1071041549
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4288377485
Short name T45
Test name
Test status
Simulation time 406300189644 ps
CPU time 225.3 seconds
Started Jul 06 05:18:45 PM PDT 24
Finished Jul 06 05:22:30 PM PDT 24
Peak memory 200416 kb
Host smart-b3b46831-fc11-46d2-83ea-f570c1b6708e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288377485 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4288377485
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3206856858
Short name T147
Test name
Test status
Simulation time 95546147589 ps
CPU time 33.36 seconds
Started Jul 06 05:18:52 PM PDT 24
Finished Jul 06 05:19:26 PM PDT 24
Peak memory 198240 kb
Host smart-11c6faf3-d8d6-4155-91ab-850058d86cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206856858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3206856858
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2729403241
Short name T142
Test name
Test status
Simulation time 72794207076 ps
CPU time 58.94 seconds
Started Jul 06 05:18:49 PM PDT 24
Finished Jul 06 05:19:49 PM PDT 24
Peak memory 193076 kb
Host smart-445191c3-a380-4eaf-98ca-290f32ceab0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729403241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2729403241
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1405496079
Short name T119
Test name
Test status
Simulation time 100127755024 ps
CPU time 310.42 seconds
Started Jul 06 05:19:06 PM PDT 24
Finished Jul 06 05:24:17 PM PDT 24
Peak memory 201588 kb
Host smart-513f1ec2-1a17-451a-9b23-9434636869db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405496079 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1405496079
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2220603630
Short name T137
Test name
Test status
Simulation time 445218161 ps
CPU time 0.96 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:18:43 PM PDT 24
Peak memory 196724 kb
Host smart-9e497b9e-ce07-410b-bd91-e1a67213c278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220603630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2220603630
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3894618534
Short name T162
Test name
Test status
Simulation time 563943824 ps
CPU time 0.95 seconds
Started Jul 06 05:18:49 PM PDT 24
Finished Jul 06 05:18:51 PM PDT 24
Peak memory 196800 kb
Host smart-8fc71c02-7473-464e-80fc-c1d6c750488f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894618534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3894618534
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3955143611
Short name T85
Test name
Test status
Simulation time 198143831167 ps
CPU time 490.05 seconds
Started Jul 06 05:19:20 PM PDT 24
Finished Jul 06 05:27:30 PM PDT 24
Peak memory 211720 kb
Host smart-fbedf6b1-72bf-4946-ba29-6dd7734c96ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955143611 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3955143611
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1156642628
Short name T133
Test name
Test status
Simulation time 21909821614 ps
CPU time 177.17 seconds
Started Jul 06 05:18:52 PM PDT 24
Finished Jul 06 05:21:50 PM PDT 24
Peak memory 206740 kb
Host smart-ab1abd35-6d01-49d5-bed2-e5d64e46ed39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156642628 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1156642628
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2329570049
Short name T167
Test name
Test status
Simulation time 87190435086 ps
CPU time 228.18 seconds
Started Jul 06 05:18:19 PM PDT 24
Finished Jul 06 05:22:08 PM PDT 24
Peak memory 209028 kb
Host smart-f27420fc-91ff-4ef4-9a30-e73d291f2d3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329570049 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2329570049
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4083902246
Short name T134
Test name
Test status
Simulation time 376353129 ps
CPU time 0.69 seconds
Started Jul 06 05:18:12 PM PDT 24
Finished Jul 06 05:18:13 PM PDT 24
Peak memory 196732 kb
Host smart-943d2b2c-a16b-49a8-b5d8-6f18ea0b008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083902246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4083902246
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2643036650
Short name T146
Test name
Test status
Simulation time 487094839 ps
CPU time 0.73 seconds
Started Jul 06 05:18:34 PM PDT 24
Finished Jul 06 05:18:36 PM PDT 24
Peak memory 196784 kb
Host smart-a1c60f76-6e18-47e1-a92c-dfba1690a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643036650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2643036650
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1160400429
Short name T75
Test name
Test status
Simulation time 619685958 ps
CPU time 0.72 seconds
Started Jul 06 05:18:37 PM PDT 24
Finished Jul 06 05:18:38 PM PDT 24
Peak memory 196772 kb
Host smart-dbeddaca-0d7e-4952-9717-f1362cb2911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160400429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1160400429
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.4263504181
Short name T154
Test name
Test status
Simulation time 528137382 ps
CPU time 0.8 seconds
Started Jul 06 05:18:35 PM PDT 24
Finished Jul 06 05:18:37 PM PDT 24
Peak memory 196768 kb
Host smart-deb9bd68-3c74-4c0f-b7f0-3e36ab136bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263504181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.4263504181
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1871788753
Short name T159
Test name
Test status
Simulation time 362343410 ps
CPU time 0.74 seconds
Started Jul 06 05:18:30 PM PDT 24
Finished Jul 06 05:18:31 PM PDT 24
Peak memory 196744 kb
Host smart-39913478-80ca-4938-ba6b-04430faa4310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871788753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1871788753
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3738014422
Short name T19
Test name
Test status
Simulation time 500833045252 ps
CPU time 203.58 seconds
Started Jul 06 05:18:52 PM PDT 24
Finished Jul 06 05:22:16 PM PDT 24
Peak memory 198340 kb
Host smart-113055d5-54f0-4f5a-b7c3-5b36147d9b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738014422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3738014422
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1981071627
Short name T116
Test name
Test status
Simulation time 411160154 ps
CPU time 0.91 seconds
Started Jul 06 05:18:16 PM PDT 24
Finished Jul 06 05:18:17 PM PDT 24
Peak memory 196732 kb
Host smart-62e20fdb-d37e-458b-8bfd-56738b99ae36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981071627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1981071627
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2710666426
Short name T32
Test name
Test status
Simulation time 583208379 ps
CPU time 0.65 seconds
Started Jul 06 05:18:50 PM PDT 24
Finished Jul 06 05:18:51 PM PDT 24
Peak memory 196736 kb
Host smart-3866d435-111c-45a5-ab67-764eeec14967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710666426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2710666426
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2121479602
Short name T174
Test name
Test status
Simulation time 139148254930 ps
CPU time 98.91 seconds
Started Jul 06 05:18:13 PM PDT 24
Finished Jul 06 05:19:52 PM PDT 24
Peak memory 192992 kb
Host smart-fd9ace9a-260f-412c-818e-f2ada443e5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121479602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2121479602
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1578864783
Short name T48
Test name
Test status
Simulation time 484892777 ps
CPU time 0.82 seconds
Started Jul 06 05:18:34 PM PDT 24
Finished Jul 06 05:18:36 PM PDT 24
Peak memory 196712 kb
Host smart-10df8cfa-4959-41dd-925c-15d40ea74d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578864783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1578864783
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4134236630
Short name T128
Test name
Test status
Simulation time 346268928 ps
CPU time 1.02 seconds
Started Jul 06 05:18:44 PM PDT 24
Finished Jul 06 05:18:45 PM PDT 24
Peak memory 196620 kb
Host smart-8f4ca869-f5a2-49f0-b9f2-bd88ccb475d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134236630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4134236630
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1557426617
Short name T111
Test name
Test status
Simulation time 531227970 ps
CPU time 0.75 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:18:42 PM PDT 24
Peak memory 196772 kb
Host smart-c5fc6f3b-ce8c-4c5b-b003-f21e8cd97997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557426617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1557426617
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1959489363
Short name T149
Test name
Test status
Simulation time 356382895 ps
CPU time 0.86 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:18:50 PM PDT 24
Peak memory 196712 kb
Host smart-5f37d42c-eab0-48b2-a713-b44724d627cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959489363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1959489363
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.706997852
Short name T181
Test name
Test status
Simulation time 89321705017 ps
CPU time 184.43 seconds
Started Jul 06 05:18:18 PM PDT 24
Finished Jul 06 05:21:23 PM PDT 24
Peak memory 200004 kb
Host smart-2a4ee808-6657-4492-964c-ca2e8d781977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706997852 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.706997852
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3877624940
Short name T135
Test name
Test status
Simulation time 411778730 ps
CPU time 0.7 seconds
Started Jul 06 05:18:53 PM PDT 24
Finished Jul 06 05:18:54 PM PDT 24
Peak memory 196784 kb
Host smart-71b00028-deef-4887-b4eb-462e9aefbe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877624940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3877624940
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1747820744
Short name T158
Test name
Test status
Simulation time 663480971 ps
CPU time 0.72 seconds
Started Jul 06 05:18:20 PM PDT 24
Finished Jul 06 05:18:21 PM PDT 24
Peak memory 196728 kb
Host smart-9b39d4a0-15fa-478a-873d-7c6f9e2274a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747820744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1747820744
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2207893724
Short name T115
Test name
Test status
Simulation time 370397866 ps
CPU time 1.09 seconds
Started Jul 06 05:18:30 PM PDT 24
Finished Jul 06 05:18:32 PM PDT 24
Peak memory 196676 kb
Host smart-ed75f6d8-3a10-4519-b478-7cc2b88bb773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207893724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2207893724
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.740538827
Short name T89
Test name
Test status
Simulation time 11575147375 ps
CPU time 80.05 seconds
Started Jul 06 05:18:32 PM PDT 24
Finished Jul 06 05:19:53 PM PDT 24
Peak memory 214860 kb
Host smart-0dd2be77-4d7d-4cfc-82fb-c47656324809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740538827 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.740538827
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1663629092
Short name T153
Test name
Test status
Simulation time 416970602 ps
CPU time 0.79 seconds
Started Jul 06 05:18:31 PM PDT 24
Finished Jul 06 05:18:32 PM PDT 24
Peak memory 196784 kb
Host smart-35b94407-6bc7-47fb-bc66-c80378fff235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663629092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1663629092
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1211770282
Short name T173
Test name
Test status
Simulation time 656315308904 ps
CPU time 133.42 seconds
Started Jul 06 05:18:36 PM PDT 24
Finished Jul 06 05:20:50 PM PDT 24
Peak memory 198360 kb
Host smart-f2356575-c8c1-4f31-8eda-b1b873198757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211770282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1211770282
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2308834621
Short name T25
Test name
Test status
Simulation time 345316279 ps
CPU time 1.2 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:18:50 PM PDT 24
Peak memory 196820 kb
Host smart-480d03a3-c52c-48ac-a127-4ef68ebd71bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308834621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2308834621
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.4182322893
Short name T164
Test name
Test status
Simulation time 480794887 ps
CPU time 1.33 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:18:42 PM PDT 24
Peak memory 196828 kb
Host smart-4fef781a-ac58-4911-863d-1960f79762f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182322893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.4182322893
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1218705559
Short name T123
Test name
Test status
Simulation time 8271990729 ps
CPU time 3.28 seconds
Started Jul 06 05:18:43 PM PDT 24
Finished Jul 06 05:18:47 PM PDT 24
Peak memory 191984 kb
Host smart-546a5909-6190-4458-805b-4229a8a5275b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218705559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1218705559
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2434625236
Short name T2
Test name
Test status
Simulation time 417670770 ps
CPU time 0.89 seconds
Started Jul 06 05:18:57 PM PDT 24
Finished Jul 06 05:18:58 PM PDT 24
Peak memory 196716 kb
Host smart-4bfa8dc7-9884-419e-acee-51ac8b251e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434625236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2434625236
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.723443768
Short name T165
Test name
Test status
Simulation time 46273207546 ps
CPU time 19.47 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:19:08 PM PDT 24
Peak memory 193024 kb
Host smart-a9589bd9-ad3f-4aea-bd80-59174317d89c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723443768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.723443768
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2624728682
Short name T103
Test name
Test status
Simulation time 574350313 ps
CPU time 1.42 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:18:50 PM PDT 24
Peak memory 196784 kb
Host smart-d1f8e428-5af9-4d01-9802-29c9fa10f4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624728682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2624728682
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1167136354
Short name T145
Test name
Test status
Simulation time 505899750 ps
CPU time 1.29 seconds
Started Jul 06 05:18:59 PM PDT 24
Finished Jul 06 05:19:01 PM PDT 24
Peak memory 196704 kb
Host smart-2f04510d-de19-435d-98af-a15411408c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167136354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1167136354
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2534416191
Short name T121
Test name
Test status
Simulation time 536787277 ps
CPU time 1.34 seconds
Started Jul 06 05:18:49 PM PDT 24
Finished Jul 06 05:18:51 PM PDT 24
Peak memory 196780 kb
Host smart-12e8e5c4-db83-4da0-900c-0626c6d53096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534416191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2534416191
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2877297087
Short name T185
Test name
Test status
Simulation time 74473799033 ps
CPU time 379.8 seconds
Started Jul 06 05:18:36 PM PDT 24
Finished Jul 06 05:24:56 PM PDT 24
Peak memory 209848 kb
Host smart-6eb108dd-acda-482a-a7ff-1ca1c76a1e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877297087 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2877297087
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.4066215917
Short name T176
Test name
Test status
Simulation time 401004901 ps
CPU time 1.15 seconds
Started Jul 06 05:18:46 PM PDT 24
Finished Jul 06 05:18:47 PM PDT 24
Peak memory 196708 kb
Host smart-6d3017e6-3f78-49e0-9ea8-600316fb163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066215917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.4066215917
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1542138555
Short name T160
Test name
Test status
Simulation time 10272506596 ps
CPU time 77.44 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:20:09 PM PDT 24
Peak memory 198628 kb
Host smart-83d9f2ab-9dc3-4d71-92ca-c5d3bae8eaf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542138555 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1542138555
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1270686824
Short name T117
Test name
Test status
Simulation time 165305461775 ps
CPU time 228.21 seconds
Started Jul 06 05:18:16 PM PDT 24
Finished Jul 06 05:22:04 PM PDT 24
Peak memory 193060 kb
Host smart-9219cefa-acb3-4a46-bfea-8e4a9eacf20d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270686824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1270686824
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1312692561
Short name T188
Test name
Test status
Simulation time 491806847 ps
CPU time 0.68 seconds
Started Jul 06 05:18:54 PM PDT 24
Finished Jul 06 05:18:56 PM PDT 24
Peak memory 196708 kb
Host smart-5793b3de-57a7-4806-9ff8-992c515ab65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312692561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1312692561
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.287211831
Short name T24
Test name
Test status
Simulation time 588182409 ps
CPU time 0.89 seconds
Started Jul 06 05:18:16 PM PDT 24
Finished Jul 06 05:18:17 PM PDT 24
Peak memory 196712 kb
Host smart-69e318f7-3f5d-4037-ad0e-7604841f54e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287211831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.287211831
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1606978643
Short name T182
Test name
Test status
Simulation time 521237302 ps
CPU time 1.34 seconds
Started Jul 06 05:18:10 PM PDT 24
Finished Jul 06 05:18:11 PM PDT 24
Peak memory 196696 kb
Host smart-30695338-d472-4f1a-a633-36a7bb871475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606978643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1606978643
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1931427075
Short name T184
Test name
Test status
Simulation time 351482908 ps
CPU time 0.71 seconds
Started Jul 06 05:18:39 PM PDT 24
Finished Jul 06 05:18:39 PM PDT 24
Peak memory 196668 kb
Host smart-7396e722-ac5a-4486-bdbc-76cdf426edb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931427075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1931427075
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2550856879
Short name T189
Test name
Test status
Simulation time 583174285 ps
CPU time 1.05 seconds
Started Jul 06 05:18:15 PM PDT 24
Finished Jul 06 05:18:16 PM PDT 24
Peak memory 196676 kb
Host smart-205990db-4cea-46e3-ad1f-42df7ec9fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550856879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2550856879
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.877249424
Short name T4
Test name
Test status
Simulation time 480757568 ps
CPU time 1.11 seconds
Started Jul 06 05:18:44 PM PDT 24
Finished Jul 06 05:18:46 PM PDT 24
Peak memory 196724 kb
Host smart-6c07379e-08d0-41ac-a222-5cd21d92a26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877249424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.877249424
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.747389729
Short name T190
Test name
Test status
Simulation time 552688134 ps
CPU time 0.97 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:18:49 PM PDT 24
Peak memory 196772 kb
Host smart-1b3e51d7-7729-4f07-aeaf-e946bda2a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747389729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.747389729
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.446610769
Short name T183
Test name
Test status
Simulation time 529918593 ps
CPU time 1.33 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:18:50 PM PDT 24
Peak memory 196696 kb
Host smart-040afd56-c90c-40c5-b15d-c5dcf586d1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446610769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.446610769
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.905160341
Short name T139
Test name
Test status
Simulation time 590630948 ps
CPU time 0.83 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:18:50 PM PDT 24
Peak memory 196720 kb
Host smart-57abf7a3-ec61-44f9-ab5a-0e168a8659b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905160341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.905160341
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.136918332
Short name T177
Test name
Test status
Simulation time 552755868 ps
CPU time 0.82 seconds
Started Jul 06 05:19:04 PM PDT 24
Finished Jul 06 05:19:06 PM PDT 24
Peak memory 196804 kb
Host smart-6cb614bd-856f-47eb-8b87-888a98e7bd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136918332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.136918332
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2992086105
Short name T179
Test name
Test status
Simulation time 554583738 ps
CPU time 1.49 seconds
Started Jul 06 05:18:19 PM PDT 24
Finished Jul 06 05:18:21 PM PDT 24
Peak memory 196700 kb
Host smart-ed085b99-ce3f-4c9f-a03d-8440a4e3d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992086105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2992086105
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.850548938
Short name T193
Test name
Test status
Simulation time 8287539861 ps
CPU time 12.91 seconds
Started Jul 06 06:31:49 PM PDT 24
Finished Jul 06 06:32:02 PM PDT 24
Peak memory 198372 kb
Host smart-1ab4637e-ff6b-4251-81ce-7af14b3aae69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850548938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.850548938
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.961546802
Short name T187
Test name
Test status
Simulation time 388508251 ps
CPU time 1.17 seconds
Started Jul 06 05:18:20 PM PDT 24
Finished Jul 06 05:18:21 PM PDT 24
Peak memory 196728 kb
Host smart-74ae01fc-facd-414b-8400-cd6f2e1f35c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961546802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.961546802
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.524240147
Short name T172
Test name
Test status
Simulation time 629199909893 ps
CPU time 419.9 seconds
Started Jul 06 05:18:29 PM PDT 24
Finished Jul 06 05:25:30 PM PDT 24
Peak memory 193084 kb
Host smart-898cfb52-d9a1-4588-8e54-417ce5a177b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524240147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.524240147
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2217931226
Short name T191
Test name
Test status
Simulation time 268671453239 ps
CPU time 58.46 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:19:41 PM PDT 24
Peak memory 192988 kb
Host smart-e46ab9d4-455d-4c47-8f58-04a95f1efcf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217931226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2217931226
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1743782156
Short name T180
Test name
Test status
Simulation time 434251350 ps
CPU time 0.65 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:18:42 PM PDT 24
Peak memory 196692 kb
Host smart-5c3f1971-090a-4282-bc4c-4a52e2de0f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743782156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1743782156
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4196993176
Short name T92
Test name
Test status
Simulation time 467730362 ps
CPU time 0.9 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:18:43 PM PDT 24
Peak memory 196708 kb
Host smart-7bbee3fb-ddd7-4b62-840a-23dbc575c8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196993176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4196993176
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2116755481
Short name T23
Test name
Test status
Simulation time 522323484 ps
CPU time 0.84 seconds
Started Jul 06 05:18:28 PM PDT 24
Finished Jul 06 05:18:29 PM PDT 24
Peak memory 196764 kb
Host smart-49e28614-29cc-492a-91b5-e0ca76b254d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116755481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2116755481
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2558415993
Short name T10
Test name
Test status
Simulation time 426042588 ps
CPU time 1.25 seconds
Started Jul 06 05:18:43 PM PDT 24
Finished Jul 06 05:18:45 PM PDT 24
Peak memory 196712 kb
Host smart-2eaab657-5d72-453b-a617-12d0e6c0668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558415993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2558415993
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.315367771
Short name T171
Test name
Test status
Simulation time 576552541 ps
CPU time 0.79 seconds
Started Jul 06 05:18:44 PM PDT 24
Finished Jul 06 05:18:45 PM PDT 24
Peak memory 196804 kb
Host smart-a53d224f-7755-4904-a263-dcf83a635b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315367771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.315367771
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2876774309
Short name T166
Test name
Test status
Simulation time 466673474 ps
CPU time 0.64 seconds
Started Jul 06 05:19:06 PM PDT 24
Finished Jul 06 05:19:08 PM PDT 24
Peak memory 196672 kb
Host smart-e0eaed42-a790-49da-b2a3-93e7ae02907a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876774309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2876774309
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2670915483
Short name T329
Test name
Test status
Simulation time 473354293 ps
CPU time 0.78 seconds
Started Jul 06 06:31:50 PM PDT 24
Finished Jul 06 06:31:51 PM PDT 24
Peak memory 193376 kb
Host smart-375ad104-9e4f-4255-ba2f-f837ecef1237
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670915483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2670915483
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.717300766
Short name T56
Test name
Test status
Simulation time 13359011990 ps
CPU time 10 seconds
Started Jul 06 06:31:50 PM PDT 24
Finished Jul 06 06:32:01 PM PDT 24
Peak memory 184064 kb
Host smart-99d4d0c4-fe94-4360-bc04-a7736a2f5e85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717300766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.717300766
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3414829803
Short name T324
Test name
Test status
Simulation time 942071056 ps
CPU time 0.87 seconds
Started Jul 06 06:31:52 PM PDT 24
Finished Jul 06 06:31:53 PM PDT 24
Peak memory 192988 kb
Host smart-cfce2887-bb39-4a62-b9a3-35ee37e03a6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414829803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3414829803
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.595127408
Short name T390
Test name
Test status
Simulation time 594597268 ps
CPU time 0.79 seconds
Started Jul 06 06:31:49 PM PDT 24
Finished Jul 06 06:31:51 PM PDT 24
Peak memory 196416 kb
Host smart-9104c176-49a4-48ce-9a94-2fcd378db071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595127408 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.595127408
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1669836922
Short name T370
Test name
Test status
Simulation time 469285390 ps
CPU time 0.86 seconds
Started Jul 06 06:31:50 PM PDT 24
Finished Jul 06 06:31:51 PM PDT 24
Peak memory 192096 kb
Host smart-22accfa6-ca56-4904-a07e-f261993bf3dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669836922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1669836922
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.181112977
Short name T373
Test name
Test status
Simulation time 474336396 ps
CPU time 0.75 seconds
Started Jul 06 06:31:52 PM PDT 24
Finished Jul 06 06:31:53 PM PDT 24
Peak memory 183752 kb
Host smart-615b903a-26f2-46de-be01-0238c9cb2f5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181112977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.181112977
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2166760453
Short name T420
Test name
Test status
Simulation time 511289672 ps
CPU time 1.2 seconds
Started Jul 06 06:31:49 PM PDT 24
Finished Jul 06 06:31:51 PM PDT 24
Peak memory 183696 kb
Host smart-209a0b4f-ccb5-4051-a311-d7db57eed406
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166760453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2166760453
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1187692575
Short name T404
Test name
Test status
Simulation time 366766518 ps
CPU time 0.65 seconds
Started Jul 06 06:31:52 PM PDT 24
Finished Jul 06 06:31:53 PM PDT 24
Peak memory 183732 kb
Host smart-4e54d4be-ca44-4144-b899-a2bbb916a443
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187692575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1187692575
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2160725006
Short name T349
Test name
Test status
Simulation time 1458844769 ps
CPU time 1.19 seconds
Started Jul 06 06:31:50 PM PDT 24
Finished Jul 06 06:31:52 PM PDT 24
Peak memory 193684 kb
Host smart-5184ae74-3dad-42c5-b6fd-283bd1b89b8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160725006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2160725006
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1574088156
Short name T363
Test name
Test status
Simulation time 374211719 ps
CPU time 1.76 seconds
Started Jul 06 06:31:45 PM PDT 24
Finished Jul 06 06:31:48 PM PDT 24
Peak memory 198628 kb
Host smart-64d7cfd3-7f0f-43cd-a8f8-d11e17f35bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574088156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1574088156
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1039176627
Short name T366
Test name
Test status
Simulation time 8174123138 ps
CPU time 3.89 seconds
Started Jul 06 06:31:49 PM PDT 24
Finished Jul 06 06:31:53 PM PDT 24
Peak memory 198308 kb
Host smart-001442db-e6c9-411f-b97d-a2ec2986399d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039176627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1039176627
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2421906528
Short name T344
Test name
Test status
Simulation time 7372102002 ps
CPU time 18.59 seconds
Started Jul 06 06:32:01 PM PDT 24
Finished Jul 06 06:32:20 PM PDT 24
Peak memory 192260 kb
Host smart-47488b95-3efd-44eb-b0a6-0a2076a24e4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421906528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2421906528
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2314051848
Short name T374
Test name
Test status
Simulation time 942469790 ps
CPU time 1.89 seconds
Started Jul 06 06:31:55 PM PDT 24
Finished Jul 06 06:31:57 PM PDT 24
Peak memory 193000 kb
Host smart-1f4f0d51-8c7b-4399-b920-5b36f2cce84e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314051848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2314051848
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3309529279
Short name T375
Test name
Test status
Simulation time 444873559 ps
CPU time 1.34 seconds
Started Jul 06 06:31:54 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 196024 kb
Host smart-dc7a408c-ae54-47ef-b9f3-24b20e6a993b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309529279 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3309529279
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.226037701
Short name T39
Test name
Test status
Simulation time 508845237 ps
CPU time 1.22 seconds
Started Jul 06 06:31:55 PM PDT 24
Finished Jul 06 06:31:57 PM PDT 24
Peak memory 193468 kb
Host smart-d57ca74a-d47a-453c-bdb9-c1ff48fc2a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226037701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.226037701
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2517399090
Short name T395
Test name
Test status
Simulation time 388332935 ps
CPU time 1.11 seconds
Started Jul 06 06:31:50 PM PDT 24
Finished Jul 06 06:31:51 PM PDT 24
Peak memory 192996 kb
Host smart-c5ec9b62-e006-418a-9d0c-18d23741aff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517399090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2517399090
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3450771079
Short name T314
Test name
Test status
Simulation time 529310040 ps
CPU time 0.72 seconds
Started Jul 06 06:31:54 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 183688 kb
Host smart-eb92bd7c-2b01-4121-85c0-6de6f60b7555
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450771079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3450771079
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2131464588
Short name T326
Test name
Test status
Simulation time 510008048 ps
CPU time 0.72 seconds
Started Jul 06 06:31:51 PM PDT 24
Finished Jul 06 06:31:52 PM PDT 24
Peak memory 183760 kb
Host smart-cfa43cd2-da01-4fdf-8f7c-633d070717ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131464588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2131464588
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4064418417
Short name T70
Test name
Test status
Simulation time 1339652071 ps
CPU time 1.22 seconds
Started Jul 06 06:31:55 PM PDT 24
Finished Jul 06 06:31:57 PM PDT 24
Peak memory 194088 kb
Host smart-6101da0b-925c-4467-97c0-c908dcf235e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064418417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4064418417
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4236974824
Short name T318
Test name
Test status
Simulation time 655888743 ps
CPU time 1.99 seconds
Started Jul 06 06:31:49 PM PDT 24
Finished Jul 06 06:31:52 PM PDT 24
Peak memory 198632 kb
Host smart-30a92ad3-0449-4b08-b50b-e14fd5160a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236974824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4236974824
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2224716967
Short name T372
Test name
Test status
Simulation time 517865366 ps
CPU time 1.18 seconds
Started Jul 06 06:32:08 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 195844 kb
Host smart-6602cbfc-f5e5-4191-9a7d-29922b36531c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224716967 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2224716967
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4178473638
Short name T195
Test name
Test status
Simulation time 379969801 ps
CPU time 0.91 seconds
Started Jul 06 06:32:04 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 193420 kb
Host smart-2d05ba2c-3be6-447b-aa2b-b741f9d1b7a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178473638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4178473638
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3939637168
Short name T287
Test name
Test status
Simulation time 473673566 ps
CPU time 0.87 seconds
Started Jul 06 06:32:04 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 183768 kb
Host smart-10297212-0960-4d58-a482-ef4d1eaef00d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939637168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3939637168
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2589208288
Short name T376
Test name
Test status
Simulation time 1535510037 ps
CPU time 3.51 seconds
Started Jul 06 06:32:14 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 183784 kb
Host smart-13db8d65-398a-4a49-840e-def5d87a6419
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589208288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2589208288
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3424752735
Short name T283
Test name
Test status
Simulation time 842668303 ps
CPU time 2.34 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 198640 kb
Host smart-4708c211-073e-4a54-befb-944e11b736dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424752735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3424752735
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1209102086
Short name T319
Test name
Test status
Simulation time 4394449342 ps
CPU time 2 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 197748 kb
Host smart-3f241441-3b62-4377-ad13-002b0d6cd0a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209102086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1209102086
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3058669370
Short name T293
Test name
Test status
Simulation time 378021578 ps
CPU time 0.9 seconds
Started Jul 06 06:32:43 PM PDT 24
Finished Jul 06 06:32:44 PM PDT 24
Peak memory 197912 kb
Host smart-513b4315-80e7-49df-b598-6113461a37c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058669370 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3058669370
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2835619452
Short name T62
Test name
Test status
Simulation time 382723728 ps
CPU time 0.67 seconds
Started Jul 06 06:32:08 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 192080 kb
Host smart-bba1283b-3674-4f67-9ce4-d29f86da12a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835619452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2835619452
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1280611797
Short name T371
Test name
Test status
Simulation time 299092024 ps
CPU time 0.87 seconds
Started Jul 06 06:32:08 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 183768 kb
Host smart-02fff18a-909a-4ea8-80bb-46f1a3997c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280611797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1280611797
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2405226916
Short name T351
Test name
Test status
Simulation time 1210835550 ps
CPU time 2.07 seconds
Started Jul 06 06:32:08 PM PDT 24
Finished Jul 06 06:32:10 PM PDT 24
Peak memory 193088 kb
Host smart-f5548832-ff14-4367-86bb-93f1a9ec6f24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405226916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2405226916
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1979735357
Short name T389
Test name
Test status
Simulation time 542785244 ps
CPU time 2.14 seconds
Started Jul 06 06:32:09 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 198688 kb
Host smart-b67fd69f-8e67-4486-80ed-452b1ea22781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979735357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1979735357
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2006700230
Short name T405
Test name
Test status
Simulation time 8080652554 ps
CPU time 11.51 seconds
Started Jul 06 06:32:06 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 198248 kb
Host smart-f10da526-56ee-4a0d-9b19-7e18d00ed08e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006700230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2006700230
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1987042678
Short name T352
Test name
Test status
Simulation time 403413965 ps
CPU time 0.82 seconds
Started Jul 06 06:32:09 PM PDT 24
Finished Jul 06 06:32:11 PM PDT 24
Peak memory 195996 kb
Host smart-fb02e2de-96aa-4aca-8483-f23423d354ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987042678 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1987042678
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.402984857
Short name T198
Test name
Test status
Simulation time 521658182 ps
CPU time 0.95 seconds
Started Jul 06 06:32:15 PM PDT 24
Finished Jul 06 06:32:17 PM PDT 24
Peak memory 192060 kb
Host smart-92bbbf52-3b2f-40c9-bcb2-0841c469d7f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402984857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.402984857
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3401053389
Short name T365
Test name
Test status
Simulation time 389217954 ps
CPU time 0.61 seconds
Started Jul 06 06:32:09 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 192976 kb
Host smart-ea70c9cf-fab9-4ebd-b098-5a2b3948ed3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401053389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3401053389
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1242155050
Short name T35
Test name
Test status
Simulation time 1183836005 ps
CPU time 2.83 seconds
Started Jul 06 06:32:15 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 183784 kb
Host smart-edebe45e-06c3-4bb3-9392-34f264b255d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242155050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1242155050
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.115924644
Short name T316
Test name
Test status
Simulation time 440043991 ps
CPU time 2.08 seconds
Started Jul 06 06:32:15 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 198616 kb
Host smart-f580a1a0-3bce-433e-b714-a0a3ec93793f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115924644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.115924644
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.950767316
Short name T196
Test name
Test status
Simulation time 440850822 ps
CPU time 0.83 seconds
Started Jul 06 06:32:10 PM PDT 24
Finished Jul 06 06:32:11 PM PDT 24
Peak memory 197028 kb
Host smart-03be270b-b0f9-4265-a8ff-d39a606243ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950767316 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.950767316
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1757348481
Short name T68
Test name
Test status
Simulation time 519411829 ps
CPU time 1.37 seconds
Started Jul 06 06:32:10 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 193968 kb
Host smart-130a7573-41b5-49b5-a977-5b62325c3b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757348481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1757348481
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3125184448
Short name T334
Test name
Test status
Simulation time 424333232 ps
CPU time 0.7 seconds
Started Jul 06 06:32:07 PM PDT 24
Finished Jul 06 06:32:08 PM PDT 24
Peak memory 183776 kb
Host smart-6714913e-7092-44d0-8631-cbe3a273f39e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125184448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3125184448
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.364571349
Short name T398
Test name
Test status
Simulation time 2335687342 ps
CPU time 2.35 seconds
Started Jul 06 06:32:15 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 195064 kb
Host smart-c7acb4bf-c535-4bee-baad-695631d5bfa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364571349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.364571349
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3946286615
Short name T332
Test name
Test status
Simulation time 512205542 ps
CPU time 1.37 seconds
Started Jul 06 06:32:09 PM PDT 24
Finished Jul 06 06:32:11 PM PDT 24
Peak memory 198488 kb
Host smart-b972ba04-1cf5-45e4-94e2-7e2f611efb8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946286615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3946286615
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2072275435
Short name T335
Test name
Test status
Simulation time 4147603027 ps
CPU time 6.54 seconds
Started Jul 06 06:32:10 PM PDT 24
Finished Jul 06 06:32:16 PM PDT 24
Peak memory 198108 kb
Host smart-084cba33-41a1-409a-8ca1-2d1a46744479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072275435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2072275435
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2040227191
Short name T360
Test name
Test status
Simulation time 462578816 ps
CPU time 0.9 seconds
Started Jul 06 06:32:14 PM PDT 24
Finished Jul 06 06:32:15 PM PDT 24
Peak memory 195788 kb
Host smart-8a592124-a491-4c90-821b-d43b293ea666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040227191 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2040227191
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3388079097
Short name T330
Test name
Test status
Simulation time 486559073 ps
CPU time 1.21 seconds
Started Jul 06 06:32:06 PM PDT 24
Finished Jul 06 06:32:08 PM PDT 24
Peak memory 192104 kb
Host smart-8df44a77-57d5-49e4-a3c9-075247625559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388079097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3388079097
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1394042964
Short name T378
Test name
Test status
Simulation time 503395212 ps
CPU time 0.88 seconds
Started Jul 06 06:32:10 PM PDT 24
Finished Jul 06 06:32:11 PM PDT 24
Peak memory 183780 kb
Host smart-1fd35a25-ea99-4a0a-acba-0ade0a100899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394042964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1394042964
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3489530330
Short name T33
Test name
Test status
Simulation time 1858263226 ps
CPU time 1.16 seconds
Started Jul 06 06:32:09 PM PDT 24
Finished Jul 06 06:32:10 PM PDT 24
Peak memory 193072 kb
Host smart-e7546036-1b1f-4ba9-9176-fda172c96d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489530330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3489530330
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.131135643
Short name T392
Test name
Test status
Simulation time 568254291 ps
CPU time 2.21 seconds
Started Jul 06 06:32:07 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 198672 kb
Host smart-e83d861d-05e6-4fde-b5e5-b112d0dc471a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131135643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.131135643
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1690386564
Short name T300
Test name
Test status
Simulation time 8593655163 ps
CPU time 1.74 seconds
Started Jul 06 06:32:06 PM PDT 24
Finished Jul 06 06:32:08 PM PDT 24
Peak memory 198296 kb
Host smart-1ac15e1f-2300-4f5e-b03e-650eee957755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690386564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1690386564
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1052443
Short name T367
Test name
Test status
Simulation time 358051442 ps
CPU time 0.8 seconds
Started Jul 06 06:32:11 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 196016 kb
Host smart-d4d852e1-a413-4432-abe4-d7649a5b3cc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052443 -assert nopostproc +UVM_TESTNAME=ao
n_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1052443
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2833457805
Short name T385
Test name
Test status
Simulation time 411501473 ps
CPU time 1.13 seconds
Started Jul 06 06:32:07 PM PDT 24
Finished Jul 06 06:32:08 PM PDT 24
Peak memory 192072 kb
Host smart-9b25cbbb-a0b7-4522-aff1-e5c484034c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833457805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2833457805
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2671806682
Short name T388
Test name
Test status
Simulation time 533996258 ps
CPU time 0.78 seconds
Started Jul 06 06:32:10 PM PDT 24
Finished Jul 06 06:32:11 PM PDT 24
Peak memory 183776 kb
Host smart-a7cf4b00-95c5-4d57-a439-6630411c1660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671806682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2671806682
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3331894803
Short name T418
Test name
Test status
Simulation time 1788330099 ps
CPU time 2.34 seconds
Started Jul 06 06:32:09 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 194976 kb
Host smart-8b5000d1-386e-4f2f-a394-8ab7b8d719ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331894803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3331894803
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3027410573
Short name T380
Test name
Test status
Simulation time 511430230 ps
CPU time 2.41 seconds
Started Jul 06 06:32:06 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 198644 kb
Host smart-15c1cfff-7c66-474c-9f21-09fdf4607fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027410573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3027410573
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3692661553
Short name T346
Test name
Test status
Simulation time 4521313717 ps
CPU time 2.39 seconds
Started Jul 06 06:32:10 PM PDT 24
Finished Jul 06 06:32:13 PM PDT 24
Peak memory 197752 kb
Host smart-828a4925-ae5e-46f5-ad98-564fec0bf66f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692661553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3692661553
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3714863643
Short name T290
Test name
Test status
Simulation time 371730951 ps
CPU time 1.17 seconds
Started Jul 06 06:32:13 PM PDT 24
Finished Jul 06 06:32:14 PM PDT 24
Peak memory 196360 kb
Host smart-59ca73cf-c88d-4190-95da-e43e2b79f699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714863643 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3714863643
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2434827046
Short name T408
Test name
Test status
Simulation time 375491565 ps
CPU time 0.84 seconds
Started Jul 06 06:32:13 PM PDT 24
Finished Jul 06 06:32:14 PM PDT 24
Peak memory 194028 kb
Host smart-6076f5f7-00d3-4cad-b101-2f8adc85fd59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434827046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2434827046
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1026166874
Short name T347
Test name
Test status
Simulation time 335904392 ps
CPU time 1 seconds
Started Jul 06 06:32:14 PM PDT 24
Finished Jul 06 06:32:15 PM PDT 24
Peak memory 192968 kb
Host smart-3581ad4b-7747-45cb-9d47-2fe82e295741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026166874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1026166874
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2988129062
Short name T350
Test name
Test status
Simulation time 1007550058 ps
CPU time 1.86 seconds
Started Jul 06 06:32:11 PM PDT 24
Finished Jul 06 06:32:13 PM PDT 24
Peak memory 193064 kb
Host smart-342a60ec-4217-4147-90d6-13b53298ae4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988129062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2988129062
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2144396649
Short name T305
Test name
Test status
Simulation time 431914059 ps
CPU time 1.8 seconds
Started Jul 06 06:32:16 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 198628 kb
Host smart-c92b9155-69e3-4773-8921-4a05c3f9de31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144396649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2144396649
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2950962628
Short name T296
Test name
Test status
Simulation time 4275795929 ps
CPU time 6.19 seconds
Started Jul 06 06:32:13 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 197624 kb
Host smart-97fa819b-b8c0-44a7-a711-92d81d4cbf38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950962628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2950962628
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3549711932
Short name T409
Test name
Test status
Simulation time 374058099 ps
CPU time 0.8 seconds
Started Jul 06 06:32:15 PM PDT 24
Finished Jul 06 06:32:16 PM PDT 24
Peak memory 195740 kb
Host smart-cc69c96f-75ed-432f-bdc8-df5a0eae0779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549711932 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3549711932
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2433478930
Short name T399
Test name
Test status
Simulation time 361408669 ps
CPU time 0.83 seconds
Started Jul 06 06:32:11 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 193132 kb
Host smart-27808307-d166-4d45-9776-80fb189b70cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433478930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2433478930
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3230133912
Short name T397
Test name
Test status
Simulation time 440820529 ps
CPU time 0.7 seconds
Started Jul 06 06:32:11 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 192948 kb
Host smart-0bfab055-a736-4d81-bd0b-32da9735d4d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230133912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3230133912
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.26464744
Short name T73
Test name
Test status
Simulation time 1810293183 ps
CPU time 1.22 seconds
Started Jul 06 06:32:12 PM PDT 24
Finished Jul 06 06:32:13 PM PDT 24
Peak memory 184052 kb
Host smart-42b2487d-e208-4ed3-a974-ec75a8aa8e29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26464744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_
timer_same_csr_outstanding.26464744
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3331295406
Short name T333
Test name
Test status
Simulation time 457892437 ps
CPU time 1.5 seconds
Started Jul 06 06:32:08 PM PDT 24
Finished Jul 06 06:32:10 PM PDT 24
Peak memory 198676 kb
Host smart-3c392c8d-6e58-44ae-8b4a-9e962a3e8349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331295406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3331295406
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.173114162
Short name T194
Test name
Test status
Simulation time 8932474867 ps
CPU time 4.19 seconds
Started Jul 06 06:32:13 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 198184 kb
Host smart-0a17de19-403e-44f1-8d7a-e44bcd164395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173114162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.173114162
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3209877150
Short name T303
Test name
Test status
Simulation time 461454360 ps
CPU time 0.79 seconds
Started Jul 06 06:32:11 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 196272 kb
Host smart-088234e3-0e72-43ab-adcd-b30408f10092
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209877150 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3209877150
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1518605689
Short name T69
Test name
Test status
Simulation time 441564206 ps
CPU time 0.78 seconds
Started Jul 06 06:32:13 PM PDT 24
Finished Jul 06 06:32:14 PM PDT 24
Peak memory 193432 kb
Host smart-05e6e0cb-4aba-4220-9692-5c1f5a8e5894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518605689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1518605689
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.575486853
Short name T411
Test name
Test status
Simulation time 373598402 ps
CPU time 0.71 seconds
Started Jul 06 06:32:18 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 183756 kb
Host smart-26a2e696-f0c6-45ba-9a9c-a454bd99ecd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575486853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.575486853
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1818442489
Short name T359
Test name
Test status
Simulation time 2668705011 ps
CPU time 1.03 seconds
Started Jul 06 06:32:11 PM PDT 24
Finished Jul 06 06:32:13 PM PDT 24
Peak memory 195056 kb
Host smart-32fb4815-e5a9-4869-9317-9bd6c958cc48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818442489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1818442489
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3096002222
Short name T301
Test name
Test status
Simulation time 614494459 ps
CPU time 2.69 seconds
Started Jul 06 06:32:11 PM PDT 24
Finished Jul 06 06:32:14 PM PDT 24
Peak memory 198696 kb
Host smart-c2416e0e-fe06-4d0d-ab8d-6543cab122eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096002222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3096002222
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.602674206
Short name T309
Test name
Test status
Simulation time 4327475161 ps
CPU time 2.37 seconds
Started Jul 06 06:32:11 PM PDT 24
Finished Jul 06 06:32:13 PM PDT 24
Peak memory 197828 kb
Host smart-28b4ac64-565c-4fb5-aa99-8aabbfeb9106
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602674206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.602674206
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.38132316
Short name T400
Test name
Test status
Simulation time 485775833 ps
CPU time 0.8 seconds
Started Jul 06 06:32:11 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 196064 kb
Host smart-2ee5029c-ebf3-4df8-b7ac-28bdd23e6972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38132316 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.38132316
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2541465198
Short name T402
Test name
Test status
Simulation time 340498428 ps
CPU time 0.61 seconds
Started Jul 06 06:32:12 PM PDT 24
Finished Jul 06 06:32:13 PM PDT 24
Peak memory 192960 kb
Host smart-22d98503-7cc4-4302-92d0-8cedd83bdf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541465198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2541465198
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1466327130
Short name T412
Test name
Test status
Simulation time 2449246804 ps
CPU time 1.6 seconds
Started Jul 06 06:32:13 PM PDT 24
Finished Jul 06 06:32:15 PM PDT 24
Peak memory 193928 kb
Host smart-8fb4bf53-c5d8-41e6-a6b4-8ed1ac59dd94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466327130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1466327130
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1261868163
Short name T323
Test name
Test status
Simulation time 394523459 ps
CPU time 1.51 seconds
Started Jul 06 06:32:14 PM PDT 24
Finished Jul 06 06:32:16 PM PDT 24
Peak memory 198356 kb
Host smart-60792a51-f5fc-42df-989f-5e99da45f369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261868163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1261868163
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.465695626
Short name T356
Test name
Test status
Simulation time 8478029924 ps
CPU time 7.81 seconds
Started Jul 06 06:32:12 PM PDT 24
Finished Jul 06 06:32:20 PM PDT 24
Peak memory 198468 kb
Host smart-f6678e83-be6f-4797-bc3b-a77ed1dc5c70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465695626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.465695626
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1872353399
Short name T64
Test name
Test status
Simulation time 582664763 ps
CPU time 0.85 seconds
Started Jul 06 06:31:54 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 183828 kb
Host smart-2394c965-8563-442d-bea4-ef0d9cbd65a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872353399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1872353399
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3191799110
Short name T297
Test name
Test status
Simulation time 7231359727 ps
CPU time 3.3 seconds
Started Jul 06 06:31:53 PM PDT 24
Finished Jul 06 06:31:57 PM PDT 24
Peak memory 184008 kb
Host smart-ff111751-9483-475f-8ac8-e0816f9a971e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191799110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3191799110
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2669742404
Short name T382
Test name
Test status
Simulation time 1180347221 ps
CPU time 0.81 seconds
Started Jul 06 06:32:01 PM PDT 24
Finished Jul 06 06:32:02 PM PDT 24
Peak memory 183836 kb
Host smart-0ebdec18-b2e5-4b23-b3d3-3c75bc0082c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669742404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2669742404
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2343536124
Short name T197
Test name
Test status
Simulation time 649768158 ps
CPU time 1 seconds
Started Jul 06 06:31:55 PM PDT 24
Finished Jul 06 06:31:56 PM PDT 24
Peak memory 197244 kb
Host smart-9cb62457-da37-4fd9-b0b4-22255fc0ab17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343536124 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2343536124
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1283880338
Short name T417
Test name
Test status
Simulation time 384717687 ps
CPU time 0.86 seconds
Started Jul 06 06:31:56 PM PDT 24
Finished Jul 06 06:31:57 PM PDT 24
Peak memory 192100 kb
Host smart-e23b7286-44ce-4bcc-b70f-606668639962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283880338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1283880338
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3081056746
Short name T291
Test name
Test status
Simulation time 324787602 ps
CPU time 1.07 seconds
Started Jul 06 06:31:54 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 183772 kb
Host smart-08c9f86d-ba8e-4f84-8b88-c35305bbc214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081056746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3081056746
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4092531053
Short name T394
Test name
Test status
Simulation time 318822015 ps
CPU time 0.92 seconds
Started Jul 06 06:32:00 PM PDT 24
Finished Jul 06 06:32:02 PM PDT 24
Peak memory 183696 kb
Host smart-fb4de84e-c111-4e7c-87cf-ffabe695fe96
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092531053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.4092531053
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1994747821
Short name T294
Test name
Test status
Simulation time 353170600 ps
CPU time 0.76 seconds
Started Jul 06 06:31:53 PM PDT 24
Finished Jul 06 06:31:54 PM PDT 24
Peak memory 183764 kb
Host smart-a3a42095-db53-4c63-b4f5-1ac7b0f2a540
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994747821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1994747821
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1057120613
Short name T341
Test name
Test status
Simulation time 2137868382 ps
CPU time 5.13 seconds
Started Jul 06 06:32:01 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 193124 kb
Host smart-7f968418-4f77-45ae-900c-27369530d630
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057120613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1057120613
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2350938856
Short name T410
Test name
Test status
Simulation time 662341589 ps
CPU time 2.17 seconds
Started Jul 06 06:31:54 PM PDT 24
Finished Jul 06 06:31:57 PM PDT 24
Peak memory 198676 kb
Host smart-3b5591a6-8dc6-4d9c-8136-e712baa93cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350938856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2350938856
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2962834542
Short name T384
Test name
Test status
Simulation time 5542784685 ps
CPU time 2.49 seconds
Started Jul 06 06:31:53 PM PDT 24
Finished Jul 06 06:31:56 PM PDT 24
Peak memory 196584 kb
Host smart-0f602a17-4bbe-4ceb-85af-44e8ec26391f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962834542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2962834542
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1864367542
Short name T355
Test name
Test status
Simulation time 310013908 ps
CPU time 0.8 seconds
Started Jul 06 06:32:16 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 192988 kb
Host smart-c9a42d3c-9c7c-496b-b04a-67ca94ec782b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864367542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1864367542
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.558553063
Short name T396
Test name
Test status
Simulation time 377284933 ps
CPU time 0.84 seconds
Started Jul 06 06:32:13 PM PDT 24
Finished Jul 06 06:32:14 PM PDT 24
Peak memory 183752 kb
Host smart-0f867dcc-3ff2-41ed-ba28-20aa7ae0a336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558553063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.558553063
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.906511350
Short name T419
Test name
Test status
Simulation time 422348259 ps
CPU time 0.59 seconds
Started Jul 06 06:32:12 PM PDT 24
Finished Jul 06 06:32:13 PM PDT 24
Peak memory 183764 kb
Host smart-60136d3e-2618-415b-9e25-127576e6f484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906511350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.906511350
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.100154355
Short name T377
Test name
Test status
Simulation time 520610915 ps
CPU time 0.91 seconds
Started Jul 06 06:32:13 PM PDT 24
Finished Jul 06 06:32:15 PM PDT 24
Peak memory 183776 kb
Host smart-38d1606a-613c-44f9-9cd5-b16585309994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100154355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.100154355
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2763401267
Short name T354
Test name
Test status
Simulation time 422573539 ps
CPU time 1.12 seconds
Started Jul 06 06:32:14 PM PDT 24
Finished Jul 06 06:32:15 PM PDT 24
Peak memory 192764 kb
Host smart-28763019-a44f-4e1f-9418-bef9964437b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763401267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2763401267
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.888217508
Short name T345
Test name
Test status
Simulation time 503022904 ps
CPU time 1.24 seconds
Started Jul 06 06:32:17 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 192996 kb
Host smart-5ea189b1-7d8c-4e65-8787-e409b7dabcfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888217508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.888217508
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1393583407
Short name T342
Test name
Test status
Simulation time 523466255 ps
CPU time 0.62 seconds
Started Jul 06 06:32:18 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 192972 kb
Host smart-eeeb6eeb-e38a-4db1-99ac-a3ae24390ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393583407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1393583407
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3800348148
Short name T282
Test name
Test status
Simulation time 354054548 ps
CPU time 1.09 seconds
Started Jul 06 06:32:20 PM PDT 24
Finished Jul 06 06:32:22 PM PDT 24
Peak memory 183732 kb
Host smart-1cc3bd69-dc1b-4c86-9e5c-2a80abc053d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800348148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3800348148
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2100619926
Short name T295
Test name
Test status
Simulation time 491969697 ps
CPU time 1.16 seconds
Started Jul 06 06:32:17 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 183780 kb
Host smart-f289968e-ae0c-4586-9660-e65daacd51c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100619926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2100619926
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2043426216
Short name T304
Test name
Test status
Simulation time 313975511 ps
CPU time 0.76 seconds
Started Jul 06 06:32:15 PM PDT 24
Finished Jul 06 06:32:16 PM PDT 24
Peak memory 192964 kb
Host smart-aff22361-ff37-4b13-b36e-39350e4e9c34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043426216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2043426216
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.873499407
Short name T67
Test name
Test status
Simulation time 498758032 ps
CPU time 1.53 seconds
Started Jul 06 06:32:01 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 194012 kb
Host smart-cd3b5edc-24c9-4cb2-8e2b-c0fe6d282e07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873499407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.873499407
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2782688216
Short name T57
Test name
Test status
Simulation time 2854784118 ps
CPU time 6.54 seconds
Started Jul 06 06:31:54 PM PDT 24
Finished Jul 06 06:32:01 PM PDT 24
Peak memory 192284 kb
Host smart-8e210b61-0fb3-45cc-ac8c-2aef06581897
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782688216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2782688216
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1542525905
Short name T66
Test name
Test status
Simulation time 674962628 ps
CPU time 1.37 seconds
Started Jul 06 06:31:53 PM PDT 24
Finished Jul 06 06:31:54 PM PDT 24
Peak memory 193012 kb
Host smart-3a2849f9-22a1-4bd4-9517-39c7e3786294
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542525905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1542525905
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1866906617
Short name T387
Test name
Test status
Simulation time 444605709 ps
CPU time 1.15 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 198468 kb
Host smart-69f18de4-3928-4742-8b6d-a67c8108ba50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866906617 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1866906617
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1892880156
Short name T59
Test name
Test status
Simulation time 369797245 ps
CPU time 1.04 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 193016 kb
Host smart-1cee88c0-a942-47d5-b15b-bb5c6aec9796
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892880156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1892880156
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2852229259
Short name T391
Test name
Test status
Simulation time 315516951 ps
CPU time 0.99 seconds
Started Jul 06 06:31:55 PM PDT 24
Finished Jul 06 06:31:56 PM PDT 24
Peak memory 192968 kb
Host smart-a9b1df88-fd36-464e-997f-0b7701cdfeb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852229259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2852229259
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2653819509
Short name T348
Test name
Test status
Simulation time 443792616 ps
CPU time 0.68 seconds
Started Jul 06 06:32:02 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 183664 kb
Host smart-4013da98-8cf2-4a0f-8970-344b92199823
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653819509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2653819509
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2035356133
Short name T302
Test name
Test status
Simulation time 293096046 ps
CPU time 0.65 seconds
Started Jul 06 06:31:55 PM PDT 24
Finished Jul 06 06:31:56 PM PDT 24
Peak memory 183740 kb
Host smart-45122793-3996-45b0-9830-41c5a5818d83
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035356133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2035356133
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1848347184
Short name T328
Test name
Test status
Simulation time 1212324063 ps
CPU time 1.07 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 193024 kb
Host smart-9ec3d75c-f196-4b81-9aeb-4c6815ba71f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848347184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1848347184
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2897960562
Short name T340
Test name
Test status
Simulation time 627359658 ps
CPU time 1.58 seconds
Started Jul 06 06:31:54 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 198620 kb
Host smart-41197019-3771-4a59-9635-78b44ba99330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897960562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2897960562
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.692217731
Short name T369
Test name
Test status
Simulation time 8488473336 ps
CPU time 13.75 seconds
Started Jul 06 06:31:55 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 198164 kb
Host smart-39c96acf-d55d-4e7b-8286-e612234168f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692217731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.692217731
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.283501556
Short name T415
Test name
Test status
Simulation time 522394193 ps
CPU time 0.89 seconds
Started Jul 06 06:32:18 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 183768 kb
Host smart-f4eb9837-d8c4-4275-9e37-cd8aea0eaa86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283501556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.283501556
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.989374236
Short name T327
Test name
Test status
Simulation time 530557829 ps
CPU time 0.75 seconds
Started Jul 06 06:32:20 PM PDT 24
Finished Jul 06 06:32:21 PM PDT 24
Peak memory 183768 kb
Host smart-a16e0fff-32d9-4d77-84cf-05f95e103200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989374236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.989374236
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1664300352
Short name T331
Test name
Test status
Simulation time 340206248 ps
CPU time 0.82 seconds
Started Jul 06 06:32:17 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 183768 kb
Host smart-873eaa6f-31b2-405d-be89-05218cfd605f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664300352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1664300352
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2784143703
Short name T306
Test name
Test status
Simulation time 470818467 ps
CPU time 0.65 seconds
Started Jul 06 06:32:21 PM PDT 24
Finished Jul 06 06:32:22 PM PDT 24
Peak memory 192976 kb
Host smart-544171f9-d43e-44f3-bff6-3d29dbd53b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784143703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2784143703
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2825885265
Short name T337
Test name
Test status
Simulation time 564587124 ps
CPU time 0.64 seconds
Started Jul 06 06:32:16 PM PDT 24
Finished Jul 06 06:32:17 PM PDT 24
Peak memory 192968 kb
Host smart-7092e8eb-2c44-416c-a085-0760aa73bbfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825885265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2825885265
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1804797343
Short name T416
Test name
Test status
Simulation time 462433578 ps
CPU time 0.75 seconds
Started Jul 06 06:32:19 PM PDT 24
Finished Jul 06 06:32:20 PM PDT 24
Peak memory 183748 kb
Host smart-2b2795ab-7a71-40d9-8ee5-809c5981e6a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804797343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1804797343
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3367303323
Short name T285
Test name
Test status
Simulation time 471896854 ps
CPU time 0.61 seconds
Started Jul 06 06:32:16 PM PDT 24
Finished Jul 06 06:32:17 PM PDT 24
Peak memory 183764 kb
Host smart-558da2d1-d537-4290-99e6-adaca44dc3cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367303323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3367303323
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.52085324
Short name T336
Test name
Test status
Simulation time 304204157 ps
CPU time 0.72 seconds
Started Jul 06 06:32:18 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 183800 kb
Host smart-e5eefe3f-fb14-4e0a-8ebb-c245dd22c085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52085324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.52085324
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.281284332
Short name T401
Test name
Test status
Simulation time 472965056 ps
CPU time 0.7 seconds
Started Jul 06 06:32:16 PM PDT 24
Finished Jul 06 06:32:17 PM PDT 24
Peak memory 183764 kb
Host smart-a52236ec-80d4-43c4-b27f-20b46c750507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281284332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.281284332
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.599372891
Short name T311
Test name
Test status
Simulation time 364021515 ps
CPU time 0.59 seconds
Started Jul 06 06:32:19 PM PDT 24
Finished Jul 06 06:32:20 PM PDT 24
Peak memory 192972 kb
Host smart-3abe21da-a4ed-4754-9dbe-97bc6b9fed47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599372891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.599372891
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4071472208
Short name T393
Test name
Test status
Simulation time 527556604 ps
CPU time 1.13 seconds
Started Jul 06 06:31:58 PM PDT 24
Finished Jul 06 06:31:59 PM PDT 24
Peak memory 191992 kb
Host smart-a4ebef7c-5ad5-419a-9af3-029b2b95939b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071472208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.4071472208
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2812727452
Short name T58
Test name
Test status
Simulation time 12752805323 ps
CPU time 10.49 seconds
Started Jul 06 06:32:00 PM PDT 24
Finished Jul 06 06:32:10 PM PDT 24
Peak memory 196240 kb
Host smart-5613dbcb-1391-43c7-b2ab-44d7dac41d2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812727452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2812727452
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3196071757
Short name T61
Test name
Test status
Simulation time 754778711 ps
CPU time 0.67 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 193024 kb
Host smart-0945e084-248c-4318-b664-032b571a3a7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196071757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3196071757
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3665711008
Short name T386
Test name
Test status
Simulation time 581214425 ps
CPU time 0.89 seconds
Started Jul 06 06:32:01 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 197716 kb
Host smart-f1db52fd-6a1a-40e2-a5a4-a5a9e12c1af1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665711008 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3665711008
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.430446160
Short name T60
Test name
Test status
Simulation time 295762097 ps
CPU time 0.66 seconds
Started Jul 06 06:31:58 PM PDT 24
Finished Jul 06 06:31:59 PM PDT 24
Peak memory 193032 kb
Host smart-3e67cc33-30f8-486b-bc2b-4d0198b26a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430446160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.430446160
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3022527299
Short name T383
Test name
Test status
Simulation time 283804962 ps
CPU time 0.72 seconds
Started Jul 06 06:31:58 PM PDT 24
Finished Jul 06 06:31:59 PM PDT 24
Peak memory 192996 kb
Host smart-d4db6875-373d-4f65-8e48-220af60ef871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022527299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3022527299
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3025730160
Short name T368
Test name
Test status
Simulation time 311168138 ps
CPU time 0.96 seconds
Started Jul 06 06:31:59 PM PDT 24
Finished Jul 06 06:32:00 PM PDT 24
Peak memory 183692 kb
Host smart-5e3eb6cd-bba6-4554-b180-9e9d50ab6289
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025730160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3025730160
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1247059799
Short name T339
Test name
Test status
Simulation time 467131444 ps
CPU time 0.66 seconds
Started Jul 06 06:31:58 PM PDT 24
Finished Jul 06 06:31:59 PM PDT 24
Peak memory 183756 kb
Host smart-713f2b51-dd92-4815-9c03-2af33a81fe4f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247059799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1247059799
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.906444068
Short name T381
Test name
Test status
Simulation time 1532343511 ps
CPU time 2.56 seconds
Started Jul 06 06:31:57 PM PDT 24
Finished Jul 06 06:32:00 PM PDT 24
Peak memory 193092 kb
Host smart-3f6e6e2f-f2ae-4004-ad69-4b11a0b15a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906444068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.906444068
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2889886039
Short name T288
Test name
Test status
Simulation time 430674825 ps
CPU time 2.53 seconds
Started Jul 06 06:31:58 PM PDT 24
Finished Jul 06 06:32:01 PM PDT 24
Peak memory 198652 kb
Host smart-22dfcd03-7843-4dff-9866-44eaf438a350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889886039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2889886039
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3218803895
Short name T37
Test name
Test status
Simulation time 8672048305 ps
CPU time 4.71 seconds
Started Jul 06 06:32:00 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 198380 kb
Host smart-565ffe10-23f3-4e62-9cc2-cdaa8bd72c00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218803895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3218803895
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4124728477
Short name T320
Test name
Test status
Simulation time 407874878 ps
CPU time 1.21 seconds
Started Jul 06 06:32:22 PM PDT 24
Finished Jul 06 06:32:24 PM PDT 24
Peak memory 192976 kb
Host smart-51113884-5301-4b68-8cfa-639c8e5c8821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124728477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4124728477
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1567905763
Short name T321
Test name
Test status
Simulation time 489030233 ps
CPU time 0.72 seconds
Started Jul 06 06:32:22 PM PDT 24
Finished Jul 06 06:32:23 PM PDT 24
Peak memory 183756 kb
Host smart-7ae9d2ab-4a90-4b23-804e-de619854385b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567905763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1567905763
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2415769928
Short name T325
Test name
Test status
Simulation time 494718329 ps
CPU time 1.25 seconds
Started Jul 06 06:32:17 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 183776 kb
Host smart-ae588e81-41cc-469d-8466-a1a65367caa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415769928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2415769928
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2036889047
Short name T421
Test name
Test status
Simulation time 354542682 ps
CPU time 0.63 seconds
Started Jul 06 06:32:18 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 183732 kb
Host smart-62813796-476b-4117-bf38-903fc7162bd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036889047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2036889047
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3167850794
Short name T312
Test name
Test status
Simulation time 448451596 ps
CPU time 1.11 seconds
Started Jul 06 06:32:14 PM PDT 24
Finished Jul 06 06:32:16 PM PDT 24
Peak memory 183764 kb
Host smart-b8ef5a43-48fd-4f6c-99b2-2be91feb0f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167850794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3167850794
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1590601753
Short name T364
Test name
Test status
Simulation time 507327593 ps
CPU time 0.74 seconds
Started Jul 06 06:32:21 PM PDT 24
Finished Jul 06 06:32:22 PM PDT 24
Peak memory 183768 kb
Host smart-3d52ed29-3967-4bd3-90a4-5793f30e1b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590601753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1590601753
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2640829790
Short name T361
Test name
Test status
Simulation time 423410346 ps
CPU time 1.1 seconds
Started Jul 06 06:32:19 PM PDT 24
Finished Jul 06 06:32:21 PM PDT 24
Peak memory 183736 kb
Host smart-123da52d-951e-4d56-a685-c56c40c12324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640829790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2640829790
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.181779998
Short name T317
Test name
Test status
Simulation time 445005509 ps
CPU time 0.58 seconds
Started Jul 06 06:32:22 PM PDT 24
Finished Jul 06 06:32:23 PM PDT 24
Peak memory 183768 kb
Host smart-a8ef3ae7-3fcc-499c-817f-045c32392da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181779998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.181779998
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1893625818
Short name T289
Test name
Test status
Simulation time 458673105 ps
CPU time 1.14 seconds
Started Jul 06 06:32:21 PM PDT 24
Finished Jul 06 06:32:22 PM PDT 24
Peak memory 183764 kb
Host smart-463fba7e-31c6-44f5-b4b8-97fc862723d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893625818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1893625818
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2391134824
Short name T286
Test name
Test status
Simulation time 272725811 ps
CPU time 0.74 seconds
Started Jul 06 06:32:19 PM PDT 24
Finished Jul 06 06:32:20 PM PDT 24
Peak memory 183780 kb
Host smart-9c4b8967-22da-4df1-b8aa-b827efd26485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391134824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2391134824
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2567796321
Short name T299
Test name
Test status
Simulation time 509493563 ps
CPU time 1.3 seconds
Started Jul 06 06:32:02 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 196224 kb
Host smart-f074cba1-56de-474f-a41e-a738bbb8afe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567796321 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2567796321
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2333690852
Short name T379
Test name
Test status
Simulation time 546473889 ps
CPU time 0.74 seconds
Started Jul 06 06:32:00 PM PDT 24
Finished Jul 06 06:32:01 PM PDT 24
Peak memory 192080 kb
Host smart-a135ac42-53a4-4b0c-ae80-90aa5b1da473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333690852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2333690852
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2457558834
Short name T308
Test name
Test status
Simulation time 481123039 ps
CPU time 1.35 seconds
Started Jul 06 06:32:02 PM PDT 24
Finished Jul 06 06:32:04 PM PDT 24
Peak memory 183752 kb
Host smart-23643574-d4ef-4d5b-b2bc-9190430d0e02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457558834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2457558834
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.505213576
Short name T338
Test name
Test status
Simulation time 1974397878 ps
CPU time 4.36 seconds
Started Jul 06 06:31:59 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 194144 kb
Host smart-167fd39a-b55b-4227-b918-06c956ac0471
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505213576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.505213576
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1587115983
Short name T310
Test name
Test status
Simulation time 661377878 ps
CPU time 2.61 seconds
Started Jul 06 06:31:57 PM PDT 24
Finished Jul 06 06:32:00 PM PDT 24
Peak memory 198664 kb
Host smart-f146ebe2-d4dc-4e92-a177-9c092a6ec532
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587115983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1587115983
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1675228181
Short name T298
Test name
Test status
Simulation time 4682434651 ps
CPU time 4.45 seconds
Started Jul 06 06:31:59 PM PDT 24
Finished Jul 06 06:32:04 PM PDT 24
Peak memory 197984 kb
Host smart-2e3e0ab3-c1bd-4a87-ae02-3507233b2ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675228181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1675228181
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1622803019
Short name T407
Test name
Test status
Simulation time 498713551 ps
CPU time 0.85 seconds
Started Jul 06 06:31:58 PM PDT 24
Finished Jul 06 06:31:59 PM PDT 24
Peak memory 196892 kb
Host smart-4d11555f-34af-4f44-a98d-e61306f37a81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622803019 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1622803019
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.597368148
Short name T71
Test name
Test status
Simulation time 452444661 ps
CPU time 1.41 seconds
Started Jul 06 06:32:02 PM PDT 24
Finished Jul 06 06:32:04 PM PDT 24
Peak memory 193120 kb
Host smart-2694a3f4-5888-4e87-a1af-47fdaf2445bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597368148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.597368148
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2358348087
Short name T406
Test name
Test status
Simulation time 440591543 ps
CPU time 0.7 seconds
Started Jul 06 06:31:57 PM PDT 24
Finished Jul 06 06:31:58 PM PDT 24
Peak memory 183768 kb
Host smart-e4d236ab-a084-4913-923e-311278ce15bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358348087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2358348087
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.753086573
Short name T72
Test name
Test status
Simulation time 1517405035 ps
CPU time 2.66 seconds
Started Jul 06 06:31:57 PM PDT 24
Finished Jul 06 06:32:00 PM PDT 24
Peak memory 194084 kb
Host smart-7ffc0d44-d186-4941-921d-2d6aa965a671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753086573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.753086573
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1088977588
Short name T413
Test name
Test status
Simulation time 473561558 ps
CPU time 2.36 seconds
Started Jul 06 06:32:01 PM PDT 24
Finished Jul 06 06:32:04 PM PDT 24
Peak memory 198696 kb
Host smart-8603e512-3055-49cb-a243-9ae1284c3ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088977588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1088977588
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1460624033
Short name T38
Test name
Test status
Simulation time 8597219960 ps
CPU time 3.23 seconds
Started Jul 06 06:31:57 PM PDT 24
Finished Jul 06 06:32:00 PM PDT 24
Peak memory 198284 kb
Host smart-5fcd522a-2880-4188-95bb-b1a1f4a5d9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460624033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1460624033
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1008664667
Short name T313
Test name
Test status
Simulation time 442107704 ps
CPU time 1.34 seconds
Started Jul 06 06:32:02 PM PDT 24
Finished Jul 06 06:32:04 PM PDT 24
Peak memory 196500 kb
Host smart-64f305b0-3fff-4a9c-af89-aecc49c9013e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008664667 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1008664667
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2540144993
Short name T403
Test name
Test status
Simulation time 361773303 ps
CPU time 0.7 seconds
Started Jul 06 06:32:04 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 192072 kb
Host smart-1c8d7a6d-9caa-422b-b37f-6f82e4e22725
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540144993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2540144993
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2650570110
Short name T292
Test name
Test status
Simulation time 434150291 ps
CPU time 0.71 seconds
Started Jul 06 06:32:02 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 183772 kb
Host smart-a73154ea-ec33-4d78-989f-ff43f56751e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650570110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2650570110
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2779974646
Short name T74
Test name
Test status
Simulation time 1399976850 ps
CPU time 0.8 seconds
Started Jul 06 06:32:05 PM PDT 24
Finished Jul 06 06:32:07 PM PDT 24
Peak memory 193696 kb
Host smart-afc13974-ad15-4b4a-b850-1c612fa1ce90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779974646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2779974646
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3913541034
Short name T322
Test name
Test status
Simulation time 357631343 ps
CPU time 1.47 seconds
Started Jul 06 06:31:58 PM PDT 24
Finished Jul 06 06:32:00 PM PDT 24
Peak memory 198484 kb
Host smart-8d8d7ed4-ffda-4d28-b340-da6d0e9604fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913541034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3913541034
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2281117853
Short name T358
Test name
Test status
Simulation time 8522337612 ps
CPU time 13.15 seconds
Started Jul 06 06:32:01 PM PDT 24
Finished Jul 06 06:32:15 PM PDT 24
Peak memory 198324 kb
Host smart-242eb1f6-cfca-4942-a9ce-4febbdeb566b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281117853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2281117853
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.732126664
Short name T353
Test name
Test status
Simulation time 333491188 ps
CPU time 1.09 seconds
Started Jul 06 06:32:04 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 195672 kb
Host smart-0597bcda-fb17-4f0b-ac69-80d0c799d332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732126664 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.732126664
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3069505826
Short name T63
Test name
Test status
Simulation time 453634335 ps
CPU time 0.87 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:04 PM PDT 24
Peak memory 193448 kb
Host smart-dd399b44-196f-46ff-b903-9be3ce04a6a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069505826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3069505826
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2040457443
Short name T357
Test name
Test status
Simulation time 428658353 ps
CPU time 0.67 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:04 PM PDT 24
Peak memory 183768 kb
Host smart-b1a138df-215b-42e8-b197-f32c7f5ae7c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040457443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2040457443
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3620637305
Short name T315
Test name
Test status
Simulation time 1601115244 ps
CPU time 0.85 seconds
Started Jul 06 06:32:04 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 191944 kb
Host smart-d7adec93-23fc-4c1e-a1f8-fe7a0c9866b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620637305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3620637305
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3128421394
Short name T422
Test name
Test status
Simulation time 588894298 ps
CPU time 1.89 seconds
Started Jul 06 06:32:02 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 198672 kb
Host smart-5c022b76-780b-48a0-8570-7c5441071981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128421394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3128421394
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.704911468
Short name T362
Test name
Test status
Simulation time 4267575626 ps
CPU time 7.4 seconds
Started Jul 06 06:32:05 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 198060 kb
Host smart-4bcd4c31-cb0c-46fe-92ca-68d5c313d580
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704911468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.704911468
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3013557324
Short name T414
Test name
Test status
Simulation time 445673849 ps
CPU time 1.18 seconds
Started Jul 06 06:32:04 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 196324 kb
Host smart-67ad6163-cd92-432b-a03e-3c1c306c2c74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013557324 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3013557324
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3770084223
Short name T65
Test name
Test status
Simulation time 354260196 ps
CPU time 0.76 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:04 PM PDT 24
Peak memory 193220 kb
Host smart-01f6c246-3066-4bd2-b71f-ca02c107da06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770084223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3770084223
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2083035337
Short name T343
Test name
Test status
Simulation time 474611734 ps
CPU time 0.88 seconds
Started Jul 06 06:32:04 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 183772 kb
Host smart-8ab40e78-17da-4f6c-baf6-9a2c9a620813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083035337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2083035337
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2616185129
Short name T34
Test name
Test status
Simulation time 1206570261 ps
CPU time 3.02 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:07 PM PDT 24
Peak memory 194076 kb
Host smart-71d5edb1-8aca-46a3-9d4a-cd89a5e1cad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616185129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2616185129
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.813366634
Short name T284
Test name
Test status
Simulation time 460451429 ps
CPU time 2.55 seconds
Started Jul 06 06:32:03 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 198664 kb
Host smart-ebb3f355-f7f3-4981-9a56-3fce7e4d1b13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813366634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.813366634
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1887015027
Short name T307
Test name
Test status
Simulation time 8245944365 ps
CPU time 4.16 seconds
Started Jul 06 06:32:05 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 198292 kb
Host smart-78b10559-2560-4e80-adad-03041be643a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887015027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1887015027
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1868418927
Short name T264
Test name
Test status
Simulation time 31697311053 ps
CPU time 47.03 seconds
Started Jul 06 05:18:07 PM PDT 24
Finished Jul 06 05:18:55 PM PDT 24
Peak memory 191868 kb
Host smart-c239d941-e870-45c5-aa31-dc14c5e9c4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868418927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1868418927
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.649720716
Short name T210
Test name
Test status
Simulation time 359803510 ps
CPU time 1.16 seconds
Started Jul 06 05:18:10 PM PDT 24
Finished Jul 06 05:18:11 PM PDT 24
Peak memory 191924 kb
Host smart-b341b22d-f7bc-459e-abfb-ef0c8b5607cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649720716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.649720716
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.4174852950
Short name T211
Test name
Test status
Simulation time 58169661665 ps
CPU time 7.97 seconds
Started Jul 06 05:18:12 PM PDT 24
Finished Jul 06 05:18:20 PM PDT 24
Peak memory 191996 kb
Host smart-d66feca4-e1f1-4ad4-8496-4fa587f1c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174852950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4174852950
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3957477057
Short name T16
Test name
Test status
Simulation time 7745263993 ps
CPU time 11.73 seconds
Started Jul 06 05:18:08 PM PDT 24
Finished Jul 06 05:18:20 PM PDT 24
Peak memory 215808 kb
Host smart-74efbd21-e70a-497b-9946-09972652f4c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957477057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3957477057
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.782279872
Short name T280
Test name
Test status
Simulation time 415674261 ps
CPU time 1.12 seconds
Started Jul 06 05:18:10 PM PDT 24
Finished Jul 06 05:18:11 PM PDT 24
Peak memory 196736 kb
Host smart-6b062079-9443-4ae8-b2a7-037760281331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782279872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.782279872
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2276112355
Short name T207
Test name
Test status
Simulation time 26594838960 ps
CPU time 9.4 seconds
Started Jul 06 05:18:19 PM PDT 24
Finished Jul 06 05:18:29 PM PDT 24
Peak memory 196964 kb
Host smart-0670867f-b8c0-4f1c-ba90-424dba710567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276112355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2276112355
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.187436004
Short name T204
Test name
Test status
Simulation time 532195605 ps
CPU time 0.77 seconds
Started Jul 06 05:18:31 PM PDT 24
Finished Jul 06 05:18:32 PM PDT 24
Peak memory 191876 kb
Host smart-a010c4a4-bbbd-4f76-b4c8-1d32fd27650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187436004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.187436004
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1875455081
Short name T253
Test name
Test status
Simulation time 9362390941 ps
CPU time 1.24 seconds
Started Jul 06 05:18:33 PM PDT 24
Finished Jul 06 05:18:35 PM PDT 24
Peak memory 191968 kb
Host smart-6fa1f65b-0a8c-4eac-9b1f-69cb524486c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875455081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1875455081
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3020016593
Short name T221
Test name
Test status
Simulation time 597250770 ps
CPU time 0.79 seconds
Started Jul 06 05:18:31 PM PDT 24
Finished Jul 06 05:18:32 PM PDT 24
Peak memory 196708 kb
Host smart-9c3799bc-12b7-4264-9a80-c1187aceed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020016593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3020016593
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3228596277
Short name T79
Test name
Test status
Simulation time 580207907 ps
CPU time 1.3 seconds
Started Jul 06 05:18:34 PM PDT 24
Finished Jul 06 05:18:36 PM PDT 24
Peak memory 196804 kb
Host smart-28d7f55a-349e-439e-a83c-de08e0d3d280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228596277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3228596277
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3556356244
Short name T235
Test name
Test status
Simulation time 26313519087 ps
CPU time 40.18 seconds
Started Jul 06 05:18:37 PM PDT 24
Finished Jul 06 05:19:17 PM PDT 24
Peak memory 196976 kb
Host smart-fe1b713c-a1db-4a5c-a442-61c70a8f5318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556356244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3556356244
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1559699108
Short name T29
Test name
Test status
Simulation time 461819595 ps
CPU time 0.76 seconds
Started Jul 06 05:18:26 PM PDT 24
Finished Jul 06 05:18:27 PM PDT 24
Peak memory 196744 kb
Host smart-73d2951d-19da-408b-90ee-62e94ef9d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559699108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1559699108
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.216033164
Short name T8
Test name
Test status
Simulation time 28657063173 ps
CPU time 8.36 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:18:51 PM PDT 24
Peak memory 191920 kb
Host smart-76f7a770-149f-4c9e-a715-c058089e13bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216033164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.216033164
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2148730235
Short name T244
Test name
Test status
Simulation time 612220215 ps
CPU time 0.78 seconds
Started Jul 06 05:18:34 PM PDT 24
Finished Jul 06 05:18:35 PM PDT 24
Peak memory 196772 kb
Host smart-63126ed5-9733-4828-9f99-79d37f56671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148730235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2148730235
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.4110868303
Short name T231
Test name
Test status
Simulation time 17165151119 ps
CPU time 8.06 seconds
Started Jul 06 05:18:30 PM PDT 24
Finished Jul 06 05:18:38 PM PDT 24
Peak memory 191988 kb
Host smart-99b57902-fc1e-46e9-82dc-00cd353bb592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110868303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.4110868303
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3371163871
Short name T209
Test name
Test status
Simulation time 517821304 ps
CPU time 1 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:18:42 PM PDT 24
Peak memory 191904 kb
Host smart-06b9a0f2-17b0-4ef3-a414-3fa706f4f278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371163871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3371163871
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.452772735
Short name T242
Test name
Test status
Simulation time 33876616898 ps
CPU time 21.74 seconds
Started Jul 06 05:18:34 PM PDT 24
Finished Jul 06 05:18:57 PM PDT 24
Peak memory 196996 kb
Host smart-732d3f09-a943-4d02-ade7-b1f14cb82852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452772735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.452772735
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2901967201
Short name T206
Test name
Test status
Simulation time 516066187 ps
CPU time 0.75 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:18:44 PM PDT 24
Peak memory 196656 kb
Host smart-5cbcaa1d-cf10-44db-84d7-98cf68140af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901967201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2901967201
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1436544369
Short name T232
Test name
Test status
Simulation time 19153171033 ps
CPU time 29.9 seconds
Started Jul 06 05:18:40 PM PDT 24
Finished Jul 06 05:19:10 PM PDT 24
Peak memory 191968 kb
Host smart-e4ced955-00d1-4ffd-bd68-7715f5711c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436544369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1436544369
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1946153121
Short name T30
Test name
Test status
Simulation time 535771971 ps
CPU time 1.31 seconds
Started Jul 06 05:18:39 PM PDT 24
Finished Jul 06 05:18:40 PM PDT 24
Peak memory 196780 kb
Host smart-9ce982f2-94b3-4e93-969c-1d10e6290654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946153121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1946153121
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1060558826
Short name T269
Test name
Test status
Simulation time 31737033467 ps
CPU time 12.58 seconds
Started Jul 06 05:18:40 PM PDT 24
Finished Jul 06 05:18:53 PM PDT 24
Peak memory 191992 kb
Host smart-3ccf75d3-48a3-41a1-bec0-d672d4e4d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060558826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1060558826
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1471832846
Short name T218
Test name
Test status
Simulation time 545459782 ps
CPU time 1.37 seconds
Started Jul 06 05:18:30 PM PDT 24
Finished Jul 06 05:18:31 PM PDT 24
Peak memory 191792 kb
Host smart-58e55d96-a96c-4e6c-95f9-cc7b7c5f7d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471832846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1471832846
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2105836076
Short name T241
Test name
Test status
Simulation time 41544704557 ps
CPU time 15.37 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:19:04 PM PDT 24
Peak memory 191880 kb
Host smart-3a3b2721-5158-402e-bd59-cc8679b21114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105836076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2105836076
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2968223134
Short name T5
Test name
Test status
Simulation time 580623976 ps
CPU time 1.48 seconds
Started Jul 06 05:18:34 PM PDT 24
Finished Jul 06 05:18:36 PM PDT 24
Peak memory 191924 kb
Host smart-ec9fcdbe-f910-46f8-b7f7-fd99ee9562a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968223134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2968223134
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3178268943
Short name T258
Test name
Test status
Simulation time 25694101631 ps
CPU time 32.89 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:19:16 PM PDT 24
Peak memory 191988 kb
Host smart-9df9f9a8-041f-45ca-bbd8-8e734a086af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178268943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3178268943
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2338408649
Short name T260
Test name
Test status
Simulation time 574340726 ps
CPU time 0.9 seconds
Started Jul 06 05:18:34 PM PDT 24
Finished Jul 06 05:18:36 PM PDT 24
Peak memory 191916 kb
Host smart-d957aab8-7220-4cb8-9065-ac4309abd094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338408649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2338408649
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3248651765
Short name T205
Test name
Test status
Simulation time 43728443067 ps
CPU time 24.24 seconds
Started Jul 06 05:18:09 PM PDT 24
Finished Jul 06 05:18:34 PM PDT 24
Peak memory 191988 kb
Host smart-d4a520fe-64bd-421e-866b-46fb5eeb003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248651765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3248651765
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3104080641
Short name T18
Test name
Test status
Simulation time 4694084148 ps
CPU time 7.22 seconds
Started Jul 06 05:18:08 PM PDT 24
Finished Jul 06 05:18:16 PM PDT 24
Peak memory 215664 kb
Host smart-7663d4ff-d10f-4d0b-97f4-8b5ad1e44903
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104080641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3104080641
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2987470104
Short name T255
Test name
Test status
Simulation time 411730499 ps
CPU time 0.73 seconds
Started Jul 06 05:18:08 PM PDT 24
Finished Jul 06 05:18:09 PM PDT 24
Peak memory 191904 kb
Host smart-ea6de6e2-0a48-4cae-8688-d9863d2e0f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987470104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2987470104
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1165627957
Short name T274
Test name
Test status
Simulation time 53818914768 ps
CPU time 38.6 seconds
Started Jul 06 05:18:44 PM PDT 24
Finished Jul 06 05:19:23 PM PDT 24
Peak memory 191948 kb
Host smart-a7a4e1f8-9a32-4bc7-8645-ab1d628a745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165627957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1165627957
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2422788599
Short name T46
Test name
Test status
Simulation time 631977212 ps
CPU time 0.71 seconds
Started Jul 06 05:18:29 PM PDT 24
Finished Jul 06 05:18:30 PM PDT 24
Peak memory 196760 kb
Host smart-ce2f6e94-aed2-49a0-8d9d-4e3a7719b9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422788599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2422788599
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4239687563
Short name T279
Test name
Test status
Simulation time 9150911525 ps
CPU time 1.31 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:18:49 PM PDT 24
Peak memory 191960 kb
Host smart-018c7085-5a9a-416c-9668-1b7584d53b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239687563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4239687563
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.71741377
Short name T251
Test name
Test status
Simulation time 461386760 ps
CPU time 0.93 seconds
Started Jul 06 05:18:45 PM PDT 24
Finished Jul 06 05:18:46 PM PDT 24
Peak memory 191744 kb
Host smart-820f485f-0988-463a-90ba-4c14f37187d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71741377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.71741377
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.292731096
Short name T215
Test name
Test status
Simulation time 42684829762 ps
CPU time 25.64 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:19:09 PM PDT 24
Peak memory 191952 kb
Host smart-d5723f33-b56c-44b2-ba7a-7312407f4281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292731096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.292731096
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3098473540
Short name T213
Test name
Test status
Simulation time 515215702 ps
CPU time 0.76 seconds
Started Jul 06 05:18:51 PM PDT 24
Finished Jul 06 05:18:52 PM PDT 24
Peak memory 191900 kb
Host smart-45480409-2d04-4408-ba2b-e4e8b0e43419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098473540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3098473540
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2825791566
Short name T278
Test name
Test status
Simulation time 53604772990 ps
CPU time 18.74 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:19:02 PM PDT 24
Peak memory 191952 kb
Host smart-ed3d585b-31a9-496b-8ed4-33d69b6ac10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825791566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2825791566
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2913541952
Short name T51
Test name
Test status
Simulation time 591319262 ps
CPU time 1.38 seconds
Started Jul 06 05:18:38 PM PDT 24
Finished Jul 06 05:18:40 PM PDT 24
Peak memory 191920 kb
Host smart-9c8697de-fa54-4a24-bf7e-9bc88e2f2976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913541952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2913541952
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.978812609
Short name T248
Test name
Test status
Simulation time 31906376095 ps
CPU time 45.53 seconds
Started Jul 06 05:18:53 PM PDT 24
Finished Jul 06 05:19:39 PM PDT 24
Peak memory 191928 kb
Host smart-30c386fc-23a2-4543-b25a-fa0619145dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978812609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.978812609
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.670175573
Short name T261
Test name
Test status
Simulation time 530156643 ps
CPU time 0.63 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:18:48 PM PDT 24
Peak memory 196732 kb
Host smart-a20606e9-1a03-4ce2-9018-072aa367df0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670175573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.670175573
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2603046386
Short name T225
Test name
Test status
Simulation time 11822023847 ps
CPU time 16.79 seconds
Started Jul 06 05:18:44 PM PDT 24
Finished Jul 06 05:19:01 PM PDT 24
Peak memory 191988 kb
Host smart-2c2269d0-88f3-4887-a582-6477cae6b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603046386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2603046386
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3979293227
Short name T275
Test name
Test status
Simulation time 477395515 ps
CPU time 0.62 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:18:49 PM PDT 24
Peak memory 196672 kb
Host smart-1c9d1dd1-0b75-45ad-9df2-b645f5e2776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979293227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3979293227
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2547811225
Short name T262
Test name
Test status
Simulation time 60996375623 ps
CPU time 87.98 seconds
Started Jul 06 05:18:56 PM PDT 24
Finished Jul 06 05:20:24 PM PDT 24
Peak memory 196932 kb
Host smart-7db63c2d-6467-4036-a872-afb57ac2019d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547811225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2547811225
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3146267559
Short name T246
Test name
Test status
Simulation time 476194147 ps
CPU time 1.18 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:18:43 PM PDT 24
Peak memory 191868 kb
Host smart-666d5058-7ad5-4f59-baa9-7c5a2d99ba76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146267559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3146267559
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2433674697
Short name T202
Test name
Test status
Simulation time 56739361078 ps
CPU time 82.72 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:20:10 PM PDT 24
Peak memory 191992 kb
Host smart-98aad51a-6963-46d6-a3f7-f5d7ab887abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433674697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2433674697
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1005499892
Short name T229
Test name
Test status
Simulation time 632533135 ps
CPU time 0.84 seconds
Started Jul 06 05:18:43 PM PDT 24
Finished Jul 06 05:18:45 PM PDT 24
Peak memory 191796 kb
Host smart-ca6a9938-e027-4146-bead-a8ff65cffcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005499892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1005499892
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2882680982
Short name T26
Test name
Test status
Simulation time 15146573702 ps
CPU time 2.89 seconds
Started Jul 06 05:18:43 PM PDT 24
Finished Jul 06 05:18:47 PM PDT 24
Peak memory 191968 kb
Host smart-4ed2cd26-bbdc-47a0-a67d-7e9747f4ea4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882680982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2882680982
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.4057885159
Short name T52
Test name
Test status
Simulation time 515892616 ps
CPU time 0.81 seconds
Started Jul 06 05:18:54 PM PDT 24
Finished Jul 06 05:18:56 PM PDT 24
Peak memory 196740 kb
Host smart-4abcc43b-4ad2-4499-9e24-203f0fe4c6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057885159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.4057885159
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.480610953
Short name T243
Test name
Test status
Simulation time 60587853556 ps
CPU time 44.75 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:19:33 PM PDT 24
Peak memory 191948 kb
Host smart-36739d6f-6dd3-447a-a8ca-6a49ad4278c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480610953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.480610953
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1020216351
Short name T249
Test name
Test status
Simulation time 552064901 ps
CPU time 1.33 seconds
Started Jul 06 05:18:46 PM PDT 24
Finished Jul 06 05:18:48 PM PDT 24
Peak memory 191908 kb
Host smart-fe9a1ab4-73ef-4f0b-a93c-5c94b447e7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020216351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1020216351
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2530016887
Short name T178
Test name
Test status
Simulation time 424869795113 ps
CPU time 540.96 seconds
Started Jul 06 05:18:43 PM PDT 24
Finished Jul 06 05:27:44 PM PDT 24
Peak memory 193080 kb
Host smart-c50e8625-5f75-4629-9129-45b3916a02c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530016887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2530016887
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.750660868
Short name T250
Test name
Test status
Simulation time 10814317189 ps
CPU time 2.06 seconds
Started Jul 06 05:18:15 PM PDT 24
Finished Jul 06 05:18:18 PM PDT 24
Peak memory 197000 kb
Host smart-cd84a727-063b-4e43-b3ca-9238c81e15ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750660868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.750660868
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2056830338
Short name T21
Test name
Test status
Simulation time 9448756200 ps
CPU time 3.77 seconds
Started Jul 06 05:18:24 PM PDT 24
Finished Jul 06 05:18:28 PM PDT 24
Peak memory 215860 kb
Host smart-7a6087f8-1777-4a43-889e-3a7c182a9094
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056830338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2056830338
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.148426673
Short name T236
Test name
Test status
Simulation time 495699768 ps
CPU time 1.18 seconds
Started Jul 06 05:18:15 PM PDT 24
Finished Jul 06 05:18:16 PM PDT 24
Peak memory 196688 kb
Host smart-ca3edb1c-c6d8-425b-bada-7346cf52cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148426673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.148426673
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2352318347
Short name T238
Test name
Test status
Simulation time 830337606 ps
CPU time 1.23 seconds
Started Jul 06 05:18:41 PM PDT 24
Finished Jul 06 05:18:43 PM PDT 24
Peak memory 191904 kb
Host smart-65303c99-e40c-4b4d-9d2b-11298c92cef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352318347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2352318347
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2925468290
Short name T233
Test name
Test status
Simulation time 557131456 ps
CPU time 0.96 seconds
Started Jul 06 05:18:43 PM PDT 24
Finished Jul 06 05:18:44 PM PDT 24
Peak memory 191920 kb
Host smart-bbb43947-689e-4548-aedd-ad12186fb510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925468290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2925468290
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1923345037
Short name T234
Test name
Test status
Simulation time 31446009449 ps
CPU time 3.94 seconds
Started Jul 06 05:19:04 PM PDT 24
Finished Jul 06 05:19:10 PM PDT 24
Peak memory 196960 kb
Host smart-f664a55b-be84-4087-b6cc-224db99432a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923345037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1923345037
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.144986717
Short name T277
Test name
Test status
Simulation time 604935979 ps
CPU time 0.67 seconds
Started Jul 06 05:18:55 PM PDT 24
Finished Jul 06 05:18:56 PM PDT 24
Peak memory 196740 kb
Host smart-b658778d-3181-49e7-a6fe-39cefaddf383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144986717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.144986717
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2480574509
Short name T199
Test name
Test status
Simulation time 42658457445 ps
CPU time 33.29 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:19:16 PM PDT 24
Peak memory 191996 kb
Host smart-5e5db278-ebe2-4614-94b5-f740181d5687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480574509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2480574509
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.843764050
Short name T78
Test name
Test status
Simulation time 508304216 ps
CPU time 0.62 seconds
Started Jul 06 05:18:43 PM PDT 24
Finished Jul 06 05:18:44 PM PDT 24
Peak memory 191924 kb
Host smart-40708ad8-bb30-43f6-99fa-6655f66ec633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843764050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.843764050
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.806421372
Short name T224
Test name
Test status
Simulation time 26476672514 ps
CPU time 19.29 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:19:07 PM PDT 24
Peak memory 191976 kb
Host smart-484108da-8f27-438b-b161-468ef5f5cd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806421372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.806421372
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2683091416
Short name T270
Test name
Test status
Simulation time 530700415 ps
CPU time 0.6 seconds
Started Jul 06 05:18:59 PM PDT 24
Finished Jul 06 05:19:00 PM PDT 24
Peak memory 191844 kb
Host smart-b41e7051-1176-4db3-b430-b0801c7a59cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683091416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2683091416
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.404522301
Short name T266
Test name
Test status
Simulation time 18759832532 ps
CPU time 13.9 seconds
Started Jul 06 05:18:55 PM PDT 24
Finished Jul 06 05:19:10 PM PDT 24
Peak memory 191940 kb
Host smart-03e8bfa8-2eff-4355-8a53-95dfe1eb9a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404522301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.404522301
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2482763577
Short name T263
Test name
Test status
Simulation time 584230178 ps
CPU time 1.4 seconds
Started Jul 06 05:18:42 PM PDT 24
Finished Jul 06 05:18:44 PM PDT 24
Peak memory 191920 kb
Host smart-1752106f-ac62-47f2-b08a-0c56f78e9868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482763577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2482763577
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2312623307
Short name T175
Test name
Test status
Simulation time 394869116 ps
CPU time 1.08 seconds
Started Jul 06 05:18:44 PM PDT 24
Finished Jul 06 05:18:46 PM PDT 24
Peak memory 196732 kb
Host smart-72639f23-da7d-4d26-9cd9-3164a8e3742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312623307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2312623307
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1665791822
Short name T217
Test name
Test status
Simulation time 37921495597 ps
CPU time 14.91 seconds
Started Jul 06 05:18:50 PM PDT 24
Finished Jul 06 05:19:05 PM PDT 24
Peak memory 191980 kb
Host smart-8d2cfac4-8272-4bf7-94ec-11c23afc3a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665791822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1665791822
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.4145202632
Short name T265
Test name
Test status
Simulation time 501950223 ps
CPU time 0.78 seconds
Started Jul 06 05:19:04 PM PDT 24
Finished Jul 06 05:19:06 PM PDT 24
Peak memory 196740 kb
Host smart-f7ceae04-8154-4d76-9612-d8aa86e08d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145202632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.4145202632
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1123612863
Short name T9
Test name
Test status
Simulation time 16757099731 ps
CPU time 23.3 seconds
Started Jul 06 05:18:49 PM PDT 24
Finished Jul 06 05:19:13 PM PDT 24
Peak memory 191952 kb
Host smart-5785a9e8-51f0-45ae-826f-be181cb81be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123612863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1123612863
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.193384699
Short name T220
Test name
Test status
Simulation time 439465387 ps
CPU time 0.91 seconds
Started Jul 06 05:18:59 PM PDT 24
Finished Jul 06 05:19:01 PM PDT 24
Peak memory 191904 kb
Host smart-e5563c36-c4f0-46a4-859c-dc6cae4daa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193384699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.193384699
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2426624584
Short name T239
Test name
Test status
Simulation time 8940944504 ps
CPU time 7.53 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:18:56 PM PDT 24
Peak memory 196956 kb
Host smart-66de2ec2-0574-4c82-8519-8f0e0e1c5e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426624584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2426624584
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.4052202790
Short name T227
Test name
Test status
Simulation time 477019607 ps
CPU time 0.93 seconds
Started Jul 06 05:19:04 PM PDT 24
Finished Jul 06 05:19:07 PM PDT 24
Peak memory 196712 kb
Host smart-d317d951-629a-4694-8212-777862c0f70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052202790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4052202790
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1813011210
Short name T230
Test name
Test status
Simulation time 49493029580 ps
CPU time 50.28 seconds
Started Jul 06 05:18:47 PM PDT 24
Finished Jul 06 05:19:38 PM PDT 24
Peak memory 191956 kb
Host smart-0d9973a2-9692-449c-992e-9e12ea5049c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813011210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1813011210
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1491198728
Short name T245
Test name
Test status
Simulation time 381129566 ps
CPU time 1.17 seconds
Started Jul 06 05:19:03 PM PDT 24
Finished Jul 06 05:19:05 PM PDT 24
Peak memory 191892 kb
Host smart-5a682c0e-d75e-42a1-b03b-2efe9a007a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491198728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1491198728
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2161084490
Short name T228
Test name
Test status
Simulation time 17559740129 ps
CPU time 6.55 seconds
Started Jul 06 05:19:05 PM PDT 24
Finished Jul 06 05:19:13 PM PDT 24
Peak memory 196952 kb
Host smart-d83159d0-cc99-404c-acc8-aa034df3d408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161084490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2161084490
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2086046483
Short name T47
Test name
Test status
Simulation time 498111211 ps
CPU time 1.44 seconds
Started Jul 06 05:18:50 PM PDT 24
Finished Jul 06 05:18:52 PM PDT 24
Peak memory 191920 kb
Host smart-8dde21ef-821b-4df3-969b-1c6bff49117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086046483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2086046483
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3108684665
Short name T219
Test name
Test status
Simulation time 54297807823 ps
CPU time 19.93 seconds
Started Jul 06 05:18:19 PM PDT 24
Finished Jul 06 05:18:39 PM PDT 24
Peak memory 191988 kb
Host smart-f94c3ea1-33b7-485c-91db-dcbf485dc0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108684665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3108684665
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2598507620
Short name T17
Test name
Test status
Simulation time 8008420397 ps
CPU time 5.86 seconds
Started Jul 06 05:18:18 PM PDT 24
Finished Jul 06 05:18:24 PM PDT 24
Peak memory 215836 kb
Host smart-26870dbc-9520-438d-9211-70bdde90082e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598507620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2598507620
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.26915464
Short name T272
Test name
Test status
Simulation time 559863573 ps
CPU time 0.66 seconds
Started Jul 06 05:18:14 PM PDT 24
Finished Jul 06 05:18:14 PM PDT 24
Peak memory 191900 kb
Host smart-42fdcb90-09e1-4622-9ad5-5adb133219ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26915464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.26915464
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2287406914
Short name T252
Test name
Test status
Simulation time 52394811791 ps
CPU time 8.88 seconds
Started Jul 06 05:19:06 PM PDT 24
Finished Jul 06 05:19:16 PM PDT 24
Peak memory 196996 kb
Host smart-836b1a98-e45a-4cf0-aabe-1ac43d119c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287406914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2287406914
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1644094594
Short name T259
Test name
Test status
Simulation time 456143016 ps
CPU time 0.74 seconds
Started Jul 06 05:19:00 PM PDT 24
Finished Jul 06 05:19:01 PM PDT 24
Peak memory 191872 kb
Host smart-52e8c670-4259-4e98-89f3-71b5484de549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644094594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1644094594
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3364433179
Short name T170
Test name
Test status
Simulation time 571682132 ps
CPU time 1.46 seconds
Started Jul 06 05:19:01 PM PDT 24
Finished Jul 06 05:19:03 PM PDT 24
Peak memory 196684 kb
Host smart-41758af8-1359-488c-a0b8-0a6019e25749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364433179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3364433179
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.130117154
Short name T49
Test name
Test status
Simulation time 15123303696 ps
CPU time 6.21 seconds
Started Jul 06 05:18:50 PM PDT 24
Finished Jul 06 05:18:56 PM PDT 24
Peak memory 191864 kb
Host smart-6216f31d-7192-4f24-a969-79bc73d14770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130117154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.130117154
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1170564111
Short name T226
Test name
Test status
Simulation time 416017861 ps
CPU time 0.74 seconds
Started Jul 06 05:19:00 PM PDT 24
Finished Jul 06 05:19:01 PM PDT 24
Peak memory 191876 kb
Host smart-9f5eb54b-a77f-472d-9833-dfeefc923d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170564111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1170564111
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.4211893002
Short name T240
Test name
Test status
Simulation time 11864404152 ps
CPU time 1.44 seconds
Started Jul 06 05:19:01 PM PDT 24
Finished Jul 06 05:19:03 PM PDT 24
Peak memory 191968 kb
Host smart-68579fe7-e0db-4dc1-a738-03b32ff02a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211893002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4211893002
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3797876880
Short name T271
Test name
Test status
Simulation time 504640145 ps
CPU time 1.03 seconds
Started Jul 06 05:18:51 PM PDT 24
Finished Jul 06 05:18:52 PM PDT 24
Peak memory 191924 kb
Host smart-387cf643-1e9a-4ab8-a879-4f0bbc40df46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797876880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3797876880
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.729946356
Short name T192
Test name
Test status
Simulation time 168552307435 ps
CPU time 250.53 seconds
Started Jul 06 05:19:03 PM PDT 24
Finished Jul 06 05:23:14 PM PDT 24
Peak memory 198340 kb
Host smart-63c7169f-c5d6-455e-9b5e-493b8d36f575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729946356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.729946356
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2408616995
Short name T257
Test name
Test status
Simulation time 37646781390 ps
CPU time 13.85 seconds
Started Jul 06 05:19:00 PM PDT 24
Finished Jul 06 05:19:14 PM PDT 24
Peak memory 196984 kb
Host smart-7c5d2f83-9dad-4ae9-8dc9-d05798d11860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408616995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2408616995
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1359433312
Short name T247
Test name
Test status
Simulation time 428124370 ps
CPU time 1.21 seconds
Started Jul 06 05:18:50 PM PDT 24
Finished Jul 06 05:18:52 PM PDT 24
Peak memory 196712 kb
Host smart-a7ff9c1c-ccca-4645-83d8-fcc3c5da0b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359433312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1359433312
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3399799557
Short name T276
Test name
Test status
Simulation time 34219665166 ps
CPU time 12.73 seconds
Started Jul 06 05:19:01 PM PDT 24
Finished Jul 06 05:19:14 PM PDT 24
Peak memory 191988 kb
Host smart-404a1aa6-f528-4247-8410-4ba91c790a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399799557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3399799557
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.920177418
Short name T216
Test name
Test status
Simulation time 465738749 ps
CPU time 0.96 seconds
Started Jul 06 05:18:55 PM PDT 24
Finished Jul 06 05:18:56 PM PDT 24
Peak memory 191892 kb
Host smart-7f99cf00-37ee-4e66-af73-3ad2998772ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920177418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.920177418
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.441479222
Short name T6
Test name
Test status
Simulation time 479401340 ps
CPU time 0.76 seconds
Started Jul 06 05:18:55 PM PDT 24
Finished Jul 06 05:18:56 PM PDT 24
Peak memory 196728 kb
Host smart-cfff5853-d6e0-4dcb-9b7e-614aa7e7b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441479222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.441479222
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2048444097
Short name T91
Test name
Test status
Simulation time 8942325891 ps
CPU time 3.5 seconds
Started Jul 06 05:18:56 PM PDT 24
Finished Jul 06 05:18:59 PM PDT 24
Peak memory 191968 kb
Host smart-4a08fbeb-4e5d-4245-aa93-c871195620d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048444097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2048444097
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.840572969
Short name T256
Test name
Test status
Simulation time 508113973 ps
CPU time 0.69 seconds
Started Jul 06 05:19:06 PM PDT 24
Finished Jul 06 05:19:08 PM PDT 24
Peak memory 191888 kb
Host smart-b83cb35f-e8f1-49d7-bde5-cf06aad53cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840572969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.840572969
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3222999063
Short name T186
Test name
Test status
Simulation time 111820015596 ps
CPU time 38.05 seconds
Started Jul 06 05:18:50 PM PDT 24
Finished Jul 06 05:19:28 PM PDT 24
Peak memory 191976 kb
Host smart-c786310d-7395-4113-aeaf-d71888c1cd7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222999063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3222999063
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.171509810
Short name T237
Test name
Test status
Simulation time 25585642777 ps
CPU time 18.94 seconds
Started Jul 06 05:19:08 PM PDT 24
Finished Jul 06 05:19:27 PM PDT 24
Peak memory 196960 kb
Host smart-ff5db7f6-a0fc-4307-98e4-bc1f2ceb49a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171509810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.171509810
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1937016438
Short name T201
Test name
Test status
Simulation time 584677030 ps
CPU time 0.93 seconds
Started Jul 06 05:18:48 PM PDT 24
Finished Jul 06 05:18:50 PM PDT 24
Peak memory 191884 kb
Host smart-08948726-1b10-4061-9956-af4eaba6aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937016438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1937016438
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.472425459
Short name T13
Test name
Test status
Simulation time 10535313087 ps
CPU time 16.8 seconds
Started Jul 06 05:18:49 PM PDT 24
Finished Jul 06 05:19:06 PM PDT 24
Peak memory 196988 kb
Host smart-2fdfa683-2981-45f0-b530-34de1a4a144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472425459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.472425459
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4214228799
Short name T281
Test name
Test status
Simulation time 407184003 ps
CPU time 1.14 seconds
Started Jul 06 05:18:59 PM PDT 24
Finished Jul 06 05:19:00 PM PDT 24
Peak memory 196720 kb
Host smart-01d02194-1c8e-4501-ad15-d067d3158be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214228799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4214228799
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2197753391
Short name T7
Test name
Test status
Simulation time 24527354260 ps
CPU time 40.32 seconds
Started Jul 06 05:18:54 PM PDT 24
Finished Jul 06 05:19:35 PM PDT 24
Peak memory 191864 kb
Host smart-000d96ba-f0e1-4736-9232-ddd280d1355e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197753391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2197753391
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.4078102301
Short name T214
Test name
Test status
Simulation time 450249141 ps
CPU time 1.17 seconds
Started Jul 06 05:19:05 PM PDT 24
Finished Jul 06 05:19:07 PM PDT 24
Peak memory 191924 kb
Host smart-841fc7bc-a941-435a-ae60-c8f2af3406de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078102301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.4078102301
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3052399153
Short name T222
Test name
Test status
Simulation time 8447190434 ps
CPU time 6.51 seconds
Started Jul 06 05:18:58 PM PDT 24
Finished Jul 06 05:19:05 PM PDT 24
Peak memory 191932 kb
Host smart-a203879d-4c5b-434f-a103-560e8aef59e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052399153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3052399153
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1538842464
Short name T212
Test name
Test status
Simulation time 438023147 ps
CPU time 0.72 seconds
Started Jul 06 05:19:06 PM PDT 24
Finished Jul 06 05:19:08 PM PDT 24
Peak memory 191880 kb
Host smart-91bc1963-d24c-437b-90b1-4960135570d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538842464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1538842464
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2733578299
Short name T267
Test name
Test status
Simulation time 36164636123 ps
CPU time 24.41 seconds
Started Jul 06 05:18:18 PM PDT 24
Finished Jul 06 05:18:42 PM PDT 24
Peak memory 191948 kb
Host smart-dd09a1a4-4daa-4fa1-a4b2-1f0bb286adf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733578299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2733578299
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2556461728
Short name T273
Test name
Test status
Simulation time 580829265 ps
CPU time 1.02 seconds
Started Jul 06 05:18:18 PM PDT 24
Finished Jul 06 05:18:19 PM PDT 24
Peak memory 196756 kb
Host smart-b1f70e66-4d98-4210-87df-191f3a00cd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556461728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2556461728
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1704056691
Short name T11
Test name
Test status
Simulation time 420087391 ps
CPU time 0.72 seconds
Started Jul 06 05:18:32 PM PDT 24
Finished Jul 06 05:18:33 PM PDT 24
Peak memory 196700 kb
Host smart-b36fc0db-b24b-467b-9fdd-0208c1619db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704056691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1704056691
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.408970401
Short name T200
Test name
Test status
Simulation time 40064883980 ps
CPU time 13.03 seconds
Started Jul 06 05:18:16 PM PDT 24
Finished Jul 06 05:18:29 PM PDT 24
Peak memory 191988 kb
Host smart-f1b0d845-d16f-4dd1-8784-d599bfdf130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408970401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.408970401
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2921643459
Short name T254
Test name
Test status
Simulation time 424500922 ps
CPU time 0.86 seconds
Started Jul 06 05:18:18 PM PDT 24
Finished Jul 06 05:18:19 PM PDT 24
Peak memory 191788 kb
Host smart-5533a228-2c3c-4fb5-9e34-466a2a281871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921643459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2921643459
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1052188533
Short name T14
Test name
Test status
Simulation time 31057508494 ps
CPU time 43.44 seconds
Started Jul 06 05:18:18 PM PDT 24
Finished Jul 06 05:19:02 PM PDT 24
Peak memory 191952 kb
Host smart-a75a08b7-7278-4136-9023-babd546394ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052188533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1052188533
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3640076841
Short name T268
Test name
Test status
Simulation time 556810280 ps
CPU time 0.98 seconds
Started Jul 06 05:18:20 PM PDT 24
Finished Jul 06 05:18:21 PM PDT 24
Peak memory 191860 kb
Host smart-64b3853f-4033-48c6-912a-10915190e7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640076841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3640076841
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3377735479
Short name T203
Test name
Test status
Simulation time 48810470161 ps
CPU time 36.12 seconds
Started Jul 06 05:18:19 PM PDT 24
Finished Jul 06 05:18:55 PM PDT 24
Peak memory 191984 kb
Host smart-566d6ca0-0b56-4e45-b174-79f25e867885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377735479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3377735479
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.200646471
Short name T208
Test name
Test status
Simulation time 389356507 ps
CPU time 1.08 seconds
Started Jul 06 05:18:23 PM PDT 24
Finished Jul 06 05:18:24 PM PDT 24
Peak memory 191892 kb
Host smart-4e01cf50-f42b-4b2a-8831-8cc7ffa29975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200646471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.200646471
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3366341446
Short name T76
Test name
Test status
Simulation time 32359280930 ps
CPU time 52.43 seconds
Started Jul 06 05:18:21 PM PDT 24
Finished Jul 06 05:19:13 PM PDT 24
Peak memory 191984 kb
Host smart-77ca561c-8099-4a31-a9e9-015020e48fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366341446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3366341446
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1130358774
Short name T223
Test name
Test status
Simulation time 432066313 ps
CPU time 1.16 seconds
Started Jul 06 05:18:30 PM PDT 24
Finished Jul 06 05:18:31 PM PDT 24
Peak memory 191908 kb
Host smart-3ab202ae-0d6c-43d5-9691-bea8f9d2c5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130358774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1130358774
Directory /workspace/9.aon_timer_smoke/latest
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