Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 30033 1 T1 1079 T2 12 T4 12
bark[1] 205 1 T173 59 T26 21 T108 14
bark[2] 577 1 T9 21 T40 37 T26 26
bark[3] 825 1 T40 230 T24 21 T105 76
bark[4] 587 1 T9 263 T18 21 T40 51
bark[5] 196 1 T47 21 T121 21 T126 42
bark[6] 699 1 T9 62 T46 14 T80 21
bark[7] 574 1 T3 14 T12 21 T42 21
bark[8] 659 1 T39 64 T26 21 T105 14
bark[9] 399 1 T6 14 T99 21 T25 33
bark[10] 244 1 T41 14 T135 30 T166 21
bark[11] 624 1 T1 21 T113 42 T43 194
bark[12] 696 1 T32 258 T99 21 T173 30
bark[13] 700 1 T14 26 T102 14 T113 21
bark[14] 1025 1 T1 61 T9 447 T14 26
bark[15] 772 1 T31 21 T18 21 T26 117
bark[16] 771 1 T9 21 T79 21 T187 14
bark[17] 257 1 T75 21 T148 21 T120 98
bark[18] 1243 1 T1 467 T24 120 T92 107
bark[19] 521 1 T31 21 T123 21 T74 315
bark[20] 335 1 T123 104 T111 26 T153 14
bark[21] 342 1 T9 21 T12 44 T26 47
bark[22] 1102 1 T1 21 T31 436 T147 42
bark[23] 387 1 T9 35 T172 14 T14 58
bark[24] 334 1 T40 30 T24 21 T26 26
bark[25] 557 1 T7 26 T99 23 T113 30
bark[26] 721 1 T31 106 T25 21 T140 35
bark[27] 391 1 T9 73 T80 21 T152 21
bark[28] 387 1 T173 42 T105 21 T111 157
bark[29] 453 1 T11 14 T108 40 T147 105
bark[30] 197 1 T178 21 T40 21 T135 21
bark[31] 547 1 T8 14 T32 21 T42 21
bark_0 4865 1 T1 77 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 29895 1 T1 1072 T2 11 T3 13
bite[1] 458 1 T9 61 T19 38 T40 30
bite[2] 664 1 T6 13 T9 21 T31 21
bite[3] 149 1 T26 21 T147 30 T140 21
bite[4] 476 1 T31 21 T178 13 T24 70
bite[5] 173 1 T118 21 T148 21 T142 21
bite[6] 609 1 T123 21 T135 26 T166 21
bite[7] 1035 1 T1 466 T12 21 T14 58
bite[8] 338 1 T41 13 T108 21 T168 21
bite[9] 736 1 T1 21 T18 21 T135 30
bite[10] 756 1 T111 156 T124 32 T126 38
bite[11] 489 1 T32 257 T40 6 T43 42
bite[12] 212 1 T8 13 T14 26 T198 13
bite[13] 344 1 T172 13 T32 21 T102 13
bite[14] 1304 1 T12 44 T31 435 T173 78
bite[15] 263 1 T1 60 T18 21 T25 21
bite[16] 946 1 T178 21 T40 30 T135 21
bite[17] 786 1 T113 30 T108 13 T147 21
bite[18] 230 1 T152 30 T130 13 T138 21
bite[19] 737 1 T31 105 T39 63 T173 30
bite[20] 164 1 T152 21 T156 21 T183 101
bite[21] 736 1 T1 21 T7 25 T9 262
bite[22] 413 1 T42 21 T108 40 T166 72
bite[23] 869 1 T9 35 T105 21 T92 104
bite[24] 547 1 T123 104 T24 49 T108 21
bite[25] 771 1 T9 446 T113 21 T47 30
bite[26] 602 1 T113 57 T24 21 T26 46
bite[27] 309 1 T26 137 T160 13 T93 74
bite[28] 518 1 T9 21 T14 26 T26 25
bite[29] 559 1 T9 21 T99 21 T80 21
bite[30] 239 1 T99 22 T40 30 T91 25
bite[31] 528 1 T40 21 T46 13 T47 30
bite_0 5370 1 T1 86 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 43679 1 T1 1108 T2 19 T3 21
auto[1] 8546 1 T1 618 T7 37 T9 192


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1860 1 T1 40 T2 9 T7 95
prescale[1] 798 1 T7 41 T9 80 T198 24
prescale[2] 814 1 T1 276 T18 19 T32 96
prescale[3] 930 1 T1 2 T99 19 T198 37
prescale[4] 1126 1 T1 28 T7 24 T9 49
prescale[5] 860 1 T9 140 T31 19 T32 35
prescale[6] 909 1 T1 70 T4 9 T7 81
prescale[7] 619 1 T204 9 T19 24 T32 28
prescale[8] 870 1 T1 28 T7 70 T9 12
prescale[9] 975 1 T1 36 T7 32 T14 36
prescale[10] 1151 1 T1 49 T9 19 T12 28
prescale[11] 1048 1 T1 19 T12 23 T40 36
prescale[12] 865 1 T1 109 T9 54 T31 2
prescale[13] 1007 1 T7 39 T31 24 T19 19
prescale[14] 912 1 T1 135 T14 2 T39 28
prescale[15] 698 1 T9 109 T18 40 T32 132
prescale[16] 740 1 T32 2 T99 32 T47 2
prescale[17] 650 1 T7 2 T9 2 T31 19
prescale[18] 625 1 T1 146 T7 2 T9 19
prescale[19] 795 1 T1 232 T7 2 T32 2
prescale[20] 737 1 T1 19 T7 19 T43 117
prescale[21] 701 1 T9 2 T19 37 T39 23
prescale[22] 440 1 T9 107 T10 9 T99 19
prescale[23] 882 1 T9 2 T18 28 T173 37
prescale[24] 1148 1 T1 2 T7 95 T31 19
prescale[25] 565 1 T1 140 T5 9 T7 2
prescale[26] 747 1 T9 19 T14 30 T31 2
prescale[27] 877 1 T9 78 T14 2 T31 32
prescale[28] 699 1 T1 2 T9 19 T31 64
prescale[29] 485 1 T1 104 T9 9 T39 19
prescale[30] 704 1 T1 19 T7 34 T173 49
prescale[31] 627 1 T7 2 T9 74 T31 2
prescale_0 25361 1 T1 270 T2 10 T3 21


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 39323 1 T1 1427 T2 9 T3 21
auto[1] 12902 1 T1 299 T2 10 T7 190


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 52225 1 T1 1726 T2 19 T3 21


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 31240 1 T1 1203 T2 14 T3 1
wkup[1] 215 1 T1 26 T7 8 T31 21
wkup[2] 224 1 T1 21 T40 21 T93 51
wkup[3] 433 1 T9 21 T31 21 T19 21
wkup[4] 285 1 T40 51 T25 21 T26 21
wkup[5] 155 1 T31 21 T32 21 T42 21
wkup[6] 293 1 T9 39 T25 21 T92 21
wkup[7] 318 1 T9 21 T12 15 T24 21
wkup[8] 241 1 T1 26 T32 21 T40 30
wkup[9] 328 1 T9 21 T32 42 T40 21
wkup[10] 313 1 T9 21 T31 26 T74 21
wkup[11] 242 1 T1 21 T3 15 T8 15
wkup[12] 261 1 T19 21 T91 21 T108 21
wkup[13] 202 1 T1 21 T32 31 T123 21
wkup[14] 276 1 T1 21 T32 21 T41 15
wkup[15] 147 1 T120 21 T95 21 T132 42
wkup[16] 243 1 T1 21 T7 21 T9 30
wkup[17] 314 1 T9 65 T12 44 T40 21
wkup[18] 286 1 T7 21 T113 30 T40 21
wkup[19] 397 1 T1 21 T9 40 T123 30
wkup[20] 214 1 T1 21 T9 21 T123 21
wkup[21] 230 1 T31 21 T26 21 T167 42
wkup[22] 274 1 T9 60 T32 21 T40 21
wkup[23] 343 1 T1 30 T9 21 T25 42
wkup[24] 343 1 T9 26 T14 6 T32 21
wkup[25] 170 1 T1 21 T7 8 T31 21
wkup[26] 167 1 T32 42 T43 21 T91 21
wkup[27] 213 1 T7 15 T9 21 T39 8
wkup[28] 298 1 T11 15 T14 58 T173 21
wkup[29] 195 1 T7 30 T19 21 T40 8
wkup[30] 270 1 T105 15 T92 21 T121 21
wkup[31] 182 1 T113 21 T92 26 T145 15
wkup[32] 197 1 T156 21 T177 15 T140 21
wkup[33] 229 1 T31 21 T135 21 T138 21
wkup[34] 267 1 T31 39 T173 30 T111 21
wkup[35] 244 1 T7 21 T31 21 T102 15
wkup[36] 279 1 T32 30 T40 30 T24 21
wkup[37] 290 1 T32 21 T24 21 T105 21
wkup[38] 230 1 T31 21 T99 21 T173 21
wkup[39] 470 1 T31 42 T74 21 T121 21
wkup[40] 330 1 T1 47 T31 21 T47 30
wkup[41] 84 1 T113 21 T114 21 T49 21
wkup[42] 376 1 T6 15 T7 26 T135 26
wkup[43] 252 1 T9 21 T39 21 T108 21
wkup[44] 408 1 T1 42 T31 15 T40 21
wkup[45] 272 1 T31 36 T32 21 T40 21
wkup[46] 230 1 T25 21 T105 21 T92 21
wkup[47] 354 1 T31 21 T99 21 T178 30
wkup[48] 275 1 T9 21 T173 21 T43 30
wkup[49] 257 1 T1 47 T31 21 T198 15
wkup[50] 304 1 T18 21 T40 42 T26 21
wkup[51] 200 1 T26 21 T74 21 T169 21
wkup[52] 278 1 T1 42 T12 21 T14 15
wkup[53] 533 1 T7 21 T14 26 T31 61
wkup[54] 273 1 T9 21 T25 21 T91 21
wkup[55] 102 1 T124 21 T183 30 T115 15
wkup[56] 379 1 T99 24 T135 30 T25 21
wkup[57] 400 1 T172 15 T14 26 T39 21
wkup[58] 145 1 T47 26 T156 30 T140 21
wkup[59] 218 1 T1 15 T32 21 T173 21
wkup[60] 266 1 T18 21 T173 21 T40 21
wkup[61] 287 1 T24 15 T105 21 T47 21
wkup[62] 273 1 T1 21 T7 21 T31 21
wkup[63] 382 1 T9 30 T39 8 T173 21
wkup_0 3829 1 T1 59 T2 5 T3 5

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