Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.09 99.33 93.67 100.00 98.40 99.51 49.66


Total test records in report: 425
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T33 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3908127963 Jul 07 05:56:04 PM PDT 24 Jul 07 05:56:06 PM PDT 24 474740287 ps
T284 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1325630603 Jul 07 05:56:19 PM PDT 24 Jul 07 05:56:20 PM PDT 24 416245079 ps
T38 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.626780581 Jul 07 05:55:56 PM PDT 24 Jul 07 05:55:58 PM PDT 24 490255662 ps
T34 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2468665089 Jul 07 05:56:13 PM PDT 24 Jul 07 05:56:15 PM PDT 24 550734799 ps
T285 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.403493131 Jul 07 05:55:42 PM PDT 24 Jul 07 05:55:45 PM PDT 24 476766800 ps
T286 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2778947839 Jul 07 05:56:13 PM PDT 24 Jul 07 05:56:14 PM PDT 24 445331680 ps
T35 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2975882851 Jul 07 05:55:57 PM PDT 24 Jul 07 05:56:00 PM PDT 24 4354797503 ps
T287 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1850851861 Jul 07 05:56:21 PM PDT 24 Jul 07 05:56:23 PM PDT 24 404826789 ps
T288 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2983782200 Jul 07 05:56:13 PM PDT 24 Jul 07 05:56:14 PM PDT 24 400414929 ps
T289 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1912192461 Jul 07 05:55:48 PM PDT 24 Jul 07 05:55:49 PM PDT 24 574783052 ps
T36 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1068829855 Jul 07 05:55:51 PM PDT 24 Jul 07 05:56:04 PM PDT 24 8407333266 ps
T205 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2933071392 Jul 07 05:55:42 PM PDT 24 Jul 07 05:55:43 PM PDT 24 661474750 ps
T82 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1352980350 Jul 07 05:56:17 PM PDT 24 Jul 07 05:56:22 PM PDT 24 2859205004 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3859635088 Jul 07 05:55:54 PM PDT 24 Jul 07 05:55:55 PM PDT 24 689446998 ps
T53 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.721865953 Jul 07 05:55:51 PM PDT 24 Jul 07 05:55:52 PM PDT 24 537801191 ps
T290 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.849376098 Jul 07 05:56:14 PM PDT 24 Jul 07 05:56:15 PM PDT 24 507426429 ps
T83 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3519309392 Jul 07 05:55:53 PM PDT 24 Jul 07 05:55:54 PM PDT 24 1286432771 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.861781250 Jul 07 05:55:45 PM PDT 24 Jul 07 05:55:46 PM PDT 24 305476888 ps
T292 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.177727400 Jul 07 05:55:45 PM PDT 24 Jul 07 05:55:46 PM PDT 24 512561562 ps
T84 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3505739793 Jul 07 05:55:41 PM PDT 24 Jul 07 05:55:43 PM PDT 24 535313658 ps
T206 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2729592505 Jul 07 05:56:16 PM PDT 24 Jul 07 05:56:17 PM PDT 24 412021354 ps
T37 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3890501807 Jul 07 05:56:09 PM PDT 24 Jul 07 05:56:22 PM PDT 24 8402676822 ps
T293 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2121019417 Jul 07 05:56:01 PM PDT 24 Jul 07 05:56:03 PM PDT 24 415269563 ps
T201 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2444747739 Jul 07 05:55:56 PM PDT 24 Jul 07 05:56:03 PM PDT 24 3973413556 ps
T294 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3812227958 Jul 07 05:55:57 PM PDT 24 Jul 07 05:55:58 PM PDT 24 317463969 ps
T295 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.578203851 Jul 07 05:55:53 PM PDT 24 Jul 07 05:55:56 PM PDT 24 326006018 ps
T202 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.770715202 Jul 07 05:55:57 PM PDT 24 Jul 07 05:56:11 PM PDT 24 8546128766 ps
T85 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.123954979 Jul 07 05:56:11 PM PDT 24 Jul 07 05:56:13 PM PDT 24 479988040 ps
T86 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2815340384 Jul 07 05:56:06 PM PDT 24 Jul 07 05:56:07 PM PDT 24 501979999 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3411540894 Jul 07 05:55:42 PM PDT 24 Jul 07 05:55:44 PM PDT 24 1218907312 ps
T296 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.430815755 Jul 07 05:56:07 PM PDT 24 Jul 07 05:56:08 PM PDT 24 331242294 ps
T297 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1384591755 Jul 07 05:56:22 PM PDT 24 Jul 07 05:56:23 PM PDT 24 487353291 ps
T298 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.570240742 Jul 07 05:56:20 PM PDT 24 Jul 07 05:56:21 PM PDT 24 477203253 ps
T299 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1921350402 Jul 07 05:55:56 PM PDT 24 Jul 07 05:55:58 PM PDT 24 550992345 ps
T300 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3508919724 Jul 07 05:56:14 PM PDT 24 Jul 07 05:56:15 PM PDT 24 459848235 ps
T301 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.320431044 Jul 07 05:55:58 PM PDT 24 Jul 07 05:55:59 PM PDT 24 435321294 ps
T302 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3445408345 Jul 07 05:55:42 PM PDT 24 Jul 07 05:55:51 PM PDT 24 7031704442 ps
T87 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.133650331 Jul 07 05:56:03 PM PDT 24 Jul 07 05:56:06 PM PDT 24 1694070331 ps
T303 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1176896590 Jul 07 05:56:17 PM PDT 24 Jul 07 05:56:19 PM PDT 24 397290302 ps
T203 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.385975274 Jul 07 05:56:00 PM PDT 24 Jul 07 05:56:03 PM PDT 24 8314248151 ps
T304 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1673869490 Jul 07 05:56:04 PM PDT 24 Jul 07 05:56:16 PM PDT 24 8312102892 ps
T55 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2399765004 Jul 07 05:56:07 PM PDT 24 Jul 07 05:56:08 PM PDT 24 313266005 ps
T88 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.432371004 Jul 07 05:55:44 PM PDT 24 Jul 07 05:55:46 PM PDT 24 1549540429 ps
T305 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1952156689 Jul 07 05:56:11 PM PDT 24 Jul 07 05:56:11 PM PDT 24 295312609 ps
T306 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1576745621 Jul 07 05:56:21 PM PDT 24 Jul 07 05:56:22 PM PDT 24 355519739 ps
T307 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2100270960 Jul 07 05:55:46 PM PDT 24 Jul 07 05:55:47 PM PDT 24 432757864 ps
T89 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.442924175 Jul 07 05:56:04 PM PDT 24 Jul 07 05:56:05 PM PDT 24 1238913983 ps
T308 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1519114412 Jul 07 05:55:54 PM PDT 24 Jul 07 05:55:55 PM PDT 24 371380579 ps
T309 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3159416321 Jul 07 05:55:51 PM PDT 24 Jul 07 05:55:52 PM PDT 24 387601873 ps
T310 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1158076944 Jul 07 05:56:18 PM PDT 24 Jul 07 05:56:19 PM PDT 24 484700789 ps
T311 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2395758304 Jul 07 05:56:20 PM PDT 24 Jul 07 05:56:21 PM PDT 24 451400338 ps
T90 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.28907628 Jul 07 05:56:08 PM PDT 24 Jul 07 05:56:10 PM PDT 24 2051396953 ps
T312 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3996990168 Jul 07 05:56:09 PM PDT 24 Jul 07 05:56:10 PM PDT 24 455667017 ps
T313 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3292802342 Jul 07 05:56:13 PM PDT 24 Jul 07 05:56:19 PM PDT 24 2667707814 ps
T314 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3124343837 Jul 07 05:56:12 PM PDT 24 Jul 07 05:56:15 PM PDT 24 4704725761 ps
T315 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3198526261 Jul 07 05:56:22 PM PDT 24 Jul 07 05:56:23 PM PDT 24 323162970 ps
T57 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4026973413 Jul 07 05:56:04 PM PDT 24 Jul 07 05:56:06 PM PDT 24 516741001 ps
T316 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2697543100 Jul 07 05:56:06 PM PDT 24 Jul 07 05:56:10 PM PDT 24 3841567651 ps
T317 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4029712399 Jul 07 05:56:10 PM PDT 24 Jul 07 05:56:13 PM PDT 24 420599938 ps
T318 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.22122429 Jul 07 05:55:48 PM PDT 24 Jul 07 05:55:49 PM PDT 24 388892590 ps
T319 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1770190374 Jul 07 05:55:54 PM PDT 24 Jul 07 05:55:55 PM PDT 24 326450710 ps
T320 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.977975654 Jul 07 05:56:14 PM PDT 24 Jul 07 05:56:16 PM PDT 24 483102431 ps
T321 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2847160966 Jul 07 05:56:15 PM PDT 24 Jul 07 05:56:16 PM PDT 24 321116150 ps
T322 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3998168445 Jul 07 05:56:21 PM PDT 24 Jul 07 05:56:22 PM PDT 24 303741652 ps
T323 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.478762661 Jul 07 05:56:03 PM PDT 24 Jul 07 05:56:15 PM PDT 24 8282946271 ps
T324 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4072970801 Jul 07 05:56:23 PM PDT 24 Jul 07 05:56:24 PM PDT 24 317754053 ps
T325 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3352729797 Jul 07 05:55:58 PM PDT 24 Jul 07 05:56:04 PM PDT 24 3748217363 ps
T326 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1070236924 Jul 07 05:56:07 PM PDT 24 Jul 07 05:56:09 PM PDT 24 1906508715 ps
T327 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1657761211 Jul 07 05:56:21 PM PDT 24 Jul 07 05:56:22 PM PDT 24 366655261 ps
T328 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1579773514 Jul 07 05:55:57 PM PDT 24 Jul 07 05:55:58 PM PDT 24 2331325166 ps
T329 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3718902688 Jul 07 05:56:11 PM PDT 24 Jul 07 05:56:18 PM PDT 24 4168674778 ps
T330 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2527797491 Jul 07 05:56:22 PM PDT 24 Jul 07 05:56:23 PM PDT 24 466603266 ps
T331 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1278153810 Jul 07 05:55:50 PM PDT 24 Jul 07 05:55:53 PM PDT 24 7954996454 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1449158210 Jul 07 05:55:43 PM PDT 24 Jul 07 05:55:44 PM PDT 24 522307881 ps
T58 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3564779310 Jul 07 05:56:09 PM PDT 24 Jul 07 05:56:10 PM PDT 24 509523244 ps
T333 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3802218767 Jul 07 05:56:03 PM PDT 24 Jul 07 05:56:04 PM PDT 24 635314704 ps
T334 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3973129969 Jul 07 05:56:07 PM PDT 24 Jul 07 05:56:09 PM PDT 24 276112274 ps
T335 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3329400580 Jul 07 05:55:50 PM PDT 24 Jul 07 05:55:51 PM PDT 24 393597233 ps
T59 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4022897962 Jul 07 05:55:47 PM PDT 24 Jul 07 05:55:48 PM PDT 24 441160859 ps
T336 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2954486311 Jul 07 05:55:38 PM PDT 24 Jul 07 05:55:39 PM PDT 24 739034599 ps
T337 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4079772834 Jul 07 05:56:02 PM PDT 24 Jul 07 05:56:05 PM PDT 24 2782593226 ps
T338 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4222605626 Jul 07 05:56:01 PM PDT 24 Jul 07 05:56:06 PM PDT 24 2787758589 ps
T339 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3254634699 Jul 07 05:55:54 PM PDT 24 Jul 07 05:55:57 PM PDT 24 1311656260 ps
T340 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1886877787 Jul 07 05:56:21 PM PDT 24 Jul 07 05:56:22 PM PDT 24 459037389 ps
T341 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1514354343 Jul 07 05:55:53 PM PDT 24 Jul 07 05:55:54 PM PDT 24 395275055 ps
T342 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1221648576 Jul 07 05:56:23 PM PDT 24 Jul 07 05:56:24 PM PDT 24 300615577 ps
T343 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2432529986 Jul 07 05:55:48 PM PDT 24 Jul 07 05:55:49 PM PDT 24 338519890 ps
T344 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.877438721 Jul 07 05:55:51 PM PDT 24 Jul 07 05:55:53 PM PDT 24 570860389 ps
T345 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4268586000 Jul 07 05:56:23 PM PDT 24 Jul 07 05:56:24 PM PDT 24 520125990 ps
T346 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.147388523 Jul 07 05:56:19 PM PDT 24 Jul 07 05:56:20 PM PDT 24 366284672 ps
T347 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3963476286 Jul 07 05:56:07 PM PDT 24 Jul 07 05:56:09 PM PDT 24 519133022 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.344036944 Jul 07 05:55:38 PM PDT 24 Jul 07 05:55:40 PM PDT 24 326698629 ps
T349 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3652897566 Jul 07 05:56:02 PM PDT 24 Jul 07 05:56:03 PM PDT 24 467392972 ps
T60 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3644956265 Jul 07 05:56:14 PM PDT 24 Jul 07 05:56:15 PM PDT 24 428112102 ps
T350 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4215318687 Jul 07 05:55:51 PM PDT 24 Jul 07 05:55:54 PM PDT 24 2222908691 ps
T351 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2514470355 Jul 07 05:56:20 PM PDT 24 Jul 07 05:56:21 PM PDT 24 304788703 ps
T352 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1323627017 Jul 07 05:56:10 PM PDT 24 Jul 07 05:56:11 PM PDT 24 1255343654 ps
T353 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2040836535 Jul 07 05:56:04 PM PDT 24 Jul 07 05:56:05 PM PDT 24 385603743 ps
T354 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1809945188 Jul 07 05:56:21 PM PDT 24 Jul 07 05:56:22 PM PDT 24 337898563 ps
T355 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3807223837 Jul 07 05:55:57 PM PDT 24 Jul 07 05:55:59 PM PDT 24 2269062505 ps
T356 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4038686760 Jul 07 05:56:07 PM PDT 24 Jul 07 05:56:08 PM PDT 24 666280906 ps
T357 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3692409611 Jul 07 05:55:53 PM PDT 24 Jul 07 05:55:57 PM PDT 24 2535984054 ps
T358 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.60278677 Jul 07 05:55:50 PM PDT 24 Jul 07 05:55:51 PM PDT 24 335410020 ps
T359 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2534050248 Jul 07 05:55:51 PM PDT 24 Jul 07 05:55:53 PM PDT 24 4429993960 ps
T360 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.409766489 Jul 07 05:56:04 PM PDT 24 Jul 07 05:56:05 PM PDT 24 1549213980 ps
T361 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.190426198 Jul 07 05:56:08 PM PDT 24 Jul 07 05:56:11 PM PDT 24 478695831 ps
T362 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.993541200 Jul 07 05:55:51 PM PDT 24 Jul 07 05:55:53 PM PDT 24 328541261 ps
T363 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3390961255 Jul 07 05:55:49 PM PDT 24 Jul 07 05:55:53 PM PDT 24 1301252791 ps
T364 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2982426341 Jul 07 05:56:00 PM PDT 24 Jul 07 05:56:01 PM PDT 24 368672990 ps
T365 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.305674766 Jul 07 05:55:47 PM PDT 24 Jul 07 05:56:11 PM PDT 24 7228522552 ps
T366 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.435344591 Jul 07 05:56:13 PM PDT 24 Jul 07 05:56:18 PM PDT 24 2867611771 ps
T367 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.7505810 Jul 07 05:56:05 PM PDT 24 Jul 07 05:56:07 PM PDT 24 394021089 ps
T61 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1030768057 Jul 07 05:56:07 PM PDT 24 Jul 07 05:56:08 PM PDT 24 371849153 ps
T368 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1115053726 Jul 07 05:56:10 PM PDT 24 Jul 07 05:56:22 PM PDT 24 8382862494 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1103862428 Jul 07 05:55:56 PM PDT 24 Jul 07 05:55:57 PM PDT 24 458983320 ps
T370 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3336437279 Jul 07 05:56:20 PM PDT 24 Jul 07 05:56:21 PM PDT 24 326263726 ps
T371 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3968796598 Jul 07 05:55:50 PM PDT 24 Jul 07 05:55:51 PM PDT 24 371445465 ps
T372 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1109248107 Jul 07 05:56:15 PM PDT 24 Jul 07 05:56:20 PM PDT 24 8738936780 ps
T373 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4016595701 Jul 07 05:56:06 PM PDT 24 Jul 07 05:56:07 PM PDT 24 407172258 ps
T374 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4155370283 Jul 07 05:56:19 PM PDT 24 Jul 07 05:56:20 PM PDT 24 436262830 ps
T375 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3906746451 Jul 07 05:55:57 PM PDT 24 Jul 07 05:56:00 PM PDT 24 499119285 ps
T376 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3620003017 Jul 07 05:56:20 PM PDT 24 Jul 07 05:56:24 PM PDT 24 2403223266 ps
T377 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.346911756 Jul 07 05:56:22 PM PDT 24 Jul 07 05:56:23 PM PDT 24 466966807 ps
T378 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2536207181 Jul 07 05:56:04 PM PDT 24 Jul 07 05:56:05 PM PDT 24 289984223 ps
T379 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2853032432 Jul 07 05:55:56 PM PDT 24 Jul 07 05:55:57 PM PDT 24 443184401 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2446095224 Jul 07 05:55:51 PM PDT 24 Jul 07 05:55:52 PM PDT 24 296089136 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.863593448 Jul 07 05:55:51 PM PDT 24 Jul 07 05:56:30 PM PDT 24 10202865017 ps
T381 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.105238335 Jul 07 05:56:18 PM PDT 24 Jul 07 05:56:19 PM PDT 24 349592618 ps
T382 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.528372552 Jul 07 05:55:53 PM PDT 24 Jul 07 05:55:54 PM PDT 24 408750812 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3999341417 Jul 07 05:55:56 PM PDT 24 Jul 07 05:55:57 PM PDT 24 313966816 ps
T384 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1013051786 Jul 07 05:56:10 PM PDT 24 Jul 07 05:56:12 PM PDT 24 431182575 ps
T385 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.186486402 Jul 07 05:56:16 PM PDT 24 Jul 07 05:56:17 PM PDT 24 499882156 ps
T386 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1351580330 Jul 07 05:56:15 PM PDT 24 Jul 07 05:56:17 PM PDT 24 319060781 ps
T387 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3525148193 Jul 07 05:56:05 PM PDT 24 Jul 07 05:56:20 PM PDT 24 8614045640 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.556393040 Jul 07 05:55:55 PM PDT 24 Jul 07 05:56:07 PM PDT 24 7301631609 ps
T389 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3749977491 Jul 07 05:56:01 PM PDT 24 Jul 07 05:56:02 PM PDT 24 461906069 ps
T390 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1360970524 Jul 07 05:56:06 PM PDT 24 Jul 07 05:56:09 PM PDT 24 396077723 ps
T391 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.594135700 Jul 07 05:55:47 PM PDT 24 Jul 07 05:55:57 PM PDT 24 8402421778 ps
T392 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1784967863 Jul 07 05:56:01 PM PDT 24 Jul 07 05:56:02 PM PDT 24 323032060 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1455085161 Jul 07 05:55:55 PM PDT 24 Jul 07 05:56:00 PM PDT 24 4015347165 ps
T393 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3085220573 Jul 07 05:56:04 PM PDT 24 Jul 07 05:56:06 PM PDT 24 601816067 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.426901487 Jul 07 05:55:44 PM PDT 24 Jul 07 05:55:45 PM PDT 24 526544442 ps
T394 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1684742291 Jul 07 05:56:20 PM PDT 24 Jul 07 05:56:22 PM PDT 24 326282526 ps
T395 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.914301297 Jul 07 05:56:14 PM PDT 24 Jul 07 05:56:14 PM PDT 24 465877595 ps
T396 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3037108733 Jul 07 05:56:17 PM PDT 24 Jul 07 05:56:19 PM PDT 24 614546997 ps
T397 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.428787446 Jul 07 05:56:12 PM PDT 24 Jul 07 05:56:13 PM PDT 24 492690028 ps
T398 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1982916125 Jul 07 05:56:20 PM PDT 24 Jul 07 05:56:21 PM PDT 24 385290045 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4254500515 Jul 07 05:55:45 PM PDT 24 Jul 07 05:55:47 PM PDT 24 793939507 ps
T400 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.715506437 Jul 07 05:56:27 PM PDT 24 Jul 07 05:56:28 PM PDT 24 545178473 ps
T401 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.913557122 Jul 07 05:55:53 PM PDT 24 Jul 07 05:55:55 PM PDT 24 402875772 ps
T402 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4081735310 Jul 07 05:55:50 PM PDT 24 Jul 07 05:55:52 PM PDT 24 487652826 ps
T403 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1667103408 Jul 07 05:56:20 PM PDT 24 Jul 07 05:56:21 PM PDT 24 368189313 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1713037832 Jul 07 05:55:56 PM PDT 24 Jul 07 05:55:57 PM PDT 24 314813097 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.248692901 Jul 07 05:55:45 PM PDT 24 Jul 07 05:55:46 PM PDT 24 486889157 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1198293191 Jul 07 05:55:46 PM PDT 24 Jul 07 05:55:48 PM PDT 24 342070031 ps
T407 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1382873963 Jul 07 05:55:54 PM PDT 24 Jul 07 05:55:55 PM PDT 24 354962696 ps
T408 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.143984203 Jul 07 05:56:00 PM PDT 24 Jul 07 05:56:01 PM PDT 24 464705084 ps
T409 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.220389747 Jul 07 05:55:50 PM PDT 24 Jul 07 05:55:51 PM PDT 24 566217192 ps
T410 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4050097080 Jul 07 05:55:52 PM PDT 24 Jul 07 05:55:53 PM PDT 24 486869259 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.47529275 Jul 07 05:55:51 PM PDT 24 Jul 07 05:55:52 PM PDT 24 643143329 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2048301272 Jul 07 05:55:51 PM PDT 24 Jul 07 05:55:55 PM PDT 24 1590168544 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1578547413 Jul 07 05:55:49 PM PDT 24 Jul 07 05:55:51 PM PDT 24 680667316 ps
T413 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1137863759 Jul 07 05:55:47 PM PDT 24 Jul 07 05:55:48 PM PDT 24 446471812 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1454459675 Jul 07 05:55:54 PM PDT 24 Jul 07 05:55:56 PM PDT 24 564995100 ps
T415 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3196245685 Jul 07 05:56:06 PM PDT 24 Jul 07 05:56:08 PM PDT 24 511232881 ps
T416 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3565014757 Jul 07 05:56:14 PM PDT 24 Jul 07 05:56:16 PM PDT 24 398536854 ps
T417 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3255829028 Jul 07 05:56:10 PM PDT 24 Jul 07 05:56:12 PM PDT 24 444862239 ps
T418 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.682655985 Jul 07 05:55:50 PM PDT 24 Jul 07 05:56:02 PM PDT 24 8483900482 ps
T419 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.60145987 Jul 07 05:56:20 PM PDT 24 Jul 07 05:56:21 PM PDT 24 291303282 ps
T420 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.83637750 Jul 07 05:56:18 PM PDT 24 Jul 07 05:56:19 PM PDT 24 495673948 ps
T421 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.218950403 Jul 07 05:55:45 PM PDT 24 Jul 07 05:55:47 PM PDT 24 569449208 ps
T422 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3576755694 Jul 07 05:55:46 PM PDT 24 Jul 07 05:55:48 PM PDT 24 433735036 ps
T423 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.134085233 Jul 07 05:55:43 PM PDT 24 Jul 07 05:55:51 PM PDT 24 4195989803 ps
T424 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1047176254 Jul 07 05:56:09 PM PDT 24 Jul 07 05:56:10 PM PDT 24 349327660 ps
T425 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1971063789 Jul 07 05:55:49 PM PDT 24 Jul 07 05:55:50 PM PDT 24 623807028 ps

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.908104264
Short name T1
Test name
Test status
Simulation time 131360952682 ps
CPU time 729.64 seconds
Started Jul 07 05:55:27 PM PDT 24
Finished Jul 07 06:07:37 PM PDT 24
Peak memory 214264 kb
Host smart-c9eea0bb-1188-4ab1-90ea-95b34309230e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908104264 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.908104264
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.774518514
Short name T40
Test name
Test status
Simulation time 96347664975 ps
CPU time 348.19 seconds
Started Jul 07 05:54:41 PM PDT 24
Finished Jul 07 06:00:29 PM PDT 24
Peak memory 206660 kb
Host smart-bbbd4278-913a-4936-a0ec-f246abb79916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774518514 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.774518514
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1068829855
Short name T36
Test name
Test status
Simulation time 8407333266 ps
CPU time 12.64 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:56:04 PM PDT 24
Peak memory 198184 kb
Host smart-0c0a5335-b92d-43fe-8b73-1e00d290fa6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068829855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1068829855
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2965657361
Short name T113
Test name
Test status
Simulation time 313550057946 ps
CPU time 406.66 seconds
Started Jul 07 05:55:35 PM PDT 24
Finished Jul 07 06:02:22 PM PDT 24
Peak memory 198308 kb
Host smart-efea9543-b4d1-4271-95af-3c2811fcac2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965657361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2965657361
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.13434725
Short name T50
Test name
Test status
Simulation time 91528680269 ps
CPU time 647.84 seconds
Started Jul 07 05:54:47 PM PDT 24
Finished Jul 07 06:05:36 PM PDT 24
Peak memory 206684 kb
Host smart-83c5bb31-6bec-4c8c-b494-712355057e59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13434725 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.13434725
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.488750332
Short name T110
Test name
Test status
Simulation time 372229351604 ps
CPU time 787.83 seconds
Started Jul 07 05:54:35 PM PDT 24
Finished Jul 07 06:07:43 PM PDT 24
Peak memory 215044 kb
Host smart-49b8270a-9157-41d7-a842-18b6f5fd52cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488750332 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.488750332
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.499396556
Short name T109
Test name
Test status
Simulation time 873281345989 ps
CPU time 614.91 seconds
Started Jul 07 05:55:27 PM PDT 24
Finished Jul 07 06:05:42 PM PDT 24
Peak memory 213948 kb
Host smart-2ff0c197-17b6-4384-857a-5cf16b40d307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499396556 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.499396556
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1419595744
Short name T133
Test name
Test status
Simulation time 366539626552 ps
CPU time 831.16 seconds
Started Jul 07 05:55:23 PM PDT 24
Finished Jul 07 06:09:15 PM PDT 24
Peak memory 207752 kb
Host smart-6e813322-b941-4c61-bf39-d460b4a2d694
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419595744 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1419595744
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.4217825575
Short name T156
Test name
Test status
Simulation time 255152295239 ps
CPU time 738.44 seconds
Started Jul 07 05:54:43 PM PDT 24
Finished Jul 07 06:07:02 PM PDT 24
Peak memory 214980 kb
Host smart-53e7906d-47ae-4574-8821-df2748464af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217825575 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.4217825575
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1589797142
Short name T14
Test name
Test status
Simulation time 40784178463 ps
CPU time 252.43 seconds
Started Jul 07 05:55:00 PM PDT 24
Finished Jul 07 05:59:12 PM PDT 24
Peak memory 213940 kb
Host smart-a34e8d43-83e4-4df2-900a-d001cd87d9e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589797142 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1589797142
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.4237215114
Short name T47
Test name
Test status
Simulation time 74417310928 ps
CPU time 485.37 seconds
Started Jul 07 05:55:36 PM PDT 24
Finished Jul 07 06:03:41 PM PDT 24
Peak memory 211160 kb
Host smart-f8f0cc9b-ff30-40b7-b8bb-0e3c8653efd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237215114 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.4237215114
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2651401391
Short name T20
Test name
Test status
Simulation time 4196194590 ps
CPU time 1.45 seconds
Started Jul 07 05:54:38 PM PDT 24
Finished Jul 07 05:54:40 PM PDT 24
Peak memory 215400 kb
Host smart-c5b05fab-c843-40be-8086-45e2d483a44f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651401391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2651401391
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.866054213
Short name T31
Test name
Test status
Simulation time 172147473163 ps
CPU time 386.49 seconds
Started Jul 07 05:55:23 PM PDT 24
Finished Jul 07 06:01:49 PM PDT 24
Peak memory 210888 kb
Host smart-500a22b0-fa8a-49ed-8bbf-0c2458ae8223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866054213 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.866054213
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1336204919
Short name T114
Test name
Test status
Simulation time 222533515472 ps
CPU time 93.75 seconds
Started Jul 07 05:54:39 PM PDT 24
Finished Jul 07 05:56:13 PM PDT 24
Peak memory 198164 kb
Host smart-c5991675-ffef-4ff8-915e-8e4735c2efa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336204919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1336204919
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.300516987
Short name T119
Test name
Test status
Simulation time 35868645056 ps
CPU time 289.69 seconds
Started Jul 07 05:55:05 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 214996 kb
Host smart-c26fd4a8-58f5-4d62-857c-a574c25ecef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300516987 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.300516987
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.28386137
Short name T80
Test name
Test status
Simulation time 46516554691 ps
CPU time 71.35 seconds
Started Jul 07 05:55:30 PM PDT 24
Finished Jul 07 05:56:41 PM PDT 24
Peak memory 193088 kb
Host smart-700e1773-31bf-41e6-8138-4237f9097647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28386137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_al
l.28386137
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2254358958
Short name T26
Test name
Test status
Simulation time 64363764749 ps
CPU time 247.98 seconds
Started Jul 07 05:55:03 PM PDT 24
Finished Jul 07 05:59:11 PM PDT 24
Peak memory 207644 kb
Host smart-7c5345d7-8b7a-4d7e-80a7-1465c67ed8fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254358958 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2254358958
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3516267118
Short name T9
Test name
Test status
Simulation time 166001695139 ps
CPU time 917.41 seconds
Started Jul 07 05:55:21 PM PDT 24
Finished Jul 07 06:10:39 PM PDT 24
Peak memory 215000 kb
Host smart-9ef012e4-830c-4047-a1df-a8298d568a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516267118 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3516267118
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3927248748
Short name T138
Test name
Test status
Simulation time 59882757800 ps
CPU time 79.49 seconds
Started Jul 07 05:55:07 PM PDT 24
Finished Jul 07 05:56:27 PM PDT 24
Peak memory 192976 kb
Host smart-e5aa5b4a-7e2c-41a1-a522-ecf8a485477c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927248748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3927248748
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1857997716
Short name T183
Test name
Test status
Simulation time 52814658704 ps
CPU time 340.13 seconds
Started Jul 07 05:55:34 PM PDT 24
Finished Jul 07 06:01:14 PM PDT 24
Peak memory 213996 kb
Host smart-a2195146-9355-4b2a-b733-3925ceede55c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857997716 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1857997716
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1222875703
Short name T125
Test name
Test status
Simulation time 79098842410 ps
CPU time 116.34 seconds
Started Jul 07 05:55:29 PM PDT 24
Finished Jul 07 05:57:26 PM PDT 24
Peak memory 192568 kb
Host smart-581be36f-b161-44ba-8723-7a591df9bfc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222875703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1222875703
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1014263906
Short name T120
Test name
Test status
Simulation time 173756062998 ps
CPU time 145.6 seconds
Started Jul 07 05:54:36 PM PDT 24
Finished Jul 07 05:57:02 PM PDT 24
Peak memory 198640 kb
Host smart-96d82f92-b18a-4c3c-be6e-e13de538c5d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014263906 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1014263906
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2738366797
Short name T92
Test name
Test status
Simulation time 183172467581 ps
CPU time 340.83 seconds
Started Jul 07 05:55:42 PM PDT 24
Finished Jul 07 06:01:23 PM PDT 24
Peak memory 201848 kb
Host smart-ce80e646-e9a5-47c2-b6bf-11b5a973729a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738366797 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2738366797
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.4246003307
Short name T115
Test name
Test status
Simulation time 260233229660 ps
CPU time 103.23 seconds
Started Jul 07 05:55:04 PM PDT 24
Finished Jul 07 05:56:48 PM PDT 24
Peak memory 193252 kb
Host smart-e9cf6ca0-346d-4850-a8b2-9875cbffced7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246003307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.4246003307
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1431385540
Short name T121
Test name
Test status
Simulation time 106104572586 ps
CPU time 30.44 seconds
Started Jul 07 05:55:25 PM PDT 24
Finished Jul 07 05:55:56 PM PDT 24
Peak memory 193020 kb
Host smart-851546c7-b90a-4923-8f38-a734e320c998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431385540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1431385540
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2601260251
Short name T105
Test name
Test status
Simulation time 88268363053 ps
CPU time 8.3 seconds
Started Jul 07 05:54:58 PM PDT 24
Finished Jul 07 05:55:06 PM PDT 24
Peak memory 191876 kb
Host smart-6ff07095-9741-40bb-8391-54ef08d95373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601260251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2601260251
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.833435630
Short name T122
Test name
Test status
Simulation time 344834641060 ps
CPU time 657.57 seconds
Started Jul 07 05:54:57 PM PDT 24
Finished Jul 07 06:05:54 PM PDT 24
Peak memory 214436 kb
Host smart-e37c9a6c-d9c5-4688-9c97-d485e68b75cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833435630 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.833435630
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3792138198
Short name T95
Test name
Test status
Simulation time 53659682887 ps
CPU time 198.38 seconds
Started Jul 07 05:54:49 PM PDT 24
Finished Jul 07 05:58:08 PM PDT 24
Peak memory 198656 kb
Host smart-a01c0a18-cffd-43bb-ad60-f7f21a22455d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792138198 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3792138198
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.721865953
Short name T53
Test name
Test status
Simulation time 537801191 ps
CPU time 0.66 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:55:52 PM PDT 24
Peak memory 193576 kb
Host smart-052294a4-18e1-4298-a61c-48684d9d6218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721865953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.721865953
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4169860969
Short name T108
Test name
Test status
Simulation time 94069342503 ps
CPU time 39.83 seconds
Started Jul 07 05:55:03 PM PDT 24
Finished Jul 07 05:55:43 PM PDT 24
Peak memory 198312 kb
Host smart-5158e8cc-d44d-4421-93e9-a26a3e2b9e5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169860969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4169860969
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.882810776
Short name T140
Test name
Test status
Simulation time 91939542518 ps
CPU time 984.67 seconds
Started Jul 07 05:55:11 PM PDT 24
Finished Jul 07 06:11:36 PM PDT 24
Peak memory 214984 kb
Host smart-4117b822-0bd0-4c76-b7c1-821a393f12dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882810776 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.882810776
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.958268881
Short name T175
Test name
Test status
Simulation time 181217322717 ps
CPU time 358.5 seconds
Started Jul 07 05:55:09 PM PDT 24
Finished Jul 07 06:01:07 PM PDT 24
Peak memory 206800 kb
Host smart-b2ec7dec-84f9-4fbf-9a99-4e754a8e6e86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958268881 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.958268881
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2316292242
Short name T118
Test name
Test status
Simulation time 240007081073 ps
CPU time 335.83 seconds
Started Jul 07 05:54:54 PM PDT 24
Finished Jul 07 06:00:30 PM PDT 24
Peak memory 198324 kb
Host smart-bc34fedc-e3cd-4005-9c8d-de5b8278059a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316292242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2316292242
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2683067299
Short name T79
Test name
Test status
Simulation time 97742766012 ps
CPU time 139.8 seconds
Started Jul 07 05:54:40 PM PDT 24
Finished Jul 07 05:57:00 PM PDT 24
Peak memory 198592 kb
Host smart-a1a74f90-f074-414e-a4e8-00b0f43c1bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683067299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2683067299
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1777591166
Short name T147
Test name
Test status
Simulation time 43952349895 ps
CPU time 68.14 seconds
Started Jul 07 05:55:44 PM PDT 24
Finished Jul 07 05:56:52 PM PDT 24
Peak memory 193080 kb
Host smart-df92e376-c8ed-4c97-98df-add44abc6a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777591166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1777591166
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1867055081
Short name T49
Test name
Test status
Simulation time 137136496098 ps
CPU time 368 seconds
Started Jul 07 05:54:57 PM PDT 24
Finished Jul 07 06:01:06 PM PDT 24
Peak memory 210956 kb
Host smart-dcca66b3-e500-4608-a872-a0da319eec85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867055081 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1867055081
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1820571732
Short name T169
Test name
Test status
Simulation time 64579063169 ps
CPU time 528.24 seconds
Started Jul 07 05:55:17 PM PDT 24
Finished Jul 07 06:04:06 PM PDT 24
Peak memory 202644 kb
Host smart-31109181-3f21-4583-884e-b7fc37161c39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820571732 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1820571732
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.602707080
Short name T32
Test name
Test status
Simulation time 62955465081 ps
CPU time 254.87 seconds
Started Jul 07 05:55:32 PM PDT 24
Finished Jul 07 05:59:47 PM PDT 24
Peak memory 207308 kb
Host smart-9eb04392-1f08-4ca1-980f-311cc49989a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602707080 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.602707080
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1951837426
Short name T135
Test name
Test status
Simulation time 76113508472 ps
CPU time 33.84 seconds
Started Jul 07 05:55:46 PM PDT 24
Finished Jul 07 05:56:20 PM PDT 24
Peak memory 184256 kb
Host smart-cbf14402-5751-443b-8d1a-b65bdbfb68b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951837426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1951837426
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3853980195
Short name T75
Test name
Test status
Simulation time 189185400442 ps
CPU time 65.23 seconds
Started Jul 07 05:54:45 PM PDT 24
Finished Jul 07 05:55:51 PM PDT 24
Peak memory 198312 kb
Host smart-0ee82c94-4bf0-4efd-a2d7-4fa424790cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853980195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3853980195
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2149500053
Short name T152
Test name
Test status
Simulation time 57179297950 ps
CPU time 23.34 seconds
Started Jul 07 05:54:54 PM PDT 24
Finished Jul 07 05:55:17 PM PDT 24
Peak memory 198148 kb
Host smart-6abe0357-10a7-4b97-91e9-6c8b249b7e5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149500053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2149500053
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1046177476
Short name T43
Test name
Test status
Simulation time 23175021360 ps
CPU time 237.01 seconds
Started Jul 07 05:55:01 PM PDT 24
Finished Jul 07 05:58:58 PM PDT 24
Peak memory 206780 kb
Host smart-043984e2-0c28-4999-a732-f175b4250956
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046177476 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1046177476
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2291951429
Short name T142
Test name
Test status
Simulation time 46335694187 ps
CPU time 19.75 seconds
Started Jul 07 05:54:51 PM PDT 24
Finished Jul 07 05:55:11 PM PDT 24
Peak memory 184240 kb
Host smart-2f681bca-09d7-4c17-ab49-e4d238c406fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291951429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2291951429
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1055109525
Short name T132
Test name
Test status
Simulation time 22215911011 ps
CPU time 184.13 seconds
Started Jul 07 05:54:55 PM PDT 24
Finished Jul 07 05:58:01 PM PDT 24
Peak memory 206788 kb
Host smart-ffe84d2e-85c4-4ba1-862c-3b5cbfa47579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055109525 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1055109525
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2963393543
Short name T139
Test name
Test status
Simulation time 151034968686 ps
CPU time 1175.29 seconds
Started Jul 07 05:55:19 PM PDT 24
Finished Jul 07 06:14:55 PM PDT 24
Peak memory 215008 kb
Host smart-a054fd9f-0c0b-4fa6-bf4e-7d112674c62a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963393543 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2963393543
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4251196350
Short name T112
Test name
Test status
Simulation time 133498668465 ps
CPU time 127.06 seconds
Started Jul 07 05:55:32 PM PDT 24
Finished Jul 07 05:57:39 PM PDT 24
Peak memory 192988 kb
Host smart-d235a7cd-769c-4a53-9e87-9f73d91c5b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251196350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4251196350
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3959043289
Short name T171
Test name
Test status
Simulation time 369671462283 ps
CPU time 399.16 seconds
Started Jul 07 05:54:45 PM PDT 24
Finished Jul 07 06:01:25 PM PDT 24
Peak memory 210540 kb
Host smart-e6a6ff3c-fcd0-4415-8c76-122db5669330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959043289 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3959043289
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.382889048
Short name T96
Test name
Test status
Simulation time 392838768555 ps
CPU time 245.93 seconds
Started Jul 07 05:55:01 PM PDT 24
Finished Jul 07 05:59:07 PM PDT 24
Peak memory 214220 kb
Host smart-7148d32a-6e63-4464-9532-2b2f6134eae4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382889048 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.382889048
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.184691056
Short name T131
Test name
Test status
Simulation time 32045208135 ps
CPU time 175.03 seconds
Started Jul 07 05:55:03 PM PDT 24
Finished Jul 07 05:57:59 PM PDT 24
Peak memory 198644 kb
Host smart-f58cc47a-4c9c-4b27-ac0e-e913149e0bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184691056 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.184691056
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3646077307
Short name T128
Test name
Test status
Simulation time 324033927528 ps
CPU time 298.58 seconds
Started Jul 07 05:55:34 PM PDT 24
Finished Jul 07 06:00:33 PM PDT 24
Peak memory 191872 kb
Host smart-01db0e54-9d6a-45d9-925a-7021dde93030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646077307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3646077307
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2216187246
Short name T167
Test name
Test status
Simulation time 180402927310 ps
CPU time 278.11 seconds
Started Jul 07 05:54:52 PM PDT 24
Finished Jul 07 05:59:31 PM PDT 24
Peak memory 209276 kb
Host smart-0bfa2fde-7d3b-49e6-aed6-e1729e6afb14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216187246 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2216187246
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3555196898
Short name T126
Test name
Test status
Simulation time 348702032895 ps
CPU time 121.67 seconds
Started Jul 07 05:55:10 PM PDT 24
Finished Jul 07 05:57:12 PM PDT 24
Peak memory 198308 kb
Host smart-9a66c1d0-7c31-49db-b2c3-54824dd461dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555196898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3555196898
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2993073145
Short name T124
Test name
Test status
Simulation time 57380396143 ps
CPU time 17.67 seconds
Started Jul 07 05:55:28 PM PDT 24
Finished Jul 07 05:55:46 PM PDT 24
Peak memory 191980 kb
Host smart-91637ee0-4d86-4f58-9051-700f969c3614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993073145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2993073145
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3815823205
Short name T107
Test name
Test status
Simulation time 3613665397 ps
CPU time 2.55 seconds
Started Jul 07 05:55:22 PM PDT 24
Finished Jul 07 05:55:24 PM PDT 24
Peak memory 184232 kb
Host smart-a7db117e-f6ae-4737-ab77-0d0b98170363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815823205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3815823205
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2393972191
Short name T163
Test name
Test status
Simulation time 154712679591 ps
CPU time 38.88 seconds
Started Jul 07 05:55:35 PM PDT 24
Finished Jul 07 05:56:14 PM PDT 24
Peak memory 193064 kb
Host smart-b4dfb711-0611-4f70-8884-fc30938e1bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393972191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2393972191
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.858510092
Short name T164
Test name
Test status
Simulation time 124936223292 ps
CPU time 30.62 seconds
Started Jul 07 05:55:00 PM PDT 24
Finished Jul 07 05:55:30 PM PDT 24
Peak memory 197864 kb
Host smart-e38e3331-aa73-437b-9041-7e9168b686fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858510092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.858510092
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.42633693
Short name T99
Test name
Test status
Simulation time 201734899065 ps
CPU time 141.7 seconds
Started Jul 07 05:54:55 PM PDT 24
Finished Jul 07 05:57:18 PM PDT 24
Peak memory 192964 kb
Host smart-d966c2dc-cee9-4829-b2da-91356822e5e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42633693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_al
l.42633693
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.892194655
Short name T106
Test name
Test status
Simulation time 123106294175 ps
CPU time 181.13 seconds
Started Jul 07 05:55:18 PM PDT 24
Finished Jul 07 05:58:19 PM PDT 24
Peak memory 192588 kb
Host smart-89684ef4-8e8f-46a3-8d3f-1b80ca51e461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892194655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.892194655
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.811808320
Short name T66
Test name
Test status
Simulation time 111852649383 ps
CPU time 167.71 seconds
Started Jul 07 05:54:37 PM PDT 24
Finished Jul 07 05:57:25 PM PDT 24
Peak memory 192984 kb
Host smart-58a03798-7ffb-4253-aa1a-54c706def6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811808320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.811808320
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2761345052
Short name T158
Test name
Test status
Simulation time 7200335848 ps
CPU time 3.32 seconds
Started Jul 07 05:55:11 PM PDT 24
Finished Jul 07 05:55:14 PM PDT 24
Peak memory 198260 kb
Host smart-6156802b-242d-49c9-90fa-3a7b467af262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761345052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2761345052
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3240736084
Short name T111
Test name
Test status
Simulation time 28674672220 ps
CPU time 117.69 seconds
Started Jul 07 05:55:18 PM PDT 24
Finished Jul 07 05:57:16 PM PDT 24
Peak memory 213924 kb
Host smart-317ffe53-3e9f-4348-ae1c-602023328de1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240736084 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3240736084
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3088716161
Short name T7
Test name
Test status
Simulation time 469623566812 ps
CPU time 1034.04 seconds
Started Jul 07 05:54:38 PM PDT 24
Finished Jul 07 06:11:52 PM PDT 24
Peak memory 214964 kb
Host smart-3b2b8522-6418-4cdb-9612-c8c03ff1c740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088716161 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3088716161
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.217437655
Short name T141
Test name
Test status
Simulation time 106848824260 ps
CPU time 33.76 seconds
Started Jul 07 05:54:42 PM PDT 24
Finished Jul 07 05:55:16 PM PDT 24
Peak memory 191944 kb
Host smart-85225efe-c13c-4640-89df-171b0aa10a56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217437655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.217437655
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1553231152
Short name T68
Test name
Test status
Simulation time 499280259 ps
CPU time 0.79 seconds
Started Jul 07 05:54:35 PM PDT 24
Finished Jul 07 05:54:36 PM PDT 24
Peak memory 196728 kb
Host smart-9270847d-2514-42bc-bef4-152be888b886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553231152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1553231152
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1075821790
Short name T91
Test name
Test status
Simulation time 68488617613 ps
CPU time 345.03 seconds
Started Jul 07 05:54:52 PM PDT 24
Finished Jul 07 06:00:38 PM PDT 24
Peak memory 206824 kb
Host smart-4b4b3ff3-316a-4a70-801f-23b8605f152b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075821790 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1075821790
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3123672442
Short name T117
Test name
Test status
Simulation time 356479362 ps
CPU time 0.76 seconds
Started Jul 07 05:55:16 PM PDT 24
Finished Jul 07 05:55:18 PM PDT 24
Peak memory 197032 kb
Host smart-d791c48a-2c0c-467c-bb8e-7c7bf31e2772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123672442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3123672442
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2853072167
Short name T157
Test name
Test status
Simulation time 129647758705 ps
CPU time 47.81 seconds
Started Jul 07 05:55:09 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 193080 kb
Host smart-e6d453d0-d430-45d2-96fd-80dfc748f599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853072167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2853072167
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2261768633
Short name T159
Test name
Test status
Simulation time 149976943213 ps
CPU time 219.81 seconds
Started Jul 07 05:54:42 PM PDT 24
Finished Jul 07 05:58:22 PM PDT 24
Peak memory 191964 kb
Host smart-9da828e0-a619-4094-b20d-616093579194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261768633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2261768633
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.707422393
Short name T94
Test name
Test status
Simulation time 170141945902 ps
CPU time 623.35 seconds
Started Jul 07 05:55:17 PM PDT 24
Finished Jul 07 06:05:41 PM PDT 24
Peak memory 206820 kb
Host smart-c3287a37-b011-4956-991c-81f2423c25a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707422393 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.707422393
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3753781749
Short name T24
Test name
Test status
Simulation time 249670531662 ps
CPU time 132.84 seconds
Started Jul 07 05:55:30 PM PDT 24
Finished Jul 07 05:57:43 PM PDT 24
Peak memory 198328 kb
Host smart-63fbaa2e-d7d3-4d69-874a-84b7b276f027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753781749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3753781749
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3800060739
Short name T18
Test name
Test status
Simulation time 242504888751 ps
CPU time 82.87 seconds
Started Jul 07 05:54:48 PM PDT 24
Finished Jul 07 05:56:12 PM PDT 24
Peak memory 198240 kb
Host smart-c2204269-fcea-49bf-abdb-78660913611c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800060739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3800060739
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.4290406469
Short name T129
Test name
Test status
Simulation time 499061990 ps
CPU time 0.96 seconds
Started Jul 07 05:54:50 PM PDT 24
Finished Jul 07 05:54:51 PM PDT 24
Peak memory 196780 kb
Host smart-12cf20e4-62c8-4863-a491-ef48bd703514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290406469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4290406469
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.297022528
Short name T123
Test name
Test status
Simulation time 18577772850 ps
CPU time 3.2 seconds
Started Jul 07 05:54:52 PM PDT 24
Finished Jul 07 05:54:55 PM PDT 24
Peak memory 191964 kb
Host smart-4ebb7b99-3d3f-4bf8-8f39-4555f670e305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297022528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.297022528
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1648507213
Short name T74
Test name
Test status
Simulation time 217780653854 ps
CPU time 349.58 seconds
Started Jul 07 05:55:09 PM PDT 24
Finished Jul 07 06:00:59 PM PDT 24
Peak memory 208860 kb
Host smart-d715251c-0f18-4f39-850b-4027f90c5d88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648507213 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1648507213
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4242899594
Short name T153
Test name
Test status
Simulation time 393695351 ps
CPU time 0.71 seconds
Started Jul 07 05:55:16 PM PDT 24
Finished Jul 07 05:55:17 PM PDT 24
Peak memory 196712 kb
Host smart-adcbe4b8-aa01-4671-97d1-2255d007dcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242899594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4242899594
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4127747904
Short name T104
Test name
Test status
Simulation time 359071331 ps
CPU time 0.81 seconds
Started Jul 07 05:55:20 PM PDT 24
Finished Jul 07 05:55:21 PM PDT 24
Peak memory 196796 kb
Host smart-8ea63fbe-fe88-4214-89f8-42852af3d0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127747904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4127747904
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1679270763
Short name T136
Test name
Test status
Simulation time 609818186 ps
CPU time 0.75 seconds
Started Jul 07 05:55:26 PM PDT 24
Finished Jul 07 05:55:27 PM PDT 24
Peak memory 196708 kb
Host smart-9979fcb3-7375-42ba-a4b2-6f9ea61ae3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679270763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1679270763
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3099019897
Short name T154
Test name
Test status
Simulation time 413901285 ps
CPU time 1.19 seconds
Started Jul 07 05:54:52 PM PDT 24
Finished Jul 07 05:54:53 PM PDT 24
Peak memory 196672 kb
Host smart-cb970f93-1680-44f7-b4cf-73978cdedae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099019897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3099019897
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2706374792
Short name T69
Test name
Test status
Simulation time 177922078063 ps
CPU time 69.23 seconds
Started Jul 07 05:55:10 PM PDT 24
Finished Jul 07 05:56:19 PM PDT 24
Peak memory 192980 kb
Host smart-b3f32db6-22e7-46f6-8bc9-836383c8de65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706374792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2706374792
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3368595666
Short name T46
Test name
Test status
Simulation time 528581779 ps
CPU time 1.47 seconds
Started Jul 07 05:55:10 PM PDT 24
Finished Jul 07 05:55:12 PM PDT 24
Peak memory 196740 kb
Host smart-eca9344d-fb04-4767-becd-d8710761b1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368595666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3368595666
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1651103942
Short name T168
Test name
Test status
Simulation time 179170040019 ps
CPU time 142.09 seconds
Started Jul 07 05:55:17 PM PDT 24
Finished Jul 07 05:57:40 PM PDT 24
Peak memory 198336 kb
Host smart-48d1bc0d-b0b5-4f07-9834-5db77b22fdb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651103942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1651103942
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3471144224
Short name T12
Test name
Test status
Simulation time 19069766721 ps
CPU time 30.66 seconds
Started Jul 07 05:55:19 PM PDT 24
Finished Jul 07 05:55:50 PM PDT 24
Peak memory 198352 kb
Host smart-3b7507e3-474e-4e19-b9e5-33b76425dbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471144224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3471144224
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3942165744
Short name T25
Test name
Test status
Simulation time 143663320232 ps
CPU time 315.93 seconds
Started Jul 07 05:55:16 PM PDT 24
Finished Jul 07 06:00:33 PM PDT 24
Peak memory 206808 kb
Host smart-0a6ba5fd-1af1-4650-990a-4e4f7967ba8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942165744 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3942165744
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.971684766
Short name T102
Test name
Test status
Simulation time 560524876 ps
CPU time 0.93 seconds
Started Jul 07 05:55:19 PM PDT 24
Finished Jul 07 05:55:20 PM PDT 24
Peak memory 196752 kb
Host smart-afd59e8d-1c1f-4145-a34d-bdaf2aeea699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971684766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.971684766
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1671408173
Short name T127
Test name
Test status
Simulation time 383502826 ps
CPU time 0.85 seconds
Started Jul 07 05:55:23 PM PDT 24
Finished Jul 07 05:55:24 PM PDT 24
Peak memory 196716 kb
Host smart-28904831-7bd0-44a0-8c99-55488a991687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671408173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1671408173
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1722635478
Short name T151
Test name
Test status
Simulation time 389300982 ps
CPU time 0.66 seconds
Started Jul 07 05:55:22 PM PDT 24
Finished Jul 07 05:55:23 PM PDT 24
Peak memory 196796 kb
Host smart-f33ba206-4e9c-45d4-8db8-e718aecdf621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722635478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1722635478
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2912615661
Short name T149
Test name
Test status
Simulation time 586876605 ps
CPU time 1.42 seconds
Started Jul 07 05:55:29 PM PDT 24
Finished Jul 07 05:55:31 PM PDT 24
Peak memory 196784 kb
Host smart-463db3ab-4c7a-4d44-a024-6bdad9e2f9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912615661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2912615661
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2112289094
Short name T65
Test name
Test status
Simulation time 461905798 ps
CPU time 1.34 seconds
Started Jul 07 05:55:43 PM PDT 24
Finished Jul 07 05:55:45 PM PDT 24
Peak memory 196728 kb
Host smart-0ccf0f95-44f9-4c67-912a-331b4bb1921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112289094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2112289094
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3364380101
Short name T116
Test name
Test status
Simulation time 538019062 ps
CPU time 0.79 seconds
Started Jul 07 05:55:45 PM PDT 24
Finished Jul 07 05:55:46 PM PDT 24
Peak memory 196692 kb
Host smart-34801e50-027e-4185-8042-658fa590ba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364380101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3364380101
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.4078721012
Short name T8
Test name
Test status
Simulation time 596233699 ps
CPU time 1.36 seconds
Started Jul 07 05:54:41 PM PDT 24
Finished Jul 07 05:54:42 PM PDT 24
Peak memory 196720 kb
Host smart-8d95bb77-36aa-448f-8f3e-5741bfb6c3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078721012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.4078721012
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.577092510
Short name T134
Test name
Test status
Simulation time 461757460 ps
CPU time 0.79 seconds
Started Jul 07 05:54:41 PM PDT 24
Finished Jul 07 05:54:42 PM PDT 24
Peak memory 196804 kb
Host smart-d84dafe2-1eb7-4f2a-9a01-e64436e094eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577092510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.577092510
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1029684942
Short name T137
Test name
Test status
Simulation time 433680845 ps
CPU time 0.76 seconds
Started Jul 07 05:54:52 PM PDT 24
Finished Jul 07 05:54:53 PM PDT 24
Peak memory 196640 kb
Host smart-a1d48c31-e56d-4f48-9bf4-b572202222eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029684942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1029684942
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1580175302
Short name T191
Test name
Test status
Simulation time 59605509860 ps
CPU time 12.32 seconds
Started Jul 07 05:54:59 PM PDT 24
Finished Jul 07 05:55:11 PM PDT 24
Peak memory 191964 kb
Host smart-676da3b2-ae8f-4071-9c28-d32338419dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580175302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1580175302
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.124198483
Short name T162
Test name
Test status
Simulation time 460572885 ps
CPU time 0.66 seconds
Started Jul 07 05:54:36 PM PDT 24
Finished Jul 07 05:54:37 PM PDT 24
Peak memory 196708 kb
Host smart-3c954189-983f-4d37-86b0-ba32d3ab66e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124198483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.124198483
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2698560781
Short name T144
Test name
Test status
Simulation time 376035658 ps
CPU time 0.74 seconds
Started Jul 07 05:54:58 PM PDT 24
Finished Jul 07 05:54:59 PM PDT 24
Peak memory 196708 kb
Host smart-5afb83a8-89e7-48f3-a50f-70964ac0d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698560781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2698560781
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.993925146
Short name T143
Test name
Test status
Simulation time 455097909 ps
CPU time 0.92 seconds
Started Jul 07 05:55:13 PM PDT 24
Finished Jul 07 05:55:14 PM PDT 24
Peak memory 196780 kb
Host smart-1aadcb66-4da2-4b75-bce5-76b5978c2a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993925146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.993925146
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1793537089
Short name T39
Test name
Test status
Simulation time 425692225946 ps
CPU time 212.01 seconds
Started Jul 07 05:55:21 PM PDT 24
Finished Jul 07 05:58:53 PM PDT 24
Peak memory 206832 kb
Host smart-54f64ba1-d13c-46b6-ac6d-a0e2532a4b2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793537089 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1793537089
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.728035134
Short name T42
Test name
Test status
Simulation time 448067163546 ps
CPU time 339.58 seconds
Started Jul 07 05:55:22 PM PDT 24
Finished Jul 07 06:01:02 PM PDT 24
Peak memory 198284 kb
Host smart-ef0248f3-29ca-4ad7-92d1-9ab24b258f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728035134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.728035134
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2012711520
Short name T160
Test name
Test status
Simulation time 472157016 ps
CPU time 0.84 seconds
Started Jul 07 05:55:31 PM PDT 24
Finished Jul 07 05:55:32 PM PDT 24
Peak memory 196644 kb
Host smart-009a6793-c12d-46b7-a82f-ae130d9377ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012711520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2012711520
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.417355379
Short name T103
Test name
Test status
Simulation time 481813511 ps
CPU time 0.78 seconds
Started Jul 07 05:54:55 PM PDT 24
Finished Jul 07 05:54:56 PM PDT 24
Peak memory 196748 kb
Host smart-725222b6-e9ce-44f7-b602-708149859f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417355379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.417355379
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3245417717
Short name T165
Test name
Test status
Simulation time 14399020913 ps
CPU time 76.69 seconds
Started Jul 07 05:54:56 PM PDT 24
Finished Jul 07 05:56:13 PM PDT 24
Peak memory 206788 kb
Host smart-8eb2bee3-8f70-41ad-82ff-97267872f9a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245417717 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3245417717
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.299560927
Short name T70
Test name
Test status
Simulation time 582264890 ps
CPU time 1.35 seconds
Started Jul 07 05:55:15 PM PDT 24
Finished Jul 07 05:55:17 PM PDT 24
Peak memory 196716 kb
Host smart-e318d716-9e54-406b-a6b7-0b52fe244d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299560927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.299560927
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2713283764
Short name T173
Test name
Test status
Simulation time 389862455434 ps
CPU time 133.82 seconds
Started Jul 07 05:55:12 PM PDT 24
Finished Jul 07 05:57:26 PM PDT 24
Peak memory 193060 kb
Host smart-1c7d0893-15a3-49b1-a6a8-d51ff3aabb4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713283764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2713283764
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1502287626
Short name T180
Test name
Test status
Simulation time 25374760552 ps
CPU time 132 seconds
Started Jul 07 05:55:38 PM PDT 24
Finished Jul 07 05:57:51 PM PDT 24
Peak memory 206796 kb
Host smart-01f1fca1-31c5-4a54-bbb5-a14fb4ec3ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502287626 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1502287626
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1399590000
Short name T146
Test name
Test status
Simulation time 16729974199 ps
CPU time 124.8 seconds
Started Jul 07 05:55:42 PM PDT 24
Finished Jul 07 05:57:47 PM PDT 24
Peak memory 207080 kb
Host smart-226eb6d4-ad2d-4c7b-8e53-0517cb291f60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399590000 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1399590000
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2940678337
Short name T148
Test name
Test status
Simulation time 59852754376 ps
CPU time 124.5 seconds
Started Jul 07 05:54:42 PM PDT 24
Finished Jul 07 05:56:47 PM PDT 24
Peak memory 206832 kb
Host smart-1bd38ebf-799a-436e-a7ab-89c02708e2a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940678337 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2940678337
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1417438042
Short name T200
Test name
Test status
Simulation time 14925736959 ps
CPU time 110.05 seconds
Started Jul 07 05:54:52 PM PDT 24
Finished Jul 07 05:56:42 PM PDT 24
Peak memory 206792 kb
Host smart-0a277484-deda-47a3-bdf2-054fa6f9a633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417438042 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1417438042
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2035605153
Short name T130
Test name
Test status
Simulation time 365830214 ps
CPU time 1.03 seconds
Started Jul 07 05:55:04 PM PDT 24
Finished Jul 07 05:55:05 PM PDT 24
Peak memory 196692 kb
Host smart-0fde747c-945c-4eef-99fd-84458816f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035605153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2035605153
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2462765723
Short name T188
Test name
Test status
Simulation time 494573850 ps
CPU time 1.32 seconds
Started Jul 07 05:55:03 PM PDT 24
Finished Jul 07 05:55:05 PM PDT 24
Peak memory 196680 kb
Host smart-cbd021b9-0c61-4f80-9aee-b9faa6927fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462765723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2462765723
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.2117417626
Short name T166
Test name
Test status
Simulation time 58407249960 ps
CPU time 72.9 seconds
Started Jul 07 05:55:09 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 192076 kb
Host smart-8822411e-fbf8-4e47-bbab-0ebcee0b177e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117417626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.2117417626
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2626817588
Short name T172
Test name
Test status
Simulation time 401631883 ps
CPU time 0.86 seconds
Started Jul 07 05:54:39 PM PDT 24
Finished Jul 07 05:54:40 PM PDT 24
Peak memory 196688 kb
Host smart-eab372a2-5164-4fde-b15b-b3078b06f02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626817588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2626817588
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1568864428
Short name T198
Test name
Test status
Simulation time 149379806331 ps
CPU time 23.51 seconds
Started Jul 07 05:55:33 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 193568 kb
Host smart-7cd36f4d-6ab8-4540-97b7-04b44288e701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568864428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1568864428
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1691032991
Short name T48
Test name
Test status
Simulation time 65080721281 ps
CPU time 334.96 seconds
Started Jul 07 05:55:46 PM PDT 24
Finished Jul 07 06:01:21 PM PDT 24
Peak memory 206816 kb
Host smart-62a536fb-1008-4007-8faf-f30a15b88490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691032991 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1691032991
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.169992027
Short name T19
Test name
Test status
Simulation time 91021339651 ps
CPU time 22.21 seconds
Started Jul 07 05:54:45 PM PDT 24
Finished Jul 07 05:55:08 PM PDT 24
Peak memory 198336 kb
Host smart-9b268ea4-ae6c-4c25-9b8b-77ff29a1354d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169992027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.169992027
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.385975274
Short name T203
Test name
Test status
Simulation time 8314248151 ps
CPU time 3 seconds
Started Jul 07 05:56:00 PM PDT 24
Finished Jul 07 05:56:03 PM PDT 24
Peak memory 198420 kb
Host smart-ad1a5ac8-3fb9-43bf-a0a4-67aed7373cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385975274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.385975274
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3689997231
Short name T179
Test name
Test status
Simulation time 403857237207 ps
CPU time 286.42 seconds
Started Jul 07 05:54:47 PM PDT 24
Finished Jul 07 05:59:33 PM PDT 24
Peak memory 184240 kb
Host smart-1108041e-65be-4fb1-91dc-4dffdae9081e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689997231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3689997231
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3144752770
Short name T11
Test name
Test status
Simulation time 513003004 ps
CPU time 0.92 seconds
Started Jul 07 05:54:53 PM PDT 24
Finished Jul 07 05:54:54 PM PDT 24
Peak memory 196808 kb
Host smart-09433ad5-1579-4b08-a033-939b6300ac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144752770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3144752770
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1415120645
Short name T196
Test name
Test status
Simulation time 620645243 ps
CPU time 0.78 seconds
Started Jul 07 05:54:55 PM PDT 24
Finished Jul 07 05:54:57 PM PDT 24
Peak memory 196668 kb
Host smart-02714856-4455-4b80-a247-958473bb3021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415120645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1415120645
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1760864484
Short name T178
Test name
Test status
Simulation time 101304061975 ps
CPU time 140.19 seconds
Started Jul 07 05:54:39 PM PDT 24
Finished Jul 07 05:57:00 PM PDT 24
Peak memory 191964 kb
Host smart-d988defd-e964-40d5-90e0-c4b9bbe0a794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760864484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1760864484
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1749411649
Short name T192
Test name
Test status
Simulation time 526028520 ps
CPU time 0.8 seconds
Started Jul 07 05:55:00 PM PDT 24
Finished Jul 07 05:55:02 PM PDT 24
Peak memory 196720 kb
Host smart-a76bc71b-8666-4b8c-a45c-9dc3ae57c52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749411649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1749411649
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2511732926
Short name T176
Test name
Test status
Simulation time 214892551860 ps
CPU time 77.86 seconds
Started Jul 07 05:54:57 PM PDT 24
Finished Jul 07 05:56:15 PM PDT 24
Peak memory 198308 kb
Host smart-641b8d99-4adc-4328-9a91-a8a50c860cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511732926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2511732926
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.142050106
Short name T182
Test name
Test status
Simulation time 529330307 ps
CPU time 0.76 seconds
Started Jul 07 05:55:09 PM PDT 24
Finished Jul 07 05:55:10 PM PDT 24
Peak memory 196652 kb
Host smart-96400f39-31a4-49fc-8c5e-67120a2f036c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142050106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.142050106
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2329567435
Short name T186
Test name
Test status
Simulation time 459815666 ps
CPU time 0.7 seconds
Started Jul 07 05:55:23 PM PDT 24
Finished Jul 07 05:55:24 PM PDT 24
Peak memory 196668 kb
Host smart-29dd460b-cc17-40a1-bb97-0e4dd6557b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329567435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2329567435
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2420555213
Short name T51
Test name
Test status
Simulation time 10729074695 ps
CPU time 104 seconds
Started Jul 07 05:55:26 PM PDT 24
Finished Jul 07 05:57:10 PM PDT 24
Peak memory 215048 kb
Host smart-071d17a2-8e37-45ca-b872-f345eeaea161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420555213 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2420555213
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.654269800
Short name T177
Test name
Test status
Simulation time 500183028 ps
CPU time 0.98 seconds
Started Jul 07 05:55:22 PM PDT 24
Finished Jul 07 05:55:23 PM PDT 24
Peak memory 196656 kb
Host smart-57be7bd0-9ca2-48d4-84ad-c04ce0247076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654269800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.654269800
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.283153975
Short name T199
Test name
Test status
Simulation time 622402084 ps
CPU time 0.72 seconds
Started Jul 07 05:55:35 PM PDT 24
Finished Jul 07 05:55:36 PM PDT 24
Peak memory 196724 kb
Host smart-6b0a4f2f-9f63-469b-ae43-d5bf93385c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283153975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.283153975
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2972385089
Short name T161
Test name
Test status
Simulation time 485010096 ps
CPU time 0.78 seconds
Started Jul 07 05:55:33 PM PDT 24
Finished Jul 07 05:55:34 PM PDT 24
Peak memory 196844 kb
Host smart-029115e5-26e4-47bc-8a97-cc122808772c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972385089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2972385089
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3828395612
Short name T145
Test name
Test status
Simulation time 367144013 ps
CPU time 0.83 seconds
Started Jul 07 05:54:43 PM PDT 24
Finished Jul 07 05:54:44 PM PDT 24
Peak memory 196692 kb
Host smart-db523b2d-a2c9-4b35-b715-ac0f2c1ba4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828395612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3828395612
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2577155778
Short name T6
Test name
Test status
Simulation time 574042568 ps
CPU time 0.85 seconds
Started Jul 07 05:54:48 PM PDT 24
Finished Jul 07 05:54:49 PM PDT 24
Peak memory 196636 kb
Host smart-de7ec1d9-4193-4208-aa2d-7a240b7a0b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577155778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2577155778
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2993873675
Short name T174
Test name
Test status
Simulation time 586302883 ps
CPU time 0.7 seconds
Started Jul 07 05:54:51 PM PDT 24
Finished Jul 07 05:54:52 PM PDT 24
Peak memory 196732 kb
Host smart-578b151f-cc7a-4862-b9ae-3ce7093f3b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993873675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2993873675
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4257283705
Short name T181
Test name
Test status
Simulation time 558587485 ps
CPU time 1.53 seconds
Started Jul 07 05:55:00 PM PDT 24
Finished Jul 07 05:55:01 PM PDT 24
Peak memory 196160 kb
Host smart-bed3672e-bc4d-4f5d-a6b5-d5269791c5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257283705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4257283705
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2964722500
Short name T187
Test name
Test status
Simulation time 605917174 ps
CPU time 1.32 seconds
Started Jul 07 05:55:00 PM PDT 24
Finished Jul 07 05:55:01 PM PDT 24
Peak memory 196640 kb
Host smart-78f1446a-37cf-4580-bd37-3856447fc404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964722500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2964722500
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3514888588
Short name T195
Test name
Test status
Simulation time 420965048 ps
CPU time 0.7 seconds
Started Jul 07 05:55:14 PM PDT 24
Finished Jul 07 05:55:15 PM PDT 24
Peak memory 196732 kb
Host smart-87970b8f-6f70-4ff0-b416-66a5eec0c24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514888588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3514888588
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.766749215
Short name T155
Test name
Test status
Simulation time 382860538 ps
CPU time 0.9 seconds
Started Jul 07 05:55:18 PM PDT 24
Finished Jul 07 05:55:19 PM PDT 24
Peak memory 196720 kb
Host smart-2cede931-d23f-4d51-868b-c6519dccd184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766749215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.766749215
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1530694993
Short name T197
Test name
Test status
Simulation time 56687609402 ps
CPU time 4.95 seconds
Started Jul 07 05:55:22 PM PDT 24
Finished Jul 07 05:55:28 PM PDT 24
Peak memory 184096 kb
Host smart-7f6163f8-a6d9-4ab7-941a-40fb6bc2a9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530694993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1530694993
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2262154643
Short name T41
Test name
Test status
Simulation time 497820372 ps
CPU time 0.77 seconds
Started Jul 07 05:54:38 PM PDT 24
Finished Jul 07 05:54:39 PM PDT 24
Peak memory 197060 kb
Host smart-59e7299c-45d8-4180-a1be-d19fee424c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262154643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2262154643
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1540040227
Short name T184
Test name
Test status
Simulation time 373216128 ps
CPU time 0.73 seconds
Started Jul 07 05:55:35 PM PDT 24
Finished Jul 07 05:55:36 PM PDT 24
Peak memory 196748 kb
Host smart-ec0a8ff4-c90c-4ba2-9773-6f687b274785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540040227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1540040227
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.4054994079
Short name T185
Test name
Test status
Simulation time 664871049 ps
CPU time 0.71 seconds
Started Jul 07 05:54:47 PM PDT 24
Finished Jul 07 05:54:48 PM PDT 24
Peak memory 196808 kb
Host smart-9fbccf1c-b27e-4bfb-aa78-7cb3ab24c2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054994079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.4054994079
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1368242647
Short name T150
Test name
Test status
Simulation time 429683435 ps
CPU time 0.78 seconds
Started Jul 07 05:54:45 PM PDT 24
Finished Jul 07 05:54:46 PM PDT 24
Peak memory 196680 kb
Host smart-95aaab42-f761-4c80-aa3b-ed607b2521a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368242647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1368242647
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2933071392
Short name T205
Test name
Test status
Simulation time 661474750 ps
CPU time 0.92 seconds
Started Jul 07 05:55:42 PM PDT 24
Finished Jul 07 05:55:43 PM PDT 24
Peak memory 183896 kb
Host smart-18330ba5-af8a-4da7-ac7a-2138dceeb3c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933071392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2933071392
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3445408345
Short name T302
Test name
Test status
Simulation time 7031704442 ps
CPU time 9.12 seconds
Started Jul 07 05:55:42 PM PDT 24
Finished Jul 07 05:55:51 PM PDT 24
Peak memory 184052 kb
Host smart-055823e7-c5b0-45dd-92ab-4317d87b8fcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445408345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3445408345
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2954486311
Short name T336
Test name
Test status
Simulation time 739034599 ps
CPU time 0.73 seconds
Started Jul 07 05:55:38 PM PDT 24
Finished Jul 07 05:55:39 PM PDT 24
Peak memory 183816 kb
Host smart-6ba13ed8-8119-4b5d-837b-17f189e35af5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954486311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2954486311
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.218950403
Short name T421
Test name
Test status
Simulation time 569449208 ps
CPU time 1.58 seconds
Started Jul 07 05:55:45 PM PDT 24
Finished Jul 07 05:55:47 PM PDT 24
Peak memory 197192 kb
Host smart-9d4a2e62-9af5-4a70-acb9-5defbc79b32c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218950403 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.218950403
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3505739793
Short name T84
Test name
Test status
Simulation time 535313658 ps
CPU time 1.39 seconds
Started Jul 07 05:55:41 PM PDT 24
Finished Jul 07 05:55:43 PM PDT 24
Peak memory 192976 kb
Host smart-bb71cd0d-cf33-4c41-a9c3-e3bcb359e984
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505739793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3505739793
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.861781250
Short name T291
Test name
Test status
Simulation time 305476888 ps
CPU time 0.93 seconds
Started Jul 07 05:55:45 PM PDT 24
Finished Jul 07 05:55:46 PM PDT 24
Peak memory 183768 kb
Host smart-599e9e16-a1a5-4806-b1b1-928169f6970d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861781250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.861781250
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.344036944
Short name T348
Test name
Test status
Simulation time 326698629 ps
CPU time 1 seconds
Started Jul 07 05:55:38 PM PDT 24
Finished Jul 07 05:55:40 PM PDT 24
Peak memory 183720 kb
Host smart-860cb134-5425-4f7a-a81c-41006a9d2184
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344036944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.344036944
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2100270960
Short name T307
Test name
Test status
Simulation time 432757864 ps
CPU time 0.93 seconds
Started Jul 07 05:55:46 PM PDT 24
Finished Jul 07 05:55:47 PM PDT 24
Peak memory 183732 kb
Host smart-a91f6a12-caeb-42c6-8c4f-375e9968967d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100270960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2100270960
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.432371004
Short name T88
Test name
Test status
Simulation time 1549540429 ps
CPU time 1.57 seconds
Started Jul 07 05:55:44 PM PDT 24
Finished Jul 07 05:55:46 PM PDT 24
Peak memory 193492 kb
Host smart-df873481-2599-462f-abf1-ee24202bbdee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432371004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.432371004
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3576755694
Short name T422
Test name
Test status
Simulation time 433735036 ps
CPU time 1.46 seconds
Started Jul 07 05:55:46 PM PDT 24
Finished Jul 07 05:55:48 PM PDT 24
Peak memory 198468 kb
Host smart-140a1778-181f-4ea8-b7d5-9190a0194214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576755694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3576755694
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.594135700
Short name T391
Test name
Test status
Simulation time 8402421778 ps
CPU time 9.51 seconds
Started Jul 07 05:55:47 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 198204 kb
Host smart-be9693f9-5d8a-469c-a717-53937ca7aba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594135700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.594135700
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4022897962
Short name T59
Test name
Test status
Simulation time 441160859 ps
CPU time 0.96 seconds
Started Jul 07 05:55:47 PM PDT 24
Finished Jul 07 05:55:48 PM PDT 24
Peak memory 194632 kb
Host smart-1c48b048-d8bf-44ee-88ff-6f5fc096d309
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022897962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.4022897962
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.305674766
Short name T365
Test name
Test status
Simulation time 7228522552 ps
CPU time 24.16 seconds
Started Jul 07 05:55:47 PM PDT 24
Finished Jul 07 05:56:11 PM PDT 24
Peak memory 196200 kb
Host smart-3564d1e6-14c0-418d-a13d-b72fa418d839
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305674766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.305674766
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3411540894
Short name T54
Test name
Test status
Simulation time 1218907312 ps
CPU time 1.81 seconds
Started Jul 07 05:55:42 PM PDT 24
Finished Jul 07 05:55:44 PM PDT 24
Peak memory 193264 kb
Host smart-6828feac-1723-44e9-8fe3-d711d128b84a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411540894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3411540894
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.177727400
Short name T292
Test name
Test status
Simulation time 512561562 ps
CPU time 0.84 seconds
Started Jul 07 05:55:45 PM PDT 24
Finished Jul 07 05:55:46 PM PDT 24
Peak memory 196264 kb
Host smart-26a3d076-144e-4376-b31f-730701739e10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177727400 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.177727400
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.426901487
Short name T63
Test name
Test status
Simulation time 526544442 ps
CPU time 0.72 seconds
Started Jul 07 05:55:44 PM PDT 24
Finished Jul 07 05:55:45 PM PDT 24
Peak memory 193828 kb
Host smart-90487b2b-74bf-47cb-8e77-ad9f027d9946
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426901487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.426901487
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1449158210
Short name T332
Test name
Test status
Simulation time 522307881 ps
CPU time 0.91 seconds
Started Jul 07 05:55:43 PM PDT 24
Finished Jul 07 05:55:44 PM PDT 24
Peak memory 183748 kb
Host smart-5cb7ea6d-705c-427e-a99f-0940aee8f44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449158210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1449158210
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1198293191
Short name T406
Test name
Test status
Simulation time 342070031 ps
CPU time 0.9 seconds
Started Jul 07 05:55:46 PM PDT 24
Finished Jul 07 05:55:48 PM PDT 24
Peak memory 183688 kb
Host smart-5c4ff2c8-7664-4f37-96f8-0ad71343752e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198293191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1198293191
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1137863759
Short name T413
Test name
Test status
Simulation time 446471812 ps
CPU time 0.66 seconds
Started Jul 07 05:55:47 PM PDT 24
Finished Jul 07 05:55:48 PM PDT 24
Peak memory 183756 kb
Host smart-a7a7aa80-2e33-4264-9389-d1f3ef889823
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137863759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1137863759
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3390961255
Short name T363
Test name
Test status
Simulation time 1301252791 ps
CPU time 3.83 seconds
Started Jul 07 05:55:49 PM PDT 24
Finished Jul 07 05:55:53 PM PDT 24
Peak memory 193040 kb
Host smart-683d2e4a-520b-45c4-9a41-6c92af4f38eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390961255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3390961255
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.403493131
Short name T285
Test name
Test status
Simulation time 476766800 ps
CPU time 2.86 seconds
Started Jul 07 05:55:42 PM PDT 24
Finished Jul 07 05:55:45 PM PDT 24
Peak memory 198676 kb
Host smart-a89bd648-845a-4e4a-87f2-35026a75ec3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403493131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.403493131
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.134085233
Short name T423
Test name
Test status
Simulation time 4195989803 ps
CPU time 7.01 seconds
Started Jul 07 05:55:43 PM PDT 24
Finished Jul 07 05:55:51 PM PDT 24
Peak memory 197752 kb
Host smart-46b294b8-03f6-43e9-aaf6-922c67a869e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134085233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.134085233
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.143984203
Short name T408
Test name
Test status
Simulation time 464705084 ps
CPU time 0.79 seconds
Started Jul 07 05:56:00 PM PDT 24
Finished Jul 07 05:56:01 PM PDT 24
Peak memory 196140 kb
Host smart-927bcde6-8ccf-4e65-aafa-bf18248b8f6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143984203 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.143984203
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4026973413
Short name T57
Test name
Test status
Simulation time 516741001 ps
CPU time 1.39 seconds
Started Jul 07 05:56:04 PM PDT 24
Finished Jul 07 05:56:06 PM PDT 24
Peak memory 193336 kb
Host smart-fbe037e4-54a8-4b48-af20-3468a0f18172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026973413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4026973413
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3652897566
Short name T349
Test name
Test status
Simulation time 467392972 ps
CPU time 0.82 seconds
Started Jul 07 05:56:02 PM PDT 24
Finished Jul 07 05:56:03 PM PDT 24
Peak memory 192984 kb
Host smart-8cd0a108-93a6-43b5-9253-7109e0da9107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652897566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3652897566
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4079772834
Short name T337
Test name
Test status
Simulation time 2782593226 ps
CPU time 2.69 seconds
Started Jul 07 05:56:02 PM PDT 24
Finished Jul 07 05:56:05 PM PDT 24
Peak memory 192076 kb
Host smart-58f89707-f382-4530-8ca9-e6a5d34ecba9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079772834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.4079772834
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.7505810
Short name T367
Test name
Test status
Simulation time 394021089 ps
CPU time 2.33 seconds
Started Jul 07 05:56:05 PM PDT 24
Finished Jul 07 05:56:07 PM PDT 24
Peak memory 198588 kb
Host smart-981c9743-716f-4513-8e4d-b58a27b92e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7505810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.7505810
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3525148193
Short name T387
Test name
Test status
Simulation time 8614045640 ps
CPU time 14.57 seconds
Started Jul 07 05:56:05 PM PDT 24
Finished Jul 07 05:56:20 PM PDT 24
Peak memory 198080 kb
Host smart-3981d609-b52c-46ed-be44-d42407733c29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525148193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3525148193
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3085220573
Short name T393
Test name
Test status
Simulation time 601816067 ps
CPU time 1.67 seconds
Started Jul 07 05:56:04 PM PDT 24
Finished Jul 07 05:56:06 PM PDT 24
Peak memory 196192 kb
Host smart-d208f7b8-0a55-46ef-8569-603bab25913f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085220573 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3085220573
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1030768057
Short name T61
Test name
Test status
Simulation time 371849153 ps
CPU time 0.84 seconds
Started Jul 07 05:56:07 PM PDT 24
Finished Jul 07 05:56:08 PM PDT 24
Peak memory 193372 kb
Host smart-d66943fd-05ef-48ed-a9c2-e28eeba0fbdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030768057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1030768057
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2536207181
Short name T378
Test name
Test status
Simulation time 289984223 ps
CPU time 0.77 seconds
Started Jul 07 05:56:04 PM PDT 24
Finished Jul 07 05:56:05 PM PDT 24
Peak memory 192968 kb
Host smart-b8555ed6-320e-46c9-92ef-45bee6945c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536207181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2536207181
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.409766489
Short name T360
Test name
Test status
Simulation time 1549213980 ps
CPU time 1.27 seconds
Started Jul 07 05:56:04 PM PDT 24
Finished Jul 07 05:56:05 PM PDT 24
Peak memory 193984 kb
Host smart-a4b1583d-d8e0-4f07-b84e-2955b65b0c02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409766489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.409766489
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2121019417
Short name T293
Test name
Test status
Simulation time 415269563 ps
CPU time 2.06 seconds
Started Jul 07 05:56:01 PM PDT 24
Finished Jul 07 05:56:03 PM PDT 24
Peak memory 198672 kb
Host smart-be0e2c76-d3bb-4260-96a0-38c0cee932c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121019417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2121019417
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3802218767
Short name T333
Test name
Test status
Simulation time 635314704 ps
CPU time 0.73 seconds
Started Jul 07 05:56:03 PM PDT 24
Finished Jul 07 05:56:04 PM PDT 24
Peak memory 196528 kb
Host smart-0074bd70-4687-4284-aad0-a92cfab28c7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802218767 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3802218767
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.430815755
Short name T296
Test name
Test status
Simulation time 331242294 ps
CPU time 0.69 seconds
Started Jul 07 05:56:07 PM PDT 24
Finished Jul 07 05:56:08 PM PDT 24
Peak memory 193020 kb
Host smart-530bb037-f099-484e-afca-52244a218b1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430815755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.430815755
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4016595701
Short name T373
Test name
Test status
Simulation time 407172258 ps
CPU time 1.04 seconds
Started Jul 07 05:56:06 PM PDT 24
Finished Jul 07 05:56:07 PM PDT 24
Peak memory 183752 kb
Host smart-de625dde-ca86-434d-98f6-7126853bf5db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016595701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.4016595701
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.133650331
Short name T87
Test name
Test status
Simulation time 1694070331 ps
CPU time 2.95 seconds
Started Jul 07 05:56:03 PM PDT 24
Finished Jul 07 05:56:06 PM PDT 24
Peak memory 183932 kb
Host smart-9a106229-7645-46eb-b9a5-fbeb5dc13558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133650331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.133650331
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4038686760
Short name T356
Test name
Test status
Simulation time 666280906 ps
CPU time 1.44 seconds
Started Jul 07 05:56:07 PM PDT 24
Finished Jul 07 05:56:08 PM PDT 24
Peak memory 198652 kb
Host smart-ad9dc19b-ca1f-4564-abdd-6ef9f591af3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038686760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4038686760
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.478762661
Short name T323
Test name
Test status
Simulation time 8282946271 ps
CPU time 11.49 seconds
Started Jul 07 05:56:03 PM PDT 24
Finished Jul 07 05:56:15 PM PDT 24
Peak memory 198212 kb
Host smart-0ea14cfe-5c35-46dc-ab34-cf6cfc02f3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478762661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.478762661
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3908127963
Short name T33
Test name
Test status
Simulation time 474740287 ps
CPU time 1.42 seconds
Started Jul 07 05:56:04 PM PDT 24
Finished Jul 07 05:56:06 PM PDT 24
Peak memory 196560 kb
Host smart-4b5824ee-cbe5-4d7e-973d-1c744be19dfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908127963 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3908127963
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3564779310
Short name T58
Test name
Test status
Simulation time 509523244 ps
CPU time 0.82 seconds
Started Jul 07 05:56:09 PM PDT 24
Finished Jul 07 05:56:10 PM PDT 24
Peak memory 193548 kb
Host smart-bd981d66-6f86-45d5-8132-1caba961dac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564779310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3564779310
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3973129969
Short name T334
Test name
Test status
Simulation time 276112274 ps
CPU time 0.9 seconds
Started Jul 07 05:56:07 PM PDT 24
Finished Jul 07 05:56:09 PM PDT 24
Peak memory 193004 kb
Host smart-73b01816-c7fe-4bb7-941b-485259b615e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973129969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3973129969
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1070236924
Short name T326
Test name
Test status
Simulation time 1906508715 ps
CPU time 1.23 seconds
Started Jul 07 05:56:07 PM PDT 24
Finished Jul 07 05:56:09 PM PDT 24
Peak memory 194372 kb
Host smart-c0cc2724-7cf6-4a82-abb2-309b178aab40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070236924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1070236924
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3963476286
Short name T347
Test name
Test status
Simulation time 519133022 ps
CPU time 2.09 seconds
Started Jul 07 05:56:07 PM PDT 24
Finished Jul 07 05:56:09 PM PDT 24
Peak memory 198696 kb
Host smart-e44464e6-72d7-4a2c-aa02-b58818e60f85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963476286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3963476286
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2697543100
Short name T316
Test name
Test status
Simulation time 3841567651 ps
CPU time 4.29 seconds
Started Jul 07 05:56:06 PM PDT 24
Finished Jul 07 05:56:10 PM PDT 24
Peak memory 197888 kb
Host smart-9b0a5560-177d-43d0-9809-ac0fa2ea9037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697543100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2697543100
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3255829028
Short name T417
Test name
Test status
Simulation time 444862239 ps
CPU time 1.38 seconds
Started Jul 07 05:56:10 PM PDT 24
Finished Jul 07 05:56:12 PM PDT 24
Peak memory 196136 kb
Host smart-7d881bbd-b719-45bb-bde9-a0f0c59ba7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255829028 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3255829028
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.123954979
Short name T85
Test name
Test status
Simulation time 479988040 ps
CPU time 1.19 seconds
Started Jul 07 05:56:11 PM PDT 24
Finished Jul 07 05:56:13 PM PDT 24
Peak memory 191960 kb
Host smart-e70c9b2f-8f05-4940-9ec4-5962a01707c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123954979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.123954979
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1952156689
Short name T305
Test name
Test status
Simulation time 295312609 ps
CPU time 0.63 seconds
Started Jul 07 05:56:11 PM PDT 24
Finished Jul 07 05:56:11 PM PDT 24
Peak memory 183736 kb
Host smart-70d48d21-c33f-46ae-aa18-f8739cf22951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952156689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1952156689
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.28907628
Short name T90
Test name
Test status
Simulation time 2051396953 ps
CPU time 1.92 seconds
Started Jul 07 05:56:08 PM PDT 24
Finished Jul 07 05:56:10 PM PDT 24
Peak memory 192020 kb
Host smart-322f2cdc-dd84-412e-81d3-b5d655b630ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28907628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_
timer_same_csr_outstanding.28907628
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1360970524
Short name T390
Test name
Test status
Simulation time 396077723 ps
CPU time 2.76 seconds
Started Jul 07 05:56:06 PM PDT 24
Finished Jul 07 05:56:09 PM PDT 24
Peak memory 198612 kb
Host smart-e5f4a5d9-0061-4aca-9515-c5af586d6b34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360970524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1360970524
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1673869490
Short name T304
Test name
Test status
Simulation time 8312102892 ps
CPU time 11.76 seconds
Started Jul 07 05:56:04 PM PDT 24
Finished Jul 07 05:56:16 PM PDT 24
Peak memory 198540 kb
Host smart-bc9a209f-d5a3-46e4-aa5c-8440516641dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673869490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1673869490
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3996990168
Short name T312
Test name
Test status
Simulation time 455667017 ps
CPU time 0.78 seconds
Started Jul 07 05:56:09 PM PDT 24
Finished Jul 07 05:56:10 PM PDT 24
Peak memory 196304 kb
Host smart-d5911bdb-5068-480e-8e5d-be54a77cbede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996990168 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3996990168
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2399765004
Short name T55
Test name
Test status
Simulation time 313266005 ps
CPU time 0.73 seconds
Started Jul 07 05:56:07 PM PDT 24
Finished Jul 07 05:56:08 PM PDT 24
Peak memory 193044 kb
Host smart-f0e2a5fe-dd49-417f-9752-07cb641d8e32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399765004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2399765004
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1047176254
Short name T424
Test name
Test status
Simulation time 349327660 ps
CPU time 0.81 seconds
Started Jul 07 05:56:09 PM PDT 24
Finished Jul 07 05:56:10 PM PDT 24
Peak memory 183696 kb
Host smart-9e2655a7-d0df-432d-acc4-f738bf498d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047176254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1047176254
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1323627017
Short name T352
Test name
Test status
Simulation time 1255343654 ps
CPU time 1.45 seconds
Started Jul 07 05:56:10 PM PDT 24
Finished Jul 07 05:56:11 PM PDT 24
Peak memory 194036 kb
Host smart-3047c006-9a82-43a3-91c7-7fe88719d75c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323627017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1323627017
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4029712399
Short name T317
Test name
Test status
Simulation time 420599938 ps
CPU time 2.98 seconds
Started Jul 07 05:56:10 PM PDT 24
Finished Jul 07 05:56:13 PM PDT 24
Peak memory 198576 kb
Host smart-ecba45b8-d706-4076-89d8-6928b07cf5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029712399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4029712399
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3890501807
Short name T37
Test name
Test status
Simulation time 8402676822 ps
CPU time 12.19 seconds
Started Jul 07 05:56:09 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 198324 kb
Host smart-b97e5dd8-30df-4c7b-9474-011e50982d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890501807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3890501807
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.428787446
Short name T397
Test name
Test status
Simulation time 492690028 ps
CPU time 0.84 seconds
Started Jul 07 05:56:12 PM PDT 24
Finished Jul 07 05:56:13 PM PDT 24
Peak memory 196236 kb
Host smart-7fd8a8db-05d4-4055-9245-09f2dbff0b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428787446 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.428787446
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3565014757
Short name T416
Test name
Test status
Simulation time 398536854 ps
CPU time 1.1 seconds
Started Jul 07 05:56:14 PM PDT 24
Finished Jul 07 05:56:16 PM PDT 24
Peak memory 193032 kb
Host smart-820d1e44-853d-4b18-9217-0f2b5b6b89c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565014757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3565014757
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2983782200
Short name T288
Test name
Test status
Simulation time 400414929 ps
CPU time 1.03 seconds
Started Jul 07 05:56:13 PM PDT 24
Finished Jul 07 05:56:14 PM PDT 24
Peak memory 183656 kb
Host smart-9d1bdfae-cd46-45e9-b9ad-4ec9499746fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983782200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2983782200
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3292802342
Short name T313
Test name
Test status
Simulation time 2667707814 ps
CPU time 6.04 seconds
Started Jul 07 05:56:13 PM PDT 24
Finished Jul 07 05:56:19 PM PDT 24
Peak memory 194432 kb
Host smart-4e47a7ed-4972-4524-970e-82a389860baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292802342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3292802342
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.190426198
Short name T361
Test name
Test status
Simulation time 478695831 ps
CPU time 2.78 seconds
Started Jul 07 05:56:08 PM PDT 24
Finished Jul 07 05:56:11 PM PDT 24
Peak memory 198636 kb
Host smart-f798f697-4655-482a-9b78-ca72ab7f72db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190426198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.190426198
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1115053726
Short name T368
Test name
Test status
Simulation time 8382862494 ps
CPU time 12.6 seconds
Started Jul 07 05:56:10 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 198352 kb
Host smart-94c3d15e-8702-4042-bde4-0855ea8b4064
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115053726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1115053726
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2729592505
Short name T206
Test name
Test status
Simulation time 412021354 ps
CPU time 0.76 seconds
Started Jul 07 05:56:16 PM PDT 24
Finished Jul 07 05:56:17 PM PDT 24
Peak memory 197040 kb
Host smart-b94de0f5-5815-4eea-a72e-730e7c7fa0a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729592505 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2729592505
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3508919724
Short name T300
Test name
Test status
Simulation time 459848235 ps
CPU time 1.2 seconds
Started Jul 07 05:56:14 PM PDT 24
Finished Jul 07 05:56:15 PM PDT 24
Peak memory 192120 kb
Host smart-e3682dd6-f294-4e0a-99e4-9048bfb1e4a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508919724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3508919724
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2778947839
Short name T286
Test name
Test status
Simulation time 445331680 ps
CPU time 0.75 seconds
Started Jul 07 05:56:13 PM PDT 24
Finished Jul 07 05:56:14 PM PDT 24
Peak memory 192988 kb
Host smart-9c9828c5-7289-4878-bc64-e8ea38ca1593
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778947839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2778947839
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.435344591
Short name T366
Test name
Test status
Simulation time 2867611771 ps
CPU time 4.46 seconds
Started Jul 07 05:56:13 PM PDT 24
Finished Jul 07 05:56:18 PM PDT 24
Peak memory 195324 kb
Host smart-745926fc-2eea-4af3-9372-96854a821cae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435344591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.435344591
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.977975654
Short name T320
Test name
Test status
Simulation time 483102431 ps
CPU time 1.52 seconds
Started Jul 07 05:56:14 PM PDT 24
Finished Jul 07 05:56:16 PM PDT 24
Peak memory 198696 kb
Host smart-ca41e646-908d-4939-9c62-142a7b4a8f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977975654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.977975654
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3124343837
Short name T314
Test name
Test status
Simulation time 4704725761 ps
CPU time 2.52 seconds
Started Jul 07 05:56:12 PM PDT 24
Finished Jul 07 05:56:15 PM PDT 24
Peak memory 197668 kb
Host smart-6b1e1896-df25-4ed5-aee5-074e465f02a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124343837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3124343837
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1351580330
Short name T386
Test name
Test status
Simulation time 319060781 ps
CPU time 1.07 seconds
Started Jul 07 05:56:15 PM PDT 24
Finished Jul 07 05:56:17 PM PDT 24
Peak memory 196208 kb
Host smart-8c5c6e06-8ee8-4c69-bd67-ae76b0aceea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351580330 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1351580330
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3644956265
Short name T60
Test name
Test status
Simulation time 428112102 ps
CPU time 1.27 seconds
Started Jul 07 05:56:14 PM PDT 24
Finished Jul 07 05:56:15 PM PDT 24
Peak memory 193192 kb
Host smart-fd08d548-cd29-44b7-ae31-5a112a09585e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644956265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3644956265
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1325630603
Short name T284
Test name
Test status
Simulation time 416245079 ps
CPU time 0.75 seconds
Started Jul 07 05:56:19 PM PDT 24
Finished Jul 07 05:56:20 PM PDT 24
Peak memory 192928 kb
Host smart-053d0981-04ed-4806-8299-ec78a3c65627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325630603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1325630603
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3620003017
Short name T376
Test name
Test status
Simulation time 2403223266 ps
CPU time 3.75 seconds
Started Jul 07 05:56:20 PM PDT 24
Finished Jul 07 05:56:24 PM PDT 24
Peak memory 193788 kb
Host smart-96b6ec33-14db-4629-bfd2-8d698c4704df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620003017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3620003017
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1013051786
Short name T384
Test name
Test status
Simulation time 431182575 ps
CPU time 1.17 seconds
Started Jul 07 05:56:10 PM PDT 24
Finished Jul 07 05:56:12 PM PDT 24
Peak memory 198564 kb
Host smart-dad34a0e-7950-474a-868a-196e9adebb11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013051786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1013051786
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3718902688
Short name T329
Test name
Test status
Simulation time 4168674778 ps
CPU time 6.29 seconds
Started Jul 07 05:56:11 PM PDT 24
Finished Jul 07 05:56:18 PM PDT 24
Peak memory 197892 kb
Host smart-a799d5d9-d170-46a8-97d8-f3142736c696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718902688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3718902688
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2468665089
Short name T34
Test name
Test status
Simulation time 550734799 ps
CPU time 1.5 seconds
Started Jul 07 05:56:13 PM PDT 24
Finished Jul 07 05:56:15 PM PDT 24
Peak memory 197268 kb
Host smart-842f0b04-3889-4899-8edc-d96fb03201af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468665089 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2468665089
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2847160966
Short name T321
Test name
Test status
Simulation time 321116150 ps
CPU time 0.62 seconds
Started Jul 07 05:56:15 PM PDT 24
Finished Jul 07 05:56:16 PM PDT 24
Peak memory 193032 kb
Host smart-4648f2f6-d734-47f0-8067-3c95456d88cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847160966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2847160966
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.849376098
Short name T290
Test name
Test status
Simulation time 507426429 ps
CPU time 0.63 seconds
Started Jul 07 05:56:14 PM PDT 24
Finished Jul 07 05:56:15 PM PDT 24
Peak memory 183772 kb
Host smart-c0486e42-d5b3-417a-ad4c-80af5cbea374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849376098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.849376098
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1352980350
Short name T82
Test name
Test status
Simulation time 2859205004 ps
CPU time 4.7 seconds
Started Jul 07 05:56:17 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 183844 kb
Host smart-25ca6438-ed2e-4485-a6c8-253e18175d44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352980350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1352980350
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3037108733
Short name T396
Test name
Test status
Simulation time 614546997 ps
CPU time 1.43 seconds
Started Jul 07 05:56:17 PM PDT 24
Finished Jul 07 05:56:19 PM PDT 24
Peak memory 198572 kb
Host smart-044b41e9-e170-4a35-9283-c15ee975b508
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037108733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3037108733
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1109248107
Short name T372
Test name
Test status
Simulation time 8738936780 ps
CPU time 4.37 seconds
Started Jul 07 05:56:15 PM PDT 24
Finished Jul 07 05:56:20 PM PDT 24
Peak memory 198140 kb
Host smart-1ce4acdf-f703-47b0-b860-6b3341ddb65d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109248107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1109248107
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1971063789
Short name T425
Test name
Test status
Simulation time 623807028 ps
CPU time 0.92 seconds
Started Jul 07 05:55:49 PM PDT 24
Finished Jul 07 05:55:50 PM PDT 24
Peak memory 192020 kb
Host smart-25228adb-cac6-4920-82db-f6b0fe69f7b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971063789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1971063789
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.863593448
Short name T62
Test name
Test status
Simulation time 10202865017 ps
CPU time 38.23 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:56:30 PM PDT 24
Peak memory 196428 kb
Host smart-812522d7-4fe8-4640-ab56-0044507bfd9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863593448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.863593448
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4254500515
Short name T399
Test name
Test status
Simulation time 793939507 ps
CPU time 0.91 seconds
Started Jul 07 05:55:45 PM PDT 24
Finished Jul 07 05:55:47 PM PDT 24
Peak memory 192168 kb
Host smart-0453acab-0f5f-44fc-b0ac-a66319191a31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254500515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4254500515
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.22122429
Short name T318
Test name
Test status
Simulation time 388892590 ps
CPU time 0.96 seconds
Started Jul 07 05:55:48 PM PDT 24
Finished Jul 07 05:55:49 PM PDT 24
Peak memory 196536 kb
Host smart-5a0d8e18-1b4c-44bd-9575-6bbb6fcc9e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22122429 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.22122429
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2432529986
Short name T343
Test name
Test status
Simulation time 338519890 ps
CPU time 0.71 seconds
Started Jul 07 05:55:48 PM PDT 24
Finished Jul 07 05:55:49 PM PDT 24
Peak memory 193344 kb
Host smart-87431440-4a5a-4411-97d9-4d160b090635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432529986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2432529986
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.248692901
Short name T405
Test name
Test status
Simulation time 486889157 ps
CPU time 0.62 seconds
Started Jul 07 05:55:45 PM PDT 24
Finished Jul 07 05:55:46 PM PDT 24
Peak memory 183772 kb
Host smart-11012280-f8b6-4d61-a0f5-38c544188d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248692901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.248692901
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3968796598
Short name T371
Test name
Test status
Simulation time 371445465 ps
CPU time 0.99 seconds
Started Jul 07 05:55:50 PM PDT 24
Finished Jul 07 05:55:51 PM PDT 24
Peak memory 183676 kb
Host smart-f0b66f77-3cf3-439c-9c91-86e3fb617008
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968796598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3968796598
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3329400580
Short name T335
Test name
Test status
Simulation time 393597233 ps
CPU time 0.64 seconds
Started Jul 07 05:55:50 PM PDT 24
Finished Jul 07 05:55:51 PM PDT 24
Peak memory 183736 kb
Host smart-3db2579d-ed4b-40e6-a9f4-91c437ca9cc6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329400580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3329400580
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2048301272
Short name T411
Test name
Test status
Simulation time 1590168544 ps
CPU time 3.62 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:55:55 PM PDT 24
Peak memory 193076 kb
Host smart-f0f5f0d6-57ba-4e4c-8f3f-51790bfd0a34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048301272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2048301272
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4081735310
Short name T402
Test name
Test status
Simulation time 487652826 ps
CPU time 2.34 seconds
Started Jul 07 05:55:50 PM PDT 24
Finished Jul 07 05:55:52 PM PDT 24
Peak memory 198672 kb
Host smart-4ac78f3a-0f67-4518-9c0a-78d0efc2dcab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081735310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4081735310
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2534050248
Short name T359
Test name
Test status
Simulation time 4429993960 ps
CPU time 1.26 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:55:53 PM PDT 24
Peak memory 196856 kb
Host smart-4c417c74-bdf6-48b1-8b79-352baa5ace68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534050248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2534050248
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.186486402
Short name T385
Test name
Test status
Simulation time 499882156 ps
CPU time 1.26 seconds
Started Jul 07 05:56:16 PM PDT 24
Finished Jul 07 05:56:17 PM PDT 24
Peak memory 192988 kb
Host smart-8dc829d0-75b8-4e33-8584-2f0f298ea201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186486402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.186486402
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.914301297
Short name T395
Test name
Test status
Simulation time 465877595 ps
CPU time 0.71 seconds
Started Jul 07 05:56:14 PM PDT 24
Finished Jul 07 05:56:14 PM PDT 24
Peak memory 183768 kb
Host smart-cde0021f-bc55-4a15-ac48-1122e1cab170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914301297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.914301297
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1886877787
Short name T340
Test name
Test status
Simulation time 459037389 ps
CPU time 1.24 seconds
Started Jul 07 05:56:21 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 183756 kb
Host smart-3af36647-747d-4d1e-b9ae-35bb53f47a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886877787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1886877787
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.570240742
Short name T298
Test name
Test status
Simulation time 477203253 ps
CPU time 0.71 seconds
Started Jul 07 05:56:20 PM PDT 24
Finished Jul 07 05:56:21 PM PDT 24
Peak memory 192964 kb
Host smart-1276d1d8-35aa-43c1-aa00-9bfc005e5da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570240742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.570240742
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2514470355
Short name T351
Test name
Test status
Simulation time 304788703 ps
CPU time 0.71 seconds
Started Jul 07 05:56:20 PM PDT 24
Finished Jul 07 05:56:21 PM PDT 24
Peak memory 183708 kb
Host smart-9fe7029b-7736-4d6c-b988-53710e4278a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514470355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2514470355
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1667103408
Short name T403
Test name
Test status
Simulation time 368189313 ps
CPU time 0.77 seconds
Started Jul 07 05:56:20 PM PDT 24
Finished Jul 07 05:56:21 PM PDT 24
Peak memory 183636 kb
Host smart-560fbc9b-8f67-4c14-aea7-afed1d5d92aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667103408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1667103408
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1809945188
Short name T354
Test name
Test status
Simulation time 337898563 ps
CPU time 0.67 seconds
Started Jul 07 05:56:21 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 183748 kb
Host smart-9ed92cbd-1036-4fe5-bdd5-bddf44aaace4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809945188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1809945188
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.147388523
Short name T346
Test name
Test status
Simulation time 366284672 ps
CPU time 1.02 seconds
Started Jul 07 05:56:19 PM PDT 24
Finished Jul 07 05:56:20 PM PDT 24
Peak memory 184012 kb
Host smart-ef1a399f-8cbb-4b6c-8bf8-3374f602d8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147388523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.147388523
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2527797491
Short name T330
Test name
Test status
Simulation time 466603266 ps
CPU time 0.89 seconds
Started Jul 07 05:56:22 PM PDT 24
Finished Jul 07 05:56:23 PM PDT 24
Peak memory 193000 kb
Host smart-63b6a3b3-cba1-4b6c-9eb2-c891a33e8a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527797491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2527797491
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1176896590
Short name T303
Test name
Test status
Simulation time 397290302 ps
CPU time 1.12 seconds
Started Jul 07 05:56:17 PM PDT 24
Finished Jul 07 05:56:19 PM PDT 24
Peak memory 192992 kb
Host smart-9ababb59-e169-4e0a-9aea-abb158db1d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176896590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1176896590
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3859635088
Short name T52
Test name
Test status
Simulation time 689446998 ps
CPU time 1.41 seconds
Started Jul 07 05:55:54 PM PDT 24
Finished Jul 07 05:55:55 PM PDT 24
Peak memory 183688 kb
Host smart-3bc45b8d-f348-4970-ae05-1d7290597308
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859635088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3859635088
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.556393040
Short name T388
Test name
Test status
Simulation time 7301631609 ps
CPU time 11.55 seconds
Started Jul 07 05:55:55 PM PDT 24
Finished Jul 07 05:56:07 PM PDT 24
Peak memory 192212 kb
Host smart-4ea449fe-45a5-4726-b9b1-62541f01255e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556393040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.556393040
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1578547413
Short name T412
Test name
Test status
Simulation time 680667316 ps
CPU time 1.66 seconds
Started Jul 07 05:55:49 PM PDT 24
Finished Jul 07 05:55:51 PM PDT 24
Peak memory 193040 kb
Host smart-462dc783-9f16-4c3a-9959-1d1e828faefa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578547413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1578547413
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.626780581
Short name T38
Test name
Test status
Simulation time 490255662 ps
CPU time 1.35 seconds
Started Jul 07 05:55:56 PM PDT 24
Finished Jul 07 05:55:58 PM PDT 24
Peak memory 195496 kb
Host smart-3cc53bb2-5291-477b-a8fa-e80e6c87544c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626780581 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.626780581
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1103862428
Short name T369
Test name
Test status
Simulation time 458983320 ps
CPU time 1.14 seconds
Started Jul 07 05:55:56 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 192080 kb
Host smart-408cd0d8-01a5-4f55-9627-708df32ef030
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103862428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1103862428
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1912192461
Short name T289
Test name
Test status
Simulation time 574783052 ps
CPU time 0.58 seconds
Started Jul 07 05:55:48 PM PDT 24
Finished Jul 07 05:55:49 PM PDT 24
Peak memory 183700 kb
Host smart-54efecb6-94b4-4fb0-ab70-54040f6ff5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912192461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1912192461
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.60278677
Short name T358
Test name
Test status
Simulation time 335410020 ps
CPU time 0.62 seconds
Started Jul 07 05:55:50 PM PDT 24
Finished Jul 07 05:55:51 PM PDT 24
Peak memory 183668 kb
Host smart-6e69cbdb-aa05-4fc3-a3df-49fb0ab07e78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60278677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_mem_partial_access.60278677
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2446095224
Short name T380
Test name
Test status
Simulation time 296089136 ps
CPU time 0.61 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:55:52 PM PDT 24
Peak memory 183696 kb
Host smart-80ccf785-5084-4232-9b59-d1270aab65da
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446095224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2446095224
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3519309392
Short name T83
Test name
Test status
Simulation time 1286432771 ps
CPU time 1 seconds
Started Jul 07 05:55:53 PM PDT 24
Finished Jul 07 05:55:54 PM PDT 24
Peak memory 193708 kb
Host smart-6e3a5436-f0d9-456f-8f76-849f4892ea32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519309392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3519309392
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.877438721
Short name T344
Test name
Test status
Simulation time 570860389 ps
CPU time 1.65 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:55:53 PM PDT 24
Peak memory 198584 kb
Host smart-1973c836-3cd8-4095-80e5-c0331bbc45c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877438721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.877438721
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1657761211
Short name T327
Test name
Test status
Simulation time 366655261 ps
CPU time 0.67 seconds
Started Jul 07 05:56:21 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 193000 kb
Host smart-2e9a4ba3-9c3e-4858-b78d-25e36ac1e76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657761211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1657761211
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1982916125
Short name T398
Test name
Test status
Simulation time 385290045 ps
CPU time 0.7 seconds
Started Jul 07 05:56:20 PM PDT 24
Finished Jul 07 05:56:21 PM PDT 24
Peak memory 183712 kb
Host smart-5da2e821-da95-48c8-8b9a-edfd44959ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982916125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1982916125
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.60145987
Short name T419
Test name
Test status
Simulation time 291303282 ps
CPU time 0.64 seconds
Started Jul 07 05:56:20 PM PDT 24
Finished Jul 07 05:56:21 PM PDT 24
Peak memory 183740 kb
Host smart-ce8ead26-35e7-4eb9-9d51-88c546237636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60145987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.60145987
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.83637750
Short name T420
Test name
Test status
Simulation time 495673948 ps
CPU time 0.73 seconds
Started Jul 07 05:56:18 PM PDT 24
Finished Jul 07 05:56:19 PM PDT 24
Peak memory 183780 kb
Host smart-b684151d-7f7e-4411-8141-e3b4bdab0581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83637750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.83637750
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1576745621
Short name T306
Test name
Test status
Simulation time 355519739 ps
CPU time 0.85 seconds
Started Jul 07 05:56:21 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 183696 kb
Host smart-e8d9559a-6dd6-4b8e-a99c-23fd303e3ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576745621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1576745621
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2395758304
Short name T311
Test name
Test status
Simulation time 451400338 ps
CPU time 0.71 seconds
Started Jul 07 05:56:20 PM PDT 24
Finished Jul 07 05:56:21 PM PDT 24
Peak memory 183744 kb
Host smart-1f1c2f17-4cad-472b-b4a7-1a08253a710b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395758304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2395758304
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3336437279
Short name T370
Test name
Test status
Simulation time 326263726 ps
CPU time 0.83 seconds
Started Jul 07 05:56:20 PM PDT 24
Finished Jul 07 05:56:21 PM PDT 24
Peak memory 183732 kb
Host smart-1230bc47-1952-42e0-a326-bd63d71f20cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336437279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3336437279
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4268586000
Short name T345
Test name
Test status
Simulation time 520125990 ps
CPU time 0.67 seconds
Started Jul 07 05:56:23 PM PDT 24
Finished Jul 07 05:56:24 PM PDT 24
Peak memory 192988 kb
Host smart-e77ed86d-3736-4e17-9384-17e376743e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268586000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.4268586000
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.105238335
Short name T381
Test name
Test status
Simulation time 349592618 ps
CPU time 0.83 seconds
Started Jul 07 05:56:18 PM PDT 24
Finished Jul 07 05:56:19 PM PDT 24
Peak memory 183756 kb
Host smart-1b1b61fb-8c16-467e-a71f-6ba2a8720b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105238335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.105238335
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4155370283
Short name T374
Test name
Test status
Simulation time 436262830 ps
CPU time 1.18 seconds
Started Jul 07 05:56:19 PM PDT 24
Finished Jul 07 05:56:20 PM PDT 24
Peak memory 184008 kb
Host smart-e322eb32-3db9-402f-8a9b-279d7bd775a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155370283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4155370283
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.47529275
Short name T64
Test name
Test status
Simulation time 643143329 ps
CPU time 0.86 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:55:52 PM PDT 24
Peak memory 194064 kb
Host smart-44b8ba37-2d00-481d-aea1-40270e523e11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47529275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_ali
asing.47529275
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1455085161
Short name T56
Test name
Test status
Simulation time 4015347165 ps
CPU time 5.34 seconds
Started Jul 07 05:55:55 PM PDT 24
Finished Jul 07 05:56:00 PM PDT 24
Peak memory 192284 kb
Host smart-47ebcba1-3623-4d51-a67d-f5201245c0dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455085161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1455085161
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3254634699
Short name T339
Test name
Test status
Simulation time 1311656260 ps
CPU time 2.72 seconds
Started Jul 07 05:55:54 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 183828 kb
Host smart-95c01984-8524-4a3f-824f-1b4c5614901b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254634699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3254634699
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3812227958
Short name T294
Test name
Test status
Simulation time 317463969 ps
CPU time 1.05 seconds
Started Jul 07 05:55:57 PM PDT 24
Finished Jul 07 05:55:58 PM PDT 24
Peak memory 195712 kb
Host smart-2272ebba-d306-4d13-a410-19dcc5a73d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812227958 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3812227958
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.220389747
Short name T409
Test name
Test status
Simulation time 566217192 ps
CPU time 0.67 seconds
Started Jul 07 05:55:50 PM PDT 24
Finished Jul 07 05:55:51 PM PDT 24
Peak memory 193368 kb
Host smart-e7b50047-aed9-4492-b05b-7531391b369d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220389747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.220389747
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1514354343
Short name T341
Test name
Test status
Simulation time 395275055 ps
CPU time 1.07 seconds
Started Jul 07 05:55:53 PM PDT 24
Finished Jul 07 05:55:54 PM PDT 24
Peak memory 192976 kb
Host smart-fa935ff3-09ca-4f22-8c76-aab69add1aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514354343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1514354343
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4050097080
Short name T410
Test name
Test status
Simulation time 486869259 ps
CPU time 0.78 seconds
Started Jul 07 05:55:52 PM PDT 24
Finished Jul 07 05:55:53 PM PDT 24
Peak memory 183664 kb
Host smart-54d6010e-419c-4f4d-b362-b82999e7fe6f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050097080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4050097080
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.913557122
Short name T401
Test name
Test status
Simulation time 402875772 ps
CPU time 1.16 seconds
Started Jul 07 05:55:53 PM PDT 24
Finished Jul 07 05:55:55 PM PDT 24
Peak memory 183744 kb
Host smart-98a0c60d-c20c-4919-b231-21fbcd1b6c72
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913557122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.913557122
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4215318687
Short name T350
Test name
Test status
Simulation time 2222908691 ps
CPU time 2.97 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:55:54 PM PDT 24
Peak memory 184288 kb
Host smart-43c2639e-502e-446f-b4de-0f2aea21dd5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215318687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4215318687
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1454459675
Short name T414
Test name
Test status
Simulation time 564995100 ps
CPU time 1.69 seconds
Started Jul 07 05:55:54 PM PDT 24
Finished Jul 07 05:55:56 PM PDT 24
Peak memory 198656 kb
Host smart-2dbc95a3-93e8-4892-9e52-3a65b74b927c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454459675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1454459675
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.682655985
Short name T418
Test name
Test status
Simulation time 8483900482 ps
CPU time 11.13 seconds
Started Jul 07 05:55:50 PM PDT 24
Finished Jul 07 05:56:02 PM PDT 24
Peak memory 198352 kb
Host smart-8050c5ea-7f33-444f-800e-5a0cb9c9678a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682655985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.682655985
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.346911756
Short name T377
Test name
Test status
Simulation time 466966807 ps
CPU time 0.68 seconds
Started Jul 07 05:56:22 PM PDT 24
Finished Jul 07 05:56:23 PM PDT 24
Peak memory 193008 kb
Host smart-56c950a2-560e-4ede-a829-8b997b4167cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346911756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.346911756
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1850851861
Short name T287
Test name
Test status
Simulation time 404826789 ps
CPU time 0.62 seconds
Started Jul 07 05:56:21 PM PDT 24
Finished Jul 07 05:56:23 PM PDT 24
Peak memory 183712 kb
Host smart-e8a14e84-d2de-4f7e-bd34-41d5cd2aefb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850851861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1850851861
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1684742291
Short name T394
Test name
Test status
Simulation time 326282526 ps
CPU time 1.09 seconds
Started Jul 07 05:56:20 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 192964 kb
Host smart-3860c893-98b8-48bd-81fe-83d8e2dd815a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684742291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1684742291
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1221648576
Short name T342
Test name
Test status
Simulation time 300615577 ps
CPU time 0.71 seconds
Started Jul 07 05:56:23 PM PDT 24
Finished Jul 07 05:56:24 PM PDT 24
Peak memory 183768 kb
Host smart-584119e7-8e52-4c44-be07-37bc67a39447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221648576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1221648576
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4072970801
Short name T324
Test name
Test status
Simulation time 317754053 ps
CPU time 0.69 seconds
Started Jul 07 05:56:23 PM PDT 24
Finished Jul 07 05:56:24 PM PDT 24
Peak memory 192988 kb
Host smart-2074af0a-0138-41ab-8aa2-87a58a9d97ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072970801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4072970801
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1158076944
Short name T310
Test name
Test status
Simulation time 484700789 ps
CPU time 0.79 seconds
Started Jul 07 05:56:18 PM PDT 24
Finished Jul 07 05:56:19 PM PDT 24
Peak memory 183752 kb
Host smart-9454f972-b74b-46d0-9a5d-2603f99048e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158076944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1158076944
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.715506437
Short name T400
Test name
Test status
Simulation time 545178473 ps
CPU time 0.65 seconds
Started Jul 07 05:56:27 PM PDT 24
Finished Jul 07 05:56:28 PM PDT 24
Peak memory 183748 kb
Host smart-0256a004-e746-421f-a9ba-81d0c0828215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715506437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.715506437
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1384591755
Short name T297
Test name
Test status
Simulation time 487353291 ps
CPU time 0.73 seconds
Started Jul 07 05:56:22 PM PDT 24
Finished Jul 07 05:56:23 PM PDT 24
Peak memory 183768 kb
Host smart-d85b7548-9eaf-4009-bb0b-5436ec7ad18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384591755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1384591755
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3198526261
Short name T315
Test name
Test status
Simulation time 323162970 ps
CPU time 0.62 seconds
Started Jul 07 05:56:22 PM PDT 24
Finished Jul 07 05:56:23 PM PDT 24
Peak memory 183748 kb
Host smart-f34e4056-ccd3-424a-b87a-524059e4ccc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198526261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3198526261
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3998168445
Short name T322
Test name
Test status
Simulation time 303741652 ps
CPU time 0.63 seconds
Started Jul 07 05:56:21 PM PDT 24
Finished Jul 07 05:56:22 PM PDT 24
Peak memory 183744 kb
Host smart-0fa4cd6f-2781-4251-8982-b1d34e1b4d45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998168445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3998168445
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3159416321
Short name T309
Test name
Test status
Simulation time 387601873 ps
CPU time 0.75 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:55:52 PM PDT 24
Peak memory 196496 kb
Host smart-52a788bb-e00e-46bd-901f-23c123f47785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159416321 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3159416321
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1382873963
Short name T407
Test name
Test status
Simulation time 354962696 ps
CPU time 0.95 seconds
Started Jul 07 05:55:54 PM PDT 24
Finished Jul 07 05:55:55 PM PDT 24
Peak memory 183640 kb
Host smart-15742f47-534a-4979-9478-213ebaf08fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382873963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1382873963
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1579773514
Short name T328
Test name
Test status
Simulation time 2331325166 ps
CPU time 1.57 seconds
Started Jul 07 05:55:57 PM PDT 24
Finished Jul 07 05:55:58 PM PDT 24
Peak memory 192084 kb
Host smart-8ca4b110-feee-45a2-a359-6ccc440344d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579773514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1579773514
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.578203851
Short name T295
Test name
Test status
Simulation time 326006018 ps
CPU time 1.88 seconds
Started Jul 07 05:55:53 PM PDT 24
Finished Jul 07 05:55:56 PM PDT 24
Peak memory 198604 kb
Host smart-17417c7d-6031-4c6d-8513-4cb6be0903ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578203851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.578203851
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1278153810
Short name T331
Test name
Test status
Simulation time 7954996454 ps
CPU time 2.92 seconds
Started Jul 07 05:55:50 PM PDT 24
Finished Jul 07 05:55:53 PM PDT 24
Peak memory 198304 kb
Host smart-f517bf68-cb55-4190-a82c-c78d66acc216
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278153810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1278153810
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1770190374
Short name T319
Test name
Test status
Simulation time 326450710 ps
CPU time 1.05 seconds
Started Jul 07 05:55:54 PM PDT 24
Finished Jul 07 05:55:55 PM PDT 24
Peak memory 195984 kb
Host smart-ff9cf41b-054f-47e2-97a2-d5eff855224a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770190374 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1770190374
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1713037832
Short name T404
Test name
Test status
Simulation time 314813097 ps
CPU time 0.76 seconds
Started Jul 07 05:55:56 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 193020 kb
Host smart-9f79449c-2728-440c-aa29-656061b94304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713037832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1713037832
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2853032432
Short name T379
Test name
Test status
Simulation time 443184401 ps
CPU time 0.69 seconds
Started Jul 07 05:55:56 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 183752 kb
Host smart-50addc02-4c2c-4349-8ba9-34da6ffb1e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853032432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2853032432
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3807223837
Short name T355
Test name
Test status
Simulation time 2269062505 ps
CPU time 1.52 seconds
Started Jul 07 05:55:57 PM PDT 24
Finished Jul 07 05:55:59 PM PDT 24
Peak memory 195608 kb
Host smart-7c62f12f-f701-4148-873b-eb4e95fe8261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807223837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3807223837
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.993541200
Short name T362
Test name
Test status
Simulation time 328541261 ps
CPU time 1.31 seconds
Started Jul 07 05:55:51 PM PDT 24
Finished Jul 07 05:55:53 PM PDT 24
Peak memory 198492 kb
Host smart-8e091ffd-6217-4979-896a-6053b6e6b748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993541200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.993541200
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2975882851
Short name T35
Test name
Test status
Simulation time 4354797503 ps
CPU time 2.35 seconds
Started Jul 07 05:55:57 PM PDT 24
Finished Jul 07 05:56:00 PM PDT 24
Peak memory 197656 kb
Host smart-76645f98-85ae-49e1-a4e5-955fe9e5dd12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975882851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2975882851
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.320431044
Short name T301
Test name
Test status
Simulation time 435321294 ps
CPU time 0.87 seconds
Started Jul 07 05:55:58 PM PDT 24
Finished Jul 07 05:55:59 PM PDT 24
Peak memory 196804 kb
Host smart-fea1c171-73aa-480e-b1ac-b5feb86f17e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320431044 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.320431044
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.528372552
Short name T382
Test name
Test status
Simulation time 408750812 ps
CPU time 0.7 seconds
Started Jul 07 05:55:53 PM PDT 24
Finished Jul 07 05:55:54 PM PDT 24
Peak memory 192136 kb
Host smart-64c32cdd-6af6-44df-882f-9e0d5ba9d5ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528372552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.528372552
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1519114412
Short name T308
Test name
Test status
Simulation time 371380579 ps
CPU time 0.68 seconds
Started Jul 07 05:55:54 PM PDT 24
Finished Jul 07 05:55:55 PM PDT 24
Peak memory 183756 kb
Host smart-04524bd4-ff0b-4af4-b096-cfb71388a825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519114412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1519114412
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3692409611
Short name T357
Test name
Test status
Simulation time 2535984054 ps
CPU time 4.04 seconds
Started Jul 07 05:55:53 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 192060 kb
Host smart-163cb930-f224-4611-b932-8761c1991262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692409611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3692409611
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1921350402
Short name T299
Test name
Test status
Simulation time 550992345 ps
CPU time 1.9 seconds
Started Jul 07 05:55:56 PM PDT 24
Finished Jul 07 05:55:58 PM PDT 24
Peak memory 198612 kb
Host smart-f4715321-d0ca-47a3-88a5-47428c38073b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921350402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1921350402
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2444747739
Short name T201
Test name
Test status
Simulation time 3973413556 ps
CPU time 7.14 seconds
Started Jul 07 05:55:56 PM PDT 24
Finished Jul 07 05:56:03 PM PDT 24
Peak memory 198016 kb
Host smart-5528f784-202a-4727-b7ff-573db51cdae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444747739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2444747739
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3749977491
Short name T389
Test name
Test status
Simulation time 461906069 ps
CPU time 1.06 seconds
Started Jul 07 05:56:01 PM PDT 24
Finished Jul 07 05:56:02 PM PDT 24
Peak memory 197104 kb
Host smart-036d9cac-cdfa-4b5f-ab21-dd9a7babab22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749977491 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3749977491
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2815340384
Short name T86
Test name
Test status
Simulation time 501979999 ps
CPU time 0.75 seconds
Started Jul 07 05:56:06 PM PDT 24
Finished Jul 07 05:56:07 PM PDT 24
Peak memory 193032 kb
Host smart-a127dab0-92ec-42b2-863f-0278e897e3b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815340384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2815340384
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2982426341
Short name T364
Test name
Test status
Simulation time 368672990 ps
CPU time 0.78 seconds
Started Jul 07 05:56:00 PM PDT 24
Finished Jul 07 05:56:01 PM PDT 24
Peak memory 183748 kb
Host smart-518ba0b1-ac48-4a0e-ae5e-5cf3a1be49a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982426341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2982426341
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.442924175
Short name T89
Test name
Test status
Simulation time 1238913983 ps
CPU time 0.8 seconds
Started Jul 07 05:56:04 PM PDT 24
Finished Jul 07 05:56:05 PM PDT 24
Peak memory 183840 kb
Host smart-2bdc2fcb-bc52-4d17-b6e1-d5b1b1e6cf40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442924175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.442924175
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3196245685
Short name T415
Test name
Test status
Simulation time 511232881 ps
CPU time 1.42 seconds
Started Jul 07 05:56:06 PM PDT 24
Finished Jul 07 05:56:08 PM PDT 24
Peak memory 198648 kb
Host smart-b54cb352-47a9-4f27-a5bf-a8825549ab0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196245685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3196245685
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.770715202
Short name T202
Test name
Test status
Simulation time 8546128766 ps
CPU time 13.66 seconds
Started Jul 07 05:55:57 PM PDT 24
Finished Jul 07 05:56:11 PM PDT 24
Peak memory 198124 kb
Host smart-badac96a-4e2d-4472-bdfb-ed11660d9ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770715202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.770715202
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2040836535
Short name T353
Test name
Test status
Simulation time 385603743 ps
CPU time 1.21 seconds
Started Jul 07 05:56:04 PM PDT 24
Finished Jul 07 05:56:05 PM PDT 24
Peak memory 197064 kb
Host smart-98dbacd2-255d-435b-99c2-85387a884291
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040836535 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2040836535
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1784967863
Short name T392
Test name
Test status
Simulation time 323032060 ps
CPU time 0.65 seconds
Started Jul 07 05:56:01 PM PDT 24
Finished Jul 07 05:56:02 PM PDT 24
Peak memory 193036 kb
Host smart-9e0f513a-3dc1-4299-a3a6-efd5f3d45352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784967863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1784967863
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3999341417
Short name T383
Test name
Test status
Simulation time 313966816 ps
CPU time 0.66 seconds
Started Jul 07 05:55:56 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 183768 kb
Host smart-c4047bb7-e08b-4b41-ade2-a3a18499d7f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999341417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3999341417
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4222605626
Short name T338
Test name
Test status
Simulation time 2787758589 ps
CPU time 4.32 seconds
Started Jul 07 05:56:01 PM PDT 24
Finished Jul 07 05:56:06 PM PDT 24
Peak memory 194988 kb
Host smart-add66abc-cbd9-4b1a-8d89-c6e9b8869aaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222605626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.4222605626
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3906746451
Short name T375
Test name
Test status
Simulation time 499119285 ps
CPU time 2.2 seconds
Started Jul 07 05:55:57 PM PDT 24
Finished Jul 07 05:56:00 PM PDT 24
Peak memory 198704 kb
Host smart-2fd5d464-89ac-4528-a8d3-c4a92492a1a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906746451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3906746451
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3352729797
Short name T325
Test name
Test status
Simulation time 3748217363 ps
CPU time 6.22 seconds
Started Jul 07 05:55:58 PM PDT 24
Finished Jul 07 05:56:04 PM PDT 24
Peak memory 196820 kb
Host smart-8d613f3b-1f46-4275-b27b-73eead3784ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352729797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3352729797
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3057365420
Short name T230
Test name
Test status
Simulation time 16547814545 ps
CPU time 4.57 seconds
Started Jul 07 05:54:39 PM PDT 24
Finished Jul 07 05:54:44 PM PDT 24
Peak memory 196960 kb
Host smart-6fe647ec-7916-43fb-bdec-61b1646ec4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057365420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3057365420
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3818156562
Short name T248
Test name
Test status
Simulation time 560024613 ps
CPU time 1.04 seconds
Started Jul 07 05:54:40 PM PDT 24
Finished Jul 07 05:54:41 PM PDT 24
Peak memory 191924 kb
Host smart-83468848-38df-4936-a625-10827d90db0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818156562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3818156562
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1946973145
Short name T229
Test name
Test status
Simulation time 24687246280 ps
CPU time 36.61 seconds
Started Jul 07 05:54:37 PM PDT 24
Finished Jul 07 05:55:14 PM PDT 24
Peak memory 191988 kb
Host smart-32c2d1a4-869e-4cb4-9878-eb122eb1f5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946973145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1946973145
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1032242642
Short name T15
Test name
Test status
Simulation time 5339524491 ps
CPU time 1.1 seconds
Started Jul 07 05:54:39 PM PDT 24
Finished Jul 07 05:54:40 PM PDT 24
Peak memory 215756 kb
Host smart-03539120-b5b8-4226-ae33-ab72719b1131
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032242642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1032242642
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.207563479
Short name T241
Test name
Test status
Simulation time 467648755 ps
CPU time 1.25 seconds
Started Jul 07 05:54:35 PM PDT 24
Finished Jul 07 05:54:36 PM PDT 24
Peak memory 191928 kb
Host smart-1a6ff800-7d26-42ed-ada2-d2d7bd9b9f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207563479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.207563479
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2568123357
Short name T226
Test name
Test status
Simulation time 29763159918 ps
CPU time 20.68 seconds
Started Jul 07 05:54:48 PM PDT 24
Finished Jul 07 05:55:10 PM PDT 24
Peak memory 196956 kb
Host smart-f1fe5d15-a344-460d-b258-fab44428e83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568123357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2568123357
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.389635284
Short name T253
Test name
Test status
Simulation time 583034156 ps
CPU time 0.68 seconds
Started Jul 07 05:54:47 PM PDT 24
Finished Jul 07 05:54:48 PM PDT 24
Peak memory 191924 kb
Host smart-b6cda0cc-383b-41b6-8496-288383c0de12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389635284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.389635284
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_jump.671575545
Short name T193
Test name
Test status
Simulation time 457642017 ps
CPU time 1.27 seconds
Started Jul 07 05:54:46 PM PDT 24
Finished Jul 07 05:54:48 PM PDT 24
Peak memory 196776 kb
Host smart-42a7560c-7684-4673-a1a1-da536513b4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671575545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.671575545
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.721597050
Short name T270
Test name
Test status
Simulation time 26758631590 ps
CPU time 2.68 seconds
Started Jul 07 05:54:46 PM PDT 24
Finished Jul 07 05:54:49 PM PDT 24
Peak memory 196984 kb
Host smart-8c76e101-d668-4aa1-8670-ff45efa750b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721597050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.721597050
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2701732567
Short name T240
Test name
Test status
Simulation time 410800273 ps
CPU time 1.22 seconds
Started Jul 07 05:54:50 PM PDT 24
Finished Jul 07 05:54:51 PM PDT 24
Peak memory 191920 kb
Host smart-7f0ed553-67a4-4f4f-aef1-0680f25d260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701732567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2701732567
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.265857869
Short name T225
Test name
Test status
Simulation time 27365285474 ps
CPU time 44.85 seconds
Started Jul 07 05:54:51 PM PDT 24
Finished Jul 07 05:55:36 PM PDT 24
Peak memory 191980 kb
Host smart-e31199bf-caea-4143-a640-045787e651b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265857869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.265857869
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1959429044
Short name T227
Test name
Test status
Simulation time 452183517 ps
CPU time 0.72 seconds
Started Jul 07 05:54:50 PM PDT 24
Finished Jul 07 05:54:51 PM PDT 24
Peak memory 196716 kb
Host smart-06c97ddc-5465-4aa8-8e4a-5b16e00c7a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959429044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1959429044
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2864692337
Short name T259
Test name
Test status
Simulation time 2828984614 ps
CPU time 1.66 seconds
Started Jul 07 05:54:54 PM PDT 24
Finished Jul 07 05:54:56 PM PDT 24
Peak memory 196796 kb
Host smart-99d209b9-c1ff-45c8-9666-9b3ed57d57cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864692337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2864692337
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1717932959
Short name T264
Test name
Test status
Simulation time 430913828 ps
CPU time 0.73 seconds
Started Jul 07 05:54:51 PM PDT 24
Finished Jul 07 05:54:52 PM PDT 24
Peak memory 191924 kb
Host smart-56ccc9b3-3b26-4f85-b602-0714b52dd6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717932959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1717932959
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.545519373
Short name T273
Test name
Test status
Simulation time 30205890418 ps
CPU time 4.9 seconds
Started Jul 07 05:54:50 PM PDT 24
Finished Jul 07 05:54:55 PM PDT 24
Peak memory 191944 kb
Host smart-0a0ecbdc-97d8-4b57-bb00-fd41a5bdbb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545519373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.545519373
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3116531801
Short name T13
Test name
Test status
Simulation time 476968969 ps
CPU time 0.77 seconds
Started Jul 07 05:54:55 PM PDT 24
Finished Jul 07 05:54:57 PM PDT 24
Peak memory 191908 kb
Host smart-950b1580-ea5c-4879-89aa-8ca2e1fa262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116531801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3116531801
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4141820814
Short name T189
Test name
Test status
Simulation time 456715162 ps
CPU time 0.64 seconds
Started Jul 07 05:54:57 PM PDT 24
Finished Jul 07 05:54:58 PM PDT 24
Peak memory 196784 kb
Host smart-258b49cc-546d-4d8e-b362-ea69062eda0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141820814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4141820814
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2083000823
Short name T212
Test name
Test status
Simulation time 5204950615 ps
CPU time 7.42 seconds
Started Jul 07 05:54:54 PM PDT 24
Finished Jul 07 05:55:02 PM PDT 24
Peak memory 196972 kb
Host smart-351123be-c390-4a67-9c5f-cdca45909668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083000823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2083000823
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.332260780
Short name T219
Test name
Test status
Simulation time 519430792 ps
CPU time 0.75 seconds
Started Jul 07 05:54:59 PM PDT 24
Finished Jul 07 05:55:00 PM PDT 24
Peak memory 191872 kb
Host smart-bb1b58c4-b6ef-4d35-a4b2-e7bb74609797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332260780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.332260780
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3058637281
Short name T5
Test name
Test status
Simulation time 49097383301 ps
CPU time 18.69 seconds
Started Jul 07 05:54:57 PM PDT 24
Finished Jul 07 05:55:16 PM PDT 24
Peak memory 196964 kb
Host smart-a5e4bae6-adc3-4691-ab28-a510b42990b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058637281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3058637281
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3350675358
Short name T256
Test name
Test status
Simulation time 494796097 ps
CPU time 1.28 seconds
Started Jul 07 05:54:58 PM PDT 24
Finished Jul 07 05:54:59 PM PDT 24
Peak memory 191828 kb
Host smart-f1b5d9ea-890a-41d8-9233-3d3898e2d63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350675358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3350675358
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2378559016
Short name T81
Test name
Test status
Simulation time 13221219022 ps
CPU time 3.88 seconds
Started Jul 07 05:54:56 PM PDT 24
Finished Jul 07 05:55:01 PM PDT 24
Peak memory 191984 kb
Host smart-cd00f3fb-761d-47f7-a42b-2c9d1f1ada36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378559016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2378559016
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.955522853
Short name T232
Test name
Test status
Simulation time 463358049 ps
CPU time 1.23 seconds
Started Jul 07 05:54:56 PM PDT 24
Finished Jul 07 05:54:58 PM PDT 24
Peak memory 191768 kb
Host smart-1ac106c4-8952-4c44-a054-cf43b5a41652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955522853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.955522853
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2117026464
Short name T262
Test name
Test status
Simulation time 23528442440 ps
CPU time 17.5 seconds
Started Jul 07 05:54:59 PM PDT 24
Finished Jul 07 05:55:16 PM PDT 24
Peak memory 196928 kb
Host smart-5543241e-a8bd-4385-b3cb-40b06ca10e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117026464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2117026464
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1297880940
Short name T67
Test name
Test status
Simulation time 528948345 ps
CPU time 0.94 seconds
Started Jul 07 05:54:56 PM PDT 24
Finished Jul 07 05:54:58 PM PDT 24
Peak memory 191792 kb
Host smart-8869fb6f-ec13-4e03-85a1-ea612969b2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297880940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1297880940
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.940917682
Short name T224
Test name
Test status
Simulation time 12062258725 ps
CPU time 19 seconds
Started Jul 07 05:54:55 PM PDT 24
Finished Jul 07 05:55:15 PM PDT 24
Peak memory 191964 kb
Host smart-1b43482c-5531-4460-b90d-cee9542900d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940917682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.940917682
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.4195751908
Short name T233
Test name
Test status
Simulation time 494489820 ps
CPU time 1.18 seconds
Started Jul 07 05:54:56 PM PDT 24
Finished Jul 07 05:54:58 PM PDT 24
Peak memory 191916 kb
Host smart-398dc6c0-dbc9-42ae-b558-5df82ca3a3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195751908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.4195751908
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3413691722
Short name T279
Test name
Test status
Simulation time 12428253857 ps
CPU time 10.11 seconds
Started Jul 07 05:54:37 PM PDT 24
Finished Jul 07 05:54:47 PM PDT 24
Peak memory 197000 kb
Host smart-fca8b69f-9ba5-481e-85c1-b7f725cca299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413691722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3413691722
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4205284422
Short name T16
Test name
Test status
Simulation time 8697112057 ps
CPU time 10.36 seconds
Started Jul 07 05:54:36 PM PDT 24
Finished Jul 07 05:54:46 PM PDT 24
Peak memory 215740 kb
Host smart-5ade6c5c-003d-4542-b9da-4d2e1d70dfdb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205284422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4205284422
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3458434046
Short name T243
Test name
Test status
Simulation time 516837195 ps
CPU time 0.75 seconds
Started Jul 07 05:54:39 PM PDT 24
Finished Jul 07 05:54:40 PM PDT 24
Peak memory 196776 kb
Host smart-216e4b6f-46cd-42fe-9c54-8188a4bb98ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458434046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3458434046
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.935510624
Short name T218
Test name
Test status
Simulation time 9027146594 ps
CPU time 88.76 seconds
Started Jul 07 05:54:36 PM PDT 24
Finished Jul 07 05:56:05 PM PDT 24
Peak memory 198644 kb
Host smart-4b870649-24e2-4526-89ee-495c2803cec8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935510624 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.935510624
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2561526180
Short name T44
Test name
Test status
Simulation time 8475683809 ps
CPU time 6.86 seconds
Started Jul 07 05:54:59 PM PDT 24
Finished Jul 07 05:55:06 PM PDT 24
Peak memory 191980 kb
Host smart-f3ad5a3c-3c98-4722-8115-ecf049b0826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561526180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2561526180
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2795399817
Short name T213
Test name
Test status
Simulation time 430538312 ps
CPU time 0.74 seconds
Started Jul 07 05:54:57 PM PDT 24
Finished Jul 07 05:54:58 PM PDT 24
Peak memory 191924 kb
Host smart-064db718-4e28-40ee-bfaf-252bcbfda49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795399817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2795399817
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.985317224
Short name T208
Test name
Test status
Simulation time 18078180038 ps
CPU time 2.99 seconds
Started Jul 07 05:54:58 PM PDT 24
Finished Jul 07 05:55:02 PM PDT 24
Peak memory 191852 kb
Host smart-c7ae91b3-278d-40f2-9183-3f41dd3758a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985317224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.985317224
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3618741578
Short name T247
Test name
Test status
Simulation time 486619848 ps
CPU time 1.37 seconds
Started Jul 07 05:55:03 PM PDT 24
Finished Jul 07 05:55:04 PM PDT 24
Peak memory 196736 kb
Host smart-ed4d54f9-a8d1-4bdd-b96a-474aea07fb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618741578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3618741578
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1815168404
Short name T280
Test name
Test status
Simulation time 3461438325 ps
CPU time 1.4 seconds
Started Jul 07 05:55:03 PM PDT 24
Finished Jul 07 05:55:04 PM PDT 24
Peak memory 191992 kb
Host smart-986f4983-e8f1-4b1b-8c6c-b86964fae8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815168404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1815168404
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.869907809
Short name T275
Test name
Test status
Simulation time 427808132 ps
CPU time 1 seconds
Started Jul 07 05:55:02 PM PDT 24
Finished Jul 07 05:55:03 PM PDT 24
Peak memory 191920 kb
Host smart-c0097333-78d6-4836-93c6-7aa7bb22f88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869907809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.869907809
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4170395002
Short name T10
Test name
Test status
Simulation time 28555834263 ps
CPU time 39.15 seconds
Started Jul 07 05:55:00 PM PDT 24
Finished Jul 07 05:55:39 PM PDT 24
Peak memory 191980 kb
Host smart-15b7e1a7-86f0-4308-82bd-0c15bb68daf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170395002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4170395002
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1817668254
Short name T265
Test name
Test status
Simulation time 507594556 ps
CPU time 0.76 seconds
Started Jul 07 05:55:05 PM PDT 24
Finished Jul 07 05:55:05 PM PDT 24
Peak memory 191848 kb
Host smart-d0f4da9e-a6ff-4f1b-84f0-184d307c2348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817668254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1817668254
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2040336510
Short name T276
Test name
Test status
Simulation time 4090038693 ps
CPU time 2.19 seconds
Started Jul 07 05:55:06 PM PDT 24
Finished Jul 07 05:55:08 PM PDT 24
Peak memory 191980 kb
Host smart-0ff124aa-a35f-4309-840b-df81aeb1e7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040336510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2040336510
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2476278167
Short name T239
Test name
Test status
Simulation time 436252118 ps
CPU time 0.88 seconds
Started Jul 07 05:55:07 PM PDT 24
Finished Jul 07 05:55:08 PM PDT 24
Peak memory 196640 kb
Host smart-136bc674-0683-401c-9250-e8743a9c0cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476278167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2476278167
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3229183622
Short name T22
Test name
Test status
Simulation time 13721176671 ps
CPU time 10.07 seconds
Started Jul 07 05:55:10 PM PDT 24
Finished Jul 07 05:55:20 PM PDT 24
Peak memory 196992 kb
Host smart-4f185903-b3d5-4004-bda9-aebccd415cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229183622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3229183622
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2436290404
Short name T238
Test name
Test status
Simulation time 384056199 ps
CPU time 0.83 seconds
Started Jul 07 05:55:06 PM PDT 24
Finished Jul 07 05:55:07 PM PDT 24
Peak memory 196752 kb
Host smart-a6c8868d-5d3d-4734-a100-c1b8de2fd394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436290404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2436290404
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2477375851
Short name T272
Test name
Test status
Simulation time 34424538531 ps
CPU time 53.14 seconds
Started Jul 07 05:55:06 PM PDT 24
Finished Jul 07 05:56:00 PM PDT 24
Peak memory 191988 kb
Host smart-a7667bdb-5ffc-43ec-9668-6f3964a85280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477375851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2477375851
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1556306102
Short name T237
Test name
Test status
Simulation time 571521525 ps
CPU time 1.35 seconds
Started Jul 07 05:55:10 PM PDT 24
Finished Jul 07 05:55:11 PM PDT 24
Peak memory 191916 kb
Host smart-0423d89a-83ca-41c8-951d-ec0afd50e6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556306102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1556306102
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1318357851
Short name T255
Test name
Test status
Simulation time 16291834353 ps
CPU time 20.48 seconds
Started Jul 07 05:55:14 PM PDT 24
Finished Jul 07 05:55:35 PM PDT 24
Peak memory 191980 kb
Host smart-f1ef73fa-4a44-469e-bebe-cf639bda143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318357851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1318357851
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2860600360
Short name T267
Test name
Test status
Simulation time 601961675 ps
CPU time 0.61 seconds
Started Jul 07 05:55:10 PM PDT 24
Finished Jul 07 05:55:11 PM PDT 24
Peak memory 196760 kb
Host smart-c4c8da20-5ac1-49b4-b933-37ef315f3b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860600360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2860600360
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1993138167
Short name T98
Test name
Test status
Simulation time 28331124418 ps
CPU time 38.61 seconds
Started Jul 07 05:55:13 PM PDT 24
Finished Jul 07 05:55:52 PM PDT 24
Peak memory 191996 kb
Host smart-0db34dd8-9db5-44e9-a9c5-1509d9dff000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993138167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1993138167
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1890446633
Short name T76
Test name
Test status
Simulation time 442522997 ps
CPU time 0.93 seconds
Started Jul 07 05:55:13 PM PDT 24
Finished Jul 07 05:55:14 PM PDT 24
Peak memory 191916 kb
Host smart-1e23ea7b-3d74-457a-89fe-a280490d13df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890446633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1890446633
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2939378635
Short name T269
Test name
Test status
Simulation time 30625060832 ps
CPU time 4.35 seconds
Started Jul 07 05:55:14 PM PDT 24
Finished Jul 07 05:55:19 PM PDT 24
Peak memory 196980 kb
Host smart-220a34ea-a75e-4bb9-b673-6a327f268543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939378635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2939378635
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1059937349
Short name T101
Test name
Test status
Simulation time 536338285 ps
CPU time 1.34 seconds
Started Jul 07 05:55:14 PM PDT 24
Finished Jul 07 05:55:16 PM PDT 24
Peak memory 191908 kb
Host smart-8d9a8212-7739-4575-817e-d936453dce0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059937349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1059937349
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.610339410
Short name T221
Test name
Test status
Simulation time 18352191562 ps
CPU time 27.38 seconds
Started Jul 07 05:54:39 PM PDT 24
Finished Jul 07 05:55:06 PM PDT 24
Peak memory 191980 kb
Host smart-37537e83-90d5-4c05-83c5-cc726449b3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610339410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.610339410
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1179440569
Short name T17
Test name
Test status
Simulation time 8144304055 ps
CPU time 2.69 seconds
Started Jul 07 05:54:39 PM PDT 24
Finished Jul 07 05:54:42 PM PDT 24
Peak memory 215840 kb
Host smart-8f64dab4-e67c-492d-a607-a7c515504700
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179440569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1179440569
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3253148762
Short name T235
Test name
Test status
Simulation time 490928401 ps
CPU time 0.62 seconds
Started Jul 07 05:54:44 PM PDT 24
Finished Jul 07 05:54:45 PM PDT 24
Peak memory 191896 kb
Host smart-b81c414f-4a38-49d6-b0af-17a2f789c5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253148762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3253148762
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1171582641
Short name T216
Test name
Test status
Simulation time 27926184440 ps
CPU time 4.24 seconds
Started Jul 07 05:55:15 PM PDT 24
Finished Jul 07 05:55:20 PM PDT 24
Peak memory 191984 kb
Host smart-5fef8c14-4f3d-458a-8c45-a29380237548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171582641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1171582641
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1299336376
Short name T282
Test name
Test status
Simulation time 491499649 ps
CPU time 0.78 seconds
Started Jul 07 05:55:16 PM PDT 24
Finished Jul 07 05:55:17 PM PDT 24
Peak memory 196724 kb
Host smart-cb5a5931-9646-477d-bac1-e9f7502655fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299336376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1299336376
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3887640973
Short name T261
Test name
Test status
Simulation time 48870611186 ps
CPU time 35.2 seconds
Started Jul 07 05:55:13 PM PDT 24
Finished Jul 07 05:55:48 PM PDT 24
Peak memory 191948 kb
Host smart-9e74cc2b-2d2c-4078-971d-5945b52b4c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887640973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3887640973
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2232901976
Short name T236
Test name
Test status
Simulation time 429808438 ps
CPU time 1.18 seconds
Started Jul 07 05:55:12 PM PDT 24
Finished Jul 07 05:55:13 PM PDT 24
Peak memory 196696 kb
Host smart-0364db3a-0254-460f-a848-add0fddef26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232901976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2232901976
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3689313645
Short name T231
Test name
Test status
Simulation time 9044769636 ps
CPU time 3.51 seconds
Started Jul 07 05:55:26 PM PDT 24
Finished Jul 07 05:55:29 PM PDT 24
Peak memory 191972 kb
Host smart-bc1bd3a2-8265-4ffa-95f2-65f82eb56435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689313645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3689313645
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2107778096
Short name T251
Test name
Test status
Simulation time 611626925 ps
CPU time 0.75 seconds
Started Jul 07 05:55:26 PM PDT 24
Finished Jul 07 05:55:27 PM PDT 24
Peak memory 191916 kb
Host smart-89d0244e-9835-4676-9147-b4498a9c68c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107778096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2107778096
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2754301740
Short name T278
Test name
Test status
Simulation time 14596528622 ps
CPU time 8.01 seconds
Started Jul 07 05:55:17 PM PDT 24
Finished Jul 07 05:55:26 PM PDT 24
Peak memory 191988 kb
Host smart-6cb45d61-4e65-47bc-acfd-6fe3b2637a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754301740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2754301740
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1033098563
Short name T215
Test name
Test status
Simulation time 403250420 ps
CPU time 1.14 seconds
Started Jul 07 05:55:16 PM PDT 24
Finished Jul 07 05:55:17 PM PDT 24
Peak memory 191936 kb
Host smart-012b7cd9-dc3f-4b10-bf28-b3995efaf311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033098563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1033098563
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3342083060
Short name T3
Test name
Test status
Simulation time 372176951 ps
CPU time 0.84 seconds
Started Jul 07 05:55:19 PM PDT 24
Finished Jul 07 05:55:20 PM PDT 24
Peak memory 196712 kb
Host smart-fbe7fee0-183d-4f3c-a78b-19995b31ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342083060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3342083060
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2999131832
Short name T244
Test name
Test status
Simulation time 36427919748 ps
CPU time 49.96 seconds
Started Jul 07 05:55:19 PM PDT 24
Finished Jul 07 05:56:10 PM PDT 24
Peak memory 196976 kb
Host smart-d80668cf-b9b5-47ee-b598-b4bdf10dbd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999131832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2999131832
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3929953096
Short name T242
Test name
Test status
Simulation time 446689080 ps
CPU time 1.24 seconds
Started Jul 07 05:55:17 PM PDT 24
Finished Jul 07 05:55:19 PM PDT 24
Peak memory 196784 kb
Host smart-365414e3-f8bd-4e0d-bc18-892e44e492ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929953096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3929953096
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1977741569
Short name T210
Test name
Test status
Simulation time 19512469399 ps
CPU time 7.58 seconds
Started Jul 07 05:55:21 PM PDT 24
Finished Jul 07 05:55:29 PM PDT 24
Peak memory 191972 kb
Host smart-a9e012d0-4ea5-4645-9bfa-b303168dad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977741569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1977741569
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1216052505
Short name T263
Test name
Test status
Simulation time 536670773 ps
CPU time 1.02 seconds
Started Jul 07 05:55:19 PM PDT 24
Finished Jul 07 05:55:20 PM PDT 24
Peak memory 191912 kb
Host smart-32cbd86d-f050-476f-b327-903d117144f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216052505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1216052505
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2649755150
Short name T97
Test name
Test status
Simulation time 35556814623 ps
CPU time 49.88 seconds
Started Jul 07 05:55:26 PM PDT 24
Finished Jul 07 05:56:16 PM PDT 24
Peak memory 191968 kb
Host smart-0492a97c-3c29-4767-9e52-57bef4713419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649755150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2649755150
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1448931775
Short name T250
Test name
Test status
Simulation time 514573606 ps
CPU time 0.8 seconds
Started Jul 07 05:55:19 PM PDT 24
Finished Jul 07 05:55:20 PM PDT 24
Peak memory 191920 kb
Host smart-87e2302c-1e72-485a-b61f-e968635418aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448931775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1448931775
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1095316772
Short name T28
Test name
Test status
Simulation time 34206103024 ps
CPU time 43.71 seconds
Started Jul 07 05:55:18 PM PDT 24
Finished Jul 07 05:56:02 PM PDT 24
Peak memory 191980 kb
Host smart-b2a34547-81c4-458e-b1ce-4cbec4add2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095316772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1095316772
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2097394728
Short name T207
Test name
Test status
Simulation time 589382134 ps
CPU time 0.79 seconds
Started Jul 07 05:55:25 PM PDT 24
Finished Jul 07 05:55:26 PM PDT 24
Peak memory 191868 kb
Host smart-ee2cd47f-216f-43de-b237-8e398aea080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097394728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2097394728
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1099651215
Short name T252
Test name
Test status
Simulation time 91547658108 ps
CPU time 140.77 seconds
Started Jul 07 05:55:23 PM PDT 24
Finished Jul 07 05:57:44 PM PDT 24
Peak memory 191980 kb
Host smart-9bb9e4d4-f307-4ab7-acf9-1e4987f923c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099651215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1099651215
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2081970740
Short name T211
Test name
Test status
Simulation time 24901849234 ps
CPU time 34.26 seconds
Started Jul 07 05:55:23 PM PDT 24
Finished Jul 07 05:55:58 PM PDT 24
Peak memory 191964 kb
Host smart-21830532-0d7f-4513-8b03-e998fe9f5b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081970740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2081970740
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1281694258
Short name T29
Test name
Test status
Simulation time 406087502 ps
CPU time 0.76 seconds
Started Jul 07 05:55:27 PM PDT 24
Finished Jul 07 05:55:28 PM PDT 24
Peak memory 191920 kb
Host smart-bb189963-e27b-4419-8f1b-74d7983298a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281694258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1281694258
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2917625223
Short name T277
Test name
Test status
Simulation time 55111471702 ps
CPU time 67.62 seconds
Started Jul 07 05:55:23 PM PDT 24
Finished Jul 07 05:56:31 PM PDT 24
Peak memory 191992 kb
Host smart-31fde0f2-318d-46f0-ac58-4977ca0bf9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917625223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2917625223
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3880009596
Short name T249
Test name
Test status
Simulation time 520759225 ps
CPU time 0.77 seconds
Started Jul 07 05:55:23 PM PDT 24
Finished Jul 07 05:55:24 PM PDT 24
Peak memory 196628 kb
Host smart-f15d701e-7b88-49ad-9c3b-0338dae8e7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880009596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3880009596
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3856304658
Short name T4
Test name
Test status
Simulation time 13906292885 ps
CPU time 21.88 seconds
Started Jul 07 05:54:42 PM PDT 24
Finished Jul 07 05:55:05 PM PDT 24
Peak memory 192000 kb
Host smart-3e11b144-6e78-40bd-8168-bef6a456b333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856304658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3856304658
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.300987306
Short name T21
Test name
Test status
Simulation time 4583766882 ps
CPU time 5.19 seconds
Started Jul 07 05:54:42 PM PDT 24
Finished Jul 07 05:54:47 PM PDT 24
Peak memory 215644 kb
Host smart-f30c69e2-670a-4f3b-8920-9ad556bbe686
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300987306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.300987306
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.728968908
Short name T78
Test name
Test status
Simulation time 454110124 ps
CPU time 1.17 seconds
Started Jul 07 05:54:40 PM PDT 24
Finished Jul 07 05:54:41 PM PDT 24
Peak memory 191924 kb
Host smart-3ce374dd-0142-4782-9790-71d4a0a577af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728968908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.728968908
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3086241211
Short name T268
Test name
Test status
Simulation time 41203679624 ps
CPU time 28.92 seconds
Started Jul 07 05:55:28 PM PDT 24
Finished Jul 07 05:55:57 PM PDT 24
Peak memory 191924 kb
Host smart-c2b53aea-e8bf-44db-a23d-f3505e53475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086241211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3086241211
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.200567959
Short name T73
Test name
Test status
Simulation time 472702300 ps
CPU time 1.22 seconds
Started Jul 07 05:55:26 PM PDT 24
Finished Jul 07 05:55:27 PM PDT 24
Peak memory 191928 kb
Host smart-53cd9ced-39e0-49b6-b07a-3a1b5b80b90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200567959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.200567959
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3840169046
Short name T93
Test name
Test status
Simulation time 37441149213 ps
CPU time 311.38 seconds
Started Jul 07 05:55:28 PM PDT 24
Finished Jul 07 06:00:39 PM PDT 24
Peak memory 206852 kb
Host smart-15d2779b-948e-4d6c-ad82-a1c5128b6e29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840169046 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3840169046
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3614414545
Short name T204
Test name
Test status
Simulation time 14898238347 ps
CPU time 22.17 seconds
Started Jul 07 05:55:26 PM PDT 24
Finished Jul 07 05:55:49 PM PDT 24
Peak memory 191944 kb
Host smart-d4588ffa-2655-4ba9-ad95-971ed5fb4af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614414545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3614414545
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2377518807
Short name T254
Test name
Test status
Simulation time 565763545 ps
CPU time 0.63 seconds
Started Jul 07 05:55:26 PM PDT 24
Finished Jul 07 05:55:27 PM PDT 24
Peak memory 191924 kb
Host smart-4b868ce9-4c17-4a18-9d62-6f76b27a6762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377518807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2377518807
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.893270089
Short name T257
Test name
Test status
Simulation time 50327896245 ps
CPU time 34.4 seconds
Started Jul 07 05:55:30 PM PDT 24
Finished Jul 07 05:56:04 PM PDT 24
Peak memory 191948 kb
Host smart-a41b2181-005b-4f0a-a0a2-2bc7fc95a9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893270089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.893270089
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.653980561
Short name T214
Test name
Test status
Simulation time 540968319 ps
CPU time 0.79 seconds
Started Jul 07 05:55:31 PM PDT 24
Finished Jul 07 05:55:32 PM PDT 24
Peak memory 191900 kb
Host smart-de4963a5-1e8c-4f41-a299-f6b7ecc942da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653980561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.653980561
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3450124270
Short name T271
Test name
Test status
Simulation time 4298147875 ps
CPU time 2.34 seconds
Started Jul 07 05:55:29 PM PDT 24
Finished Jul 07 05:55:31 PM PDT 24
Peak memory 196788 kb
Host smart-bfe352fd-5b95-4a6b-a34e-1dc2715f1355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450124270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3450124270
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.136534826
Short name T72
Test name
Test status
Simulation time 363755284 ps
CPU time 1.04 seconds
Started Jul 07 05:55:33 PM PDT 24
Finished Jul 07 05:55:34 PM PDT 24
Peak memory 196608 kb
Host smart-978c8ac3-3e1e-48a0-959a-258b6de846a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136534826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.136534826
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.26057144
Short name T209
Test name
Test status
Simulation time 60474830775 ps
CPU time 20.77 seconds
Started Jul 07 05:55:38 PM PDT 24
Finished Jul 07 05:55:59 PM PDT 24
Peak memory 196980 kb
Host smart-4979e372-bcfa-4f55-ad14-89ab1596c8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26057144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.26057144
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2055757591
Short name T45
Test name
Test status
Simulation time 625560400 ps
CPU time 0.81 seconds
Started Jul 07 05:55:39 PM PDT 24
Finished Jul 07 05:55:40 PM PDT 24
Peak memory 196736 kb
Host smart-16aeace0-6d77-4029-b497-4e79e87a2916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055757591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2055757591
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3535423068
Short name T266
Test name
Test status
Simulation time 50655303206 ps
CPU time 204.59 seconds
Started Jul 07 05:55:30 PM PDT 24
Finished Jul 07 05:58:54 PM PDT 24
Peak memory 206872 kb
Host smart-aa316a9d-88ae-411f-a4d6-851e86c53283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535423068 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3535423068
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2058689152
Short name T194
Test name
Test status
Simulation time 542189873 ps
CPU time 1.4 seconds
Started Jul 07 05:55:34 PM PDT 24
Finished Jul 07 05:55:36 PM PDT 24
Peak memory 196580 kb
Host smart-ef859d71-4c2f-48d4-83f0-baeacfd141c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058689152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2058689152
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1713828777
Short name T222
Test name
Test status
Simulation time 6388152396 ps
CPU time 9.92 seconds
Started Jul 07 05:55:29 PM PDT 24
Finished Jul 07 05:55:39 PM PDT 24
Peak memory 191976 kb
Host smart-dcdc8dad-8949-47e2-82a3-fb684297f258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713828777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1713828777
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2011695571
Short name T228
Test name
Test status
Simulation time 442266145 ps
CPU time 0.75 seconds
Started Jul 07 05:55:30 PM PDT 24
Finished Jul 07 05:55:31 PM PDT 24
Peak memory 191928 kb
Host smart-9e8d8987-3feb-43c7-9dc1-3aeb6c00d089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011695571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2011695571
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2397903390
Short name T170
Test name
Test status
Simulation time 594471995 ps
CPU time 1 seconds
Started Jul 07 05:55:37 PM PDT 24
Finished Jul 07 05:55:38 PM PDT 24
Peak memory 196576 kb
Host smart-729dfe35-5026-4008-9caa-da227a6581bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397903390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2397903390
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1716766348
Short name T234
Test name
Test status
Simulation time 5567403692 ps
CPU time 2.41 seconds
Started Jul 07 05:55:34 PM PDT 24
Finished Jul 07 05:55:37 PM PDT 24
Peak memory 191924 kb
Host smart-fc7d6dc2-7642-4650-83c0-bb7698dcc9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716766348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1716766348
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3637688157
Short name T100
Test name
Test status
Simulation time 466092583 ps
CPU time 1.26 seconds
Started Jul 07 05:55:36 PM PDT 24
Finished Jul 07 05:55:37 PM PDT 24
Peak memory 191776 kb
Host smart-93c84dc4-6b9d-4d8c-8284-a67f8f2cf15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637688157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3637688157
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1332300401
Short name T30
Test name
Test status
Simulation time 20665717918 ps
CPU time 4.67 seconds
Started Jul 07 05:55:36 PM PDT 24
Finished Jul 07 05:55:41 PM PDT 24
Peak memory 191960 kb
Host smart-3b368e01-c95d-4cd6-ab61-640bd599b059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332300401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1332300401
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.460694268
Short name T245
Test name
Test status
Simulation time 364443645 ps
CPU time 0.67 seconds
Started Jul 07 05:55:35 PM PDT 24
Finished Jul 07 05:55:36 PM PDT 24
Peak memory 191896 kb
Host smart-2dc0d713-c527-4abd-9e67-1d3f410999ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460694268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.460694268
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4089822946
Short name T220
Test name
Test status
Simulation time 33814381408 ps
CPU time 22.18 seconds
Started Jul 07 05:55:47 PM PDT 24
Finished Jul 07 05:56:10 PM PDT 24
Peak memory 191904 kb
Host smart-00533e38-cf13-414a-8071-4e224d37d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089822946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4089822946
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.339054580
Short name T223
Test name
Test status
Simulation time 693256916 ps
CPU time 0.67 seconds
Started Jul 07 05:55:45 PM PDT 24
Finished Jul 07 05:55:46 PM PDT 24
Peak memory 196704 kb
Host smart-872d7724-8098-4d65-a8f4-c62c7aed59ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339054580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.339054580
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.607467256
Short name T283
Test name
Test status
Simulation time 681225925 ps
CPU time 1.51 seconds
Started Jul 07 05:55:37 PM PDT 24
Finished Jul 07 05:55:39 PM PDT 24
Peak memory 191884 kb
Host smart-14b58ab7-f9a0-482a-b535-333c8217672f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607467256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.607467256
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4028340234
Short name T71
Test name
Test status
Simulation time 381791254 ps
CPU time 1.04 seconds
Started Jul 07 05:55:42 PM PDT 24
Finished Jul 07 05:55:43 PM PDT 24
Peak memory 191916 kb
Host smart-d29a66ca-0258-4597-9e3c-cbf6556ecfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028340234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4028340234
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2180626727
Short name T274
Test name
Test status
Simulation time 29892932299 ps
CPU time 23.86 seconds
Started Jul 07 05:54:42 PM PDT 24
Finished Jul 07 05:55:06 PM PDT 24
Peak memory 191952 kb
Host smart-1b7c08b3-fdc7-483e-bd67-8057111b5edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180626727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2180626727
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1001334372
Short name T260
Test name
Test status
Simulation time 578383086 ps
CPU time 1.46 seconds
Started Jul 07 05:54:49 PM PDT 24
Finished Jul 07 05:54:51 PM PDT 24
Peak memory 191920 kb
Host smart-69140a69-8b54-4c44-a90a-50944848002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001334372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1001334372
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3200074168
Short name T77
Test name
Test status
Simulation time 36918378603 ps
CPU time 14.28 seconds
Started Jul 07 05:54:49 PM PDT 24
Finished Jul 07 05:55:04 PM PDT 24
Peak memory 191984 kb
Host smart-e5574241-60cd-49b4-94c6-149949df598e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200074168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3200074168
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1186151788
Short name T27
Test name
Test status
Simulation time 489273033 ps
CPU time 0.71 seconds
Started Jul 07 05:54:47 PM PDT 24
Finished Jul 07 05:54:48 PM PDT 24
Peak memory 196752 kb
Host smart-aca33ac3-7719-4121-85ce-893aca38b300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186151788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1186151788
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3851449329
Short name T2
Test name
Test status
Simulation time 1335005222 ps
CPU time 2.53 seconds
Started Jul 07 05:54:47 PM PDT 24
Finished Jul 07 05:54:50 PM PDT 24
Peak memory 191796 kb
Host smart-96730de9-6ee8-455e-8beb-6e25581b5eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851449329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3851449329
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.33122195
Short name T217
Test name
Test status
Simulation time 513505564 ps
CPU time 0.91 seconds
Started Jul 07 05:54:42 PM PDT 24
Finished Jul 07 05:54:43 PM PDT 24
Peak memory 191868 kb
Host smart-2ce1a57b-8e4b-49db-88e1-7a3fd262835a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33122195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.33122195
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1546945905
Short name T258
Test name
Test status
Simulation time 60282348339 ps
CPU time 89.46 seconds
Started Jul 07 05:54:44 PM PDT 24
Finished Jul 07 05:56:13 PM PDT 24
Peak memory 191980 kb
Host smart-ee86d559-96c9-45d4-9b22-a2ed69ee014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546945905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1546945905
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2055570060
Short name T23
Test name
Test status
Simulation time 465954168 ps
CPU time 1.14 seconds
Started Jul 07 05:54:41 PM PDT 24
Finished Jul 07 05:54:42 PM PDT 24
Peak memory 191908 kb
Host smart-834b6491-0298-4d1e-80aa-8ca4391ae828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055570060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2055570060
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3033926996
Short name T281
Test name
Test status
Simulation time 9473493294 ps
CPU time 15.25 seconds
Started Jul 07 05:54:45 PM PDT 24
Finished Jul 07 05:55:00 PM PDT 24
Peak memory 191928 kb
Host smart-d423fd0b-541a-4739-a778-158efc027593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033926996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3033926996
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1012460804
Short name T246
Test name
Test status
Simulation time 521364940 ps
CPU time 0.73 seconds
Started Jul 07 05:54:49 PM PDT 24
Finished Jul 07 05:54:50 PM PDT 24
Peak memory 191856 kb
Host smart-c78e3ed3-ec90-401a-825c-a5d3bf0507ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012460804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1012460804
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1082374396
Short name T190
Test name
Test status
Simulation time 45289475611 ps
CPU time 259.72 seconds
Started Jul 07 05:54:50 PM PDT 24
Finished Jul 07 05:59:10 PM PDT 24
Peak memory 206784 kb
Host smart-cf95db56-c27e-4511-a446-ca6948c146e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082374396 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1082374396
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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