Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	32149	1		T1	12		T2	11		T3	12
bark[1]	406	1		T97	21		T88	21		T105	184
bark[2]	594	1		T10	33		T97	21		T98	211
bark[3]	133	1		T27	21		T113	21		T55	14
bark[4]	544	1		T14	14		T176	14		T111	21
bark[5]	515	1		T8	14		T21	42		T35	21
bark[6]	990	1		T7	249		T43	44		T56	85
bark[7]	1034	1		T46	14		T44	140		T101	21
bark[8]	358	1		T28	7		T179	26		T43	21
bark[9]	623	1		T15	21		T88	468		T89	14
bark[10]	130	1		T32	48		T147	26		T88	35
bark[11]	457	1		T32	35		T111	35		T168	69
bark[12]	178	1		T20	14		T22	47		T35	21
bark[13]	1016	1		T178	14		T46	57		T97	199
bark[14]	493	1		T23	14		T26	191		T172	14
bark[15]	671	1		T20	21		T42	43		T44	94
bark[16]	518	1		T7	21		T20	21		T105	261
bark[17]	563	1		T10	26		T43	127		T50	36
bark[18]	410	1		T22	21		T135	14		T180	14
bark[19]	633	1		T7	71		T141	14		T137	14
bark[20]	719	1		T20	21		T43	35		T44	294
bark[21]	489	1		T21	21		T26	40		T27	21
bark[22]	158	1		T7	5		T147	21		T47	21
bark[23]	208	1		T111	91		T151	14		T120	14
bark[24]	634	1		T29	14		T133	14		T168	110
bark[25]	286	1		T32	21		T98	21		T85	179
bark[26]	301	1		T15	26		T20	21		T146	21
bark[27]	566	1		T4	14		T7	21		T34	14
bark[28]	287	1		T20	21		T103	21		T111	43
bark[29]	565	1		T111	83		T50	5		T108	21
bark[30]	422	1		T7	21		T179	52		T159	14
bark[31]	287	1		T44	21		T105	21		T140	30
bark_0	4389	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	31602	1		T1	11		T2	10		T3	11
bite[1]	393	1		T7	21		T10	32		T35	21
bite[2]	473	1		T7	25		T28	19		T42	42
bite[3]	819	1		T20	21		T22	26		T32	21
bite[4]	636	1		T7	63		T22	21		T103	21
bite[5]	370	1		T20	21		T44	63		T97	21
bite[6]	207	1		T14	13		T101	21		T113	21
bite[7]	328	1		T21	21		T26	190		T47	21
bite[8]	261	1		T4	13		T15	25		T179	26
bite[9]	151	1		T20	21		T113	22		T126	13
bite[10]	394	1		T105	237		T167	42		T173	47
bite[11]	658	1		T10	25		T35	21		T50	141
bite[12]	565	1		T15	21		T20	21		T29	13
bite[13]	357	1		T8	13		T20	21		T32	48
bite[14]	632	1		T137	13		T55	13		T123	173
bite[15]	889	1		T27	21		T146	21		T97	21
bite[16]	689	1		T176	13		T133	13		T111	69
bite[17]	819	1		T7	21		T97	219		T168	109
bite[18]	432	1		T32	35		T141	13		T103	42
bite[19]	634	1		T22	21		T101	21		T108	21
bite[20]	501	1		T34	13		T179	52		T103	26
bite[21]	834	1		T32	21		T135	13		T43	35
bite[22]	637	1		T21	21		T44	293		T85	178
bite[23]	602	1		T26	40		T113	21		T98	210
bite[24]	316	1		T21	21		T99	26		T144	201
bite[25]	143	1		T111	42		T123	25		T98	21
bite[26]	266	1		T46	13		T88	21		T128	21
bite[27]	629	1		T7	248		T35	21		T43	126
bite[28]	397	1		T23	13		T189	13		T85	21
bite[29]	259	1		T7	6		T147	21		T127	21
bite[30]	588	1		T20	13		T178	13		T46	57
bite[31]	341	1		T27	21		T159	13		T51	40
bite_0	4904	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40425	1		T1	19		T2	11		T3	19
auto[1]	11301	1		T2	7		T5	7		T6	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1238	1		T1	9		T21	19		T103	33
prescale[1]	1330	1		T7	24		T26	53		T27	135
prescale[2]	686	1		T27	28		T42	2		T197	9
prescale[3]	685	1		T43	64		T146	44		T103	19
prescale[4]	605	1		T12	9		T22	40		T44	2
prescale[5]	986	1		T21	36		T27	9		T28	2
prescale[6]	878	1		T7	56		T26	45		T32	88
prescale[7]	690	1		T7	2		T35	59		T43	9
prescale[8]	861	1		T35	32		T43	2		T44	61
prescale[9]	837	1		T20	62		T27	30		T179	19
prescale[10]	841	1		T7	116		T26	2		T27	19
prescale[11]	714	1		T26	2		T28	2		T179	19
prescale[12]	1203	1		T21	42		T26	71		T43	2
prescale[13]	1120	1		T46	45		T179	9		T103	19
prescale[14]	1047	1		T26	36		T42	37		T43	2
prescale[15]	897	1		T21	23		T27	26		T28	2
prescale[16]	899	1		T7	30		T43	9		T97	30
prescale[17]	957	1		T10	2		T43	184		T198	9
prescale[18]	964	1		T7	116		T21	40		T46	23
prescale[19]	288	1		T3	9		T7	11		T11	9
prescale[20]	686	1		T15	2		T20	61		T27	60
prescale[21]	582	1		T10	9		T28	2		T179	19
prescale[22]	1490	1		T15	2		T35	19		T199	9
prescale[23]	1007	1		T7	2		T27	144		T35	36
prescale[24]	796	1		T15	2		T27	2		T47	37
prescale[25]	816	1		T27	48		T44	57		T147	40
prescale[26]	880	1		T15	2		T35	57		T200	9
prescale[27]	1117	1		T7	2		T16	9		T26	55
prescale[28]	468	1		T10	2		T42	2		T43	19
prescale[29]	1081	1		T7	132		T10	2		T27	84
prescale[30]	926	1		T26	75		T101	44		T111	109
prescale[31]	914	1		T10	28		T15	2		T21	62
prescale_0	23237	1		T1	10		T2	18		T3	10

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39546	1		T1	9		T2	9		T3	9
auto[1]	12180	1		T1	10		T2	9		T3	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51726	1		T1	19		T2	18		T3	19

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30435	1		T1	14		T2	13		T3	14
wkup[1]	237	1		T7	21		T87	30		T88	30
wkup[2]	306	1		T43	21		T113	21		T51	26
wkup[3]	197	1		T35	8		T97	21		T108	21
wkup[4]	272	1		T135	15		T97	21		T47	26
wkup[5]	260	1		T7	21		T32	21		T111	21
wkup[6]	246	1		T14	15		T21	21		T123	21
wkup[7]	323	1		T20	21		T103	21		T47	21
wkup[8]	228	1		T7	21		T21	21		T46	42
wkup[9]	343	1		T141	15		T103	26		T97	36
wkup[10]	318	1		T7	21		T20	21		T26	21
wkup[11]	378	1		T22	21		T43	35		T44	8
wkup[12]	191	1		T27	36		T147	26		T101	15
wkup[13]	325	1		T7	6		T44	21		T111	56
wkup[14]	187	1		T123	21		T125	15		T85	21
wkup[15]	516	1		T146	21		T101	21		T111	21
wkup[16]	332	1		T26	15		T35	26		T47	89
wkup[17]	239	1		T32	35		T111	30		T97	30
wkup[18]	234	1		T35	21		T111	30		T82	42
wkup[19]	317	1		T7	21		T22	21		T44	21
wkup[20]	368	1		T43	21		T44	21		T111	42
wkup[21]	332	1		T4	15		T20	21		T27	21
wkup[22]	356	1		T35	21		T44	21		T111	52
wkup[23]	393	1		T21	21		T27	26		T46	21
wkup[24]	306	1		T7	42		T15	21		T27	21
wkup[25]	218	1		T103	21		T111	26		T84	21
wkup[26]	280	1		T179	31		T50	21		T82	21
wkup[27]	436	1		T35	21		T111	21		T113	21
wkup[28]	284	1		T32	21		T44	26		T47	21
wkup[29]	113	1		T99	21		T144	26		T119	21
wkup[30]	246	1		T7	21		T44	21		T147	21
wkup[31]	293	1		T27	21		T43	21		T159	15
wkup[32]	108	1		T111	15		T47	30		T51	21
wkup[33]	375	1		T7	21		T44	21		T101	21
wkup[34]	224	1		T20	15		T27	21		T47	21
wkup[35]	283	1		T44	26		T123	21		T105	21
wkup[36]	171	1		T180	15		T47	42		T85	21
wkup[37]	250	1		T27	21		T43	21		T47	35
wkup[38]	301	1		T7	21		T20	21		T35	21
wkup[39]	276	1		T7	21		T20	21		T179	26
wkup[40]	244	1		T44	21		T147	21		T168	26
wkup[41]	367	1		T7	8		T35	30		T146	26
wkup[42]	268	1		T179	21		T43	44		T85	44
wkup[43]	366	1		T133	15		T101	21		T47	47
wkup[44]	319	1		T7	26		T15	21		T26	21
wkup[45]	247	1		T10	21		T35	21		T43	21
wkup[46]	374	1		T7	42		T26	40		T111	21
wkup[47]	228	1		T26	45		T29	15		T98	21
wkup[48]	242	1		T34	15		T32	21		T35	30
wkup[49]	339	1		T44	21		T103	26		T47	21
wkup[50]	228	1		T35	21		T44	21		T103	21
wkup[51]	235	1		T7	42		T97	15		T119	35
wkup[52]	198	1		T10	21		T44	21		T105	21
wkup[53]	227	1		T27	21		T35	21		T43	26
wkup[54]	274	1		T44	30		T111	21		T175	15
wkup[55]	217	1		T111	21		T113	21		T50	21
wkup[56]	317	1		T20	21		T28	8		T147	21
wkup[57]	194	1		T21	21		T22	21		T47	21
wkup[58]	228	1		T26	21		T85	21		T116	21
wkup[59]	381	1		T26	26		T42	21		T43	15
wkup[60]	231	1		T23	15		T178	15		T43	26
wkup[61]	340	1		T111	21		T50	6		T56	21
wkup[62]	444	1		T7	21		T20	21		T26	15
wkup[63]	246	1		T43	21		T44	21		T85	15
wkup_0	3475	1		T1	5		T2	5		T3	5