Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.89 99.33 93.67 100.00 98.40 99.51 48.44


Total test records in report: 418
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T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2726195452 Jul 09 06:23:11 PM PDT 24 Jul 09 06:23:13 PM PDT 24 1064177802 ps
T61 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2532163445 Jul 09 06:23:55 PM PDT 24 Jul 09 06:23:56 PM PDT 24 516622626 ps
T38 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1629237790 Jul 09 06:23:31 PM PDT 24 Jul 09 06:23:33 PM PDT 24 580634212 ps
T39 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2714828251 Jul 09 06:24:05 PM PDT 24 Jul 09 06:24:07 PM PDT 24 4584647231 ps
T280 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3925732395 Jul 09 06:22:49 PM PDT 24 Jul 09 06:22:50 PM PDT 24 432473934 ps
T281 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2819993805 Jul 09 06:24:01 PM PDT 24 Jul 09 06:24:02 PM PDT 24 396585724 ps
T282 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4013878994 Jul 09 06:23:25 PM PDT 24 Jul 09 06:23:26 PM PDT 24 427229959 ps
T74 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.915300730 Jul 09 06:23:33 PM PDT 24 Jul 09 06:23:35 PM PDT 24 330655586 ps
T75 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.41098235 Jul 09 06:22:51 PM PDT 24 Jul 09 06:22:58 PM PDT 24 2714477838 ps
T283 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3481485896 Jul 09 06:24:02 PM PDT 24 Jul 09 06:24:03 PM PDT 24 348808982 ps
T284 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.620564708 Jul 09 06:23:44 PM PDT 24 Jul 09 06:23:46 PM PDT 24 511900792 ps
T285 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2499357315 Jul 09 06:23:38 PM PDT 24 Jul 09 06:23:39 PM PDT 24 308202690 ps
T286 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1542846421 Jul 09 06:23:32 PM PDT 24 Jul 09 06:23:34 PM PDT 24 607448117 ps
T287 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1758906118 Jul 09 06:23:31 PM PDT 24 Jul 09 06:23:34 PM PDT 24 336982784 ps
T40 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3389301040 Jul 09 06:23:37 PM PDT 24 Jul 09 06:23:39 PM PDT 24 8284832980 ps
T288 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1874829525 Jul 09 06:23:36 PM PDT 24 Jul 09 06:23:39 PM PDT 24 615313699 ps
T289 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3181790368 Jul 09 06:23:30 PM PDT 24 Jul 09 06:23:32 PM PDT 24 366676679 ps
T76 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3628732387 Jul 09 06:23:44 PM PDT 24 Jul 09 06:23:46 PM PDT 24 469781598 ps
T290 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2016927860 Jul 09 06:23:00 PM PDT 24 Jul 09 06:23:01 PM PDT 24 428295543 ps
T62 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2335948169 Jul 09 06:22:51 PM PDT 24 Jul 09 06:22:57 PM PDT 24 13261389659 ps
T291 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3839759598 Jul 09 06:24:01 PM PDT 24 Jul 09 06:24:02 PM PDT 24 398305465 ps
T292 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4173909639 Jul 09 06:23:28 PM PDT 24 Jul 09 06:23:29 PM PDT 24 532349462 ps
T77 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3525978551 Jul 09 06:23:25 PM PDT 24 Jul 09 06:23:27 PM PDT 24 1643071937 ps
T293 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1223841260 Jul 09 06:23:27 PM PDT 24 Jul 09 06:23:28 PM PDT 24 325586012 ps
T294 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3602508818 Jul 09 06:23:21 PM PDT 24 Jul 09 06:23:22 PM PDT 24 577738426 ps
T295 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2452162625 Jul 09 06:23:28 PM PDT 24 Jul 09 06:23:29 PM PDT 24 577074570 ps
T296 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3639839163 Jul 09 06:23:15 PM PDT 24 Jul 09 06:23:16 PM PDT 24 466091884 ps
T78 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2345322969 Jul 09 06:23:03 PM PDT 24 Jul 09 06:23:06 PM PDT 24 1409398370 ps
T297 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4198079082 Jul 09 06:24:03 PM PDT 24 Jul 09 06:24:04 PM PDT 24 451343659 ps
T298 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3792073024 Jul 09 06:23:18 PM PDT 24 Jul 09 06:23:20 PM PDT 24 593100168 ps
T299 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2655880042 Jul 09 06:24:05 PM PDT 24 Jul 09 06:24:06 PM PDT 24 484182632 ps
T300 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3337407008 Jul 09 06:24:00 PM PDT 24 Jul 09 06:24:01 PM PDT 24 425045692 ps
T301 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3215956095 Jul 09 06:23:18 PM PDT 24 Jul 09 06:23:19 PM PDT 24 421051281 ps
T79 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.12614894 Jul 09 06:23:34 PM PDT 24 Jul 09 06:23:36 PM PDT 24 1248990303 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3903310975 Jul 09 06:22:41 PM PDT 24 Jul 09 06:22:42 PM PDT 24 421373773 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2076129608 Jul 09 06:22:56 PM PDT 24 Jul 09 06:22:58 PM PDT 24 819115388 ps
T302 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3656731593 Jul 09 06:23:41 PM PDT 24 Jul 09 06:23:43 PM PDT 24 500526115 ps
T193 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.115310257 Jul 09 06:22:53 PM PDT 24 Jul 09 06:22:57 PM PDT 24 8948728108 ps
T303 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.704470737 Jul 09 06:23:32 PM PDT 24 Jul 09 06:23:33 PM PDT 24 386229297 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1704073306 Jul 09 06:22:51 PM PDT 24 Jul 09 06:22:54 PM PDT 24 705809154 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2549124380 Jul 09 06:22:50 PM PDT 24 Jul 09 06:22:51 PM PDT 24 528535763 ps
T305 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2627554846 Jul 09 06:23:59 PM PDT 24 Jul 09 06:24:01 PM PDT 24 425099733 ps
T306 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2751705016 Jul 09 06:23:17 PM PDT 24 Jul 09 06:23:24 PM PDT 24 7934723478 ps
T307 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1091265019 Jul 09 06:24:00 PM PDT 24 Jul 09 06:24:01 PM PDT 24 332221809 ps
T80 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.954977639 Jul 09 06:23:29 PM PDT 24 Jul 09 06:23:32 PM PDT 24 2855534427 ps
T308 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.730010257 Jul 09 06:23:18 PM PDT 24 Jul 09 06:23:19 PM PDT 24 369897069 ps
T309 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2837553563 Jul 09 06:23:51 PM PDT 24 Jul 09 06:23:52 PM PDT 24 531126690 ps
T81 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2134384999 Jul 09 06:23:34 PM PDT 24 Jul 09 06:23:36 PM PDT 24 1240365247 ps
T71 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.847644007 Jul 09 06:23:20 PM PDT 24 Jul 09 06:23:22 PM PDT 24 405685194 ps
T310 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1170186693 Jul 09 06:24:03 PM PDT 24 Jul 09 06:24:04 PM PDT 24 440487887 ps
T311 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1434388976 Jul 09 06:23:24 PM PDT 24 Jul 09 06:23:25 PM PDT 24 340599211 ps
T312 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1628945626 Jul 09 06:23:59 PM PDT 24 Jul 09 06:24:00 PM PDT 24 425068761 ps
T313 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3685470308 Jul 09 06:23:28 PM PDT 24 Jul 09 06:23:30 PM PDT 24 4348679034 ps
T314 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1130195456 Jul 09 06:23:54 PM PDT 24 Jul 09 06:23:55 PM PDT 24 525521674 ps
T315 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2654670071 Jul 09 06:23:42 PM PDT 24 Jul 09 06:23:44 PM PDT 24 664446586 ps
T316 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.618991662 Jul 09 06:23:28 PM PDT 24 Jul 09 06:23:30 PM PDT 24 504239396 ps
T317 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1765141741 Jul 09 06:24:03 PM PDT 24 Jul 09 06:24:04 PM PDT 24 468555267 ps
T318 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4262490567 Jul 09 06:23:10 PM PDT 24 Jul 09 06:23:11 PM PDT 24 473171202 ps
T72 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1629042417 Jul 09 06:22:51 PM PDT 24 Jul 09 06:22:52 PM PDT 24 600178768 ps
T319 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2355642264 Jul 09 06:22:56 PM PDT 24 Jul 09 06:23:01 PM PDT 24 4452467421 ps
T320 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.517946451 Jul 09 06:24:06 PM PDT 24 Jul 09 06:24:07 PM PDT 24 291482582 ps
T321 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3015899481 Jul 09 06:23:37 PM PDT 24 Jul 09 06:23:38 PM PDT 24 1884464194 ps
T322 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.954875872 Jul 09 06:23:18 PM PDT 24 Jul 09 06:23:22 PM PDT 24 1363350321 ps
T323 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3082837881 Jul 09 06:24:00 PM PDT 24 Jul 09 06:24:01 PM PDT 24 511632458 ps
T324 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1657319914 Jul 09 06:24:00 PM PDT 24 Jul 09 06:24:00 PM PDT 24 406848890 ps
T325 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1550528169 Jul 09 06:24:05 PM PDT 24 Jul 09 06:24:06 PM PDT 24 373407058 ps
T65 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2258474608 Jul 09 06:23:32 PM PDT 24 Jul 09 06:23:33 PM PDT 24 544799692 ps
T73 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1923498743 Jul 09 06:23:15 PM PDT 24 Jul 09 06:23:17 PM PDT 24 479813417 ps
T326 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3499635087 Jul 09 06:23:30 PM PDT 24 Jul 09 06:23:31 PM PDT 24 422797170 ps
T327 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1568145168 Jul 09 06:23:55 PM PDT 24 Jul 09 06:23:56 PM PDT 24 412184749 ps
T328 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2493583271 Jul 09 06:23:42 PM PDT 24 Jul 09 06:23:43 PM PDT 24 481741669 ps
T66 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.377359696 Jul 09 06:24:06 PM PDT 24 Jul 09 06:24:07 PM PDT 24 379425114 ps
T329 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2286112963 Jul 09 06:23:31 PM PDT 24 Jul 09 06:23:35 PM PDT 24 8317335107 ps
T330 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1484839674 Jul 09 06:23:29 PM PDT 24 Jul 09 06:23:31 PM PDT 24 555004537 ps
T331 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3874212153 Jul 09 06:23:32 PM PDT 24 Jul 09 06:23:35 PM PDT 24 1477576617 ps
T332 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2087034180 Jul 09 06:23:24 PM PDT 24 Jul 09 06:23:26 PM PDT 24 318723169 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3129514045 Jul 09 06:23:41 PM PDT 24 Jul 09 06:23:49 PM PDT 24 4115879966 ps
T334 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.42309053 Jul 09 06:23:47 PM PDT 24 Jul 09 06:23:51 PM PDT 24 7929507872 ps
T335 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1972131478 Jul 09 06:23:55 PM PDT 24 Jul 09 06:23:57 PM PDT 24 573607441 ps
T336 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2583834036 Jul 09 06:23:19 PM PDT 24 Jul 09 06:23:22 PM PDT 24 397874624 ps
T337 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2705011359 Jul 09 06:23:59 PM PDT 24 Jul 09 06:24:01 PM PDT 24 323693601 ps
T338 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.127237780 Jul 09 06:23:24 PM PDT 24 Jul 09 06:23:33 PM PDT 24 4642392072 ps
T196 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1657054154 Jul 09 06:23:45 PM PDT 24 Jul 09 06:23:57 PM PDT 24 8898110081 ps
T339 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1710597180 Jul 09 06:23:30 PM PDT 24 Jul 09 06:23:33 PM PDT 24 4508408331 ps
T340 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.739924793 Jul 09 06:22:48 PM PDT 24 Jul 09 06:22:50 PM PDT 24 534629253 ps
T341 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1036230227 Jul 09 06:24:07 PM PDT 24 Jul 09 06:24:08 PM PDT 24 329761705 ps
T342 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1931602571 Jul 09 06:23:50 PM PDT 24 Jul 09 06:23:52 PM PDT 24 2399531757 ps
T343 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3542951891 Jul 09 06:23:56 PM PDT 24 Jul 09 06:23:57 PM PDT 24 436252964 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3155289658 Jul 09 06:22:44 PM PDT 24 Jul 09 06:22:46 PM PDT 24 525902186 ps
T344 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4097441063 Jul 09 06:22:52 PM PDT 24 Jul 09 06:22:55 PM PDT 24 966925828 ps
T345 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3592661897 Jul 09 06:24:04 PM PDT 24 Jul 09 06:24:05 PM PDT 24 323443105 ps
T346 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2254714438 Jul 09 06:23:45 PM PDT 24 Jul 09 06:23:47 PM PDT 24 570184887 ps
T347 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2836652030 Jul 09 06:24:07 PM PDT 24 Jul 09 06:24:08 PM PDT 24 424306620 ps
T348 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1205151293 Jul 09 06:23:06 PM PDT 24 Jul 09 06:23:07 PM PDT 24 293033359 ps
T349 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1036557747 Jul 09 06:23:32 PM PDT 24 Jul 09 06:23:34 PM PDT 24 1169707047 ps
T194 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2010258351 Jul 09 06:23:27 PM PDT 24 Jul 09 06:23:32 PM PDT 24 8592515938 ps
T350 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3192263946 Jul 09 06:23:34 PM PDT 24 Jul 09 06:23:40 PM PDT 24 4442082506 ps
T351 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3341954209 Jul 09 06:23:20 PM PDT 24 Jul 09 06:23:21 PM PDT 24 326208941 ps
T352 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4159125099 Jul 09 06:24:03 PM PDT 24 Jul 09 06:24:04 PM PDT 24 409679129 ps
T353 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2308350501 Jul 09 06:23:47 PM PDT 24 Jul 09 06:23:48 PM PDT 24 528622222 ps
T354 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1648912929 Jul 09 06:23:44 PM PDT 24 Jul 09 06:23:47 PM PDT 24 1411850447 ps
T355 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3058668293 Jul 09 06:24:08 PM PDT 24 Jul 09 06:24:09 PM PDT 24 433415084 ps
T356 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1087805408 Jul 09 06:22:56 PM PDT 24 Jul 09 06:22:58 PM PDT 24 2667508807 ps
T357 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1832084671 Jul 09 06:23:01 PM PDT 24 Jul 09 06:23:03 PM PDT 24 812020044 ps
T358 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3089093305 Jul 09 06:22:39 PM PDT 24 Jul 09 06:22:42 PM PDT 24 489392740 ps
T359 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.59841585 Jul 09 06:22:49 PM PDT 24 Jul 09 06:22:51 PM PDT 24 366048332 ps
T360 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1623375384 Jul 09 06:22:57 PM PDT 24 Jul 09 06:23:00 PM PDT 24 677959948 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4220429012 Jul 09 06:22:55 PM PDT 24 Jul 09 06:22:56 PM PDT 24 454194903 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1724032434 Jul 09 06:22:51 PM PDT 24 Jul 09 06:22:53 PM PDT 24 614316628 ps
T363 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.737631570 Jul 09 06:23:45 PM PDT 24 Jul 09 06:23:47 PM PDT 24 1155531483 ps
T364 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2962709571 Jul 09 06:23:14 PM PDT 24 Jul 09 06:23:19 PM PDT 24 3009530015 ps
T365 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3213987251 Jul 09 06:22:56 PM PDT 24 Jul 09 06:22:57 PM PDT 24 343440974 ps
T366 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.881618949 Jul 09 06:23:56 PM PDT 24 Jul 09 06:23:58 PM PDT 24 326360001 ps
T367 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3471988074 Jul 09 06:23:56 PM PDT 24 Jul 09 06:23:58 PM PDT 24 284540644 ps
T368 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3349618216 Jul 09 06:23:07 PM PDT 24 Jul 09 06:23:09 PM PDT 24 458806137 ps
T369 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2804127702 Jul 09 06:24:02 PM PDT 24 Jul 09 06:24:03 PM PDT 24 478560915 ps
T370 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3118428857 Jul 09 06:23:37 PM PDT 24 Jul 09 06:23:39 PM PDT 24 432434639 ps
T371 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.677588229 Jul 09 06:23:25 PM PDT 24 Jul 09 06:23:26 PM PDT 24 312884433 ps
T195 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2342785689 Jul 09 06:23:17 PM PDT 24 Jul 09 06:23:25 PM PDT 24 4325546561 ps
T372 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2741861679 Jul 09 06:22:43 PM PDT 24 Jul 09 06:22:58 PM PDT 24 8492354969 ps
T373 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2666401339 Jul 09 06:22:57 PM PDT 24 Jul 09 06:22:59 PM PDT 24 475272301 ps
T374 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.859005538 Jul 09 06:23:49 PM PDT 24 Jul 09 06:23:50 PM PDT 24 423146425 ps
T375 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.560515178 Jul 09 06:23:26 PM PDT 24 Jul 09 06:23:28 PM PDT 24 472541736 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.548930348 Jul 09 06:22:52 PM PDT 24 Jul 09 06:22:53 PM PDT 24 419129044 ps
T377 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1020744565 Jul 09 06:23:27 PM PDT 24 Jul 09 06:23:28 PM PDT 24 509074322 ps
T378 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2594748707 Jul 09 06:23:27 PM PDT 24 Jul 09 06:23:30 PM PDT 24 8245106633 ps
T379 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1592908832 Jul 09 06:23:11 PM PDT 24 Jul 09 06:23:15 PM PDT 24 7454257322 ps
T380 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3362031726 Jul 09 06:23:44 PM PDT 24 Jul 09 06:23:46 PM PDT 24 459662448 ps
T381 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.425930250 Jul 09 06:23:17 PM PDT 24 Jul 09 06:23:20 PM PDT 24 801856881 ps
T382 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1462389250 Jul 09 06:23:30 PM PDT 24 Jul 09 06:23:32 PM PDT 24 673027442 ps
T383 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.197659521 Jul 09 06:23:03 PM PDT 24 Jul 09 06:23:05 PM PDT 24 453571118 ps
T384 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.713837140 Jul 09 06:23:55 PM PDT 24 Jul 09 06:23:57 PM PDT 24 743389831 ps
T385 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1873287874 Jul 09 06:24:01 PM PDT 24 Jul 09 06:24:03 PM PDT 24 448633779 ps
T386 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2115755376 Jul 09 06:23:36 PM PDT 24 Jul 09 06:23:37 PM PDT 24 369871874 ps
T387 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4011020973 Jul 09 06:23:55 PM PDT 24 Jul 09 06:23:58 PM PDT 24 4317401490 ps
T388 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2602252096 Jul 09 06:23:07 PM PDT 24 Jul 09 06:23:08 PM PDT 24 279569444 ps
T389 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.708615796 Jul 09 06:22:42 PM PDT 24 Jul 09 06:22:44 PM PDT 24 441915893 ps
T390 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1053554303 Jul 09 06:22:47 PM PDT 24 Jul 09 06:22:49 PM PDT 24 399708469 ps
T391 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.888783684 Jul 09 06:22:58 PM PDT 24 Jul 09 06:23:00 PM PDT 24 265823207 ps
T392 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2578149584 Jul 09 06:23:20 PM PDT 24 Jul 09 06:23:22 PM PDT 24 2914546251 ps
T393 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.787710836 Jul 09 06:23:54 PM PDT 24 Jul 09 06:23:55 PM PDT 24 492683523 ps
T394 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.611356101 Jul 09 06:23:31 PM PDT 24 Jul 09 06:23:33 PM PDT 24 357894460 ps
T395 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2722170479 Jul 09 06:22:48 PM PDT 24 Jul 09 06:22:49 PM PDT 24 446846739 ps
T396 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2508513827 Jul 09 06:23:38 PM PDT 24 Jul 09 06:23:39 PM PDT 24 431112188 ps
T397 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.26840176 Jul 09 06:22:41 PM PDT 24 Jul 09 06:22:42 PM PDT 24 435109352 ps
T398 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.260340801 Jul 09 06:24:05 PM PDT 24 Jul 09 06:24:06 PM PDT 24 349646570 ps
T399 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.959431992 Jul 09 06:23:51 PM PDT 24 Jul 09 06:23:53 PM PDT 24 498758863 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2548663119 Jul 09 06:24:05 PM PDT 24 Jul 09 06:24:08 PM PDT 24 2146963033 ps
T401 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.542905085 Jul 09 06:23:01 PM PDT 24 Jul 09 06:23:02 PM PDT 24 478369305 ps
T402 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1798016052 Jul 09 06:23:17 PM PDT 24 Jul 09 06:23:20 PM PDT 24 614038731 ps
T403 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.752035655 Jul 09 06:23:54 PM PDT 24 Jul 09 06:23:56 PM PDT 24 943098067 ps
T404 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4014714944 Jul 09 06:23:28 PM PDT 24 Jul 09 06:23:30 PM PDT 24 482922758 ps
T405 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2523357553 Jul 09 06:23:30 PM PDT 24 Jul 09 06:23:31 PM PDT 24 404909024 ps
T406 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1066725166 Jul 09 06:23:43 PM PDT 24 Jul 09 06:23:46 PM PDT 24 385238539 ps
T407 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.721034166 Jul 09 06:22:45 PM PDT 24 Jul 09 06:22:47 PM PDT 24 685812758 ps
T408 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3755211088 Jul 09 06:22:47 PM PDT 24 Jul 09 06:22:49 PM PDT 24 1206339122 ps
T409 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.109603231 Jul 09 06:24:06 PM PDT 24 Jul 09 06:24:08 PM PDT 24 283049406 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2940318349 Jul 09 06:22:41 PM PDT 24 Jul 09 06:22:43 PM PDT 24 626514641 ps
T69 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1630156827 Jul 09 06:23:05 PM PDT 24 Jul 09 06:23:07 PM PDT 24 483765756 ps
T410 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2305450176 Jul 09 06:22:39 PM PDT 24 Jul 09 06:22:40 PM PDT 24 419229920 ps
T411 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1236427544 Jul 09 06:23:46 PM PDT 24 Jul 09 06:23:47 PM PDT 24 362404302 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2059744956 Jul 09 06:22:59 PM PDT 24 Jul 09 06:23:24 PM PDT 24 13300009900 ps
T413 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1084577413 Jul 09 06:23:05 PM PDT 24 Jul 09 06:23:10 PM PDT 24 4243124407 ps
T414 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2913855721 Jul 09 06:23:25 PM PDT 24 Jul 09 06:23:28 PM PDT 24 1151595670 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2342770932 Jul 09 06:22:49 PM PDT 24 Jul 09 06:22:52 PM PDT 24 1259806862 ps
T416 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1668720169 Jul 09 06:23:50 PM PDT 24 Jul 09 06:23:51 PM PDT 24 521335059 ps
T417 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1476925481 Jul 09 06:23:53 PM PDT 24 Jul 09 06:23:54 PM PDT 24 409471124 ps
T418 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.111880130 Jul 09 06:23:12 PM PDT 24 Jul 09 06:23:13 PM PDT 24 481632112 ps

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3230737436
Short name T7
Test name
Test status
Simulation time 39244704059 ps
CPU time 275.75 seconds
Started Jul 09 06:20:28 PM PDT 24
Finished Jul 09 06:25:04 PM PDT 24
Peak memory 206836 kb
Host smart-339b271c-6a0e-4f6f-9f96-e6873584c540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230737436 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3230737436
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1735155619
Short name T22
Test name
Test status
Simulation time 25959438452 ps
CPU time 11.53 seconds
Started Jul 09 06:19:21 PM PDT 24
Finished Jul 09 06:19:32 PM PDT 24
Peak memory 198340 kb
Host smart-95e74dce-3dbe-45f1-b5a0-9868dfbaacf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735155619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1735155619
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.451063428
Short name T37
Test name
Test status
Simulation time 8573140971 ps
CPU time 14.84 seconds
Started Jul 09 06:22:47 PM PDT 24
Finished Jul 09 06:23:02 PM PDT 24
Peak memory 198208 kb
Host smart-7d62b54a-32ea-4b0f-942a-94617cc26687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451063428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.451063428
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2316973089
Short name T59
Test name
Test status
Simulation time 281500250348 ps
CPU time 397.93 seconds
Started Jul 09 06:19:12 PM PDT 24
Finished Jul 09 06:25:50 PM PDT 24
Peak memory 214268 kb
Host smart-1be1163b-d64f-425c-a301-1410ce37f648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316973089 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2316973089
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2019515305
Short name T105
Test name
Test status
Simulation time 241479271086 ps
CPU time 514.74 seconds
Started Jul 09 06:20:19 PM PDT 24
Finished Jul 09 06:28:54 PM PDT 24
Peak memory 212624 kb
Host smart-fd5f030c-39c1-44f3-a669-30d2eb31b6ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019515305 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2019515305
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3317349223
Short name T4
Test name
Test status
Simulation time 399869447 ps
CPU time 1.22 seconds
Started Jul 09 06:19:32 PM PDT 24
Finished Jul 09 06:19:34 PM PDT 24
Peak memory 196728 kb
Host smart-82406673-7447-492f-8c44-af33ec3a1445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317349223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3317349223
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2447204001
Short name T130
Test name
Test status
Simulation time 19315786218 ps
CPU time 112.32 seconds
Started Jul 09 06:22:01 PM PDT 24
Finished Jul 09 06:23:53 PM PDT 24
Peak memory 198612 kb
Host smart-88924dc9-bc81-4456-bf80-f8320560df47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447204001 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2447204001
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2010980372
Short name T82
Test name
Test status
Simulation time 361214281424 ps
CPU time 863.82 seconds
Started Jul 09 06:20:16 PM PDT 24
Finished Jul 09 06:34:40 PM PDT 24
Peak memory 208100 kb
Host smart-0f319159-32a2-47d4-979c-47bb5aeece13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010980372 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2010980372
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1323564315
Short name T111
Test name
Test status
Simulation time 49349004944 ps
CPU time 512.55 seconds
Started Jul 09 06:22:22 PM PDT 24
Finished Jul 09 06:30:55 PM PDT 24
Peak memory 202080 kb
Host smart-4cca7abd-8e16-45e5-bdb8-82bc2803a971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323564315 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1323564315
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1842964804
Short name T94
Test name
Test status
Simulation time 70787241892 ps
CPU time 485.11 seconds
Started Jul 09 06:19:59 PM PDT 24
Finished Jul 09 06:28:05 PM PDT 24
Peak memory 210064 kb
Host smart-4dd41e9a-9b6a-417f-91af-caf95af5f92a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842964804 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1842964804
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2758032699
Short name T88
Test name
Test status
Simulation time 120624129632 ps
CPU time 226.63 seconds
Started Jul 09 06:21:43 PM PDT 24
Finished Jul 09 06:25:29 PM PDT 24
Peak memory 206788 kb
Host smart-7cfe8b5a-a384-4b40-bbf2-d22d3b3e9b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758032699 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2758032699
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.659191612
Short name T99
Test name
Test status
Simulation time 173853623631 ps
CPU time 339.42 seconds
Started Jul 09 06:21:31 PM PDT 24
Finished Jul 09 06:27:11 PM PDT 24
Peak memory 210400 kb
Host smart-3aa28955-208f-4473-aa7e-8446b1a959cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659191612 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.659191612
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.720880787
Short name T24
Test name
Test status
Simulation time 7642813020 ps
CPU time 3.42 seconds
Started Jul 09 06:19:01 PM PDT 24
Finished Jul 09 06:19:04 PM PDT 24
Peak memory 215844 kb
Host smart-4e4e7e2a-9335-4073-bc7e-a956f37e24f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720880787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.720880787
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3792646808
Short name T85
Test name
Test status
Simulation time 1081224287188 ps
CPU time 474.06 seconds
Started Jul 09 06:20:45 PM PDT 24
Finished Jul 09 06:28:40 PM PDT 24
Peak memory 206864 kb
Host smart-35b22b64-fa9b-4392-a0a1-8bb688dcc6f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792646808 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3792646808
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.60497528
Short name T96
Test name
Test status
Simulation time 88785750375 ps
CPU time 656.64 seconds
Started Jul 09 06:22:10 PM PDT 24
Finished Jul 09 06:33:07 PM PDT 24
Peak memory 206424 kb
Host smart-c3fea3d4-e307-4d29-b15a-a93451f77180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60497528 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.60497528
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3697986802
Short name T20
Test name
Test status
Simulation time 21921320602 ps
CPU time 34.59 seconds
Started Jul 09 06:19:12 PM PDT 24
Finished Jul 09 06:19:47 PM PDT 24
Peak memory 198272 kb
Host smart-b214c0dd-01ae-4ec9-92ab-5d518ce63d33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697986802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3697986802
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.247720627
Short name T58
Test name
Test status
Simulation time 693073350714 ps
CPU time 714.71 seconds
Started Jul 09 06:22:32 PM PDT 24
Finished Jul 09 06:34:27 PM PDT 24
Peak memory 214436 kb
Host smart-5c24f1bd-18f3-4cb1-a76a-77cd120cea02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247720627 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.247720627
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3556137936
Short name T95
Test name
Test status
Simulation time 209428950715 ps
CPU time 1063.52 seconds
Started Jul 09 06:21:23 PM PDT 24
Finished Jul 09 06:39:07 PM PDT 24
Peak memory 215060 kb
Host smart-80586f4c-33ab-49f7-9530-3bcd53f7c1e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556137936 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3556137936
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3283263786
Short name T57
Test name
Test status
Simulation time 491281061005 ps
CPU time 573.25 seconds
Started Jul 09 06:20:16 PM PDT 24
Finished Jul 09 06:29:49 PM PDT 24
Peak memory 214660 kb
Host smart-3c42822f-440a-4ca5-8bb6-623da6c87d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283263786 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3283263786
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2442206881
Short name T114
Test name
Test status
Simulation time 46210897365 ps
CPU time 123.38 seconds
Started Jul 09 06:19:20 PM PDT 24
Finished Jul 09 06:21:24 PM PDT 24
Peak memory 206852 kb
Host smart-0c05f6af-0219-42f2-8f9c-6c8f2d0fa925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442206881 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2442206881
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.4196830330
Short name T104
Test name
Test status
Simulation time 47954643819 ps
CPU time 64.31 seconds
Started Jul 09 06:22:13 PM PDT 24
Finished Jul 09 06:23:17 PM PDT 24
Peak memory 193096 kb
Host smart-07c8cea5-60a3-4cd2-9f47-9940e6818a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196830330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.4196830330
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2549124380
Short name T70
Test name
Test status
Simulation time 528535763 ps
CPU time 1.24 seconds
Started Jul 09 06:22:50 PM PDT 24
Finished Jul 09 06:22:51 PM PDT 24
Peak memory 193216 kb
Host smart-51d7baef-1f1d-499d-896e-92f589f57d1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549124380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2549124380
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1615903171
Short name T127
Test name
Test status
Simulation time 89051112732 ps
CPU time 661.78 seconds
Started Jul 09 06:21:04 PM PDT 24
Finished Jul 09 06:32:07 PM PDT 24
Peak memory 205772 kb
Host smart-a1a08d31-5d48-449e-a142-6ea5ebe8b09f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615903171 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1615903171
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1925475910
Short name T101
Test name
Test status
Simulation time 315550151271 ps
CPU time 119.97 seconds
Started Jul 09 06:21:19 PM PDT 24
Finished Jul 09 06:23:19 PM PDT 24
Peak memory 198316 kb
Host smart-98bd5b29-e2e0-4b03-b68d-3b207ea666e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925475910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1925475910
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3447278116
Short name T119
Test name
Test status
Simulation time 134823572758 ps
CPU time 177.07 seconds
Started Jul 09 06:20:34 PM PDT 24
Finished Jul 09 06:23:31 PM PDT 24
Peak memory 193080 kb
Host smart-a4de2571-96e2-412a-8557-7d0e34b5386e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447278116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3447278116
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1105978141
Short name T103
Test name
Test status
Simulation time 69067392020 ps
CPU time 24.38 seconds
Started Jul 09 06:22:18 PM PDT 24
Finished Jul 09 06:22:43 PM PDT 24
Peak memory 193260 kb
Host smart-6fed3d7e-cec4-41f9-a34b-43f9460f4ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105978141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1105978141
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.875508887
Short name T44
Test name
Test status
Simulation time 245690607244 ps
CPU time 292.57 seconds
Started Jul 09 06:20:49 PM PDT 24
Finished Jul 09 06:25:42 PM PDT 24
Peak memory 201604 kb
Host smart-67a259f8-3d73-486d-947a-425a9fa99b21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875508887 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.875508887
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.61340201
Short name T35
Test name
Test status
Simulation time 859034567345 ps
CPU time 654.53 seconds
Started Jul 09 06:20:55 PM PDT 24
Finished Jul 09 06:31:50 PM PDT 24
Peak memory 214396 kb
Host smart-6ff52f2c-0142-4f78-9309-38f37bfbebcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61340201 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.61340201
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.660539667
Short name T113
Test name
Test status
Simulation time 37311122555 ps
CPU time 28.33 seconds
Started Jul 09 06:19:46 PM PDT 24
Finished Jul 09 06:20:15 PM PDT 24
Peak memory 191996 kb
Host smart-62a96648-5b32-4448-82e2-18bb152e42ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660539667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.660539667
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.27626486
Short name T145
Test name
Test status
Simulation time 116751288894 ps
CPU time 169.56 seconds
Started Jul 09 06:20:49 PM PDT 24
Finished Jul 09 06:23:39 PM PDT 24
Peak memory 193080 kb
Host smart-24cdfe3c-f28d-4e0b-9e5c-c553649c390e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27626486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_al
l.27626486
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1455334112
Short name T123
Test name
Test status
Simulation time 87708809897 ps
CPU time 252.16 seconds
Started Jul 09 06:21:21 PM PDT 24
Finished Jul 09 06:25:34 PM PDT 24
Peak memory 201020 kb
Host smart-3d9fb5ec-2154-4934-a173-ac7c91568cd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455334112 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1455334112
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3604596317
Short name T122
Test name
Test status
Simulation time 56338508719 ps
CPU time 447.6 seconds
Started Jul 09 06:20:41 PM PDT 24
Finished Jul 09 06:28:09 PM PDT 24
Peak memory 209356 kb
Host smart-abd0984d-7b56-48be-9609-7ed1c466f37e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604596317 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3604596317
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2392905242
Short name T168
Test name
Test status
Simulation time 25512389720 ps
CPU time 189.43 seconds
Started Jul 09 06:20:40 PM PDT 24
Finished Jul 09 06:23:49 PM PDT 24
Peak memory 198576 kb
Host smart-972a8792-c87b-41e7-884b-2c7dd5ba629f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392905242 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2392905242
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2438805797
Short name T43
Test name
Test status
Simulation time 39425336087 ps
CPU time 268.72 seconds
Started Jul 09 06:22:19 PM PDT 24
Finished Jul 09 06:26:48 PM PDT 24
Peak memory 206796 kb
Host smart-d66d55ba-06fd-4db0-8e92-f901ff7cd7dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438805797 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2438805797
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4215612590
Short name T102
Test name
Test status
Simulation time 51678341115 ps
CPU time 68.04 seconds
Started Jul 09 06:19:56 PM PDT 24
Finished Jul 09 06:21:05 PM PDT 24
Peak memory 192004 kb
Host smart-fe49c9a1-1f46-4a1c-b626-0592fb624992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215612590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4215612590
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3038602546
Short name T27
Test name
Test status
Simulation time 17950418092 ps
CPU time 152.38 seconds
Started Jul 09 06:20:58 PM PDT 24
Finished Jul 09 06:23:31 PM PDT 24
Peak memory 206884 kb
Host smart-718aecdd-9a4c-4271-b940-e9e9bf0095a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038602546 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3038602546
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.182165426
Short name T138
Test name
Test status
Simulation time 22833465698 ps
CPU time 239.02 seconds
Started Jul 09 06:21:05 PM PDT 24
Finished Jul 09 06:25:05 PM PDT 24
Peak memory 198652 kb
Host smart-192d3c26-5015-4e33-94d6-33b4af4d1ecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182165426 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.182165426
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3390526154
Short name T32
Test name
Test status
Simulation time 40184912828 ps
CPU time 55.56 seconds
Started Jul 09 06:21:38 PM PDT 24
Finished Jul 09 06:22:35 PM PDT 24
Peak memory 198300 kb
Host smart-5613429b-6da0-4ca3-9230-3f3dd34cd705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390526154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3390526154
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3714788794
Short name T132
Test name
Test status
Simulation time 394984930945 ps
CPU time 133.54 seconds
Started Jul 09 06:21:35 PM PDT 24
Finished Jul 09 06:23:49 PM PDT 24
Peak memory 192972 kb
Host smart-487c2bb5-9dd8-49f3-b7dd-57a4650ca33e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714788794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3714788794
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2628807831
Short name T87
Test name
Test status
Simulation time 118143768861 ps
CPU time 86.77 seconds
Started Jul 09 06:21:43 PM PDT 24
Finished Jul 09 06:23:10 PM PDT 24
Peak memory 192004 kb
Host smart-3660bc1e-527a-4027-9dcf-a2a5c8720e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628807831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2628807831
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1609921331
Short name T156
Test name
Test status
Simulation time 55926315497 ps
CPU time 19.66 seconds
Started Jul 09 06:21:53 PM PDT 24
Finished Jul 09 06:22:13 PM PDT 24
Peak memory 184292 kb
Host smart-facbe3cb-3049-4d3d-9696-84d986f0b8cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609921331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1609921331
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3282835408
Short name T21
Test name
Test status
Simulation time 541435093606 ps
CPU time 785.75 seconds
Started Jul 09 06:19:40 PM PDT 24
Finished Jul 09 06:32:46 PM PDT 24
Peak memory 192932 kb
Host smart-fd2cdaf5-2d87-4da5-bef7-b56b5ff545de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282835408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3282835408
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3081156296
Short name T97
Test name
Test status
Simulation time 38656569473 ps
CPU time 152.11 seconds
Started Jul 09 06:19:36 PM PDT 24
Finished Jul 09 06:22:09 PM PDT 24
Peak memory 198672 kb
Host smart-c55e38a7-4606-4292-bf81-b51e0d3ba37d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081156296 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3081156296
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3333431478
Short name T124
Test name
Test status
Simulation time 231603696686 ps
CPU time 305.98 seconds
Started Jul 09 06:20:07 PM PDT 24
Finished Jul 09 06:25:14 PM PDT 24
Peak memory 198352 kb
Host smart-3b7daff5-e0bb-4fb5-b8fa-a045e1753cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333431478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3333431478
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3018823903
Short name T92
Test name
Test status
Simulation time 20591989704 ps
CPU time 144.37 seconds
Started Jul 09 06:21:15 PM PDT 24
Finished Jul 09 06:23:40 PM PDT 24
Peak memory 206832 kb
Host smart-c274a086-f886-4187-b2a7-c7a75a81f0d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018823903 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3018823903
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3327701754
Short name T150
Test name
Test status
Simulation time 230492190704 ps
CPU time 174.42 seconds
Started Jul 09 06:22:38 PM PDT 24
Finished Jul 09 06:25:33 PM PDT 24
Peak memory 191992 kb
Host smart-fbb42961-a3c6-4727-b569-abc6de4440e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327701754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3327701754
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1213282025
Short name T116
Test name
Test status
Simulation time 162283466193 ps
CPU time 217.92 seconds
Started Jul 09 06:21:46 PM PDT 24
Finished Jul 09 06:25:24 PM PDT 24
Peak memory 198360 kb
Host smart-90939184-c53e-4fb2-8696-8c8fd00c8fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213282025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1213282025
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1489750451
Short name T112
Test name
Test status
Simulation time 116727519776 ps
CPU time 84.72 seconds
Started Jul 09 06:22:22 PM PDT 24
Finished Jul 09 06:23:47 PM PDT 24
Peak memory 198344 kb
Host smart-ef39551b-7eb4-46c5-8fe1-5b7a093a4bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489750451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1489750451
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.203369200
Short name T147
Test name
Test status
Simulation time 183182198343 ps
CPU time 140.72 seconds
Started Jul 09 06:22:31 PM PDT 24
Finished Jul 09 06:24:52 PM PDT 24
Peak memory 193068 kb
Host smart-c27005bf-9edd-4341-8868-4e9809129826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203369200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.203369200
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.231720124
Short name T50
Test name
Test status
Simulation time 21543737121 ps
CPU time 90.83 seconds
Started Jul 09 06:19:46 PM PDT 24
Finished Jul 09 06:21:17 PM PDT 24
Peak memory 198848 kb
Host smart-0b047fb3-7f13-4f94-8250-986b8a8304a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231720124 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.231720124
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2417650320
Short name T110
Test name
Test status
Simulation time 181157933946 ps
CPU time 64.39 seconds
Started Jul 09 06:20:18 PM PDT 24
Finished Jul 09 06:21:23 PM PDT 24
Peak memory 192668 kb
Host smart-4f4ead08-7c0e-4ed0-bcfb-70e8e0a9b702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417650320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2417650320
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.48135966
Short name T46
Test name
Test status
Simulation time 457196165542 ps
CPU time 348.07 seconds
Started Jul 09 06:20:28 PM PDT 24
Finished Jul 09 06:26:16 PM PDT 24
Peak memory 192992 kb
Host smart-81a83831-a995-4803-8a98-2a256aba2396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48135966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_al
l.48135966
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.4193447703
Short name T106
Test name
Test status
Simulation time 75059074756 ps
CPU time 45.55 seconds
Started Jul 09 06:21:24 PM PDT 24
Finished Jul 09 06:22:10 PM PDT 24
Peak memory 191932 kb
Host smart-88545cb2-0b00-49d6-82af-95c905a729dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193447703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.4193447703
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3864278549
Short name T144
Test name
Test status
Simulation time 51281980340 ps
CPU time 185.81 seconds
Started Jul 09 06:22:12 PM PDT 24
Finished Jul 09 06:25:18 PM PDT 24
Peak memory 206804 kb
Host smart-d158c22b-e7e5-483b-8400-2e43ff95928c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864278549 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3864278549
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3948688865
Short name T107
Test name
Test status
Simulation time 303764049863 ps
CPU time 79.99 seconds
Started Jul 09 06:21:00 PM PDT 24
Finished Jul 09 06:22:21 PM PDT 24
Peak memory 184636 kb
Host smart-8ae952b3-fd9e-4d2f-83dd-0e0ca01e1c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948688865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3948688865
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.42194907
Short name T26
Test name
Test status
Simulation time 42970075227 ps
CPU time 241.38 seconds
Started Jul 09 06:21:53 PM PDT 24
Finished Jul 09 06:25:55 PM PDT 24
Peak memory 214232 kb
Host smart-f8bd6bce-15b1-4567-b751-5c4886acfaf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42194907 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.42194907
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2959483128
Short name T108
Test name
Test status
Simulation time 23643417242 ps
CPU time 15.69 seconds
Started Jul 09 06:22:27 PM PDT 24
Finished Jul 09 06:22:43 PM PDT 24
Peak memory 192564 kb
Host smart-0b9fa16e-12d3-4296-b789-8404fa290d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959483128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2959483128
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2416276762
Short name T155
Test name
Test status
Simulation time 419157782 ps
CPU time 1.15 seconds
Started Jul 09 06:20:34 PM PDT 24
Finished Jul 09 06:20:36 PM PDT 24
Peak memory 196892 kb
Host smart-0a4c6625-ee08-466a-a8ea-9b73abe62a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416276762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2416276762
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1182443900
Short name T148
Test name
Test status
Simulation time 561944979 ps
CPU time 1.38 seconds
Started Jul 09 06:21:18 PM PDT 24
Finished Jul 09 06:21:20 PM PDT 24
Peak memory 196796 kb
Host smart-db5fba35-9544-4a76-853e-9a0120182326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182443900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1182443900
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2979689443
Short name T167
Test name
Test status
Simulation time 123412274879 ps
CPU time 49.57 seconds
Started Jul 09 06:19:33 PM PDT 24
Finished Jul 09 06:20:23 PM PDT 24
Peak memory 192684 kb
Host smart-8ab49827-2724-4c1a-991c-8f8cf0dc009c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979689443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2979689443
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1895953307
Short name T15
Test name
Test status
Simulation time 19974357577 ps
CPU time 147.3 seconds
Started Jul 09 06:19:39 PM PDT 24
Finished Jul 09 06:22:07 PM PDT 24
Peak memory 198540 kb
Host smart-c3306a4a-bc56-4335-ab31-9555a29dd983
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895953307 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1895953307
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1009653869
Short name T121
Test name
Test status
Simulation time 195261417550 ps
CPU time 212.19 seconds
Started Jul 09 06:20:41 PM PDT 24
Finished Jul 09 06:24:14 PM PDT 24
Peak memory 191976 kb
Host smart-2d642cd6-fb0b-41d9-8923-9b73d2da0f5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009653869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1009653869
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1100018892
Short name T115
Test name
Test status
Simulation time 54146599321 ps
CPU time 152.6 seconds
Started Jul 09 06:21:48 PM PDT 24
Finished Jul 09 06:24:21 PM PDT 24
Peak memory 206864 kb
Host smart-1e4189ff-1bbb-4b69-be19-d43efc566c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100018892 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1100018892
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1917645898
Short name T146
Test name
Test status
Simulation time 37545719604 ps
CPU time 61.13 seconds
Started Jul 09 06:21:59 PM PDT 24
Finished Jul 09 06:23:01 PM PDT 24
Peak memory 191972 kb
Host smart-89ccb487-68cb-43d4-b905-beb4642b0813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917645898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1917645898
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3947625737
Short name T55
Test name
Test status
Simulation time 465159748 ps
CPU time 0.65 seconds
Started Jul 09 06:22:04 PM PDT 24
Finished Jul 09 06:22:05 PM PDT 24
Peak memory 196884 kb
Host smart-3f4cbf5e-3691-4436-b019-a487a64c3f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947625737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3947625737
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2799678722
Short name T125
Test name
Test status
Simulation time 483419314 ps
CPU time 1.34 seconds
Started Jul 09 06:19:36 PM PDT 24
Finished Jul 09 06:19:38 PM PDT 24
Peak memory 196756 kb
Host smart-6196a9ba-9ea1-494f-8eb6-f5c186c9c340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799678722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2799678722
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.4020174138
Short name T133
Test name
Test status
Simulation time 427283775 ps
CPU time 0.9 seconds
Started Jul 09 06:19:06 PM PDT 24
Finished Jul 09 06:19:07 PM PDT 24
Peak memory 196996 kb
Host smart-989bfed8-6ebe-4f0a-a676-0074c97f92ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020174138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.4020174138
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3383484917
Short name T120
Test name
Test status
Simulation time 376804188 ps
CPU time 1.13 seconds
Started Jul 09 06:20:40 PM PDT 24
Finished Jul 09 06:20:41 PM PDT 24
Peak memory 196688 kb
Host smart-c1375ed0-17e3-48be-b91f-17eea7a04254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383484917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3383484917
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2170370967
Short name T51
Test name
Test status
Simulation time 136313406527 ps
CPU time 15.93 seconds
Started Jul 09 06:21:25 PM PDT 24
Finished Jul 09 06:21:42 PM PDT 24
Peak memory 191912 kb
Host smart-aa0e2df5-b279-42de-b5d2-ac06d178e205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170370967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2170370967
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.941470426
Short name T152
Test name
Test status
Simulation time 391973937 ps
CPU time 0.73 seconds
Started Jul 09 06:22:18 PM PDT 24
Finished Jul 09 06:22:19 PM PDT 24
Peak memory 196712 kb
Host smart-c4bb0827-ca64-4cb0-b60b-d94bb3d661ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941470426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.941470426
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3713446146
Short name T154
Test name
Test status
Simulation time 223072574258 ps
CPU time 322.53 seconds
Started Jul 09 06:22:27 PM PDT 24
Finished Jul 09 06:27:50 PM PDT 24
Peak memory 192444 kb
Host smart-87d9ee3c-ae30-4b62-bab2-81fc4b32930b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713446146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3713446146
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2992225628
Short name T136
Test name
Test status
Simulation time 463425871282 ps
CPU time 347.51 seconds
Started Jul 09 06:19:35 PM PDT 24
Finished Jul 09 06:25:23 PM PDT 24
Peak memory 193068 kb
Host smart-5a96e71e-787d-4a02-962e-6cdb27699fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992225628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2992225628
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1238241995
Short name T47
Test name
Test status
Simulation time 89814987423 ps
CPU time 418.91 seconds
Started Jul 09 06:19:51 PM PDT 24
Finished Jul 09 06:26:50 PM PDT 24
Peak memory 207588 kb
Host smart-59981f00-b1c7-4b10-9483-8f32ae383c8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238241995 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1238241995
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2398189375
Short name T126
Test name
Test status
Simulation time 446328469 ps
CPU time 1.26 seconds
Started Jul 09 06:20:19 PM PDT 24
Finished Jul 09 06:20:21 PM PDT 24
Peak memory 196676 kb
Host smart-ce475032-b46d-4ef1-ac46-ecda8af608ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398189375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2398189375
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.982461682
Short name T158
Test name
Test status
Simulation time 111029407535 ps
CPU time 83.54 seconds
Started Jul 09 06:20:30 PM PDT 24
Finished Jul 09 06:21:54 PM PDT 24
Peak memory 192492 kb
Host smart-e0f973d5-7575-4b91-9099-82023773ef49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982461682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.982461682
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.4283977919
Short name T118
Test name
Test status
Simulation time 573682392 ps
CPU time 1.35 seconds
Started Jul 09 06:20:49 PM PDT 24
Finished Jul 09 06:20:50 PM PDT 24
Peak memory 196728 kb
Host smart-8cb4527b-73ee-4f5b-ba7d-e0890a354069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283977919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.4283977919
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3772793479
Short name T160
Test name
Test status
Simulation time 531772165 ps
CPU time 0.79 seconds
Started Jul 09 06:21:22 PM PDT 24
Finished Jul 09 06:21:23 PM PDT 24
Peak memory 196688 kb
Host smart-f4673a56-e719-4197-ab11-b0c5e6ba11bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772793479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3772793479
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1259695677
Short name T109
Test name
Test status
Simulation time 387955357 ps
CPU time 1.17 seconds
Started Jul 09 06:19:20 PM PDT 24
Finished Jul 09 06:19:22 PM PDT 24
Peak memory 196764 kb
Host smart-4be3987b-c37d-449a-b94d-a4430961363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259695677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1259695677
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3225843576
Short name T23
Test name
Test status
Simulation time 574213679 ps
CPU time 1.36 seconds
Started Jul 09 06:21:46 PM PDT 24
Finished Jul 09 06:21:47 PM PDT 24
Peak memory 196824 kb
Host smart-98c28c7d-3291-4bfe-b0cc-0ee517ba5389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225843576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3225843576
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1964505944
Short name T153
Test name
Test status
Simulation time 534142273 ps
CPU time 0.77 seconds
Started Jul 09 06:22:03 PM PDT 24
Finished Jul 09 06:22:04 PM PDT 24
Peak memory 196752 kb
Host smart-3d80f9b7-2ab7-4689-9066-268913db003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964505944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1964505944
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3671867980
Short name T142
Test name
Test status
Simulation time 610099550 ps
CPU time 0.69 seconds
Started Jul 09 06:22:32 PM PDT 24
Finished Jul 09 06:22:33 PM PDT 24
Peak memory 196760 kb
Host smart-f642dcb4-8c3a-4a73-b025-dccde311ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671867980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3671867980
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1932575027
Short name T184
Test name
Test status
Simulation time 109394787755 ps
CPU time 216.99 seconds
Started Jul 09 06:19:00 PM PDT 24
Finished Jul 09 06:22:38 PM PDT 24
Peak memory 208648 kb
Host smart-99ce74b6-e3fd-4f11-8bd3-30b523fbe268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932575027 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1932575027
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.4157593485
Short name T117
Test name
Test status
Simulation time 605772289 ps
CPU time 0.72 seconds
Started Jul 09 06:19:56 PM PDT 24
Finished Jul 09 06:19:57 PM PDT 24
Peak memory 196652 kb
Host smart-413d4ccb-21dc-43c7-9d0d-bdd930da0014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157593485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4157593485
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3533961984
Short name T159
Test name
Test status
Simulation time 372570031 ps
CPU time 1.07 seconds
Started Jul 09 06:20:04 PM PDT 24
Finished Jul 09 06:20:05 PM PDT 24
Peak memory 196840 kb
Host smart-bdc5db80-9f2a-409d-b139-40b8d0089c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533961984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3533961984
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3119901306
Short name T173
Test name
Test status
Simulation time 41779952452 ps
CPU time 101.79 seconds
Started Jul 09 06:20:06 PM PDT 24
Finished Jul 09 06:21:48 PM PDT 24
Peak memory 206788 kb
Host smart-703c52b8-1eca-4d5b-969f-1b6781d6e8cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119901306 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3119901306
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1420774680
Short name T174
Test name
Test status
Simulation time 160441123826 ps
CPU time 62.28 seconds
Started Jul 09 06:20:56 PM PDT 24
Finished Jul 09 06:21:59 PM PDT 24
Peak memory 191916 kb
Host smart-eddaa2be-f5d4-4e6c-8d8a-3d967c01dd72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420774680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1420774680
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2414854173
Short name T54
Test name
Test status
Simulation time 56771991688 ps
CPU time 77.16 seconds
Started Jul 09 06:21:16 PM PDT 24
Finished Jul 09 06:22:33 PM PDT 24
Peak memory 191992 kb
Host smart-735a9bef-0fd8-4ae6-ac0a-bf603256cc1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414854173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2414854173
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1993965021
Short name T129
Test name
Test status
Simulation time 524072590 ps
CPU time 0.87 seconds
Started Jul 09 06:21:52 PM PDT 24
Finished Jul 09 06:21:54 PM PDT 24
Peak memory 196696 kb
Host smart-1a7aa257-a803-428a-b488-d19775509aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993965021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1993965021
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2331434630
Short name T157
Test name
Test status
Simulation time 538739230 ps
CPU time 1.38 seconds
Started Jul 09 06:21:55 PM PDT 24
Finished Jul 09 06:21:57 PM PDT 24
Peak memory 196716 kb
Host smart-5aa45325-241e-4c49-8e83-c344e4aa0839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331434630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2331434630
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.415420677
Short name T56
Test name
Test status
Simulation time 30223855490 ps
CPU time 137.33 seconds
Started Jul 09 06:21:58 PM PDT 24
Finished Jul 09 06:24:16 PM PDT 24
Peak memory 213104 kb
Host smart-99bf8562-a321-4e40-a272-c88fce46e850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415420677 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.415420677
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1484024473
Short name T163
Test name
Test status
Simulation time 257116576215 ps
CPU time 173.35 seconds
Started Jul 09 06:22:19 PM PDT 24
Finished Jul 09 06:25:12 PM PDT 24
Peak memory 191996 kb
Host smart-3c069a92-c944-416d-9ee1-589c4ee7aede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484024473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1484024473
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3099525532
Short name T151
Test name
Test status
Simulation time 571998591 ps
CPU time 1.33 seconds
Started Jul 09 06:22:28 PM PDT 24
Finished Jul 09 06:22:29 PM PDT 24
Peak memory 196712 kb
Host smart-0a94333a-f551-485c-b14c-85e5a4b4c827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099525532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3099525532
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1217652056
Short name T140
Test name
Test status
Simulation time 102372773188 ps
CPU time 157.22 seconds
Started Jul 09 06:19:51 PM PDT 24
Finished Jul 09 06:22:29 PM PDT 24
Peak memory 198340 kb
Host smart-06a788c7-d973-4d42-949f-1bff48a578b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217652056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1217652056
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3697705931
Short name T128
Test name
Test status
Simulation time 60919324110 ps
CPU time 8.25 seconds
Started Jul 09 06:20:12 PM PDT 24
Finished Jul 09 06:20:20 PM PDT 24
Peak memory 198304 kb
Host smart-1ea73778-4d59-4a6b-b082-58bfea157be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697705931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3697705931
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2928340418
Short name T131
Test name
Test status
Simulation time 357785242 ps
CPU time 0.83 seconds
Started Jul 09 06:20:17 PM PDT 24
Finished Jul 09 06:20:18 PM PDT 24
Peak memory 196732 kb
Host smart-644e6835-5d6d-4ab3-8748-8a94f3f2c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928340418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2928340418
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.4149385888
Short name T162
Test name
Test status
Simulation time 401410621733 ps
CPU time 52.88 seconds
Started Jul 09 06:20:17 PM PDT 24
Finished Jul 09 06:21:11 PM PDT 24
Peak memory 198352 kb
Host smart-116f2d4b-2194-45dd-a170-92e0b500e490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149385888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.4149385888
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2561072705
Short name T165
Test name
Test status
Simulation time 242225825087 ps
CPU time 93.54 seconds
Started Jul 09 06:20:26 PM PDT 24
Finished Jul 09 06:22:00 PM PDT 24
Peak memory 191924 kb
Host smart-f3c0a2dd-8a49-4609-94cd-b64f1513d231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561072705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2561072705
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.954547234
Short name T134
Test name
Test status
Simulation time 436506299 ps
CPU time 1.29 seconds
Started Jul 09 06:20:28 PM PDT 24
Finished Jul 09 06:20:29 PM PDT 24
Peak memory 196776 kb
Host smart-b2c53c10-e94b-4667-82ca-54aae66c06d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954547234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.954547234
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3180052274
Short name T149
Test name
Test status
Simulation time 447800207 ps
CPU time 1.16 seconds
Started Jul 09 06:21:06 PM PDT 24
Finished Jul 09 06:21:07 PM PDT 24
Peak memory 196604 kb
Host smart-5e9bd85a-dc2a-4c69-8a44-8ba737fc7cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180052274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3180052274
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.897874015
Short name T10
Test name
Test status
Simulation time 101610780504 ps
CPU time 191.45 seconds
Started Jul 09 06:22:18 PM PDT 24
Finished Jul 09 06:25:30 PM PDT 24
Peak memory 200196 kb
Host smart-acd98de1-2154-4837-95a3-1173f9780805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897874015 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.897874015
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2925842746
Short name T137
Test name
Test status
Simulation time 478457071 ps
CPU time 0.91 seconds
Started Jul 09 06:19:42 PM PDT 24
Finished Jul 09 06:19:43 PM PDT 24
Peak memory 196788 kb
Host smart-25712956-0013-4e1b-a31f-3a35cbcc79d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925842746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2925842746
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1678251978
Short name T185
Test name
Test status
Simulation time 428807090 ps
CPU time 1.22 seconds
Started Jul 09 06:18:57 PM PDT 24
Finished Jul 09 06:18:59 PM PDT 24
Peak memory 196956 kb
Host smart-222b95e6-a1db-465b-8c1a-95800343a229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678251978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1678251978
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.4114594340
Short name T93
Test name
Test status
Simulation time 212887007558 ps
CPU time 339.12 seconds
Started Jul 09 06:20:26 PM PDT 24
Finished Jul 09 06:26:05 PM PDT 24
Peak memory 201864 kb
Host smart-1b91976c-4193-4a4b-ab29-8ae52352fe69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114594340 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.4114594340
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1478627575
Short name T186
Test name
Test status
Simulation time 382986105080 ps
CPU time 124.24 seconds
Started Jul 09 06:19:13 PM PDT 24
Finished Jul 09 06:21:18 PM PDT 24
Peak memory 192528 kb
Host smart-993cc42f-0f0d-4f9a-b016-da997253de2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478627575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1478627575
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3521874352
Short name T171
Test name
Test status
Simulation time 241783948345 ps
CPU time 91.51 seconds
Started Jul 09 06:20:51 PM PDT 24
Finished Jul 09 06:22:23 PM PDT 24
Peak memory 192648 kb
Host smart-4e3bfe1f-0558-43ce-a572-585a169a993b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521874352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3521874352
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2771976787
Short name T166
Test name
Test status
Simulation time 332247680083 ps
CPU time 378.39 seconds
Started Jul 09 06:20:56 PM PDT 24
Finished Jul 09 06:27:15 PM PDT 24
Peak memory 193076 kb
Host smart-0ae7d674-f191-4b73-b89c-20b5b031c821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771976787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2771976787
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.449341774
Short name T98
Test name
Test status
Simulation time 53372244115 ps
CPU time 382.32 seconds
Started Jul 09 06:21:36 PM PDT 24
Finished Jul 09 06:27:59 PM PDT 24
Peak memory 200316 kb
Host smart-e7c9d75d-a0ee-40c2-ac5e-7c58de57a4b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449341774 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.449341774
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3669532331
Short name T189
Test name
Test status
Simulation time 528456316 ps
CPU time 1.27 seconds
Started Jul 09 06:21:40 PM PDT 24
Finished Jul 09 06:21:42 PM PDT 24
Peak memory 196700 kb
Host smart-475eceef-7a20-45d2-a35f-226b59eae9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669532331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3669532331
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2865462781
Short name T164
Test name
Test status
Simulation time 42020938217 ps
CPU time 301.36 seconds
Started Jul 09 06:19:32 PM PDT 24
Finished Jul 09 06:24:34 PM PDT 24
Peak memory 206964 kb
Host smart-4d9c383b-5919-45c4-8612-fe7035a5ac66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865462781 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2865462781
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1941058137
Short name T14
Test name
Test status
Simulation time 525979922 ps
CPU time 1.4 seconds
Started Jul 09 06:22:12 PM PDT 24
Finished Jul 09 06:22:14 PM PDT 24
Peak memory 196736 kb
Host smart-41133dd8-c9c4-4a8c-880e-c40e89c3da2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941058137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1941058137
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3213421843
Short name T135
Test name
Test status
Simulation time 478517595 ps
CPU time 1.21 seconds
Started Jul 09 06:22:20 PM PDT 24
Finished Jul 09 06:22:22 PM PDT 24
Peak memory 196748 kb
Host smart-11572907-afa1-45ee-8bad-6348b65946ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213421843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3213421843
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.784881228
Short name T190
Test name
Test status
Simulation time 573433492 ps
CPU time 0.8 seconds
Started Jul 09 06:22:17 PM PDT 24
Finished Jul 09 06:22:18 PM PDT 24
Peak memory 196784 kb
Host smart-b22b55d5-a433-4571-8cbd-ec2a72d3675a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784881228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.784881228
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3910039704
Short name T175
Test name
Test status
Simulation time 393025852 ps
CPU time 1.13 seconds
Started Jul 09 06:22:47 PM PDT 24
Finished Jul 09 06:22:49 PM PDT 24
Peak memory 196696 kb
Host smart-270acbcf-987a-485e-9c89-5403e5209494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910039704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3910039704
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2010258351
Short name T194
Test name
Test status
Simulation time 8592515938 ps
CPU time 4.55 seconds
Started Jul 09 06:23:27 PM PDT 24
Finished Jul 09 06:23:32 PM PDT 24
Peak memory 198388 kb
Host smart-1a8e9fff-5924-43b9-9673-0c1de0c855c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010258351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2010258351
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.920529032
Short name T177
Test name
Test status
Simulation time 247456553404 ps
CPU time 372.71 seconds
Started Jul 09 06:19:02 PM PDT 24
Finished Jul 09 06:25:15 PM PDT 24
Peak memory 198336 kb
Host smart-47844be6-3f4e-4fc5-a34c-840da95b267d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920529032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.920529032
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2875194176
Short name T169
Test name
Test status
Simulation time 578642141 ps
CPU time 0.87 seconds
Started Jul 09 06:20:10 PM PDT 24
Finished Jul 09 06:20:11 PM PDT 24
Peak memory 196632 kb
Host smart-e59ed5b6-d136-42e0-b2b2-45d49a107380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875194176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2875194176
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.4161447879
Short name T8
Test name
Test status
Simulation time 361619066 ps
CPU time 0.72 seconds
Started Jul 09 06:20:17 PM PDT 24
Finished Jul 09 06:20:18 PM PDT 24
Peak memory 196716 kb
Host smart-f11368de-681e-4e50-b346-83f6a20fee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161447879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.4161447879
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1445627546
Short name T29
Test name
Test status
Simulation time 402726220 ps
CPU time 0.72 seconds
Started Jul 09 06:20:26 PM PDT 24
Finished Jul 09 06:20:27 PM PDT 24
Peak memory 196708 kb
Host smart-596949b1-9340-42d8-bdd6-8d8da8c08ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445627546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1445627546
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3927112744
Short name T191
Test name
Test status
Simulation time 463561467 ps
CPU time 0.77 seconds
Started Jul 09 06:20:59 PM PDT 24
Finished Jul 09 06:21:00 PM PDT 24
Peak memory 196712 kb
Host smart-d0c0b5d0-c1c0-42f0-beb4-7d79f10d15ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927112744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3927112744
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.815516138
Short name T170
Test name
Test status
Simulation time 373628813 ps
CPU time 1.18 seconds
Started Jul 09 06:21:03 PM PDT 24
Finished Jul 09 06:21:04 PM PDT 24
Peak memory 196788 kb
Host smart-5feb1ce2-0661-41ab-9c74-a71bfd9238c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815516138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.815516138
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1239707046
Short name T141
Test name
Test status
Simulation time 430793819 ps
CPU time 1.22 seconds
Started Jul 09 06:21:12 PM PDT 24
Finished Jul 09 06:21:14 PM PDT 24
Peak memory 196648 kb
Host smart-d41fccb8-a19d-43c9-ab47-ffdc08c35b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239707046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1239707046
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.4279320027
Short name T180
Test name
Test status
Simulation time 510440505 ps
CPU time 0.7 seconds
Started Jul 09 06:22:22 PM PDT 24
Finished Jul 09 06:22:23 PM PDT 24
Peak memory 196796 kb
Host smart-a0a176d3-cfd6-4d91-a2c5-fbc662029187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279320027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.4279320027
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.321381456
Short name T179
Test name
Test status
Simulation time 83106560809 ps
CPU time 52.36 seconds
Started Jul 09 06:22:33 PM PDT 24
Finished Jul 09 06:23:26 PM PDT 24
Peak memory 191992 kb
Host smart-95f0cefd-3108-4419-9a9b-e3a549fd9a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321381456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.321381456
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3036487529
Short name T192
Test name
Test status
Simulation time 497383555 ps
CPU time 0.8 seconds
Started Jul 09 06:20:44 PM PDT 24
Finished Jul 09 06:20:46 PM PDT 24
Peak memory 196764 kb
Host smart-028fb07e-b084-4d9f-b683-3020e5f32fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036487529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3036487529
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.971437724
Short name T53
Test name
Test status
Simulation time 430857839 ps
CPU time 1.25 seconds
Started Jul 09 06:21:15 PM PDT 24
Finished Jul 09 06:21:17 PM PDT 24
Peak memory 196656 kb
Host smart-70c48918-8a20-4179-b009-71a4d9bda28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971437724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.971437724
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1557630945
Short name T34
Test name
Test status
Simulation time 703098249 ps
CPU time 0.67 seconds
Started Jul 09 06:21:39 PM PDT 24
Finished Jul 09 06:21:41 PM PDT 24
Peak memory 196672 kb
Host smart-1df6549f-4b64-465e-9242-650937957f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557630945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1557630945
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.648354936
Short name T143
Test name
Test status
Simulation time 493948783 ps
CPU time 1.24 seconds
Started Jul 09 06:21:41 PM PDT 24
Finished Jul 09 06:21:43 PM PDT 24
Peak memory 196752 kb
Host smart-ffde2e17-faa6-4f70-8d75-11ef1b0a61f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648354936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.648354936
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1157127835
Short name T181
Test name
Test status
Simulation time 585730646 ps
CPU time 0.81 seconds
Started Jul 09 06:21:47 PM PDT 24
Finished Jul 09 06:21:48 PM PDT 24
Peak memory 196756 kb
Host smart-6d865ef7-c834-4ad8-8f9e-5401b113a96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157127835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1157127835
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.4265229427
Short name T84
Test name
Test status
Simulation time 362352499759 ps
CPU time 507.54 seconds
Started Jul 09 06:21:51 PM PDT 24
Finished Jul 09 06:30:18 PM PDT 24
Peak memory 198312 kb
Host smart-eaa3dd95-64e8-4dab-89a5-c1c885dc4d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265229427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.4265229427
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.4111641275
Short name T187
Test name
Test status
Simulation time 409231364 ps
CPU time 1.21 seconds
Started Jul 09 06:22:00 PM PDT 24
Finished Jul 09 06:22:01 PM PDT 24
Peak memory 196768 kb
Host smart-b4435b66-ad60-4408-82ba-cda1ee5f09cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111641275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.4111641275
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1400393714
Short name T139
Test name
Test status
Simulation time 96297286445 ps
CPU time 134.78 seconds
Started Jul 09 06:22:03 PM PDT 24
Finished Jul 09 06:24:18 PM PDT 24
Peak memory 193004 kb
Host smart-eff3de90-6cc6-4e78-871b-9cfdbefd3ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400393714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1400393714
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.491489101
Short name T42
Test name
Test status
Simulation time 126066523339 ps
CPU time 342.19 seconds
Started Jul 09 06:22:23 PM PDT 24
Finished Jul 09 06:28:05 PM PDT 24
Peak memory 214936 kb
Host smart-f379ebd2-600c-40c7-b431-c6435e36aea1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491489101 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.491489101
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3698702788
Short name T178
Test name
Test status
Simulation time 628995010 ps
CPU time 1.02 seconds
Started Jul 09 06:22:26 PM PDT 24
Finished Jul 09 06:22:28 PM PDT 24
Peak memory 196676 kb
Host smart-e708a227-b587-467e-8e62-63ea16b93984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698702788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3698702788
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.109261960
Short name T188
Test name
Test status
Simulation time 181524373375 ps
CPU time 155.34 seconds
Started Jul 09 06:22:26 PM PDT 24
Finished Jul 09 06:25:02 PM PDT 24
Peak memory 206812 kb
Host smart-45b12896-62d8-47e6-8942-ccd83779996d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109261960 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.109261960
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2089807060
Short name T183
Test name
Test status
Simulation time 346524213 ps
CPU time 0.83 seconds
Started Jul 09 06:19:41 PM PDT 24
Finished Jul 09 06:19:42 PM PDT 24
Peak memory 196880 kb
Host smart-36c11df8-58fd-4302-806f-5f002a5d2ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089807060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2089807060
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1476508447
Short name T172
Test name
Test status
Simulation time 585791369 ps
CPU time 0.65 seconds
Started Jul 09 06:19:49 PM PDT 24
Finished Jul 09 06:19:50 PM PDT 24
Peak memory 196668 kb
Host smart-4020de4a-d400-4f91-81fd-1aaf22ac1fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476508447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1476508447
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3903310975
Short name T63
Test name
Test status
Simulation time 421373773 ps
CPU time 0.91 seconds
Started Jul 09 06:22:41 PM PDT 24
Finished Jul 09 06:22:42 PM PDT 24
Peak memory 193892 kb
Host smart-6e482850-33ea-49de-9e92-ab3647c1f294
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903310975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3903310975
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2940318349
Short name T68
Test name
Test status
Simulation time 626514641 ps
CPU time 1.73 seconds
Started Jul 09 06:22:41 PM PDT 24
Finished Jul 09 06:22:43 PM PDT 24
Peak memory 192348 kb
Host smart-87a7f425-e1b8-4fd1-a0e3-e5fc6dcc9c4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940318349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2940318349
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.721034166
Short name T407
Test name
Test status
Simulation time 685812758 ps
CPU time 1.71 seconds
Started Jul 09 06:22:45 PM PDT 24
Finished Jul 09 06:22:47 PM PDT 24
Peak memory 192168 kb
Host smart-1665f12c-49ff-4c41-9482-f6b261f13ca6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721034166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.721034166
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.739924793
Short name T340
Test name
Test status
Simulation time 534629253 ps
CPU time 0.92 seconds
Started Jul 09 06:22:48 PM PDT 24
Finished Jul 09 06:22:50 PM PDT 24
Peak memory 196332 kb
Host smart-3903a8e5-7c5e-43c9-9875-096712d46688
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739924793 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.739924793
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3155289658
Short name T67
Test name
Test status
Simulation time 525902186 ps
CPU time 0.96 seconds
Started Jul 09 06:22:44 PM PDT 24
Finished Jul 09 06:22:46 PM PDT 24
Peak memory 193452 kb
Host smart-0bd33609-7229-4527-a590-3fc4ee86b53f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155289658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3155289658
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.26840176
Short name T397
Test name
Test status
Simulation time 435109352 ps
CPU time 1.15 seconds
Started Jul 09 06:22:41 PM PDT 24
Finished Jul 09 06:22:42 PM PDT 24
Peak memory 183724 kb
Host smart-66c0a0a7-e20e-4ef2-bfa3-f8b342c9db65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26840176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.26840176
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.708615796
Short name T389
Test name
Test status
Simulation time 441915893 ps
CPU time 0.57 seconds
Started Jul 09 06:22:42 PM PDT 24
Finished Jul 09 06:22:44 PM PDT 24
Peak memory 183608 kb
Host smart-1056808a-0282-4f1e-a30c-4438d82bf86f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708615796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.708615796
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2305450176
Short name T410
Test name
Test status
Simulation time 419229920 ps
CPU time 0.64 seconds
Started Jul 09 06:22:39 PM PDT 24
Finished Jul 09 06:22:40 PM PDT 24
Peak memory 183748 kb
Host smart-d1a8a660-8263-4d01-a146-2d2112f4fc2e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305450176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2305450176
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3755211088
Short name T408
Test name
Test status
Simulation time 1206339122 ps
CPU time 2.29 seconds
Started Jul 09 06:22:47 PM PDT 24
Finished Jul 09 06:22:49 PM PDT 24
Peak memory 193032 kb
Host smart-63b646ca-dd0d-43ec-8f51-4e5db6ca36ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755211088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3755211088
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3089093305
Short name T358
Test name
Test status
Simulation time 489392740 ps
CPU time 2.11 seconds
Started Jul 09 06:22:39 PM PDT 24
Finished Jul 09 06:22:42 PM PDT 24
Peak memory 198632 kb
Host smart-34961f9e-9809-4b7b-9b27-25241a2388b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089093305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3089093305
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2741861679
Short name T372
Test name
Test status
Simulation time 8492354969 ps
CPU time 14.4 seconds
Started Jul 09 06:22:43 PM PDT 24
Finished Jul 09 06:22:58 PM PDT 24
Peak memory 198340 kb
Host smart-779b545b-0272-4ed6-80e8-0318ae788125
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741861679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2741861679
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1629042417
Short name T72
Test name
Test status
Simulation time 600178768 ps
CPU time 0.85 seconds
Started Jul 09 06:22:51 PM PDT 24
Finished Jul 09 06:22:52 PM PDT 24
Peak memory 194376 kb
Host smart-5b98b991-546c-455a-b37a-5b157bfed2a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629042417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1629042417
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2335948169
Short name T62
Test name
Test status
Simulation time 13261389659 ps
CPU time 5.88 seconds
Started Jul 09 06:22:51 PM PDT 24
Finished Jul 09 06:22:57 PM PDT 24
Peak memory 196240 kb
Host smart-3b6e21eb-a506-4bbc-82ea-18f7ec47de44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335948169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2335948169
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2342770932
Short name T415
Test name
Test status
Simulation time 1259806862 ps
CPU time 2.41 seconds
Started Jul 09 06:22:49 PM PDT 24
Finished Jul 09 06:22:52 PM PDT 24
Peak memory 193140 kb
Host smart-040304b5-f0f8-4a86-80ed-e0a2b9a27d0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342770932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2342770932
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1724032434
Short name T362
Test name
Test status
Simulation time 614316628 ps
CPU time 0.83 seconds
Started Jul 09 06:22:51 PM PDT 24
Finished Jul 09 06:22:53 PM PDT 24
Peak memory 196192 kb
Host smart-f5a7f7ca-bffc-4b8b-8dc7-a46261de7f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724032434 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1724032434
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2722170479
Short name T395
Test name
Test status
Simulation time 446846739 ps
CPU time 1.07 seconds
Started Jul 09 06:22:48 PM PDT 24
Finished Jul 09 06:22:49 PM PDT 24
Peak memory 183792 kb
Host smart-ebe625e6-66bc-4692-a93a-7a783999dc44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722170479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2722170479
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.59841585
Short name T359
Test name
Test status
Simulation time 366048332 ps
CPU time 1.03 seconds
Started Jul 09 06:22:49 PM PDT 24
Finished Jul 09 06:22:51 PM PDT 24
Peak memory 183836 kb
Host smart-11733e47-0b0f-4a5d-8319-7e5d367150b7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59841585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_tim
er_mem_partial_access.59841585
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3925732395
Short name T280
Test name
Test status
Simulation time 432473934 ps
CPU time 1.02 seconds
Started Jul 09 06:22:49 PM PDT 24
Finished Jul 09 06:22:50 PM PDT 24
Peak memory 183764 kb
Host smart-011bcd38-1180-4d72-bab6-69860aa9e1b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925732395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3925732395
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.41098235
Short name T75
Test name
Test status
Simulation time 2714477838 ps
CPU time 6.14 seconds
Started Jul 09 06:22:51 PM PDT 24
Finished Jul 09 06:22:58 PM PDT 24
Peak memory 193892 kb
Host smart-b7599ff9-99f6-489d-9a2b-a07f6a7fa195
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41098235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_same_csr_outstanding.41098235
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1053554303
Short name T390
Test name
Test status
Simulation time 399708469 ps
CPU time 2.58 seconds
Started Jul 09 06:22:47 PM PDT 24
Finished Jul 09 06:22:49 PM PDT 24
Peak memory 198680 kb
Host smart-6f5955d2-d6cc-4394-853b-03fc88e9bae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053554303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1053554303
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3181790368
Short name T289
Test name
Test status
Simulation time 366676679 ps
CPU time 1.28 seconds
Started Jul 09 06:23:30 PM PDT 24
Finished Jul 09 06:23:32 PM PDT 24
Peak memory 196460 kb
Host smart-e8a49c5e-dfd6-4b36-8a29-f8a0713f6299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181790368 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3181790368
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1020744565
Short name T377
Test name
Test status
Simulation time 509074322 ps
CPU time 0.73 seconds
Started Jul 09 06:23:27 PM PDT 24
Finished Jul 09 06:23:28 PM PDT 24
Peak memory 193340 kb
Host smart-cb97d20f-3452-4c50-a60a-3c8f049f0058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020744565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1020744565
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.704470737
Short name T303
Test name
Test status
Simulation time 386229297 ps
CPU time 0.84 seconds
Started Jul 09 06:23:32 PM PDT 24
Finished Jul 09 06:23:33 PM PDT 24
Peak memory 183732 kb
Host smart-0a6a6372-39f0-4a20-a66c-27bde81e55ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704470737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.704470737
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.954977639
Short name T80
Test name
Test status
Simulation time 2855534427 ps
CPU time 2.82 seconds
Started Jul 09 06:23:29 PM PDT 24
Finished Jul 09 06:23:32 PM PDT 24
Peak memory 194160 kb
Host smart-fb8b0df2-6183-452b-931c-360be7fb2b43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954977639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.954977639
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4173909639
Short name T292
Test name
Test status
Simulation time 532349462 ps
CPU time 1.41 seconds
Started Jul 09 06:23:28 PM PDT 24
Finished Jul 09 06:23:29 PM PDT 24
Peak memory 198660 kb
Host smart-0b471a04-acd4-47d0-991c-7118e9f1e2c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173909639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4173909639
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2594748707
Short name T378
Test name
Test status
Simulation time 8245106633 ps
CPU time 2.97 seconds
Started Jul 09 06:23:27 PM PDT 24
Finished Jul 09 06:23:30 PM PDT 24
Peak memory 198192 kb
Host smart-7f96e8ad-04b6-438a-800a-e9f416186da3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594748707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2594748707
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1484839674
Short name T330
Test name
Test status
Simulation time 555004537 ps
CPU time 0.92 seconds
Started Jul 09 06:23:29 PM PDT 24
Finished Jul 09 06:23:31 PM PDT 24
Peak memory 198352 kb
Host smart-fc10a514-4bdf-40d0-b469-d3af63640d25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484839674 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1484839674
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2258474608
Short name T65
Test name
Test status
Simulation time 544799692 ps
CPU time 0.7 seconds
Started Jul 09 06:23:32 PM PDT 24
Finished Jul 09 06:23:33 PM PDT 24
Peak memory 193356 kb
Host smart-e74d5753-0c0d-45d3-9266-507c0e56a794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258474608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2258474608
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2523357553
Short name T405
Test name
Test status
Simulation time 404909024 ps
CPU time 0.59 seconds
Started Jul 09 06:23:30 PM PDT 24
Finished Jul 09 06:23:31 PM PDT 24
Peak memory 183760 kb
Host smart-00f475f6-48a0-47e7-a177-7042faed2a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523357553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2523357553
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1036557747
Short name T349
Test name
Test status
Simulation time 1169707047 ps
CPU time 2.02 seconds
Started Jul 09 06:23:32 PM PDT 24
Finished Jul 09 06:23:34 PM PDT 24
Peak memory 193652 kb
Host smart-ff2b32cd-6292-485b-bd01-b4e176c161fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036557747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1036557747
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1542846421
Short name T286
Test name
Test status
Simulation time 607448117 ps
CPU time 2.11 seconds
Started Jul 09 06:23:32 PM PDT 24
Finished Jul 09 06:23:34 PM PDT 24
Peak memory 198644 kb
Host smart-78704b92-52a4-4219-ad6e-6951c1314577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542846421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1542846421
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2286112963
Short name T329
Test name
Test status
Simulation time 8317335107 ps
CPU time 3.11 seconds
Started Jul 09 06:23:31 PM PDT 24
Finished Jul 09 06:23:35 PM PDT 24
Peak memory 198116 kb
Host smart-4f246603-8704-4daa-8d28-f03d5faa8bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286112963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2286112963
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1359927752
Short name T36
Test name
Test status
Simulation time 619477656 ps
CPU time 1.11 seconds
Started Jul 09 06:23:33 PM PDT 24
Finished Jul 09 06:23:34 PM PDT 24
Peak memory 196996 kb
Host smart-05aafee9-7ab9-4521-a932-454d6607a00c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359927752 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1359927752
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.611356101
Short name T394
Test name
Test status
Simulation time 357894460 ps
CPU time 1.09 seconds
Started Jul 09 06:23:31 PM PDT 24
Finished Jul 09 06:23:33 PM PDT 24
Peak memory 193192 kb
Host smart-16e1a517-894e-46b5-a71b-154c1afbab7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611356101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.611356101
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3499635087
Short name T326
Test name
Test status
Simulation time 422797170 ps
CPU time 1.14 seconds
Started Jul 09 06:23:30 PM PDT 24
Finished Jul 09 06:23:31 PM PDT 24
Peak memory 183780 kb
Host smart-dc38a21a-a4bd-40aa-a335-896a638385d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499635087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3499635087
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2134384999
Short name T81
Test name
Test status
Simulation time 1240365247 ps
CPU time 1.86 seconds
Started Jul 09 06:23:34 PM PDT 24
Finished Jul 09 06:23:36 PM PDT 24
Peak memory 193668 kb
Host smart-caf4a5f5-4fa1-4a72-aeeb-990b0771a775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134384999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2134384999
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1462389250
Short name T382
Test name
Test status
Simulation time 673027442 ps
CPU time 1.44 seconds
Started Jul 09 06:23:30 PM PDT 24
Finished Jul 09 06:23:32 PM PDT 24
Peak memory 198696 kb
Host smart-4c981215-ae8c-4853-a53f-b2bd160d9b29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462389250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1462389250
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1710597180
Short name T339
Test name
Test status
Simulation time 4508408331 ps
CPU time 2.5 seconds
Started Jul 09 06:23:30 PM PDT 24
Finished Jul 09 06:23:33 PM PDT 24
Peak memory 197896 kb
Host smart-7e0412f8-2a2f-4041-a6ee-b11a35e40301
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710597180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1710597180
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3118428857
Short name T370
Test name
Test status
Simulation time 432434639 ps
CPU time 1.39 seconds
Started Jul 09 06:23:37 PM PDT 24
Finished Jul 09 06:23:39 PM PDT 24
Peak memory 197092 kb
Host smart-1f4d4e6b-149b-4af6-9650-ce813c0407b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118428857 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3118428857
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.915300730
Short name T74
Test name
Test status
Simulation time 330655586 ps
CPU time 1.05 seconds
Started Jul 09 06:23:33 PM PDT 24
Finished Jul 09 06:23:35 PM PDT 24
Peak memory 193192 kb
Host smart-8bde7dfe-36d5-491a-b923-0762956d307f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915300730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.915300730
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2115755376
Short name T386
Test name
Test status
Simulation time 369871874 ps
CPU time 0.64 seconds
Started Jul 09 06:23:36 PM PDT 24
Finished Jul 09 06:23:37 PM PDT 24
Peak memory 193000 kb
Host smart-a00c631a-3aee-4f1e-90c0-9dfdabc1acdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115755376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2115755376
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.12614894
Short name T79
Test name
Test status
Simulation time 1248990303 ps
CPU time 1.27 seconds
Started Jul 09 06:23:34 PM PDT 24
Finished Jul 09 06:23:36 PM PDT 24
Peak memory 192012 kb
Host smart-d51f18b8-464e-4f6e-bfa0-3e9aef7110b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12614894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_
timer_same_csr_outstanding.12614894
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1874829525
Short name T288
Test name
Test status
Simulation time 615313699 ps
CPU time 2.21 seconds
Started Jul 09 06:23:36 PM PDT 24
Finished Jul 09 06:23:39 PM PDT 24
Peak memory 198648 kb
Host smart-94424e64-f677-49fe-94f3-22937f56dc0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874829525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1874829525
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3192263946
Short name T350
Test name
Test status
Simulation time 4442082506 ps
CPU time 5.92 seconds
Started Jul 09 06:23:34 PM PDT 24
Finished Jul 09 06:23:40 PM PDT 24
Peak memory 196480 kb
Host smart-2e673c63-7cc9-4ca5-aae4-a5dc0302d009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192263946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3192263946
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3656731593
Short name T302
Test name
Test status
Simulation time 500526115 ps
CPU time 1.47 seconds
Started Jul 09 06:23:41 PM PDT 24
Finished Jul 09 06:23:43 PM PDT 24
Peak memory 196284 kb
Host smart-5dea97e2-a772-48fb-977c-9d25eb2f110e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656731593 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3656731593
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2508513827
Short name T396
Test name
Test status
Simulation time 431112188 ps
CPU time 0.68 seconds
Started Jul 09 06:23:38 PM PDT 24
Finished Jul 09 06:23:39 PM PDT 24
Peak memory 192108 kb
Host smart-7d43f1ea-44f4-4b2c-88c7-d47cc0a0ebda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508513827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2508513827
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2499357315
Short name T285
Test name
Test status
Simulation time 308202690 ps
CPU time 0.7 seconds
Started Jul 09 06:23:38 PM PDT 24
Finished Jul 09 06:23:39 PM PDT 24
Peak memory 183764 kb
Host smart-4c96bcbb-2119-4e61-8047-c23f230a154f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499357315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2499357315
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3015899481
Short name T321
Test name
Test status
Simulation time 1884464194 ps
CPU time 0.89 seconds
Started Jul 09 06:23:37 PM PDT 24
Finished Jul 09 06:23:38 PM PDT 24
Peak memory 193344 kb
Host smart-d732db48-9ba4-40fc-abc4-3ca4ed4e06fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015899481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3015899481
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2254714438
Short name T346
Test name
Test status
Simulation time 570184887 ps
CPU time 1.93 seconds
Started Jul 09 06:23:45 PM PDT 24
Finished Jul 09 06:23:47 PM PDT 24
Peak memory 198684 kb
Host smart-672db311-d25b-4eff-a025-d8176887ade5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254714438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2254714438
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3389301040
Short name T40
Test name
Test status
Simulation time 8284832980 ps
CPU time 2.01 seconds
Started Jul 09 06:23:37 PM PDT 24
Finished Jul 09 06:23:39 PM PDT 24
Peak memory 198264 kb
Host smart-c3490977-68f8-4c39-bbce-4d918b84a59d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389301040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3389301040
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3362031726
Short name T380
Test name
Test status
Simulation time 459662448 ps
CPU time 1.06 seconds
Started Jul 09 06:23:44 PM PDT 24
Finished Jul 09 06:23:46 PM PDT 24
Peak memory 197072 kb
Host smart-028c156d-1a91-49ad-989d-61e67c5761ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362031726 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3362031726
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3628732387
Short name T76
Test name
Test status
Simulation time 469781598 ps
CPU time 1.13 seconds
Started Jul 09 06:23:44 PM PDT 24
Finished Jul 09 06:23:46 PM PDT 24
Peak memory 192072 kb
Host smart-6926a8bf-8b55-4678-941e-b24a7ed537c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628732387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3628732387
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2493583271
Short name T328
Test name
Test status
Simulation time 481741669 ps
CPU time 0.63 seconds
Started Jul 09 06:23:42 PM PDT 24
Finished Jul 09 06:23:43 PM PDT 24
Peak memory 183700 kb
Host smart-d21ff60b-0133-4e30-a818-d4187426bfb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493583271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2493583271
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.737631570
Short name T363
Test name
Test status
Simulation time 1155531483 ps
CPU time 1.92 seconds
Started Jul 09 06:23:45 PM PDT 24
Finished Jul 09 06:23:47 PM PDT 24
Peak memory 193032 kb
Host smart-b594a3a6-c9cc-4a7c-b168-82558cb0bbfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737631570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.737631570
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2654670071
Short name T315
Test name
Test status
Simulation time 664446586 ps
CPU time 2.22 seconds
Started Jul 09 06:23:42 PM PDT 24
Finished Jul 09 06:23:44 PM PDT 24
Peak memory 198672 kb
Host smart-5b78d2c8-4398-411c-85d1-fcc96de41dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654670071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2654670071
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3129514045
Short name T333
Test name
Test status
Simulation time 4115879966 ps
CPU time 7.03 seconds
Started Jul 09 06:23:41 PM PDT 24
Finished Jul 09 06:23:49 PM PDT 24
Peak memory 197736 kb
Host smart-0e2ab487-4288-4cbe-925a-79c7886f63ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129514045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3129514045
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.859005538
Short name T374
Test name
Test status
Simulation time 423146425 ps
CPU time 0.81 seconds
Started Jul 09 06:23:49 PM PDT 24
Finished Jul 09 06:23:50 PM PDT 24
Peak memory 196448 kb
Host smart-a24c360a-26c6-454b-8ad0-0289a45b19d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859005538 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.859005538
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1668720169
Short name T416
Test name
Test status
Simulation time 521335059 ps
CPU time 0.78 seconds
Started Jul 09 06:23:50 PM PDT 24
Finished Jul 09 06:23:51 PM PDT 24
Peak memory 193264 kb
Host smart-99cbe38e-e033-45e1-a9c6-d3fdd2d3a658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668720169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1668720169
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.620564708
Short name T284
Test name
Test status
Simulation time 511900792 ps
CPU time 1.29 seconds
Started Jul 09 06:23:44 PM PDT 24
Finished Jul 09 06:23:46 PM PDT 24
Peak memory 192988 kb
Host smart-b3b52558-e009-43e8-91c0-490678d72606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620564708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.620564708
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1648912929
Short name T354
Test name
Test status
Simulation time 1411850447 ps
CPU time 2.65 seconds
Started Jul 09 06:23:44 PM PDT 24
Finished Jul 09 06:23:47 PM PDT 24
Peak memory 183824 kb
Host smart-ec9907c9-669c-4c7c-b78d-e57c35f0e61e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648912929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1648912929
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1066725166
Short name T406
Test name
Test status
Simulation time 385238539 ps
CPU time 1.61 seconds
Started Jul 09 06:23:43 PM PDT 24
Finished Jul 09 06:23:46 PM PDT 24
Peak memory 198688 kb
Host smart-75dbf9a6-7e81-4e3f-aa15-6a40e802778e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066725166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1066725166
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1657054154
Short name T196
Test name
Test status
Simulation time 8898110081 ps
CPU time 12.19 seconds
Started Jul 09 06:23:45 PM PDT 24
Finished Jul 09 06:23:57 PM PDT 24
Peak memory 198272 kb
Host smart-df1f4195-e241-43d7-ba9c-87cade4347fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657054154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1657054154
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2837553563
Short name T309
Test name
Test status
Simulation time 531126690 ps
CPU time 1.39 seconds
Started Jul 09 06:23:51 PM PDT 24
Finished Jul 09 06:23:52 PM PDT 24
Peak memory 195972 kb
Host smart-3d1bd437-3e4a-4b2c-87a1-0282196c9666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837553563 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2837553563
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.959431992
Short name T399
Test name
Test status
Simulation time 498758863 ps
CPU time 1.34 seconds
Started Jul 09 06:23:51 PM PDT 24
Finished Jul 09 06:23:53 PM PDT 24
Peak memory 193040 kb
Host smart-17849313-3b3f-4591-919c-e32721e77376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959431992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.959431992
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1236427544
Short name T411
Test name
Test status
Simulation time 362404302 ps
CPU time 0.67 seconds
Started Jul 09 06:23:46 PM PDT 24
Finished Jul 09 06:23:47 PM PDT 24
Peak memory 183748 kb
Host smart-35cedffb-3996-4d6d-b8da-f92539fcec43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236427544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1236427544
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1931602571
Short name T342
Test name
Test status
Simulation time 2399531757 ps
CPU time 1.35 seconds
Started Jul 09 06:23:50 PM PDT 24
Finished Jul 09 06:23:52 PM PDT 24
Peak memory 195052 kb
Host smart-56742258-e142-4c73-85d6-7f6336af297d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931602571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1931602571
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2308350501
Short name T353
Test name
Test status
Simulation time 528622222 ps
CPU time 1.22 seconds
Started Jul 09 06:23:47 PM PDT 24
Finished Jul 09 06:23:48 PM PDT 24
Peak memory 198472 kb
Host smart-fa06972d-7a76-481d-b5cb-0fd99d592875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308350501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2308350501
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.42309053
Short name T334
Test name
Test status
Simulation time 7929507872 ps
CPU time 3.59 seconds
Started Jul 09 06:23:47 PM PDT 24
Finished Jul 09 06:23:51 PM PDT 24
Peak memory 198376 kb
Host smart-5948453f-16f7-4441-b96d-4c898bdaad29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42309053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_
intg_err.42309053
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2655880042
Short name T299
Test name
Test status
Simulation time 484182632 ps
CPU time 1 seconds
Started Jul 09 06:24:05 PM PDT 24
Finished Jul 09 06:24:06 PM PDT 24
Peak memory 196008 kb
Host smart-377cfa80-0d6b-412e-b0f6-5f92b0d4639a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655880042 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2655880042
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2532163445
Short name T61
Test name
Test status
Simulation time 516622626 ps
CPU time 0.77 seconds
Started Jul 09 06:23:55 PM PDT 24
Finished Jul 09 06:23:56 PM PDT 24
Peak memory 193056 kb
Host smart-1a3d24a9-5191-4371-90ec-3947dcf31506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532163445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2532163445
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1130195456
Short name T314
Test name
Test status
Simulation time 525521674 ps
CPU time 0.68 seconds
Started Jul 09 06:23:54 PM PDT 24
Finished Jul 09 06:23:55 PM PDT 24
Peak memory 183740 kb
Host smart-e5bdc081-97eb-42bc-bbb7-b45042de07b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130195456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1130195456
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.752035655
Short name T403
Test name
Test status
Simulation time 943098067 ps
CPU time 1.72 seconds
Started Jul 09 06:23:54 PM PDT 24
Finished Jul 09 06:23:56 PM PDT 24
Peak memory 193052 kb
Host smart-6bad967b-e9e1-4bdf-920a-87da298d4ba9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752035655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.752035655
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1268891573
Short name T276
Test name
Test status
Simulation time 434766674 ps
CPU time 1.22 seconds
Started Jul 09 06:23:52 PM PDT 24
Finished Jul 09 06:23:53 PM PDT 24
Peak memory 198492 kb
Host smart-5d3de8b0-0d49-4909-a71a-78bc4403f47f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268891573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1268891573
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2714828251
Short name T39
Test name
Test status
Simulation time 4584647231 ps
CPU time 1.61 seconds
Started Jul 09 06:24:05 PM PDT 24
Finished Jul 09 06:24:07 PM PDT 24
Peak memory 197728 kb
Host smart-ce763906-a45a-4a77-9024-f96ea0c365a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714828251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2714828251
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1972131478
Short name T335
Test name
Test status
Simulation time 573607441 ps
CPU time 1.46 seconds
Started Jul 09 06:23:55 PM PDT 24
Finished Jul 09 06:23:57 PM PDT 24
Peak memory 196640 kb
Host smart-fee9c9af-163a-4dd6-8504-685c50036bfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972131478 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1972131478
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.377359696
Short name T66
Test name
Test status
Simulation time 379425114 ps
CPU time 0.74 seconds
Started Jul 09 06:24:06 PM PDT 24
Finished Jul 09 06:24:07 PM PDT 24
Peak memory 193036 kb
Host smart-3b14690b-38b1-4d08-b6b1-215349f2634b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377359696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.377359696
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1568145168
Short name T327
Test name
Test status
Simulation time 412184749 ps
CPU time 0.7 seconds
Started Jul 09 06:23:55 PM PDT 24
Finished Jul 09 06:23:56 PM PDT 24
Peak memory 183756 kb
Host smart-6ac687c6-c0bb-4122-a2f4-b79a18516cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568145168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1568145168
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2548663119
Short name T400
Test name
Test status
Simulation time 2146963033 ps
CPU time 3.29 seconds
Started Jul 09 06:24:05 PM PDT 24
Finished Jul 09 06:24:08 PM PDT 24
Peak memory 193908 kb
Host smart-6c0613ec-83f3-48e5-a017-cafc04fdda2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548663119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2548663119
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.713837140
Short name T384
Test name
Test status
Simulation time 743389831 ps
CPU time 2.22 seconds
Started Jul 09 06:23:55 PM PDT 24
Finished Jul 09 06:23:57 PM PDT 24
Peak memory 198680 kb
Host smart-2cf523de-7043-4b3a-bd2a-f4c5c705ddae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713837140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.713837140
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4011020973
Short name T387
Test name
Test status
Simulation time 4317401490 ps
CPU time 2.39 seconds
Started Jul 09 06:23:55 PM PDT 24
Finished Jul 09 06:23:58 PM PDT 24
Peak memory 197644 kb
Host smart-36ee555b-1327-4051-b87f-d63d271a35df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011020973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.4011020973
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2076129608
Short name T64
Test name
Test status
Simulation time 819115388 ps
CPU time 0.86 seconds
Started Jul 09 06:22:56 PM PDT 24
Finished Jul 09 06:22:58 PM PDT 24
Peak memory 194732 kb
Host smart-22f34f93-50c8-4da8-8499-390f0f37d854
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076129608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2076129608
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4118133120
Short name T41
Test name
Test status
Simulation time 7372233585 ps
CPU time 6.46 seconds
Started Jul 09 06:22:53 PM PDT 24
Finished Jul 09 06:23:00 PM PDT 24
Peak memory 192280 kb
Host smart-02949d35-c0bf-4994-85b8-65c1199abdb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118133120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4118133120
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1704073306
Short name T304
Test name
Test status
Simulation time 705809154 ps
CPU time 1.6 seconds
Started Jul 09 06:22:51 PM PDT 24
Finished Jul 09 06:22:54 PM PDT 24
Peak memory 192188 kb
Host smart-d9dfd62d-16db-4108-be89-45c8903262a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704073306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1704073306
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2666401339
Short name T373
Test name
Test status
Simulation time 475272301 ps
CPU time 0.73 seconds
Started Jul 09 06:22:57 PM PDT 24
Finished Jul 09 06:22:59 PM PDT 24
Peak memory 196108 kb
Host smart-bfc2b43e-24b3-42fa-8ee4-9ab74332f1e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666401339 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2666401339
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4220429012
Short name T361
Test name
Test status
Simulation time 454194903 ps
CPU time 0.75 seconds
Started Jul 09 06:22:55 PM PDT 24
Finished Jul 09 06:22:56 PM PDT 24
Peak memory 194064 kb
Host smart-9fe6a000-15d1-40b2-bda0-56e7003f3105
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220429012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.4220429012
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2258014606
Short name T277
Test name
Test status
Simulation time 344395907 ps
CPU time 1.05 seconds
Started Jul 09 06:22:50 PM PDT 24
Finished Jul 09 06:22:52 PM PDT 24
Peak memory 183776 kb
Host smart-680eb230-1082-41a2-bfa4-35d5c3ab9cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258014606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2258014606
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1969610108
Short name T278
Test name
Test status
Simulation time 409234195 ps
CPU time 0.58 seconds
Started Jul 09 06:22:55 PM PDT 24
Finished Jul 09 06:22:55 PM PDT 24
Peak memory 183688 kb
Host smart-84e11896-3d1c-457e-acf0-65ff6aeeb5d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969610108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1969610108
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.548930348
Short name T376
Test name
Test status
Simulation time 419129044 ps
CPU time 0.64 seconds
Started Jul 09 06:22:52 PM PDT 24
Finished Jul 09 06:22:53 PM PDT 24
Peak memory 183708 kb
Host smart-7dba4084-6d32-43b4-9265-e33659b5ba7c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548930348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.548930348
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1087805408
Short name T356
Test name
Test status
Simulation time 2667508807 ps
CPU time 2.06 seconds
Started Jul 09 06:22:56 PM PDT 24
Finished Jul 09 06:22:58 PM PDT 24
Peak memory 194116 kb
Host smart-141c66dd-9d74-425a-b7e7-05b2398ef74b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087805408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1087805408
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4097441063
Short name T344
Test name
Test status
Simulation time 966925828 ps
CPU time 2.89 seconds
Started Jul 09 06:22:52 PM PDT 24
Finished Jul 09 06:22:55 PM PDT 24
Peak memory 198704 kb
Host smart-59934b33-aad4-455d-b981-43cb1d550391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097441063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4097441063
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.115310257
Short name T193
Test name
Test status
Simulation time 8948728108 ps
CPU time 3.5 seconds
Started Jul 09 06:22:53 PM PDT 24
Finished Jul 09 06:22:57 PM PDT 24
Peak memory 198224 kb
Host smart-8ea6ee5d-1af1-4cd9-9c19-0b7783b108ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115310257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.115310257
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3471988074
Short name T367
Test name
Test status
Simulation time 284540644 ps
CPU time 1.02 seconds
Started Jul 09 06:23:56 PM PDT 24
Finished Jul 09 06:23:58 PM PDT 24
Peak memory 183752 kb
Host smart-63bcc189-9cba-4433-a0fc-c348026bb2a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471988074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3471988074
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1476925481
Short name T417
Test name
Test status
Simulation time 409471124 ps
CPU time 0.71 seconds
Started Jul 09 06:23:53 PM PDT 24
Finished Jul 09 06:23:54 PM PDT 24
Peak memory 192944 kb
Host smart-df4e8d9b-fade-4de2-8a67-2ad838c93474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476925481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1476925481
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3592661897
Short name T345
Test name
Test status
Simulation time 323443105 ps
CPU time 0.77 seconds
Started Jul 09 06:24:04 PM PDT 24
Finished Jul 09 06:24:05 PM PDT 24
Peak memory 183768 kb
Host smart-c40410e7-4102-44fc-8a86-a3872f1dd595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592661897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3592661897
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3542951891
Short name T343
Test name
Test status
Simulation time 436252964 ps
CPU time 0.82 seconds
Started Jul 09 06:23:56 PM PDT 24
Finished Jul 09 06:23:57 PM PDT 24
Peak memory 183744 kb
Host smart-628eda97-74a7-441c-9a19-a87158104b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542951891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3542951891
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.787710836
Short name T393
Test name
Test status
Simulation time 492683523 ps
CPU time 0.7 seconds
Started Jul 09 06:23:54 PM PDT 24
Finished Jul 09 06:23:55 PM PDT 24
Peak memory 183776 kb
Host smart-51831f07-b3cf-4932-982f-189fd1458e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787710836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.787710836
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.881618949
Short name T366
Test name
Test status
Simulation time 326360001 ps
CPU time 0.95 seconds
Started Jul 09 06:23:56 PM PDT 24
Finished Jul 09 06:23:58 PM PDT 24
Peak memory 183772 kb
Host smart-fa11eb01-5c2e-446e-bf35-93abc1d7aa48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881618949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.881618949
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3337407008
Short name T300
Test name
Test status
Simulation time 425045692 ps
CPU time 0.82 seconds
Started Jul 09 06:24:00 PM PDT 24
Finished Jul 09 06:24:01 PM PDT 24
Peak memory 192968 kb
Host smart-370fd34d-08d1-4c5d-9338-14cc869ea46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337407008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3337407008
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2705011359
Short name T337
Test name
Test status
Simulation time 323693601 ps
CPU time 0.99 seconds
Started Jul 09 06:23:59 PM PDT 24
Finished Jul 09 06:24:01 PM PDT 24
Peak memory 192988 kb
Host smart-cc8845fe-58b9-4d62-bd6d-108e74b6c5a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705011359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2705011359
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1091265019
Short name T307
Test name
Test status
Simulation time 332221809 ps
CPU time 0.68 seconds
Started Jul 09 06:24:00 PM PDT 24
Finished Jul 09 06:24:01 PM PDT 24
Peak memory 193000 kb
Host smart-253a5c71-6219-40ec-bb65-e5e8b1e45759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091265019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1091265019
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1873287874
Short name T385
Test name
Test status
Simulation time 448633779 ps
CPU time 0.85 seconds
Started Jul 09 06:24:01 PM PDT 24
Finished Jul 09 06:24:03 PM PDT 24
Peak memory 183792 kb
Host smart-f4254099-7f7a-4573-b588-9ac4d533e143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873287874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1873287874
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1630156827
Short name T69
Test name
Test status
Simulation time 483765756 ps
CPU time 1.34 seconds
Started Jul 09 06:23:05 PM PDT 24
Finished Jul 09 06:23:07 PM PDT 24
Peak memory 193216 kb
Host smart-87e65328-80b8-422d-8315-196310a025f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630156827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1630156827
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2059744956
Short name T412
Test name
Test status
Simulation time 13300009900 ps
CPU time 25.25 seconds
Started Jul 09 06:22:59 PM PDT 24
Finished Jul 09 06:23:24 PM PDT 24
Peak memory 184040 kb
Host smart-a9821958-61cd-4ba8-aae3-7a481d31980c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059744956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2059744956
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1832084671
Short name T357
Test name
Test status
Simulation time 812020044 ps
CPU time 1.79 seconds
Started Jul 09 06:23:01 PM PDT 24
Finished Jul 09 06:23:03 PM PDT 24
Peak memory 183832 kb
Host smart-6271fd10-c13e-4ad7-818d-c8af47ea92d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832084671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1832084671
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.197659521
Short name T383
Test name
Test status
Simulation time 453571118 ps
CPU time 1.35 seconds
Started Jul 09 06:23:03 PM PDT 24
Finished Jul 09 06:23:05 PM PDT 24
Peak memory 196580 kb
Host smart-477f4f55-e889-47ba-aec2-5de2661b0683
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197659521 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.197659521
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.542905085
Short name T401
Test name
Test status
Simulation time 478369305 ps
CPU time 0.75 seconds
Started Jul 09 06:23:01 PM PDT 24
Finished Jul 09 06:23:02 PM PDT 24
Peak memory 193252 kb
Host smart-39b4eead-2bf1-4378-bfc5-412e9cebd5e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542905085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.542905085
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.888783684
Short name T391
Test name
Test status
Simulation time 265823207 ps
CPU time 0.89 seconds
Started Jul 09 06:22:58 PM PDT 24
Finished Jul 09 06:23:00 PM PDT 24
Peak memory 183776 kb
Host smart-5d932fd3-b8f5-4d9e-8081-e75a77366bd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888783684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.888783684
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2016927860
Short name T290
Test name
Test status
Simulation time 428295543 ps
CPU time 1.05 seconds
Started Jul 09 06:23:00 PM PDT 24
Finished Jul 09 06:23:01 PM PDT 24
Peak memory 183608 kb
Host smart-0082f7f0-772f-49b5-9720-7b6cd2357517
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016927860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2016927860
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3213987251
Short name T365
Test name
Test status
Simulation time 343440974 ps
CPU time 0.58 seconds
Started Jul 09 06:22:56 PM PDT 24
Finished Jul 09 06:22:57 PM PDT 24
Peak memory 183752 kb
Host smart-7eb63575-7e0f-49bf-962d-6dd8edc63ee3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213987251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3213987251
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2345322969
Short name T78
Test name
Test status
Simulation time 1409398370 ps
CPU time 2.6 seconds
Started Jul 09 06:23:03 PM PDT 24
Finished Jul 09 06:23:06 PM PDT 24
Peak memory 194196 kb
Host smart-9ae00ad6-dd6a-400d-91a4-a37754e6410a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345322969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2345322969
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1623375384
Short name T360
Test name
Test status
Simulation time 677959948 ps
CPU time 2.26 seconds
Started Jul 09 06:22:57 PM PDT 24
Finished Jul 09 06:23:00 PM PDT 24
Peak memory 198620 kb
Host smart-0e124cad-3e3b-4b6a-863e-3ad77fa9f20f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623375384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1623375384
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2355642264
Short name T319
Test name
Test status
Simulation time 4452467421 ps
CPU time 4.3 seconds
Started Jul 09 06:22:56 PM PDT 24
Finished Jul 09 06:23:01 PM PDT 24
Peak memory 197628 kb
Host smart-0af6c1a0-2608-4e3b-8619-e36caf85f7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355642264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2355642264
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1628945626
Short name T312
Test name
Test status
Simulation time 425068761 ps
CPU time 0.69 seconds
Started Jul 09 06:23:59 PM PDT 24
Finished Jul 09 06:24:00 PM PDT 24
Peak memory 192976 kb
Host smart-ebc77d48-ca70-4abd-8140-c73e156162dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628945626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1628945626
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2627554846
Short name T305
Test name
Test status
Simulation time 425099733 ps
CPU time 1.21 seconds
Started Jul 09 06:23:59 PM PDT 24
Finished Jul 09 06:24:01 PM PDT 24
Peak memory 183780 kb
Host smart-b47bcde8-5911-49c6-88fb-2d0a5bcf9990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627554846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2627554846
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1657319914
Short name T324
Test name
Test status
Simulation time 406848890 ps
CPU time 0.67 seconds
Started Jul 09 06:24:00 PM PDT 24
Finished Jul 09 06:24:00 PM PDT 24
Peak memory 183748 kb
Host smart-d8130e45-16aa-44f2-ab06-9e369598f675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657319914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1657319914
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3082837881
Short name T323
Test name
Test status
Simulation time 511632458 ps
CPU time 0.67 seconds
Started Jul 09 06:24:00 PM PDT 24
Finished Jul 09 06:24:01 PM PDT 24
Peak memory 183720 kb
Host smart-2508dbbe-b181-41fb-833b-b32349b78f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082837881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3082837881
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1170186693
Short name T310
Test name
Test status
Simulation time 440487887 ps
CPU time 0.72 seconds
Started Jul 09 06:24:03 PM PDT 24
Finished Jul 09 06:24:04 PM PDT 24
Peak memory 183716 kb
Host smart-aac4c1b8-add3-4987-a9f0-b9111c60d1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170186693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1170186693
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4198079082
Short name T297
Test name
Test status
Simulation time 451343659 ps
CPU time 1.2 seconds
Started Jul 09 06:24:03 PM PDT 24
Finished Jul 09 06:24:04 PM PDT 24
Peak memory 193012 kb
Host smart-d4139cf6-b760-4a00-9e69-af4e13be8c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198079082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.4198079082
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1765141741
Short name T317
Test name
Test status
Simulation time 468555267 ps
CPU time 0.86 seconds
Started Jul 09 06:24:03 PM PDT 24
Finished Jul 09 06:24:04 PM PDT 24
Peak memory 193140 kb
Host smart-59a3c6dd-4b5c-403e-ae7b-a514d91a9e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765141741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1765141741
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2804127702
Short name T369
Test name
Test status
Simulation time 478560915 ps
CPU time 0.76 seconds
Started Jul 09 06:24:02 PM PDT 24
Finished Jul 09 06:24:03 PM PDT 24
Peak memory 183756 kb
Host smart-b28b908b-938c-4641-a3ae-047bae19d3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804127702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2804127702
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2013189829
Short name T279
Test name
Test status
Simulation time 450663276 ps
CPU time 1.19 seconds
Started Jul 09 06:24:03 PM PDT 24
Finished Jul 09 06:24:05 PM PDT 24
Peak memory 192988 kb
Host smart-5b92dba9-7e5f-46af-9f4a-90c15267efe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013189829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2013189829
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3839759598
Short name T291
Test name
Test status
Simulation time 398305465 ps
CPU time 0.71 seconds
Started Jul 09 06:24:01 PM PDT 24
Finished Jul 09 06:24:02 PM PDT 24
Peak memory 192980 kb
Host smart-accfc084-81c7-405c-aed1-bd7f62bc26fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839759598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3839759598
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1923498743
Short name T73
Test name
Test status
Simulation time 479813417 ps
CPU time 1.37 seconds
Started Jul 09 06:23:15 PM PDT 24
Finished Jul 09 06:23:17 PM PDT 24
Peak memory 193248 kb
Host smart-c749dca6-d161-49fd-a39b-67524e6121a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923498743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1923498743
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1592908832
Short name T379
Test name
Test status
Simulation time 7454257322 ps
CPU time 3.29 seconds
Started Jul 09 06:23:11 PM PDT 24
Finished Jul 09 06:23:15 PM PDT 24
Peak memory 192224 kb
Host smart-4eac407e-d155-4efb-b5e0-82ea9a92febb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592908832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1592908832
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2726195452
Short name T60
Test name
Test status
Simulation time 1064177802 ps
CPU time 1.3 seconds
Started Jul 09 06:23:11 PM PDT 24
Finished Jul 09 06:23:13 PM PDT 24
Peak memory 183824 kb
Host smart-ab3a74c2-bc85-4bbc-af44-dbd742feea8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726195452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2726195452
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3639839163
Short name T296
Test name
Test status
Simulation time 466091884 ps
CPU time 0.98 seconds
Started Jul 09 06:23:15 PM PDT 24
Finished Jul 09 06:23:16 PM PDT 24
Peak memory 196128 kb
Host smart-8d095217-718c-4ad1-9d8f-35c2e1c6f3b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639839163 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3639839163
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.111880130
Short name T418
Test name
Test status
Simulation time 481632112 ps
CPU time 0.74 seconds
Started Jul 09 06:23:12 PM PDT 24
Finished Jul 09 06:23:13 PM PDT 24
Peak memory 193040 kb
Host smart-8c029c09-9087-4f41-9ac4-dd12f7fd4693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111880130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.111880130
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1205151293
Short name T348
Test name
Test status
Simulation time 293033359 ps
CPU time 0.63 seconds
Started Jul 09 06:23:06 PM PDT 24
Finished Jul 09 06:23:07 PM PDT 24
Peak memory 183748 kb
Host smart-72ac2a9a-b018-4d68-afdf-87d96260827f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205151293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1205151293
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4262490567
Short name T318
Test name
Test status
Simulation time 473171202 ps
CPU time 0.87 seconds
Started Jul 09 06:23:10 PM PDT 24
Finished Jul 09 06:23:11 PM PDT 24
Peak memory 183664 kb
Host smart-4862ed1a-daf1-431b-814e-3371122de25a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262490567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4262490567
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2602252096
Short name T388
Test name
Test status
Simulation time 279569444 ps
CPU time 0.73 seconds
Started Jul 09 06:23:07 PM PDT 24
Finished Jul 09 06:23:08 PM PDT 24
Peak memory 183756 kb
Host smart-08984775-38ca-4a69-b735-039524b77006
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602252096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2602252096
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2962709571
Short name T364
Test name
Test status
Simulation time 3009530015 ps
CPU time 4.45 seconds
Started Jul 09 06:23:14 PM PDT 24
Finished Jul 09 06:23:19 PM PDT 24
Peak memory 195364 kb
Host smart-1458e23e-e5ca-45b6-86ec-e170a4d27ee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962709571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2962709571
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3349618216
Short name T368
Test name
Test status
Simulation time 458806137 ps
CPU time 1.24 seconds
Started Jul 09 06:23:07 PM PDT 24
Finished Jul 09 06:23:09 PM PDT 24
Peak memory 198572 kb
Host smart-c311de30-ff72-4714-8d1f-df34284f373d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349618216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3349618216
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1084577413
Short name T413
Test name
Test status
Simulation time 4243124407 ps
CPU time 4.25 seconds
Started Jul 09 06:23:05 PM PDT 24
Finished Jul 09 06:23:10 PM PDT 24
Peak memory 198040 kb
Host smart-f92cd205-e57f-4bf0-b332-d9de3e33611e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084577413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1084577413
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4159125099
Short name T352
Test name
Test status
Simulation time 409679129 ps
CPU time 0.77 seconds
Started Jul 09 06:24:03 PM PDT 24
Finished Jul 09 06:24:04 PM PDT 24
Peak memory 183760 kb
Host smart-e753e1bb-5e91-4a1f-84e6-2886bd28bc34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159125099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4159125099
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3481485896
Short name T283
Test name
Test status
Simulation time 348808982 ps
CPU time 1.07 seconds
Started Jul 09 06:24:02 PM PDT 24
Finished Jul 09 06:24:03 PM PDT 24
Peak memory 193012 kb
Host smart-39dde3a6-6371-4a19-ad08-7f16941b7556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481485896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3481485896
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2819993805
Short name T281
Test name
Test status
Simulation time 396585724 ps
CPU time 1.09 seconds
Started Jul 09 06:24:01 PM PDT 24
Finished Jul 09 06:24:02 PM PDT 24
Peak memory 192944 kb
Host smart-ae90d67d-4590-46b3-bebc-e61425b5c0ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819993805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2819993805
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.517946451
Short name T320
Test name
Test status
Simulation time 291482582 ps
CPU time 0.99 seconds
Started Jul 09 06:24:06 PM PDT 24
Finished Jul 09 06:24:07 PM PDT 24
Peak memory 193144 kb
Host smart-d6b18650-7fb7-460b-9ddc-f34bf66ea753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517946451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.517946451
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1550528169
Short name T325
Test name
Test status
Simulation time 373407058 ps
CPU time 0.72 seconds
Started Jul 09 06:24:05 PM PDT 24
Finished Jul 09 06:24:06 PM PDT 24
Peak memory 193004 kb
Host smart-6eb68c75-729d-40ea-9161-124071a7a26d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550528169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1550528169
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2836652030
Short name T347
Test name
Test status
Simulation time 424306620 ps
CPU time 0.71 seconds
Started Jul 09 06:24:07 PM PDT 24
Finished Jul 09 06:24:08 PM PDT 24
Peak memory 183784 kb
Host smart-fe9e1d3c-b7e0-46a4-a8e6-fc72bc047bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836652030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2836652030
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1036230227
Short name T341
Test name
Test status
Simulation time 329761705 ps
CPU time 0.76 seconds
Started Jul 09 06:24:07 PM PDT 24
Finished Jul 09 06:24:08 PM PDT 24
Peak memory 193004 kb
Host smart-920060ef-471f-47d4-9658-ff92cd7339b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036230227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1036230227
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3058668293
Short name T355
Test name
Test status
Simulation time 433415084 ps
CPU time 0.68 seconds
Started Jul 09 06:24:08 PM PDT 24
Finished Jul 09 06:24:09 PM PDT 24
Peak memory 183764 kb
Host smart-7da5ed33-8a79-417f-ae3e-357c70f21b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058668293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3058668293
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.109603231
Short name T409
Test name
Test status
Simulation time 283049406 ps
CPU time 0.92 seconds
Started Jul 09 06:24:06 PM PDT 24
Finished Jul 09 06:24:08 PM PDT 24
Peak memory 183772 kb
Host smart-782ff60a-d6f0-45ad-b240-d3935c56e9f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109603231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.109603231
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.260340801
Short name T398
Test name
Test status
Simulation time 349646570 ps
CPU time 0.89 seconds
Started Jul 09 06:24:05 PM PDT 24
Finished Jul 09 06:24:06 PM PDT 24
Peak memory 192984 kb
Host smart-4564674f-15f9-45ab-bb2d-ec3132d135ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260340801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.260340801
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.730010257
Short name T308
Test name
Test status
Simulation time 369897069 ps
CPU time 0.85 seconds
Started Jul 09 06:23:18 PM PDT 24
Finished Jul 09 06:23:19 PM PDT 24
Peak memory 196456 kb
Host smart-69b0681f-647b-4063-a8f9-0c6bcf193401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730010257 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.730010257
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3792073024
Short name T298
Test name
Test status
Simulation time 593100168 ps
CPU time 0.67 seconds
Started Jul 09 06:23:18 PM PDT 24
Finished Jul 09 06:23:20 PM PDT 24
Peak memory 193196 kb
Host smart-38d71f01-03c0-4900-971d-2c17822c46c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792073024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3792073024
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3215956095
Short name T301
Test name
Test status
Simulation time 421051281 ps
CPU time 0.84 seconds
Started Jul 09 06:23:18 PM PDT 24
Finished Jul 09 06:23:19 PM PDT 24
Peak memory 192980 kb
Host smart-4762dca3-35bf-4647-87c4-a93b72bc9cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215956095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3215956095
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.954875872
Short name T322
Test name
Test status
Simulation time 1363350321 ps
CPU time 3.09 seconds
Started Jul 09 06:23:18 PM PDT 24
Finished Jul 09 06:23:22 PM PDT 24
Peak memory 193064 kb
Host smart-cbf38d4d-aefb-4782-ac28-91e0f9fe43a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954875872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.954875872
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1798016052
Short name T402
Test name
Test status
Simulation time 614038731 ps
CPU time 1.84 seconds
Started Jul 09 06:23:17 PM PDT 24
Finished Jul 09 06:23:20 PM PDT 24
Peak memory 198648 kb
Host smart-2fdb7a71-d9c6-4bb9-9bc8-a3ad6e0f35c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798016052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1798016052
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2342785689
Short name T195
Test name
Test status
Simulation time 4325546561 ps
CPU time 7.07 seconds
Started Jul 09 06:23:17 PM PDT 24
Finished Jul 09 06:23:25 PM PDT 24
Peak memory 197856 kb
Host smart-a3a18d92-b41f-457a-a860-645449fa9cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342785689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2342785689
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3602508818
Short name T294
Test name
Test status
Simulation time 577738426 ps
CPU time 1.42 seconds
Started Jul 09 06:23:21 PM PDT 24
Finished Jul 09 06:23:22 PM PDT 24
Peak memory 195624 kb
Host smart-3ed1ee79-f733-43b4-ad57-237c15231415
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602508818 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3602508818
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.847644007
Short name T71
Test name
Test status
Simulation time 405685194 ps
CPU time 1.25 seconds
Started Jul 09 06:23:20 PM PDT 24
Finished Jul 09 06:23:22 PM PDT 24
Peak memory 193288 kb
Host smart-6d815082-c9ee-4450-8c51-a89e5b90c4b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847644007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.847644007
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3341954209
Short name T351
Test name
Test status
Simulation time 326208941 ps
CPU time 0.99 seconds
Started Jul 09 06:23:20 PM PDT 24
Finished Jul 09 06:23:21 PM PDT 24
Peak memory 183752 kb
Host smart-4b647802-9c64-4806-85b5-c9bd18af7719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341954209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3341954209
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2578149584
Short name T392
Test name
Test status
Simulation time 2914546251 ps
CPU time 1.7 seconds
Started Jul 09 06:23:20 PM PDT 24
Finished Jul 09 06:23:22 PM PDT 24
Peak memory 194108 kb
Host smart-bb64fa30-15a7-4f38-8315-e95b223f6ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578149584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2578149584
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.425930250
Short name T381
Test name
Test status
Simulation time 801856881 ps
CPU time 2.14 seconds
Started Jul 09 06:23:17 PM PDT 24
Finished Jul 09 06:23:20 PM PDT 24
Peak memory 198676 kb
Host smart-718cd955-6d9a-4df3-8368-1fb02f59ee13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425930250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.425930250
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2751705016
Short name T306
Test name
Test status
Simulation time 7934723478 ps
CPU time 6.24 seconds
Started Jul 09 06:23:17 PM PDT 24
Finished Jul 09 06:23:24 PM PDT 24
Peak memory 198044 kb
Host smart-95152cb5-3463-4dea-a501-f42325dc9f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751705016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2751705016
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.4013878994
Short name T282
Test name
Test status
Simulation time 427229959 ps
CPU time 0.77 seconds
Started Jul 09 06:23:25 PM PDT 24
Finished Jul 09 06:23:26 PM PDT 24
Peak memory 195728 kb
Host smart-5299fea4-06b0-4c58-b10c-471e3e32c373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013878994 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.4013878994
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1434388976
Short name T311
Test name
Test status
Simulation time 340599211 ps
CPU time 1.07 seconds
Started Jul 09 06:23:24 PM PDT 24
Finished Jul 09 06:23:25 PM PDT 24
Peak memory 193188 kb
Host smart-83615388-57ec-45d7-af45-e5bc77649b6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434388976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1434388976
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.677588229
Short name T371
Test name
Test status
Simulation time 312884433 ps
CPU time 0.9 seconds
Started Jul 09 06:23:25 PM PDT 24
Finished Jul 09 06:23:26 PM PDT 24
Peak memory 192988 kb
Host smart-8795ecbd-b49f-4d2a-a6e4-6b12b6b8b3f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677588229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.677588229
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3525978551
Short name T77
Test name
Test status
Simulation time 1643071937 ps
CPU time 1.18 seconds
Started Jul 09 06:23:25 PM PDT 24
Finished Jul 09 06:23:27 PM PDT 24
Peak memory 193032 kb
Host smart-cf8ed438-d66c-48b8-a0e3-2c1a0ec2fca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525978551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3525978551
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2583834036
Short name T336
Test name
Test status
Simulation time 397874624 ps
CPU time 2.54 seconds
Started Jul 09 06:23:19 PM PDT 24
Finished Jul 09 06:23:22 PM PDT 24
Peak memory 198648 kb
Host smart-7a9579fa-127f-4347-9902-c8c452e9d222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583834036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2583834036
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3685470308
Short name T313
Test name
Test status
Simulation time 4348679034 ps
CPU time 1.7 seconds
Started Jul 09 06:23:28 PM PDT 24
Finished Jul 09 06:23:30 PM PDT 24
Peak memory 196492 kb
Host smart-aff8d19a-dace-4359-9c59-b6e16ebce0de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685470308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3685470308
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2452162625
Short name T295
Test name
Test status
Simulation time 577074570 ps
CPU time 1.06 seconds
Started Jul 09 06:23:28 PM PDT 24
Finished Jul 09 06:23:29 PM PDT 24
Peak memory 196144 kb
Host smart-d419ab7a-7c38-4684-a29f-1316f5ef2bee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452162625 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2452162625
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2087034180
Short name T332
Test name
Test status
Simulation time 318723169 ps
CPU time 1 seconds
Started Jul 09 06:23:24 PM PDT 24
Finished Jul 09 06:23:26 PM PDT 24
Peak memory 193040 kb
Host smart-11bc1367-3643-4935-973b-12517fa936f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087034180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2087034180
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1223841260
Short name T293
Test name
Test status
Simulation time 325586012 ps
CPU time 0.66 seconds
Started Jul 09 06:23:27 PM PDT 24
Finished Jul 09 06:23:28 PM PDT 24
Peak memory 183744 kb
Host smart-ce659c19-7287-4b7b-9b01-2898294b08d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223841260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1223841260
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2913855721
Short name T414
Test name
Test status
Simulation time 1151595670 ps
CPU time 3.42 seconds
Started Jul 09 06:23:25 PM PDT 24
Finished Jul 09 06:23:28 PM PDT 24
Peak memory 193800 kb
Host smart-e8180745-80af-4ac1-adea-170bad9439a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913855721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2913855721
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4014714944
Short name T404
Test name
Test status
Simulation time 482922758 ps
CPU time 2.15 seconds
Started Jul 09 06:23:28 PM PDT 24
Finished Jul 09 06:23:30 PM PDT 24
Peak memory 198592 kb
Host smart-c7b5d36d-5d25-4939-8143-635e56d14466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014714944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4014714944
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.127237780
Short name T338
Test name
Test status
Simulation time 4642392072 ps
CPU time 7.99 seconds
Started Jul 09 06:23:24 PM PDT 24
Finished Jul 09 06:23:33 PM PDT 24
Peak memory 198044 kb
Host smart-0db97a10-8f71-49ba-9404-40c447825140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127237780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.127237780
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1629237790
Short name T38
Test name
Test status
Simulation time 580634212 ps
CPU time 1.05 seconds
Started Jul 09 06:23:31 PM PDT 24
Finished Jul 09 06:23:33 PM PDT 24
Peak memory 196216 kb
Host smart-74e788c3-5bdb-4e04-9a1d-1c36aaa9b7c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629237790 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1629237790
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.560515178
Short name T375
Test name
Test status
Simulation time 472541736 ps
CPU time 1.25 seconds
Started Jul 09 06:23:26 PM PDT 24
Finished Jul 09 06:23:28 PM PDT 24
Peak memory 193056 kb
Host smart-ac8f0576-29a8-43f5-956c-a850907ae9dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560515178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.560515178
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.618991662
Short name T316
Test name
Test status
Simulation time 504239396 ps
CPU time 1.3 seconds
Started Jul 09 06:23:28 PM PDT 24
Finished Jul 09 06:23:30 PM PDT 24
Peak memory 183788 kb
Host smart-9d2f476f-4ea6-4246-b630-c98ed68138cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618991662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.618991662
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3874212153
Short name T331
Test name
Test status
Simulation time 1477576617 ps
CPU time 2.96 seconds
Started Jul 09 06:23:32 PM PDT 24
Finished Jul 09 06:23:35 PM PDT 24
Peak memory 193068 kb
Host smart-e244a351-2479-4d84-85bf-8267a530c1d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874212153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3874212153
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1758906118
Short name T287
Test name
Test status
Simulation time 336982784 ps
CPU time 2.55 seconds
Started Jul 09 06:23:31 PM PDT 24
Finished Jul 09 06:23:34 PM PDT 24
Peak memory 198652 kb
Host smart-c16a5817-58de-453e-a801-68ed71dabc4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758906118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1758906118
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1503252171
Short name T203
Test name
Test status
Simulation time 44996977469 ps
CPU time 57.12 seconds
Started Jul 09 06:18:56 PM PDT 24
Finished Jul 09 06:19:54 PM PDT 24
Peak memory 191888 kb
Host smart-aa9e199c-852b-44cd-8c2a-e746cec04594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503252171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1503252171
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.727078888
Short name T217
Test name
Test status
Simulation time 448247626 ps
CPU time 0.71 seconds
Started Jul 09 06:18:54 PM PDT 24
Finished Jul 09 06:18:55 PM PDT 24
Peak memory 191936 kb
Host smart-959b05b7-8b46-46cb-9f4d-b62cf981b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727078888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.727078888
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3273745635
Short name T86
Test name
Test status
Simulation time 42473375359 ps
CPU time 39.83 seconds
Started Jul 09 06:19:07 PM PDT 24
Finished Jul 09 06:19:47 PM PDT 24
Peak memory 196988 kb
Host smart-e39afcd5-333b-4100-94db-b2792b5b280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273745635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3273745635
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1787972623
Short name T19
Test name
Test status
Simulation time 7852328232 ps
CPU time 3.52 seconds
Started Jul 09 06:19:09 PM PDT 24
Finished Jul 09 06:19:13 PM PDT 24
Peak memory 215748 kb
Host smart-6003b0ed-2c2d-4baa-98fb-61c02bddc4b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787972623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1787972623
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3905822196
Short name T257
Test name
Test status
Simulation time 490919183 ps
CPU time 1.22 seconds
Started Jul 09 06:19:04 PM PDT 24
Finished Jul 09 06:19:06 PM PDT 24
Peak memory 191860 kb
Host smart-f3131081-ebdb-4281-bf5e-8b8b2f2f02c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905822196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3905822196
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4176466634
Short name T3
Test name
Test status
Simulation time 37481052544 ps
CPU time 11.37 seconds
Started Jul 09 06:19:56 PM PDT 24
Finished Jul 09 06:20:08 PM PDT 24
Peak memory 196952 kb
Host smart-8f3bc3de-bded-4e27-afc4-25c42627178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176466634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4176466634
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.4033187513
Short name T13
Test name
Test status
Simulation time 468196511 ps
CPU time 0.71 seconds
Started Jul 09 06:19:55 PM PDT 24
Finished Jul 09 06:19:56 PM PDT 24
Peak memory 191900 kb
Host smart-e7cf4134-4715-4418-a26f-2ea2e49418a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033187513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.4033187513
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1108532976
Short name T199
Test name
Test status
Simulation time 42627661884 ps
CPU time 60.28 seconds
Started Jul 09 06:20:02 PM PDT 24
Finished Jul 09 06:21:03 PM PDT 24
Peak memory 197000 kb
Host smart-459fc098-bc1e-40cd-b9aa-b9cce4dfeb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108532976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1108532976
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.739371995
Short name T202
Test name
Test status
Simulation time 736649238 ps
CPU time 0.62 seconds
Started Jul 09 06:20:00 PM PDT 24
Finished Jul 09 06:20:01 PM PDT 24
Peak memory 191888 kb
Host smart-de736049-5f5c-4010-a8f4-c296602a4079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739371995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.739371995
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2499830850
Short name T267
Test name
Test status
Simulation time 28837718379 ps
CPU time 23.16 seconds
Started Jul 09 06:20:06 PM PDT 24
Finished Jul 09 06:20:30 PM PDT 24
Peak memory 197016 kb
Host smart-49058e46-e63b-4417-9c10-de40998b136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499830850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2499830850
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.601816853
Short name T207
Test name
Test status
Simulation time 423790426 ps
CPU time 0.69 seconds
Started Jul 09 06:20:08 PM PDT 24
Finished Jul 09 06:20:09 PM PDT 24
Peak memory 191928 kb
Host smart-2027e6ea-8b86-45dd-8235-e3c22c78ffef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601816853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.601816853
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.906174940
Short name T11
Test name
Test status
Simulation time 36942141992 ps
CPU time 57.91 seconds
Started Jul 09 06:20:18 PM PDT 24
Finished Jul 09 06:21:16 PM PDT 24
Peak memory 191964 kb
Host smart-b54d9311-94f5-44c3-9445-dc7ddec536bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906174940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.906174940
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2281317230
Short name T228
Test name
Test status
Simulation time 426087291 ps
CPU time 0.91 seconds
Started Jul 09 06:20:13 PM PDT 24
Finished Jul 09 06:20:15 PM PDT 24
Peak memory 196804 kb
Host smart-91a044c8-a5c7-4fd5-9794-eea220ea7785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281317230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2281317230
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.47632141
Short name T242
Test name
Test status
Simulation time 27075582654 ps
CPU time 17.98 seconds
Started Jul 09 06:20:18 PM PDT 24
Finished Jul 09 06:20:37 PM PDT 24
Peak memory 196960 kb
Host smart-21867971-8778-4295-bd11-1faaf3c934ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47632141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.47632141
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3621061643
Short name T260
Test name
Test status
Simulation time 609129622 ps
CPU time 1.45 seconds
Started Jul 09 06:20:17 PM PDT 24
Finished Jul 09 06:20:19 PM PDT 24
Peak memory 196724 kb
Host smart-51c9d3f5-d95f-4d15-8455-5f4eab31de41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621061643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3621061643
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.258992534
Short name T224
Test name
Test status
Simulation time 637876516 ps
CPU time 1.52 seconds
Started Jul 09 06:20:18 PM PDT 24
Finished Jul 09 06:20:19 PM PDT 24
Peak memory 196644 kb
Host smart-1a6033de-11b8-4845-ab25-14305d69dcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258992534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.258992534
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.585542402
Short name T245
Test name
Test status
Simulation time 530130016 ps
CPU time 1.38 seconds
Started Jul 09 06:20:25 PM PDT 24
Finished Jul 09 06:20:26 PM PDT 24
Peak memory 191864 kb
Host smart-bf910dc5-51e1-4112-b3e7-a988fb54631c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585542402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.585542402
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2125733652
Short name T271
Test name
Test status
Simulation time 2538620736 ps
CPU time 2.03 seconds
Started Jul 09 06:20:22 PM PDT 24
Finished Jul 09 06:20:24 PM PDT 24
Peak memory 196772 kb
Host smart-3a997d63-056d-4e35-b2ea-bae59846978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125733652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2125733652
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2800932010
Short name T33
Test name
Test status
Simulation time 368768480 ps
CPU time 0.93 seconds
Started Jul 09 06:20:26 PM PDT 24
Finished Jul 09 06:20:27 PM PDT 24
Peak memory 196724 kb
Host smart-372137bc-a34d-49e1-b11e-3032fabcaa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800932010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2800932010
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3800879849
Short name T262
Test name
Test status
Simulation time 6681458700 ps
CPU time 10.88 seconds
Started Jul 09 06:20:26 PM PDT 24
Finished Jul 09 06:20:37 PM PDT 24
Peak memory 196992 kb
Host smart-4a2a228c-bc7b-4d70-b123-8c691f3fb000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800879849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3800879849
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1833802879
Short name T240
Test name
Test status
Simulation time 473453854 ps
CPU time 0.92 seconds
Started Jul 09 06:20:26 PM PDT 24
Finished Jul 09 06:20:27 PM PDT 24
Peak memory 196704 kb
Host smart-3238ee29-13bd-4651-900a-478ebba71100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833802879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1833802879
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.4110755903
Short name T216
Test name
Test status
Simulation time 26877243802 ps
CPU time 10.09 seconds
Started Jul 09 06:20:32 PM PDT 24
Finished Jul 09 06:20:42 PM PDT 24
Peak memory 191940 kb
Host smart-d0fd64fd-b75f-4706-87d6-72f6a3fa959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110755903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4110755903
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2859177885
Short name T235
Test name
Test status
Simulation time 463081528 ps
CPU time 1.13 seconds
Started Jul 09 06:20:30 PM PDT 24
Finished Jul 09 06:20:32 PM PDT 24
Peak memory 191924 kb
Host smart-cfa682cf-328c-4d64-b77d-694609e920a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859177885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2859177885
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2765297445
Short name T208
Test name
Test status
Simulation time 40406626246 ps
CPU time 64.82 seconds
Started Jul 09 06:20:39 PM PDT 24
Finished Jul 09 06:21:44 PM PDT 24
Peak memory 191956 kb
Host smart-63eff30e-2606-4d14-9b13-ea3ac0811c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765297445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2765297445
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3008408225
Short name T227
Test name
Test status
Simulation time 421521259 ps
CPU time 0.79 seconds
Started Jul 09 06:20:38 PM PDT 24
Finished Jul 09 06:20:39 PM PDT 24
Peak memory 191924 kb
Host smart-e38af3bf-ae87-49f1-82ae-4ea09d30012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008408225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3008408225
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1788720533
Short name T89
Test name
Test status
Simulation time 558171683 ps
CPU time 0.78 seconds
Started Jul 09 06:19:14 PM PDT 24
Finished Jul 09 06:19:15 PM PDT 24
Peak memory 196728 kb
Host smart-f860d033-2178-4884-90de-1768d42e7e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788720533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1788720533
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.267127303
Short name T272
Test name
Test status
Simulation time 35564370619 ps
CPU time 13.25 seconds
Started Jul 09 06:19:11 PM PDT 24
Finished Jul 09 06:19:24 PM PDT 24
Peak memory 192004 kb
Host smart-02ace2fd-a7f7-426f-841a-00445bde2212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267127303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.267127303
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.152456389
Short name T25
Test name
Test status
Simulation time 4637393753 ps
CPU time 3.54 seconds
Started Jul 09 06:19:14 PM PDT 24
Finished Jul 09 06:19:18 PM PDT 24
Peak memory 215740 kb
Host smart-ac4f4188-67a2-4659-b3c0-e3e3f03adba3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152456389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.152456389
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.915036820
Short name T2
Test name
Test status
Simulation time 448160134 ps
CPU time 0.74 seconds
Started Jul 09 06:19:12 PM PDT 24
Finished Jul 09 06:19:14 PM PDT 24
Peak memory 191916 kb
Host smart-89f98abe-55cb-49f5-be85-a91fddf1559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915036820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.915036820
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2271747112
Short name T275
Test name
Test status
Simulation time 9172318111 ps
CPU time 7.44 seconds
Started Jul 09 06:20:43 PM PDT 24
Finished Jul 09 06:20:51 PM PDT 24
Peak memory 196936 kb
Host smart-1ff3c0ac-9187-485d-b745-4a2b7ec46ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271747112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2271747112
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1815438533
Short name T215
Test name
Test status
Simulation time 536344424 ps
CPU time 0.8 seconds
Started Jul 09 06:20:42 PM PDT 24
Finished Jul 09 06:20:44 PM PDT 24
Peak memory 196692 kb
Host smart-07b4e06d-2082-4d2c-acb0-0cfdfeb5031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815438533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1815438533
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3039196367
Short name T261
Test name
Test status
Simulation time 52926633309 ps
CPU time 82 seconds
Started Jul 09 06:20:49 PM PDT 24
Finished Jul 09 06:22:12 PM PDT 24
Peak memory 196944 kb
Host smart-fdbba479-2319-4a9c-a425-9a3ed86e38fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039196367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3039196367
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1421841378
Short name T232
Test name
Test status
Simulation time 517968002 ps
CPU time 0.75 seconds
Started Jul 09 06:20:48 PM PDT 24
Finished Jul 09 06:20:49 PM PDT 24
Peak memory 191932 kb
Host smart-3be462be-09a5-4e84-b40e-bf495cf8f2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421841378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1421841378
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3586148224
Short name T182
Test name
Test status
Simulation time 593843176 ps
CPU time 0.76 seconds
Started Jul 09 06:20:52 PM PDT 24
Finished Jul 09 06:20:53 PM PDT 24
Peak memory 196724 kb
Host smart-5cd88644-5a5d-4e78-90d5-171e3b70e68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586148224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3586148224
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.21368416
Short name T264
Test name
Test status
Simulation time 23972759755 ps
CPU time 7.54 seconds
Started Jul 09 06:20:51 PM PDT 24
Finished Jul 09 06:20:58 PM PDT 24
Peak memory 196892 kb
Host smart-bb616d4a-8ea7-4e76-9a01-26f3179214e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21368416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.21368416
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.239384569
Short name T9
Test name
Test status
Simulation time 517735044 ps
CPU time 0.73 seconds
Started Jul 09 06:20:51 PM PDT 24
Finished Jul 09 06:20:52 PM PDT 24
Peak memory 196736 kb
Host smart-05222fd3-f04b-49a1-8d0d-ec2655ac4244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239384569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.239384569
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.283612360
Short name T48
Test name
Test status
Simulation time 19275612133 ps
CPU time 22.12 seconds
Started Jul 09 06:20:55 PM PDT 24
Finished Jul 09 06:21:18 PM PDT 24
Peak memory 192012 kb
Host smart-07c32338-ac74-4fb5-b815-1b9b2378b6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283612360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.283612360
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.680104048
Short name T5
Test name
Test status
Simulation time 453825710 ps
CPU time 1.15 seconds
Started Jul 09 06:20:54 PM PDT 24
Finished Jul 09 06:20:55 PM PDT 24
Peak memory 191892 kb
Host smart-117d282f-d6cb-4094-ae47-5a995d8e9625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680104048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.680104048
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3387228648
Short name T197
Test name
Test status
Simulation time 3815680627 ps
CPU time 1.96 seconds
Started Jul 09 06:21:03 PM PDT 24
Finished Jul 09 06:21:05 PM PDT 24
Peak memory 196760 kb
Host smart-788bc234-f70e-41b2-88db-b054b3ef51df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387228648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3387228648
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4017633252
Short name T248
Test name
Test status
Simulation time 578028468 ps
CPU time 0.94 seconds
Started Jul 09 06:20:59 PM PDT 24
Finished Jul 09 06:21:00 PM PDT 24
Peak memory 196784 kb
Host smart-d38a623f-7227-4abc-bc70-634f96cc13a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017633252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4017633252
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.286297460
Short name T198
Test name
Test status
Simulation time 33292759580 ps
CPU time 22.18 seconds
Started Jul 09 06:21:05 PM PDT 24
Finished Jul 09 06:21:28 PM PDT 24
Peak memory 191900 kb
Host smart-724359f8-0eeb-4541-9a76-ec7dcfce789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286297460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.286297460
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3654532361
Short name T250
Test name
Test status
Simulation time 603047888 ps
CPU time 1.06 seconds
Started Jul 09 06:21:04 PM PDT 24
Finished Jul 09 06:21:05 PM PDT 24
Peak memory 191944 kb
Host smart-96246e34-088e-4527-94f5-7ecce672b066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654532361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3654532361
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.4275536586
Short name T273
Test name
Test status
Simulation time 10513943250 ps
CPU time 4.87 seconds
Started Jul 09 06:21:12 PM PDT 24
Finished Jul 09 06:21:17 PM PDT 24
Peak memory 196964 kb
Host smart-3dec360d-7cc2-41e5-9838-ec6182b9861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275536586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.4275536586
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1375942346
Short name T222
Test name
Test status
Simulation time 454854422 ps
CPU time 0.74 seconds
Started Jul 09 06:21:07 PM PDT 24
Finished Jul 09 06:21:08 PM PDT 24
Peak memory 196784 kb
Host smart-facdf6a3-2df7-40e6-a5d9-b476d8fa77dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375942346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1375942346
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3357425338
Short name T231
Test name
Test status
Simulation time 33144471045 ps
CPU time 25.48 seconds
Started Jul 09 06:21:14 PM PDT 24
Finished Jul 09 06:21:40 PM PDT 24
Peak memory 192144 kb
Host smart-9b087f45-0919-45a8-9e97-2fade8a374e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357425338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3357425338
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1878371336
Short name T204
Test name
Test status
Simulation time 428836516 ps
CPU time 0.76 seconds
Started Jul 09 06:21:15 PM PDT 24
Finished Jul 09 06:21:16 PM PDT 24
Peak memory 196792 kb
Host smart-fc1efe5e-3642-4cee-8e44-a685a7405b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878371336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1878371336
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1788027801
Short name T200
Test name
Test status
Simulation time 51449061932 ps
CPU time 63.68 seconds
Started Jul 09 06:21:19 PM PDT 24
Finished Jul 09 06:22:23 PM PDT 24
Peak memory 191956 kb
Host smart-39bd8d0d-bc8b-4aa5-a2a4-c82da7da5596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788027801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1788027801
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.653792132
Short name T31
Test name
Test status
Simulation time 516506883 ps
CPU time 0.84 seconds
Started Jul 09 06:21:16 PM PDT 24
Finished Jul 09 06:21:18 PM PDT 24
Peak memory 191916 kb
Host smart-9170ed78-c231-4d04-8f81-ba179ed8336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653792132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.653792132
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1584124543
Short name T219
Test name
Test status
Simulation time 26757348351 ps
CPU time 10.07 seconds
Started Jul 09 06:21:24 PM PDT 24
Finished Jul 09 06:21:34 PM PDT 24
Peak memory 191980 kb
Host smart-e36e6ab7-e88a-42d5-b2fd-0e474556dc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584124543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1584124543
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2043815737
Short name T223
Test name
Test status
Simulation time 592140244 ps
CPU time 0.84 seconds
Started Jul 09 06:21:22 PM PDT 24
Finished Jul 09 06:21:23 PM PDT 24
Peak memory 191928 kb
Host smart-08119cca-b93e-4a94-be69-dd02a52740f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043815737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2043815737
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1517468940
Short name T237
Test name
Test status
Simulation time 3649569214 ps
CPU time 6.18 seconds
Started Jul 09 06:19:17 PM PDT 24
Finished Jul 09 06:19:24 PM PDT 24
Peak memory 192000 kb
Host smart-9af494c3-ee75-4f2a-bcba-56a2b2d2886a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517468940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1517468940
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4002256494
Short name T17
Test name
Test status
Simulation time 8568327902 ps
CPU time 14.19 seconds
Started Jul 09 06:19:26 PM PDT 24
Finished Jul 09 06:19:41 PM PDT 24
Peak memory 215856 kb
Host smart-18d48cca-bab0-410d-8246-171b229dcf59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002256494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4002256494
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2227702535
Short name T205
Test name
Test status
Simulation time 510160301 ps
CPU time 0.85 seconds
Started Jul 09 06:19:17 PM PDT 24
Finished Jul 09 06:19:18 PM PDT 24
Peak memory 196724 kb
Host smart-5833e61b-af5c-4fe9-86b7-e16a5de03b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227702535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2227702535
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.618845515
Short name T176
Test name
Test status
Simulation time 713762427 ps
CPU time 0.66 seconds
Started Jul 09 06:21:29 PM PDT 24
Finished Jul 09 06:21:30 PM PDT 24
Peak memory 196684 kb
Host smart-b9810a11-e92e-4cbc-95ff-c5bb2e7e0d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618845515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.618845515
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1066881952
Short name T268
Test name
Test status
Simulation time 50809149184 ps
CPU time 19.13 seconds
Started Jul 09 06:21:25 PM PDT 24
Finished Jul 09 06:21:45 PM PDT 24
Peak memory 191964 kb
Host smart-1f7e90ca-942a-4913-b89a-d8fbfbd09cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066881952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1066881952
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.720182587
Short name T241
Test name
Test status
Simulation time 443020562 ps
CPU time 0.89 seconds
Started Jul 09 06:21:26 PM PDT 24
Finished Jul 09 06:21:27 PM PDT 24
Peak memory 191820 kb
Host smart-88e187ec-8d66-4e16-8976-7511016e6803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720182587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.720182587
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2472382846
Short name T266
Test name
Test status
Simulation time 16051477884 ps
CPU time 23.17 seconds
Started Jul 09 06:21:34 PM PDT 24
Finished Jul 09 06:21:58 PM PDT 24
Peak memory 191988 kb
Host smart-c94b2e38-47bc-4412-b902-96e229d0e7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472382846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2472382846
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3722894339
Short name T254
Test name
Test status
Simulation time 543227638 ps
CPU time 0.91 seconds
Started Jul 09 06:21:31 PM PDT 24
Finished Jul 09 06:21:33 PM PDT 24
Peak memory 191924 kb
Host smart-af619629-aa04-4fc2-9f03-2379a595f988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722894339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3722894339
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1182984098
Short name T238
Test name
Test status
Simulation time 27041986086 ps
CPU time 6.93 seconds
Started Jul 09 06:21:42 PM PDT 24
Finished Jul 09 06:21:49 PM PDT 24
Peak memory 191940 kb
Host smart-5a856312-da79-4ca1-8e73-c01397251d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182984098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1182984098
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2297180083
Short name T225
Test name
Test status
Simulation time 560707222 ps
CPU time 0.92 seconds
Started Jul 09 06:21:40 PM PDT 24
Finished Jul 09 06:21:41 PM PDT 24
Peak memory 191892 kb
Host smart-db3c1432-113f-4b4b-82de-67aa583db020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297180083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2297180083
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.884104209
Short name T236
Test name
Test status
Simulation time 7951340339 ps
CPU time 12.91 seconds
Started Jul 09 06:21:40 PM PDT 24
Finished Jul 09 06:21:54 PM PDT 24
Peak memory 192004 kb
Host smart-5150a7d6-bde3-45cc-898a-ef0087ac21b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884104209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.884104209
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1311527820
Short name T255
Test name
Test status
Simulation time 588331155 ps
CPU time 0.75 seconds
Started Jul 09 06:21:40 PM PDT 24
Finished Jul 09 06:21:41 PM PDT 24
Peak memory 191888 kb
Host smart-f46f4995-eec4-4220-bc7f-a71ce1a16a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311527820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1311527820
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3022673565
Short name T213
Test name
Test status
Simulation time 30384089043 ps
CPU time 7.03 seconds
Started Jul 09 06:21:44 PM PDT 24
Finished Jul 09 06:21:52 PM PDT 24
Peak memory 191964 kb
Host smart-a89c5aa1-4071-4a38-8213-4ce82f7b65e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022673565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3022673565
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.774064699
Short name T209
Test name
Test status
Simulation time 517926584 ps
CPU time 0.77 seconds
Started Jul 09 06:21:42 PM PDT 24
Finished Jul 09 06:21:43 PM PDT 24
Peak memory 196768 kb
Host smart-5d4ea745-1a75-4f9d-8618-d888a551bb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774064699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.774064699
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4223822228
Short name T30
Test name
Test status
Simulation time 41331887876 ps
CPU time 8.86 seconds
Started Jul 09 06:21:49 PM PDT 24
Finished Jul 09 06:21:59 PM PDT 24
Peak memory 192004 kb
Host smart-2f89bc85-d0ef-4229-95c4-88d25b7cb042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223822228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4223822228
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1311503997
Short name T265
Test name
Test status
Simulation time 377189753 ps
CPU time 0.85 seconds
Started Jul 09 06:21:44 PM PDT 24
Finished Jul 09 06:21:45 PM PDT 24
Peak memory 191900 kb
Host smart-887db5c4-5b6b-46d0-a0a5-75e0276b27e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311503997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1311503997
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3655643074
Short name T234
Test name
Test status
Simulation time 17669706046 ps
CPU time 12.03 seconds
Started Jul 09 06:21:52 PM PDT 24
Finished Jul 09 06:22:04 PM PDT 24
Peak memory 191864 kb
Host smart-4183c013-ae7e-48ff-ad3b-e472d7222875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655643074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3655643074
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1967869694
Short name T269
Test name
Test status
Simulation time 616903388 ps
CPU time 0.75 seconds
Started Jul 09 06:21:52 PM PDT 24
Finished Jul 09 06:21:53 PM PDT 24
Peak memory 191888 kb
Host smart-58f8c742-489d-4059-b50d-32b0a8835f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967869694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1967869694
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3935522485
Short name T246
Test name
Test status
Simulation time 14235574392 ps
CPU time 5.86 seconds
Started Jul 09 06:21:53 PM PDT 24
Finished Jul 09 06:21:59 PM PDT 24
Peak memory 197000 kb
Host smart-3f25460c-a886-4edd-b252-a036789ef84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935522485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3935522485
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1154216488
Short name T252
Test name
Test status
Simulation time 563005774 ps
CPU time 1.45 seconds
Started Jul 09 06:21:53 PM PDT 24
Finished Jul 09 06:21:55 PM PDT 24
Peak memory 191944 kb
Host smart-df743dd4-a295-4641-a694-6a6ef6d5e410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154216488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1154216488
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3155059733
Short name T263
Test name
Test status
Simulation time 3908100558 ps
CPU time 5.59 seconds
Started Jul 09 06:22:02 PM PDT 24
Finished Jul 09 06:22:08 PM PDT 24
Peak memory 196732 kb
Host smart-f0ba4a46-1e52-42b1-93d7-c125b13e719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155059733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3155059733
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4201751577
Short name T45
Test name
Test status
Simulation time 486028998 ps
CPU time 0.98 seconds
Started Jul 09 06:21:55 PM PDT 24
Finished Jul 09 06:21:56 PM PDT 24
Peak memory 191908 kb
Host smart-2ff32c2f-e914-45d2-869d-4ff48cb954d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201751577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4201751577
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2873985245
Short name T16
Test name
Test status
Simulation time 53136175300 ps
CPU time 38.06 seconds
Started Jul 09 06:22:03 PM PDT 24
Finished Jul 09 06:22:41 PM PDT 24
Peak memory 192004 kb
Host smart-8bc4988d-9962-4e19-a32e-4c0db760044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873985245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2873985245
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1834056170
Short name T201
Test name
Test status
Simulation time 558374634 ps
CPU time 0.98 seconds
Started Jul 09 06:22:00 PM PDT 24
Finished Jul 09 06:22:01 PM PDT 24
Peak memory 191932 kb
Host smart-d3afab27-1ea2-4e5a-8c28-ee5cdb91cd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834056170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1834056170
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2207317453
Short name T249
Test name
Test status
Simulation time 19517686057 ps
CPU time 2.69 seconds
Started Jul 09 06:19:26 PM PDT 24
Finished Jul 09 06:19:29 PM PDT 24
Peak memory 191956 kb
Host smart-dba17347-f21d-4aa2-a838-40cef3221bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207317453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2207317453
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3859621275
Short name T18
Test name
Test status
Simulation time 3909521970 ps
CPU time 1.56 seconds
Started Jul 09 06:19:31 PM PDT 24
Finished Jul 09 06:19:33 PM PDT 24
Peak memory 215464 kb
Host smart-3d7da22f-1047-4f6b-8ef2-1202859cc3d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859621275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3859621275
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1891159795
Short name T210
Test name
Test status
Simulation time 414883280 ps
CPU time 0.91 seconds
Started Jul 09 06:19:29 PM PDT 24
Finished Jul 09 06:19:31 PM PDT 24
Peak memory 196776 kb
Host smart-dbb327d5-7a7b-48aa-96f6-72e4717e4b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891159795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1891159795
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1528843443
Short name T251
Test name
Test status
Simulation time 33569090449 ps
CPU time 3.54 seconds
Started Jul 09 06:22:05 PM PDT 24
Finished Jul 09 06:22:08 PM PDT 24
Peak memory 196952 kb
Host smart-78152530-833e-441e-9695-8cfe1b88e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528843443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1528843443
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1736971198
Short name T244
Test name
Test status
Simulation time 605974410 ps
CPU time 0.92 seconds
Started Jul 09 06:22:06 PM PDT 24
Finished Jul 09 06:22:07 PM PDT 24
Peak memory 191952 kb
Host smart-23796f5c-e5a9-4981-80fb-f62fc55582a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736971198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1736971198
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.994270117
Short name T253
Test name
Test status
Simulation time 112351330488 ps
CPU time 87.62 seconds
Started Jul 09 06:22:09 PM PDT 24
Finished Jul 09 06:23:37 PM PDT 24
Peak memory 198272 kb
Host smart-1afe1f75-feaf-417a-bf71-dc9468719355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994270117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.994270117
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2721214321
Short name T218
Test name
Test status
Simulation time 8656229468 ps
CPU time 2.08 seconds
Started Jul 09 06:22:13 PM PDT 24
Finished Jul 09 06:22:16 PM PDT 24
Peak memory 192004 kb
Host smart-3a7b7f02-1099-496b-ac4b-d3f39424760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721214321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2721214321
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1738393093
Short name T206
Test name
Test status
Simulation time 392091112 ps
CPU time 1.13 seconds
Started Jul 09 06:22:09 PM PDT 24
Finished Jul 09 06:22:11 PM PDT 24
Peak memory 191924 kb
Host smart-9583b4ce-4bfc-40c2-87d0-38a0a598a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738393093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1738393093
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1403816744
Short name T274
Test name
Test status
Simulation time 40839868660 ps
CPU time 28.37 seconds
Started Jul 09 06:22:18 PM PDT 24
Finished Jul 09 06:22:47 PM PDT 24
Peak memory 196988 kb
Host smart-bbeb128a-4680-4d75-96ea-00a0ae807800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403816744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1403816744
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.334698853
Short name T239
Test name
Test status
Simulation time 554750913 ps
CPU time 1.34 seconds
Started Jul 09 06:22:16 PM PDT 24
Finished Jul 09 06:22:18 PM PDT 24
Peak memory 191928 kb
Host smart-ce62042c-abf3-494d-ab3a-2ca6c621141b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334698853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.334698853
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2545701432
Short name T12
Test name
Test status
Simulation time 9613701496 ps
CPU time 1.25 seconds
Started Jul 09 06:22:14 PM PDT 24
Finished Jul 09 06:22:15 PM PDT 24
Peak memory 191980 kb
Host smart-eda14136-d402-490d-a7ab-4c3259441725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545701432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2545701432
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4275115184
Short name T212
Test name
Test status
Simulation time 517557617 ps
CPU time 0.85 seconds
Started Jul 09 06:22:16 PM PDT 24
Finished Jul 09 06:22:17 PM PDT 24
Peak memory 191844 kb
Host smart-3642cf1a-3df0-4db7-91ea-679851029fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275115184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4275115184
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1232952291
Short name T214
Test name
Test status
Simulation time 6173384802 ps
CPU time 2.52 seconds
Started Jul 09 06:22:17 PM PDT 24
Finished Jul 09 06:22:20 PM PDT 24
Peak memory 196932 kb
Host smart-c85f790a-faba-431e-915f-b7312df47108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232952291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1232952291
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2476683697
Short name T91
Test name
Test status
Simulation time 633829041 ps
CPU time 0.65 seconds
Started Jul 09 06:22:21 PM PDT 24
Finished Jul 09 06:22:22 PM PDT 24
Peak memory 196728 kb
Host smart-8c662d56-fa31-4883-ada0-c563013fdb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476683697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2476683697
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2519164290
Short name T259
Test name
Test status
Simulation time 20883170665 ps
CPU time 5.52 seconds
Started Jul 09 06:22:21 PM PDT 24
Finished Jul 09 06:22:27 PM PDT 24
Peak memory 191980 kb
Host smart-1db3de7b-cd25-4176-93a0-7ebe732d4f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519164290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2519164290
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3421445422
Short name T211
Test name
Test status
Simulation time 580944884 ps
CPU time 0.63 seconds
Started Jul 09 06:22:21 PM PDT 24
Finished Jul 09 06:22:22 PM PDT 24
Peak memory 191804 kb
Host smart-56dea89b-300f-4321-90e9-177c7b7ead83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421445422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3421445422
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3652791679
Short name T256
Test name
Test status
Simulation time 39575616176 ps
CPU time 58.1 seconds
Started Jul 09 06:22:26 PM PDT 24
Finished Jul 09 06:23:24 PM PDT 24
Peak memory 196992 kb
Host smart-13314014-7605-4555-8ba8-2fb4bcd35ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652791679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3652791679
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1555245654
Short name T161
Test name
Test status
Simulation time 502676692 ps
CPU time 0.76 seconds
Started Jul 09 06:22:26 PM PDT 24
Finished Jul 09 06:22:28 PM PDT 24
Peak memory 191952 kb
Host smart-2ebcc930-5a86-4ead-aa22-73c0abe47be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555245654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1555245654
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.488612756
Short name T28
Test name
Test status
Simulation time 6486798416 ps
CPU time 45.01 seconds
Started Jul 09 06:22:28 PM PDT 24
Finished Jul 09 06:23:14 PM PDT 24
Peak memory 198608 kb
Host smart-0dfd4bfe-2821-418d-b137-a419e293a0f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488612756 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.488612756
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.928024030
Short name T49
Test name
Test status
Simulation time 52731260614 ps
CPU time 75.87 seconds
Started Jul 09 06:22:29 PM PDT 24
Finished Jul 09 06:23:46 PM PDT 24
Peak memory 191880 kb
Host smart-03acaaa0-de33-4c8a-b7e6-0697be98d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928024030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.928024030
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1188788564
Short name T52
Test name
Test status
Simulation time 588278232 ps
CPU time 0.78 seconds
Started Jul 09 06:22:30 PM PDT 24
Finished Jul 09 06:22:31 PM PDT 24
Peak memory 196716 kb
Host smart-6e17c8ff-3351-4a8d-8f0e-0c43469b243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188788564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1188788564
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2921294845
Short name T230
Test name
Test status
Simulation time 29530189174 ps
CPU time 41.31 seconds
Started Jul 09 06:22:30 PM PDT 24
Finished Jul 09 06:23:12 PM PDT 24
Peak memory 192004 kb
Host smart-ad2a5a97-f13c-43c8-8e68-4394a78f15b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921294845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2921294845
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1310693345
Short name T233
Test name
Test status
Simulation time 577674344 ps
CPU time 1.01 seconds
Started Jul 09 06:22:32 PM PDT 24
Finished Jul 09 06:22:33 PM PDT 24
Peak memory 191908 kb
Host smart-f12b4935-90cd-486d-8c66-cc84fd042809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310693345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1310693345
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2024425535
Short name T1
Test name
Test status
Simulation time 1614817291 ps
CPU time 2.72 seconds
Started Jul 09 06:22:36 PM PDT 24
Finished Jul 09 06:22:40 PM PDT 24
Peak memory 196656 kb
Host smart-d9dfcd43-1cbc-42c8-8bf8-130452fa77ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024425535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2024425535
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1763703534
Short name T220
Test name
Test status
Simulation time 366204194 ps
CPU time 1.05 seconds
Started Jul 09 06:22:35 PM PDT 24
Finished Jul 09 06:22:37 PM PDT 24
Peak memory 196712 kb
Host smart-240ab5c3-bf29-4b4f-b056-3c7beade6129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763703534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1763703534
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2100867734
Short name T243
Test name
Test status
Simulation time 12157891841 ps
CPU time 18.5 seconds
Started Jul 09 06:19:30 PM PDT 24
Finished Jul 09 06:19:49 PM PDT 24
Peak memory 191904 kb
Host smart-9b5029bd-c08d-4ad5-bd9a-0b2fe0c4a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100867734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2100867734
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3392455969
Short name T6
Test name
Test status
Simulation time 562117561 ps
CPU time 0.77 seconds
Started Jul 09 06:19:30 PM PDT 24
Finished Jul 09 06:19:31 PM PDT 24
Peak memory 191940 kb
Host smart-1244956c-15b6-4d80-87d5-d99a4d48cc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392455969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3392455969
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3101516251
Short name T247
Test name
Test status
Simulation time 1687161072 ps
CPU time 1.09 seconds
Started Jul 09 06:19:41 PM PDT 24
Finished Jul 09 06:19:42 PM PDT 24
Peak memory 191868 kb
Host smart-6a297fc2-c594-4e5c-9c1b-5bc91a5df2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101516251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3101516251
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2507146674
Short name T100
Test name
Test status
Simulation time 530573036 ps
CPU time 1.33 seconds
Started Jul 09 06:19:36 PM PDT 24
Finished Jul 09 06:19:38 PM PDT 24
Peak memory 191896 kb
Host smart-8f867244-34ed-463c-9cc6-3ebe2944a696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507146674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2507146674
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2775086426
Short name T258
Test name
Test status
Simulation time 33781858539 ps
CPU time 12.76 seconds
Started Jul 09 06:19:41 PM PDT 24
Finished Jul 09 06:19:54 PM PDT 24
Peak memory 196912 kb
Host smart-bd5cf544-a4cf-4943-a54c-661413790701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775086426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2775086426
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3830951885
Short name T221
Test name
Test status
Simulation time 449773196 ps
CPU time 1.14 seconds
Started Jul 09 06:19:41 PM PDT 24
Finished Jul 09 06:19:42 PM PDT 24
Peak memory 191872 kb
Host smart-db0ae0c0-9bbc-4fb4-a12e-9a0a59785bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830951885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3830951885
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.437891082
Short name T226
Test name
Test status
Simulation time 35320039905 ps
CPU time 53.53 seconds
Started Jul 09 06:19:51 PM PDT 24
Finished Jul 09 06:20:45 PM PDT 24
Peak memory 196980 kb
Host smart-89083e99-b152-493f-aee0-5303e1840669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437891082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.437891082
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1747486344
Short name T83
Test name
Test status
Simulation time 561205876 ps
CPU time 0.66 seconds
Started Jul 09 06:19:46 PM PDT 24
Finished Jul 09 06:19:48 PM PDT 24
Peak memory 191860 kb
Host smart-c6046467-bee7-4b31-bf4c-2052a8b0c5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747486344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1747486344
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3048742983
Short name T90
Test name
Test status
Simulation time 447441364 ps
CPU time 1.15 seconds
Started Jul 09 06:19:52 PM PDT 24
Finished Jul 09 06:19:54 PM PDT 24
Peak memory 196724 kb
Host smart-6dd9e502-1b27-4e79-b5a6-f736a2d6a068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048742983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3048742983
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1484627932
Short name T229
Test name
Test status
Simulation time 6455764943 ps
CPU time 10.82 seconds
Started Jul 09 06:19:53 PM PDT 24
Finished Jul 09 06:20:04 PM PDT 24
Peak memory 192000 kb
Host smart-ea00c245-a621-487c-a389-8b143dead964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484627932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1484627932
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.143367862
Short name T270
Test name
Test status
Simulation time 631116848 ps
CPU time 0.81 seconds
Started Jul 09 06:19:51 PM PDT 24
Finished Jul 09 06:19:52 PM PDT 24
Peak memory 191900 kb
Host smart-ce8bcfea-d07b-46e6-98c7-779d49287172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143367862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.143367862
Directory /workspace/9.aon_timer_smoke/latest
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