Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 28487 1 T1 190 T2 272 T4 987
bark[1] 572 1 T1 14 T21 21 T30 286
bark[2] 642 1 T1 26 T10 97 T30 7
bark[3] 497 1 T14 96 T32 30 T172 5
bark[4] 598 1 T145 82 T42 21 T114 64
bark[5] 63 1 T4 21 T37 21 T167 21
bark[6] 912 1 T20 38 T35 244 T71 61
bark[7] 397 1 T9 191 T28 31 T29 28
bark[8] 568 1 T1 21 T4 177 T5 71
bark[9] 725 1 T12 160 T32 21 T96 21
bark[10] 764 1 T9 21 T21 486 T90 43
bark[11] 221 1 T29 30 T134 21 T123 14
bark[12] 614 1 T174 14 T80 30 T105 14
bark[13] 511 1 T14 21 T27 88 T35 47
bark[14] 582 1 T112 14 T96 21 T80 42
bark[15] 440 1 T1 21 T20 47 T79 21
bark[16] 377 1 T4 21 T7 14 T12 219
bark[17] 785 1 T4 21 T12 21 T20 104
bark[18] 293 1 T8 14 T32 14 T33 14
bark[19] 493 1 T4 43 T30 26 T134 38
bark[20] 1023 1 T27 292 T79 38 T118 21
bark[21] 269 1 T119 21 T68 21 T90 83
bark[22] 816 1 T1 59 T12 7 T14 107
bark[23] 767 1 T10 21 T21 21 T43 14
bark[24] 290 1 T5 21 T145 21 T79 21
bark[25] 637 1 T3 14 T4 73 T127 14
bark[26] 713 1 T30 188 T31 21 T96 21
bark[27] 261 1 T10 21 T31 69 T145 14
bark[28] 618 1 T28 21 T29 179 T96 21
bark[29] 316 1 T14 26 T27 7 T119 30
bark[30] 201 1 T10 21 T14 7 T21 35
bark[31] 401 1 T1 21 T12 70 T29 52
bark_0 4596 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 28449 1 T1 211 T2 271 T4 980
bite[1] 261 1 T4 21 T20 104 T80 21
bite[2] 944 1 T5 21 T9 21 T14 21
bite[3] 145 1 T31 21 T96 21 T69 48
bite[4] 542 1 T12 69 T30 187 T35 44
bite[5] 482 1 T28 21 T134 38 T33 13
bite[6] 211 1 T1 21 T14 6 T30 6
bite[7] 520 1 T12 6 T80 91 T142 13
bite[8] 439 1 T29 178 T93 21 T124 13
bite[9] 375 1 T21 55 T29 21 T31 30
bite[10] 561 1 T1 21 T4 21 T10 21
bite[11] 640 1 T119 40 T96 21 T139 191
bite[12] 340 1 T98 21 T71 169 T147 95
bite[13] 595 1 T145 13 T79 21 T37 21
bite[14] 523 1 T5 70 T20 47 T119 21
bite[15] 263 1 T31 69 T96 21 T122 21
bite[16] 764 1 T3 13 T10 96 T27 371
bite[17] 384 1 T4 137 T29 51 T37 21
bite[18] 455 1 T8 13 T32 30 T80 21
bite[19] 101 1 T96 21 T40 21 T108 21
bite[20] 1106 1 T21 224 T172 4 T96 21
bite[21] 932 1 T10 21 T14 95 T27 6
bite[22] 580 1 T12 218 T79 38 T118 21
bite[23] 854 1 T21 260 T30 285 T122 26
bite[24] 346 1 T1 26 T4 42 T30 6
bite[25] 913 1 T7 13 T9 190 T20 38
bite[26] 477 1 T1 13 T12 159 T28 30
bite[27] 442 1 T1 59 T42 26 T120 184
bite[28] 353 1 T10 21 T75 65 T76 154
bite[29] 854 1 T4 60 T14 25 T30 25
bite[30] 461 1 T4 72 T14 106 T134 21
bite[31] 89 1 T21 21 T167 13 T95 21
bite_0 5048 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 42517 1 T1 359 T2 241 T3 21
auto[1] 6932 1 T2 38 T4 337 T5 261


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 724 1 T4 93 T79 24 T42 78
prescale[1] 937 1 T4 19 T5 41 T21 123
prescale[2] 1058 1 T1 40 T9 66 T12 19
prescale[3] 417 1 T4 89 T5 54 T21 70
prescale[4] 1079 1 T9 61 T27 101 T28 216
prescale[5] 796 1 T2 19 T4 19 T5 19
prescale[6] 847 1 T4 129 T5 2 T12 28
prescale[7] 603 1 T5 40 T12 97 T21 46
prescale[8] 923 1 T1 19 T4 195 T21 2
prescale[9] 873 1 T4 138 T5 36 T14 19
prescale[10] 749 1 T9 9 T14 2 T21 36
prescale[11] 541 1 T4 44 T187 9 T118 19
prescale[12] 1240 1 T6 9 T14 158 T21 200
prescale[13] 321 1 T4 32 T30 70 T42 19
prescale[14] 957 1 T1 40 T4 19 T27 57
prescale[15] 727 1 T4 9 T5 45 T12 61
prescale[16] 971 1 T2 92 T9 37 T14 40
prescale[17] 355 1 T2 19 T5 19 T21 92
prescale[18] 823 1 T2 19 T4 51 T27 2
prescale[19] 702 1 T2 19 T9 2 T14 2
prescale[20] 987 1 T9 2 T12 2 T19 9
prescale[21] 949 1 T1 38 T4 91 T5 2
prescale[22] 816 1 T21 80 T27 2 T30 41
prescale[23] 596 1 T1 44 T14 2 T30 51
prescale[24] 499 1 T4 28 T21 19 T27 33
prescale[25] 715 1 T4 2 T5 24 T9 19
prescale[26] 876 1 T5 89 T9 45 T32 38
prescale[27] 526 1 T5 2 T12 60 T21 105
prescale[28] 472 1 T14 21 T27 47 T30 58
prescale[29] 1173 1 T4 2 T12 24 T13 9
prescale[30] 838 1 T1 19 T5 80 T21 53
prescale[31] 863 1 T1 23 T4 2 T14 18
prescale_0 24496 1 T1 136 T2 111 T3 21


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 37532 1 T1 184 T2 197 T3 21
auto[1] 11917 1 T1 175 T2 82 T4 222


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 49449 1 T1 359 T2 279 T3 21


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 28245 1 T1 187 T2 253 T3 1
wkup[1] 382 1 T9 21 T12 21 T21 21
wkup[2] 380 1 T4 21 T12 21 T119 40
wkup[3] 265 1 T9 51 T14 44 T27 21
wkup[4] 289 1 T14 41 T27 21 T28 30
wkup[5] 374 1 T4 42 T10 21 T27 21
wkup[6] 360 1 T1 15 T4 21 T10 21
wkup[7] 215 1 T21 15 T27 21 T139 56
wkup[8] 178 1 T12 26 T29 8 T80 21
wkup[9] 265 1 T4 39 T5 15 T14 29
wkup[10] 228 1 T10 21 T27 21 T29 21
wkup[11] 232 1 T5 47 T21 21 T27 21
wkup[12] 474 1 T1 21 T9 21 T12 21
wkup[13] 256 1 T14 21 T20 26 T21 21
wkup[14] 316 1 T8 15 T14 21 T122 26
wkup[15] 262 1 T9 8 T30 26 T35 21
wkup[16] 417 1 T27 36 T28 26 T30 30
wkup[17] 299 1 T1 21 T4 29 T21 21
wkup[18] 413 1 T4 21 T14 21 T28 26
wkup[19] 177 1 T21 15 T119 21 T80 21
wkup[20] 379 1 T2 21 T4 21 T127 15
wkup[21] 387 1 T4 35 T12 42 T20 21
wkup[22] 161 1 T21 30 T119 30 T80 30
wkup[23] 227 1 T4 21 T30 15 T79 15
wkup[24] 300 1 T4 21 T14 26 T21 30
wkup[25] 414 1 T5 21 T10 21 T27 21
wkup[26] 420 1 T21 39 T27 21 T172 21
wkup[27] 320 1 T4 39 T21 47 T27 21
wkup[28] 381 1 T5 21 T12 74 T27 21
wkup[29] 189 1 T4 42 T172 42 T68 21
wkup[30] 175 1 T30 41 T174 15 T104 30
wkup[31] 338 1 T5 20 T20 21 T21 26
wkup[32] 278 1 T4 21 T27 29 T96 21
wkup[33] 115 1 T4 21 T20 21 T42 26
wkup[34] 356 1 T21 21 T27 21 T30 50
wkup[35] 296 1 T14 26 T21 21 T172 21
wkup[36] 317 1 T4 21 T9 21 T21 30
wkup[37] 228 1 T4 21 T7 15 T114 21
wkup[38] 310 1 T80 21 T99 21 T120 65
wkup[39] 328 1 T4 21 T9 30 T21 21
wkup[40] 264 1 T5 21 T27 38 T31 26
wkup[41] 235 1 T9 21 T12 21 T21 26
wkup[42] 248 1 T12 8 T21 42 T28 21
wkup[43] 455 1 T14 26 T21 47 T40 21
wkup[44] 260 1 T9 21 T79 21 T42 21
wkup[45] 274 1 T21 21 T29 51 T30 42
wkup[46] 250 1 T21 41 T28 35 T122 21
wkup[47] 276 1 T1 47 T30 21 T134 21
wkup[48] 131 1 T79 21 T69 42 T75 21
wkup[49] 89 1 T31 47 T42 21 T85 21
wkup[50] 116 1 T80 30 T77 29 T86 15
wkup[51] 274 1 T21 21 T32 15 T80 21
wkup[52] 148 1 T29 21 T31 21 T104 29
wkup[53] 135 1 T1 21 T4 21 T20 21
wkup[54] 194 1 T4 21 T96 21 T148 42
wkup[55] 171 1 T4 21 T90 21 T104 42
wkup[56] 224 1 T30 21 T148 56 T104 21
wkup[57] 284 1 T1 21 T3 15 T4 21
wkup[58] 314 1 T4 21 T10 21 T14 21
wkup[59] 232 1 T5 30 T28 24 T145 26
wkup[60] 267 1 T14 21 T28 21 T29 30
wkup[61] 260 1 T4 21 T21 21 T172 6
wkup[62] 270 1 T4 42 T21 21 T28 21
wkup[63] 536 1 T1 21 T12 21 T21 21
wkup_0 3596 1 T1 5 T2 5 T3 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%