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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.99 99.33 93.67 100.00 98.40 99.51 49.04


Total test records in report: 424
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T283 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2676428029 Jul 10 06:08:29 PM PDT 24 Jul 10 06:08:30 PM PDT 24 341199264 ps
T22 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.806250878 Jul 10 06:08:19 PM PDT 24 Jul 10 06:08:21 PM PDT 24 682212400 ps
T23 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.753252645 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:20 PM PDT 24 7766048077 ps
T284 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2967143023 Jul 10 06:08:23 PM PDT 24 Jul 10 06:08:25 PM PDT 24 403526457 ps
T26 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3473879708 Jul 10 06:08:17 PM PDT 24 Jul 10 06:08:19 PM PDT 24 1109325119 ps
T24 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3833222493 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:05 PM PDT 24 8122233847 ps
T285 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2640897234 Jul 10 06:08:23 PM PDT 24 Jul 10 06:08:26 PM PDT 24 462148377 ps
T286 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1778359595 Jul 10 06:08:01 PM PDT 24 Jul 10 06:08:05 PM PDT 24 341995383 ps
T287 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1587050040 Jul 10 06:08:17 PM PDT 24 Jul 10 06:08:20 PM PDT 24 540742476 ps
T288 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.13105638 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:02 PM PDT 24 467924456 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.505028228 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:02 PM PDT 24 884341118 ps
T290 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2718655825 Jul 10 06:08:10 PM PDT 24 Jul 10 06:08:13 PM PDT 24 621237578 ps
T291 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3906303061 Jul 10 06:08:22 PM PDT 24 Jul 10 06:08:24 PM PDT 24 377866663 ps
T46 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.277584678 Jul 10 06:08:01 PM PDT 24 Jul 10 06:08:21 PM PDT 24 4720730109 ps
T292 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2591219993 Jul 10 06:08:07 PM PDT 24 Jul 10 06:08:11 PM PDT 24 520891687 ps
T293 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3409996277 Jul 10 06:08:29 PM PDT 24 Jul 10 06:08:31 PM PDT 24 421706246 ps
T294 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1515725759 Jul 10 06:08:00 PM PDT 24 Jul 10 06:08:04 PM PDT 24 322100898 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.640611986 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:02 PM PDT 24 1004747748 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4060000979 Jul 10 06:07:54 PM PDT 24 Jul 10 06:08:00 PM PDT 24 1595338156 ps
T296 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.166751709 Jul 10 06:08:24 PM PDT 24 Jul 10 06:08:26 PM PDT 24 338586200 ps
T188 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1928965825 Jul 10 06:08:10 PM PDT 24 Jul 10 06:08:12 PM PDT 24 352561723 ps
T25 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1260991122 Jul 10 06:08:07 PM PDT 24 Jul 10 06:08:23 PM PDT 24 8278273904 ps
T297 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2062037379 Jul 10 06:08:22 PM PDT 24 Jul 10 06:08:24 PM PDT 24 371146648 ps
T60 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.300773736 Jul 10 06:08:15 PM PDT 24 Jul 10 06:08:21 PM PDT 24 2526795368 ps
T298 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2466926258 Jul 10 06:08:17 PM PDT 24 Jul 10 06:08:19 PM PDT 24 271573810 ps
T47 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3594267738 Jul 10 06:08:04 PM PDT 24 Jul 10 06:08:06 PM PDT 24 427095814 ps
T299 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.36534143 Jul 10 06:08:01 PM PDT 24 Jul 10 06:08:05 PM PDT 24 707528998 ps
T61 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3470855166 Jul 10 06:08:10 PM PDT 24 Jul 10 06:08:16 PM PDT 24 1800358408 ps
T300 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3413810335 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:14 PM PDT 24 299075573 ps
T301 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1338622420 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:02 PM PDT 24 493000544 ps
T62 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3886541331 Jul 10 06:08:28 PM PDT 24 Jul 10 06:08:30 PM PDT 24 1092364925 ps
T302 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1565039074 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:09 PM PDT 24 420758895 ps
T303 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.725765257 Jul 10 06:08:13 PM PDT 24 Jul 10 06:08:17 PM PDT 24 742287215 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3335243058 Jul 10 06:07:54 PM PDT 24 Jul 10 06:07:57 PM PDT 24 315676626 ps
T305 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1837387290 Jul 10 06:08:24 PM PDT 24 Jul 10 06:08:26 PM PDT 24 580474256 ps
T306 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.190369644 Jul 10 06:08:17 PM PDT 24 Jul 10 06:08:19 PM PDT 24 762926226 ps
T307 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2994915417 Jul 10 06:08:16 PM PDT 24 Jul 10 06:08:18 PM PDT 24 488668507 ps
T308 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3378752808 Jul 10 06:07:54 PM PDT 24 Jul 10 06:07:57 PM PDT 24 454486113 ps
T309 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.767446497 Jul 10 06:08:28 PM PDT 24 Jul 10 06:08:29 PM PDT 24 356491961 ps
T310 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.663911590 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:09 PM PDT 24 573729158 ps
T63 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.247568733 Jul 10 06:08:04 PM PDT 24 Jul 10 06:08:07 PM PDT 24 2113626884 ps
T311 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1269851614 Jul 10 06:08:05 PM PDT 24 Jul 10 06:08:07 PM PDT 24 468367712 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3430901616 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:08 PM PDT 24 459046253 ps
T312 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3768171057 Jul 10 06:08:17 PM PDT 24 Jul 10 06:08:19 PM PDT 24 472798892 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3623673314 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:03 PM PDT 24 1969639184 ps
T183 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1702701235 Jul 10 06:08:13 PM PDT 24 Jul 10 06:08:21 PM PDT 24 4263963465 ps
T66 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.186291090 Jul 10 06:08:07 PM PDT 24 Jul 10 06:08:10 PM PDT 24 616723666 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.821808017 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:00 PM PDT 24 595930952 ps
T184 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2979176370 Jul 10 06:08:10 PM PDT 24 Jul 10 06:08:15 PM PDT 24 4889889815 ps
T314 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.69635433 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:09 PM PDT 24 386412780 ps
T315 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3109288360 Jul 10 06:08:10 PM PDT 24 Jul 10 06:08:13 PM PDT 24 381201805 ps
T185 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.266996013 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:11 PM PDT 24 4263943246 ps
T316 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1316025905 Jul 10 06:08:07 PM PDT 24 Jul 10 06:08:10 PM PDT 24 294278907 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1294150163 Jul 10 06:07:55 PM PDT 24 Jul 10 06:07:58 PM PDT 24 523527183 ps
T67 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3259096148 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:13 PM PDT 24 2150648285 ps
T318 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4119185699 Jul 10 06:08:23 PM PDT 24 Jul 10 06:08:25 PM PDT 24 457998765 ps
T319 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.74287194 Jul 10 06:08:16 PM PDT 24 Jul 10 06:08:19 PM PDT 24 1099697264 ps
T320 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2919119048 Jul 10 06:08:07 PM PDT 24 Jul 10 06:08:14 PM PDT 24 4031339366 ps
T321 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2324656326 Jul 10 06:08:01 PM PDT 24 Jul 10 06:08:05 PM PDT 24 763560644 ps
T322 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1169576120 Jul 10 06:08:22 PM PDT 24 Jul 10 06:08:34 PM PDT 24 7515102969 ps
T323 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1193090196 Jul 10 06:08:19 PM PDT 24 Jul 10 06:08:20 PM PDT 24 1705248320 ps
T324 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3149679615 Jul 10 06:08:26 PM PDT 24 Jul 10 06:08:27 PM PDT 24 513178343 ps
T325 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1538438236 Jul 10 06:08:28 PM PDT 24 Jul 10 06:08:29 PM PDT 24 521756525 ps
T326 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3797686156 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:03 PM PDT 24 590784282 ps
T327 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1720464601 Jul 10 06:07:54 PM PDT 24 Jul 10 06:08:03 PM PDT 24 4419000195 ps
T48 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1695568485 Jul 10 06:08:16 PM PDT 24 Jul 10 06:08:17 PM PDT 24 496923578 ps
T328 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1553152316 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:15 PM PDT 24 298121144 ps
T49 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1766078133 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:13 PM PDT 24 580546411 ps
T329 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3147419810 Jul 10 06:08:02 PM PDT 24 Jul 10 06:08:06 PM PDT 24 499164894 ps
T50 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3694013085 Jul 10 06:07:57 PM PDT 24 Jul 10 06:07:59 PM PDT 24 472878458 ps
T330 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3385314125 Jul 10 06:08:01 PM PDT 24 Jul 10 06:08:04 PM PDT 24 445630532 ps
T331 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3576442349 Jul 10 06:08:12 PM PDT 24 Jul 10 06:08:15 PM PDT 24 547421952 ps
T332 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2565896699 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:03 PM PDT 24 699439631 ps
T333 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2055145308 Jul 10 06:08:00 PM PDT 24 Jul 10 06:08:03 PM PDT 24 511757405 ps
T334 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2508194520 Jul 10 06:08:19 PM PDT 24 Jul 10 06:08:24 PM PDT 24 1415105042 ps
T335 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4097939420 Jul 10 06:08:24 PM PDT 24 Jul 10 06:08:26 PM PDT 24 385042076 ps
T336 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3974207458 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:09 PM PDT 24 689822215 ps
T337 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3830506645 Jul 10 06:08:12 PM PDT 24 Jul 10 06:08:18 PM PDT 24 2270336965 ps
T338 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2237135293 Jul 10 06:07:53 PM PDT 24 Jul 10 06:07:57 PM PDT 24 4314036001 ps
T339 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2549823713 Jul 10 06:07:53 PM PDT 24 Jul 10 06:07:58 PM PDT 24 6948740310 ps
T340 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.986066468 Jul 10 06:08:23 PM PDT 24 Jul 10 06:08:25 PM PDT 24 372280725 ps
T341 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.455365848 Jul 10 06:08:24 PM PDT 24 Jul 10 06:08:26 PM PDT 24 340775772 ps
T342 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4654342 Jul 10 06:08:00 PM PDT 24 Jul 10 06:08:03 PM PDT 24 837000120 ps
T343 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1786480756 Jul 10 06:08:14 PM PDT 24 Jul 10 06:08:17 PM PDT 24 455201607 ps
T344 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3739639063 Jul 10 06:08:17 PM PDT 24 Jul 10 06:08:20 PM PDT 24 473019467 ps
T345 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.610981472 Jul 10 06:08:27 PM PDT 24 Jul 10 06:08:29 PM PDT 24 320804403 ps
T346 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.767400271 Jul 10 06:07:55 PM PDT 24 Jul 10 06:08:01 PM PDT 24 1693077959 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2024662098 Jul 10 06:07:53 PM PDT 24 Jul 10 06:07:56 PM PDT 24 484207777 ps
T348 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1698184868 Jul 10 06:08:20 PM PDT 24 Jul 10 06:08:22 PM PDT 24 592791096 ps
T349 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1453638665 Jul 10 06:08:12 PM PDT 24 Jul 10 06:08:15 PM PDT 24 426157397 ps
T350 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2354372566 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:14 PM PDT 24 451524333 ps
T351 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1297935313 Jul 10 06:08:26 PM PDT 24 Jul 10 06:08:28 PM PDT 24 533173799 ps
T352 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.974565740 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:03 PM PDT 24 1235238817 ps
T353 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2963530580 Jul 10 06:08:02 PM PDT 24 Jul 10 06:08:05 PM PDT 24 354305968 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2943452505 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:01 PM PDT 24 489261313 ps
T355 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2408270959 Jul 10 06:08:08 PM PDT 24 Jul 10 06:08:11 PM PDT 24 344632735 ps
T356 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1390587809 Jul 10 06:08:08 PM PDT 24 Jul 10 06:08:11 PM PDT 24 1015371080 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2530157120 Jul 10 06:07:55 PM PDT 24 Jul 10 06:07:57 PM PDT 24 318623936 ps
T358 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.26830080 Jul 10 06:08:21 PM PDT 24 Jul 10 06:08:23 PM PDT 24 366776579 ps
T359 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.615015608 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:04 PM PDT 24 1243330742 ps
T51 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2041082572 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:13 PM PDT 24 589319159 ps
T360 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.658168581 Jul 10 06:08:26 PM PDT 24 Jul 10 06:08:27 PM PDT 24 508602276 ps
T52 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.648203625 Jul 10 06:07:54 PM PDT 24 Jul 10 06:07:56 PM PDT 24 705580672 ps
T186 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3241532118 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:15 PM PDT 24 8302146854 ps
T361 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1682758318 Jul 10 06:08:17 PM PDT 24 Jul 10 06:08:22 PM PDT 24 1252223467 ps
T362 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2904331599 Jul 10 06:08:21 PM PDT 24 Jul 10 06:08:26 PM PDT 24 8718228483 ps
T363 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2991067877 Jul 10 06:08:26 PM PDT 24 Jul 10 06:08:28 PM PDT 24 339306510 ps
T364 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3206609 Jul 10 06:08:16 PM PDT 24 Jul 10 06:08:25 PM PDT 24 8120234634 ps
T365 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.203165387 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:24 PM PDT 24 7925231059 ps
T366 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1433952173 Jul 10 06:08:19 PM PDT 24 Jul 10 06:08:27 PM PDT 24 8520696540 ps
T367 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2629219159 Jul 10 06:08:20 PM PDT 24 Jul 10 06:08:23 PM PDT 24 867307576 ps
T53 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3197066080 Jul 10 06:08:05 PM PDT 24 Jul 10 06:08:07 PM PDT 24 508468672 ps
T54 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3875719441 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:04 PM PDT 24 12572772973 ps
T55 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.803792622 Jul 10 06:08:01 PM PDT 24 Jul 10 06:08:22 PM PDT 24 13000811099 ps
T368 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2578028971 Jul 10 06:08:25 PM PDT 24 Jul 10 06:08:27 PM PDT 24 428374330 ps
T369 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2608611572 Jul 10 06:07:56 PM PDT 24 Jul 10 06:07:58 PM PDT 24 527594411 ps
T370 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3663781852 Jul 10 06:08:25 PM PDT 24 Jul 10 06:08:27 PM PDT 24 463469511 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.81559199 Jul 10 06:07:54 PM PDT 24 Jul 10 06:07:57 PM PDT 24 514193718 ps
T372 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.647452973 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:02 PM PDT 24 421912602 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3101380240 Jul 10 06:07:53 PM PDT 24 Jul 10 06:07:55 PM PDT 24 319402573 ps
T374 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2035516612 Jul 10 06:08:05 PM PDT 24 Jul 10 06:08:08 PM PDT 24 541006103 ps
T375 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.363844780 Jul 10 06:07:53 PM PDT 24 Jul 10 06:07:55 PM PDT 24 439523927 ps
T376 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2256808020 Jul 10 06:08:18 PM PDT 24 Jul 10 06:08:20 PM PDT 24 522674360 ps
T377 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2221231944 Jul 10 06:08:19 PM PDT 24 Jul 10 06:08:21 PM PDT 24 395509350 ps
T378 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4041618546 Jul 10 06:08:24 PM PDT 24 Jul 10 06:08:26 PM PDT 24 432780812 ps
T379 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3455212536 Jul 10 06:08:29 PM PDT 24 Jul 10 06:08:31 PM PDT 24 331544621 ps
T380 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3954672539 Jul 10 06:07:55 PM PDT 24 Jul 10 06:07:58 PM PDT 24 561409474 ps
T381 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2838528333 Jul 10 06:08:23 PM PDT 24 Jul 10 06:08:25 PM PDT 24 400098284 ps
T382 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.369032784 Jul 10 06:08:25 PM PDT 24 Jul 10 06:08:29 PM PDT 24 820353209 ps
T383 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2769278739 Jul 10 06:07:55 PM PDT 24 Jul 10 06:07:57 PM PDT 24 418752738 ps
T384 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1525692045 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:15 PM PDT 24 869583155 ps
T385 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1539916557 Jul 10 06:08:13 PM PDT 24 Jul 10 06:08:16 PM PDT 24 557742642 ps
T386 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.943768565 Jul 10 06:07:56 PM PDT 24 Jul 10 06:07:58 PM PDT 24 417108375 ps
T387 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1560416949 Jul 10 06:08:21 PM PDT 24 Jul 10 06:08:22 PM PDT 24 450063623 ps
T56 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3772685607 Jul 10 06:08:20 PM PDT 24 Jul 10 06:08:22 PM PDT 24 475304857 ps
T388 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2915191086 Jul 10 06:08:23 PM PDT 24 Jul 10 06:08:26 PM PDT 24 309492690 ps
T389 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1305707190 Jul 10 06:08:01 PM PDT 24 Jul 10 06:08:04 PM PDT 24 451023002 ps
T390 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3689940078 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:15 PM PDT 24 1752779761 ps
T391 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.438812651 Jul 10 06:08:10 PM PDT 24 Jul 10 06:08:13 PM PDT 24 337259160 ps
T392 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.315025900 Jul 10 06:08:16 PM PDT 24 Jul 10 06:08:18 PM PDT 24 362255324 ps
T393 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.135820897 Jul 10 06:08:10 PM PDT 24 Jul 10 06:08:13 PM PDT 24 1695411869 ps
T57 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2712701416 Jul 10 06:08:20 PM PDT 24 Jul 10 06:08:22 PM PDT 24 536303898 ps
T394 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2284806002 Jul 10 06:08:12 PM PDT 24 Jul 10 06:08:17 PM PDT 24 614158164 ps
T395 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.884334148 Jul 10 06:08:15 PM PDT 24 Jul 10 06:08:17 PM PDT 24 382665329 ps
T396 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1353226109 Jul 10 06:07:57 PM PDT 24 Jul 10 06:08:00 PM PDT 24 352532315 ps
T397 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2826440612 Jul 10 06:08:15 PM PDT 24 Jul 10 06:08:18 PM PDT 24 455200418 ps
T398 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1254508979 Jul 10 06:07:59 PM PDT 24 Jul 10 06:08:03 PM PDT 24 526163708 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.402396934 Jul 10 06:07:54 PM PDT 24 Jul 10 06:07:58 PM PDT 24 397385314 ps
T400 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.102350855 Jul 10 06:08:23 PM PDT 24 Jul 10 06:08:25 PM PDT 24 319115799 ps
T401 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3817644869 Jul 10 06:08:04 PM PDT 24 Jul 10 06:08:06 PM PDT 24 379999048 ps
T58 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1122463188 Jul 10 06:08:04 PM PDT 24 Jul 10 06:08:20 PM PDT 24 6221730910 ps
T402 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3271934395 Jul 10 06:08:30 PM PDT 24 Jul 10 06:08:31 PM PDT 24 302109739 ps
T403 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3015740553 Jul 10 06:08:17 PM PDT 24 Jul 10 06:08:26 PM PDT 24 3981348281 ps
T404 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2989337421 Jul 10 06:08:02 PM PDT 24 Jul 10 06:08:05 PM PDT 24 396956228 ps
T405 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.679951202 Jul 10 06:08:16 PM PDT 24 Jul 10 06:08:19 PM PDT 24 410093391 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1804660925 Jul 10 06:07:58 PM PDT 24 Jul 10 06:07:59 PM PDT 24 1179361135 ps
T407 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3129987481 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:08 PM PDT 24 2359116830 ps
T408 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.739876716 Jul 10 06:08:05 PM PDT 24 Jul 10 06:08:10 PM PDT 24 4232405909 ps
T409 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.883885480 Jul 10 06:08:24 PM PDT 24 Jul 10 06:08:26 PM PDT 24 441556672 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4186269506 Jul 10 06:08:12 PM PDT 24 Jul 10 06:08:15 PM PDT 24 481544182 ps
T411 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.242276032 Jul 10 06:08:21 PM PDT 24 Jul 10 06:08:23 PM PDT 24 540934638 ps
T412 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1360921094 Jul 10 06:07:52 PM PDT 24 Jul 10 06:07:54 PM PDT 24 4487266072 ps
T413 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4188363613 Jul 10 06:08:29 PM PDT 24 Jul 10 06:08:31 PM PDT 24 349569815 ps
T414 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2204271776 Jul 10 06:08:00 PM PDT 24 Jul 10 06:08:03 PM PDT 24 1018161543 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.938822229 Jul 10 06:08:12 PM PDT 24 Jul 10 06:08:15 PM PDT 24 600674183 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.843446390 Jul 10 06:08:00 PM PDT 24 Jul 10 06:08:03 PM PDT 24 446003191 ps
T417 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2531305022 Jul 10 06:08:15 PM PDT 24 Jul 10 06:08:17 PM PDT 24 539891407 ps
T418 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1318618204 Jul 10 06:08:11 PM PDT 24 Jul 10 06:08:16 PM PDT 24 8332013320 ps
T419 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2669099438 Jul 10 06:07:54 PM PDT 24 Jul 10 06:07:57 PM PDT 24 306104823 ps
T420 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2460318323 Jul 10 06:08:06 PM PDT 24 Jul 10 06:08:10 PM PDT 24 592623553 ps
T421 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2531115958 Jul 10 06:08:13 PM PDT 24 Jul 10 06:08:18 PM PDT 24 4148548637 ps
T422 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3757510251 Jul 10 06:08:05 PM PDT 24 Jul 10 06:08:08 PM PDT 24 432057436 ps
T423 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2469672145 Jul 10 06:07:56 PM PDT 24 Jul 10 06:07:58 PM PDT 24 597462611 ps
T424 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1507581258 Jul 10 06:08:07 PM PDT 24 Jul 10 06:08:10 PM PDT 24 317302892 ps

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3800465914
Short name T5
Test name
Test status
Simulation time 67015870379 ps
CPU time 122.69 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:05:41 PM PDT 24
Peak memory 198648 kb
Host smart-79a01390-e4ee-40e3-836c-c35360f7fff6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800465914 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3800465914
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.286386981
Short name T4
Test name
Test status
Simulation time 333463999320 ps
CPU time 526.69 seconds
Started Jul 10 06:04:17 PM PDT 24
Finished Jul 10 06:13:04 PM PDT 24
Peak memory 204924 kb
Host smart-c0982ff4-1204-4784-aa88-99630b683f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286386981 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.286386981
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3833222493
Short name T24
Test name
Test status
Simulation time 8122233847 ps
CPU time 4.95 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:05 PM PDT 24
Peak memory 198264 kb
Host smart-83fbf7be-925f-4de5-b756-eb4f71892c80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833222493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3833222493
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1037517136
Short name T1
Test name
Test status
Simulation time 226515975653 ps
CPU time 271.58 seconds
Started Jul 10 06:03:59 PM PDT 24
Finished Jul 10 06:08:32 PM PDT 24
Peak memory 193072 kb
Host smart-2507532a-0e3d-4df6-86e5-7d865c944abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037517136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1037517136
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.257712249
Short name T69
Test name
Test status
Simulation time 186192226591 ps
CPU time 761.95 seconds
Started Jul 10 06:03:37 PM PDT 24
Finished Jul 10 06:16:22 PM PDT 24
Peak memory 207172 kb
Host smart-c1e9b14b-1952-445f-9fe4-1f98829a2455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257712249 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.257712249
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3611753048
Short name T80
Test name
Test status
Simulation time 42823316749 ps
CPU time 346.07 seconds
Started Jul 10 06:03:51 PM PDT 24
Finished Jul 10 06:09:38 PM PDT 24
Peak memory 207316 kb
Host smart-f362d397-d7df-4e69-b999-4b3c5d822c89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611753048 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3611753048
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1766078133
Short name T49
Test name
Test status
Simulation time 580546411 ps
CPU time 0.67 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:13 PM PDT 24
Peak memory 193340 kb
Host smart-2e2443f5-f2fb-4d67-85af-1fc416c61a3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766078133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1766078133
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3132900147
Short name T104
Test name
Test status
Simulation time 112218427897 ps
CPU time 895.99 seconds
Started Jul 10 06:03:35 PM PDT 24
Finished Jul 10 06:18:34 PM PDT 24
Peak memory 214948 kb
Host smart-97dfd48a-2658-400e-b558-72be1fac20f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132900147 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3132900147
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1435480977
Short name T31
Test name
Test status
Simulation time 102880634239 ps
CPU time 42.48 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:04:48 PM PDT 24
Peak memory 192532 kb
Host smart-85d941ad-7453-4c22-bf97-52e3d4569410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435480977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1435480977
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3196726974
Short name T120
Test name
Test status
Simulation time 925644017827 ps
CPU time 767.39 seconds
Started Jul 10 06:04:24 PM PDT 24
Finished Jul 10 06:17:14 PM PDT 24
Peak memory 215148 kb
Host smart-08e3db78-f6ca-4f1f-aa12-d77406c24ab8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196726974 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3196726974
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1974763129
Short name T85
Test name
Test status
Simulation time 49364973369 ps
CPU time 75.26 seconds
Started Jul 10 06:03:23 PM PDT 24
Finished Jul 10 06:04:39 PM PDT 24
Peak memory 191968 kb
Host smart-2fdc7106-07d2-460b-9810-a2915e17b809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974763129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1974763129
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3362014452
Short name T42
Test name
Test status
Simulation time 92023190763 ps
CPU time 13.06 seconds
Started Jul 10 06:03:51 PM PDT 24
Finished Jul 10 06:04:05 PM PDT 24
Peak memory 198472 kb
Host smart-5e6cfbf3-acb1-4c3d-bad3-46c15ba86552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362014452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3362014452
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.34992820
Short name T17
Test name
Test status
Simulation time 4286438521 ps
CPU time 3.48 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:03:29 PM PDT 24
Peak memory 215408 kb
Host smart-70ffa2ea-83b6-4b24-af8a-f355cddbb590
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34992820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.34992820
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3503821768
Short name T106
Test name
Test status
Simulation time 77816956314 ps
CPU time 416.34 seconds
Started Jul 10 06:04:09 PM PDT 24
Finished Jul 10 06:11:07 PM PDT 24
Peak memory 203064 kb
Host smart-cdf312c5-4a06-4129-ae5d-332dd25c1542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503821768 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3503821768
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3297788655
Short name T77
Test name
Test status
Simulation time 33010810061 ps
CPU time 247.58 seconds
Started Jul 10 06:03:32 PM PDT 24
Finished Jul 10 06:07:41 PM PDT 24
Peak memory 206824 kb
Host smart-d996d4cf-dac0-4f76-96ce-d89716b274bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297788655 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3297788655
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3506415035
Short name T96
Test name
Test status
Simulation time 104599301133 ps
CPU time 132.6 seconds
Started Jul 10 06:03:35 PM PDT 24
Finished Jul 10 06:05:50 PM PDT 24
Peak memory 198324 kb
Host smart-b79c5752-45e4-4e04-8051-b2c3a5af7e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506415035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3506415035
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2080872093
Short name T9
Test name
Test status
Simulation time 187550707316 ps
CPU time 171.07 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:06:55 PM PDT 24
Peak memory 200020 kb
Host smart-1a3a2bfb-d36d-4f1e-b225-62b1fbb20b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080872093 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2080872093
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2699964070
Short name T98
Test name
Test status
Simulation time 368916240720 ps
CPU time 135.51 seconds
Started Jul 10 06:03:29 PM PDT 24
Finished Jul 10 06:05:46 PM PDT 24
Peak memory 193092 kb
Host smart-34274c52-65bf-44dd-9e7d-4128f1e8d700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699964070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2699964070
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.453587492
Short name T90
Test name
Test status
Simulation time 246811904676 ps
CPU time 230.45 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:07:59 PM PDT 24
Peak memory 200752 kb
Host smart-b8728c37-b49f-4768-8b6c-d712d979bc51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453587492 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.453587492
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3931053157
Short name T111
Test name
Test status
Simulation time 259056857152 ps
CPU time 578.69 seconds
Started Jul 10 06:03:31 PM PDT 24
Finished Jul 10 06:13:11 PM PDT 24
Peak memory 204848 kb
Host smart-894d03be-fe5e-4aed-9f30-8a9320fcebf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931053157 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3931053157
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.784509043
Short name T21
Test name
Test status
Simulation time 365035686590 ps
CPU time 638.15 seconds
Started Jul 10 06:04:25 PM PDT 24
Finished Jul 10 06:15:06 PM PDT 24
Peak memory 205968 kb
Host smart-c8ced414-2dea-4f3f-9985-e96ef8c46222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784509043 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.784509043
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1472352531
Short name T44
Test name
Test status
Simulation time 79985774789 ps
CPU time 27.95 seconds
Started Jul 10 06:04:24 PM PDT 24
Finished Jul 10 06:04:53 PM PDT 24
Peak memory 192048 kb
Host smart-f0dcd9d1-7446-413d-8d90-cc2b6cb2df89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472352531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1472352531
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.845105112
Short name T97
Test name
Test status
Simulation time 125752232115 ps
CPU time 36.01 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:04:41 PM PDT 24
Peak memory 198348 kb
Host smart-a2819779-ef62-4a04-872d-4ab8c06a3be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845105112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.845105112
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1908093928
Short name T73
Test name
Test status
Simulation time 263063351981 ps
CPU time 1392.07 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:27:17 PM PDT 24
Peak memory 215520 kb
Host smart-0024829a-d18b-45de-9237-3f2c76ecde7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908093928 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1908093928
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1274240183
Short name T133
Test name
Test status
Simulation time 130304203335 ps
CPU time 541.31 seconds
Started Jul 10 06:03:59 PM PDT 24
Finished Jul 10 06:13:01 PM PDT 24
Peak memory 212592 kb
Host smart-14f1989c-42e2-4dbc-ae8d-a70dfaa35012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274240183 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1274240183
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1686721093
Short name T83
Test name
Test status
Simulation time 304710276485 ps
CPU time 93.59 seconds
Started Jul 10 06:04:16 PM PDT 24
Finished Jul 10 06:05:51 PM PDT 24
Peak memory 191988 kb
Host smart-554fc863-ff3b-4ca0-8764-cd900b1e8800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686721093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1686721093
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3986222123
Short name T110
Test name
Test status
Simulation time 61453345665 ps
CPU time 155.18 seconds
Started Jul 10 06:03:46 PM PDT 24
Finished Jul 10 06:06:22 PM PDT 24
Peak memory 198660 kb
Host smart-2867d7c9-55ee-4f1a-8ad7-a0d2feb083f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986222123 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3986222123
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2939192815
Short name T108
Test name
Test status
Simulation time 426583330883 ps
CPU time 309.7 seconds
Started Jul 10 06:04:16 PM PDT 24
Finished Jul 10 06:09:27 PM PDT 24
Peak memory 198340 kb
Host smart-fdf5c785-a32f-4a68-a59b-c5579dae09e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939192815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2939192815
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2751175983
Short name T148
Test name
Test status
Simulation time 60125058199 ps
CPU time 378.35 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:09:57 PM PDT 24
Peak memory 206852 kb
Host smart-866b493c-3457-4c77-b017-8cd10004c6a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751175983 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2751175983
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2481335020
Short name T131
Test name
Test status
Simulation time 32787748600 ps
CPU time 342.01 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:09:08 PM PDT 24
Peak memory 198728 kb
Host smart-d5564996-0692-448f-a866-280780623367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481335020 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2481335020
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.436752814
Short name T95
Test name
Test status
Simulation time 176716843385 ps
CPU time 285.15 seconds
Started Jul 10 06:04:09 PM PDT 24
Finished Jul 10 06:08:56 PM PDT 24
Peak memory 184276 kb
Host smart-8e389d98-1ba9-401f-8455-2ce0e1af8e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436752814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.436752814
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3734970767
Short name T10
Test name
Test status
Simulation time 3443812801 ps
CPU time 5.82 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:03:31 PM PDT 24
Peak memory 191984 kb
Host smart-504c06ee-214e-4530-ad67-8a710fce066a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734970767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3734970767
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.110514955
Short name T29
Test name
Test status
Simulation time 24269212052 ps
CPU time 195.28 seconds
Started Jul 10 06:04:06 PM PDT 24
Finished Jul 10 06:07:22 PM PDT 24
Peak memory 213332 kb
Host smart-76f9bd45-83da-4991-9a88-2f7526423516
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110514955 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.110514955
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3483368676
Short name T114
Test name
Test status
Simulation time 52459750270 ps
CPU time 79.73 seconds
Started Jul 10 06:03:44 PM PDT 24
Finished Jul 10 06:05:05 PM PDT 24
Peak memory 184248 kb
Host smart-2d0279cd-3751-41c3-b941-30d60639dd5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483368676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3483368676
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.317790717
Short name T87
Test name
Test status
Simulation time 45105017595 ps
CPU time 467.87 seconds
Started Jul 10 06:04:08 PM PDT 24
Finished Jul 10 06:11:58 PM PDT 24
Peak memory 209400 kb
Host smart-e4d798fc-7459-4e93-9519-e768deb3e425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317790717 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.317790717
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3359459856
Short name T117
Test name
Test status
Simulation time 43692566216 ps
CPU time 18.56 seconds
Started Jul 10 06:04:15 PM PDT 24
Finished Jul 10 06:04:35 PM PDT 24
Peak memory 198368 kb
Host smart-0d7ced22-527c-4295-9d8c-6e2932cf5941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359459856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3359459856
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3858063917
Short name T14
Test name
Test status
Simulation time 139677227645 ps
CPU time 549.82 seconds
Started Jul 10 06:04:15 PM PDT 24
Finished Jul 10 06:13:26 PM PDT 24
Peak memory 204288 kb
Host smart-88532cbe-1f61-4648-8f60-a78238ec7e88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858063917 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3858063917
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1166934776
Short name T81
Test name
Test status
Simulation time 265961510962 ps
CPU time 394.05 seconds
Started Jul 10 06:03:47 PM PDT 24
Finished Jul 10 06:10:22 PM PDT 24
Peak memory 192652 kb
Host smart-de50da03-a602-4ca6-ae85-7fbb572baab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166934776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1166934776
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.917188469
Short name T72
Test name
Test status
Simulation time 220765514303 ps
CPU time 739.57 seconds
Started Jul 10 06:04:01 PM PDT 24
Finished Jul 10 06:16:22 PM PDT 24
Peak memory 214908 kb
Host smart-c0f89808-8aad-47d5-ac4c-cdd2b42ef1b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917188469 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.917188469
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1625842655
Short name T71
Test name
Test status
Simulation time 103155180112 ps
CPU time 373.18 seconds
Started Jul 10 06:03:32 PM PDT 24
Finished Jul 10 06:09:46 PM PDT 24
Peak memory 200156 kb
Host smart-d93a1c84-a231-4ccf-ad14-007060cd0eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625842655 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1625842655
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2022892513
Short name T135
Test name
Test status
Simulation time 114042686031 ps
CPU time 158.54 seconds
Started Jul 10 06:03:37 PM PDT 24
Finished Jul 10 06:06:18 PM PDT 24
Peak memory 198508 kb
Host smart-e714e6b3-19f9-4205-8627-129939b15cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022892513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2022892513
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1380862734
Short name T40
Test name
Test status
Simulation time 210527912465 ps
CPU time 32.58 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:04:41 PM PDT 24
Peak memory 198328 kb
Host smart-b08d3239-ac67-4b9f-b1bd-a35836dd6ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380862734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1380862734
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.999840250
Short name T130
Test name
Test status
Simulation time 134130277864 ps
CPU time 189.15 seconds
Started Jul 10 06:03:37 PM PDT 24
Finished Jul 10 06:06:49 PM PDT 24
Peak memory 198224 kb
Host smart-62cfc11b-bb03-413f-8636-c441b93200f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999840250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.999840250
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2746911586
Short name T37
Test name
Test status
Simulation time 114013948279 ps
CPU time 37.61 seconds
Started Jul 10 06:03:30 PM PDT 24
Finished Jul 10 06:04:09 PM PDT 24
Peak memory 191976 kb
Host smart-c7cb09b9-926c-4724-bd39-5f4ec8b2ed0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746911586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2746911586
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.475340949
Short name T107
Test name
Test status
Simulation time 201200632260 ps
CPU time 264.45 seconds
Started Jul 10 06:03:41 PM PDT 24
Finished Jul 10 06:08:08 PM PDT 24
Peak memory 214200 kb
Host smart-10b9de5c-3e7e-4017-9038-56bcd7d8f599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475340949 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.475340949
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3965523131
Short name T89
Test name
Test status
Simulation time 4381498159 ps
CPU time 2.45 seconds
Started Jul 10 06:03:39 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 184256 kb
Host smart-de8407ce-cc25-4f08-98fe-d701a4008876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965523131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3965523131
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2539895434
Short name T103
Test name
Test status
Simulation time 171339721438 ps
CPU time 46.43 seconds
Started Jul 10 06:03:50 PM PDT 24
Finished Jul 10 06:04:38 PM PDT 24
Peak memory 198304 kb
Host smart-4c8e4e62-ea19-4475-a85d-8739931fa802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539895434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2539895434
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.712733419
Short name T32
Test name
Test status
Simulation time 409375487165 ps
CPU time 133.98 seconds
Started Jul 10 06:03:59 PM PDT 24
Finished Jul 10 06:06:14 PM PDT 24
Peak memory 198200 kb
Host smart-01fb63ff-5d64-4ead-ab58-cdc52838b6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712733419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.712733419
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2790184144
Short name T101
Test name
Test status
Simulation time 52681418841 ps
CPU time 45.3 seconds
Started Jul 10 06:04:11 PM PDT 24
Finished Jul 10 06:04:57 PM PDT 24
Peak memory 191984 kb
Host smart-799f7877-9d07-43a0-9021-ddba32df4147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790184144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2790184144
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2504232542
Short name T119
Test name
Test status
Simulation time 20144198901 ps
CPU time 3.5 seconds
Started Jul 10 06:03:31 PM PDT 24
Finished Jul 10 06:03:35 PM PDT 24
Peak memory 191960 kb
Host smart-e44161af-3764-4751-af4d-6de21800c910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504232542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2504232542
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2950894830
Short name T78
Test name
Test status
Simulation time 145651466586 ps
CPU time 211.73 seconds
Started Jul 10 06:03:29 PM PDT 24
Finished Jul 10 06:07:01 PM PDT 24
Peak memory 200444 kb
Host smart-a08e6d8d-66a7-40f1-a02f-1f84a03b2391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950894830 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2950894830
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2803715093
Short name T79
Test name
Test status
Simulation time 110596879214 ps
CPU time 29.54 seconds
Started Jul 10 06:03:45 PM PDT 24
Finished Jul 10 06:04:15 PM PDT 24
Peak memory 184476 kb
Host smart-82f172fd-6c53-4c12-a0be-2d212789b47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803715093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2803715093
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3891033697
Short name T93
Test name
Test status
Simulation time 116923718571 ps
CPU time 41.16 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:04:50 PM PDT 24
Peak memory 184240 kb
Host smart-703b7383-ffba-4a69-b3bd-5956ee4f99ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891033697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3891033697
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2043853834
Short name T129
Test name
Test status
Simulation time 22025497117 ps
CPU time 244.03 seconds
Started Jul 10 06:04:04 PM PDT 24
Finished Jul 10 06:08:10 PM PDT 24
Peak memory 206836 kb
Host smart-acf58dbf-d729-4952-85b0-b3937a9a1350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043853834 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2043853834
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.255785510
Short name T35
Test name
Test status
Simulation time 23470783093 ps
CPU time 106.04 seconds
Started Jul 10 06:03:28 PM PDT 24
Finished Jul 10 06:05:15 PM PDT 24
Peak memory 206900 kb
Host smart-ed3747b4-f5fd-4c96-adc8-db95601e634a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255785510 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.255785510
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3808358110
Short name T30
Test name
Test status
Simulation time 57599455913 ps
CPU time 595.48 seconds
Started Jul 10 06:04:14 PM PDT 24
Finished Jul 10 06:14:10 PM PDT 24
Peak memory 211788 kb
Host smart-e39855b0-735d-4857-9478-826d2b3ef5fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808358110 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3808358110
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4060000979
Short name T59
Test name
Test status
Simulation time 1595338156 ps
CPU time 3.68 seconds
Started Jul 10 06:07:54 PM PDT 24
Finished Jul 10 06:08:00 PM PDT 24
Peak memory 193108 kb
Host smart-aa4c87f1-ec11-4f24-8432-34e932c7cdad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060000979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.4060000979
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2977452208
Short name T75
Test name
Test status
Simulation time 30038846978 ps
CPU time 215.39 seconds
Started Jul 10 06:03:39 PM PDT 24
Finished Jul 10 06:07:18 PM PDT 24
Peak memory 198636 kb
Host smart-27f10c54-8402-441a-9f89-be9f22554ddf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977452208 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2977452208
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2980900009
Short name T118
Test name
Test status
Simulation time 303548833278 ps
CPU time 452.14 seconds
Started Jul 10 06:03:41 PM PDT 24
Finished Jul 10 06:11:16 PM PDT 24
Peak memory 192068 kb
Host smart-57ac6a7a-a383-4748-bee1-92d85b935de3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980900009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2980900009
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2673760969
Short name T76
Test name
Test status
Simulation time 128601587549 ps
CPU time 146.47 seconds
Started Jul 10 06:04:09 PM PDT 24
Finished Jul 10 06:06:37 PM PDT 24
Peak memory 207936 kb
Host smart-1ca04bbc-5086-4ad3-bb91-bf0ba7f14f88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673760969 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2673760969
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2427055530
Short name T102
Test name
Test status
Simulation time 284473836808 ps
CPU time 88.36 seconds
Started Jul 10 06:03:39 PM PDT 24
Finished Jul 10 06:05:11 PM PDT 24
Peak memory 198356 kb
Host smart-8384164e-f6d6-4491-a3b4-57565cdc41c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427055530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2427055530
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3761416355
Short name T27
Test name
Test status
Simulation time 95553872391 ps
CPU time 354.11 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:09:19 PM PDT 24
Peak memory 214080 kb
Host smart-927c33d7-3a04-4771-abf3-228dd0cfb405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761416355 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3761416355
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1837508180
Short name T100
Test name
Test status
Simulation time 4260914597 ps
CPU time 2.43 seconds
Started Jul 10 06:03:47 PM PDT 24
Finished Jul 10 06:03:50 PM PDT 24
Peak memory 191968 kb
Host smart-79abed69-4ff8-41db-aff4-61c885a079c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837508180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1837508180
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.235254023
Short name T88
Test name
Test status
Simulation time 247580555757 ps
CPU time 197.59 seconds
Started Jul 10 06:04:02 PM PDT 24
Finished Jul 10 06:07:21 PM PDT 24
Peak memory 193064 kb
Host smart-55112dba-6a28-4457-8586-913e21d3f906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235254023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.235254023
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.825902651
Short name T125
Test name
Test status
Simulation time 87221378365 ps
CPU time 488.11 seconds
Started Jul 10 06:04:17 PM PDT 24
Finished Jul 10 06:12:26 PM PDT 24
Peak memory 212620 kb
Host smart-4b239346-e2bb-42d3-be36-c9f27ca0064c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825902651 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.825902651
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3841810967
Short name T134
Test name
Test status
Simulation time 361783493497 ps
CPU time 270.45 seconds
Started Jul 10 06:04:17 PM PDT 24
Finished Jul 10 06:08:48 PM PDT 24
Peak memory 198308 kb
Host smart-4477b70e-d2e0-44dc-90bc-47e1e6d7d514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841810967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3841810967
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2821460537
Short name T139
Test name
Test status
Simulation time 65407137623 ps
CPU time 337.32 seconds
Started Jul 10 06:03:47 PM PDT 24
Finished Jul 10 06:09:26 PM PDT 24
Peak memory 208964 kb
Host smart-02a94881-7022-4ae7-8734-4f3b797a78b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821460537 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2821460537
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4184750043
Short name T82
Test name
Test status
Simulation time 80238403132 ps
CPU time 71.59 seconds
Started Jul 10 06:03:28 PM PDT 24
Finished Jul 10 06:04:41 PM PDT 24
Peak memory 192032 kb
Host smart-077f5ade-1cbe-49fc-9a88-841d0913e69b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184750043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4184750043
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1285961426
Short name T28
Test name
Test status
Simulation time 44466376484 ps
CPU time 169.48 seconds
Started Jul 10 06:03:47 PM PDT 24
Finished Jul 10 06:06:37 PM PDT 24
Peak memory 198608 kb
Host smart-7304d88b-66d8-4a7e-b23c-1cc28ad366fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285961426 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1285961426
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.672775682
Short name T20
Test name
Test status
Simulation time 113570790529 ps
CPU time 36.38 seconds
Started Jul 10 06:03:46 PM PDT 24
Finished Jul 10 06:04:24 PM PDT 24
Peak memory 184228 kb
Host smart-02f5002b-4c23-43a4-a6d9-4f5133062067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672775682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.672775682
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3933849528
Short name T113
Test name
Test status
Simulation time 517971098 ps
CPU time 1.33 seconds
Started Jul 10 06:03:51 PM PDT 24
Finished Jul 10 06:03:54 PM PDT 24
Peak memory 196716 kb
Host smart-8fcb35ca-cf08-468f-b672-f184ca444a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933849528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3933849528
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.244250849
Short name T7
Test name
Test status
Simulation time 545658074 ps
CPU time 0.99 seconds
Started Jul 10 06:04:00 PM PDT 24
Finished Jul 10 06:04:01 PM PDT 24
Peak memory 196632 kb
Host smart-24e5c55b-ff18-4b39-94d4-18fa59a720e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244250849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.244250849
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.38076538
Short name T12
Test name
Test status
Simulation time 52049869486 ps
CPU time 75.23 seconds
Started Jul 10 06:03:31 PM PDT 24
Finished Jul 10 06:04:47 PM PDT 24
Peak memory 198616 kb
Host smart-4b2de445-0504-44ff-8d87-7e548d0bd93a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38076538 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.38076538
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3421790941
Short name T127
Test name
Test status
Simulation time 519282343 ps
CPU time 1.33 seconds
Started Jul 10 06:03:57 PM PDT 24
Finished Jul 10 06:03:59 PM PDT 24
Peak memory 196744 kb
Host smart-ea4f3384-d0ee-437c-8f7f-6c708acfdd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421790941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3421790941
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.763346635
Short name T126
Test name
Test status
Simulation time 440649552 ps
CPU time 1.13 seconds
Started Jul 10 06:03:34 PM PDT 24
Finished Jul 10 06:03:36 PM PDT 24
Peak memory 196644 kb
Host smart-94672b03-ddb7-4cc1-8f12-7e6c929da57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763346635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.763346635
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1221293382
Short name T94
Test name
Test status
Simulation time 465183961 ps
CPU time 1.2 seconds
Started Jul 10 06:03:34 PM PDT 24
Finished Jul 10 06:03:36 PM PDT 24
Peak memory 196712 kb
Host smart-4cf50016-da76-4615-9f3a-8098658c8bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221293382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1221293382
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1091672850
Short name T140
Test name
Test status
Simulation time 253262239393 ps
CPU time 84.09 seconds
Started Jul 10 06:03:47 PM PDT 24
Finished Jul 10 06:05:12 PM PDT 24
Peak memory 192948 kb
Host smart-d7161343-a6dc-4901-995e-f4a5b4c0010b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091672850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1091672850
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3357054078
Short name T109
Test name
Test status
Simulation time 33264178700 ps
CPU time 141.45 seconds
Started Jul 10 06:03:40 PM PDT 24
Finished Jul 10 06:06:05 PM PDT 24
Peak memory 206828 kb
Host smart-239d87dc-0840-48a2-bd55-cf27bb8fb35f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357054078 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3357054078
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1259256449
Short name T121
Test name
Test status
Simulation time 559720819 ps
CPU time 0.78 seconds
Started Jul 10 06:03:45 PM PDT 24
Finished Jul 10 06:03:47 PM PDT 24
Peak memory 196780 kb
Host smart-4f3b1d98-df10-463d-9366-348da029834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259256449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1259256449
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3339498656
Short name T68
Test name
Test status
Simulation time 199097263330 ps
CPU time 210.54 seconds
Started Jul 10 06:03:51 PM PDT 24
Finished Jul 10 06:07:22 PM PDT 24
Peak memory 199176 kb
Host smart-0ebdf754-79b5-4953-9d24-59ad2aa02ba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339498656 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3339498656
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2448838353
Short name T45
Test name
Test status
Simulation time 87942349231 ps
CPU time 564.93 seconds
Started Jul 10 06:03:53 PM PDT 24
Finished Jul 10 06:13:19 PM PDT 24
Peak memory 201680 kb
Host smart-a87bfcf8-0706-49e9-8181-db1f1c6630ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448838353 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2448838353
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2229896190
Short name T99
Test name
Test status
Simulation time 169116482799 ps
CPU time 49.57 seconds
Started Jul 10 06:03:30 PM PDT 24
Finished Jul 10 06:04:21 PM PDT 24
Peak memory 198308 kb
Host smart-395fb87d-b034-4ace-8281-93aa88a57c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229896190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2229896190
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1992364967
Short name T86
Test name
Test status
Simulation time 386802787 ps
CPU time 0.86 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:04:09 PM PDT 24
Peak memory 196732 kb
Host smart-690193c1-a5c4-4dce-a8f3-224db2dba204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992364967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1992364967
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2206468604
Short name T138
Test name
Test status
Simulation time 331225722550 ps
CPU time 28.45 seconds
Started Jul 10 06:04:12 PM PDT 24
Finished Jul 10 06:04:42 PM PDT 24
Peak memory 193072 kb
Host smart-06fe0217-8607-4d9e-ae37-7e804b90a313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206468604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2206468604
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1506890542
Short name T122
Test name
Test status
Simulation time 48108940617 ps
CPU time 65.19 seconds
Started Jul 10 06:03:30 PM PDT 24
Finished Jul 10 06:04:36 PM PDT 24
Peak memory 191880 kb
Host smart-ba6df74d-976a-403d-bdc6-bd762dba4981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506890542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1506890542
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.984566686
Short name T116
Test name
Test status
Simulation time 166606079882 ps
CPU time 242.38 seconds
Started Jul 10 06:03:37 PM PDT 24
Finished Jul 10 06:07:43 PM PDT 24
Peak memory 184500 kb
Host smart-cec232b4-ab6f-4590-af91-f10bd9c518b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984566686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.984566686
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.375103359
Short name T84
Test name
Test status
Simulation time 483688558 ps
CPU time 0.72 seconds
Started Jul 10 06:03:41 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 196716 kb
Host smart-b4e123c6-1313-4edb-b3ad-e7e9edddf875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375103359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.375103359
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1123623196
Short name T92
Test name
Test status
Simulation time 142186555861 ps
CPU time 215.85 seconds
Started Jul 10 06:03:57 PM PDT 24
Finished Jul 10 06:07:33 PM PDT 24
Peak memory 191976 kb
Host smart-570d1fe1-338d-4d55-93a9-dd72432eee0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123623196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1123623196
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1821924724
Short name T124
Test name
Test status
Simulation time 520343154 ps
CPU time 0.84 seconds
Started Jul 10 06:04:01 PM PDT 24
Finished Jul 10 06:04:03 PM PDT 24
Peak memory 196856 kb
Host smart-ca582cc3-214e-4e31-913c-1ee67425fef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821924724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1821924724
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.147953482
Short name T137
Test name
Test status
Simulation time 167535078192 ps
CPU time 121.04 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:06:06 PM PDT 24
Peak memory 191964 kb
Host smart-28abb03c-7fa2-44c5-ac07-3a2414c3fc8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147953482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.147953482
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1242277134
Short name T157
Test name
Test status
Simulation time 120051701996 ps
CPU time 86.68 seconds
Started Jul 10 06:04:13 PM PDT 24
Finished Jul 10 06:05:41 PM PDT 24
Peak memory 193052 kb
Host smart-e0716f7a-1fed-43ec-a6e1-1066dfc13ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242277134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1242277134
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3202916062
Short name T74
Test name
Test status
Simulation time 46263776743 ps
CPU time 361.21 seconds
Started Jul 10 06:03:37 PM PDT 24
Finished Jul 10 06:09:41 PM PDT 24
Peak memory 199692 kb
Host smart-97585052-e497-4eb1-911f-ad11e66801db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202916062 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3202916062
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2968236464
Short name T123
Test name
Test status
Simulation time 451666970 ps
CPU time 0.91 seconds
Started Jul 10 06:03:45 PM PDT 24
Finished Jul 10 06:03:47 PM PDT 24
Peak memory 196712 kb
Host smart-a67afc4b-c8b0-44c8-9ba7-36defd966f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968236464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2968236464
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3100377976
Short name T147
Test name
Test status
Simulation time 143805258366 ps
CPU time 384.92 seconds
Started Jul 10 06:03:52 PM PDT 24
Finished Jul 10 06:10:18 PM PDT 24
Peak memory 201416 kb
Host smart-c5a63465-1011-4f01-8de7-0b3e144b1f46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100377976 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3100377976
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3235044676
Short name T128
Test name
Test status
Simulation time 397581696 ps
CPU time 1.15 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:04:06 PM PDT 24
Peak memory 196724 kb
Host smart-2b62db13-f9fb-46ae-b045-4fab312b2f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235044676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3235044676
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3015163374
Short name T91
Test name
Test status
Simulation time 528186964 ps
CPU time 0.83 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:04:05 PM PDT 24
Peak memory 196736 kb
Host smart-6bdd1dd2-416a-44dc-aa41-0398c6a877b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015163374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3015163374
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3958821258
Short name T145
Test name
Test status
Simulation time 38317896532 ps
CPU time 15.16 seconds
Started Jul 10 06:04:11 PM PDT 24
Finished Jul 10 06:04:27 PM PDT 24
Peak memory 192996 kb
Host smart-5c8013f5-b1f6-4cd0-8abc-8994a83179b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958821258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3958821258
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3292551994
Short name T70
Test name
Test status
Simulation time 32504316272 ps
CPU time 56.21 seconds
Started Jul 10 06:04:09 PM PDT 24
Finished Jul 10 06:05:07 PM PDT 24
Peak memory 198628 kb
Host smart-b69f93b3-36ef-4ea6-a40b-37b72fbd4146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292551994 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3292551994
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.4186266705
Short name T136
Test name
Test status
Simulation time 505233977 ps
CPU time 0.72 seconds
Started Jul 10 06:03:35 PM PDT 24
Finished Jul 10 06:03:38 PM PDT 24
Peak memory 196912 kb
Host smart-d1ee781b-fce9-40e9-8fa1-d4c9602ba04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186266705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.4186266705
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2315903345
Short name T178
Test name
Test status
Simulation time 532465940 ps
CPU time 1.38 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:03:27 PM PDT 24
Peak memory 196712 kb
Host smart-fae49ff8-78ce-4b98-b061-7db70c1c56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315903345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2315903345
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2810630809
Short name T155
Test name
Test status
Simulation time 494981014 ps
CPU time 0.77 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:03:39 PM PDT 24
Peak memory 196772 kb
Host smart-9f9c5552-926e-4a6c-90f6-a79e60fec2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810630809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2810630809
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1948107499
Short name T38
Test name
Test status
Simulation time 56553624443 ps
CPU time 166.93 seconds
Started Jul 10 06:03:45 PM PDT 24
Finished Jul 10 06:06:33 PM PDT 24
Peak memory 206836 kb
Host smart-2b9e3f59-30a9-4b4a-bb5c-10b51ae199e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948107499 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1948107499
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.4271389560
Short name T112
Test name
Test status
Simulation time 427877280 ps
CPU time 1.27 seconds
Started Jul 10 06:04:14 PM PDT 24
Finished Jul 10 06:04:16 PM PDT 24
Peak memory 196716 kb
Host smart-2ed64936-339c-4e1f-b379-e02276d25bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271389560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.4271389560
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1087006902
Short name T115
Test name
Test status
Simulation time 391244645 ps
CPU time 1.14 seconds
Started Jul 10 06:03:30 PM PDT 24
Finished Jul 10 06:03:32 PM PDT 24
Peak memory 196716 kb
Host smart-5aca6041-ee9c-499b-931a-d0bcfdd9dd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087006902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1087006902
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2046288095
Short name T163
Test name
Test status
Simulation time 354259284 ps
CPU time 0.91 seconds
Started Jul 10 06:03:35 PM PDT 24
Finished Jul 10 06:03:38 PM PDT 24
Peak memory 196596 kb
Host smart-cb462e0c-2900-4aaf-b528-2f341b0ccc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046288095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2046288095
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3668146724
Short name T165
Test name
Test status
Simulation time 427973061 ps
CPU time 0.8 seconds
Started Jul 10 06:03:35 PM PDT 24
Finished Jul 10 06:03:38 PM PDT 24
Peak memory 196720 kb
Host smart-cf9f3117-0155-4f44-8bbc-54c6429f9e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668146724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3668146724
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.191140327
Short name T167
Test name
Test status
Simulation time 127787264651 ps
CPU time 180.54 seconds
Started Jul 10 06:03:37 PM PDT 24
Finished Jul 10 06:06:40 PM PDT 24
Peak memory 193012 kb
Host smart-874badfb-dfc9-4dc1-956e-dff19c83d9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191140327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.191140327
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2307925194
Short name T141
Test name
Test status
Simulation time 281336225776 ps
CPU time 94.27 seconds
Started Jul 10 06:03:46 PM PDT 24
Finished Jul 10 06:05:21 PM PDT 24
Peak memory 198352 kb
Host smart-1d6cc650-414b-43f7-89a0-01482b2b19dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307925194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2307925194
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3338591876
Short name T174
Test name
Test status
Simulation time 537792167 ps
CPU time 0.71 seconds
Started Jul 10 06:03:45 PM PDT 24
Finished Jul 10 06:03:47 PM PDT 24
Peak memory 196704 kb
Host smart-4cf4e96d-2419-4560-9774-9604876dd2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338591876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3338591876
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3122546338
Short name T146
Test name
Test status
Simulation time 575454538 ps
CPU time 0.8 seconds
Started Jul 10 06:03:52 PM PDT 24
Finished Jul 10 06:03:54 PM PDT 24
Peak memory 196760 kb
Host smart-873a8588-ed24-4f9b-be86-1bbf3fbf42c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122546338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3122546338
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1364598622
Short name T8
Test name
Test status
Simulation time 529856917 ps
CPU time 1.3 seconds
Started Jul 10 06:03:32 PM PDT 24
Finished Jul 10 06:03:35 PM PDT 24
Peak memory 196688 kb
Host smart-6552c239-1356-41a2-95f6-07e5e7f651e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364598622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1364598622
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2460835724
Short name T149
Test name
Test status
Simulation time 208811261579 ps
CPU time 298.56 seconds
Started Jul 10 06:03:59 PM PDT 24
Finished Jul 10 06:08:58 PM PDT 24
Peak memory 198332 kb
Host smart-3c150e93-9154-41c7-8ea7-5a0add7580e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460835724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2460835724
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3990038002
Short name T153
Test name
Test status
Simulation time 592379335 ps
CPU time 1.08 seconds
Started Jul 10 06:04:08 PM PDT 24
Finished Jul 10 06:04:10 PM PDT 24
Peak memory 196964 kb
Host smart-fd24b207-b987-4400-8af6-a4eea9d7f2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990038002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3990038002
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2505931735
Short name T158
Test name
Test status
Simulation time 465531447 ps
CPU time 1.25 seconds
Started Jul 10 06:04:01 PM PDT 24
Finished Jul 10 06:04:03 PM PDT 24
Peak memory 196720 kb
Host smart-77b7c3c2-786d-4727-a646-20fc64ae5bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505931735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2505931735
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.123101167
Short name T162
Test name
Test status
Simulation time 523352108 ps
CPU time 0.83 seconds
Started Jul 10 06:04:05 PM PDT 24
Finished Jul 10 06:04:07 PM PDT 24
Peak memory 196680 kb
Host smart-058e6111-7064-4ed0-ab7d-d696c5c98ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123101167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.123101167
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2572552378
Short name T159
Test name
Test status
Simulation time 216730270777 ps
CPU time 151.06 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:06:40 PM PDT 24
Peak memory 198360 kb
Host smart-3d85911a-1c28-4a3a-8f7c-6efda9c9733b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572552378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2572552378
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2078457232
Short name T33
Test name
Test status
Simulation time 385925565 ps
CPU time 0.75 seconds
Started Jul 10 06:03:29 PM PDT 24
Finished Jul 10 06:03:31 PM PDT 24
Peak memory 196716 kb
Host smart-255b17ee-a676-4658-af98-185d3da4b737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078457232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2078457232
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.683400466
Short name T179
Test name
Test status
Simulation time 429979126 ps
CPU time 0.8 seconds
Started Jul 10 06:04:14 PM PDT 24
Finished Jul 10 06:04:16 PM PDT 24
Peak memory 196696 kb
Host smart-bb87e184-6068-43d3-935d-2b9aa349d32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683400466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.683400466
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1402527574
Short name T176
Test name
Test status
Simulation time 495930055 ps
CPU time 1.31 seconds
Started Jul 10 06:04:16 PM PDT 24
Finished Jul 10 06:04:18 PM PDT 24
Peak memory 196696 kb
Host smart-ab0f113e-76db-4750-894d-a6cd954a3980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402527574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1402527574
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2764658123
Short name T164
Test name
Test status
Simulation time 504540804 ps
CPU time 1.25 seconds
Started Jul 10 06:04:25 PM PDT 24
Finished Jul 10 06:04:29 PM PDT 24
Peak memory 196708 kb
Host smart-647cd5ef-2b2e-4e65-a1b6-6e46d80611c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764658123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2764658123
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2162661093
Short name T144
Test name
Test status
Simulation time 466622997 ps
CPU time 0.75 seconds
Started Jul 10 06:03:34 PM PDT 24
Finished Jul 10 06:03:37 PM PDT 24
Peak memory 196880 kb
Host smart-ab227ce5-102d-4dec-9a27-7a0513b09547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162661093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2162661093
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2334385067
Short name T105
Test name
Test status
Simulation time 541927625 ps
CPU time 1.04 seconds
Started Jul 10 06:03:39 PM PDT 24
Finished Jul 10 06:03:42 PM PDT 24
Peak memory 196748 kb
Host smart-033d5c19-3a1b-4ce1-9f7f-2b4a663411b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334385067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2334385067
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2979176370
Short name T184
Test name
Test status
Simulation time 4889889815 ps
CPU time 2.74 seconds
Started Jul 10 06:08:10 PM PDT 24
Finished Jul 10 06:08:15 PM PDT 24
Peak memory 196840 kb
Host smart-ac2ff909-176a-4168-8c98-c7c9016e64e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979176370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2979176370
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1260991122
Short name T25
Test name
Test status
Simulation time 8278273904 ps
CPU time 13.42 seconds
Started Jul 10 06:08:07 PM PDT 24
Finished Jul 10 06:08:23 PM PDT 24
Peak memory 198388 kb
Host smart-0c50007d-b612-4335-a53f-a42addb54308
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260991122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1260991122
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.458754810
Short name T2
Test name
Test status
Simulation time 251409191425 ps
CPU time 174.54 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:06:34 PM PDT 24
Peak memory 193060 kb
Host smart-dcf87440-c5d5-46a7-83e1-6fd002677888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458754810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.458754810
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2281558543
Short name T132
Test name
Test status
Simulation time 480286295 ps
CPU time 0.96 seconds
Started Jul 10 06:03:35 PM PDT 24
Finished Jul 10 06:03:38 PM PDT 24
Peak memory 196792 kb
Host smart-e8c36311-3165-4d04-8656-11b086ff05f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281558543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2281558543
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.994010279
Short name T43
Test name
Test status
Simulation time 480810748 ps
CPU time 0.78 seconds
Started Jul 10 06:03:40 PM PDT 24
Finished Jul 10 06:03:43 PM PDT 24
Peak memory 196672 kb
Host smart-b33a2bdd-543d-43af-8d67-7a69066ee2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994010279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.994010279
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1344706644
Short name T171
Test name
Test status
Simulation time 519003129 ps
CPU time 0.92 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:03:26 PM PDT 24
Peak memory 196800 kb
Host smart-c87b4404-a0af-49b1-9798-8a4b5f0deb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344706644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1344706644
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4025897003
Short name T175
Test name
Test status
Simulation time 529254317 ps
CPU time 1.27 seconds
Started Jul 10 06:03:41 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 196772 kb
Host smart-7a234c18-1c1b-4731-8b45-1d8c588be3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025897003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4025897003
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2479304041
Short name T142
Test name
Test status
Simulation time 418103318 ps
CPU time 1.22 seconds
Started Jul 10 06:03:49 PM PDT 24
Finished Jul 10 06:03:51 PM PDT 24
Peak memory 196668 kb
Host smart-d1d5a53e-bb50-4dc4-ad12-c49850245909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479304041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2479304041
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2486685510
Short name T152
Test name
Test status
Simulation time 453922321675 ps
CPU time 310.79 seconds
Started Jul 10 06:04:04 PM PDT 24
Finished Jul 10 06:09:17 PM PDT 24
Peak memory 202120 kb
Host smart-736211e8-b550-4ceb-bd64-9b1a7a39ff15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486685510 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2486685510
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3860890791
Short name T143
Test name
Test status
Simulation time 254314688619 ps
CPU time 131.23 seconds
Started Jul 10 06:04:02 PM PDT 24
Finished Jul 10 06:06:15 PM PDT 24
Peak memory 193084 kb
Host smart-7a13d3a2-774f-45fe-999d-28f5340ccf58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860890791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3860890791
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3920594057
Short name T154
Test name
Test status
Simulation time 477560479 ps
CPU time 1.19 seconds
Started Jul 10 06:04:08 PM PDT 24
Finished Jul 10 06:04:11 PM PDT 24
Peak memory 196780 kb
Host smart-2fdfda5c-d3ff-4e43-a078-07133c0c3419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920594057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3920594057
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.184133892
Short name T168
Test name
Test status
Simulation time 14780406868 ps
CPU time 104.94 seconds
Started Jul 10 06:04:11 PM PDT 24
Finished Jul 10 06:05:57 PM PDT 24
Peak memory 198640 kb
Host smart-1b22f851-aa57-4598-9126-b55fe7df5bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184133892 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.184133892
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.232902882
Short name T150
Test name
Test status
Simulation time 404583247 ps
CPU time 1.29 seconds
Started Jul 10 06:04:09 PM PDT 24
Finished Jul 10 06:04:12 PM PDT 24
Peak memory 196684 kb
Host smart-8b71c989-2a5a-4c1c-8d64-aba81c86f307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232902882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.232902882
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1711259756
Short name T169
Test name
Test status
Simulation time 618009834 ps
CPU time 1.02 seconds
Started Jul 10 06:04:09 PM PDT 24
Finished Jul 10 06:04:12 PM PDT 24
Peak memory 196708 kb
Host smart-9522f29b-5412-4ef4-81f0-1837119aca72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711259756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1711259756
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1393428148
Short name T166
Test name
Test status
Simulation time 518020656 ps
CPU time 0.74 seconds
Started Jul 10 06:04:11 PM PDT 24
Finished Jul 10 06:04:13 PM PDT 24
Peak memory 196712 kb
Host smart-8fa87a9e-46de-4374-b628-d6f282daae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393428148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1393428148
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.269662107
Short name T182
Test name
Test status
Simulation time 500142727 ps
CPU time 0.83 seconds
Started Jul 10 06:04:14 PM PDT 24
Finished Jul 10 06:04:16 PM PDT 24
Peak memory 196696 kb
Host smart-932b37ab-5372-4e5c-9a03-6aeb96ab3485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269662107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.269662107
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3485066760
Short name T170
Test name
Test status
Simulation time 406058655 ps
CPU time 0.67 seconds
Started Jul 10 06:04:25 PM PDT 24
Finished Jul 10 06:04:29 PM PDT 24
Peak memory 196744 kb
Host smart-2fe0228d-ba23-42d7-a8f5-6fada95ea7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485066760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3485066760
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.261607156
Short name T151
Test name
Test status
Simulation time 448619802 ps
CPU time 0.96 seconds
Started Jul 10 06:03:34 PM PDT 24
Finished Jul 10 06:03:37 PM PDT 24
Peak memory 196692 kb
Host smart-88920c93-db04-4aa4-a595-4eb8dcc63484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261607156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.261607156
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.648203625
Short name T52
Test name
Test status
Simulation time 705580672 ps
CPU time 0.91 seconds
Started Jul 10 06:07:54 PM PDT 24
Finished Jul 10 06:07:56 PM PDT 24
Peak memory 194288 kb
Host smart-c2c87452-97fe-4310-b4a1-11ae7e8279c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648203625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.648203625
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1122463188
Short name T58
Test name
Test status
Simulation time 6221730910 ps
CPU time 14.13 seconds
Started Jul 10 06:08:04 PM PDT 24
Finished Jul 10 06:08:20 PM PDT 24
Peak memory 192264 kb
Host smart-60d5772c-6ffd-4415-a8f1-0f0a122f6e7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122463188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1122463188
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.505028228
Short name T289
Test name
Test status
Simulation time 884341118 ps
CPU time 0.66 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:02 PM PDT 24
Peak memory 183828 kb
Host smart-a45bcf88-b2c0-4496-ad6c-5a808f8b01a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505028228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.505028228
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2469672145
Short name T423
Test name
Test status
Simulation time 597462611 ps
CPU time 0.98 seconds
Started Jul 10 06:07:56 PM PDT 24
Finished Jul 10 06:07:58 PM PDT 24
Peak memory 197548 kb
Host smart-d8e9bdd3-1cce-4bca-a587-7323e50cd99f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469672145 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2469672145
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2608611572
Short name T369
Test name
Test status
Simulation time 527594411 ps
CPU time 1.15 seconds
Started Jul 10 06:07:56 PM PDT 24
Finished Jul 10 06:07:58 PM PDT 24
Peak memory 192104 kb
Host smart-62adc1d1-fab4-41ee-b91a-2cfe2a11fd0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608611572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2608611572
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2530157120
Short name T357
Test name
Test status
Simulation time 318623936 ps
CPU time 0.95 seconds
Started Jul 10 06:07:55 PM PDT 24
Finished Jul 10 06:07:57 PM PDT 24
Peak memory 183764 kb
Host smart-13354d8d-2eea-4f19-b6dc-a8635b802302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530157120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2530157120
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.363844780
Short name T375
Test name
Test status
Simulation time 439523927 ps
CPU time 0.62 seconds
Started Jul 10 06:07:53 PM PDT 24
Finished Jul 10 06:07:55 PM PDT 24
Peak memory 183720 kb
Host smart-3c652c01-42ca-42b7-9063-b026eb04e247
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363844780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.363844780
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3101380240
Short name T373
Test name
Test status
Simulation time 319402573 ps
CPU time 0.96 seconds
Started Jul 10 06:07:53 PM PDT 24
Finished Jul 10 06:07:55 PM PDT 24
Peak memory 183740 kb
Host smart-7733ef37-3fff-404c-b883-75ff325f7837
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101380240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3101380240
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1294150163
Short name T317
Test name
Test status
Simulation time 523527183 ps
CPU time 1.33 seconds
Started Jul 10 06:07:55 PM PDT 24
Finished Jul 10 06:07:58 PM PDT 24
Peak memory 198500 kb
Host smart-18ca36ae-5b4b-4850-8965-ae80d2975c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294150163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1294150163
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1720464601
Short name T327
Test name
Test status
Simulation time 4419000195 ps
CPU time 7.47 seconds
Started Jul 10 06:07:54 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 198016 kb
Host smart-155dd0a0-12e1-4c3f-b103-803cfc4c0ca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720464601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1720464601
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3694013085
Short name T50
Test name
Test status
Simulation time 472878458 ps
CPU time 1.56 seconds
Started Jul 10 06:07:57 PM PDT 24
Finished Jul 10 06:07:59 PM PDT 24
Peak memory 183812 kb
Host smart-68ae84bb-80d0-4b39-85f0-821fbc2ace4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694013085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3694013085
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2549823713
Short name T339
Test name
Test status
Simulation time 6948740310 ps
CPU time 3.48 seconds
Started Jul 10 06:07:53 PM PDT 24
Finished Jul 10 06:07:58 PM PDT 24
Peak memory 192268 kb
Host smart-fb79686a-f5c2-44a0-88d3-35856cf81524
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549823713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2549823713
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1804660925
Short name T406
Test name
Test status
Simulation time 1179361135 ps
CPU time 0.79 seconds
Started Jul 10 06:07:58 PM PDT 24
Finished Jul 10 06:07:59 PM PDT 24
Peak memory 183704 kb
Host smart-91dc921b-84b9-4503-ac7a-cd93a10081c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804660925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1804660925
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3954672539
Short name T380
Test name
Test status
Simulation time 561409474 ps
CPU time 1.52 seconds
Started Jul 10 06:07:55 PM PDT 24
Finished Jul 10 06:07:58 PM PDT 24
Peak memory 196280 kb
Host smart-7ebf053e-191a-470e-a13f-f0db474b26e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954672539 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3954672539
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2769278739
Short name T383
Test name
Test status
Simulation time 418752738 ps
CPU time 0.84 seconds
Started Jul 10 06:07:55 PM PDT 24
Finished Jul 10 06:07:57 PM PDT 24
Peak memory 193060 kb
Host smart-6abb543b-8ea6-4566-a13c-73dd23f17508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769278739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2769278739
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.81559199
Short name T371
Test name
Test status
Simulation time 514193718 ps
CPU time 1.29 seconds
Started Jul 10 06:07:54 PM PDT 24
Finished Jul 10 06:07:57 PM PDT 24
Peak memory 192996 kb
Host smart-f2c07557-ebd1-487f-8e16-523fe62dc2aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81559199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.81559199
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2669099438
Short name T419
Test name
Test status
Simulation time 306104823 ps
CPU time 0.75 seconds
Started Jul 10 06:07:54 PM PDT 24
Finished Jul 10 06:07:57 PM PDT 24
Peak memory 183688 kb
Host smart-34828509-0187-4127-81ab-71299438e27d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669099438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2669099438
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2024662098
Short name T347
Test name
Test status
Simulation time 484207777 ps
CPU time 1.18 seconds
Started Jul 10 06:07:53 PM PDT 24
Finished Jul 10 06:07:56 PM PDT 24
Peak memory 183744 kb
Host smart-8cd9526f-e616-4988-b3f1-60908f99a887
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024662098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2024662098
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.767400271
Short name T346
Test name
Test status
Simulation time 1693077959 ps
CPU time 3.65 seconds
Started Jul 10 06:07:55 PM PDT 24
Finished Jul 10 06:08:01 PM PDT 24
Peak memory 183824 kb
Host smart-ca9d6c9d-f56f-4467-80bd-9b192eee7882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767400271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.767400271
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1353226109
Short name T396
Test name
Test status
Simulation time 352532315 ps
CPU time 1.8 seconds
Started Jul 10 06:07:57 PM PDT 24
Finished Jul 10 06:08:00 PM PDT 24
Peak memory 198648 kb
Host smart-3f04bbf2-cb8c-4f70-b2da-f502f442719c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353226109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1353226109
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2237135293
Short name T338
Test name
Test status
Simulation time 4314036001 ps
CPU time 2.55 seconds
Started Jul 10 06:07:53 PM PDT 24
Finished Jul 10 06:07:57 PM PDT 24
Peak memory 196736 kb
Host smart-406cb8cf-8b81-4017-849b-ccb9ce7b1b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237135293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2237135293
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.884334148
Short name T395
Test name
Test status
Simulation time 382665329 ps
CPU time 1.25 seconds
Started Jul 10 06:08:15 PM PDT 24
Finished Jul 10 06:08:17 PM PDT 24
Peak memory 196892 kb
Host smart-802bc371-022e-42b7-8f80-c6ea7836b4e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884334148 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.884334148
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2531305022
Short name T417
Test name
Test status
Simulation time 539891407 ps
CPU time 0.68 seconds
Started Jul 10 06:08:15 PM PDT 24
Finished Jul 10 06:08:17 PM PDT 24
Peak memory 192100 kb
Host smart-bdb45bad-732b-4373-90f7-2a1f73cc3c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531305022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2531305022
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.438812651
Short name T391
Test name
Test status
Simulation time 337259160 ps
CPU time 0.68 seconds
Started Jul 10 06:08:10 PM PDT 24
Finished Jul 10 06:08:13 PM PDT 24
Peak memory 192968 kb
Host smart-89ce069b-2c11-4c73-8215-dc1173ef3844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438812651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.438812651
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3830506645
Short name T337
Test name
Test status
Simulation time 2270336965 ps
CPU time 3.92 seconds
Started Jul 10 06:08:12 PM PDT 24
Finished Jul 10 06:08:18 PM PDT 24
Peak memory 194620 kb
Host smart-aa20e3ba-575b-48b2-b92c-18b5bf636d26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830506645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3830506645
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2035516612
Short name T374
Test name
Test status
Simulation time 541006103 ps
CPU time 2.24 seconds
Started Jul 10 06:08:05 PM PDT 24
Finished Jul 10 06:08:08 PM PDT 24
Peak memory 198664 kb
Host smart-6c1890dd-8a90-445c-b125-3553f06701c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035516612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2035516612
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.203165387
Short name T365
Test name
Test status
Simulation time 7925231059 ps
CPU time 10.84 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:24 PM PDT 24
Peak memory 198268 kb
Host smart-78a63d5a-a931-4c2f-8ef4-3147b2c609d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203165387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.203165387
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3576442349
Short name T331
Test name
Test status
Simulation time 547421952 ps
CPU time 1.17 seconds
Started Jul 10 06:08:12 PM PDT 24
Finished Jul 10 06:08:15 PM PDT 24
Peak memory 198456 kb
Host smart-12d0b762-fc82-444c-82d8-f98130c8bc82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576442349 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3576442349
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4186269506
Short name T410
Test name
Test status
Simulation time 481544182 ps
CPU time 1.31 seconds
Started Jul 10 06:08:12 PM PDT 24
Finished Jul 10 06:08:15 PM PDT 24
Peak memory 193112 kb
Host smart-a254f25e-6446-4f97-83b6-3bda4023d146
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186269506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4186269506
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1453638665
Short name T349
Test name
Test status
Simulation time 426157397 ps
CPU time 1.1 seconds
Started Jul 10 06:08:12 PM PDT 24
Finished Jul 10 06:08:15 PM PDT 24
Peak memory 193160 kb
Host smart-97b78fa3-6866-4bf7-a7e6-a2487c61cef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453638665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1453638665
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3689940078
Short name T390
Test name
Test status
Simulation time 1752779761 ps
CPU time 2.86 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:15 PM PDT 24
Peak memory 184016 kb
Host smart-0f07a463-65f5-4070-98af-a4cf8a2cbb62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689940078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3689940078
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1553152316
Short name T328
Test name
Test status
Simulation time 298121144 ps
CPU time 2.04 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:15 PM PDT 24
Peak memory 198664 kb
Host smart-849118a0-f70d-4659-9af7-1997c8a48f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553152316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1553152316
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1702701235
Short name T183
Test name
Test status
Simulation time 4263963465 ps
CPU time 6.21 seconds
Started Jul 10 06:08:13 PM PDT 24
Finished Jul 10 06:08:21 PM PDT 24
Peak memory 196744 kb
Host smart-f470ce1e-fd7e-4945-8628-f292d6469aff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702701235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1702701235
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1928965825
Short name T188
Test name
Test status
Simulation time 352561723 ps
CPU time 1.08 seconds
Started Jul 10 06:08:10 PM PDT 24
Finished Jul 10 06:08:12 PM PDT 24
Peak memory 196028 kb
Host smart-6a06bf41-5463-4131-a4e6-030b78075188
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928965825 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1928965825
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1539916557
Short name T385
Test name
Test status
Simulation time 557742642 ps
CPU time 0.86 seconds
Started Jul 10 06:08:13 PM PDT 24
Finished Jul 10 06:08:16 PM PDT 24
Peak memory 193268 kb
Host smart-2c14d28c-b9f2-4fe2-91c6-c5b03a5ec49e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539916557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1539916557
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2354372566
Short name T350
Test name
Test status
Simulation time 451524333 ps
CPU time 0.89 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:14 PM PDT 24
Peak memory 192988 kb
Host smart-32bdffa7-944f-4f40-b8d4-0b8c532d25e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354372566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2354372566
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.74287194
Short name T319
Test name
Test status
Simulation time 1099697264 ps
CPU time 1.95 seconds
Started Jul 10 06:08:16 PM PDT 24
Finished Jul 10 06:08:19 PM PDT 24
Peak memory 193044 kb
Host smart-c4417261-f0a7-46d0-bc6f-22a8ec417c70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74287194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_
timer_same_csr_outstanding.74287194
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2284806002
Short name T394
Test name
Test status
Simulation time 614158164 ps
CPU time 2.47 seconds
Started Jul 10 06:08:12 PM PDT 24
Finished Jul 10 06:08:17 PM PDT 24
Peak memory 198676 kb
Host smart-31034816-94bb-4568-8bfe-019d0775fade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284806002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2284806002
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2718655825
Short name T290
Test name
Test status
Simulation time 621237578 ps
CPU time 1.19 seconds
Started Jul 10 06:08:10 PM PDT 24
Finished Jul 10 06:08:13 PM PDT 24
Peak memory 196356 kb
Host smart-eaa359cb-8eea-46a1-8301-cdeb5ba8be3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718655825 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2718655825
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3413810335
Short name T300
Test name
Test status
Simulation time 299075573 ps
CPU time 0.65 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:14 PM PDT 24
Peak memory 183744 kb
Host smart-c1cba153-69f6-4ca3-81c6-5ff1500675b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413810335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3413810335
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3470855166
Short name T61
Test name
Test status
Simulation time 1800358408 ps
CPU time 4.42 seconds
Started Jul 10 06:08:10 PM PDT 24
Finished Jul 10 06:08:16 PM PDT 24
Peak memory 193908 kb
Host smart-4a4e2660-2270-43d6-87e0-ae30cb959598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470855166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3470855166
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.725765257
Short name T303
Test name
Test status
Simulation time 742287215 ps
CPU time 2.27 seconds
Started Jul 10 06:08:13 PM PDT 24
Finished Jul 10 06:08:17 PM PDT 24
Peak memory 198656 kb
Host smart-42d007b9-efa3-45e1-bda1-ce5a2cbf6556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725765257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.725765257
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.753252645
Short name T23
Test name
Test status
Simulation time 7766048077 ps
CPU time 7.03 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:20 PM PDT 24
Peak memory 198364 kb
Host smart-6ccd592b-d3d3-49e1-b2c7-646590ae755a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753252645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.753252645
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.806250878
Short name T22
Test name
Test status
Simulation time 682212400 ps
CPU time 0.9 seconds
Started Jul 10 06:08:19 PM PDT 24
Finished Jul 10 06:08:21 PM PDT 24
Peak memory 197768 kb
Host smart-5899a5b0-2f55-4182-99c3-dc1ba68f255e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806250878 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.806250878
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1695568485
Short name T48
Test name
Test status
Simulation time 496923578 ps
CPU time 0.7 seconds
Started Jul 10 06:08:16 PM PDT 24
Finished Jul 10 06:08:17 PM PDT 24
Peak memory 192100 kb
Host smart-68e414ca-c867-42dc-a350-50f0c4e25acd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695568485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1695568485
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3109288360
Short name T315
Test name
Test status
Simulation time 381201805 ps
CPU time 0.63 seconds
Started Jul 10 06:08:10 PM PDT 24
Finished Jul 10 06:08:13 PM PDT 24
Peak memory 183648 kb
Host smart-be05353e-2e9c-47ba-b12f-aae39e08aa0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109288360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3109288360
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.300773736
Short name T60
Test name
Test status
Simulation time 2526795368 ps
CPU time 4.15 seconds
Started Jul 10 06:08:15 PM PDT 24
Finished Jul 10 06:08:21 PM PDT 24
Peak memory 195180 kb
Host smart-60c25d77-083e-4b21-bd23-762cb33278d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300773736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.300773736
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.938822229
Short name T415
Test name
Test status
Simulation time 600674183 ps
CPU time 1.59 seconds
Started Jul 10 06:08:12 PM PDT 24
Finished Jul 10 06:08:15 PM PDT 24
Peak memory 198644 kb
Host smart-dd85b97d-8097-4f3c-ba25-d70b9920c021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938822229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.938822229
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2531115958
Short name T421
Test name
Test status
Simulation time 4148548637 ps
CPU time 3.75 seconds
Started Jul 10 06:08:13 PM PDT 24
Finished Jul 10 06:08:18 PM PDT 24
Peak memory 196864 kb
Host smart-b7b6d458-856e-49bd-b902-250f4ca64735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531115958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2531115958
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.190369644
Short name T306
Test name
Test status
Simulation time 762926226 ps
CPU time 0.76 seconds
Started Jul 10 06:08:17 PM PDT 24
Finished Jul 10 06:08:19 PM PDT 24
Peak memory 196832 kb
Host smart-15e7ef6b-217f-4c58-b0dd-528585495916
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190369644 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.190369644
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2221231944
Short name T377
Test name
Test status
Simulation time 395509350 ps
CPU time 0.72 seconds
Started Jul 10 06:08:19 PM PDT 24
Finished Jul 10 06:08:21 PM PDT 24
Peak memory 194052 kb
Host smart-1beb0bbc-171e-4b5b-b287-b99a8874dd32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221231944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2221231944
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3768171057
Short name T312
Test name
Test status
Simulation time 472798892 ps
CPU time 0.67 seconds
Started Jul 10 06:08:17 PM PDT 24
Finished Jul 10 06:08:19 PM PDT 24
Peak memory 183764 kb
Host smart-34838416-df0c-4c30-b8da-f5d18dd1517a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768171057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3768171057
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2508194520
Short name T334
Test name
Test status
Simulation time 1415105042 ps
CPU time 4.26 seconds
Started Jul 10 06:08:19 PM PDT 24
Finished Jul 10 06:08:24 PM PDT 24
Peak memory 194300 kb
Host smart-00389786-14ca-435d-9011-1aca96289f75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508194520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2508194520
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2629219159
Short name T367
Test name
Test status
Simulation time 867307576 ps
CPU time 2.22 seconds
Started Jul 10 06:08:20 PM PDT 24
Finished Jul 10 06:08:23 PM PDT 24
Peak memory 198832 kb
Host smart-989450fa-2258-4f8b-84dd-c45d18d3b4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629219159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2629219159
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3015740553
Short name T403
Test name
Test status
Simulation time 3981348281 ps
CPU time 6.87 seconds
Started Jul 10 06:08:17 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 196792 kb
Host smart-9ff93e2d-d298-4e73-b7a2-282294796943
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015740553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3015740553
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3739639063
Short name T344
Test name
Test status
Simulation time 473019467 ps
CPU time 1.01 seconds
Started Jul 10 06:08:17 PM PDT 24
Finished Jul 10 06:08:20 PM PDT 24
Peak memory 196316 kb
Host smart-0937c76f-c7e9-44cb-bda1-919f30f3e7d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739639063 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3739639063
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1786480756
Short name T343
Test name
Test status
Simulation time 455201607 ps
CPU time 1.31 seconds
Started Jul 10 06:08:14 PM PDT 24
Finished Jul 10 06:08:17 PM PDT 24
Peak memory 193012 kb
Host smart-8d221036-6ff7-4e76-a036-a9da9554c811
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786480756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1786480756
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.679951202
Short name T405
Test name
Test status
Simulation time 410093391 ps
CPU time 0.7 seconds
Started Jul 10 06:08:16 PM PDT 24
Finished Jul 10 06:08:19 PM PDT 24
Peak memory 183764 kb
Host smart-995f9884-6329-4dd0-8fcc-c1c5156a3213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679951202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.679951202
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1682758318
Short name T361
Test name
Test status
Simulation time 1252223467 ps
CPU time 3.78 seconds
Started Jul 10 06:08:17 PM PDT 24
Finished Jul 10 06:08:22 PM PDT 24
Peak memory 194060 kb
Host smart-9ee773c4-b1cf-465f-9d16-3a412ef991d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682758318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1682758318
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.369032784
Short name T382
Test name
Test status
Simulation time 820353209 ps
CPU time 2.43 seconds
Started Jul 10 06:08:25 PM PDT 24
Finished Jul 10 06:08:29 PM PDT 24
Peak memory 198632 kb
Host smart-2bb6b543-cca6-4643-afa7-582dde88fd7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369032784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.369032784
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1169576120
Short name T322
Test name
Test status
Simulation time 7515102969 ps
CPU time 11.38 seconds
Started Jul 10 06:08:22 PM PDT 24
Finished Jul 10 06:08:34 PM PDT 24
Peak memory 198224 kb
Host smart-a9ef2565-0288-4a6d-93f7-1025a2bb3634
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169576120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1169576120
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1698184868
Short name T348
Test name
Test status
Simulation time 592791096 ps
CPU time 0.99 seconds
Started Jul 10 06:08:20 PM PDT 24
Finished Jul 10 06:08:22 PM PDT 24
Peak memory 196232 kb
Host smart-ab17d5fd-7180-4037-9b4c-f44f271c12fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698184868 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1698184868
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2712701416
Short name T57
Test name
Test status
Simulation time 536303898 ps
CPU time 1.09 seconds
Started Jul 10 06:08:20 PM PDT 24
Finished Jul 10 06:08:22 PM PDT 24
Peak memory 193036 kb
Host smart-9df1a81b-88ad-437d-a343-bd3262e16e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712701416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2712701416
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2578028971
Short name T368
Test name
Test status
Simulation time 428374330 ps
CPU time 0.76 seconds
Started Jul 10 06:08:25 PM PDT 24
Finished Jul 10 06:08:27 PM PDT 24
Peak memory 183752 kb
Host smart-efbdb93f-46d4-48dc-a8e2-224b9a1513ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578028971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2578028971
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3473879708
Short name T26
Test name
Test status
Simulation time 1109325119 ps
CPU time 1.33 seconds
Started Jul 10 06:08:17 PM PDT 24
Finished Jul 10 06:08:19 PM PDT 24
Peak memory 193072 kb
Host smart-27296eb2-01e6-4d6f-83a2-cfb25486c9a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473879708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3473879708
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1587050040
Short name T287
Test name
Test status
Simulation time 540742476 ps
CPU time 1.77 seconds
Started Jul 10 06:08:17 PM PDT 24
Finished Jul 10 06:08:20 PM PDT 24
Peak memory 198648 kb
Host smart-6aa78aac-f8fd-4886-bdd7-69bbf6ce7944
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587050040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1587050040
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1433952173
Short name T366
Test name
Test status
Simulation time 8520696540 ps
CPU time 6.88 seconds
Started Jul 10 06:08:19 PM PDT 24
Finished Jul 10 06:08:27 PM PDT 24
Peak memory 198128 kb
Host smart-4d297173-1bfe-4e2d-9f2f-d57f9b57b93d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433952173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1433952173
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2994915417
Short name T307
Test name
Test status
Simulation time 488668507 ps
CPU time 0.98 seconds
Started Jul 10 06:08:16 PM PDT 24
Finished Jul 10 06:08:18 PM PDT 24
Peak memory 195276 kb
Host smart-405a6fd0-5084-4846-94b2-6e27fdc83f74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994915417 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2994915417
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3772685607
Short name T56
Test name
Test status
Simulation time 475304857 ps
CPU time 1.19 seconds
Started Jul 10 06:08:20 PM PDT 24
Finished Jul 10 06:08:22 PM PDT 24
Peak memory 193312 kb
Host smart-35363d98-158c-48ee-a4b8-9ba42fca8da4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772685607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3772685607
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2466926258
Short name T298
Test name
Test status
Simulation time 271573810 ps
CPU time 0.94 seconds
Started Jul 10 06:08:17 PM PDT 24
Finished Jul 10 06:08:19 PM PDT 24
Peak memory 183728 kb
Host smart-8523b98d-c25a-4113-9040-9d35ee420249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466926258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2466926258
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1193090196
Short name T323
Test name
Test status
Simulation time 1705248320 ps
CPU time 0.82 seconds
Started Jul 10 06:08:19 PM PDT 24
Finished Jul 10 06:08:20 PM PDT 24
Peak memory 193880 kb
Host smart-d7421880-9c02-4cb0-97c4-3d67f5a166b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193090196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1193090196
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.242276032
Short name T411
Test name
Test status
Simulation time 540934638 ps
CPU time 1.52 seconds
Started Jul 10 06:08:21 PM PDT 24
Finished Jul 10 06:08:23 PM PDT 24
Peak memory 198656 kb
Host smart-b7fac580-1c1e-4300-877d-243a1d244e32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242276032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.242276032
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3206609
Short name T364
Test name
Test status
Simulation time 8120234634 ps
CPU time 6.92 seconds
Started Jul 10 06:08:16 PM PDT 24
Finished Jul 10 06:08:25 PM PDT 24
Peak memory 198304 kb
Host smart-7f3a8ec2-d0df-4f71-8d30-4a18766b3e13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_i
ntg_err.3206609
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3455212536
Short name T379
Test name
Test status
Simulation time 331544621 ps
CPU time 1.16 seconds
Started Jul 10 06:08:29 PM PDT 24
Finished Jul 10 06:08:31 PM PDT 24
Peak memory 195664 kb
Host smart-859d654b-bef3-4807-8462-79c32953b744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455212536 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3455212536
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2256808020
Short name T376
Test name
Test status
Simulation time 522674360 ps
CPU time 1 seconds
Started Jul 10 06:08:18 PM PDT 24
Finished Jul 10 06:08:20 PM PDT 24
Peak memory 191976 kb
Host smart-fe4df55a-c9c4-4977-9f2e-3fba88eb1a25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256808020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2256808020
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.315025900
Short name T392
Test name
Test status
Simulation time 362255324 ps
CPU time 0.69 seconds
Started Jul 10 06:08:16 PM PDT 24
Finished Jul 10 06:08:18 PM PDT 24
Peak memory 183796 kb
Host smart-7508bb4c-da33-4274-ad5b-4ae2f89a2293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315025900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.315025900
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3886541331
Short name T62
Test name
Test status
Simulation time 1092364925 ps
CPU time 1.22 seconds
Started Jul 10 06:08:28 PM PDT 24
Finished Jul 10 06:08:30 PM PDT 24
Peak memory 193036 kb
Host smart-8cce513e-be91-41bf-ace1-df6605b5538b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886541331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3886541331
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2826440612
Short name T397
Test name
Test status
Simulation time 455200418 ps
CPU time 1.77 seconds
Started Jul 10 06:08:15 PM PDT 24
Finished Jul 10 06:08:18 PM PDT 24
Peak memory 198672 kb
Host smart-14aaf79f-c535-4fef-835b-3b596e8ff615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826440612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2826440612
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2904331599
Short name T362
Test name
Test status
Simulation time 8718228483 ps
CPU time 4.01 seconds
Started Jul 10 06:08:21 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 198320 kb
Host smart-57f94827-1ae4-49b6-b0ce-d553b2e35181
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904331599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2904331599
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.647452973
Short name T372
Test name
Test status
Simulation time 421912602 ps
CPU time 0.83 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:02 PM PDT 24
Peak memory 183824 kb
Host smart-4461ff36-02bf-4f4d-b2e7-dfc72406af03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647452973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.647452973
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.803792622
Short name T55
Test name
Test status
Simulation time 13000811099 ps
CPU time 18.72 seconds
Started Jul 10 06:08:01 PM PDT 24
Finished Jul 10 06:08:22 PM PDT 24
Peak memory 192240 kb
Host smart-13eb3844-1cc3-42b3-bf36-a38fb77afcbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803792622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.803792622
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2204271776
Short name T414
Test name
Test status
Simulation time 1018161543 ps
CPU time 0.97 seconds
Started Jul 10 06:08:00 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 193096 kb
Host smart-61c7cf30-e61c-41e2-bd23-9c680cbfb77f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204271776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2204271776
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3974207458
Short name T336
Test name
Test status
Simulation time 689822215 ps
CPU time 0.81 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:09 PM PDT 24
Peak memory 196744 kb
Host smart-c589bcb1-1bf1-4852-bd1b-2a57359c7ef4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974207458 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3974207458
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3430901616
Short name T64
Test name
Test status
Simulation time 459046253 ps
CPU time 0.79 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:08 PM PDT 24
Peak memory 193200 kb
Host smart-baa94c65-5595-4b15-9be2-0766c70cf6b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430901616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3430901616
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.943768565
Short name T386
Test name
Test status
Simulation time 417108375 ps
CPU time 0.7 seconds
Started Jul 10 06:07:56 PM PDT 24
Finished Jul 10 06:07:58 PM PDT 24
Peak memory 183764 kb
Host smart-aee25218-3336-4ea5-a82f-b1732b0e8328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943768565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.943768565
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3378752808
Short name T308
Test name
Test status
Simulation time 454486113 ps
CPU time 1.14 seconds
Started Jul 10 06:07:54 PM PDT 24
Finished Jul 10 06:07:57 PM PDT 24
Peak memory 183684 kb
Host smart-03558f68-e5cd-4791-993c-60c8f3ea92a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378752808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3378752808
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3335243058
Short name T304
Test name
Test status
Simulation time 315676626 ps
CPU time 0.69 seconds
Started Jul 10 06:07:54 PM PDT 24
Finished Jul 10 06:07:57 PM PDT 24
Peak memory 183740 kb
Host smart-8db54959-9d3c-4f61-8c1a-757b8b215d35
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335243058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3335243058
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.247568733
Short name T63
Test name
Test status
Simulation time 2113626884 ps
CPU time 1.87 seconds
Started Jul 10 06:08:04 PM PDT 24
Finished Jul 10 06:08:07 PM PDT 24
Peak memory 195060 kb
Host smart-24e05e26-e6d1-4e68-b23c-2a60c6d154ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247568733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.247568733
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.402396934
Short name T399
Test name
Test status
Simulation time 397385314 ps
CPU time 2.11 seconds
Started Jul 10 06:07:54 PM PDT 24
Finished Jul 10 06:07:58 PM PDT 24
Peak memory 198660 kb
Host smart-7f9f0d55-bf8e-4a25-a24e-0c3bf83c93de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402396934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.402396934
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1360921094
Short name T412
Test name
Test status
Simulation time 4487266072 ps
CPU time 1.37 seconds
Started Jul 10 06:07:52 PM PDT 24
Finished Jul 10 06:07:54 PM PDT 24
Peak memory 196656 kb
Host smart-d391dbd5-e9c8-49b6-a814-eab1dbef16a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360921094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1360921094
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1990755061
Short name T282
Test name
Test status
Simulation time 369061949 ps
CPU time 0.69 seconds
Started Jul 10 06:08:27 PM PDT 24
Finished Jul 10 06:08:28 PM PDT 24
Peak memory 183916 kb
Host smart-cf856751-80f8-4a38-ac55-ad015e279141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990755061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1990755061
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2991067877
Short name T363
Test name
Test status
Simulation time 339306510 ps
CPU time 0.6 seconds
Started Jul 10 06:08:26 PM PDT 24
Finished Jul 10 06:08:28 PM PDT 24
Peak memory 183392 kb
Host smart-76c28919-6e2d-4a30-a1eb-6fc58eae04a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991067877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2991067877
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2640897234
Short name T285
Test name
Test status
Simulation time 462148377 ps
CPU time 1.19 seconds
Started Jul 10 06:08:23 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 183744 kb
Host smart-2cdb8206-612d-4e31-a1c7-a29445c4e526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640897234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2640897234
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3149679615
Short name T324
Test name
Test status
Simulation time 513178343 ps
CPU time 0.77 seconds
Started Jul 10 06:08:26 PM PDT 24
Finished Jul 10 06:08:27 PM PDT 24
Peak memory 183760 kb
Host smart-68f92525-1843-430e-84be-98a534637996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149679615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3149679615
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.610981472
Short name T345
Test name
Test status
Simulation time 320804403 ps
CPU time 1.09 seconds
Started Jul 10 06:08:27 PM PDT 24
Finished Jul 10 06:08:29 PM PDT 24
Peak memory 183764 kb
Host smart-6a4abc6a-63f5-4cfb-a299-5bbdaaddea78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610981472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.610981472
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.455365848
Short name T341
Test name
Test status
Simulation time 340775772 ps
CPU time 0.8 seconds
Started Jul 10 06:08:24 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 192968 kb
Host smart-42927bb9-29a2-40af-86ea-15c306275eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455365848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.455365848
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.658168581
Short name T360
Test name
Test status
Simulation time 508602276 ps
CPU time 0.81 seconds
Started Jul 10 06:08:26 PM PDT 24
Finished Jul 10 06:08:27 PM PDT 24
Peak memory 183752 kb
Host smart-589be1aa-e0a7-4737-8dab-5d47eb0d5f45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658168581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.658168581
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.986066468
Short name T340
Test name
Test status
Simulation time 372280725 ps
CPU time 0.81 seconds
Started Jul 10 06:08:23 PM PDT 24
Finished Jul 10 06:08:25 PM PDT 24
Peak memory 192980 kb
Host smart-f4e246fe-90ac-443e-b88d-8b7603d5bc54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986066468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.986066468
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.767446497
Short name T309
Test name
Test status
Simulation time 356491961 ps
CPU time 1.01 seconds
Started Jul 10 06:08:28 PM PDT 24
Finished Jul 10 06:08:29 PM PDT 24
Peak memory 183764 kb
Host smart-e9b874df-5182-4096-9dd4-2d7baabab11e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767446497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.767446497
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1538438236
Short name T325
Test name
Test status
Simulation time 521756525 ps
CPU time 0.8 seconds
Started Jul 10 06:08:28 PM PDT 24
Finished Jul 10 06:08:29 PM PDT 24
Peak memory 183760 kb
Host smart-5cab28e1-37bb-4609-9bdf-001ff38dabd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538438236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1538438236
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2324656326
Short name T321
Test name
Test status
Simulation time 763560644 ps
CPU time 1 seconds
Started Jul 10 06:08:01 PM PDT 24
Finished Jul 10 06:08:05 PM PDT 24
Peak memory 194612 kb
Host smart-c02bb913-f8c5-46c8-b281-1f8fb4028900
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324656326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2324656326
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.277584678
Short name T46
Test name
Test status
Simulation time 4720730109 ps
CPU time 16.95 seconds
Started Jul 10 06:08:01 PM PDT 24
Finished Jul 10 06:08:21 PM PDT 24
Peak memory 196372 kb
Host smart-35be7d4d-9edf-4212-8101-a728a4023ca4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277584678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.277584678
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.640611986
Short name T295
Test name
Test status
Simulation time 1004747748 ps
CPU time 0.84 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:02 PM PDT 24
Peak memory 183800 kb
Host smart-8cf9edee-bd10-4a97-bc53-fd6494af926d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640611986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.640611986
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.69635433
Short name T314
Test name
Test status
Simulation time 386412780 ps
CPU time 1.04 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:09 PM PDT 24
Peak memory 195548 kb
Host smart-dcd21557-4ce6-4843-98b6-c56e7c606323
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69635433 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.69635433
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2943452505
Short name T354
Test name
Test status
Simulation time 489261313 ps
CPU time 1.26 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:01 PM PDT 24
Peak memory 192996 kb
Host smart-668d9302-8c0e-4b30-80e5-7333c007c612
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943452505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2943452505
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.13105638
Short name T288
Test name
Test status
Simulation time 467924456 ps
CPU time 1.28 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:02 PM PDT 24
Peak memory 192964 kb
Host smart-6c9bdd10-06b5-43a6-b8ae-c6e49ede240f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13105638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.13105638
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1305707190
Short name T389
Test name
Test status
Simulation time 451023002 ps
CPU time 0.6 seconds
Started Jul 10 06:08:01 PM PDT 24
Finished Jul 10 06:08:04 PM PDT 24
Peak memory 183684 kb
Host smart-8e0ba6d3-f733-4aa5-83fd-078961664330
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305707190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1305707190
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1515725759
Short name T294
Test name
Test status
Simulation time 322100898 ps
CPU time 0.93 seconds
Started Jul 10 06:08:00 PM PDT 24
Finished Jul 10 06:08:04 PM PDT 24
Peak memory 183752 kb
Host smart-08d34d5a-5f10-44e9-8d3c-4855c39c16e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515725759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1515725759
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.615015608
Short name T359
Test name
Test status
Simulation time 1243330742 ps
CPU time 2.98 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:04 PM PDT 24
Peak memory 193716 kb
Host smart-e405cb4e-ec83-4661-84d2-631c85e596d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615015608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.615015608
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3797686156
Short name T326
Test name
Test status
Simulation time 590784282 ps
CPU time 2.74 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 198680 kb
Host smart-19d5f0bd-391d-4f65-8c4b-62842bfb01e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797686156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3797686156
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.739876716
Short name T408
Test name
Test status
Simulation time 4232405909 ps
CPU time 3.89 seconds
Started Jul 10 06:08:05 PM PDT 24
Finished Jul 10 06:08:10 PM PDT 24
Peak memory 196700 kb
Host smart-69d5e966-5835-41ec-9b15-f264d0391923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739876716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.739876716
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2676428029
Short name T283
Test name
Test status
Simulation time 341199264 ps
CPU time 0.68 seconds
Started Jul 10 06:08:29 PM PDT 24
Finished Jul 10 06:08:30 PM PDT 24
Peak memory 183672 kb
Host smart-f9937a7d-074f-4ab4-b50e-34f15e748cc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676428029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2676428029
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3409996277
Short name T293
Test name
Test status
Simulation time 421706246 ps
CPU time 1.1 seconds
Started Jul 10 06:08:29 PM PDT 24
Finished Jul 10 06:08:31 PM PDT 24
Peak memory 183672 kb
Host smart-ee4d2dee-8937-4ffb-98c1-06ce9d5dc089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409996277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3409996277
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4041618546
Short name T378
Test name
Test status
Simulation time 432780812 ps
CPU time 0.7 seconds
Started Jul 10 06:08:24 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 183764 kb
Host smart-c7ffb809-b4ba-476e-b3eb-8a66f6b10907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041618546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4041618546
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2838528333
Short name T381
Test name
Test status
Simulation time 400098284 ps
CPU time 0.84 seconds
Started Jul 10 06:08:23 PM PDT 24
Finished Jul 10 06:08:25 PM PDT 24
Peak memory 183716 kb
Host smart-ee7bfb01-d4e5-46a4-b134-904fdc585285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838528333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2838528333
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2915191086
Short name T388
Test name
Test status
Simulation time 309492690 ps
CPU time 1.01 seconds
Started Jul 10 06:08:23 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 183940 kb
Host smart-8c0c8c42-b661-4330-97a1-b5859c8bc7f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915191086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2915191086
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.166751709
Short name T296
Test name
Test status
Simulation time 338586200 ps
CPU time 0.67 seconds
Started Jul 10 06:08:24 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 183776 kb
Host smart-17cf1fb5-c09c-4e11-be28-0a541cff0e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166751709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.166751709
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4097939420
Short name T335
Test name
Test status
Simulation time 385042076 ps
CPU time 0.69 seconds
Started Jul 10 06:08:24 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 192992 kb
Host smart-f3e0e7dc-78a4-41d4-85e1-51e6f7db2bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097939420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.4097939420
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2967143023
Short name T284
Test name
Test status
Simulation time 403526457 ps
CPU time 0.67 seconds
Started Jul 10 06:08:23 PM PDT 24
Finished Jul 10 06:08:25 PM PDT 24
Peak memory 183780 kb
Host smart-09059e85-45df-4473-81a7-59927044fb83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967143023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2967143023
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2062037379
Short name T297
Test name
Test status
Simulation time 371146648 ps
CPU time 1.14 seconds
Started Jul 10 06:08:22 PM PDT 24
Finished Jul 10 06:08:24 PM PDT 24
Peak memory 192980 kb
Host smart-9a6bbee7-3c21-456a-913d-aabe2a1e3a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062037379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2062037379
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4119185699
Short name T318
Test name
Test status
Simulation time 457998765 ps
CPU time 0.9 seconds
Started Jul 10 06:08:23 PM PDT 24
Finished Jul 10 06:08:25 PM PDT 24
Peak memory 183792 kb
Host smart-3fe59507-a621-4381-8bb1-514187272ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119185699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4119185699
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.821808017
Short name T313
Test name
Test status
Simulation time 595930952 ps
CPU time 0.72 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:00 PM PDT 24
Peak memory 183812 kb
Host smart-ee04a653-2d52-43dd-9766-0d6b1dc5608e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821808017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.821808017
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3875719441
Short name T54
Test name
Test status
Simulation time 12572772973 ps
CPU time 3.59 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:04 PM PDT 24
Peak memory 196092 kb
Host smart-57485b02-b68d-4cc6-89b9-3f2878b430e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875719441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3875719441
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.4654342
Short name T342
Test name
Test status
Simulation time 837000120 ps
CPU time 0.77 seconds
Started Jul 10 06:08:00 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 193032 kb
Host smart-f43c8ba5-61ed-4fe5-a061-961353652d4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4654342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_r
eset.4654342
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1338622420
Short name T301
Test name
Test status
Simulation time 493000544 ps
CPU time 1.03 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:02 PM PDT 24
Peak memory 195816 kb
Host smart-8416dc4c-b77e-4f38-b08d-0f79fec54854
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338622420 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1338622420
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3147419810
Short name T329
Test name
Test status
Simulation time 499164894 ps
CPU time 1.43 seconds
Started Jul 10 06:08:02 PM PDT 24
Finished Jul 10 06:08:06 PM PDT 24
Peak memory 193460 kb
Host smart-32554aab-0279-4d09-ac38-967d34f371ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147419810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3147419810
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2989337421
Short name T404
Test name
Test status
Simulation time 396956228 ps
CPU time 0.83 seconds
Started Jul 10 06:08:02 PM PDT 24
Finished Jul 10 06:08:05 PM PDT 24
Peak memory 183708 kb
Host smart-89e6691c-40c8-4a5a-b577-177e67ccb93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989337421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2989337421
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.843446390
Short name T416
Test name
Test status
Simulation time 446003191 ps
CPU time 1.19 seconds
Started Jul 10 06:08:00 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 183716 kb
Host smart-2a57c088-addc-4d12-94d6-eed073710a7a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843446390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.843446390
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3385314125
Short name T330
Test name
Test status
Simulation time 445630532 ps
CPU time 0.86 seconds
Started Jul 10 06:08:01 PM PDT 24
Finished Jul 10 06:08:04 PM PDT 24
Peak memory 183724 kb
Host smart-01473b5f-3d04-4fb1-adbf-f142c736422c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385314125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3385314125
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3623673314
Short name T65
Test name
Test status
Simulation time 1969639184 ps
CPU time 2.02 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 194012 kb
Host smart-d19d789e-16b6-476e-a9c3-fe1bd538dea8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623673314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3623673314
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2565896699
Short name T332
Test name
Test status
Simulation time 699439631 ps
CPU time 2.42 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 198648 kb
Host smart-7f7237ef-1d45-4146-8079-5ef05fcddee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565896699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2565896699
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3663781852
Short name T370
Test name
Test status
Simulation time 463469511 ps
CPU time 0.68 seconds
Started Jul 10 06:08:25 PM PDT 24
Finished Jul 10 06:08:27 PM PDT 24
Peak memory 183772 kb
Host smart-0caa9e58-dced-4915-9ab4-c2f1b5b17047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663781852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3663781852
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1560416949
Short name T387
Test name
Test status
Simulation time 450063623 ps
CPU time 0.68 seconds
Started Jul 10 06:08:21 PM PDT 24
Finished Jul 10 06:08:22 PM PDT 24
Peak memory 183776 kb
Host smart-78c4e40e-832b-432c-a32c-a58fee415fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560416949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1560416949
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.883885480
Short name T409
Test name
Test status
Simulation time 441556672 ps
CPU time 0.63 seconds
Started Jul 10 06:08:24 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 183764 kb
Host smart-a48aa320-a1e6-44fd-a39b-69dde4a31242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883885480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.883885480
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1837387290
Short name T305
Test name
Test status
Simulation time 580474256 ps
CPU time 0.62 seconds
Started Jul 10 06:08:24 PM PDT 24
Finished Jul 10 06:08:26 PM PDT 24
Peak memory 192964 kb
Host smart-c9cec976-999e-4d00-a2e9-7b163c1e0879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837387290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1837387290
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1297935313
Short name T351
Test name
Test status
Simulation time 533173799 ps
CPU time 0.62 seconds
Started Jul 10 06:08:26 PM PDT 24
Finished Jul 10 06:08:28 PM PDT 24
Peak memory 183376 kb
Host smart-6391e2cd-b434-4797-97ef-e778a9300cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297935313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1297935313
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.102350855
Short name T400
Test name
Test status
Simulation time 319115799 ps
CPU time 0.97 seconds
Started Jul 10 06:08:23 PM PDT 24
Finished Jul 10 06:08:25 PM PDT 24
Peak memory 183764 kb
Host smart-abf5169b-1c25-42b9-8e10-84836c5daae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102350855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.102350855
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.26830080
Short name T358
Test name
Test status
Simulation time 366776579 ps
CPU time 1.14 seconds
Started Jul 10 06:08:21 PM PDT 24
Finished Jul 10 06:08:23 PM PDT 24
Peak memory 193000 kb
Host smart-c4475ad8-6edc-4078-a2a9-2997b5f2199c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26830080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.26830080
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3906303061
Short name T291
Test name
Test status
Simulation time 377866663 ps
CPU time 0.66 seconds
Started Jul 10 06:08:22 PM PDT 24
Finished Jul 10 06:08:24 PM PDT 24
Peak memory 183760 kb
Host smart-680a0b9c-4aea-4a48-85e8-41ed9bbcc3bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906303061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3906303061
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3271934395
Short name T402
Test name
Test status
Simulation time 302109739 ps
CPU time 0.99 seconds
Started Jul 10 06:08:30 PM PDT 24
Finished Jul 10 06:08:31 PM PDT 24
Peak memory 192980 kb
Host smart-d96ebd51-337c-4683-ad90-cad52575b68c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271934395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3271934395
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4188363613
Short name T413
Test name
Test status
Simulation time 349569815 ps
CPU time 1.01 seconds
Started Jul 10 06:08:29 PM PDT 24
Finished Jul 10 06:08:31 PM PDT 24
Peak memory 192980 kb
Host smart-1e3fcd8c-e800-4b74-b362-8cc70a8175db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188363613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4188363613
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.36534143
Short name T299
Test name
Test status
Simulation time 707528998 ps
CPU time 0.87 seconds
Started Jul 10 06:08:01 PM PDT 24
Finished Jul 10 06:08:05 PM PDT 24
Peak memory 196660 kb
Host smart-862564d4-aeb4-48ad-9976-3fec28d430f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36534143 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.36534143
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2963530580
Short name T353
Test name
Test status
Simulation time 354305968 ps
CPU time 0.67 seconds
Started Jul 10 06:08:02 PM PDT 24
Finished Jul 10 06:08:05 PM PDT 24
Peak memory 192972 kb
Host smart-53eb2710-5108-4b66-b530-09096b19e67d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963530580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2963530580
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2055145308
Short name T333
Test name
Test status
Simulation time 511757405 ps
CPU time 0.81 seconds
Started Jul 10 06:08:00 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 192996 kb
Host smart-6b2e1e9e-2fbb-4b8a-a876-0742b525b635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055145308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2055145308
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.974565740
Short name T352
Test name
Test status
Simulation time 1235238817 ps
CPU time 1.17 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 193336 kb
Host smart-16950380-844f-47c3-8b4f-bfc1f9d65b3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974565740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.974565740
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1254508979
Short name T398
Test name
Test status
Simulation time 526163708 ps
CPU time 1.69 seconds
Started Jul 10 06:07:59 PM PDT 24
Finished Jul 10 06:08:03 PM PDT 24
Peak memory 198652 kb
Host smart-cf9b523c-d53d-48d2-8862-6b0276b4a5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254508979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1254508979
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3241532118
Short name T186
Test name
Test status
Simulation time 8302146854 ps
CPU time 7.64 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:15 PM PDT 24
Peak memory 198508 kb
Host smart-92318b33-2a14-4282-8c7e-ae0a29b6be91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241532118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3241532118
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3757510251
Short name T422
Test name
Test status
Simulation time 432057436 ps
CPU time 1.26 seconds
Started Jul 10 06:08:05 PM PDT 24
Finished Jul 10 06:08:08 PM PDT 24
Peak memory 196436 kb
Host smart-e508eec7-aba4-4e11-ac53-9ec484661e90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757510251 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3757510251
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.186291090
Short name T66
Test name
Test status
Simulation time 616723666 ps
CPU time 0.62 seconds
Started Jul 10 06:08:07 PM PDT 24
Finished Jul 10 06:08:10 PM PDT 24
Peak memory 192088 kb
Host smart-7821eddd-08b8-475f-b318-4f120d857bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186291090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.186291090
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1316025905
Short name T316
Test name
Test status
Simulation time 294278907 ps
CPU time 0.96 seconds
Started Jul 10 06:08:07 PM PDT 24
Finished Jul 10 06:08:10 PM PDT 24
Peak memory 192964 kb
Host smart-b064a75b-2af8-42d9-9772-e5fd4fd084a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316025905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1316025905
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.135820897
Short name T393
Test name
Test status
Simulation time 1695411869 ps
CPU time 1.68 seconds
Started Jul 10 06:08:10 PM PDT 24
Finished Jul 10 06:08:13 PM PDT 24
Peak memory 194048 kb
Host smart-01a0627b-cbdf-4abc-891a-cd3e746c2962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135820897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.135820897
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1778359595
Short name T286
Test name
Test status
Simulation time 341995383 ps
CPU time 1.54 seconds
Started Jul 10 06:08:01 PM PDT 24
Finished Jul 10 06:08:05 PM PDT 24
Peak memory 198500 kb
Host smart-03f66a2a-97e8-4ffa-b18a-834dddf196aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778359595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1778359595
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1318618204
Short name T418
Test name
Test status
Simulation time 8332013320 ps
CPU time 2.98 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:16 PM PDT 24
Peak memory 198320 kb
Host smart-d6163937-c15d-43ec-ab5f-7621a4f81723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318618204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1318618204
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3817644869
Short name T401
Test name
Test status
Simulation time 379999048 ps
CPU time 0.91 seconds
Started Jul 10 06:08:04 PM PDT 24
Finished Jul 10 06:08:06 PM PDT 24
Peak memory 195856 kb
Host smart-a6d0edeb-1e7f-40e9-a5ef-4d60daa6d94a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817644869 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3817644869
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3197066080
Short name T53
Test name
Test status
Simulation time 508468672 ps
CPU time 0.78 seconds
Started Jul 10 06:08:05 PM PDT 24
Finished Jul 10 06:08:07 PM PDT 24
Peak memory 193144 kb
Host smart-f903bfd9-efc4-4ccb-8aa0-f2185e16cb2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197066080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3197066080
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1507581258
Short name T424
Test name
Test status
Simulation time 317302892 ps
CPU time 1.01 seconds
Started Jul 10 06:08:07 PM PDT 24
Finished Jul 10 06:08:10 PM PDT 24
Peak memory 192984 kb
Host smart-0a2ac2f6-47d6-42e2-8551-8de76d7d6f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507581258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1507581258
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1390587809
Short name T356
Test name
Test status
Simulation time 1015371080 ps
CPU time 1.8 seconds
Started Jul 10 06:08:08 PM PDT 24
Finished Jul 10 06:08:11 PM PDT 24
Peak memory 193640 kb
Host smart-75459605-471a-415c-a136-fa3562bee7b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390587809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1390587809
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2460318323
Short name T420
Test name
Test status
Simulation time 592623553 ps
CPU time 1.91 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:10 PM PDT 24
Peak memory 198660 kb
Host smart-13d85d8a-c8e7-4aab-884e-7792efd3e30a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460318323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2460318323
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2919119048
Short name T320
Test name
Test status
Simulation time 4031339366 ps
CPU time 4.6 seconds
Started Jul 10 06:08:07 PM PDT 24
Finished Jul 10 06:08:14 PM PDT 24
Peak memory 197828 kb
Host smart-d456fe90-a499-4b29-8ad8-0318adb29330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919119048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2919119048
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1565039074
Short name T302
Test name
Test status
Simulation time 420758895 ps
CPU time 1.42 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:09 PM PDT 24
Peak memory 196188 kb
Host smart-cd05f2da-67bb-4645-af2a-4a2eaef7db84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565039074 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1565039074
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2041082572
Short name T51
Test name
Test status
Simulation time 589319159 ps
CPU time 0.62 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:13 PM PDT 24
Peak memory 192104 kb
Host smart-9a563c25-248c-4b39-b3a4-ac8dddcfea3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041082572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2041082572
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2408270959
Short name T355
Test name
Test status
Simulation time 344632735 ps
CPU time 0.69 seconds
Started Jul 10 06:08:08 PM PDT 24
Finished Jul 10 06:08:11 PM PDT 24
Peak memory 183656 kb
Host smart-5fc1b84f-b144-4618-8f65-6e10828f9fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408270959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2408270959
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3259096148
Short name T67
Test name
Test status
Simulation time 2150648285 ps
CPU time 4.96 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:13 PM PDT 24
Peak memory 192056 kb
Host smart-5cc58b6a-30fc-47b4-98b4-8fd6cdb695e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259096148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3259096148
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1525692045
Short name T384
Test name
Test status
Simulation time 869583155 ps
CPU time 1.67 seconds
Started Jul 10 06:08:11 PM PDT 24
Finished Jul 10 06:08:15 PM PDT 24
Peak memory 198664 kb
Host smart-74924e44-8dc4-4af4-ac24-ceb27f36287f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525692045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1525692045
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.266996013
Short name T185
Test name
Test status
Simulation time 4263943246 ps
CPU time 3.13 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:11 PM PDT 24
Peak memory 197976 kb
Host smart-9d878f89-3133-48f2-a2a2-47214cd0976d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266996013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.266996013
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.663911590
Short name T310
Test name
Test status
Simulation time 573729158 ps
CPU time 0.87 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:09 PM PDT 24
Peak memory 196080 kb
Host smart-7a6d9ae9-f156-4a3c-947b-def4fdfa273a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663911590 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.663911590
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3594267738
Short name T47
Test name
Test status
Simulation time 427095814 ps
CPU time 0.75 seconds
Started Jul 10 06:08:04 PM PDT 24
Finished Jul 10 06:08:06 PM PDT 24
Peak memory 192084 kb
Host smart-8759843d-9c84-471e-8d0e-c6a7d573cce8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594267738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3594267738
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1269851614
Short name T311
Test name
Test status
Simulation time 468367712 ps
CPU time 0.96 seconds
Started Jul 10 06:08:05 PM PDT 24
Finished Jul 10 06:08:07 PM PDT 24
Peak memory 183764 kb
Host smart-032e6c5a-9b87-4de2-86a9-0bfc2c9e16da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269851614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1269851614
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3129987481
Short name T407
Test name
Test status
Simulation time 2359116830 ps
CPU time 0.96 seconds
Started Jul 10 06:08:06 PM PDT 24
Finished Jul 10 06:08:08 PM PDT 24
Peak memory 193960 kb
Host smart-2a88e5d8-7f34-4b18-b014-109ad84628c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129987481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3129987481
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2591219993
Short name T292
Test name
Test status
Simulation time 520891687 ps
CPU time 1.82 seconds
Started Jul 10 06:08:07 PM PDT 24
Finished Jul 10 06:08:11 PM PDT 24
Peak memory 198680 kb
Host smart-e9962883-4453-4206-aa02-2eb0c4c8179a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591219993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2591219993
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2625076661
Short name T218
Test name
Test status
Simulation time 41724153213 ps
CPU time 15.53 seconds
Started Jul 10 06:03:28 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 196976 kb
Host smart-f010647a-a5de-483f-b628-ed70ed15bc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625076661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2625076661
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.4141389456
Short name T36
Test name
Test status
Simulation time 585176989 ps
CPU time 0.61 seconds
Started Jul 10 06:03:23 PM PDT 24
Finished Jul 10 06:03:24 PM PDT 24
Peak memory 191908 kb
Host smart-8d43194d-2d0f-425d-8198-4787fce73e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141389456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.4141389456
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2959884505
Short name T161
Test name
Test status
Simulation time 355156137 ps
CPU time 1.14 seconds
Started Jul 10 06:03:26 PM PDT 24
Finished Jul 10 06:03:28 PM PDT 24
Peak memory 196708 kb
Host smart-f8acdbb6-586d-41f3-b2e4-f8d3358f9b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959884505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2959884505
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1638382881
Short name T270
Test name
Test status
Simulation time 40488482699 ps
CPU time 16.03 seconds
Started Jul 10 06:03:28 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 196976 kb
Host smart-a385f015-6370-48c7-b7cd-9327e7e0a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638382881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1638382881
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3480072080
Short name T16
Test name
Test status
Simulation time 4062296293 ps
CPU time 6.62 seconds
Started Jul 10 06:03:22 PM PDT 24
Finished Jul 10 06:03:29 PM PDT 24
Peak memory 215412 kb
Host smart-5763735d-8a58-45ff-bb33-5749b9f82f4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480072080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3480072080
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1575380258
Short name T192
Test name
Test status
Simulation time 595968647 ps
CPU time 0.72 seconds
Started Jul 10 06:03:24 PM PDT 24
Finished Jul 10 06:03:26 PM PDT 24
Peak memory 196704 kb
Host smart-d54964ec-06df-4a51-a38e-cfe191899abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575380258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1575380258
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.538158991
Short name T3
Test name
Test status
Simulation time 372291242 ps
CPU time 1.12 seconds
Started Jul 10 06:03:35 PM PDT 24
Finished Jul 10 06:03:38 PM PDT 24
Peak memory 196664 kb
Host smart-c0621c24-456b-4ba9-a82f-71e414e7049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538158991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.538158991
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.776975677
Short name T271
Test name
Test status
Simulation time 23847405659 ps
CPU time 36.6 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:04:15 PM PDT 24
Peak memory 191976 kb
Host smart-c841ce4c-f38f-447f-82e1-22bf0c2c559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776975677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.776975677
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3322885197
Short name T249
Test name
Test status
Simulation time 458162514 ps
CPU time 0.75 seconds
Started Jul 10 06:03:39 PM PDT 24
Finished Jul 10 06:03:42 PM PDT 24
Peak memory 191856 kb
Host smart-00d71612-ec88-471f-83a2-a8beb2ba34d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322885197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3322885197
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4251072185
Short name T279
Test name
Test status
Simulation time 10569667279 ps
CPU time 6.52 seconds
Started Jul 10 06:03:34 PM PDT 24
Finished Jul 10 06:03:42 PM PDT 24
Peak memory 196976 kb
Host smart-d9121540-887f-41a9-8d58-55d28326a5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251072185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4251072185
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3181829740
Short name T235
Test name
Test status
Simulation time 413735060 ps
CPU time 0.75 seconds
Started Jul 10 06:03:34 PM PDT 24
Finished Jul 10 06:03:36 PM PDT 24
Peak memory 191924 kb
Host smart-054537c1-419b-4665-8cfe-c2950c9bc632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181829740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3181829740
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1070694472
Short name T280
Test name
Test status
Simulation time 831679855 ps
CPU time 0.92 seconds
Started Jul 10 06:03:38 PM PDT 24
Finished Jul 10 06:03:42 PM PDT 24
Peak memory 191964 kb
Host smart-7d845d23-2eee-47a7-a92f-cf31dc4f772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070694472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1070694472
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2386523844
Short name T248
Test name
Test status
Simulation time 373122767 ps
CPU time 0.87 seconds
Started Jul 10 06:03:39 PM PDT 24
Finished Jul 10 06:03:43 PM PDT 24
Peak memory 191952 kb
Host smart-f67c0724-9c5a-49ae-82bd-f026ba1f9938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386523844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2386523844
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3353887830
Short name T34
Test name
Test status
Simulation time 25099817144 ps
CPU time 9.44 seconds
Started Jul 10 06:03:35 PM PDT 24
Finished Jul 10 06:03:46 PM PDT 24
Peak memory 196880 kb
Host smart-5423cc0f-879a-4ba7-9384-c3a4b8740c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353887830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3353887830
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.516424595
Short name T195
Test name
Test status
Simulation time 474098430 ps
CPU time 0.63 seconds
Started Jul 10 06:03:40 PM PDT 24
Finished Jul 10 06:03:43 PM PDT 24
Peak memory 196776 kb
Host smart-495aa14f-ef1c-4993-8909-c213bdb9aec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516424595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.516424595
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.960396327
Short name T217
Test name
Test status
Simulation time 53730085982 ps
CPU time 70.64 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:04:49 PM PDT 24
Peak memory 191988 kb
Host smart-5639b7cb-b224-4f8b-babe-650cab169516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960396327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.960396327
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2661456884
Short name T273
Test name
Test status
Simulation time 402254804 ps
CPU time 1.21 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:03:40 PM PDT 24
Peak memory 196724 kb
Host smart-3f2064ea-a2ea-435c-9d5b-4ea2e9f07c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661456884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2661456884
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1690617870
Short name T13
Test name
Test status
Simulation time 38403889640 ps
CPU time 9.04 seconds
Started Jul 10 06:03:33 PM PDT 24
Finished Jul 10 06:03:44 PM PDT 24
Peak memory 191976 kb
Host smart-c941bca2-3aaa-44a0-8069-887967572ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690617870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1690617870
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3206941991
Short name T244
Test name
Test status
Simulation time 447380609 ps
CPU time 0.75 seconds
Started Jul 10 06:03:37 PM PDT 24
Finished Jul 10 06:03:40 PM PDT 24
Peak memory 196712 kb
Host smart-42cfba6e-72fc-4b14-90e5-2b6374fc0bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206941991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3206941991
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1489219135
Short name T243
Test name
Test status
Simulation time 50664372149 ps
CPU time 216.31 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:07:15 PM PDT 24
Peak memory 206916 kb
Host smart-77965269-d6e6-4f54-997e-000ccbe30d97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489219135 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1489219135
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.524159214
Short name T281
Test name
Test status
Simulation time 37659598909 ps
CPU time 14.5 seconds
Started Jul 10 06:03:39 PM PDT 24
Finished Jul 10 06:03:56 PM PDT 24
Peak memory 196908 kb
Host smart-ad2f94e7-2ee0-43bd-b7a3-c5ddcb159a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524159214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.524159214
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3316167151
Short name T233
Test name
Test status
Simulation time 491956682 ps
CPU time 1.26 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:03:40 PM PDT 24
Peak memory 191824 kb
Host smart-9cc9eccc-0642-4a0b-aa3a-ddfe2fbdfdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316167151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3316167151
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1329719478
Short name T264
Test name
Test status
Simulation time 30121180017 ps
CPU time 45.04 seconds
Started Jul 10 06:03:40 PM PDT 24
Finished Jul 10 06:04:28 PM PDT 24
Peak memory 191876 kb
Host smart-39cb6361-58bf-419c-9402-b40509758169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329719478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1329719478
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1750308769
Short name T259
Test name
Test status
Simulation time 392626388 ps
CPU time 0.89 seconds
Started Jul 10 06:03:41 PM PDT 24
Finished Jul 10 06:03:44 PM PDT 24
Peak memory 191916 kb
Host smart-1e954d50-0b78-4ff4-b414-e9ea1e162350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750308769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1750308769
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.940527453
Short name T200
Test name
Test status
Simulation time 44288272137 ps
CPU time 16.86 seconds
Started Jul 10 06:03:47 PM PDT 24
Finished Jul 10 06:04:05 PM PDT 24
Peak memory 196452 kb
Host smart-a19ff8ba-b6af-4926-b9ad-85c1cbfa4089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940527453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.940527453
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.563424927
Short name T272
Test name
Test status
Simulation time 556527225 ps
CPU time 1.01 seconds
Started Jul 10 06:03:40 PM PDT 24
Finished Jul 10 06:03:44 PM PDT 24
Peak memory 191916 kb
Host smart-01efca12-052d-4820-8749-a409a177cccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563424927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.563424927
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1292936407
Short name T181
Test name
Test status
Simulation time 352105351 ps
CPU time 0.84 seconds
Started Jul 10 06:03:41 PM PDT 24
Finished Jul 10 06:03:45 PM PDT 24
Peak memory 196780 kb
Host smart-c38cd61f-7bb8-4a11-8837-a55d07e8b45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292936407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1292936407
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2243768547
Short name T203
Test name
Test status
Simulation time 16915140683 ps
CPU time 13.41 seconds
Started Jul 10 06:03:39 PM PDT 24
Finished Jul 10 06:03:55 PM PDT 24
Peak memory 191888 kb
Host smart-bd533096-0bcf-44b3-bdda-59a978de6543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243768547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2243768547
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.963349713
Short name T231
Test name
Test status
Simulation time 549689488 ps
CPU time 1.31 seconds
Started Jul 10 06:03:40 PM PDT 24
Finished Jul 10 06:03:44 PM PDT 24
Peak memory 191924 kb
Host smart-fc07e5dd-998e-44e8-a7e1-b76d2ae0c145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963349713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.963349713
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.853754943
Short name T212
Test name
Test status
Simulation time 36965763296 ps
CPU time 49.85 seconds
Started Jul 10 06:03:23 PM PDT 24
Finished Jul 10 06:04:14 PM PDT 24
Peak memory 191996 kb
Host smart-c43f3b77-4f9e-42c1-a3b3-21c14b417548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853754943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.853754943
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.945401457
Short name T18
Test name
Test status
Simulation time 4290681130 ps
CPU time 3.82 seconds
Started Jul 10 06:03:30 PM PDT 24
Finished Jul 10 06:03:35 PM PDT 24
Peak memory 215428 kb
Host smart-bfe36125-ffc9-4e49-8931-de1eeb2f1d87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945401457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.945401457
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3971423324
Short name T242
Test name
Test status
Simulation time 480168174 ps
CPU time 0.76 seconds
Started Jul 10 06:03:22 PM PDT 24
Finished Jul 10 06:03:24 PM PDT 24
Peak memory 191908 kb
Host smart-d91deda8-5120-4bbd-b2c9-399cf55db432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971423324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3971423324
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1268948828
Short name T252
Test name
Test status
Simulation time 19782553466 ps
CPU time 7.33 seconds
Started Jul 10 06:03:43 PM PDT 24
Finished Jul 10 06:03:52 PM PDT 24
Peak memory 191972 kb
Host smart-f76859c8-6e3f-4f90-af72-e2270d849084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268948828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1268948828
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3685538514
Short name T198
Test name
Test status
Simulation time 445265499 ps
CPU time 0.7 seconds
Started Jul 10 06:03:47 PM PDT 24
Finished Jul 10 06:03:48 PM PDT 24
Peak memory 196156 kb
Host smart-930973e4-86ad-452f-996b-037821b3e3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685538514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3685538514
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.962667909
Short name T197
Test name
Test status
Simulation time 7231343990 ps
CPU time 6.15 seconds
Started Jul 10 06:03:48 PM PDT 24
Finished Jul 10 06:03:55 PM PDT 24
Peak memory 191984 kb
Host smart-7b5905c3-c376-41e7-8fdf-99ef49fc9209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962667909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.962667909
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1558151546
Short name T225
Test name
Test status
Simulation time 617006892 ps
CPU time 0.99 seconds
Started Jul 10 06:03:47 PM PDT 24
Finished Jul 10 06:03:49 PM PDT 24
Peak memory 191944 kb
Host smart-9b42f0c8-7239-402a-ad82-3c35843b67f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558151546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1558151546
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2807790550
Short name T278
Test name
Test status
Simulation time 18028056622 ps
CPU time 28.19 seconds
Started Jul 10 06:03:46 PM PDT 24
Finished Jul 10 06:04:15 PM PDT 24
Peak memory 191884 kb
Host smart-c7753a6a-62f4-4bba-8f70-d57a11de5918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807790550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2807790550
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1174638694
Short name T226
Test name
Test status
Simulation time 544108195 ps
CPU time 1 seconds
Started Jul 10 06:03:49 PM PDT 24
Finished Jul 10 06:03:50 PM PDT 24
Peak memory 191920 kb
Host smart-b5e507c9-2181-458e-932e-acdbbcf5560b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174638694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1174638694
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4233053283
Short name T205
Test name
Test status
Simulation time 32917064944 ps
CPU time 24.07 seconds
Started Jul 10 06:03:45 PM PDT 24
Finished Jul 10 06:04:10 PM PDT 24
Peak memory 196988 kb
Host smart-dd133f7b-3005-4a45-a840-6c8630599f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233053283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4233053283
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.232334976
Short name T275
Test name
Test status
Simulation time 531565599 ps
CPU time 0.78 seconds
Started Jul 10 06:03:47 PM PDT 24
Finished Jul 10 06:03:49 PM PDT 24
Peak memory 196716 kb
Host smart-04fe3cbe-6869-442b-ad27-c1cfac14fe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232334976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.232334976
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.931820456
Short name T172
Test name
Test status
Simulation time 37262728614 ps
CPU time 152.07 seconds
Started Jul 10 06:03:46 PM PDT 24
Finished Jul 10 06:06:19 PM PDT 24
Peak memory 214336 kb
Host smart-ae74d53b-902a-4198-8978-1f231ed26cb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931820456 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.931820456
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3806116255
Short name T266
Test name
Test status
Simulation time 18220601402 ps
CPU time 27.23 seconds
Started Jul 10 06:03:50 PM PDT 24
Finished Jul 10 06:04:18 PM PDT 24
Peak memory 196968 kb
Host smart-100ff99a-b489-4315-a66b-ad6ba1e571c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806116255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3806116255
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4162867645
Short name T265
Test name
Test status
Simulation time 416159638 ps
CPU time 0.95 seconds
Started Jul 10 06:03:49 PM PDT 24
Finished Jul 10 06:03:50 PM PDT 24
Peak memory 192104 kb
Host smart-724f0718-f213-4d76-9511-72a48bf2c82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162867645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4162867645
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3629430756
Short name T160
Test name
Test status
Simulation time 388776330 ps
CPU time 0.87 seconds
Started Jul 10 06:03:54 PM PDT 24
Finished Jul 10 06:03:55 PM PDT 24
Peak memory 196748 kb
Host smart-4146cc40-3474-4629-869b-e1c6ad8a3621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629430756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3629430756
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4193538442
Short name T229
Test name
Test status
Simulation time 48414827718 ps
CPU time 14.98 seconds
Started Jul 10 06:03:51 PM PDT 24
Finished Jul 10 06:04:07 PM PDT 24
Peak memory 191980 kb
Host smart-b1000b64-375a-407b-8100-e4e673c4d0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193538442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4193538442
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.136280597
Short name T199
Test name
Test status
Simulation time 554462236 ps
CPU time 0.77 seconds
Started Jul 10 06:03:52 PM PDT 24
Finished Jul 10 06:03:54 PM PDT 24
Peak memory 195496 kb
Host smart-c37eb893-b621-4267-bdb9-7b6cc32f477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136280597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.136280597
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1253837397
Short name T6
Test name
Test status
Simulation time 23322466260 ps
CPU time 17.52 seconds
Started Jul 10 06:03:51 PM PDT 24
Finished Jul 10 06:04:09 PM PDT 24
Peak memory 192020 kb
Host smart-cff58c95-14ef-4fb7-986e-15d7639f6ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253837397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1253837397
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.347200472
Short name T232
Test name
Test status
Simulation time 550832742 ps
CPU time 1.39 seconds
Started Jul 10 06:03:53 PM PDT 24
Finished Jul 10 06:03:55 PM PDT 24
Peak memory 191912 kb
Host smart-a8329c90-680b-4800-ad64-a3eeb46dad03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347200472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.347200472
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.4219499288
Short name T209
Test name
Test status
Simulation time 60412593345 ps
CPU time 22.08 seconds
Started Jul 10 06:03:51 PM PDT 24
Finished Jul 10 06:04:14 PM PDT 24
Peak memory 191964 kb
Host smart-0a567ae9-ae53-4470-a4fb-37907e37d9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219499288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.4219499288
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.428249341
Short name T261
Test name
Test status
Simulation time 518947303 ps
CPU time 0.81 seconds
Started Jul 10 06:03:54 PM PDT 24
Finished Jul 10 06:03:56 PM PDT 24
Peak memory 191912 kb
Host smart-547530b1-a72b-473b-8163-db3e5f4673d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428249341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.428249341
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3867596891
Short name T187
Test name
Test status
Simulation time 21853613266 ps
CPU time 30.95 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:04:35 PM PDT 24
Peak memory 196972 kb
Host smart-a8201b24-5dcb-44ec-82bf-b0fb946fba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867596891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3867596891
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3616582781
Short name T223
Test name
Test status
Simulation time 342333248 ps
CPU time 0.81 seconds
Started Jul 10 06:04:01 PM PDT 24
Finished Jul 10 06:04:03 PM PDT 24
Peak memory 191948 kb
Host smart-56775087-640e-4d02-a056-f48ff090eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616582781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3616582781
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1029605783
Short name T210
Test name
Test status
Simulation time 37302906363 ps
CPU time 13.48 seconds
Started Jul 10 06:03:59 PM PDT 24
Finished Jul 10 06:04:14 PM PDT 24
Peak memory 196960 kb
Host smart-b76f6bf0-6dab-4f29-9efa-c9b9d07a3fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029605783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1029605783
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1201531459
Short name T204
Test name
Test status
Simulation time 403742497 ps
CPU time 0.76 seconds
Started Jul 10 06:03:58 PM PDT 24
Finished Jul 10 06:04:00 PM PDT 24
Peak memory 191892 kb
Host smart-dbb1adbf-9101-444b-a173-956474926c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201531459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1201531459
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2670149890
Short name T237
Test name
Test status
Simulation time 20747476251 ps
CPU time 7.84 seconds
Started Jul 10 06:03:33 PM PDT 24
Finished Jul 10 06:03:43 PM PDT 24
Peak memory 192004 kb
Host smart-a1550d72-5b6b-431f-9655-9e1e0b1aa78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670149890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2670149890
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.527795909
Short name T15
Test name
Test status
Simulation time 8465130918 ps
CPU time 2.46 seconds
Started Jul 10 06:03:33 PM PDT 24
Finished Jul 10 06:03:37 PM PDT 24
Peak memory 215804 kb
Host smart-9611a99b-15a8-497f-a781-e8c5dcc8d3dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527795909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.527795909
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3334278967
Short name T239
Test name
Test status
Simulation time 532325323 ps
CPU time 1.35 seconds
Started Jul 10 06:03:31 PM PDT 24
Finished Jul 10 06:03:34 PM PDT 24
Peak memory 191900 kb
Host smart-0ed83eb1-8d8e-4b07-9af6-543c32c19d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334278967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3334278967
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2450901508
Short name T19
Test name
Test status
Simulation time 26147292218 ps
CPU time 39.06 seconds
Started Jul 10 06:03:59 PM PDT 24
Finished Jul 10 06:04:39 PM PDT 24
Peak memory 196984 kb
Host smart-3235a806-d377-42c1-9370-9c102faf65e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450901508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2450901508
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1868094456
Short name T251
Test name
Test status
Simulation time 370198303 ps
CPU time 0.69 seconds
Started Jul 10 06:03:58 PM PDT 24
Finished Jul 10 06:03:59 PM PDT 24
Peak memory 191920 kb
Host smart-6186211b-df78-4836-80df-9942ece4fe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868094456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1868094456
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.996372322
Short name T173
Test name
Test status
Simulation time 628346940 ps
CPU time 0.66 seconds
Started Jul 10 06:04:10 PM PDT 24
Finished Jul 10 06:04:12 PM PDT 24
Peak memory 196864 kb
Host smart-bf5fb536-4dfe-4653-a785-d14c9668dca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996372322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.996372322
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2334689667
Short name T230
Test name
Test status
Simulation time 37400486080 ps
CPU time 28.82 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:04:33 PM PDT 24
Peak memory 191988 kb
Host smart-042e1f4a-09e2-43c5-be24-80859e547e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334689667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2334689667
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3318711073
Short name T207
Test name
Test status
Simulation time 422366671 ps
CPU time 1.15 seconds
Started Jul 10 06:03:58 PM PDT 24
Finished Jul 10 06:04:00 PM PDT 24
Peak memory 196776 kb
Host smart-fe5800cb-632d-4fa1-84af-2e2d92f985bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318711073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3318711073
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2451415164
Short name T180
Test name
Test status
Simulation time 174123820684 ps
CPU time 89.13 seconds
Started Jul 10 06:03:57 PM PDT 24
Finished Jul 10 06:05:27 PM PDT 24
Peak memory 191968 kb
Host smart-4f82ac00-a6e7-4b80-8eea-9bce1f4afbd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451415164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2451415164
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.311815494
Short name T277
Test name
Test status
Simulation time 3124834461 ps
CPU time 4.33 seconds
Started Jul 10 06:04:02 PM PDT 24
Finished Jul 10 06:04:07 PM PDT 24
Peak memory 191988 kb
Host smart-611a7f0a-0e28-477d-ad6e-480b7fa09187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311815494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.311815494
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3668210720
Short name T213
Test name
Test status
Simulation time 385947922 ps
CPU time 0.87 seconds
Started Jul 10 06:04:01 PM PDT 24
Finished Jul 10 06:04:03 PM PDT 24
Peak memory 191920 kb
Host smart-0187502c-5c30-4a56-a7bd-e1f41238ef26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668210720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3668210720
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2483543157
Short name T214
Test name
Test status
Simulation time 28704146090 ps
CPU time 23.3 seconds
Started Jul 10 06:03:58 PM PDT 24
Finished Jul 10 06:04:22 PM PDT 24
Peak memory 191976 kb
Host smart-33f2aeaa-68d2-4140-a859-251cf12369f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483543157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2483543157
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3273428496
Short name T260
Test name
Test status
Simulation time 409655465 ps
CPU time 1.22 seconds
Started Jul 10 06:03:59 PM PDT 24
Finished Jul 10 06:04:01 PM PDT 24
Peak memory 191916 kb
Host smart-b2882cc7-ef90-4207-b5d2-cb42fcd5448d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273428496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3273428496
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4244010340
Short name T257
Test name
Test status
Simulation time 19004447351 ps
CPU time 25.82 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:04:34 PM PDT 24
Peak memory 197000 kb
Host smart-ee689186-26e4-4444-81e0-00a61f87e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244010340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4244010340
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3588003532
Short name T208
Test name
Test status
Simulation time 439218788 ps
CPU time 1.13 seconds
Started Jul 10 06:04:02 PM PDT 24
Finished Jul 10 06:04:05 PM PDT 24
Peak memory 196724 kb
Host smart-d62d9561-ffa4-484f-9a33-37f40398550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588003532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3588003532
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.4274692621
Short name T193
Test name
Test status
Simulation time 45920716073 ps
CPU time 70.4 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:05:19 PM PDT 24
Peak memory 191768 kb
Host smart-81f0e794-f1c8-49b0-bf30-7f3921f85294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274692621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.4274692621
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3811118942
Short name T201
Test name
Test status
Simulation time 373393836 ps
CPU time 1.17 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:04:06 PM PDT 24
Peak memory 196696 kb
Host smart-ae0186ad-92be-417f-b35d-790b3892a1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811118942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3811118942
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3474836969
Short name T177
Test name
Test status
Simulation time 436586521 ps
CPU time 0.9 seconds
Started Jul 10 06:04:04 PM PDT 24
Finished Jul 10 06:04:07 PM PDT 24
Peak memory 196676 kb
Host smart-6f6954ad-5b42-4327-b00e-3651ce00f0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474836969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3474836969
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2638030268
Short name T246
Test name
Test status
Simulation time 53164083101 ps
CPU time 80.33 seconds
Started Jul 10 06:04:02 PM PDT 24
Finished Jul 10 06:05:24 PM PDT 24
Peak memory 191968 kb
Host smart-4ecca499-8d60-47a7-8f9d-dfd229d02bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638030268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2638030268
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.364175413
Short name T234
Test name
Test status
Simulation time 621390824 ps
CPU time 0.97 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:04:06 PM PDT 24
Peak memory 191940 kb
Host smart-349ac5ac-2b27-4a1a-ae02-852beeabc11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364175413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.364175413
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1519205083
Short name T238
Test name
Test status
Simulation time 11182183335 ps
CPU time 14.8 seconds
Started Jul 10 06:04:04 PM PDT 24
Finished Jul 10 06:04:21 PM PDT 24
Peak memory 196984 kb
Host smart-753981ed-c21a-4a65-a70e-0259dabd5cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519205083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1519205083
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1714841193
Short name T250
Test name
Test status
Simulation time 561731617 ps
CPU time 0.77 seconds
Started Jul 10 06:04:04 PM PDT 24
Finished Jul 10 06:04:07 PM PDT 24
Peak memory 191824 kb
Host smart-c4091be5-5e3e-42e4-b7a5-04491c128477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714841193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1714841193
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.775520170
Short name T211
Test name
Test status
Simulation time 40727198107 ps
CPU time 15.93 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:04:25 PM PDT 24
Peak memory 196972 kb
Host smart-03a0e3a0-c287-4eaf-af29-733fa867fb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775520170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.775520170
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1972158569
Short name T268
Test name
Test status
Simulation time 534031322 ps
CPU time 0.8 seconds
Started Jul 10 06:04:03 PM PDT 24
Finished Jul 10 06:04:06 PM PDT 24
Peak memory 191920 kb
Host smart-1d017b48-66c8-4410-b496-07e3820ef580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972158569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1972158569
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.830120399
Short name T245
Test name
Test status
Simulation time 47541990771 ps
CPU time 16.06 seconds
Started Jul 10 06:04:11 PM PDT 24
Finished Jul 10 06:04:28 PM PDT 24
Peak memory 192004 kb
Host smart-0d768e89-b427-45f2-b550-078806c3f76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830120399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.830120399
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.112994470
Short name T190
Test name
Test status
Simulation time 352474231 ps
CPU time 1.13 seconds
Started Jul 10 06:04:08 PM PDT 24
Finished Jul 10 06:04:11 PM PDT 24
Peak memory 196756 kb
Host smart-accea964-690d-4c89-9333-62ed50873a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112994470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.112994470
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.181410937
Short name T269
Test name
Test status
Simulation time 50262075193 ps
CPU time 39.14 seconds
Started Jul 10 06:03:31 PM PDT 24
Finished Jul 10 06:04:12 PM PDT 24
Peak memory 197004 kb
Host smart-42349c93-25cb-4eea-8aca-7d829bc21030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181410937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.181410937
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3931466797
Short name T11
Test name
Test status
Simulation time 3467622711 ps
CPU time 5.81 seconds
Started Jul 10 06:03:33 PM PDT 24
Finished Jul 10 06:03:40 PM PDT 24
Peak memory 215408 kb
Host smart-66b268aa-5fa6-4cdc-b73f-b6cdf22d862f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931466797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3931466797
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1222783558
Short name T276
Test name
Test status
Simulation time 358873379 ps
CPU time 1.2 seconds
Started Jul 10 06:03:30 PM PDT 24
Finished Jul 10 06:03:33 PM PDT 24
Peak memory 191920 kb
Host smart-08071bc2-4003-46eb-8706-938c449dea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222783558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1222783558
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2912122829
Short name T241
Test name
Test status
Simulation time 46753145068 ps
CPU time 35.04 seconds
Started Jul 10 06:04:09 PM PDT 24
Finished Jul 10 06:04:46 PM PDT 24
Peak memory 191884 kb
Host smart-6a9528ff-4dd3-4e86-a45e-c29a354aa27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912122829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2912122829
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1939085589
Short name T189
Test name
Test status
Simulation time 407785593 ps
CPU time 0.73 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:04:09 PM PDT 24
Peak memory 191952 kb
Host smart-886cc5fe-98ad-41df-9731-f54d38158f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939085589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1939085589
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3017961083
Short name T156
Test name
Test status
Simulation time 463388554 ps
CPU time 0.94 seconds
Started Jul 10 06:04:07 PM PDT 24
Finished Jul 10 06:04:10 PM PDT 24
Peak memory 196688 kb
Host smart-73117400-7578-40e5-9986-8cb234c7b7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017961083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3017961083
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2501817251
Short name T220
Test name
Test status
Simulation time 43311492035 ps
CPU time 10.11 seconds
Started Jul 10 06:04:08 PM PDT 24
Finished Jul 10 06:04:20 PM PDT 24
Peak memory 191972 kb
Host smart-252fec8f-7099-4412-b9fb-7d1c9efafdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501817251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2501817251
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2805264064
Short name T253
Test name
Test status
Simulation time 402421923 ps
CPU time 0.86 seconds
Started Jul 10 06:04:13 PM PDT 24
Finished Jul 10 06:04:15 PM PDT 24
Peak memory 191932 kb
Host smart-9991a201-30f5-4e95-8194-becb0f3d0fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805264064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2805264064
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1012725087
Short name T262
Test name
Test status
Simulation time 29962793041 ps
CPU time 5.15 seconds
Started Jul 10 06:04:09 PM PDT 24
Finished Jul 10 06:04:16 PM PDT 24
Peak memory 196892 kb
Host smart-09f8f808-fdb6-47e3-8700-8fb657a33a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012725087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1012725087
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.126916490
Short name T41
Test name
Test status
Simulation time 417597926 ps
CPU time 0.64 seconds
Started Jul 10 06:04:08 PM PDT 24
Finished Jul 10 06:04:11 PM PDT 24
Peak memory 191912 kb
Host smart-674e5c46-b017-4a46-8e00-bf81b4dcb63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126916490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.126916490
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2711785678
Short name T258
Test name
Test status
Simulation time 55324198509 ps
CPU time 80.53 seconds
Started Jul 10 06:04:09 PM PDT 24
Finished Jul 10 06:05:31 PM PDT 24
Peak memory 191976 kb
Host smart-4b98c652-be6c-42a1-8510-fc78bdeb2b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711785678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2711785678
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.892453527
Short name T236
Test name
Test status
Simulation time 541194193 ps
CPU time 0.95 seconds
Started Jul 10 06:04:12 PM PDT 24
Finished Jul 10 06:04:14 PM PDT 24
Peak memory 191928 kb
Host smart-994f812d-3d9e-4947-9655-1b1a792892e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892453527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.892453527
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.636640837
Short name T228
Test name
Test status
Simulation time 30060905524 ps
CPU time 12.08 seconds
Started Jul 10 06:04:17 PM PDT 24
Finished Jul 10 06:04:30 PM PDT 24
Peak memory 192004 kb
Host smart-433ff00f-6286-45db-8e7d-69cae86978be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636640837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.636640837
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1761489854
Short name T224
Test name
Test status
Simulation time 373041261 ps
CPU time 1.08 seconds
Started Jul 10 06:04:24 PM PDT 24
Finished Jul 10 06:04:27 PM PDT 24
Peak memory 191920 kb
Host smart-3795ee11-007d-48d6-bead-da3793a6fc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761489854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1761489854
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3250785878
Short name T191
Test name
Test status
Simulation time 22081025700 ps
CPU time 16.49 seconds
Started Jul 10 06:04:18 PM PDT 24
Finished Jul 10 06:04:35 PM PDT 24
Peak memory 191972 kb
Host smart-a5b6ccca-9146-4ead-8989-49b31809e3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250785878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3250785878
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2735024446
Short name T274
Test name
Test status
Simulation time 401411267 ps
CPU time 0.73 seconds
Started Jul 10 06:04:16 PM PDT 24
Finished Jul 10 06:04:18 PM PDT 24
Peak memory 191836 kb
Host smart-29cc041d-b5da-42c9-b210-ef6f7ce2b0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735024446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2735024446
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2555032716
Short name T247
Test name
Test status
Simulation time 26401264699 ps
CPU time 33.84 seconds
Started Jul 10 06:04:15 PM PDT 24
Finished Jul 10 06:04:51 PM PDT 24
Peak memory 191976 kb
Host smart-55471535-4b58-4ef6-8b92-4caa715b7078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555032716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2555032716
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.608122172
Short name T194
Test name
Test status
Simulation time 427190306 ps
CPU time 0.75 seconds
Started Jul 10 06:04:16 PM PDT 24
Finished Jul 10 06:04:18 PM PDT 24
Peak memory 196764 kb
Host smart-41aed5da-c2bc-42de-8b31-f92f7d900236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608122172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.608122172
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2561755588
Short name T196
Test name
Test status
Simulation time 9190420803 ps
CPU time 3.52 seconds
Started Jul 10 06:04:16 PM PDT 24
Finished Jul 10 06:04:21 PM PDT 24
Peak memory 196892 kb
Host smart-94acbfdf-375e-49d4-9544-93238eb5f67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561755588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2561755588
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3027188220
Short name T222
Test name
Test status
Simulation time 542802157 ps
CPU time 1.32 seconds
Started Jul 10 06:04:13 PM PDT 24
Finished Jul 10 06:04:15 PM PDT 24
Peak memory 191912 kb
Host smart-25c4875b-66e4-478e-9e16-987c60e17443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027188220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3027188220
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.555350217
Short name T216
Test name
Test status
Simulation time 35319958220 ps
CPU time 47.01 seconds
Started Jul 10 06:04:15 PM PDT 24
Finished Jul 10 06:05:03 PM PDT 24
Peak memory 196984 kb
Host smart-ae9ca055-7487-402d-9158-c702c09a8ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555350217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.555350217
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2923438147
Short name T202
Test name
Test status
Simulation time 373658180 ps
CPU time 1.08 seconds
Started Jul 10 06:04:14 PM PDT 24
Finished Jul 10 06:04:17 PM PDT 24
Peak memory 191916 kb
Host smart-c6dbb1e9-006a-4586-b7dc-d9318e29f677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923438147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2923438147
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2588677633
Short name T255
Test name
Test status
Simulation time 31981278165 ps
CPU time 25.24 seconds
Started Jul 10 06:04:13 PM PDT 24
Finished Jul 10 06:04:39 PM PDT 24
Peak memory 191972 kb
Host smart-f52d2f94-f5b9-4544-ba9d-f111cf01c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588677633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2588677633
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1064904185
Short name T206
Test name
Test status
Simulation time 537055904 ps
CPU time 1.35 seconds
Started Jul 10 06:04:17 PM PDT 24
Finished Jul 10 06:04:20 PM PDT 24
Peak memory 191908 kb
Host smart-e10dba0e-cb83-41c8-8f61-03d6f1b2d7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064904185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1064904185
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.93173314
Short name T227
Test name
Test status
Simulation time 51351028418 ps
CPU time 38.85 seconds
Started Jul 10 06:03:29 PM PDT 24
Finished Jul 10 06:04:09 PM PDT 24
Peak memory 191988 kb
Host smart-fbddaa70-1a72-4a1d-97a3-8ff2b226e566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93173314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.93173314
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2302637946
Short name T221
Test name
Test status
Simulation time 595860180 ps
CPU time 1.44 seconds
Started Jul 10 06:03:28 PM PDT 24
Finished Jul 10 06:03:31 PM PDT 24
Peak memory 191892 kb
Host smart-e10b46b9-0857-47ef-93b9-e577593d9f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302637946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2302637946
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2633318142
Short name T39
Test name
Test status
Simulation time 3328200131 ps
CPU time 5.22 seconds
Started Jul 10 06:03:31 PM PDT 24
Finished Jul 10 06:03:37 PM PDT 24
Peak memory 191980 kb
Host smart-20ebb251-b845-49f0-b43b-75709b6b9aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633318142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2633318142
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1615971223
Short name T267
Test name
Test status
Simulation time 387195748 ps
CPU time 1.14 seconds
Started Jul 10 06:03:30 PM PDT 24
Finished Jul 10 06:03:32 PM PDT 24
Peak memory 191912 kb
Host smart-46129d0d-3a46-43b9-98a2-cf32a438e0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615971223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1615971223
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1647904958
Short name T254
Test name
Test status
Simulation time 15833709055 ps
CPU time 8.18 seconds
Started Jul 10 06:03:33 PM PDT 24
Finished Jul 10 06:03:42 PM PDT 24
Peak memory 191988 kb
Host smart-a25e6fa9-0fab-4ca2-b464-8a709c758964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647904958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1647904958
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.4159244923
Short name T219
Test name
Test status
Simulation time 446767710 ps
CPU time 1.3 seconds
Started Jul 10 06:03:32 PM PDT 24
Finished Jul 10 06:03:34 PM PDT 24
Peak memory 191900 kb
Host smart-00dc25b8-04bc-41ab-b67b-f8fe1e245755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159244923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.4159244923
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2122340915
Short name T240
Test name
Test status
Simulation time 52124512294 ps
CPU time 20 seconds
Started Jul 10 06:03:28 PM PDT 24
Finished Jul 10 06:03:49 PM PDT 24
Peak memory 191980 kb
Host smart-755084b6-65fa-47fa-9a79-ce992a0326e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122340915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2122340915
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1885897006
Short name T263
Test name
Test status
Simulation time 536939978 ps
CPU time 1.33 seconds
Started Jul 10 06:03:32 PM PDT 24
Finished Jul 10 06:03:35 PM PDT 24
Peak memory 191820 kb
Host smart-aaa54ee6-6d92-4837-9db2-9ee0a6237225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885897006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1885897006
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.4158776148
Short name T215
Test name
Test status
Simulation time 30761346034 ps
CPU time 46.19 seconds
Started Jul 10 06:03:36 PM PDT 24
Finished Jul 10 06:04:24 PM PDT 24
Peak memory 191884 kb
Host smart-8e3fa55a-1193-41e6-a98d-9e1ee460676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158776148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.4158776148
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.738681479
Short name T256
Test name
Test status
Simulation time 510525060 ps
CPU time 1.36 seconds
Started Jul 10 06:03:34 PM PDT 24
Finished Jul 10 06:03:37 PM PDT 24
Peak memory 191892 kb
Host smart-5487533f-72a4-462a-9514-d53246d9fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738681479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.738681479
Directory /workspace/9.aon_timer_smoke/latest
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