Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 29517 1 T1 464 T2 12 T3 10
bark[1] 415 1 T5 110 T59 40 T119 30
bark[2] 320 1 T60 26 T32 121 T134 52
bark[3] 1079 1 T13 243 T155 78 T127 21
bark[4] 746 1 T28 100 T186 14 T183 14
bark[5] 694 1 T56 21 T125 21 T101 14
bark[6] 1022 1 T11 21 T13 21 T163 21
bark[7] 461 1 T41 14 T104 14 T59 21
bark[8] 419 1 T9 30 T162 89 T90 21
bark[9] 494 1 T13 21 T18 45 T125 61
bark[10] 371 1 T6 14 T168 14 T124 21
bark[11] 842 1 T42 21 T58 78 T125 26
bark[12] 640 1 T9 21 T56 21 T58 21
bark[13] 811 1 T13 124 T165 14 T32 21
bark[14] 178 1 T56 21 T134 26 T117 21
bark[15] 1021 1 T1 26 T12 56 T56 26
bark[16] 441 1 T1 182 T35 31 T121 14
bark[17] 496 1 T5 30 T18 49 T82 176
bark[18] 495 1 T13 21 T30 30 T181 14
bark[19] 952 1 T9 35 T13 47 T109 21
bark[20] 519 1 T7 31 T18 95 T184 14
bark[21] 251 1 T9 21 T142 14 T31 85
bark[22] 284 1 T12 26 T189 14 T134 21
bark[23] 410 1 T28 68 T135 21 T32 26
bark[24] 354 1 T13 21 T19 14 T56 21
bark[25] 346 1 T18 21 T163 23 T79 107
bark[26] 1470 1 T1 21 T11 35 T13 179
bark[27] 639 1 T7 208 T11 21 T163 51
bark[28] 734 1 T11 31 T163 30 T162 54
bark[29] 308 1 T73 21 T127 21 T81 5
bark[30] 722 1 T31 241 T143 21 T109 42
bark[31] 973 1 T12 42 T36 14 T28 21
bark_0 4877 1 T1 70 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 28966 1 T1 457 T2 11 T3 9
bite[1] 1198 1 T1 153 T7 31 T13 178
bite[2] 618 1 T56 21 T60 26 T113 140
bite[3] 398 1 T125 47 T134 26 T145 13
bite[4] 940 1 T1 21 T7 207 T13 21
bite[5] 625 1 T1 21 T11 42 T28 99
bite[6] 999 1 T1 25 T163 81 T113 21
bite[7] 831 1 T12 42 T19 13 T35 30
bite[8] 263 1 T5 30 T183 13 T56 21
bite[9] 254 1 T35 21 T56 21 T109 21
bite[10] 400 1 T9 34 T36 13 T153 59
bite[11] 548 1 T9 21 T165 13 T31 4
bite[12] 520 1 T135 21 T56 21 T32 94
bite[13] 838 1 T13 21 T18 48 T168 13
bite[14] 388 1 T9 21 T184 13 T56 21
bite[15] 681 1 T18 44 T181 13 T125 40
bite[16] 254 1 T42 21 T162 54 T125 40
bite[17] 133 1 T124 21 T81 21 T150 70
bite[18] 647 1 T28 21 T104 13 T117 38
bite[19] 1265 1 T6 13 T163 22 T41 13
bite[20] 613 1 T125 21 T86 13 T140 208
bite[21] 607 1 T13 46 T56 21 T90 218
bite[22] 245 1 T59 40 T60 21 T143 21
bite[23] 393 1 T13 21 T189 13 T136 13
bite[24] 1108 1 T33 266 T125 21 T140 55
bite[25] 265 1 T58 78 T90 21 T80 21
bite[26] 371 1 T13 21 T56 26 T73 21
bite[27] 732 1 T11 35 T12 26 T18 94
bite[28] 682 1 T11 31 T13 102 T186 13
bite[29] 1132 1 T1 6 T142 13 T33 42
bite[30] 478 1 T5 110 T18 21 T163 21
bite[31] 546 1 T9 30 T12 55 T13 21
bite_0 5363 1 T1 80 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 43379 1 T1 347 T2 19 T3 17
auto[1] 9922 1 T1 416 T7 584 T8 7


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1146 1 T1 19 T12 41 T56 9
prescale[1] 1072 1 T5 19 T13 149 T42 40
prescale[2] 1269 1 T5 38 T10 9 T13 9
prescale[3] 809 1 T11 19 T18 37 T33 81
prescale[4] 865 1 T1 97 T162 19 T143 36
prescale[5] 928 1 T1 47 T7 19 T13 45
prescale[6] 504 1 T9 38 T13 58 T31 19
prescale[7] 739 1 T7 2 T13 140 T162 33
prescale[8] 914 1 T18 18 T38 9 T59 19
prescale[9] 725 1 T1 4 T7 38 T9 23
prescale[10] 1101 1 T7 19 T11 60 T13 95
prescale[11] 815 1 T1 2 T7 19 T30 2
prescale[12] 719 1 T1 2 T13 19 T135 33
prescale[13] 687 1 T1 35 T7 21 T13 19
prescale[14] 980 1 T5 53 T13 28 T162 40
prescale[15] 1312 1 T1 95 T7 482 T28 83
prescale[16] 1317 1 T1 19 T7 61 T35 28
prescale[17] 785 1 T13 129 T162 19 T30 39
prescale[18] 837 1 T42 19 T60 23 T155 2
prescale[19] 962 1 T1 166 T18 24 T163 19
prescale[20] 861 1 T2 9 T9 28 T18 2
prescale[21] 1029 1 T5 36 T9 32 T13 76
prescale[22] 856 1 T7 19 T11 28 T13 2
prescale[23] 667 1 T7 84 T13 57 T28 2
prescale[24] 1035 1 T13 19 T37 9 T30 19
prescale[25] 712 1 T5 53 T29 4 T135 87
prescale[26] 287 1 T18 28 T32 2 T113 19
prescale[27] 549 1 T9 49 T162 49 T31 87
prescale[28] 966 1 T1 9 T7 69 T13 23
prescale[29] 557 1 T13 19 T30 19 T58 23
prescale[30] 1025 1 T12 19 T13 119 T153 19
prescale[31] 977 1 T13 92 T30 118 T58 37
prescale_0 25294 1 T1 268 T2 10 T3 17


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 40270 1 T1 563 T2 19 T3 17
auto[1] 13031 1 T1 200 T5 76 T6 12


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 53301 1 T1 763 T2 19 T3 17


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 30503 1 T1 495 T2 14 T3 12
wkup[1] 228 1 T7 21 T13 21 T18 21
wkup[2] 285 1 T7 21 T11 15 T12 21
wkup[3] 378 1 T12 21 T35 21 T165 15
wkup[4] 243 1 T18 21 T31 21 T32 30
wkup[5] 220 1 T32 39 T134 8 T127 26
wkup[6] 343 1 T7 21 T13 21 T35 21
wkup[7] 299 1 T7 21 T18 21 T32 26
wkup[8] 291 1 T13 21 T153 21 T80 51
wkup[9] 187 1 T28 21 T31 20 T109 21
wkup[10] 420 1 T32 39 T33 21 T73 31
wkup[11] 228 1 T162 21 T28 21 T134 21
wkup[12] 360 1 T7 21 T12 15 T13 21
wkup[13] 224 1 T28 21 T79 26 T115 15
wkup[14] 298 1 T1 21 T13 21 T18 21
wkup[15] 205 1 T80 8 T140 47 T81 35
wkup[16] 417 1 T13 80 T28 26 T56 26
wkup[17] 147 1 T1 6 T33 21 T82 21
wkup[18] 334 1 T1 21 T7 26 T13 21
wkup[19] 287 1 T33 21 T125 21 T73 21
wkup[20] 502 1 T7 21 T162 24 T29 21
wkup[21] 289 1 T163 21 T162 30 T29 21
wkup[22] 170 1 T7 21 T42 21 T134 26
wkup[23] 391 1 T5 21 T7 31 T11 21
wkup[24] 191 1 T81 21 T147 21 T131 21
wkup[25] 376 1 T12 26 T13 21 T56 21
wkup[26] 342 1 T7 30 T12 21 T13 21
wkup[27] 242 1 T135 21 T79 21 T127 21
wkup[28] 416 1 T1 36 T36 15 T28 21
wkup[29] 317 1 T9 21 T11 21 T19 15
wkup[30] 290 1 T1 21 T9 21 T11 35
wkup[31] 299 1 T7 42 T13 29 T104 15
wkup[32] 195 1 T1 21 T6 15 T113 33
wkup[33] 264 1 T13 21 T32 21 T121 15
wkup[34] 171 1 T140 21 T81 21 T76 21
wkup[35] 335 1 T18 21 T125 21 T134 21
wkup[36] 155 1 T1 21 T13 21 T56 21
wkup[37] 346 1 T5 21 T18 21 T135 21
wkup[38] 307 1 T1 21 T13 53 T168 15
wkup[39] 265 1 T42 21 T117 21 T79 42
wkup[40] 335 1 T13 21 T56 21 T33 30
wkup[41] 411 1 T42 21 T32 26 T153 21
wkup[42] 427 1 T163 21 T31 30 T125 21
wkup[43] 262 1 T13 21 T32 21 T110 21
wkup[44] 435 1 T32 26 T143 42 T113 21
wkup[45] 287 1 T1 29 T127 21 T90 21
wkup[46] 319 1 T13 21 T18 21 T127 21
wkup[47] 325 1 T7 21 T28 42 T30 30
wkup[48] 418 1 T28 21 T117 24 T127 21
wkup[49] 236 1 T7 21 T13 24 T58 21
wkup[50] 296 1 T11 21 T163 30 T33 21
wkup[51] 180 1 T13 21 T41 15 T58 21
wkup[52] 244 1 T39 15 T73 21 T134 15
wkup[53] 284 1 T13 21 T163 45 T58 21
wkup[54] 426 1 T162 42 T29 8 T30 59
wkup[55] 379 1 T1 21 T189 15 T56 21
wkup[56] 338 1 T7 21 T11 31 T13 21
wkup[57] 274 1 T163 30 T80 21 T81 6
wkup[58] 353 1 T9 51 T12 21 T163 21
wkup[59] 276 1 T5 30 T134 21 T79 21
wkup[60] 316 1 T9 15 T31 21 T32 21
wkup[61] 338 1 T56 21 T60 26 T117 21
wkup[62] 296 1 T7 21 T134 21 T149 21
wkup[63] 282 1 T18 8 T155 26 T136 15
wkup_0 3804 1 T1 50 T2 5 T3 5

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