Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.45 99.33 93.67 100.00 98.40 99.51 51.82


Total test records in report: 424
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T20 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1238667990 Jul 11 05:46:41 PM PDT 24 Jul 11 05:46:51 PM PDT 24 9195849852 ps
T282 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3232536553 Jul 11 05:46:49 PM PDT 24 Jul 11 05:46:53 PM PDT 24 413680098 ps
T27 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2244157894 Jul 11 05:47:07 PM PDT 24 Jul 11 05:47:09 PM PDT 24 527332887 ps
T283 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4256740288 Jul 11 05:47:17 PM PDT 24 Jul 11 05:47:22 PM PDT 24 402743294 ps
T21 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.825236115 Jul 11 05:47:06 PM PDT 24 Jul 11 05:47:08 PM PDT 24 433160894 ps
T22 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3006711572 Jul 11 05:46:47 PM PDT 24 Jul 11 05:46:50 PM PDT 24 305555039 ps
T284 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1500443689 Jul 11 05:47:29 PM PDT 24 Jul 11 05:47:32 PM PDT 24 508644040 ps
T25 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4103118964 Jul 11 05:47:24 PM PDT 24 Jul 11 05:47:30 PM PDT 24 4581888122 ps
T285 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4150012777 Jul 11 05:47:09 PM PDT 24 Jul 11 05:47:12 PM PDT 24 475190782 ps
T286 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3273979100 Jul 11 05:47:18 PM PDT 24 Jul 11 05:47:22 PM PDT 24 502945840 ps
T44 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1433502030 Jul 11 05:47:16 PM PDT 24 Jul 11 05:47:20 PM PDT 24 307867123 ps
T26 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.96180232 Jul 11 05:46:47 PM PDT 24 Jul 11 05:47:01 PM PDT 24 8316138751 ps
T45 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.630368040 Jul 11 05:46:53 PM PDT 24 Jul 11 05:47:28 PM PDT 24 12823469489 ps
T287 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2923956055 Jul 11 05:46:56 PM PDT 24 Jul 11 05:47:00 PM PDT 24 446680107 ps
T288 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3577628833 Jul 11 05:46:56 PM PDT 24 Jul 11 05:47:00 PM PDT 24 472248269 ps
T46 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1190402545 Jul 11 05:46:53 PM PDT 24 Jul 11 05:46:56 PM PDT 24 449023812 ps
T289 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2063234831 Jul 11 05:47:09 PM PDT 24 Jul 11 05:47:13 PM PDT 24 360987834 ps
T64 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.500462732 Jul 11 05:47:43 PM PDT 24 Jul 11 05:47:47 PM PDT 24 347267528 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3282660265 Jul 11 05:46:52 PM PDT 24 Jul 11 05:46:56 PM PDT 24 936989826 ps
T290 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3849440676 Jul 11 05:47:03 PM PDT 24 Jul 11 05:47:06 PM PDT 24 475282507 ps
T291 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2012831963 Jul 11 05:47:23 PM PDT 24 Jul 11 05:47:26 PM PDT 24 524169921 ps
T292 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1819373451 Jul 11 05:47:23 PM PDT 24 Jul 11 05:47:27 PM PDT 24 288098276 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2826726767 Jul 11 05:46:58 PM PDT 24 Jul 11 05:47:03 PM PDT 24 2076708027 ps
T293 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3533088558 Jul 11 05:47:07 PM PDT 24 Jul 11 05:47:08 PM PDT 24 525959158 ps
T47 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1299637991 Jul 11 05:46:45 PM PDT 24 Jul 11 05:46:49 PM PDT 24 1205161341 ps
T67 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2180125091 Jul 11 05:47:14 PM PDT 24 Jul 11 05:47:20 PM PDT 24 1953514678 ps
T48 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.579281459 Jul 11 05:47:16 PM PDT 24 Jul 11 05:47:20 PM PDT 24 316213599 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.992718176 Jul 11 05:47:15 PM PDT 24 Jul 11 05:47:19 PM PDT 24 354192071 ps
T49 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3349179191 Jul 11 05:46:59 PM PDT 24 Jul 11 05:47:23 PM PDT 24 10349203227 ps
T68 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2089685558 Jul 11 05:47:17 PM PDT 24 Jul 11 05:47:22 PM PDT 24 942956647 ps
T295 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3132907007 Jul 11 05:47:24 PM PDT 24 Jul 11 05:47:27 PM PDT 24 311529377 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2468696345 Jul 11 05:46:58 PM PDT 24 Jul 11 05:47:02 PM PDT 24 634607508 ps
T69 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3217316846 Jul 11 05:47:13 PM PDT 24 Jul 11 05:47:16 PM PDT 24 1160723018 ps
T297 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2658923218 Jul 11 05:46:56 PM PDT 24 Jul 11 05:47:03 PM PDT 24 4537859816 ps
T298 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4020037808 Jul 11 05:47:15 PM PDT 24 Jul 11 05:47:19 PM PDT 24 427954398 ps
T299 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3377012389 Jul 11 05:46:55 PM PDT 24 Jul 11 05:46:58 PM PDT 24 286688739 ps
T70 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2208878459 Jul 11 05:46:58 PM PDT 24 Jul 11 05:47:02 PM PDT 24 1202902886 ps
T300 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1085600139 Jul 11 05:47:24 PM PDT 24 Jul 11 05:47:28 PM PDT 24 371734653 ps
T71 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2953349008 Jul 11 05:47:15 PM PDT 24 Jul 11 05:47:21 PM PDT 24 2258574844 ps
T301 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2861460875 Jul 11 05:46:55 PM PDT 24 Jul 11 05:46:59 PM PDT 24 304604893 ps
T302 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1122592099 Jul 11 05:47:10 PM PDT 24 Jul 11 05:47:13 PM PDT 24 285351822 ps
T303 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.23298229 Jul 11 05:47:02 PM PDT 24 Jul 11 05:47:05 PM PDT 24 413175188 ps
T72 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1760516933 Jul 11 05:47:08 PM PDT 24 Jul 11 05:47:14 PM PDT 24 2699017798 ps
T304 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.57007836 Jul 11 05:47:01 PM PDT 24 Jul 11 05:47:10 PM PDT 24 4619622596 ps
T305 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2122217333 Jul 11 05:47:32 PM PDT 24 Jul 11 05:47:38 PM PDT 24 1840144657 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2760761452 Jul 11 05:46:56 PM PDT 24 Jul 11 05:46:59 PM PDT 24 955765554 ps
T306 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3531032579 Jul 11 05:47:13 PM PDT 24 Jul 11 05:47:16 PM PDT 24 1943645600 ps
T307 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1128382331 Jul 11 05:46:59 PM PDT 24 Jul 11 05:47:04 PM PDT 24 589069537 ps
T308 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.354304076 Jul 11 05:47:18 PM PDT 24 Jul 11 05:47:22 PM PDT 24 300101682 ps
T309 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.485536499 Jul 11 05:47:43 PM PDT 24 Jul 11 05:47:46 PM PDT 24 439338318 ps
T310 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1906639762 Jul 11 05:47:17 PM PDT 24 Jul 11 05:47:22 PM PDT 24 353239870 ps
T311 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4151835293 Jul 11 05:46:39 PM PDT 24 Jul 11 05:46:42 PM PDT 24 375088966 ps
T312 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2716641275 Jul 11 05:47:08 PM PDT 24 Jul 11 05:47:11 PM PDT 24 752939056 ps
T313 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.150562430 Jul 11 05:47:15 PM PDT 24 Jul 11 05:47:19 PM PDT 24 576723321 ps
T314 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2100242884 Jul 11 05:47:06 PM PDT 24 Jul 11 05:47:07 PM PDT 24 541772473 ps
T315 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2049872389 Jul 11 05:47:01 PM PDT 24 Jul 11 05:47:04 PM PDT 24 345919513 ps
T316 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3290409305 Jul 11 05:47:13 PM PDT 24 Jul 11 05:47:26 PM PDT 24 8286998286 ps
T317 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4245738543 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 318208636 ps
T318 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3435673250 Jul 11 05:46:55 PM PDT 24 Jul 11 05:47:15 PM PDT 24 13879174385 ps
T319 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2539468574 Jul 11 05:47:03 PM PDT 24 Jul 11 05:47:05 PM PDT 24 512491902 ps
T320 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2942793474 Jul 11 05:47:18 PM PDT 24 Jul 11 05:47:22 PM PDT 24 2919771744 ps
T321 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.986463280 Jul 11 05:47:24 PM PDT 24 Jul 11 05:47:28 PM PDT 24 286146887 ps
T322 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2076070553 Jul 11 05:46:46 PM PDT 24 Jul 11 05:46:49 PM PDT 24 369796809 ps
T323 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2407672284 Jul 11 05:47:10 PM PDT 24 Jul 11 05:47:13 PM PDT 24 709225235 ps
T324 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3415218963 Jul 11 05:47:38 PM PDT 24 Jul 11 05:47:42 PM PDT 24 505207245 ps
T50 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.489797207 Jul 11 05:46:44 PM PDT 24 Jul 11 05:46:55 PM PDT 24 7082404013 ps
T325 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1664495073 Jul 11 05:46:52 PM PDT 24 Jul 11 05:46:57 PM PDT 24 528957272 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.38241000 Jul 11 05:46:57 PM PDT 24 Jul 11 05:47:01 PM PDT 24 593016168 ps
T326 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2382734476 Jul 11 05:46:58 PM PDT 24 Jul 11 05:47:02 PM PDT 24 494506289 ps
T327 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1324213840 Jul 11 05:47:13 PM PDT 24 Jul 11 05:47:16 PM PDT 24 493259010 ps
T190 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4248941937 Jul 11 05:47:14 PM PDT 24 Jul 11 05:47:19 PM PDT 24 8714157012 ps
T328 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3479019590 Jul 11 05:47:17 PM PDT 24 Jul 11 05:47:21 PM PDT 24 274214311 ps
T329 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2135609038 Jul 11 05:47:11 PM PDT 24 Jul 11 05:47:13 PM PDT 24 462717955 ps
T330 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2770828205 Jul 11 05:47:14 PM PDT 24 Jul 11 05:47:18 PM PDT 24 455775536 ps
T331 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1895446389 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 320292673 ps
T332 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.401756943 Jul 11 05:47:16 PM PDT 24 Jul 11 05:47:20 PM PDT 24 716025657 ps
T333 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2970124547 Jul 11 05:47:11 PM PDT 24 Jul 11 05:47:14 PM PDT 24 482105894 ps
T334 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.630425060 Jul 11 05:47:05 PM PDT 24 Jul 11 05:47:08 PM PDT 24 436543808 ps
T335 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2455324708 Jul 11 05:47:18 PM PDT 24 Jul 11 05:47:22 PM PDT 24 576886537 ps
T336 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.894305167 Jul 11 05:46:46 PM PDT 24 Jul 11 05:46:49 PM PDT 24 546893825 ps
T337 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2382412461 Jul 11 05:47:19 PM PDT 24 Jul 11 05:47:23 PM PDT 24 422336807 ps
T338 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.687934896 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 295452978 ps
T339 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1538808072 Jul 11 05:46:47 PM PDT 24 Jul 11 05:46:50 PM PDT 24 383766064 ps
T340 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.630461631 Jul 11 05:46:53 PM PDT 24 Jul 11 05:46:56 PM PDT 24 462863958 ps
T341 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.162506304 Jul 11 05:47:09 PM PDT 24 Jul 11 05:47:13 PM PDT 24 417518422 ps
T342 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2835180788 Jul 11 05:47:15 PM PDT 24 Jul 11 05:47:19 PM PDT 24 479834738 ps
T343 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3694742207 Jul 11 05:47:43 PM PDT 24 Jul 11 05:47:48 PM PDT 24 4417381433 ps
T344 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2434255776 Jul 11 05:47:13 PM PDT 24 Jul 11 05:47:16 PM PDT 24 598983571 ps
T345 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.187195879 Jul 11 05:46:57 PM PDT 24 Jul 11 05:47:03 PM PDT 24 1578982429 ps
T346 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.762311081 Jul 11 05:47:29 PM PDT 24 Jul 11 05:47:34 PM PDT 24 826952016 ps
T347 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1800845849 Jul 11 05:46:39 PM PDT 24 Jul 11 05:46:41 PM PDT 24 352407074 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1587981853 Jul 11 05:46:40 PM PDT 24 Jul 11 05:46:42 PM PDT 24 851236930 ps
T349 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1352679644 Jul 11 05:47:43 PM PDT 24 Jul 11 05:47:46 PM PDT 24 505892332 ps
T350 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1124995510 Jul 11 05:46:48 PM PDT 24 Jul 11 05:46:50 PM PDT 24 489306485 ps
T351 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.938265639 Jul 11 05:47:07 PM PDT 24 Jul 11 05:47:09 PM PDT 24 339129988 ps
T352 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.387049161 Jul 11 05:46:56 PM PDT 24 Jul 11 05:47:00 PM PDT 24 487145833 ps
T353 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1165282420 Jul 11 05:47:27 PM PDT 24 Jul 11 05:47:30 PM PDT 24 562623454 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3953838876 Jul 11 05:46:46 PM PDT 24 Jul 11 05:46:48 PM PDT 24 313998207 ps
T355 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2353390879 Jul 11 05:47:13 PM PDT 24 Jul 11 05:47:18 PM PDT 24 2702082022 ps
T356 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.191514580 Jul 11 05:47:19 PM PDT 24 Jul 11 05:47:27 PM PDT 24 4650569359 ps
T357 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.380410351 Jul 11 05:47:25 PM PDT 24 Jul 11 05:47:29 PM PDT 24 447321936 ps
T358 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2360623941 Jul 11 05:46:58 PM PDT 24 Jul 11 05:47:01 PM PDT 24 470713654 ps
T359 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3523814640 Jul 11 05:47:19 PM PDT 24 Jul 11 05:47:23 PM PDT 24 345994504 ps
T360 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.226228058 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 971028482 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1659131890 Jul 11 05:46:49 PM PDT 24 Jul 11 05:46:58 PM PDT 24 2502041603 ps
T362 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.380694219 Jul 11 05:47:25 PM PDT 24 Jul 11 05:47:28 PM PDT 24 311146494 ps
T363 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1635095278 Jul 11 05:47:24 PM PDT 24 Jul 11 05:47:27 PM PDT 24 413229341 ps
T364 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1528553808 Jul 11 05:47:09 PM PDT 24 Jul 11 05:47:12 PM PDT 24 538590125 ps
T365 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1774563296 Jul 11 05:47:25 PM PDT 24 Jul 11 05:47:29 PM PDT 24 514418591 ps
T366 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.303689261 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:36 PM PDT 24 457612035 ps
T367 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2392476818 Jul 11 05:47:25 PM PDT 24 Jul 11 05:47:29 PM PDT 24 1420179541 ps
T368 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.921115204 Jul 11 05:47:18 PM PDT 24 Jul 11 05:47:22 PM PDT 24 427793085 ps
T369 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4056348470 Jul 11 05:47:25 PM PDT 24 Jul 11 05:47:29 PM PDT 24 443934231 ps
T370 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.933375874 Jul 11 05:46:51 PM PDT 24 Jul 11 05:46:55 PM PDT 24 331280413 ps
T371 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3168138011 Jul 11 05:47:02 PM PDT 24 Jul 11 05:47:05 PM PDT 24 350572769 ps
T372 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4183355765 Jul 11 05:47:02 PM PDT 24 Jul 11 05:47:06 PM PDT 24 1371551586 ps
T373 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2798279024 Jul 11 05:47:05 PM PDT 24 Jul 11 05:47:13 PM PDT 24 8696560944 ps
T374 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3439163011 Jul 11 05:47:23 PM PDT 24 Jul 11 05:47:26 PM PDT 24 413750926 ps
T375 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1838814683 Jul 11 05:47:32 PM PDT 24 Jul 11 05:47:36 PM PDT 24 467279687 ps
T55 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3452720943 Jul 11 05:47:16 PM PDT 24 Jul 11 05:47:20 PM PDT 24 495713484 ps
T376 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2862546392 Jul 11 05:47:18 PM PDT 24 Jul 11 05:47:23 PM PDT 24 447639439 ps
T377 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1590020798 Jul 11 05:46:48 PM PDT 24 Jul 11 05:46:50 PM PDT 24 1168960092 ps
T378 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.694595183 Jul 11 05:47:24 PM PDT 24 Jul 11 05:47:28 PM PDT 24 445022277 ps
T379 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1623472643 Jul 11 05:47:25 PM PDT 24 Jul 11 05:47:29 PM PDT 24 469729084 ps
T380 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1264092949 Jul 11 05:47:12 PM PDT 24 Jul 11 05:47:16 PM PDT 24 2191413439 ps
T381 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3588975332 Jul 11 05:46:46 PM PDT 24 Jul 11 05:46:48 PM PDT 24 439682692 ps
T382 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3217207324 Jul 11 05:47:17 PM PDT 24 Jul 11 05:47:27 PM PDT 24 4264361180 ps
T383 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3353662550 Jul 11 05:47:16 PM PDT 24 Jul 11 05:47:21 PM PDT 24 310428142 ps
T384 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.496366021 Jul 11 05:46:44 PM PDT 24 Jul 11 05:46:47 PM PDT 24 297685909 ps
T51 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4232701552 Jul 11 05:46:58 PM PDT 24 Jul 11 05:47:03 PM PDT 24 528756851 ps
T385 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3664860380 Jul 11 05:46:59 PM PDT 24 Jul 11 05:47:02 PM PDT 24 463671101 ps
T386 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3125250017 Jul 11 05:47:06 PM PDT 24 Jul 11 05:47:12 PM PDT 24 8762110209 ps
T387 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3584537753 Jul 11 05:47:14 PM PDT 24 Jul 11 05:47:18 PM PDT 24 433522624 ps
T388 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3265443117 Jul 11 05:47:26 PM PDT 24 Jul 11 05:47:29 PM PDT 24 352502691 ps
T389 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1218902296 Jul 11 05:47:20 PM PDT 24 Jul 11 05:47:30 PM PDT 24 4321996731 ps
T390 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3214486795 Jul 11 05:47:16 PM PDT 24 Jul 11 05:47:20 PM PDT 24 420782965 ps
T391 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.13537235 Jul 11 05:46:47 PM PDT 24 Jul 11 05:46:50 PM PDT 24 607623629 ps
T392 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2852974241 Jul 11 05:47:13 PM PDT 24 Jul 11 05:47:16 PM PDT 24 1274308262 ps
T393 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3248843815 Jul 11 05:46:58 PM PDT 24 Jul 11 05:47:02 PM PDT 24 317054070 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2951630219 Jul 11 05:46:56 PM PDT 24 Jul 11 05:47:11 PM PDT 24 7923663014 ps
T395 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.476614876 Jul 11 05:47:23 PM PDT 24 Jul 11 05:47:33 PM PDT 24 4296695715 ps
T396 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2407440882 Jul 11 05:46:58 PM PDT 24 Jul 11 05:47:02 PM PDT 24 468035151 ps
T397 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1212307213 Jul 11 05:47:37 PM PDT 24 Jul 11 05:47:41 PM PDT 24 364641881 ps
T192 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2907548087 Jul 11 05:46:45 PM PDT 24 Jul 11 05:47:01 PM PDT 24 8238875788 ps
T398 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.822351577 Jul 11 05:47:18 PM PDT 24 Jul 11 05:47:23 PM PDT 24 513759850 ps
T399 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4227337109 Jul 11 05:46:58 PM PDT 24 Jul 11 05:47:02 PM PDT 24 342634571 ps
T400 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1780524140 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:38 PM PDT 24 4160761979 ps
T401 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2747431867 Jul 11 05:47:14 PM PDT 24 Jul 11 05:47:17 PM PDT 24 516774056 ps
T402 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1081008236 Jul 11 05:47:24 PM PDT 24 Jul 11 05:47:27 PM PDT 24 502841559 ps
T403 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3638165270 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 400390419 ps
T404 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4285243870 Jul 11 05:47:24 PM PDT 24 Jul 11 05:47:28 PM PDT 24 539655795 ps
T405 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.862012671 Jul 11 05:46:47 PM PDT 24 Jul 11 05:46:51 PM PDT 24 715144262 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.921660432 Jul 11 05:46:50 PM PDT 24 Jul 11 05:47:02 PM PDT 24 12175090656 ps
T406 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3983607040 Jul 11 05:46:55 PM PDT 24 Jul 11 05:47:00 PM PDT 24 517277065 ps
T407 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4261387995 Jul 11 05:47:15 PM PDT 24 Jul 11 05:47:21 PM PDT 24 4126084035 ps
T408 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.239629470 Jul 11 05:46:47 PM PDT 24 Jul 11 05:46:51 PM PDT 24 2616829298 ps
T409 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3651435895 Jul 11 05:47:22 PM PDT 24 Jul 11 05:47:25 PM PDT 24 400553551 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1876293895 Jul 11 05:47:02 PM PDT 24 Jul 11 05:47:07 PM PDT 24 4284644806 ps
T191 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1223138498 Jul 11 05:46:52 PM PDT 24 Jul 11 05:46:58 PM PDT 24 8431857316 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2825269078 Jul 11 05:46:48 PM PDT 24 Jul 11 05:46:53 PM PDT 24 1128680040 ps
T412 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3211154765 Jul 11 05:47:28 PM PDT 24 Jul 11 05:47:31 PM PDT 24 353225697 ps
T413 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.637593045 Jul 11 05:46:40 PM PDT 24 Jul 11 05:46:44 PM PDT 24 358899790 ps
T414 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.597980048 Jul 11 05:47:18 PM PDT 24 Jul 11 05:47:22 PM PDT 24 599898104 ps
T415 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.763120260 Jul 11 05:47:02 PM PDT 24 Jul 11 05:47:05 PM PDT 24 521844942 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.471634487 Jul 11 05:46:56 PM PDT 24 Jul 11 05:46:59 PM PDT 24 501978504 ps
T417 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4052043394 Jul 11 05:47:13 PM PDT 24 Jul 11 05:47:16 PM PDT 24 404438117 ps
T418 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.381216382 Jul 11 05:47:19 PM PDT 24 Jul 11 05:47:24 PM PDT 24 599748289 ps
T419 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1410402559 Jul 11 05:46:46 PM PDT 24 Jul 11 05:46:50 PM PDT 24 378047926 ps
T420 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.91417634 Jul 11 05:47:43 PM PDT 24 Jul 11 05:47:47 PM PDT 24 372254477 ps
T421 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3977327501 Jul 11 05:47:05 PM PDT 24 Jul 11 05:47:07 PM PDT 24 631460797 ps
T422 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4157107031 Jul 11 05:47:12 PM PDT 24 Jul 11 05:47:15 PM PDT 24 341402419 ps
T423 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3190321024 Jul 11 05:46:56 PM PDT 24 Jul 11 05:47:00 PM PDT 24 2272973810 ps
T424 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1828983292 Jul 11 05:46:51 PM PDT 24 Jul 11 05:46:55 PM PDT 24 486981379 ps
T52 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.244093146 Jul 11 05:47:31 PM PDT 24 Jul 11 05:47:35 PM PDT 24 507420030 ps

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1822562255
Short name T7
Test name
Test status
Simulation time 63344437538 ps
CPU time 234.27 seconds
Started Jul 11 05:45:46 PM PDT 24
Finished Jul 11 05:49:43 PM PDT 24
Peak memory 207784 kb
Host smart-d448d006-b319-459f-b34e-90a0b9ab4927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822562255 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1822562255
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3554999543
Short name T18
Test name
Test status
Simulation time 242503164707 ps
CPU time 539.38 seconds
Started Jul 11 05:46:11 PM PDT 24
Finished Jul 11 05:55:13 PM PDT 24
Peak memory 204440 kb
Host smart-fd457ab0-cc13-42fd-b216-ab48a1d97dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554999543 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3554999543
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.704483492
Short name T13
Test name
Test status
Simulation time 850070948432 ps
CPU time 525.5 seconds
Started Jul 11 05:46:37 PM PDT 24
Finished Jul 11 05:55:24 PM PDT 24
Peak memory 204360 kb
Host smart-859b0c54-9453-4a98-8aee-d2fb715770b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704483492 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.704483492
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1238667990
Short name T20
Test name
Test status
Simulation time 9195849852 ps
CPU time 7.57 seconds
Started Jul 11 05:46:41 PM PDT 24
Finished Jul 11 05:46:51 PM PDT 24
Peak memory 198184 kb
Host smart-7f253a03-cdc1-488e-8184-748ce672b2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238667990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1238667990
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1800600991
Short name T89
Test name
Test status
Simulation time 689827536643 ps
CPU time 1111.26 seconds
Started Jul 11 05:46:41 PM PDT 24
Finished Jul 11 06:05:14 PM PDT 24
Peak memory 214920 kb
Host smart-1593d700-7233-40ba-b35d-38b9ffbf02c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800600991 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1800600991
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2093787732
Short name T82
Test name
Test status
Simulation time 816618480404 ps
CPU time 766.58 seconds
Started Jul 11 05:46:32 PM PDT 24
Finished Jul 11 05:59:20 PM PDT 24
Peak memory 214972 kb
Host smart-b7e194ec-5dce-40f4-959f-4566cbd9229f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093787732 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2093787732
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2234217616
Short name T56
Test name
Test status
Simulation time 199446370644 ps
CPU time 32.24 seconds
Started Jul 11 05:46:00 PM PDT 24
Finished Jul 11 05:46:35 PM PDT 24
Peak memory 192836 kb
Host smart-8c5be28d-617d-46ea-afbd-18cbd04e5b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234217616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2234217616
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.842439286
Short name T132
Test name
Test status
Simulation time 711114478556 ps
CPU time 534.38 seconds
Started Jul 11 05:46:05 PM PDT 24
Finished Jul 11 05:55:03 PM PDT 24
Peak memory 215052 kb
Host smart-6c10cb5c-2a6d-48c1-85ae-f0408ada2404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842439286 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.842439286
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1494876842
Short name T77
Test name
Test status
Simulation time 223244470989 ps
CPU time 596.41 seconds
Started Jul 11 05:46:21 PM PDT 24
Finished Jul 11 05:56:20 PM PDT 24
Peak memory 213648 kb
Host smart-87401709-71e2-46a0-953e-9e7f1c6f0d81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494876842 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1494876842
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2765097819
Short name T103
Test name
Test status
Simulation time 489880884308 ps
CPU time 337.82 seconds
Started Jul 11 05:46:00 PM PDT 24
Finished Jul 11 05:51:41 PM PDT 24
Peak memory 202224 kb
Host smart-37a6cc38-d2a6-466b-9042-8575f9c15ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765097819 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2765097819
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.4287449178
Short name T81
Test name
Test status
Simulation time 54481667821 ps
CPU time 396.19 seconds
Started Jul 11 05:46:04 PM PDT 24
Finished Jul 11 05:52:43 PM PDT 24
Peak memory 208724 kb
Host smart-f7d838a8-0d89-4851-b96f-629eb0415c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287449178 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.4287449178
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4290498624
Short name T4
Test name
Test status
Simulation time 7723853670 ps
CPU time 11.98 seconds
Started Jul 11 05:46:02 PM PDT 24
Finished Jul 11 05:46:17 PM PDT 24
Peak memory 215812 kb
Host smart-d939eb21-b45d-4e6d-9850-b742b2df583e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290498624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4290498624
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3303242059
Short name T32
Test name
Test status
Simulation time 266491312223 ps
CPU time 486.16 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:55:05 PM PDT 24
Peak memory 211988 kb
Host smart-1c70f1d0-5d45-4897-901e-9c1ae5e65d78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303242059 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3303242059
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2943757857
Short name T94
Test name
Test status
Simulation time 603001462953 ps
CPU time 793.8 seconds
Started Jul 11 05:46:39 PM PDT 24
Finished Jul 11 05:59:54 PM PDT 24
Peak memory 184332 kb
Host smart-03608c95-2f16-4b9b-8353-1c20214dc048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943757857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2943757857
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.875821727
Short name T11
Test name
Test status
Simulation time 4021464929 ps
CPU time 1.52 seconds
Started Jul 11 05:46:24 PM PDT 24
Finished Jul 11 05:46:28 PM PDT 24
Peak memory 198268 kb
Host smart-e7ca925e-15b9-45e3-a321-2c8f88d23ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875821727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.875821727
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3395106156
Short name T99
Test name
Test status
Simulation time 191118991577 ps
CPU time 239.2 seconds
Started Jul 11 05:45:49 PM PDT 24
Finished Jul 11 05:49:50 PM PDT 24
Peak memory 198152 kb
Host smart-34fa8e72-bdd4-43a9-b555-fa898fd50ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395106156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3395106156
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2916437187
Short name T106
Test name
Test status
Simulation time 157796829615 ps
CPU time 301.13 seconds
Started Jul 11 05:45:54 PM PDT 24
Finished Jul 11 05:50:58 PM PDT 24
Peak memory 201484 kb
Host smart-cdef2f16-4b3a-4ac0-99c0-95455fd297af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916437187 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2916437187
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.878480641
Short name T110
Test name
Test status
Simulation time 346584807497 ps
CPU time 133.63 seconds
Started Jul 11 05:46:16 PM PDT 24
Finished Jul 11 05:48:31 PM PDT 24
Peak memory 192980 kb
Host smart-98b3df59-c7bb-4e05-8e09-3e416bb9f933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878480641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.878480641
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.425189862
Short name T109
Test name
Test status
Simulation time 131640536964 ps
CPU time 46.2 seconds
Started Jul 11 05:46:19 PM PDT 24
Finished Jul 11 05:47:07 PM PDT 24
Peak memory 198344 kb
Host smart-3625edfc-cd43-433a-96fb-23c7447ff629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425189862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.425189862
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3617934317
Short name T120
Test name
Test status
Simulation time 79807218046 ps
CPU time 109.79 seconds
Started Jul 11 05:46:57 PM PDT 24
Finished Jul 11 05:48:49 PM PDT 24
Peak memory 192640 kb
Host smart-50eeda6a-049c-4374-b312-b5ac55be64bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617934317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3617934317
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1442277181
Short name T90
Test name
Test status
Simulation time 125124751370 ps
CPU time 616.5 seconds
Started Jul 11 05:46:32 PM PDT 24
Finished Jul 11 05:56:50 PM PDT 24
Peak memory 205288 kb
Host smart-b7820dc0-6248-4218-8307-205eb04a6a1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442277181 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1442277181
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.579281459
Short name T48
Test name
Test status
Simulation time 316213599 ps
CPU time 0.83 seconds
Started Jul 11 05:47:16 PM PDT 24
Finished Jul 11 05:47:20 PM PDT 24
Peak memory 193428 kb
Host smart-4c4a96a7-cb5a-4dbd-bbff-570bc32f53ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579281459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.579281459
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2813023285
Short name T98
Test name
Test status
Simulation time 195208470645 ps
CPU time 134.34 seconds
Started Jul 11 05:46:36 PM PDT 24
Finished Jul 11 05:48:52 PM PDT 24
Peak memory 193084 kb
Host smart-aae2ec8a-c442-442e-9f7e-96eb8092a0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813023285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2813023285
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3645973835
Short name T75
Test name
Test status
Simulation time 283962885537 ps
CPU time 615.35 seconds
Started Jul 11 05:46:00 PM PDT 24
Finished Jul 11 05:56:18 PM PDT 24
Peak memory 205612 kb
Host smart-dc1b1150-d34b-447c-8a10-dc5cba116de6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645973835 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3645973835
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2741683084
Short name T85
Test name
Test status
Simulation time 136259458818 ps
CPU time 232.1 seconds
Started Jul 11 05:46:14 PM PDT 24
Finished Jul 11 05:50:09 PM PDT 24
Peak memory 200504 kb
Host smart-93175e07-1dda-46be-bea4-e67beb00e470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741683084 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2741683084
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.510810650
Short name T80
Test name
Test status
Simulation time 150365129012 ps
CPU time 259.97 seconds
Started Jul 11 05:46:41 PM PDT 24
Finished Jul 11 05:51:03 PM PDT 24
Peak memory 209172 kb
Host smart-23b47738-9b32-4d22-aa66-5ac64369b9b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510810650 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.510810650
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3296207148
Short name T78
Test name
Test status
Simulation time 130326420851 ps
CPU time 516.05 seconds
Started Jul 11 05:46:12 PM PDT 24
Finished Jul 11 05:54:50 PM PDT 24
Peak memory 213944 kb
Host smart-6beea7c5-a9e8-4151-a733-737f0af7b094
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296207148 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3296207148
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.631339196
Short name T105
Test name
Test status
Simulation time 17175228855 ps
CPU time 175.9 seconds
Started Jul 11 05:46:24 PM PDT 24
Finished Jul 11 05:49:23 PM PDT 24
Peak memory 198488 kb
Host smart-b0d5522a-5bda-4b91-a423-102c99a786f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631339196 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.631339196
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.857683875
Short name T126
Test name
Test status
Simulation time 25358411729 ps
CPU time 260.33 seconds
Started Jul 11 05:46:05 PM PDT 24
Finished Jul 11 05:50:28 PM PDT 24
Peak memory 198924 kb
Host smart-48bb8da8-a030-4c42-9001-ddadb7cfd8a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857683875 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.857683875
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.543233808
Short name T117
Test name
Test status
Simulation time 51661498795 ps
CPU time 70.01 seconds
Started Jul 11 05:46:02 PM PDT 24
Finished Jul 11 05:47:15 PM PDT 24
Peak memory 192572 kb
Host smart-95f35213-711f-4172-acab-e3f53a2b7ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543233808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.543233808
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2142256600
Short name T79
Test name
Test status
Simulation time 333989114629 ps
CPU time 716.69 seconds
Started Jul 11 05:45:45 PM PDT 24
Finished Jul 11 05:57:43 PM PDT 24
Peak memory 215060 kb
Host smart-26cd2c08-725c-480b-9d09-9c8889aae6ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142256600 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2142256600
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3497815040
Short name T140
Test name
Test status
Simulation time 51428060231 ps
CPU time 554.62 seconds
Started Jul 11 05:46:27 PM PDT 24
Finished Jul 11 05:55:45 PM PDT 24
Peak memory 202692 kb
Host smart-81dfb726-78d5-4392-a443-182ea7ce70ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497815040 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3497815040
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3615482119
Short name T111
Test name
Test status
Simulation time 49254983288 ps
CPU time 65.83 seconds
Started Jul 11 05:46:03 PM PDT 24
Finished Jul 11 05:47:12 PM PDT 24
Peak memory 198488 kb
Host smart-f0d470bf-c0af-42cb-ac61-a9780de3e611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615482119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3615482119
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1942131980
Short name T129
Test name
Test status
Simulation time 278502533156 ps
CPU time 340.04 seconds
Started Jul 11 05:46:36 PM PDT 24
Finished Jul 11 05:52:17 PM PDT 24
Peak memory 192944 kb
Host smart-0a526232-e706-46d1-b0af-f5b82dcb4786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942131980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1942131980
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1747860175
Short name T88
Test name
Test status
Simulation time 75997840750 ps
CPU time 188.76 seconds
Started Jul 11 05:46:09 PM PDT 24
Finished Jul 11 05:49:19 PM PDT 24
Peak memory 207668 kb
Host smart-05e59ebf-06f9-4a39-9304-e08820458d68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747860175 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1747860175
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1365737021
Short name T113
Test name
Test status
Simulation time 83201847803 ps
CPU time 128.51 seconds
Started Jul 11 05:46:41 PM PDT 24
Finished Jul 11 05:48:52 PM PDT 24
Peak memory 198292 kb
Host smart-a6ef9e5f-e8fd-4585-8c28-013300f2e2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365737021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1365737021
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.941058287
Short name T108
Test name
Test status
Simulation time 32041572096 ps
CPU time 43.7 seconds
Started Jul 11 05:46:23 PM PDT 24
Finished Jul 11 05:47:10 PM PDT 24
Peak memory 198352 kb
Host smart-4a070676-9ced-4950-9107-74043287b301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941058287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.941058287
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3136535820
Short name T134
Test name
Test status
Simulation time 74693505911 ps
CPU time 302.92 seconds
Started Jul 11 05:46:27 PM PDT 24
Finished Jul 11 05:51:34 PM PDT 24
Peak memory 214016 kb
Host smart-7169a428-ee45-4329-8ec6-d3e4e742bf5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136535820 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3136535820
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.190133749
Short name T83
Test name
Test status
Simulation time 469093811086 ps
CPU time 310.87 seconds
Started Jul 11 05:45:45 PM PDT 24
Finished Jul 11 05:50:57 PM PDT 24
Peak memory 201292 kb
Host smart-656ae6c1-ce33-483e-acaa-f88bca1bf50b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190133749 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.190133749
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3357736321
Short name T161
Test name
Test status
Simulation time 116020871937 ps
CPU time 306.73 seconds
Started Jul 11 05:46:22 PM PDT 24
Finished Jul 11 05:51:32 PM PDT 24
Peak memory 215020 kb
Host smart-e0a0aa34-b9e6-42d6-8746-2ca6103d103d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357736321 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3357736321
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1579097988
Short name T93
Test name
Test status
Simulation time 132357485540 ps
CPU time 35.34 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:37 PM PDT 24
Peak memory 191944 kb
Host smart-b2c868de-11d4-4118-9fe5-dfe0dd85574b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579097988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1579097988
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.593071186
Short name T58
Test name
Test status
Simulation time 168470431025 ps
CPU time 49.16 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:48:05 PM PDT 24
Peak memory 198320 kb
Host smart-ee5925b2-c95f-464c-8e0e-744cca5cdb57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593071186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.593071186
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2509667446
Short name T9
Test name
Test status
Simulation time 334477471856 ps
CPU time 124.99 seconds
Started Jul 11 05:45:48 PM PDT 24
Finished Jul 11 05:47:55 PM PDT 24
Peak memory 193016 kb
Host smart-5ad364d1-2e1c-4803-bf3f-6c937bdc22f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509667446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2509667446
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2466334872
Short name T143
Test name
Test status
Simulation time 18589040060 ps
CPU time 153.32 seconds
Started Jul 11 05:46:23 PM PDT 24
Finished Jul 11 05:49:00 PM PDT 24
Peak memory 214760 kb
Host smart-63e33e99-30ee-43a9-9ac7-912f494d4ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466334872 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2466334872
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1255833528
Short name T95
Test name
Test status
Simulation time 325343590840 ps
CPU time 482.63 seconds
Started Jul 11 05:46:46 PM PDT 24
Finished Jul 11 05:54:51 PM PDT 24
Peak memory 206736 kb
Host smart-c817f488-99fb-42a5-a842-2a868a16d038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255833528 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1255833528
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1779050139
Short name T130
Test name
Test status
Simulation time 821788315206 ps
CPU time 572.14 seconds
Started Jul 11 05:45:51 PM PDT 24
Finished Jul 11 05:55:26 PM PDT 24
Peak memory 198316 kb
Host smart-de3a06cc-29cb-4bab-86b2-19acf6dddd3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779050139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1779050139
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3513087615
Short name T139
Test name
Test status
Simulation time 105482450249 ps
CPU time 31.3 seconds
Started Jul 11 05:45:53 PM PDT 24
Finished Jul 11 05:46:28 PM PDT 24
Peak memory 198416 kb
Host smart-17fd449b-7b78-49f2-b557-ef0491634f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513087615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3513087615
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3799037375
Short name T28
Test name
Test status
Simulation time 18795327215 ps
CPU time 148.88 seconds
Started Jul 11 05:45:59 PM PDT 24
Finished Jul 11 05:48:31 PM PDT 24
Peak memory 198828 kb
Host smart-3c9d42e2-84dd-4240-93a5-82846553f396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799037375 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3799037375
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3890438528
Short name T118
Test name
Test status
Simulation time 172095557526 ps
CPU time 60.89 seconds
Started Jul 11 05:45:59 PM PDT 24
Finished Jul 11 05:47:03 PM PDT 24
Peak memory 198340 kb
Host smart-5772a3f7-ca0a-4c6e-b089-c6284c24504e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890438528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3890438528
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.489051532
Short name T102
Test name
Test status
Simulation time 71668561597 ps
CPU time 54.17 seconds
Started Jul 11 05:46:24 PM PDT 24
Finished Jul 11 05:47:23 PM PDT 24
Peak memory 198320 kb
Host smart-5c8d44c7-e970-4204-8ed8-c3e924f0a7d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489051532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.489051532
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2490724824
Short name T119
Test name
Test status
Simulation time 86156029910 ps
CPU time 124.56 seconds
Started Jul 11 05:46:51 PM PDT 24
Finished Jul 11 05:48:59 PM PDT 24
Peak memory 192940 kb
Host smart-8efcd77b-7e1f-476f-a926-9fc4f68795c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490724824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2490724824
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3174464245
Short name T107
Test name
Test status
Simulation time 87496170912 ps
CPU time 108.03 seconds
Started Jul 11 05:46:01 PM PDT 24
Finished Jul 11 05:47:52 PM PDT 24
Peak memory 198512 kb
Host smart-033fb3c2-f060-4d92-a442-24c83b7ec450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174464245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3174464245
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2273717804
Short name T125
Test name
Test status
Simulation time 59204424294 ps
CPU time 16.95 seconds
Started Jul 11 05:46:08 PM PDT 24
Finished Jul 11 05:46:27 PM PDT 24
Peak memory 198300 kb
Host smart-eab9d7dd-7e57-4dfa-a36d-8c0a9bbea245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273717804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2273717804
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2969015361
Short name T74
Test name
Test status
Simulation time 50612812665 ps
CPU time 251.6 seconds
Started Jul 11 05:46:23 PM PDT 24
Finished Jul 11 05:50:38 PM PDT 24
Peak memory 207288 kb
Host smart-7ffea075-9357-42d9-9eee-367e038347aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969015361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2969015361
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.569572906
Short name T138
Test name
Test status
Simulation time 286926223492 ps
CPU time 424.33 seconds
Started Jul 11 05:45:54 PM PDT 24
Finished Jul 11 05:53:01 PM PDT 24
Peak memory 198336 kb
Host smart-2dbf115a-42f4-45e3-8e0a-1350e302fb30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569572906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.569572906
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2304511484
Short name T97
Test name
Test status
Simulation time 28973237608 ps
CPU time 122.2 seconds
Started Jul 11 05:46:40 PM PDT 24
Finished Jul 11 05:48:44 PM PDT 24
Peak memory 198624 kb
Host smart-97028053-50c1-4d5c-8cc6-9344c5e51acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304511484 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2304511484
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3533957841
Short name T127
Test name
Test status
Simulation time 27933159209 ps
CPU time 229.64 seconds
Started Jul 11 05:46:14 PM PDT 24
Finished Jul 11 05:50:06 PM PDT 24
Peak memory 212904 kb
Host smart-0ea35977-ef30-4c02-ac69-7660191be8c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533957841 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3533957841
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3495160386
Short name T100
Test name
Test status
Simulation time 302018861275 ps
CPU time 449.64 seconds
Started Jul 11 05:46:26 PM PDT 24
Finished Jul 11 05:53:59 PM PDT 24
Peak memory 198348 kb
Host smart-a97da476-9265-44be-a38b-d09e8f459559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495160386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3495160386
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.671346783
Short name T43
Test name
Test status
Simulation time 685660299094 ps
CPU time 799.32 seconds
Started Jul 11 05:46:07 PM PDT 24
Finished Jul 11 05:59:28 PM PDT 24
Peak memory 214636 kb
Host smart-77243067-d4c5-47b6-a0d7-ce72b4f8c619
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671346783 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.671346783
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1778862490
Short name T131
Test name
Test status
Simulation time 139174256374 ps
CPU time 34.17 seconds
Started Jul 11 05:45:49 PM PDT 24
Finished Jul 11 05:46:26 PM PDT 24
Peak memory 198508 kb
Host smart-530aaf96-854d-41b7-8775-428f85d57794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778862490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1778862490
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1438696534
Short name T162
Test name
Test status
Simulation time 501857153133 ps
CPU time 178.98 seconds
Started Jul 11 05:46:22 PM PDT 24
Finished Jul 11 05:49:24 PM PDT 24
Peak memory 192756 kb
Host smart-18255dc8-8958-4379-8f80-729bf84608f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438696534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1438696534
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.101607983
Short name T123
Test name
Test status
Simulation time 49840436664 ps
CPU time 70.56 seconds
Started Jul 11 05:46:37 PM PDT 24
Finished Jul 11 05:47:49 PM PDT 24
Peak memory 193076 kb
Host smart-38cb3e89-47eb-4d1d-aa85-9718eb797b55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101607983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.101607983
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.13470481
Short name T124
Test name
Test status
Simulation time 271208316667 ps
CPU time 360.56 seconds
Started Jul 11 05:46:38 PM PDT 24
Finished Jul 11 05:52:40 PM PDT 24
Peak memory 191976 kb
Host smart-bcc26e48-0a88-4041-8696-b536003500ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13470481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_al
l.13470481
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.249538421
Short name T1
Test name
Test status
Simulation time 75095277190 ps
CPU time 579.28 seconds
Started Jul 11 05:46:30 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 212664 kb
Host smart-a03359f2-aef6-4be1-a434-19086e761f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249538421 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.249538421
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1586927321
Short name T5
Test name
Test status
Simulation time 304557799570 ps
CPU time 370.42 seconds
Started Jul 11 05:46:43 PM PDT 24
Finished Jul 11 05:52:55 PM PDT 24
Peak memory 192484 kb
Host smart-4547a17b-9aec-403c-bfbe-3e5cbca9a548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586927321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1586927321
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1901696167
Short name T146
Test name
Test status
Simulation time 531648429 ps
CPU time 1.33 seconds
Started Jul 11 05:46:21 PM PDT 24
Finished Jul 11 05:46:26 PM PDT 24
Peak memory 196692 kb
Host smart-3762833d-ee72-473a-ae70-587cc4285fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901696167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1901696167
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.638573622
Short name T148
Test name
Test status
Simulation time 273647201725 ps
CPU time 87.6 seconds
Started Jul 11 05:46:26 PM PDT 24
Finished Jul 11 05:47:57 PM PDT 24
Peak memory 198212 kb
Host smart-6aab166c-1e71-4e24-bf18-7f71c03e8c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638573622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.638573622
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.105901193
Short name T112
Test name
Test status
Simulation time 312116827572 ps
CPU time 476.75 seconds
Started Jul 11 05:46:23 PM PDT 24
Finished Jul 11 05:54:23 PM PDT 24
Peak memory 191964 kb
Host smart-61ff1b14-26e2-40e0-b320-ad89346f8041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105901193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.105901193
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2561456350
Short name T122
Test name
Test status
Simulation time 464173916 ps
CPU time 0.73 seconds
Started Jul 11 05:46:34 PM PDT 24
Finished Jul 11 05:46:36 PM PDT 24
Peak memory 196772 kb
Host smart-cbddb8af-3758-41c1-9f75-773cc4e8a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561456350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2561456350
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.786718828
Short name T163
Test name
Test status
Simulation time 96300835074 ps
CPU time 42.13 seconds
Started Jul 11 05:46:05 PM PDT 24
Finished Jul 11 05:46:50 PM PDT 24
Peak memory 192460 kb
Host smart-ff866b33-3718-412f-bc63-33179be80f9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786718828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.786718828
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2474642490
Short name T116
Test name
Test status
Simulation time 92007652021 ps
CPU time 69.61 seconds
Started Jul 11 05:46:06 PM PDT 24
Finished Jul 11 05:47:18 PM PDT 24
Peak memory 184260 kb
Host smart-791fd3fb-9622-4e89-9e77-403388319170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474642490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2474642490
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1236467407
Short name T91
Test name
Test status
Simulation time 61667478194 ps
CPU time 23.53 seconds
Started Jul 11 05:46:09 PM PDT 24
Finished Jul 11 05:46:34 PM PDT 24
Peak memory 192748 kb
Host smart-94ae4e05-781e-4bb2-ac7e-cd0739fe8ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236467407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1236467407
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.373115836
Short name T76
Test name
Test status
Simulation time 401714315801 ps
CPU time 980.78 seconds
Started Jul 11 05:45:58 PM PDT 24
Finished Jul 11 06:02:22 PM PDT 24
Peak memory 215028 kb
Host smart-7851ab89-0dc6-45b2-a9b1-655969ef8aad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373115836 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.373115836
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.292162392
Short name T73
Test name
Test status
Simulation time 76638902715 ps
CPU time 542.83 seconds
Started Jul 11 05:46:30 PM PDT 24
Finished Jul 11 05:55:35 PM PDT 24
Peak memory 211560 kb
Host smart-c46c2353-a512-421c-9755-5153f4a449b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292162392 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.292162392
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2149528292
Short name T147
Test name
Test status
Simulation time 160841834287 ps
CPU time 453.76 seconds
Started Jul 11 05:46:36 PM PDT 24
Finished Jul 11 05:54:11 PM PDT 24
Peak memory 203712 kb
Host smart-fdf242e6-7f0d-4a71-b76f-e17c661c2418
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149528292 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2149528292
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2837066855
Short name T128
Test name
Test status
Simulation time 184837901274 ps
CPU time 268.75 seconds
Started Jul 11 05:45:54 PM PDT 24
Finished Jul 11 05:50:25 PM PDT 24
Peak memory 198336 kb
Host smart-f862ab34-2951-4bb9-a79d-afd6f0c25282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837066855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2837066855
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2302829815
Short name T101
Test name
Test status
Simulation time 547086563 ps
CPU time 0.65 seconds
Started Jul 11 05:46:08 PM PDT 24
Finished Jul 11 05:46:10 PM PDT 24
Peak memory 196752 kb
Host smart-09e3ca08-1b31-4aae-a690-13b6f558c700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302829815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2302829815
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.492252672
Short name T59
Test name
Test status
Simulation time 88974521572 ps
CPU time 33.4 seconds
Started Jul 11 05:46:11 PM PDT 24
Finished Jul 11 05:46:46 PM PDT 24
Peak memory 193032 kb
Host smart-69d0c4ac-ec06-47cd-9ad9-0824b1261bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492252672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.492252672
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.77276989
Short name T96
Test name
Test status
Simulation time 125179491142 ps
CPU time 53.87 seconds
Started Jul 11 05:46:18 PM PDT 24
Finished Jul 11 05:47:14 PM PDT 24
Peak memory 184744 kb
Host smart-5bcb6682-8c3b-4ad1-8ef7-4a10a57043c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77276989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_al
l.77276989
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.463992545
Short name T121
Test name
Test status
Simulation time 554003989 ps
CPU time 0.95 seconds
Started Jul 11 05:46:16 PM PDT 24
Finished Jul 11 05:46:19 PM PDT 24
Peak memory 196660 kb
Host smart-a36df55f-b31a-4f3a-bfa8-4cae35c1496e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463992545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.463992545
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.4089499019
Short name T141
Test name
Test status
Simulation time 369698552048 ps
CPU time 99.13 seconds
Started Jul 11 05:46:19 PM PDT 24
Finished Jul 11 05:48:00 PM PDT 24
Peak memory 191988 kb
Host smart-f05bd086-96d8-41a1-bb40-588e0bfb988a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089499019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.4089499019
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.147147941
Short name T115
Test name
Test status
Simulation time 342170990 ps
CPU time 0.85 seconds
Started Jul 11 05:46:37 PM PDT 24
Finished Jul 11 05:46:39 PM PDT 24
Peak memory 196800 kb
Host smart-66b320eb-dcec-46a1-a095-c71ad6949025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147147941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.147147941
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1744068122
Short name T150
Test name
Test status
Simulation time 268879872696 ps
CPU time 85.97 seconds
Started Jul 11 05:46:59 PM PDT 24
Finished Jul 11 05:48:28 PM PDT 24
Peak memory 191944 kb
Host smart-b836290b-5dac-4157-a6b5-81c3cb2d5aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744068122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1744068122
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2443875780
Short name T170
Test name
Test status
Simulation time 149056475393 ps
CPU time 275.96 seconds
Started Jul 11 05:46:08 PM PDT 24
Finished Jul 11 05:50:46 PM PDT 24
Peak memory 206776 kb
Host smart-fe74e2ba-1779-4bae-a23d-5b41910ec9b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443875780 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2443875780
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3404333681
Short name T84
Test name
Test status
Simulation time 45003062476 ps
CPU time 168.07 seconds
Started Jul 11 05:46:04 PM PDT 24
Finished Jul 11 05:48:54 PM PDT 24
Peak memory 207004 kb
Host smart-dd01ab58-ce67-4d95-b16e-da3092dbb3a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404333681 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3404333681
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1199129069
Short name T6
Test name
Test status
Simulation time 480683041 ps
CPU time 0.77 seconds
Started Jul 11 05:46:25 PM PDT 24
Finished Jul 11 05:46:29 PM PDT 24
Peak memory 196744 kb
Host smart-6dea1d85-1337-41ae-bc4f-efdae1559f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199129069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1199129069
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2512775852
Short name T30
Test name
Test status
Simulation time 27205603422 ps
CPU time 209.13 seconds
Started Jul 11 05:46:19 PM PDT 24
Finished Jul 11 05:49:50 PM PDT 24
Peak memory 214856 kb
Host smart-cb7965be-eb1b-441f-9a44-bcb8b31c093d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512775852 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2512775852
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3172269179
Short name T104
Test name
Test status
Simulation time 592311604 ps
CPU time 1.49 seconds
Started Jul 11 05:45:50 PM PDT 24
Finished Jul 11 05:45:54 PM PDT 24
Peak memory 196764 kb
Host smart-8c894406-8bbd-45f1-b59a-fee0ded725ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172269179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3172269179
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4276655133
Short name T149
Test name
Test status
Simulation time 61409149720 ps
CPU time 332.11 seconds
Started Jul 11 05:46:59 PM PDT 24
Finished Jul 11 05:52:34 PM PDT 24
Peak memory 200664 kb
Host smart-e41c798e-2724-40e1-a27f-e20e0b4fa393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276655133 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4276655133
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2240517566
Short name T145
Test name
Test status
Simulation time 385246892 ps
CPU time 0.73 seconds
Started Jul 11 05:46:39 PM PDT 24
Finished Jul 11 05:46:41 PM PDT 24
Peak memory 196736 kb
Host smart-aad5dcf2-d5ec-4da6-a912-a84cda8019be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240517566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2240517566
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2727769412
Short name T137
Test name
Test status
Simulation time 433005293 ps
CPU time 0.88 seconds
Started Jul 11 05:46:43 PM PDT 24
Finished Jul 11 05:46:45 PM PDT 24
Peak memory 196624 kb
Host smart-65e7e000-465a-42b3-8243-91ce7d996819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727769412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2727769412
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2142565771
Short name T142
Test name
Test status
Simulation time 414601098 ps
CPU time 1.01 seconds
Started Jul 11 05:46:42 PM PDT 24
Finished Jul 11 05:46:44 PM PDT 24
Peak memory 196624 kb
Host smart-388cd474-dd85-4d1f-aad5-78b0f07efd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142565771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2142565771
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2803286679
Short name T60
Test name
Test status
Simulation time 77451619148 ps
CPU time 16.82 seconds
Started Jul 11 05:46:48 PM PDT 24
Finished Jul 11 05:47:07 PM PDT 24
Peak memory 193076 kb
Host smart-1863d9f9-31d7-42c7-b76b-2ad0cf6af882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803286679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2803286679
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2800505750
Short name T114
Test name
Test status
Simulation time 455184348 ps
CPU time 1.3 seconds
Started Jul 11 05:45:58 PM PDT 24
Finished Jul 11 05:46:02 PM PDT 24
Peak memory 196840 kb
Host smart-5f388747-1edd-4605-b3a6-f98b049d84e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800505750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2800505750
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.873377614
Short name T19
Test name
Test status
Simulation time 419769022 ps
CPU time 1.12 seconds
Started Jul 11 05:46:06 PM PDT 24
Finished Jul 11 05:46:10 PM PDT 24
Peak memory 196900 kb
Host smart-f2e6dfc8-bcaf-4911-a37e-3eba4bb5bc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873377614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.873377614
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1778116141
Short name T12
Test name
Test status
Simulation time 65536175110 ps
CPU time 10.28 seconds
Started Jul 11 05:46:15 PM PDT 24
Finished Jul 11 05:46:28 PM PDT 24
Peak memory 191956 kb
Host smart-f840bd5e-ed87-4c43-a885-66bbaf824b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778116141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1778116141
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3149788050
Short name T136
Test name
Test status
Simulation time 480259906 ps
CPU time 0.76 seconds
Started Jul 11 05:46:14 PM PDT 24
Finished Jul 11 05:46:17 PM PDT 24
Peak memory 196736 kb
Host smart-69446957-ede1-49c6-aa6a-7fc31d8b5fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149788050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3149788050
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.718384264
Short name T135
Test name
Test status
Simulation time 467703354002 ps
CPU time 45.95 seconds
Started Jul 11 05:46:34 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 193072 kb
Host smart-98afc6fa-1353-4938-a9e3-273609bb4e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718384264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.718384264
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.187824484
Short name T144
Test name
Test status
Simulation time 481518147 ps
CPU time 0.94 seconds
Started Jul 11 05:46:27 PM PDT 24
Finished Jul 11 05:46:32 PM PDT 24
Peak memory 196716 kb
Host smart-17d971be-d6bb-4307-a1c7-c507ed3ae5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187824484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.187824484
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.835049604
Short name T36
Test name
Test status
Simulation time 367786076 ps
CPU time 1.05 seconds
Started Jul 11 05:46:26 PM PDT 24
Finished Jul 11 05:46:31 PM PDT 24
Peak memory 196764 kb
Host smart-2968329c-8ac1-4d65-a410-4c477d0a99b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835049604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.835049604
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3642892161
Short name T31
Test name
Test status
Simulation time 77755311131 ps
CPU time 216.33 seconds
Started Jul 11 05:46:59 PM PDT 24
Finished Jul 11 05:50:38 PM PDT 24
Peak memory 198708 kb
Host smart-e13eb2eb-24b7-405e-8d18-49f17e92f232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642892161 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3642892161
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3477167572
Short name T33
Test name
Test status
Simulation time 19371462783 ps
CPU time 128.04 seconds
Started Jul 11 05:46:48 PM PDT 24
Finished Jul 11 05:48:58 PM PDT 24
Peak memory 206836 kb
Host smart-0e69a4e3-6feb-4be5-84d3-8171aa3a432e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477167572 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3477167572
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.841204182
Short name T173
Test name
Test status
Simulation time 211210545870 ps
CPU time 26.7 seconds
Started Jul 11 05:46:01 PM PDT 24
Finished Jul 11 05:46:30 PM PDT 24
Peak memory 192492 kb
Host smart-33cfb792-d41b-4903-95f3-c15fb8b68dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841204182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.841204182
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2122867658
Short name T86
Test name
Test status
Simulation time 489539414 ps
CPU time 0.96 seconds
Started Jul 11 05:46:27 PM PDT 24
Finished Jul 11 05:46:32 PM PDT 24
Peak memory 196720 kb
Host smart-353743cf-892a-4f0d-98b1-6a2efdde3453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122867658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2122867658
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4271607713
Short name T159
Test name
Test status
Simulation time 78727588017 ps
CPU time 186.25 seconds
Started Jul 11 05:46:03 PM PDT 24
Finished Jul 11 05:49:12 PM PDT 24
Peak memory 199204 kb
Host smart-35577455-8286-422c-ad4b-07ca257648d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271607713 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4271607713
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2000588357
Short name T172
Test name
Test status
Simulation time 450030769 ps
CPU time 0.88 seconds
Started Jul 11 05:46:13 PM PDT 24
Finished Jul 11 05:46:15 PM PDT 24
Peak memory 196648 kb
Host smart-2d7a2cef-71d3-4258-9cdf-99b4380c648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000588357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2000588357
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4057928998
Short name T42
Test name
Test status
Simulation time 140416818848 ps
CPU time 197.8 seconds
Started Jul 11 05:46:49 PM PDT 24
Finished Jul 11 05:50:10 PM PDT 24
Peak memory 193008 kb
Host smart-10510a58-8e23-409c-aa29-7e02358295bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057928998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4057928998
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1999500534
Short name T169
Test name
Test status
Simulation time 368842703 ps
CPU time 0.74 seconds
Started Jul 11 05:46:42 PM PDT 24
Finished Jul 11 05:46:44 PM PDT 24
Peak memory 196708 kb
Host smart-5b1786ef-189b-4e46-b01d-603b4e951ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999500534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1999500534
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1505513065
Short name T151
Test name
Test status
Simulation time 99281849785 ps
CPU time 226.28 seconds
Started Jul 11 05:46:42 PM PDT 24
Finished Jul 11 05:50:30 PM PDT 24
Peak memory 208752 kb
Host smart-847c6a24-e58e-4fcf-83ee-653a3b80496e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505513065 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1505513065
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2264033761
Short name T181
Test name
Test status
Simulation time 453797999 ps
CPU time 0.75 seconds
Started Jul 11 05:46:00 PM PDT 24
Finished Jul 11 05:46:04 PM PDT 24
Peak memory 196792 kb
Host smart-29fb9552-9ee8-45df-b8c6-e155ec6dc267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264033761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2264033761
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3707635191
Short name T39
Test name
Test status
Simulation time 445651240 ps
CPU time 0.91 seconds
Started Jul 11 05:45:54 PM PDT 24
Finished Jul 11 05:45:58 PM PDT 24
Peak memory 196672 kb
Host smart-7799a2fd-2a74-41fc-92ff-bccb5241bfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707635191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3707635191
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2211916975
Short name T186
Test name
Test status
Simulation time 423010110 ps
CPU time 1.2 seconds
Started Jul 11 05:45:58 PM PDT 24
Finished Jul 11 05:46:02 PM PDT 24
Peak memory 196800 kb
Host smart-ff0b178d-64c6-40d3-8330-14f926d74615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211916975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2211916975
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2134454595
Short name T164
Test name
Test status
Simulation time 97225032624 ps
CPU time 34.8 seconds
Started Jul 11 05:45:58 PM PDT 24
Finished Jul 11 05:46:36 PM PDT 24
Peak memory 192156 kb
Host smart-cdafdd9c-c5dc-4590-be6e-0a4cdc470639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134454595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2134454595
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2211595092
Short name T35
Test name
Test status
Simulation time 36031509419 ps
CPU time 24.65 seconds
Started Jul 11 05:46:06 PM PDT 24
Finished Jul 11 05:46:33 PM PDT 24
Peak memory 192572 kb
Host smart-e3dfd8cd-e684-4927-9f2c-304e8fd1e8d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211595092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2211595092
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3757092696
Short name T92
Test name
Test status
Simulation time 359439769 ps
CPU time 0.82 seconds
Started Jul 11 05:46:15 PM PDT 24
Finished Jul 11 05:46:18 PM PDT 24
Peak memory 196736 kb
Host smart-e5f0115f-cf79-47a5-b1b8-d9a714f5282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757092696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3757092696
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1027417227
Short name T185
Test name
Test status
Simulation time 672573460 ps
CPU time 0.65 seconds
Started Jul 11 05:46:12 PM PDT 24
Finished Jul 11 05:46:14 PM PDT 24
Peak memory 196644 kb
Host smart-cbe410b2-e18b-4acd-a54c-bb770653a641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027417227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1027417227
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3496381074
Short name T174
Test name
Test status
Simulation time 411763021 ps
CPU time 1.15 seconds
Started Jul 11 05:46:50 PM PDT 24
Finished Jul 11 05:46:55 PM PDT 24
Peak memory 196632 kb
Host smart-821a6cc6-83ff-4e13-a2f2-a10f7faa7f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496381074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3496381074
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2077300671
Short name T158
Test name
Test status
Simulation time 584312872 ps
CPU time 1.02 seconds
Started Jul 11 05:46:26 PM PDT 24
Finished Jul 11 05:46:30 PM PDT 24
Peak memory 196680 kb
Host smart-4991ee9c-8a70-4805-88b3-d901bae2ec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077300671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2077300671
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1407290268
Short name T152
Test name
Test status
Simulation time 41010826743 ps
CPU time 417.46 seconds
Started Jul 11 05:46:40 PM PDT 24
Finished Jul 11 05:53:39 PM PDT 24
Peak memory 199952 kb
Host smart-8ff7771a-276b-441f-a11a-d350b5c77333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407290268 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1407290268
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2265979970
Short name T87
Test name
Test status
Simulation time 579698596 ps
CPU time 1.39 seconds
Started Jul 11 05:46:40 PM PDT 24
Finished Jul 11 05:46:43 PM PDT 24
Peak memory 196688 kb
Host smart-2e863e69-e0aa-47bb-bf33-fb883f1b7a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265979970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2265979970
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3789022978
Short name T171
Test name
Test status
Simulation time 605417252 ps
CPU time 0.79 seconds
Started Jul 11 05:46:44 PM PDT 24
Finished Jul 11 05:46:46 PM PDT 24
Peak memory 196756 kb
Host smart-4b52f0b2-5ef9-4785-b08a-a6aa72dd7719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789022978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3789022978
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2074197686
Short name T176
Test name
Test status
Simulation time 463283620 ps
CPU time 0.75 seconds
Started Jul 11 05:45:51 PM PDT 24
Finished Jul 11 05:45:54 PM PDT 24
Peak memory 196812 kb
Host smart-75d028e5-1359-4277-93cc-a9c2f02a9625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074197686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2074197686
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1447414872
Short name T183
Test name
Test status
Simulation time 580709874 ps
CPU time 1.41 seconds
Started Jul 11 05:46:03 PM PDT 24
Finished Jul 11 05:46:07 PM PDT 24
Peak memory 196672 kb
Host smart-68ed78d8-6c7a-485a-bd6b-01988af34c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447414872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1447414872
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.316800260
Short name T165
Test name
Test status
Simulation time 454389041 ps
CPU time 1.23 seconds
Started Jul 11 05:46:04 PM PDT 24
Finished Jul 11 05:46:08 PM PDT 24
Peak memory 196696 kb
Host smart-e52a0728-8ce8-438d-a69e-82bcece1744f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316800260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.316800260
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2402178617
Short name T157
Test name
Test status
Simulation time 462571278 ps
CPU time 0.67 seconds
Started Jul 11 05:46:22 PM PDT 24
Finished Jul 11 05:46:26 PM PDT 24
Peak memory 196680 kb
Host smart-8812e003-90bd-404c-a542-26131ef8928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402178617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2402178617
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1838437423
Short name T29
Test name
Test status
Simulation time 15971688117 ps
CPU time 167.9 seconds
Started Jul 11 05:45:58 PM PDT 24
Finished Jul 11 05:48:49 PM PDT 24
Peak memory 207080 kb
Host smart-0cd6fba0-3928-4d8a-8462-1552e5f65d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838437423 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1838437423
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2377208380
Short name T156
Test name
Test status
Simulation time 533653995 ps
CPU time 1.39 seconds
Started Jul 11 05:46:11 PM PDT 24
Finished Jul 11 05:46:14 PM PDT 24
Peak memory 196648 kb
Host smart-7485d138-9919-44f7-a40e-6fc3f160752e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377208380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2377208380
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1434386319
Short name T166
Test name
Test status
Simulation time 536599169 ps
CPU time 1.5 seconds
Started Jul 11 05:46:09 PM PDT 24
Finished Jul 11 05:46:12 PM PDT 24
Peak memory 196772 kb
Host smart-2ab8e704-7922-4b32-ab4f-f9b42af3bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434386319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1434386319
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.4205739928
Short name T180
Test name
Test status
Simulation time 594605771 ps
CPU time 0.73 seconds
Started Jul 11 05:46:16 PM PDT 24
Finished Jul 11 05:46:19 PM PDT 24
Peak memory 196736 kb
Host smart-882c54c6-7702-4ab2-ad8e-41f725c73b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205739928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.4205739928
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3843060321
Short name T184
Test name
Test status
Simulation time 450053613 ps
CPU time 1.22 seconds
Started Jul 11 05:46:10 PM PDT 24
Finished Jul 11 05:46:12 PM PDT 24
Peak memory 196776 kb
Host smart-9b65d3f0-ec87-49b2-a1e8-bacbdd80a06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843060321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3843060321
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1217352661
Short name T168
Test name
Test status
Simulation time 517844568 ps
CPU time 0.78 seconds
Started Jul 11 05:46:35 PM PDT 24
Finished Jul 11 05:46:37 PM PDT 24
Peak memory 196804 kb
Host smart-c0831326-1806-4cf6-a757-3b92dce6af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217352661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1217352661
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2713982771
Short name T178
Test name
Test status
Simulation time 598805088 ps
CPU time 0.78 seconds
Started Jul 11 05:46:24 PM PDT 24
Finished Jul 11 05:46:27 PM PDT 24
Peak memory 196808 kb
Host smart-f94f5881-aa7a-4b25-877c-86062b7d4a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713982771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2713982771
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3471796668
Short name T182
Test name
Test status
Simulation time 487307553 ps
CPU time 1.11 seconds
Started Jul 11 05:46:02 PM PDT 24
Finished Jul 11 05:46:06 PM PDT 24
Peak memory 196780 kb
Host smart-b3644cc5-cc3b-46c7-acf8-be25c663595d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471796668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3471796668
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.837762723
Short name T160
Test name
Test status
Simulation time 391057141 ps
CPU time 0.72 seconds
Started Jul 11 05:46:39 PM PDT 24
Finished Jul 11 05:46:41 PM PDT 24
Peak memory 196796 kb
Host smart-e8013166-24b4-4ba5-b412-16553b4c22da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837762723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.837762723
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1997476818
Short name T133
Test name
Test status
Simulation time 445062796 ps
CPU time 0.75 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:47:17 PM PDT 24
Peak memory 196812 kb
Host smart-d9f527c1-64ea-4f0b-a100-e4aebe00f90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997476818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1997476818
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2735888683
Short name T153
Test name
Test status
Simulation time 335573479360 ps
CPU time 445 seconds
Started Jul 11 05:46:41 PM PDT 24
Finished Jul 11 05:54:08 PM PDT 24
Peak memory 198516 kb
Host smart-c067ef49-3cb5-485a-ae66-8be7fddaa71e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735888683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2735888683
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3486775467
Short name T188
Test name
Test status
Simulation time 398370704 ps
CPU time 1.17 seconds
Started Jul 11 05:46:03 PM PDT 24
Finished Jul 11 05:46:06 PM PDT 24
Peak memory 196604 kb
Host smart-cc21203a-0ff1-4dcc-8a2a-cada5a358e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486775467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3486775467
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3596037037
Short name T189
Test name
Test status
Simulation time 471664580 ps
CPU time 1.35 seconds
Started Jul 11 05:45:58 PM PDT 24
Finished Jul 11 05:46:02 PM PDT 24
Peak memory 196748 kb
Host smart-2f1dc721-0a34-42d8-b8f3-9314d209cc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596037037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3596037037
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2076070553
Short name T322
Test name
Test status
Simulation time 369796809 ps
CPU time 1.17 seconds
Started Jul 11 05:46:46 PM PDT 24
Finished Jul 11 05:46:49 PM PDT 24
Peak memory 193264 kb
Host smart-7cecec76-33be-4d70-8f9f-d11264e54294
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076070553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2076070553
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.630368040
Short name T45
Test name
Test status
Simulation time 12823469489 ps
CPU time 32.46 seconds
Started Jul 11 05:46:53 PM PDT 24
Finished Jul 11 05:47:28 PM PDT 24
Peak memory 192260 kb
Host smart-c8d0ff83-aedc-4ce2-a556-c727c0b90f44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630368040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.630368040
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1587981853
Short name T348
Test name
Test status
Simulation time 851236930 ps
CPU time 0.71 seconds
Started Jul 11 05:46:40 PM PDT 24
Finished Jul 11 05:46:42 PM PDT 24
Peak memory 183836 kb
Host smart-3cc19446-fe73-436e-bca8-f653faaa81c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587981853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1587981853
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3588975332
Short name T381
Test name
Test status
Simulation time 439682692 ps
CPU time 0.84 seconds
Started Jul 11 05:46:46 PM PDT 24
Finished Jul 11 05:46:48 PM PDT 24
Peak memory 195928 kb
Host smart-841d7df3-47cc-42af-9fef-4d75d9177ed4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588975332 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3588975332
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4151835293
Short name T311
Test name
Test status
Simulation time 375088966 ps
CPU time 0.68 seconds
Started Jul 11 05:46:39 PM PDT 24
Finished Jul 11 05:46:42 PM PDT 24
Peak memory 192104 kb
Host smart-46520076-cc1d-462e-b1c8-9a5a03720e35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151835293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4151835293
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1800845849
Short name T347
Test name
Test status
Simulation time 352407074 ps
CPU time 0.98 seconds
Started Jul 11 05:46:39 PM PDT 24
Finished Jul 11 05:46:41 PM PDT 24
Peak memory 192988 kb
Host smart-244cbf03-9780-470d-8745-18bd1c056017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800845849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1800845849
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1124995510
Short name T350
Test name
Test status
Simulation time 489306485 ps
CPU time 0.88 seconds
Started Jul 11 05:46:48 PM PDT 24
Finished Jul 11 05:46:50 PM PDT 24
Peak memory 183656 kb
Host smart-6f8a71e4-0f4e-427f-9db1-e68b79fc42fa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124995510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1124995510
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1828983292
Short name T424
Test name
Test status
Simulation time 486981379 ps
CPU time 0.88 seconds
Started Jul 11 05:46:51 PM PDT 24
Finished Jul 11 05:46:55 PM PDT 24
Peak memory 183752 kb
Host smart-931c30e8-6538-47e9-b90c-82aa7733593d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828983292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1828983292
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3190321024
Short name T423
Test name
Test status
Simulation time 2272973810 ps
CPU time 0.97 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:47:00 PM PDT 24
Peak memory 183880 kb
Host smart-873c0585-4c10-4b7c-87cd-40f9d4710dbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190321024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3190321024
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.637593045
Short name T413
Test name
Test status
Simulation time 358899790 ps
CPU time 2.1 seconds
Started Jul 11 05:46:40 PM PDT 24
Finished Jul 11 05:46:44 PM PDT 24
Peak memory 198672 kb
Host smart-8772ddc4-5363-4cbf-b036-b2e5c1a93bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637593045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.637593045
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.38241000
Short name T54
Test name
Test status
Simulation time 593016168 ps
CPU time 1.5 seconds
Started Jul 11 05:46:57 PM PDT 24
Finished Jul 11 05:47:01 PM PDT 24
Peak memory 191948 kb
Host smart-dd2e91a5-8d75-46bd-b64f-4db74653a2bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38241000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_ali
asing.38241000
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3435673250
Short name T318
Test name
Test status
Simulation time 13879174385 ps
CPU time 16.89 seconds
Started Jul 11 05:46:55 PM PDT 24
Finished Jul 11 05:47:15 PM PDT 24
Peak memory 184084 kb
Host smart-28454c69-7336-497e-b2ff-d6f1268663b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435673250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3435673250
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1590020798
Short name T377
Test name
Test status
Simulation time 1168960092 ps
CPU time 0.96 seconds
Started Jul 11 05:46:48 PM PDT 24
Finished Jul 11 05:46:50 PM PDT 24
Peak memory 193300 kb
Host smart-4aa18502-1612-480e-9779-b582844426e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590020798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1590020798
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.13537235
Short name T391
Test name
Test status
Simulation time 607623629 ps
CPU time 1.55 seconds
Started Jul 11 05:46:47 PM PDT 24
Finished Jul 11 05:46:50 PM PDT 24
Peak memory 196672 kb
Host smart-2218c80b-65eb-4403-8874-112c3f0185e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537235 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.13537235
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3006711572
Short name T22
Test name
Test status
Simulation time 305555039 ps
CPU time 0.67 seconds
Started Jul 11 05:46:47 PM PDT 24
Finished Jul 11 05:46:50 PM PDT 24
Peak memory 192096 kb
Host smart-333ed37d-54b8-437f-b3fc-762158cf3df3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006711572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3006711572
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2360623941
Short name T358
Test name
Test status
Simulation time 470713654 ps
CPU time 0.7 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:01 PM PDT 24
Peak memory 183776 kb
Host smart-fce8d6c3-bde7-40a1-8796-e777a363d211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360623941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2360623941
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3232536553
Short name T282
Test name
Test status
Simulation time 413680098 ps
CPU time 0.61 seconds
Started Jul 11 05:46:49 PM PDT 24
Finished Jul 11 05:46:53 PM PDT 24
Peak memory 183696 kb
Host smart-4993a920-5b84-47f3-9d8f-728c8057b839
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232536553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3232536553
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2861460875
Short name T301
Test name
Test status
Simulation time 304604893 ps
CPU time 0.9 seconds
Started Jul 11 05:46:55 PM PDT 24
Finished Jul 11 05:46:59 PM PDT 24
Peak memory 183756 kb
Host smart-329d0ff0-fbc7-48dd-9f95-1f8d15e23b2c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861460875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2861460875
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2825269078
Short name T411
Test name
Test status
Simulation time 1128680040 ps
CPU time 3.76 seconds
Started Jul 11 05:46:48 PM PDT 24
Finished Jul 11 05:46:53 PM PDT 24
Peak memory 193684 kb
Host smart-71c9471a-d584-48ae-ba73-1da862e8666b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825269078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2825269078
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.862012671
Short name T405
Test name
Test status
Simulation time 715144262 ps
CPU time 1.65 seconds
Started Jul 11 05:46:47 PM PDT 24
Finished Jul 11 05:46:51 PM PDT 24
Peak memory 198652 kb
Host smart-5707b6ac-c9e1-42b1-9c8f-61f64e0d6935
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862012671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.862012671
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2907548087
Short name T192
Test name
Test status
Simulation time 8238875788 ps
CPU time 14.1 seconds
Started Jul 11 05:46:45 PM PDT 24
Finished Jul 11 05:47:01 PM PDT 24
Peak memory 198524 kb
Host smart-a6528c8a-0288-4181-a2b8-a1a3ce59eab5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907548087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2907548087
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2716641275
Short name T312
Test name
Test status
Simulation time 752939056 ps
CPU time 1.27 seconds
Started Jul 11 05:47:08 PM PDT 24
Finished Jul 11 05:47:11 PM PDT 24
Peak memory 198656 kb
Host smart-c0e9ed3a-38bd-4318-8777-5208a76091d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716641275 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2716641275
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2100242884
Short name T314
Test name
Test status
Simulation time 541772473 ps
CPU time 0.82 seconds
Started Jul 11 05:47:06 PM PDT 24
Finished Jul 11 05:47:07 PM PDT 24
Peak memory 193048 kb
Host smart-f5e98ca5-081e-4a2b-9d3d-39e6f3ebd3ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100242884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2100242884
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2539468574
Short name T319
Test name
Test status
Simulation time 512491902 ps
CPU time 0.72 seconds
Started Jul 11 05:47:03 PM PDT 24
Finished Jul 11 05:47:05 PM PDT 24
Peak memory 183760 kb
Host smart-5a434c7a-371e-4845-9716-4a4fe3b91118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539468574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2539468574
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1760516933
Short name T72
Test name
Test status
Simulation time 2699017798 ps
CPU time 4.2 seconds
Started Jul 11 05:47:08 PM PDT 24
Finished Jul 11 05:47:14 PM PDT 24
Peak memory 195044 kb
Host smart-fe85ee33-862c-42ed-833c-8b8b8aa918ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760516933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1760516933
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.162506304
Short name T341
Test name
Test status
Simulation time 417518422 ps
CPU time 2.16 seconds
Started Jul 11 05:47:09 PM PDT 24
Finished Jul 11 05:47:13 PM PDT 24
Peak memory 198632 kb
Host smart-df6d19c6-d546-4595-b5cd-53c4517504d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162506304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.162506304
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.57007836
Short name T304
Test name
Test status
Simulation time 4619622596 ps
CPU time 7.04 seconds
Started Jul 11 05:47:01 PM PDT 24
Finished Jul 11 05:47:10 PM PDT 24
Peak memory 197864 kb
Host smart-03c35dc4-c5c9-473d-bf77-4831431c7403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57007836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_
intg_err.57007836
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2770828205
Short name T330
Test name
Test status
Simulation time 455775536 ps
CPU time 1.14 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:47:18 PM PDT 24
Peak memory 196128 kb
Host smart-36805f11-6185-40aa-92d8-92d38164e0ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770828205 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2770828205
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3584537753
Short name T387
Test name
Test status
Simulation time 433522624 ps
CPU time 1.35 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:47:18 PM PDT 24
Peak memory 193200 kb
Host smart-9424bb63-fc67-46ce-9c10-cf75f625b8e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584537753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3584537753
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3651435895
Short name T409
Test name
Test status
Simulation time 400553551 ps
CPU time 0.61 seconds
Started Jul 11 05:47:22 PM PDT 24
Finished Jul 11 05:47:25 PM PDT 24
Peak memory 183772 kb
Host smart-e9c9bfda-4357-4316-b5ea-55573844a05b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651435895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3651435895
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.226228058
Short name T360
Test name
Test status
Simulation time 971028482 ps
CPU time 1.06 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 193348 kb
Host smart-db726eaa-a7bc-4cd2-8ecb-e465a749dcc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226228058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.226228058
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1128382331
Short name T307
Test name
Test status
Simulation time 589069537 ps
CPU time 1.32 seconds
Started Jul 11 05:46:59 PM PDT 24
Finished Jul 11 05:47:04 PM PDT 24
Peak memory 198392 kb
Host smart-84871ba1-3dd7-463b-9bdd-3dc87433c475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128382331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1128382331
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1876293895
Short name T410
Test name
Test status
Simulation time 4284644806 ps
CPU time 3.41 seconds
Started Jul 11 05:47:02 PM PDT 24
Finished Jul 11 05:47:07 PM PDT 24
Peak memory 197584 kb
Host smart-c91c97de-da71-4eca-b42e-011d46e7db90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876293895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1876293895
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2135609038
Short name T329
Test name
Test status
Simulation time 462717955 ps
CPU time 1.29 seconds
Started Jul 11 05:47:11 PM PDT 24
Finished Jul 11 05:47:13 PM PDT 24
Peak memory 196420 kb
Host smart-b5b1e5bb-2639-4dac-b80c-c368d80e38e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135609038 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2135609038
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1085600139
Short name T300
Test name
Test status
Simulation time 371734653 ps
CPU time 0.69 seconds
Started Jul 11 05:47:24 PM PDT 24
Finished Jul 11 05:47:28 PM PDT 24
Peak memory 193036 kb
Host smart-15834427-f60e-43ca-8b81-8601e6b1aca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085600139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1085600139
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4020037808
Short name T298
Test name
Test status
Simulation time 427954398 ps
CPU time 0.68 seconds
Started Jul 11 05:47:15 PM PDT 24
Finished Jul 11 05:47:19 PM PDT 24
Peak memory 183444 kb
Host smart-f50e74b8-2243-44d8-bd61-26743c4907c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020037808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.4020037808
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3217316846
Short name T69
Test name
Test status
Simulation time 1160723018 ps
CPU time 1.42 seconds
Started Jul 11 05:47:13 PM PDT 24
Finished Jul 11 05:47:16 PM PDT 24
Peak memory 183828 kb
Host smart-647ecbdb-78fb-4372-a3db-5ce5a8eb412c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217316846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3217316846
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1122592099
Short name T302
Test name
Test status
Simulation time 285351822 ps
CPU time 1.72 seconds
Started Jul 11 05:47:10 PM PDT 24
Finished Jul 11 05:47:13 PM PDT 24
Peak memory 198688 kb
Host smart-3f179a80-94d7-47bc-8111-d1a5d5a1b1d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122592099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1122592099
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4261387995
Short name T407
Test name
Test status
Simulation time 4126084035 ps
CPU time 3.94 seconds
Started Jul 11 05:47:15 PM PDT 24
Finished Jul 11 05:47:21 PM PDT 24
Peak memory 198032 kb
Host smart-e4dbcc39-3b6c-46a0-a2aa-45c06922c058
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261387995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.4261387995
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2434255776
Short name T344
Test name
Test status
Simulation time 598983571 ps
CPU time 1.17 seconds
Started Jul 11 05:47:13 PM PDT 24
Finished Jul 11 05:47:16 PM PDT 24
Peak memory 196412 kb
Host smart-bd580408-4505-4785-a517-e81f27af4a64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434255776 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2434255776
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1324213840
Short name T327
Test name
Test status
Simulation time 493259010 ps
CPU time 0.74 seconds
Started Jul 11 05:47:13 PM PDT 24
Finished Jul 11 05:47:16 PM PDT 24
Peak memory 193260 kb
Host smart-e8274278-cbec-44c9-9bf5-d5b2c15e5eb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324213840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1324213840
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.380694219
Short name T362
Test name
Test status
Simulation time 311146494 ps
CPU time 0.64 seconds
Started Jul 11 05:47:25 PM PDT 24
Finished Jul 11 05:47:28 PM PDT 24
Peak memory 192992 kb
Host smart-1fb35ca7-4732-4452-8184-8659db90f3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380694219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.380694219
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3531032579
Short name T306
Test name
Test status
Simulation time 1943645600 ps
CPU time 1.59 seconds
Started Jul 11 05:47:13 PM PDT 24
Finished Jul 11 05:47:16 PM PDT 24
Peak memory 194068 kb
Host smart-bb5007e6-11a7-47d0-965e-d3bbad5ee999
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531032579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3531032579
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2970124547
Short name T333
Test name
Test status
Simulation time 482105894 ps
CPU time 2.67 seconds
Started Jul 11 05:47:11 PM PDT 24
Finished Jul 11 05:47:14 PM PDT 24
Peak memory 198664 kb
Host smart-09e0cff9-4498-4b8d-86b1-cc2c561b8420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970124547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2970124547
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4248941937
Short name T190
Test name
Test status
Simulation time 8714157012 ps
CPU time 3.12 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:47:19 PM PDT 24
Peak memory 198276 kb
Host smart-6e746c98-e6a3-4d2c-a472-c4d77a09bfe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248941937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.4248941937
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1906639762
Short name T310
Test name
Test status
Simulation time 353239870 ps
CPU time 1.19 seconds
Started Jul 11 05:47:17 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 196120 kb
Host smart-03f134c4-160e-4329-a13c-a5aa388f6be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906639762 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1906639762
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2747431867
Short name T401
Test name
Test status
Simulation time 516774056 ps
CPU time 0.84 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:47:17 PM PDT 24
Peak memory 183728 kb
Host smart-6e14ffe1-47f0-4de9-a05e-af6e38473f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747431867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2747431867
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2353390879
Short name T355
Test name
Test status
Simulation time 2702082022 ps
CPU time 2.79 seconds
Started Jul 11 05:47:13 PM PDT 24
Finished Jul 11 05:47:18 PM PDT 24
Peak memory 193984 kb
Host smart-9d10156a-92af-4e2a-868d-873f93eaea41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353390879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2353390879
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2407672284
Short name T323
Test name
Test status
Simulation time 709225235 ps
CPU time 1.79 seconds
Started Jul 11 05:47:10 PM PDT 24
Finished Jul 11 05:47:13 PM PDT 24
Peak memory 198676 kb
Host smart-af696a2e-ce61-49cf-ba06-50a612ad0f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407672284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2407672284
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3217207324
Short name T382
Test name
Test status
Simulation time 4264361180 ps
CPU time 6.23 seconds
Started Jul 11 05:47:17 PM PDT 24
Finished Jul 11 05:47:27 PM PDT 24
Peak memory 196856 kb
Host smart-d57edd35-3933-4248-a410-22998b8a252e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217207324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3217207324
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.992718176
Short name T294
Test name
Test status
Simulation time 354192071 ps
CPU time 1.09 seconds
Started Jul 11 05:47:15 PM PDT 24
Finished Jul 11 05:47:19 PM PDT 24
Peak memory 195684 kb
Host smart-dae66a48-b284-4b15-8d88-e148de437e3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992718176 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.992718176
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.150562430
Short name T313
Test name
Test status
Simulation time 576723321 ps
CPU time 0.62 seconds
Started Jul 11 05:47:15 PM PDT 24
Finished Jul 11 05:47:19 PM PDT 24
Peak memory 192780 kb
Host smart-99d02915-33f3-404c-ab01-3922ceba8115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150562430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.150562430
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4256740288
Short name T283
Test name
Test status
Simulation time 402743294 ps
CPU time 1.1 seconds
Started Jul 11 05:47:17 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 183692 kb
Host smart-99348ba8-a823-4da2-a8cd-9b13aac2b17a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256740288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.4256740288
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1264092949
Short name T380
Test name
Test status
Simulation time 2191413439 ps
CPU time 3.01 seconds
Started Jul 11 05:47:12 PM PDT 24
Finished Jul 11 05:47:16 PM PDT 24
Peak memory 194076 kb
Host smart-85cd0e82-e4fa-4bca-8ae9-003c5266c612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264092949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1264092949
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4157107031
Short name T422
Test name
Test status
Simulation time 341402419 ps
CPU time 2 seconds
Started Jul 11 05:47:12 PM PDT 24
Finished Jul 11 05:47:15 PM PDT 24
Peak memory 198668 kb
Host smart-b6247b58-3c46-499d-b268-1a581d1aaea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157107031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4157107031
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1780524140
Short name T400
Test name
Test status
Simulation time 4160761979 ps
CPU time 3.7 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:38 PM PDT 24
Peak memory 197668 kb
Host smart-8e01c77b-d67a-4512-b02a-d3d087d8cf31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780524140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1780524140
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3211154765
Short name T412
Test name
Test status
Simulation time 353225697 ps
CPU time 0.92 seconds
Started Jul 11 05:47:28 PM PDT 24
Finished Jul 11 05:47:31 PM PDT 24
Peak memory 196208 kb
Host smart-493f9e04-b0fb-47f8-9dc0-8bf33eb9d6bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211154765 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3211154765
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1433502030
Short name T44
Test name
Test status
Simulation time 307867123 ps
CPU time 0.75 seconds
Started Jul 11 05:47:16 PM PDT 24
Finished Jul 11 05:47:20 PM PDT 24
Peak memory 193144 kb
Host smart-14093f8a-7749-4e23-a180-b79def7d5508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433502030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1433502030
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4052043394
Short name T417
Test name
Test status
Simulation time 404438117 ps
CPU time 0.61 seconds
Started Jul 11 05:47:13 PM PDT 24
Finished Jul 11 05:47:16 PM PDT 24
Peak memory 192992 kb
Host smart-cf27807c-a466-4172-9716-74f0e758e371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052043394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4052043394
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2089685558
Short name T68
Test name
Test status
Simulation time 942956647 ps
CPU time 2.18 seconds
Started Jul 11 05:47:17 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 193824 kb
Host smart-d8bbbb4a-1f07-4eee-a6c8-67da855ae8b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089685558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2089685558
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2063234831
Short name T289
Test name
Test status
Simulation time 360987834 ps
CPU time 2.01 seconds
Started Jul 11 05:47:09 PM PDT 24
Finished Jul 11 05:47:13 PM PDT 24
Peak memory 198664 kb
Host smart-2a382d60-a5fd-4cd0-ac62-b249b4224540
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063234831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2063234831
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1218902296
Short name T389
Test name
Test status
Simulation time 4321996731 ps
CPU time 6.89 seconds
Started Jul 11 05:47:20 PM PDT 24
Finished Jul 11 05:47:30 PM PDT 24
Peak memory 197876 kb
Host smart-381cb844-6daf-4246-b89b-8712a305d2a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218902296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1218902296
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1838814683
Short name T375
Test name
Test status
Simulation time 467279687 ps
CPU time 0.86 seconds
Started Jul 11 05:47:32 PM PDT 24
Finished Jul 11 05:47:36 PM PDT 24
Peak memory 196204 kb
Host smart-7bfb96fd-63a7-450f-a403-a5607403ae22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838814683 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1838814683
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.500462732
Short name T64
Test name
Test status
Simulation time 347267528 ps
CPU time 0.95 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:47:47 PM PDT 24
Peak memory 192084 kb
Host smart-4a2e06ee-8acf-4d15-b0e1-d6e2acd63e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500462732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.500462732
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1352679644
Short name T349
Test name
Test status
Simulation time 505892332 ps
CPU time 1.19 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:47:46 PM PDT 24
Peak memory 183756 kb
Host smart-4496f613-05e4-4f0f-af53-a226b823e1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352679644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1352679644
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2392476818
Short name T367
Test name
Test status
Simulation time 1420179541 ps
CPU time 1.26 seconds
Started Jul 11 05:47:25 PM PDT 24
Finished Jul 11 05:47:29 PM PDT 24
Peak memory 193564 kb
Host smart-a40130f8-aa44-4402-9089-b263081dbf7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392476818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2392476818
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.303689261
Short name T366
Test name
Test status
Simulation time 457612035 ps
CPU time 1.89 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:36 PM PDT 24
Peak memory 198660 kb
Host smart-3ed9d0e7-d713-40cd-b5fe-49108ae533b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303689261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.303689261
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3694742207
Short name T343
Test name
Test status
Simulation time 4417381433 ps
CPU time 2.35 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:47:48 PM PDT 24
Peak memory 197864 kb
Host smart-2d968a72-6e06-44ab-8dd3-458bb05ec385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694742207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3694742207
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4285243870
Short name T404
Test name
Test status
Simulation time 539655795 ps
CPU time 1.43 seconds
Started Jul 11 05:47:24 PM PDT 24
Finished Jul 11 05:47:28 PM PDT 24
Peak memory 197152 kb
Host smart-57a60026-63be-4172-ae5d-ab4038eda5e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285243870 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4285243870
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3452720943
Short name T55
Test name
Test status
Simulation time 495713484 ps
CPU time 0.67 seconds
Started Jul 11 05:47:16 PM PDT 24
Finished Jul 11 05:47:20 PM PDT 24
Peak memory 193604 kb
Host smart-567474e0-96e2-4f0f-b705-95e97c829f11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452720943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3452720943
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1165282420
Short name T353
Test name
Test status
Simulation time 562623454 ps
CPU time 0.63 seconds
Started Jul 11 05:47:27 PM PDT 24
Finished Jul 11 05:47:30 PM PDT 24
Peak memory 183772 kb
Host smart-c9e0faeb-8c77-44bf-8e10-31e4d3f89c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165282420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1165282420
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2953349008
Short name T71
Test name
Test status
Simulation time 2258574844 ps
CPU time 3.09 seconds
Started Jul 11 05:47:15 PM PDT 24
Finished Jul 11 05:47:21 PM PDT 24
Peak memory 193884 kb
Host smart-e7e35ff6-31df-48bc-b45e-34b19bbd0e3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953349008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2953349008
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.762311081
Short name T346
Test name
Test status
Simulation time 826952016 ps
CPU time 2.32 seconds
Started Jul 11 05:47:29 PM PDT 24
Finished Jul 11 05:47:34 PM PDT 24
Peak memory 198680 kb
Host smart-59cc0385-ec71-4784-96f7-b8e991360174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762311081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.762311081
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4103118964
Short name T25
Test name
Test status
Simulation time 4581888122 ps
CPU time 2.68 seconds
Started Jul 11 05:47:24 PM PDT 24
Finished Jul 11 05:47:30 PM PDT 24
Peak memory 197872 kb
Host smart-05853291-b1e6-4f9b-b66a-54fc948f26b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103118964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.4103118964
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.597980048
Short name T414
Test name
Test status
Simulation time 599898104 ps
CPU time 1.07 seconds
Started Jul 11 05:47:18 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 198492 kb
Host smart-efc50a0e-97cf-4c12-b0f8-5cd276226a68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597980048 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.597980048
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.244093146
Short name T52
Test name
Test status
Simulation time 507420030 ps
CPU time 1.15 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 193052 kb
Host smart-81fca3b4-b652-4401-b091-e9e48f340326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244093146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.244093146
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1623472643
Short name T379
Test name
Test status
Simulation time 469729084 ps
CPU time 0.71 seconds
Started Jul 11 05:47:25 PM PDT 24
Finished Jul 11 05:47:29 PM PDT 24
Peak memory 183772 kb
Host smart-118b1cfa-9c84-4ff4-95b4-5b23042c372b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623472643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1623472643
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2122217333
Short name T305
Test name
Test status
Simulation time 1840144657 ps
CPU time 2.35 seconds
Started Jul 11 05:47:32 PM PDT 24
Finished Jul 11 05:47:38 PM PDT 24
Peak memory 192040 kb
Host smart-0a14b634-67ef-4523-b73d-16b6427f7426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122217333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2122217333
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1245237945
Short name T281
Test name
Test status
Simulation time 625917208 ps
CPU time 1.15 seconds
Started Jul 11 05:47:19 PM PDT 24
Finished Jul 11 05:47:23 PM PDT 24
Peak memory 198312 kb
Host smart-955cae5c-d88d-4313-ad91-c37ca2114b25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245237945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1245237945
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.476614876
Short name T395
Test name
Test status
Simulation time 4296695715 ps
CPU time 7.15 seconds
Started Jul 11 05:47:23 PM PDT 24
Finished Jul 11 05:47:33 PM PDT 24
Peak memory 198092 kb
Host smart-f53b7fc2-c085-4a2c-9d19-cd392d4fb70f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476614876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.476614876
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2468696345
Short name T296
Test name
Test status
Simulation time 634607508 ps
CPU time 0.94 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:02 PM PDT 24
Peak memory 183780 kb
Host smart-f2ef801e-8820-4cd4-9d61-c32c79b3335a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468696345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2468696345
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.489797207
Short name T50
Test name
Test status
Simulation time 7082404013 ps
CPU time 10.12 seconds
Started Jul 11 05:46:44 PM PDT 24
Finished Jul 11 05:46:55 PM PDT 24
Peak memory 196280 kb
Host smart-25d89a73-2107-486b-8d6b-e49092ca6720
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489797207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.489797207
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1299637991
Short name T47
Test name
Test status
Simulation time 1205161341 ps
CPU time 2.28 seconds
Started Jul 11 05:46:45 PM PDT 24
Finished Jul 11 05:46:49 PM PDT 24
Peak memory 193220 kb
Host smart-9e5420c4-98b4-4e6b-93d7-9eb4872c854f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299637991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1299637991
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.894305167
Short name T336
Test name
Test status
Simulation time 546893825 ps
CPU time 1.4 seconds
Started Jul 11 05:46:46 PM PDT 24
Finished Jul 11 05:46:49 PM PDT 24
Peak memory 196536 kb
Host smart-8689a6c8-43d0-4be4-a283-bcb27bccd20f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894305167 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.894305167
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1538808072
Short name T339
Test name
Test status
Simulation time 383766064 ps
CPU time 0.7 seconds
Started Jul 11 05:46:47 PM PDT 24
Finished Jul 11 05:46:50 PM PDT 24
Peak memory 193012 kb
Host smart-b1526938-981f-49b9-ad37-7de5e9b70b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538808072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1538808072
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.496366021
Short name T384
Test name
Test status
Simulation time 297685909 ps
CPU time 0.91 seconds
Started Jul 11 05:46:44 PM PDT 24
Finished Jul 11 05:46:47 PM PDT 24
Peak memory 183760 kb
Host smart-958ef163-769e-44d3-9839-4dcff8a2faf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496366021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.496366021
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2049872389
Short name T315
Test name
Test status
Simulation time 345919513 ps
CPU time 0.69 seconds
Started Jul 11 05:47:01 PM PDT 24
Finished Jul 11 05:47:04 PM PDT 24
Peak memory 183604 kb
Host smart-739315be-0a86-44c4-8fac-c8e5053752af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049872389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2049872389
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3377012389
Short name T299
Test name
Test status
Simulation time 286688739 ps
CPU time 0.59 seconds
Started Jul 11 05:46:55 PM PDT 24
Finished Jul 11 05:46:58 PM PDT 24
Peak memory 183756 kb
Host smart-c2757683-4fb6-446f-8d43-93776c04350f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377012389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3377012389
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1659131890
Short name T361
Test name
Test status
Simulation time 2502041603 ps
CPU time 5.38 seconds
Started Jul 11 05:46:49 PM PDT 24
Finished Jul 11 05:46:58 PM PDT 24
Peak memory 194212 kb
Host smart-17a56f5f-668d-4c63-b3a4-0af0c85965d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659131890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1659131890
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.239629470
Short name T408
Test name
Test status
Simulation time 2616829298 ps
CPU time 2.41 seconds
Started Jul 11 05:46:47 PM PDT 24
Finished Jul 11 05:46:51 PM PDT 24
Peak memory 198752 kb
Host smart-6a3095ba-0ecb-4b7b-a0ac-9f1158c3ac0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239629470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.239629470
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2951630219
Short name T394
Test name
Test status
Simulation time 7923663014 ps
CPU time 12.24 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:47:11 PM PDT 24
Peak memory 198156 kb
Host smart-b174161d-ecaa-4750-88fc-4805a111fa7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951630219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2951630219
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.4245738543
Short name T317
Test name
Test status
Simulation time 318208636 ps
CPU time 0.64 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 193004 kb
Host smart-3188ea93-d8ab-4d27-8f21-c7de8507f20b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245738543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.4245738543
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.687934896
Short name T338
Test name
Test status
Simulation time 295452978 ps
CPU time 0.92 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 192984 kb
Host smart-f427d2b2-d67e-4331-a3a1-085a72fe2b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687934896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.687934896
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.694595183
Short name T378
Test name
Test status
Simulation time 445022277 ps
CPU time 0.64 seconds
Started Jul 11 05:47:24 PM PDT 24
Finished Jul 11 05:47:28 PM PDT 24
Peak memory 192964 kb
Host smart-27c8b50b-686a-44aa-8a70-3209e3becf01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694595183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.694595183
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1774563296
Short name T365
Test name
Test status
Simulation time 514418591 ps
CPU time 0.87 seconds
Started Jul 11 05:47:25 PM PDT 24
Finished Jul 11 05:47:29 PM PDT 24
Peak memory 192900 kb
Host smart-55492034-4e3c-49ae-b49b-fe8265d381b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774563296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1774563296
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3273979100
Short name T286
Test name
Test status
Simulation time 502945840 ps
CPU time 1.17 seconds
Started Jul 11 05:47:18 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 183220 kb
Host smart-4ede52a7-21f7-4551-8cdd-c00556affa2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273979100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3273979100
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3523814640
Short name T359
Test name
Test status
Simulation time 345994504 ps
CPU time 1.09 seconds
Started Jul 11 05:47:19 PM PDT 24
Finished Jul 11 05:47:23 PM PDT 24
Peak memory 183760 kb
Host smart-c7416f15-4c3a-42e2-93d1-dca39c54486a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523814640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3523814640
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3265443117
Short name T388
Test name
Test status
Simulation time 352502691 ps
CPU time 0.59 seconds
Started Jul 11 05:47:26 PM PDT 24
Finished Jul 11 05:47:29 PM PDT 24
Peak memory 192968 kb
Host smart-0287cef8-3f37-43b2-ac5c-ed13c2bfa0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265443117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3265443117
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3132907007
Short name T295
Test name
Test status
Simulation time 311529377 ps
CPU time 0.65 seconds
Started Jul 11 05:47:24 PM PDT 24
Finished Jul 11 05:47:27 PM PDT 24
Peak memory 192968 kb
Host smart-db260d68-dc2a-440a-9063-186a07e2a4a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132907007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3132907007
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1819373451
Short name T292
Test name
Test status
Simulation time 288098276 ps
CPU time 0.78 seconds
Started Jul 11 05:47:23 PM PDT 24
Finished Jul 11 05:47:27 PM PDT 24
Peak memory 192992 kb
Host smart-efdcb1a6-f009-4b7e-a96d-da515932f83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819373451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1819373451
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3353662550
Short name T383
Test name
Test status
Simulation time 310428142 ps
CPU time 1.01 seconds
Started Jul 11 05:47:16 PM PDT 24
Finished Jul 11 05:47:21 PM PDT 24
Peak memory 183916 kb
Host smart-ee0c0e7f-3e7f-4b84-923e-2f240925c5e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353662550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3353662550
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4232701552
Short name T51
Test name
Test status
Simulation time 528756851 ps
CPU time 1.59 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:03 PM PDT 24
Peak memory 193864 kb
Host smart-8768f237-36ce-4639-8bda-0115fe5f57be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232701552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4232701552
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.921660432
Short name T63
Test name
Test status
Simulation time 12175090656 ps
CPU time 9.4 seconds
Started Jul 11 05:46:50 PM PDT 24
Finished Jul 11 05:47:02 PM PDT 24
Peak memory 196520 kb
Host smart-78179a83-c5de-40fc-93cd-43352b0e2eb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921660432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.921660432
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2852974241
Short name T392
Test name
Test status
Simulation time 1274308262 ps
CPU time 1.6 seconds
Started Jul 11 05:47:13 PM PDT 24
Finished Jul 11 05:47:16 PM PDT 24
Peak memory 193184 kb
Host smart-73658c0a-fc18-473b-b1ef-d522696b899b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852974241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2852974241
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.825236115
Short name T21
Test name
Test status
Simulation time 433160894 ps
CPU time 0.85 seconds
Started Jul 11 05:47:06 PM PDT 24
Finished Jul 11 05:47:08 PM PDT 24
Peak memory 196576 kb
Host smart-d73bca04-2764-4ca4-86f8-038947bed1d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825236115 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.825236115
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.763120260
Short name T415
Test name
Test status
Simulation time 521844942 ps
CPU time 0.79 seconds
Started Jul 11 05:47:02 PM PDT 24
Finished Jul 11 05:47:05 PM PDT 24
Peak memory 192960 kb
Host smart-0c25a765-3358-486f-b656-0d52dee40293
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763120260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.763120260
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3953838876
Short name T354
Test name
Test status
Simulation time 313998207 ps
CPU time 0.84 seconds
Started Jul 11 05:46:46 PM PDT 24
Finished Jul 11 05:46:48 PM PDT 24
Peak memory 183772 kb
Host smart-18f21a33-4731-4994-9eed-a56576c87baa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953838876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3953838876
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3168138011
Short name T371
Test name
Test status
Simulation time 350572769 ps
CPU time 1 seconds
Started Jul 11 05:47:02 PM PDT 24
Finished Jul 11 05:47:05 PM PDT 24
Peak memory 183696 kb
Host smart-6111278e-f20f-42c1-8a7c-48c5ef805bbe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168138011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3168138011
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.387049161
Short name T352
Test name
Test status
Simulation time 487145833 ps
CPU time 1.12 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:47:00 PM PDT 24
Peak memory 183752 kb
Host smart-8fb4946b-f2ea-42d9-baf2-3bb62c1dedef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387049161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.387049161
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2826726767
Short name T66
Test name
Test status
Simulation time 2076708027 ps
CPU time 2.12 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:03 PM PDT 24
Peak memory 194664 kb
Host smart-46338ff5-7fa7-4b2f-90a5-f4d58269dc32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826726767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2826726767
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1410402559
Short name T419
Test name
Test status
Simulation time 378047926 ps
CPU time 1.59 seconds
Started Jul 11 05:46:46 PM PDT 24
Finished Jul 11 05:46:50 PM PDT 24
Peak memory 198688 kb
Host smart-13333181-1c70-42ba-9d01-1b48399b5312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410402559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1410402559
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.96180232
Short name T26
Test name
Test status
Simulation time 8316138751 ps
CPU time 12.08 seconds
Started Jul 11 05:46:47 PM PDT 24
Finished Jul 11 05:47:01 PM PDT 24
Peak memory 198120 kb
Host smart-d236a036-e441-48a8-a890-413b80edc9fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96180232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_i
ntg_err.96180232
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1895446389
Short name T331
Test name
Test status
Simulation time 320292673 ps
CPU time 0.95 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 192996 kb
Host smart-9aad80ec-5e98-4cc1-9408-6bafa2abd116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895446389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1895446389
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2835180788
Short name T342
Test name
Test status
Simulation time 479834738 ps
CPU time 0.97 seconds
Started Jul 11 05:47:15 PM PDT 24
Finished Jul 11 05:47:19 PM PDT 24
Peak memory 192988 kb
Host smart-cfa7c7f3-e550-48bc-86eb-bb32763f8a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835180788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2835180788
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1081008236
Short name T402
Test name
Test status
Simulation time 502841559 ps
CPU time 0.74 seconds
Started Jul 11 05:47:24 PM PDT 24
Finished Jul 11 05:47:27 PM PDT 24
Peak memory 192992 kb
Host smart-5285fea7-f741-40f4-986d-c952300e9570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081008236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1081008236
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3214486795
Short name T390
Test name
Test status
Simulation time 420782965 ps
CPU time 1.05 seconds
Started Jul 11 05:47:16 PM PDT 24
Finished Jul 11 05:47:20 PM PDT 24
Peak memory 192912 kb
Host smart-e3d6a042-d1da-4b12-a76a-5e41d1a57abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214486795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3214486795
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3479019590
Short name T328
Test name
Test status
Simulation time 274214311 ps
CPU time 0.95 seconds
Started Jul 11 05:47:17 PM PDT 24
Finished Jul 11 05:47:21 PM PDT 24
Peak memory 183760 kb
Host smart-eee85c7a-b233-4c6e-bf08-90de51752b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479019590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3479019590
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2012831963
Short name T291
Test name
Test status
Simulation time 524169921 ps
CPU time 0.7 seconds
Started Jul 11 05:47:23 PM PDT 24
Finished Jul 11 05:47:26 PM PDT 24
Peak memory 183772 kb
Host smart-65c48305-0586-43b8-9f3e-2b637583ab46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012831963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2012831963
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.485536499
Short name T309
Test name
Test status
Simulation time 439338318 ps
CPU time 1.2 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:47:46 PM PDT 24
Peak memory 183756 kb
Host smart-af1047fb-9735-4133-8a2f-41547b3b6dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485536499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.485536499
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.380410351
Short name T357
Test name
Test status
Simulation time 447321936 ps
CPU time 1.12 seconds
Started Jul 11 05:47:25 PM PDT 24
Finished Jul 11 05:47:29 PM PDT 24
Peak memory 183692 kb
Host smart-414ee6d4-250a-4c4a-939d-e09054752742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380410351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.380410351
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2862546392
Short name T376
Test name
Test status
Simulation time 447639439 ps
CPU time 1.13 seconds
Started Jul 11 05:47:18 PM PDT 24
Finished Jul 11 05:47:23 PM PDT 24
Peak memory 183772 kb
Host smart-cc6808f8-df23-473d-a5e5-3497ad14dd55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862546392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2862546392
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3638165270
Short name T403
Test name
Test status
Simulation time 400390419 ps
CPU time 0.74 seconds
Started Jul 11 05:47:31 PM PDT 24
Finished Jul 11 05:47:35 PM PDT 24
Peak memory 193004 kb
Host smart-e86e6a3d-c21e-4071-9d11-376c6bbb1285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638165270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3638165270
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.401756943
Short name T332
Test name
Test status
Simulation time 716025657 ps
CPU time 0.99 seconds
Started Jul 11 05:47:16 PM PDT 24
Finished Jul 11 05:47:20 PM PDT 24
Peak memory 194692 kb
Host smart-1db138ed-13fb-41ae-a9e9-a0a076766246
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401756943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.401756943
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3349179191
Short name T49
Test name
Test status
Simulation time 10349203227 ps
CPU time 21.19 seconds
Started Jul 11 05:46:59 PM PDT 24
Finished Jul 11 05:47:23 PM PDT 24
Peak memory 192252 kb
Host smart-761948af-31ad-4d2f-91ef-3838316084c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349179191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3349179191
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2760761452
Short name T53
Test name
Test status
Simulation time 955765554 ps
CPU time 1.22 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:46:59 PM PDT 24
Peak memory 183824 kb
Host smart-6dda178d-a411-46ae-abd9-b77a957dd03e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760761452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2760761452
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2923956055
Short name T287
Test name
Test status
Simulation time 446680107 ps
CPU time 1.28 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:47:00 PM PDT 24
Peak memory 196244 kb
Host smart-e53cd4fa-809f-4de9-b5ad-a1b64bb97b9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923956055 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2923956055
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4227337109
Short name T399
Test name
Test status
Simulation time 342634571 ps
CPU time 0.71 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:02 PM PDT 24
Peak memory 193132 kb
Host smart-2aec45d4-f49b-4cbf-b43a-5169139f14f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227337109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4227337109
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.471634487
Short name T416
Test name
Test status
Simulation time 501978504 ps
CPU time 0.68 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:46:59 PM PDT 24
Peak memory 192992 kb
Host smart-c29ffcb2-cf43-4b76-a48b-ad4b824792c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471634487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.471634487
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.822351577
Short name T398
Test name
Test status
Simulation time 513759850 ps
CPU time 1.19 seconds
Started Jul 11 05:47:18 PM PDT 24
Finished Jul 11 05:47:23 PM PDT 24
Peak memory 183708 kb
Host smart-95481fd1-0d34-4c08-a89f-1d4ebc09582e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822351577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.822351577
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.933375874
Short name T370
Test name
Test status
Simulation time 331280413 ps
CPU time 0.62 seconds
Started Jul 11 05:46:51 PM PDT 24
Finished Jul 11 05:46:55 PM PDT 24
Peak memory 183748 kb
Host smart-39e476d7-5b00-4308-9400-8dbee1451c4a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933375874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.933375874
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3282660265
Short name T65
Test name
Test status
Simulation time 936989826 ps
CPU time 1.7 seconds
Started Jul 11 05:46:52 PM PDT 24
Finished Jul 11 05:46:56 PM PDT 24
Peak memory 183836 kb
Host smart-24733758-c093-4f64-9e50-ed0a1287140c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282660265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3282660265
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1664495073
Short name T325
Test name
Test status
Simulation time 528957272 ps
CPU time 2.15 seconds
Started Jul 11 05:46:52 PM PDT 24
Finished Jul 11 05:46:57 PM PDT 24
Peak memory 198696 kb
Host smart-363cdbd5-4047-482e-9871-bbd5313d47c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664495073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1664495073
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1223138498
Short name T191
Test name
Test status
Simulation time 8431857316 ps
CPU time 3.05 seconds
Started Jul 11 05:46:52 PM PDT 24
Finished Jul 11 05:46:58 PM PDT 24
Peak memory 198232 kb
Host smart-d3b336be-770e-4eed-ab53-98019f53d387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223138498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1223138498
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1500443689
Short name T284
Test name
Test status
Simulation time 508644040 ps
CPU time 0.9 seconds
Started Jul 11 05:47:29 PM PDT 24
Finished Jul 11 05:47:32 PM PDT 24
Peak memory 193008 kb
Host smart-1d0030d2-2386-45eb-a583-71bdf1d2ba1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500443689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1500443689
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.354304076
Short name T308
Test name
Test status
Simulation time 300101682 ps
CPU time 0.74 seconds
Started Jul 11 05:47:18 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 183080 kb
Host smart-a68e48d6-5855-40af-9898-70fc69c4efe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354304076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.354304076
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.986463280
Short name T321
Test name
Test status
Simulation time 286146887 ps
CPU time 0.8 seconds
Started Jul 11 05:47:24 PM PDT 24
Finished Jul 11 05:47:28 PM PDT 24
Peak memory 183708 kb
Host smart-d600cd99-cbe0-433a-a5d7-8216d09aa801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986463280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.986463280
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.921115204
Short name T368
Test name
Test status
Simulation time 427793085 ps
CPU time 0.86 seconds
Started Jul 11 05:47:18 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 183760 kb
Host smart-82d093d9-ae3d-460f-a085-5ce0a850febc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921115204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.921115204
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1635095278
Short name T363
Test name
Test status
Simulation time 413229341 ps
CPU time 1.13 seconds
Started Jul 11 05:47:24 PM PDT 24
Finished Jul 11 05:47:27 PM PDT 24
Peak memory 192992 kb
Host smart-c93a9ddb-a993-4634-bc10-c38581273237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635095278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1635095278
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3439163011
Short name T374
Test name
Test status
Simulation time 413750926 ps
CPU time 0.63 seconds
Started Jul 11 05:47:23 PM PDT 24
Finished Jul 11 05:47:26 PM PDT 24
Peak memory 183780 kb
Host smart-0714beb6-1800-4622-a316-96408f3fa397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439163011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3439163011
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.91417634
Short name T420
Test name
Test status
Simulation time 372254477 ps
CPU time 0.68 seconds
Started Jul 11 05:47:43 PM PDT 24
Finished Jul 11 05:47:47 PM PDT 24
Peak memory 183760 kb
Host smart-8c9bbf39-3bfc-4add-a09b-dbdea2075745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91417634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.91417634
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1212307213
Short name T397
Test name
Test status
Simulation time 364641881 ps
CPU time 0.67 seconds
Started Jul 11 05:47:37 PM PDT 24
Finished Jul 11 05:47:41 PM PDT 24
Peak memory 192968 kb
Host smart-7dee1abe-73a8-436e-ae7f-e354cc143ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212307213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1212307213
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3415218963
Short name T324
Test name
Test status
Simulation time 505207245 ps
CPU time 1.05 seconds
Started Jul 11 05:47:38 PM PDT 24
Finished Jul 11 05:47:42 PM PDT 24
Peak memory 192972 kb
Host smart-4a7912cc-2d91-4283-a1d8-204c1f935ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415218963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3415218963
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4056348470
Short name T369
Test name
Test status
Simulation time 443934231 ps
CPU time 0.8 seconds
Started Jul 11 05:47:25 PM PDT 24
Finished Jul 11 05:47:29 PM PDT 24
Peak memory 183784 kb
Host smart-21100e5a-5a6e-468d-be06-0c616d5fe530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056348470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4056348470
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2382734476
Short name T326
Test name
Test status
Simulation time 494506289 ps
CPU time 0.91 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:02 PM PDT 24
Peak memory 196196 kb
Host smart-9069d230-9e5c-4b10-9071-83b50c7f3160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382734476 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2382734476
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3577628833
Short name T288
Test name
Test status
Simulation time 472248269 ps
CPU time 1.34 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:47:00 PM PDT 24
Peak memory 194068 kb
Host smart-fe800ddd-87fb-4b36-b36a-78f17388812a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577628833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3577628833
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3664860380
Short name T385
Test name
Test status
Simulation time 463671101 ps
CPU time 0.68 seconds
Started Jul 11 05:46:59 PM PDT 24
Finished Jul 11 05:47:02 PM PDT 24
Peak memory 183720 kb
Host smart-60e7de23-cead-47ff-99bc-5b46bcbb5e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664860380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3664860380
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2942793474
Short name T320
Test name
Test status
Simulation time 2919771744 ps
CPU time 1.11 seconds
Started Jul 11 05:47:18 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 192088 kb
Host smart-091980b5-9efc-497f-8913-2dba3014ca9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942793474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2942793474
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.630425060
Short name T334
Test name
Test status
Simulation time 436543808 ps
CPU time 2.32 seconds
Started Jul 11 05:47:05 PM PDT 24
Finished Jul 11 05:47:08 PM PDT 24
Peak memory 198664 kb
Host smart-a1b7a54c-68e6-4583-9af0-9e4e610599ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630425060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.630425060
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2658923218
Short name T297
Test name
Test status
Simulation time 4537859816 ps
CPU time 3.85 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:47:03 PM PDT 24
Peak memory 198036 kb
Host smart-19e7fa4f-f950-4a51-921a-80373c7a9bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658923218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2658923218
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2407440882
Short name T396
Test name
Test status
Simulation time 468035151 ps
CPU time 0.97 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:02 PM PDT 24
Peak memory 198476 kb
Host smart-a334bef6-0ce2-457a-b2b7-6ef7ca1dfccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407440882 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2407440882
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1190402545
Short name T46
Test name
Test status
Simulation time 449023812 ps
CPU time 0.63 seconds
Started Jul 11 05:46:53 PM PDT 24
Finished Jul 11 05:46:56 PM PDT 24
Peak memory 193500 kb
Host smart-cfa3c9d7-9ccf-4419-b8f3-8e58937bee51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190402545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1190402545
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.23298229
Short name T303
Test name
Test status
Simulation time 413175188 ps
CPU time 0.86 seconds
Started Jul 11 05:47:02 PM PDT 24
Finished Jul 11 05:47:05 PM PDT 24
Peak memory 183768 kb
Host smart-11561f09-f607-4fb2-8c71-434a3a6d7875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23298229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.23298229
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.187195879
Short name T345
Test name
Test status
Simulation time 1578982429 ps
CPU time 2.58 seconds
Started Jul 11 05:46:57 PM PDT 24
Finished Jul 11 05:47:03 PM PDT 24
Peak memory 191976 kb
Host smart-72f3d157-0ae9-4467-8b4b-9c1644b9198e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187195879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.187195879
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2455324708
Short name T335
Test name
Test status
Simulation time 576886537 ps
CPU time 1.31 seconds
Started Jul 11 05:47:18 PM PDT 24
Finished Jul 11 05:47:22 PM PDT 24
Peak memory 198472 kb
Host smart-8040da5f-a7be-4ddb-8390-8b9f4cadc6f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455324708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2455324708
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3290409305
Short name T316
Test name
Test status
Simulation time 8286998286 ps
CPU time 11.05 seconds
Started Jul 11 05:47:13 PM PDT 24
Finished Jul 11 05:47:26 PM PDT 24
Peak memory 198220 kb
Host smart-d6494af2-c516-4e83-a018-363ab8ad8599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290409305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3290409305
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2244157894
Short name T27
Test name
Test status
Simulation time 527332887 ps
CPU time 0.82 seconds
Started Jul 11 05:47:07 PM PDT 24
Finished Jul 11 05:47:09 PM PDT 24
Peak memory 195100 kb
Host smart-c13394cc-17e2-4fa7-8583-208b1ee7c859
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244157894 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2244157894
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.630461631
Short name T340
Test name
Test status
Simulation time 462863958 ps
CPU time 0.87 seconds
Started Jul 11 05:46:53 PM PDT 24
Finished Jul 11 05:46:56 PM PDT 24
Peak memory 193024 kb
Host smart-7922d0c8-1a28-44c6-b1f7-05678c1c0689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630461631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.630461631
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.938265639
Short name T351
Test name
Test status
Simulation time 339129988 ps
CPU time 0.77 seconds
Started Jul 11 05:47:07 PM PDT 24
Finished Jul 11 05:47:09 PM PDT 24
Peak memory 192968 kb
Host smart-ec5a992e-f01a-4f8d-955a-639d4ec272e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938265639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.938265639
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2180125091
Short name T67
Test name
Test status
Simulation time 1953514678 ps
CPU time 3.37 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:47:20 PM PDT 24
Peak memory 195088 kb
Host smart-a457e3ba-6963-4295-ac04-74a5d345e215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180125091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2180125091
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3983607040
Short name T406
Test name
Test status
Simulation time 517277065 ps
CPU time 2.26 seconds
Started Jul 11 05:46:55 PM PDT 24
Finished Jul 11 05:47:00 PM PDT 24
Peak memory 198636 kb
Host smart-42b6298a-7d85-446e-92b4-1e9830a3da98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983607040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3983607040
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.191514580
Short name T356
Test name
Test status
Simulation time 4650569359 ps
CPU time 4.27 seconds
Started Jul 11 05:47:19 PM PDT 24
Finished Jul 11 05:47:27 PM PDT 24
Peak memory 197672 kb
Host smart-acd3a233-11f7-42bc-ac80-ae6fff3c9a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191514580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.191514580
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.381216382
Short name T418
Test name
Test status
Simulation time 599748289 ps
CPU time 1.57 seconds
Started Jul 11 05:47:19 PM PDT 24
Finished Jul 11 05:47:24 PM PDT 24
Peak memory 196744 kb
Host smart-1040880a-6419-48e1-be32-603871259271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381216382 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.381216382
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1528553808
Short name T364
Test name
Test status
Simulation time 538590125 ps
CPU time 0.75 seconds
Started Jul 11 05:47:09 PM PDT 24
Finished Jul 11 05:47:12 PM PDT 24
Peak memory 193280 kb
Host smart-a3b17505-82a6-4594-a405-4e7b0280a406
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528553808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1528553808
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4150012777
Short name T285
Test name
Test status
Simulation time 475190782 ps
CPU time 1.29 seconds
Started Jul 11 05:47:09 PM PDT 24
Finished Jul 11 05:47:12 PM PDT 24
Peak memory 192976 kb
Host smart-87d06cad-49df-4ff3-8717-94d5c9634f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150012777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.4150012777
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4183355765
Short name T372
Test name
Test status
Simulation time 1371551586 ps
CPU time 1.67 seconds
Started Jul 11 05:47:02 PM PDT 24
Finished Jul 11 05:47:06 PM PDT 24
Peak memory 194064 kb
Host smart-0dbdbb7d-8fde-4f3b-9a58-e18cd1cca960
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183355765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4183355765
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3849440676
Short name T290
Test name
Test status
Simulation time 475282507 ps
CPU time 1.65 seconds
Started Jul 11 05:47:03 PM PDT 24
Finished Jul 11 05:47:06 PM PDT 24
Peak memory 198660 kb
Host smart-cf0c6cc6-cc5a-4ffe-aae7-48eedb6c7a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849440676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3849440676
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3125250017
Short name T386
Test name
Test status
Simulation time 8762110209 ps
CPU time 5.23 seconds
Started Jul 11 05:47:06 PM PDT 24
Finished Jul 11 05:47:12 PM PDT 24
Peak memory 198296 kb
Host smart-51eee2b4-5d82-4edf-a6ad-4528ea7cab75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125250017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3125250017
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3977327501
Short name T421
Test name
Test status
Simulation time 631460797 ps
CPU time 0.74 seconds
Started Jul 11 05:47:05 PM PDT 24
Finished Jul 11 05:47:07 PM PDT 24
Peak memory 196208 kb
Host smart-f5ee74f1-4250-44f1-a915-18b29e2227d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977327501 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3977327501
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2382412461
Short name T337
Test name
Test status
Simulation time 422336807 ps
CPU time 0.76 seconds
Started Jul 11 05:47:19 PM PDT 24
Finished Jul 11 05:47:23 PM PDT 24
Peak memory 193104 kb
Host smart-8527b219-4c30-4a36-baa3-2c9655a0b3b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382412461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2382412461
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3533088558
Short name T293
Test name
Test status
Simulation time 525959158 ps
CPU time 0.71 seconds
Started Jul 11 05:47:07 PM PDT 24
Finished Jul 11 05:47:08 PM PDT 24
Peak memory 183776 kb
Host smart-730fb0f3-1021-4d4d-aee6-fe219a274b91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533088558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3533088558
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2208878459
Short name T70
Test name
Test status
Simulation time 1202902886 ps
CPU time 1.15 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:02 PM PDT 24
Peak memory 193828 kb
Host smart-41e8f9aa-9db6-4931-96b0-dc5a00a1bcfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208878459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2208878459
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3248843815
Short name T393
Test name
Test status
Simulation time 317054070 ps
CPU time 1.51 seconds
Started Jul 11 05:46:58 PM PDT 24
Finished Jul 11 05:47:02 PM PDT 24
Peak memory 198164 kb
Host smart-507316cd-44a8-4139-a106-a3c515b3715b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248843815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3248843815
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2798279024
Short name T373
Test name
Test status
Simulation time 8696560944 ps
CPU time 7.33 seconds
Started Jul 11 05:47:05 PM PDT 24
Finished Jul 11 05:47:13 PM PDT 24
Peak memory 198184 kb
Host smart-4399d401-0219-4918-bfa2-d2495f0a2be5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798279024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2798279024
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2425539297
Short name T280
Test name
Test status
Simulation time 6088204672 ps
CPU time 1.7 seconds
Started Jul 11 05:45:47 PM PDT 24
Finished Jul 11 05:45:51 PM PDT 24
Peak memory 196988 kb
Host smart-0d91fe4d-749a-4d9c-82a3-6ecb7864fe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425539297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2425539297
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.864945286
Short name T267
Test name
Test status
Simulation time 540996575 ps
CPU time 1.29 seconds
Started Jul 11 05:45:53 PM PDT 24
Finished Jul 11 05:45:58 PM PDT 24
Peak memory 196700 kb
Host smart-f67fc22f-c102-45a0-bb5c-95bddacd5175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864945286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.864945286
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.364460722
Short name T37
Test name
Test status
Simulation time 31702139030 ps
CPU time 47.11 seconds
Started Jul 11 05:45:50 PM PDT 24
Finished Jul 11 05:46:40 PM PDT 24
Peak memory 191844 kb
Host smart-7c4ac237-cb69-4dd9-878c-7f484c969043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364460722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.364460722
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3873348721
Short name T17
Test name
Test status
Simulation time 8199069034 ps
CPU time 1.89 seconds
Started Jul 11 05:45:46 PM PDT 24
Finished Jul 11 05:45:50 PM PDT 24
Peak memory 216056 kb
Host smart-3a0362f0-46b9-458f-9eda-2076f9c077e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873348721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3873348721
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.4003701465
Short name T206
Test name
Test status
Simulation time 556162632 ps
CPU time 1.27 seconds
Started Jul 11 05:46:04 PM PDT 24
Finished Jul 11 05:46:08 PM PDT 24
Peak memory 196740 kb
Host smart-57398b33-ab90-461c-a635-be08cacc0cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003701465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.4003701465
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.385246136
Short name T254
Test name
Test status
Simulation time 26585911997 ps
CPU time 43.6 seconds
Started Jul 11 05:46:01 PM PDT 24
Finished Jul 11 05:46:47 PM PDT 24
Peak memory 196980 kb
Host smart-8450ac09-f565-4bb3-8d36-d0e9f4037b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385246136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.385246136
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1364650609
Short name T235
Test name
Test status
Simulation time 568694583 ps
CPU time 1.31 seconds
Started Jul 11 05:45:56 PM PDT 24
Finished Jul 11 05:46:00 PM PDT 24
Peak memory 191896 kb
Host smart-a9cf36a3-abd0-42a8-9939-d969bd5e26a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364650609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1364650609
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.692717320
Short name T215
Test name
Test status
Simulation time 13552624028 ps
CPU time 17.52 seconds
Started Jul 11 05:46:01 PM PDT 24
Finished Jul 11 05:46:21 PM PDT 24
Peak memory 191992 kb
Host smart-833aa731-b1f6-4128-ab92-f71c2e914fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692717320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.692717320
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1859946800
Short name T252
Test name
Test status
Simulation time 569049925 ps
CPU time 1.31 seconds
Started Jul 11 05:45:59 PM PDT 24
Finished Jul 11 05:46:03 PM PDT 24
Peak memory 191772 kb
Host smart-ec2008f3-f320-435b-a27e-ed2c8e1b6dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859946800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1859946800
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.203519038
Short name T212
Test name
Test status
Simulation time 10268201546 ps
CPU time 13.44 seconds
Started Jul 11 05:45:59 PM PDT 24
Finished Jul 11 05:46:15 PM PDT 24
Peak memory 191976 kb
Host smart-26b17e5b-f2d3-4eae-bb51-6e5079020a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203519038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.203519038
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.951350394
Short name T259
Test name
Test status
Simulation time 604975208 ps
CPU time 0.83 seconds
Started Jul 11 05:45:58 PM PDT 24
Finished Jul 11 05:46:02 PM PDT 24
Peak memory 192084 kb
Host smart-4003f21f-d861-4e90-8e1a-703fad0dc151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951350394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.951350394
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2856769722
Short name T227
Test name
Test status
Simulation time 47541461643 ps
CPU time 11.55 seconds
Started Jul 11 05:46:18 PM PDT 24
Finished Jul 11 05:46:32 PM PDT 24
Peak memory 191988 kb
Host smart-ff27f83b-70eb-45ae-b25d-2266c3a74f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856769722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2856769722
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2531111575
Short name T196
Test name
Test status
Simulation time 562723776 ps
CPU time 0.62 seconds
Started Jul 11 05:46:12 PM PDT 24
Finished Jul 11 05:46:14 PM PDT 24
Peak memory 191928 kb
Host smart-9fb7a455-9b5a-49e3-9ac9-5f5bb0d978c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531111575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2531111575
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1701886064
Short name T248
Test name
Test status
Simulation time 13668269627 ps
CPU time 5.8 seconds
Started Jul 11 05:46:02 PM PDT 24
Finished Jul 11 05:46:11 PM PDT 24
Peak memory 192172 kb
Host smart-410b570d-90ed-4aec-bb82-a7f20423ccd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701886064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1701886064
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2737736241
Short name T243
Test name
Test status
Simulation time 535058516 ps
CPU time 0.92 seconds
Started Jul 11 05:46:11 PM PDT 24
Finished Jul 11 05:46:14 PM PDT 24
Peak memory 191880 kb
Host smart-16fd10f9-e361-4465-8c55-ec8413c5469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737736241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2737736241
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2795780968
Short name T57
Test name
Test status
Simulation time 1542582060 ps
CPU time 1.05 seconds
Started Jul 11 05:46:14 PM PDT 24
Finished Jul 11 05:46:17 PM PDT 24
Peak memory 191936 kb
Host smart-d4c434be-62b7-4995-ba36-b657ae524ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795780968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2795780968
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3208264752
Short name T226
Test name
Test status
Simulation time 550062394 ps
CPU time 1.3 seconds
Started Jul 11 05:46:01 PM PDT 24
Finished Jul 11 05:46:05 PM PDT 24
Peak memory 196752 kb
Host smart-3c26304a-ef6c-4103-89f3-176b8239ccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208264752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3208264752
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3934954764
Short name T213
Test name
Test status
Simulation time 3912470309 ps
CPU time 1.74 seconds
Started Jul 11 05:46:00 PM PDT 24
Finished Jul 11 05:46:05 PM PDT 24
Peak memory 196736 kb
Host smart-7c48f7d3-6a1c-4387-8d14-87eb3df83dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934954764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3934954764
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1809905416
Short name T209
Test name
Test status
Simulation time 476936108 ps
CPU time 0.98 seconds
Started Jul 11 05:45:59 PM PDT 24
Finished Jul 11 05:46:03 PM PDT 24
Peak memory 191916 kb
Host smart-e45d1059-bdaa-4ac8-9485-d11d6fb6f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809905416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1809905416
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2181011827
Short name T257
Test name
Test status
Simulation time 493639985 ps
CPU time 0.83 seconds
Started Jul 11 05:46:06 PM PDT 24
Finished Jul 11 05:46:09 PM PDT 24
Peak memory 196612 kb
Host smart-ebd932dc-3fc2-4a5f-96f2-0a1fe21f4d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181011827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2181011827
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1232492257
Short name T200
Test name
Test status
Simulation time 522219209 ps
CPU time 1.32 seconds
Started Jul 11 05:46:14 PM PDT 24
Finished Jul 11 05:46:18 PM PDT 24
Peak memory 196696 kb
Host smart-4bff5c85-bcc9-4ade-bdb0-b6aca6b3dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232492257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1232492257
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3351254784
Short name T258
Test name
Test status
Simulation time 23214185447 ps
CPU time 8.68 seconds
Started Jul 11 05:46:04 PM PDT 24
Finished Jul 11 05:46:16 PM PDT 24
Peak memory 196992 kb
Host smart-5cf1d357-f8fe-49b6-9f12-f8c6920e8b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351254784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3351254784
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.4191512595
Short name T197
Test name
Test status
Simulation time 397487761 ps
CPU time 0.72 seconds
Started Jul 11 05:46:35 PM PDT 24
Finished Jul 11 05:46:38 PM PDT 24
Peak memory 191920 kb
Host smart-fe146bfa-2a09-4ea8-87ea-8f7b0271f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191512595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4191512595
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1667892834
Short name T2
Test name
Test status
Simulation time 26340004734 ps
CPU time 10.4 seconds
Started Jul 11 05:46:22 PM PDT 24
Finished Jul 11 05:46:35 PM PDT 24
Peak memory 191968 kb
Host smart-4e1ccbfb-ac15-4394-b15f-291034810fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667892834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1667892834
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1129777036
Short name T246
Test name
Test status
Simulation time 411322971 ps
CPU time 1.19 seconds
Started Jul 11 05:46:07 PM PDT 24
Finished Jul 11 05:46:10 PM PDT 24
Peak memory 196744 kb
Host smart-b647c06c-c198-4c4d-8117-bc30ba20f71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129777036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1129777036
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_jump.781182625
Short name T167
Test name
Test status
Simulation time 627298636 ps
CPU time 0.76 seconds
Started Jul 11 05:45:54 PM PDT 24
Finished Jul 11 05:45:58 PM PDT 24
Peak memory 196692 kb
Host smart-cbd4e4af-c3d0-4039-bc38-5d50edc1615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781182625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.781182625
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3090042450
Short name T278
Test name
Test status
Simulation time 19109830382 ps
CPU time 27.35 seconds
Started Jul 11 05:45:53 PM PDT 24
Finished Jul 11 05:46:24 PM PDT 24
Peak memory 192072 kb
Host smart-6479b5c9-a05d-42aa-abb6-5205b23cfb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090042450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3090042450
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3637251017
Short name T14
Test name
Test status
Simulation time 8008984083 ps
CPU time 3.92 seconds
Started Jul 11 05:45:46 PM PDT 24
Finished Jul 11 05:45:52 PM PDT 24
Peak memory 215828 kb
Host smart-dfe457f1-3492-4f45-b668-d981444a7749
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637251017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3637251017
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.998972633
Short name T274
Test name
Test status
Simulation time 427144400 ps
CPU time 0.73 seconds
Started Jul 11 05:45:54 PM PDT 24
Finished Jul 11 05:45:58 PM PDT 24
Peak memory 196688 kb
Host smart-9a0917db-b61d-42b8-8e39-8ecd40e39fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998972633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.998972633
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1147034121
Short name T154
Test name
Test status
Simulation time 562469333 ps
CPU time 1.49 seconds
Started Jul 11 05:46:22 PM PDT 24
Finished Jul 11 05:46:27 PM PDT 24
Peak memory 196660 kb
Host smart-d9531124-4f96-4d16-9ce6-10ce8c8e1769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147034121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1147034121
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2230229577
Short name T40
Test name
Test status
Simulation time 18588325237 ps
CPU time 7.61 seconds
Started Jul 11 05:46:19 PM PDT 24
Finished Jul 11 05:46:29 PM PDT 24
Peak memory 196980 kb
Host smart-684297f9-6eb6-44cf-b9ed-2ed0efee657c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230229577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2230229577
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2256608353
Short name T23
Test name
Test status
Simulation time 355065374 ps
CPU time 1.07 seconds
Started Jul 11 05:46:56 PM PDT 24
Finished Jul 11 05:47:00 PM PDT 24
Peak memory 196684 kb
Host smart-1a44a9d8-3e2b-4bdf-9c4e-1615e7e94c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256608353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2256608353
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3313361208
Short name T205
Test name
Test status
Simulation time 20700465703 ps
CPU time 7.27 seconds
Started Jul 11 05:46:50 PM PDT 24
Finished Jul 11 05:47:01 PM PDT 24
Peak memory 196920 kb
Host smart-c6a8c014-5ab4-4e81-af87-4f34acb30bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313361208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3313361208
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1990902752
Short name T203
Test name
Test status
Simulation time 599189243 ps
CPU time 1.5 seconds
Started Jul 11 05:46:50 PM PDT 24
Finished Jul 11 05:46:55 PM PDT 24
Peak memory 191852 kb
Host smart-77d62e54-a893-4ecb-b221-21d7ea76ba8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990902752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1990902752
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.637227570
Short name T255
Test name
Test status
Simulation time 40310942668 ps
CPU time 13.26 seconds
Started Jul 11 05:46:13 PM PDT 24
Finished Jul 11 05:46:28 PM PDT 24
Peak memory 191988 kb
Host smart-dddef2f7-7b09-464e-b560-4133fee9c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637227570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.637227570
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3630404417
Short name T266
Test name
Test status
Simulation time 465383748 ps
CPU time 0.74 seconds
Started Jul 11 05:46:04 PM PDT 24
Finished Jul 11 05:46:08 PM PDT 24
Peak memory 191928 kb
Host smart-c713e2f6-81f1-42ec-aed4-6ebd80e1a341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630404417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3630404417
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.390927598
Short name T228
Test name
Test status
Simulation time 12499993135 ps
CPU time 17.22 seconds
Started Jul 11 05:46:14 PM PDT 24
Finished Jul 11 05:46:34 PM PDT 24
Peak memory 192004 kb
Host smart-216c4bec-e051-42e8-8626-2d18978708d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390927598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.390927598
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2630821527
Short name T223
Test name
Test status
Simulation time 482657040 ps
CPU time 0.78 seconds
Started Jul 11 05:46:50 PM PDT 24
Finished Jul 11 05:46:54 PM PDT 24
Peak memory 196688 kb
Host smart-3f50c31c-d82f-4c4f-b702-c31178810249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630821527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2630821527
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2429330011
Short name T34
Test name
Test status
Simulation time 5390794460 ps
CPU time 8.69 seconds
Started Jul 11 05:46:10 PM PDT 24
Finished Jul 11 05:46:21 PM PDT 24
Peak memory 191832 kb
Host smart-26ff49c3-741d-48a4-8fe3-7336fd8e9d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429330011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2429330011
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3686258147
Short name T242
Test name
Test status
Simulation time 494441157 ps
CPU time 0.76 seconds
Started Jul 11 05:46:14 PM PDT 24
Finished Jul 11 05:46:17 PM PDT 24
Peak memory 196764 kb
Host smart-9b7a1a72-e703-4470-89d7-687d00f0cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686258147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3686258147
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2776663422
Short name T261
Test name
Test status
Simulation time 14282297415 ps
CPU time 10.74 seconds
Started Jul 11 05:46:25 PM PDT 24
Finished Jul 11 05:46:40 PM PDT 24
Peak memory 191880 kb
Host smart-2787d675-e440-442c-80c5-832c362fdd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776663422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2776663422
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4171283315
Short name T220
Test name
Test status
Simulation time 581403685 ps
CPU time 1.02 seconds
Started Jul 11 05:46:11 PM PDT 24
Finished Jul 11 05:46:14 PM PDT 24
Peak memory 191932 kb
Host smart-7d0a3afa-badd-4c6c-9fa1-251e44a74b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171283315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4171283315
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1687614388
Short name T177
Test name
Test status
Simulation time 399317032 ps
CPU time 0.65 seconds
Started Jul 11 05:46:13 PM PDT 24
Finished Jul 11 05:46:15 PM PDT 24
Peak memory 196716 kb
Host smart-2a16a25d-8fe8-4818-8e04-9db80f63f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687614388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1687614388
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.482165644
Short name T260
Test name
Test status
Simulation time 3257575039 ps
CPU time 1.67 seconds
Started Jul 11 05:46:19 PM PDT 24
Finished Jul 11 05:46:23 PM PDT 24
Peak memory 191988 kb
Host smart-0278a911-64e3-491c-8f7a-05571c984bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482165644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.482165644
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4191119173
Short name T24
Test name
Test status
Simulation time 496216830 ps
CPU time 0.74 seconds
Started Jul 11 05:46:10 PM PDT 24
Finished Jul 11 05:46:13 PM PDT 24
Peak memory 196700 kb
Host smart-684beda6-ea50-484f-b504-3cf32458abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191119173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4191119173
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2353016718
Short name T195
Test name
Test status
Simulation time 19556356512 ps
CPU time 30.22 seconds
Started Jul 11 05:46:17 PM PDT 24
Finished Jul 11 05:46:49 PM PDT 24
Peak memory 192004 kb
Host smart-f91fb3bd-1966-4be7-9c0b-4e54d08710b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353016718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2353016718
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3032921912
Short name T221
Test name
Test status
Simulation time 458371872 ps
CPU time 0.95 seconds
Started Jul 11 05:46:23 PM PDT 24
Finished Jul 11 05:46:27 PM PDT 24
Peak memory 196820 kb
Host smart-d0f22144-cea2-4b09-a4f2-5bcb03e04256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032921912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3032921912
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.354875513
Short name T262
Test name
Test status
Simulation time 33127904656 ps
CPU time 11.85 seconds
Started Jul 11 05:46:48 PM PDT 24
Finished Jul 11 05:47:03 PM PDT 24
Peak memory 191912 kb
Host smart-0fcd1354-1723-4ea8-b947-b8d5a7024cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354875513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.354875513
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1140799550
Short name T275
Test name
Test status
Simulation time 497002412 ps
CPU time 0.91 seconds
Started Jul 11 05:46:16 PM PDT 24
Finished Jul 11 05:46:19 PM PDT 24
Peak memory 191908 kb
Host smart-4089cc17-7748-47be-b61b-cdc3ae5eeb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140799550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1140799550
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3560005749
Short name T187
Test name
Test status
Simulation time 581756283 ps
CPU time 1.28 seconds
Started Jul 11 05:46:22 PM PDT 24
Finished Jul 11 05:46:27 PM PDT 24
Peak memory 196812 kb
Host smart-efd803d9-b377-447f-8f31-f01c9753755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560005749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3560005749
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2827962058
Short name T240
Test name
Test status
Simulation time 25098886515 ps
CPU time 32.04 seconds
Started Jul 11 05:46:23 PM PDT 24
Finished Jul 11 05:46:58 PM PDT 24
Peak memory 191936 kb
Host smart-7a0bb830-14d5-421c-9def-83b37636ec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827962058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2827962058
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4061206781
Short name T233
Test name
Test status
Simulation time 486030240 ps
CPU time 1.29 seconds
Started Jul 11 05:46:50 PM PDT 24
Finished Jul 11 05:46:55 PM PDT 24
Peak memory 191856 kb
Host smart-a5825fa6-df43-44a8-92d7-1e701b1ec2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061206781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4061206781
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3786879809
Short name T250
Test name
Test status
Simulation time 740703956 ps
CPU time 1.59 seconds
Started Jul 11 05:45:57 PM PDT 24
Finished Jul 11 05:46:01 PM PDT 24
Peak memory 191928 kb
Host smart-2d79836d-7ffb-4ac6-996c-9c7a8648c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786879809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3786879809
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3979564994
Short name T16
Test name
Test status
Simulation time 4770545067 ps
CPU time 2.45 seconds
Started Jul 11 05:45:56 PM PDT 24
Finished Jul 11 05:46:01 PM PDT 24
Peak memory 215724 kb
Host smart-6b86f9c7-b821-4ddf-81e8-db5fb1bf01d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979564994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3979564994
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3345865922
Short name T201
Test name
Test status
Simulation time 467650012 ps
CPU time 1.22 seconds
Started Jul 11 05:45:45 PM PDT 24
Finished Jul 11 05:45:47 PM PDT 24
Peak memory 196716 kb
Host smart-f5c5d96e-d862-4c08-8291-67cada7b83a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345865922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3345865922
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.713123447
Short name T245
Test name
Test status
Simulation time 34878735940 ps
CPU time 22.16 seconds
Started Jul 11 05:46:25 PM PDT 24
Finished Jul 11 05:46:51 PM PDT 24
Peak memory 196992 kb
Host smart-b6228690-4aa7-4a10-963d-72996875f1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713123447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.713123447
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2132861864
Short name T229
Test name
Test status
Simulation time 538587622 ps
CPU time 1.31 seconds
Started Jul 11 05:46:19 PM PDT 24
Finished Jul 11 05:46:22 PM PDT 24
Peak memory 196720 kb
Host smart-20f9ec40-d579-4a69-8fc8-64cdea5d79f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132861864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2132861864
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2082037381
Short name T232
Test name
Test status
Simulation time 28951346633 ps
CPU time 20.1 seconds
Started Jul 11 05:46:45 PM PDT 24
Finished Jul 11 05:47:07 PM PDT 24
Peak memory 196920 kb
Host smart-8b8b2fc3-737c-408b-b3ea-217b31bc333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082037381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2082037381
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.838612185
Short name T216
Test name
Test status
Simulation time 497573472 ps
CPU time 0.77 seconds
Started Jul 11 05:46:24 PM PDT 24
Finished Jul 11 05:46:29 PM PDT 24
Peak memory 191920 kb
Host smart-1bb5d156-77eb-4945-bc46-f1caa6f5db05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838612185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.838612185
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3661562097
Short name T273
Test name
Test status
Simulation time 3113239103 ps
CPU time 1.63 seconds
Started Jul 11 05:46:30 PM PDT 24
Finished Jul 11 05:46:34 PM PDT 24
Peak memory 191944 kb
Host smart-ec0ee42e-7c68-477d-a564-ed3691603ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661562097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3661562097
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.556664351
Short name T3
Test name
Test status
Simulation time 601681568 ps
CPU time 0.99 seconds
Started Jul 11 05:46:21 PM PDT 24
Finished Jul 11 05:46:25 PM PDT 24
Peak memory 191904 kb
Host smart-09d89d21-b683-43e6-8023-bf07db952e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556664351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.556664351
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3224503746
Short name T249
Test name
Test status
Simulation time 27806213897 ps
CPU time 38.93 seconds
Started Jul 11 05:46:26 PM PDT 24
Finished Jul 11 05:47:09 PM PDT 24
Peak memory 197184 kb
Host smart-63263a58-71ae-491c-b1c6-ebbf4ba5de8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224503746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3224503746
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3382903670
Short name T272
Test name
Test status
Simulation time 584136892 ps
CPU time 1.49 seconds
Started Jul 11 05:46:37 PM PDT 24
Finished Jul 11 05:46:40 PM PDT 24
Peak memory 196708 kb
Host smart-9cae61b9-e9df-42d2-a111-7100402cdc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382903670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3382903670
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3392000648
Short name T218
Test name
Test status
Simulation time 27357818360 ps
CPU time 17.91 seconds
Started Jul 11 05:46:27 PM PDT 24
Finished Jul 11 05:46:48 PM PDT 24
Peak memory 192000 kb
Host smart-f26dfcb4-7240-4124-b579-02971db9be96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392000648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3392000648
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1427369232
Short name T8
Test name
Test status
Simulation time 491609742 ps
CPU time 0.78 seconds
Started Jul 11 05:46:29 PM PDT 24
Finished Jul 11 05:46:32 PM PDT 24
Peak memory 191868 kb
Host smart-5271d8e4-9bad-451c-a8cd-42206fec7025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427369232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1427369232
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3150897602
Short name T264
Test name
Test status
Simulation time 29986964061 ps
CPU time 2.64 seconds
Started Jul 11 05:46:30 PM PDT 24
Finished Jul 11 05:46:35 PM PDT 24
Peak memory 191876 kb
Host smart-43de979a-4b3d-469a-b358-83e1629b03c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150897602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3150897602
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.261239348
Short name T214
Test name
Test status
Simulation time 540272900 ps
CPU time 0.77 seconds
Started Jul 11 05:46:28 PM PDT 24
Finished Jul 11 05:46:32 PM PDT 24
Peak memory 196676 kb
Host smart-92c183df-7132-4a37-9f06-2acf17ed205e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261239348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.261239348
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.600709323
Short name T268
Test name
Test status
Simulation time 56120207465 ps
CPU time 21.73 seconds
Started Jul 11 05:46:26 PM PDT 24
Finished Jul 11 05:46:52 PM PDT 24
Peak memory 192176 kb
Host smart-6c87a674-7820-481a-bcd9-799e3feeba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600709323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.600709323
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1752872295
Short name T193
Test name
Test status
Simulation time 451769060 ps
CPU time 1.28 seconds
Started Jul 11 05:46:30 PM PDT 24
Finished Jul 11 05:46:33 PM PDT 24
Peak memory 191804 kb
Host smart-1152ab34-16e4-4d15-8253-e1be7729e0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752872295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1752872295
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1061527957
Short name T239
Test name
Test status
Simulation time 24295096442 ps
CPU time 32.97 seconds
Started Jul 11 05:46:30 PM PDT 24
Finished Jul 11 05:47:05 PM PDT 24
Peak memory 191932 kb
Host smart-89b6efa0-8423-4c18-be60-14b793466988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061527957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1061527957
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1078189837
Short name T202
Test name
Test status
Simulation time 403196749 ps
CPU time 0.67 seconds
Started Jul 11 05:46:33 PM PDT 24
Finished Jul 11 05:46:35 PM PDT 24
Peak memory 196816 kb
Host smart-09402188-15ea-41ae-ad9c-80524523b2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078189837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1078189837
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.697160500
Short name T247
Test name
Test status
Simulation time 19484917168 ps
CPU time 27.24 seconds
Started Jul 11 05:46:40 PM PDT 24
Finished Jul 11 05:47:09 PM PDT 24
Peak memory 191968 kb
Host smart-56c01d6d-28e1-43fa-aab6-aac1b26944b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697160500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.697160500
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1551077530
Short name T208
Test name
Test status
Simulation time 588238842 ps
CPU time 0.72 seconds
Started Jul 11 05:46:31 PM PDT 24
Finished Jul 11 05:46:34 PM PDT 24
Peak memory 196740 kb
Host smart-190a41b4-4652-4a11-8b87-7e827b69ed02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551077530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1551077530
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1065499364
Short name T175
Test name
Test status
Simulation time 406851984 ps
CPU time 0.87 seconds
Started Jul 11 05:46:35 PM PDT 24
Finished Jul 11 05:46:38 PM PDT 24
Peak memory 196700 kb
Host smart-fafacfcd-75dc-49d2-94b7-42548222f458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065499364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1065499364
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.634071477
Short name T194
Test name
Test status
Simulation time 13208297927 ps
CPU time 3.67 seconds
Started Jul 11 05:46:33 PM PDT 24
Finished Jul 11 05:46:38 PM PDT 24
Peak memory 192028 kb
Host smart-6b151441-bab2-4272-959e-69473a598659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634071477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.634071477
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4041706398
Short name T207
Test name
Test status
Simulation time 495760546 ps
CPU time 1.32 seconds
Started Jul 11 05:46:35 PM PDT 24
Finished Jul 11 05:46:38 PM PDT 24
Peak memory 191824 kb
Host smart-82c72caa-7291-4b86-a509-62902d0d5e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041706398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4041706398
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2066519839
Short name T276
Test name
Test status
Simulation time 31927657472 ps
CPU time 48.63 seconds
Started Jul 11 05:45:54 PM PDT 24
Finished Jul 11 05:46:46 PM PDT 24
Peak memory 191996 kb
Host smart-61e43f22-46d7-4ba6-896f-58cd4a7d78f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066519839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2066519839
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2214330727
Short name T15
Test name
Test status
Simulation time 4030282780 ps
CPU time 6.35 seconds
Started Jul 11 05:45:52 PM PDT 24
Finished Jul 11 05:46:01 PM PDT 24
Peak memory 215336 kb
Host smart-8f31173a-9517-465a-8d01-a67eab68338c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214330727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2214330727
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.464513510
Short name T244
Test name
Test status
Simulation time 453151329 ps
CPU time 0.7 seconds
Started Jul 11 05:45:56 PM PDT 24
Finished Jul 11 05:45:59 PM PDT 24
Peak memory 196776 kb
Host smart-f344b768-9dd3-4360-9972-38b154d92363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464513510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.464513510
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1574468870
Short name T62
Test name
Test status
Simulation time 440792435 ps
CPU time 1.36 seconds
Started Jul 11 05:46:59 PM PDT 24
Finished Jul 11 05:47:03 PM PDT 24
Peak memory 196756 kb
Host smart-edf27fac-94af-4daf-86bb-a29f301fa97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574468870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1574468870
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3162191153
Short name T219
Test name
Test status
Simulation time 27162520747 ps
CPU time 2.51 seconds
Started Jul 11 05:46:31 PM PDT 24
Finished Jul 11 05:46:35 PM PDT 24
Peak memory 191992 kb
Host smart-95f4a737-247e-487d-9ac2-514fe61ddd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162191153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3162191153
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1307954592
Short name T198
Test name
Test status
Simulation time 490826723 ps
CPU time 0.93 seconds
Started Jul 11 05:46:49 PM PDT 24
Finished Jul 11 05:46:53 PM PDT 24
Peak memory 191820 kb
Host smart-aac216c7-f98c-490a-8e63-4bbe367be577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307954592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1307954592
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3725140487
Short name T279
Test name
Test status
Simulation time 28890900439 ps
CPU time 11.36 seconds
Started Jul 11 05:46:28 PM PDT 24
Finished Jul 11 05:46:42 PM PDT 24
Peak memory 191980 kb
Host smart-e14e3565-31c3-43d1-9253-96c077687643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725140487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3725140487
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1045257559
Short name T269
Test name
Test status
Simulation time 393103418 ps
CPU time 0.72 seconds
Started Jul 11 05:46:41 PM PDT 24
Finished Jul 11 05:46:43 PM PDT 24
Peak memory 191912 kb
Host smart-d4aa03f2-6539-4698-bcfc-66a5d366be09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045257559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1045257559
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3667849316
Short name T210
Test name
Test status
Simulation time 33085095329 ps
CPU time 12.72 seconds
Started Jul 11 05:46:31 PM PDT 24
Finished Jul 11 05:46:46 PM PDT 24
Peak memory 196972 kb
Host smart-d869b870-9843-47e9-b52f-a63399a6575e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667849316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3667849316
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1563979857
Short name T222
Test name
Test status
Simulation time 436473015 ps
CPU time 1.17 seconds
Started Jul 11 05:46:35 PM PDT 24
Finished Jul 11 05:46:38 PM PDT 24
Peak memory 191940 kb
Host smart-5b2d6365-376b-4fb0-ab1d-34a40c4163e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563979857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1563979857
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1588013117
Short name T179
Test name
Test status
Simulation time 456845788 ps
CPU time 0.71 seconds
Started Jul 11 05:46:37 PM PDT 24
Finished Jul 11 05:46:39 PM PDT 24
Peak memory 196716 kb
Host smart-5f717ab8-029f-4cac-bcbb-81a0b0650598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588013117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1588013117
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2296882598
Short name T263
Test name
Test status
Simulation time 29361307734 ps
CPU time 25.28 seconds
Started Jul 11 05:46:42 PM PDT 24
Finished Jul 11 05:47:09 PM PDT 24
Peak memory 191932 kb
Host smart-e1f06225-0924-41fb-a53e-628beb54b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296882598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2296882598
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.533897512
Short name T251
Test name
Test status
Simulation time 603597354 ps
CPU time 0.62 seconds
Started Jul 11 05:46:41 PM PDT 24
Finished Jul 11 05:46:44 PM PDT 24
Peak memory 191928 kb
Host smart-877698b3-339f-450e-86fc-275982f9cbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533897512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.533897512
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2284522368
Short name T225
Test name
Test status
Simulation time 42041483142 ps
CPU time 14.63 seconds
Started Jul 11 05:46:35 PM PDT 24
Finished Jul 11 05:46:51 PM PDT 24
Peak memory 191988 kb
Host smart-87a64a1c-ed50-4e76-89a5-41f45902ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284522368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2284522368
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.166281489
Short name T277
Test name
Test status
Simulation time 517607586 ps
CPU time 0.89 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:47:17 PM PDT 24
Peak memory 196688 kb
Host smart-be2f7086-202a-4be8-a9c1-540b815e5a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166281489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.166281489
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.781664919
Short name T38
Test name
Test status
Simulation time 17171614299 ps
CPU time 2.68 seconds
Started Jul 11 05:46:40 PM PDT 24
Finished Jul 11 05:46:45 PM PDT 24
Peak memory 191964 kb
Host smart-d118257b-0760-44b1-91c2-5f53fd7979a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781664919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.781664919
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1422199731
Short name T234
Test name
Test status
Simulation time 489120436 ps
CPU time 1.32 seconds
Started Jul 11 05:47:14 PM PDT 24
Finished Jul 11 05:47:17 PM PDT 24
Peak memory 191920 kb
Host smart-c622a21d-02a0-4a46-b3b4-4f038de2a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422199731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1422199731
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3033137973
Short name T256
Test name
Test status
Simulation time 3844228536 ps
CPU time 6.3 seconds
Started Jul 11 05:46:43 PM PDT 24
Finished Jul 11 05:46:51 PM PDT 24
Peak memory 196768 kb
Host smart-34ee09c8-a0b2-423b-8010-88fd27bd8ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033137973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3033137973
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4154121136
Short name T211
Test name
Test status
Simulation time 390430635 ps
CPU time 0.75 seconds
Started Jul 11 05:46:49 PM PDT 24
Finished Jul 11 05:46:53 PM PDT 24
Peak memory 196716 kb
Host smart-d89afd6f-cd60-4c85-820d-a84cb98de722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154121136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4154121136
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2312771596
Short name T155
Test name
Test status
Simulation time 14000400720 ps
CPU time 114.76 seconds
Started Jul 11 05:46:44 PM PDT 24
Finished Jul 11 05:48:41 PM PDT 24
Peak memory 206808 kb
Host smart-c687b450-b567-4dab-8b69-3c188ab33977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312771596 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2312771596
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.4185011074
Short name T237
Test name
Test status
Simulation time 8271522537 ps
CPU time 3.54 seconds
Started Jul 11 05:46:43 PM PDT 24
Finished Jul 11 05:46:48 PM PDT 24
Peak memory 196996 kb
Host smart-16831aef-6df3-4f30-8ae4-ebf779142c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185011074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.4185011074
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2075806462
Short name T231
Test name
Test status
Simulation time 480826564 ps
CPU time 1.19 seconds
Started Jul 11 05:46:47 PM PDT 24
Finished Jul 11 05:46:50 PM PDT 24
Peak memory 196772 kb
Host smart-5e606e7e-b4da-44c0-ac87-fe462675d770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075806462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2075806462
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1879854219
Short name T265
Test name
Test status
Simulation time 56084839221 ps
CPU time 22.28 seconds
Started Jul 11 05:46:47 PM PDT 24
Finished Jul 11 05:47:11 PM PDT 24
Peak memory 191980 kb
Host smart-71ecc40e-ac4d-40e2-98c8-474e3e8a7609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879854219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1879854219
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1384711555
Short name T217
Test name
Test status
Simulation time 403250230 ps
CPU time 0.76 seconds
Started Jul 11 05:46:49 PM PDT 24
Finished Jul 11 05:46:53 PM PDT 24
Peak memory 191928 kb
Host smart-f7ee4d29-87f3-4500-a545-66bc3cd4af8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384711555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1384711555
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1447491265
Short name T271
Test name
Test status
Simulation time 27782593897 ps
CPU time 19.87 seconds
Started Jul 11 05:46:51 PM PDT 24
Finished Jul 11 05:47:14 PM PDT 24
Peak memory 191916 kb
Host smart-4e588779-98eb-4856-b912-769d28d3c888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447491265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1447491265
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1646139644
Short name T241
Test name
Test status
Simulation time 582337925 ps
CPU time 1.28 seconds
Started Jul 11 05:46:48 PM PDT 24
Finished Jul 11 05:46:51 PM PDT 24
Peak memory 191948 kb
Host smart-2f773220-d238-405a-a28a-e0324695b53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646139644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1646139644
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3524298937
Short name T41
Test name
Test status
Simulation time 456722742 ps
CPU time 1.25 seconds
Started Jul 11 05:45:53 PM PDT 24
Finished Jul 11 05:45:57 PM PDT 24
Peak memory 196796 kb
Host smart-b44dfe09-3e8e-4de5-b7de-273d93e68812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524298937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3524298937
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2076949322
Short name T61
Test name
Test status
Simulation time 1088716952 ps
CPU time 0.99 seconds
Started Jul 11 05:45:47 PM PDT 24
Finished Jul 11 05:45:51 PM PDT 24
Peak memory 191924 kb
Host smart-e85f6b35-d51e-4842-8062-e1a42d6635e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076949322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2076949322
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3046276669
Short name T199
Test name
Test status
Simulation time 510716935 ps
CPU time 1.21 seconds
Started Jul 11 05:45:54 PM PDT 24
Finished Jul 11 05:45:58 PM PDT 24
Peak memory 196756 kb
Host smart-150063fc-6e25-4172-98f0-cd89b4bb7b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046276669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3046276669
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4027684065
Short name T10
Test name
Test status
Simulation time 5111150256 ps
CPU time 4.7 seconds
Started Jul 11 05:46:05 PM PDT 24
Finished Jul 11 05:46:13 PM PDT 24
Peak memory 191940 kb
Host smart-755b5f17-3d5f-4cce-9f25-f06dc290ca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027684065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4027684065
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.481586462
Short name T236
Test name
Test status
Simulation time 577082436 ps
CPU time 0.71 seconds
Started Jul 11 05:45:59 PM PDT 24
Finished Jul 11 05:46:03 PM PDT 24
Peak memory 191928 kb
Host smart-cd4bec90-86ff-493e-88a3-4559b17ebfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481586462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.481586462
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.869498152
Short name T224
Test name
Test status
Simulation time 36932237359 ps
CPU time 48.95 seconds
Started Jul 11 05:46:00 PM PDT 24
Finished Jul 11 05:46:52 PM PDT 24
Peak memory 196932 kb
Host smart-bcab27bf-faff-4531-988a-7b3af6f5f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869498152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.869498152
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2927443704
Short name T230
Test name
Test status
Simulation time 494238528 ps
CPU time 1.2 seconds
Started Jul 11 05:46:04 PM PDT 24
Finished Jul 11 05:46:08 PM PDT 24
Peak memory 191808 kb
Host smart-b41cacfa-58e1-41a5-81e2-2fd482a5ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927443704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2927443704
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.56423708
Short name T238
Test name
Test status
Simulation time 30990641836 ps
CPU time 9.73 seconds
Started Jul 11 05:46:02 PM PDT 24
Finished Jul 11 05:46:14 PM PDT 24
Peak memory 191992 kb
Host smart-d7d993af-46a2-4e4b-b170-fbb3427c5140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56423708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.56423708
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3471289963
Short name T253
Test name
Test status
Simulation time 551372142 ps
CPU time 0.96 seconds
Started Jul 11 05:45:59 PM PDT 24
Finished Jul 11 05:46:03 PM PDT 24
Peak memory 196580 kb
Host smart-caebe469-216b-4435-b85a-9dfca7b90237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471289963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3471289963
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.4041670606
Short name T270
Test name
Test status
Simulation time 36892807770 ps
CPU time 56.65 seconds
Started Jul 11 05:46:01 PM PDT 24
Finished Jul 11 05:47:01 PM PDT 24
Peak memory 196972 kb
Host smart-396afb5f-2c83-4a3f-a8ca-9d4b4f97ca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041670606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.4041670606
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1523947975
Short name T204
Test name
Test status
Simulation time 427611882 ps
CPU time 0.75 seconds
Started Jul 11 05:46:00 PM PDT 24
Finished Jul 11 05:46:04 PM PDT 24
Peak memory 191936 kb
Host smart-606d48b5-5101-42cd-a211-4e757b8b6484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523947975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1523947975
Directory /workspace/9.aon_timer_smoke/latest
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