Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	27506	1		T1	1317		T2	12		T4	11
bark[1]	358	1		T30	21		T122	14		T172	21
bark[2]	452	1		T3	14		T8	21		T30	21
bark[3]	1103	1		T8	21		T28	225		T23	44
bark[4]	624	1		T25	21		T42	56		T159	7
bark[5]	671	1		T5	40		T30	31		T25	31
bark[6]	603	1		T1	21		T21	261		T25	26
bark[7]	425	1		T10	7		T29	38		T22	21
bark[8]	848	1		T28	21		T172	26		T107	21
bark[9]	947	1		T1	21		T8	235		T159	316
bark[10]	463	1		T12	42		T24	21		T105	14
bark[11]	481	1		T30	21		T21	201		T22	21
bark[12]	360	1		T29	38		T23	38		T159	66
bark[13]	751	1		T11	39		T25	151		T121	38
bark[14]	233	1		T22	21		T24	57		T44	31
bark[15]	499	1		T1	21		T8	21		T31	21
bark[16]	362	1		T44	21		T165	64		T103	21
bark[17]	469	1		T8	21		T31	21		T25	94
bark[18]	1211	1		T10	26		T11	14		T31	30
bark[19]	518	1		T24	39		T121	30		T97	21
bark[20]	344	1		T1	21		T21	159		T22	21
bark[21]	554	1		T10	21		T12	94		T149	70
bark[22]	773	1		T1	21		T19	14		T42	52
bark[23]	536	1		T23	30		T89	220		T138	21
bark[24]	518	1		T8	92		T23	21		T152	14
bark[25]	174	1		T1	7		T153	14		T133	21
bark[26]	501	1		T28	56		T97	21		T92	166
bark[27]	670	1		T24	38		T146	14		T130	42
bark[28]	736	1		T13	21		T28	21		T31	42
bark[29]	440	1		T1	45		T10	21		T12	47
bark[30]	222	1		T29	21		T21	21		T131	21
bark[31]	895	1		T8	21		T11	21		T13	87
bark_0	4632	1		T1	111		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	27553	1		T1	1309		T2	11		T4	10
bite[1]	475	1		T13	21		T28	21		T44	21
bite[2]	562	1		T12	21		T29	38		T30	21
bite[3]	711	1		T1	21		T8	91		T21	21
bite[4]	566	1		T1	6		T10	6		T13	87
bite[5]	791	1		T8	234		T28	224		T30	30
bite[6]	203	1		T1	21		T31	21		T23	51
bite[7]	301	1		T12	72		T121	26		T42	21
bite[8]	696	1		T8	21		T29	21		T19	13
bite[9]	607	1		T8	21		T122	13		T121	21
bite[10]	603	1		T29	38		T31	30		T24	38
bite[11]	1245	1		T23	22		T44	31		T156	13
bite[12]	388	1		T30	21		T42	21		T129	21
bite[13]	715	1		T12	21		T25	202		T121	30
bite[14]	254	1		T22	21		T132	13		T180	13
bite[15]	865	1		T21	200		T25	150		T103	21
bite[16]	642	1		T1	21		T80	13		T172	26
bite[17]	898	1		T104	21		T137	36		T107	21
bite[18]	292	1		T8	21		T31	42		T23	40
bite[19]	242	1		T12	25		T21	21		T89	21
bite[20]	286	1		T89	4		T97	21		T91	21
bite[21]	899	1		T8	42		T11	39		T21	137
bite[22]	608	1		T5	40		T100	39		T182	13
bite[23]	202	1		T1	21		T82	13		T104	13
bite[24]	642	1		T10	46		T22	21		T23	21
bite[25]	131	1		T97	21		T176	13		T131	21
bite[26]	358	1		T22	26		T104	26		T129	202
bite[27]	485	1		T31	21		T40	21		T89	21
bite[28]	314	1		T3	13		T28	21		T121	38
bite[29]	398	1		T1	65		T11	21		T28	55
bite[30]	644	1		T10	21		T11	13		T43	13
bite[31]	1106	1		T12	25		T30	21		T24	39
bite_0	5197	1		T1	121		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	42150	1		T1	1316		T2	19		T3	21
auto[1]	7729	1		T1	269		T8	249		T10	476

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	706	1		T8	106		T13	29		T91	151
prescale[1]	1002	1		T1	56		T8	19		T10	55
prescale[2]	1299	1		T10	40		T28	64		T160	53
prescale[3]	783	1		T1	50		T13	49		T21	85
prescale[4]	769	1		T1	101		T8	57		T42	79
prescale[5]	971	1		T8	28		T10	145		T12	2
prescale[6]	589	1		T1	60		T13	45		T22	9
prescale[7]	1333	1		T8	19		T21	63		T41	2
prescale[8]	517	1		T1	45		T29	19		T21	41
prescale[9]	676	1		T1	139		T5	19		T21	58
prescale[10]	472	1		T2	9		T10	19		T12	49
prescale[11]	961	1		T10	95		T28	101		T21	9
prescale[12]	809	1		T1	110		T8	9		T21	33
prescale[13]	699	1		T8	79		T11	45		T25	19
prescale[14]	812	1		T10	2		T11	47		T28	99
prescale[15]	1366	1		T5	9		T8	33		T12	2
prescale[16]	691	1		T1	2		T8	110		T12	108
prescale[17]	662	1		T12	19		T21	4		T23	23
prescale[18]	578	1		T1	19		T8	66		T10	2
prescale[19]	657	1		T1	19		T12	19		T20	9
prescale[20]	492	1		T10	2		T21	2		T42	255
prescale[21]	1338	1		T1	19		T7	9		T8	130
prescale[22]	770	1		T8	41		T21	2		T121	14
prescale[23]	1028	1		T1	11		T8	21		T29	19
prescale[24]	551	1		T24	26		T25	2		T40	2
prescale[25]	552	1		T8	14		T29	28		T100	23
prescale[26]	547	1		T1	192		T8	40		T28	2
prescale[27]	824	1		T5	57		T8	106		T30	68
prescale[28]	605	1		T8	99		T10	2		T12	54
prescale[29]	650	1		T8	2		T10	4		T21	14
prescale[30]	664	1		T5	28		T8	45		T21	24
prescale[31]	1095	1		T1	227		T8	2		T12	26
prescale_0	24411	1		T1	535		T2	10		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36872	1		T1	1193		T2	9		T3	21
auto[1]	13007	1		T1	392		T2	10		T4	9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	49879	1		T1	1585		T2	19		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	29693	1		T1	1064		T2	14		T3	1
wkup[1]	200	1		T30	21		T21	21		T121	21
wkup[2]	247	1		T10	21		T28	21		T42	21
wkup[3]	324	1		T8	42		T42	29		T159	21
wkup[4]	407	1		T8	30		T10	6		T31	15
wkup[5]	146	1		T42	21		T159	21		T163	26
wkup[6]	170	1		T8	63		T165	21		T96	35
wkup[7]	174	1		T23	24		T25	21		T167	21
wkup[8]	170	1		T138	21		T171	26		T96	21
wkup[9]	425	1		T1	24		T8	21		T10	21
wkup[10]	296	1		T24	39		T89	21		T91	21
wkup[11]	243	1		T10	21		T28	21		T97	21
wkup[12]	196	1		T1	21		T10	21		T28	15
wkup[13]	258	1		T1	35		T28	21		T89	21
wkup[14]	175	1		T25	21		T89	21		T129	8
wkup[15]	198	1		T25	21		T80	15		T138	21
wkup[16]	177	1		T1	21		T8	21		T12	15
wkup[17]	240	1		T10	42		T30	21		T23	30
wkup[18]	294	1		T21	21		T24	21		T42	26
wkup[19]	181	1		T25	21		T121	21		T89	21
wkup[20]	374	1		T1	21		T8	60		T10	21
wkup[21]	285	1		T1	51		T10	26		T159	21
wkup[22]	267	1		T1	21		T30	21		T21	21
wkup[23]	275	1		T10	8		T13	21		T23	21
wkup[24]	384	1		T28	21		T21	21		T160	21
wkup[25]	275	1		T1	21		T12	21		T21	39
wkup[26]	313	1		T1	21		T10	21		T31	21
wkup[27]	162	1		T13	21		T91	36		T163	21
wkup[28]	133	1		T30	21		T42	21		T171	8
wkup[29]	186	1		T5	30		T28	21		T25	21
wkup[30]	271	1		T11	15		T12	26		T25	21
wkup[31]	236	1		T1	72		T12	21		T42	21
wkup[32]	221	1		T1	15		T8	21		T138	30
wkup[33]	271	1		T8	21		T12	35		T42	21
wkup[34]	146	1		T22	21		T131	15		T154	26
wkup[35]	224	1		T12	21		T22	21		T171	30
wkup[36]	419	1		T8	21		T21	21		T121	26
wkup[37]	154	1		T5	40		T149	15		T103	21
wkup[38]	316	1		T8	26		T21	42		T149	21
wkup[39]	367	1		T5	21		T40	21		T91	21
wkup[40]	374	1		T12	21		T100	21		T42	21
wkup[41]	371	1		T3	15		T8	21		T25	21
wkup[42]	335	1		T21	21		T23	21		T172	26
wkup[43]	212	1		T1	8		T10	15		T21	21
wkup[44]	155	1		T109	21		T94	21		T87	21
wkup[45]	257	1		T1	21		T156	15		T104	15
wkup[46]	330	1		T1	15		T8	21		T22	21
wkup[47]	356	1		T10	21		T28	21		T24	21
wkup[48]	325	1		T8	21		T12	15		T42	8
wkup[49]	249	1		T8	21		T31	21		T42	30
wkup[50]	167	1		T8	21		T21	21		T89	21
wkup[51]	331	1		T1	21		T12	21		T25	21
wkup[52]	304	1		T11	21		T12	21		T25	26
wkup[53]	152	1		T28	21		T171	21		T108	21
wkup[54]	398	1		T1	21		T8	21		T29	21
wkup[55]	261	1		T40	21		T42	30		T159	30
wkup[56]	243	1		T1	21		T43	15		T29	21
wkup[57]	215	1		T22	47		T122	15		T129	61
wkup[58]	313	1		T28	30		T182	15		T163	35
wkup[59]	194	1		T21	21		T44	21		T91	35
wkup[60]	364	1		T8	21		T11	39		T12	21
wkup[61]	262	1		T31	30		T21	21		T121	21
wkup[62]	261	1		T8	21		T10	15		T12	21
wkup[63]	313	1		T21	21		T159	21		T99	21
wkup_0	3644	1		T1	91		T2	5		T3	5