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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.60 99.33 93.67 100.00 98.40 99.51 46.72


Total test records in report: 423
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T38 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2264291372 Jul 12 05:54:28 PM PDT 24 Jul 12 05:54:30 PM PDT 24 702730846 ps
T39 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1361136145 Jul 12 05:54:35 PM PDT 24 Jul 12 05:54:40 PM PDT 24 4994351784 ps
T33 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4066880894 Jul 12 05:54:56 PM PDT 24 Jul 12 05:54:59 PM PDT 24 1408613375 ps
T34 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1550942002 Jul 12 05:54:41 PM PDT 24 Jul 12 05:54:43 PM PDT 24 402282981 ps
T286 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3999797695 Jul 12 05:55:03 PM PDT 24 Jul 12 05:55:04 PM PDT 24 319313577 ps
T35 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.590155106 Jul 12 05:54:53 PM PDT 24 Jul 12 05:55:10 PM PDT 24 8828032403 ps
T71 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.535388177 Jul 12 05:54:48 PM PDT 24 Jul 12 05:54:53 PM PDT 24 1155858240 ps
T198 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3996645903 Jul 12 05:54:43 PM PDT 24 Jul 12 05:54:45 PM PDT 24 550280285 ps
T199 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3738071907 Jul 12 05:54:46 PM PDT 24 Jul 12 05:54:49 PM PDT 24 428679977 ps
T287 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2673526286 Jul 12 05:55:04 PM PDT 24 Jul 12 05:55:06 PM PDT 24 422140072 ps
T288 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.375964293 Jul 12 05:54:29 PM PDT 24 Jul 12 05:54:32 PM PDT 24 500375027 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2880660667 Jul 12 05:54:30 PM PDT 24 Jul 12 05:54:35 PM PDT 24 650787706 ps
T290 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1115671026 Jul 12 05:55:01 PM PDT 24 Jul 12 05:55:03 PM PDT 24 473570498 ps
T291 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.103206544 Jul 12 05:54:45 PM PDT 24 Jul 12 05:54:49 PM PDT 24 616765857 ps
T292 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2751597162 Jul 12 05:55:00 PM PDT 24 Jul 12 05:55:02 PM PDT 24 292562631 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3253657115 Jul 12 05:54:41 PM PDT 24 Jul 12 05:54:43 PM PDT 24 705749846 ps
T72 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.369567020 Jul 12 05:54:56 PM PDT 24 Jul 12 05:55:02 PM PDT 24 2715243001 ps
T73 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.615285349 Jul 12 05:54:49 PM PDT 24 Jul 12 05:54:54 PM PDT 24 2974964428 ps
T293 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3449355265 Jul 12 05:54:46 PM PDT 24 Jul 12 05:54:50 PM PDT 24 648133966 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2830636293 Jul 12 05:54:33 PM PDT 24 Jul 12 05:55:11 PM PDT 24 13099901612 ps
T294 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2904676937 Jul 12 05:54:57 PM PDT 24 Jul 12 05:55:01 PM PDT 24 680275219 ps
T295 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2103111403 Jul 12 05:54:37 PM PDT 24 Jul 12 05:54:39 PM PDT 24 325352319 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.337664436 Jul 12 05:54:40 PM PDT 24 Jul 12 05:54:42 PM PDT 24 989523721 ps
T296 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3553262960 Jul 12 05:54:45 PM PDT 24 Jul 12 05:54:48 PM PDT 24 447789125 ps
T297 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2389226467 Jul 12 05:54:43 PM PDT 24 Jul 12 05:54:46 PM PDT 24 757391129 ps
T59 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3446234200 Jul 12 05:54:32 PM PDT 24 Jul 12 05:54:51 PM PDT 24 7107439315 ps
T36 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3330668341 Jul 12 05:54:39 PM PDT 24 Jul 12 05:54:43 PM PDT 24 4555623566 ps
T298 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2321803649 Jul 12 05:55:04 PM PDT 24 Jul 12 05:55:07 PM PDT 24 562222608 ps
T299 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2146432132 Jul 12 05:54:34 PM PDT 24 Jul 12 05:54:38 PM PDT 24 384479257 ps
T74 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1176870704 Jul 12 05:54:43 PM PDT 24 Jul 12 05:54:50 PM PDT 24 2198281741 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2262889243 Jul 12 05:54:39 PM PDT 24 Jul 12 05:54:41 PM PDT 24 422157247 ps
T75 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.210167882 Jul 12 05:54:46 PM PDT 24 Jul 12 05:54:50 PM PDT 24 1504815154 ps
T300 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3011336728 Jul 12 05:54:29 PM PDT 24 Jul 12 05:54:32 PM PDT 24 411831693 ps
T301 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.745531183 Jul 12 05:55:01 PM PDT 24 Jul 12 05:55:03 PM PDT 24 516484197 ps
T302 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3510852327 Jul 12 05:54:48 PM PDT 24 Jul 12 05:54:52 PM PDT 24 500619433 ps
T303 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.555566425 Jul 12 05:55:03 PM PDT 24 Jul 12 05:55:05 PM PDT 24 333879393 ps
T304 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.133425543 Jul 12 05:55:05 PM PDT 24 Jul 12 05:55:07 PM PDT 24 376247364 ps
T76 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2073489262 Jul 12 05:54:35 PM PDT 24 Jul 12 05:54:39 PM PDT 24 449937404 ps
T305 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3654903285 Jul 12 05:54:56 PM PDT 24 Jul 12 05:54:58 PM PDT 24 494840053 ps
T77 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.491585166 Jul 12 05:54:39 PM PDT 24 Jul 12 05:54:42 PM PDT 24 1311690314 ps
T306 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3091067277 Jul 12 05:54:48 PM PDT 24 Jul 12 05:54:52 PM PDT 24 419955001 ps
T78 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2904122496 Jul 12 05:54:44 PM PDT 24 Jul 12 05:54:47 PM PDT 24 2339318603 ps
T194 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.822737519 Jul 12 05:54:44 PM PDT 24 Jul 12 05:54:50 PM PDT 24 8715418041 ps
T307 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2548670178 Jul 12 05:55:01 PM PDT 24 Jul 12 05:55:04 PM PDT 24 336600658 ps
T308 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1931846646 Jul 12 05:54:54 PM PDT 24 Jul 12 05:54:57 PM PDT 24 384100243 ps
T309 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2722403527 Jul 12 05:54:55 PM PDT 24 Jul 12 05:54:58 PM PDT 24 328557771 ps
T310 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2302460693 Jul 12 05:55:01 PM PDT 24 Jul 12 05:55:03 PM PDT 24 483334174 ps
T311 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.677711739 Jul 12 05:55:05 PM PDT 24 Jul 12 05:55:07 PM PDT 24 435656613 ps
T312 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.210710565 Jul 12 05:54:49 PM PDT 24 Jul 12 05:54:59 PM PDT 24 8810764512 ps
T313 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.537773707 Jul 12 05:54:56 PM PDT 24 Jul 12 05:54:59 PM PDT 24 364627350 ps
T314 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4027385401 Jul 12 05:54:36 PM PDT 24 Jul 12 05:54:39 PM PDT 24 522279154 ps
T315 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3299904065 Jul 12 05:54:57 PM PDT 24 Jul 12 05:55:02 PM PDT 24 2798168387 ps
T316 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3059849972 Jul 12 05:54:50 PM PDT 24 Jul 12 05:54:55 PM PDT 24 434838761 ps
T61 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2144625667 Jul 12 05:54:48 PM PDT 24 Jul 12 05:54:52 PM PDT 24 525730115 ps
T317 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1549232832 Jul 12 05:55:03 PM PDT 24 Jul 12 05:55:04 PM PDT 24 596203319 ps
T62 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3426162863 Jul 12 05:54:29 PM PDT 24 Jul 12 05:54:33 PM PDT 24 316454292 ps
T318 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3543432918 Jul 12 05:55:03 PM PDT 24 Jul 12 05:55:11 PM PDT 24 4016626112 ps
T319 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.511340541 Jul 12 05:54:28 PM PDT 24 Jul 12 05:54:30 PM PDT 24 294664132 ps
T320 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2494903372 Jul 12 05:54:40 PM PDT 24 Jul 12 05:54:48 PM PDT 24 8003042456 ps
T321 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2676713522 Jul 12 05:54:37 PM PDT 24 Jul 12 05:54:40 PM PDT 24 539532210 ps
T322 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1547669985 Jul 12 05:54:35 PM PDT 24 Jul 12 05:54:38 PM PDT 24 441878413 ps
T323 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2144880768 Jul 12 05:54:39 PM PDT 24 Jul 12 05:54:42 PM PDT 24 506153184 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1889100604 Jul 12 05:54:49 PM PDT 24 Jul 12 05:54:54 PM PDT 24 1186455194 ps
T325 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2543711619 Jul 12 05:54:34 PM PDT 24 Jul 12 05:54:38 PM PDT 24 440234662 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4079547031 Jul 12 05:54:39 PM PDT 24 Jul 12 05:54:41 PM PDT 24 328771666 ps
T327 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3772121769 Jul 12 05:54:44 PM PDT 24 Jul 12 05:54:48 PM PDT 24 1370322800 ps
T328 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3968796112 Jul 12 05:55:03 PM PDT 24 Jul 12 05:55:05 PM PDT 24 345577019 ps
T329 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3087610516 Jul 12 05:54:39 PM PDT 24 Jul 12 05:54:42 PM PDT 24 753489199 ps
T63 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1429907190 Jul 12 05:54:43 PM PDT 24 Jul 12 05:54:44 PM PDT 24 488811334 ps
T330 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2820570136 Jul 12 05:54:47 PM PDT 24 Jul 12 05:54:53 PM PDT 24 606563258 ps
T331 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2618751636 Jul 12 05:54:56 PM PDT 24 Jul 12 05:54:59 PM PDT 24 495569912 ps
T332 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.133554233 Jul 12 05:55:04 PM PDT 24 Jul 12 05:55:06 PM PDT 24 604728895 ps
T333 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2367252641 Jul 12 05:54:49 PM PDT 24 Jul 12 05:55:06 PM PDT 24 8078146940 ps
T334 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1617337636 Jul 12 05:54:47 PM PDT 24 Jul 12 05:54:51 PM PDT 24 424384130 ps
T335 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.674810836 Jul 12 05:54:34 PM PDT 24 Jul 12 05:54:38 PM PDT 24 693515875 ps
T64 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4193465063 Jul 12 05:54:35 PM PDT 24 Jul 12 05:54:38 PM PDT 24 593705345 ps
T336 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.178476602 Jul 12 05:55:02 PM PDT 24 Jul 12 05:55:04 PM PDT 24 349268279 ps
T337 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.878352570 Jul 12 05:55:01 PM PDT 24 Jul 12 05:55:03 PM PDT 24 449378338 ps
T338 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.744018093 Jul 12 05:54:48 PM PDT 24 Jul 12 05:54:54 PM PDT 24 743178786 ps
T339 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3574242553 Jul 12 05:54:36 PM PDT 24 Jul 12 05:54:40 PM PDT 24 589073291 ps
T340 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.202806691 Jul 12 05:54:44 PM PDT 24 Jul 12 05:54:48 PM PDT 24 8742540176 ps
T341 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1559580923 Jul 12 05:55:04 PM PDT 24 Jul 12 05:55:06 PM PDT 24 528069180 ps
T195 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2609550614 Jul 12 05:54:45 PM PDT 24 Jul 12 05:54:49 PM PDT 24 9122722459 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3078765076 Jul 12 05:54:35 PM PDT 24 Jul 12 05:54:39 PM PDT 24 668495013 ps
T342 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2349387545 Jul 12 05:54:32 PM PDT 24 Jul 12 05:54:36 PM PDT 24 2637442688 ps
T343 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.979432037 Jul 12 05:54:56 PM PDT 24 Jul 12 05:55:03 PM PDT 24 8031623858 ps
T344 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1688576018 Jul 12 05:54:33 PM PDT 24 Jul 12 05:54:38 PM PDT 24 2751482416 ps
T345 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3276475722 Jul 12 05:55:02 PM PDT 24 Jul 12 05:55:04 PM PDT 24 456534957 ps
T346 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.678924892 Jul 12 05:54:57 PM PDT 24 Jul 12 05:55:01 PM PDT 24 470966184 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4216139508 Jul 12 05:54:31 PM PDT 24 Jul 12 05:54:35 PM PDT 24 2023889119 ps
T348 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.94298218 Jul 12 05:54:39 PM PDT 24 Jul 12 05:54:41 PM PDT 24 339864289 ps
T349 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1810328292 Jul 12 05:54:46 PM PDT 24 Jul 12 05:54:49 PM PDT 24 312768526 ps
T350 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3743573058 Jul 12 05:54:28 PM PDT 24 Jul 12 05:54:33 PM PDT 24 1179919147 ps
T351 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1070404986 Jul 12 05:54:58 PM PDT 24 Jul 12 05:55:00 PM PDT 24 322737726 ps
T67 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1827308575 Jul 12 05:54:42 PM PDT 24 Jul 12 05:54:44 PM PDT 24 368306680 ps
T352 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.865032049 Jul 12 05:54:48 PM PDT 24 Jul 12 05:54:53 PM PDT 24 719218528 ps
T353 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3045473108 Jul 12 05:54:46 PM PDT 24 Jul 12 05:54:50 PM PDT 24 1212608647 ps
T354 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2241194121 Jul 12 05:54:34 PM PDT 24 Jul 12 05:54:38 PM PDT 24 497580156 ps
T355 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.137701700 Jul 12 05:54:58 PM PDT 24 Jul 12 05:55:00 PM PDT 24 410204669 ps
T356 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.305184192 Jul 12 05:54:33 PM PDT 24 Jul 12 05:54:36 PM PDT 24 312029553 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1166695508 Jul 12 05:54:32 PM PDT 24 Jul 12 05:54:35 PM PDT 24 370245357 ps
T358 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2325661 Jul 12 05:54:50 PM PDT 24 Jul 12 05:54:54 PM PDT 24 462384185 ps
T68 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2255183306 Jul 12 05:54:50 PM PDT 24 Jul 12 05:54:54 PM PDT 24 274144217 ps
T359 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1872316301 Jul 12 05:54:33 PM PDT 24 Jul 12 05:54:35 PM PDT 24 367654152 ps
T360 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3163547943 Jul 12 05:54:44 PM PDT 24 Jul 12 05:54:46 PM PDT 24 519717469 ps
T361 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.619146082 Jul 12 05:54:44 PM PDT 24 Jul 12 05:54:46 PM PDT 24 346965501 ps
T362 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.862559123 Jul 12 05:54:42 PM PDT 24 Jul 12 05:54:44 PM PDT 24 359709263 ps
T363 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2175458807 Jul 12 05:54:46 PM PDT 24 Jul 12 05:54:51 PM PDT 24 394434315 ps
T364 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.588984357 Jul 12 05:54:48 PM PDT 24 Jul 12 05:54:52 PM PDT 24 506923230 ps
T365 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2780982065 Jul 12 05:54:40 PM PDT 24 Jul 12 05:54:46 PM PDT 24 7612867588 ps
T366 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2235232100 Jul 12 05:54:59 PM PDT 24 Jul 12 05:55:01 PM PDT 24 449466922 ps
T367 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.218033372 Jul 12 05:54:53 PM PDT 24 Jul 12 05:54:57 PM PDT 24 411153404 ps
T368 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1405571747 Jul 12 05:55:03 PM PDT 24 Jul 12 05:55:04 PM PDT 24 425490552 ps
T369 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2487816870 Jul 12 05:54:49 PM PDT 24 Jul 12 05:54:53 PM PDT 24 592844384 ps
T370 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3161415917 Jul 12 05:54:46 PM PDT 24 Jul 12 05:54:51 PM PDT 24 659340971 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.236985128 Jul 12 05:54:28 PM PDT 24 Jul 12 05:54:31 PM PDT 24 557692254 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2050502297 Jul 12 05:55:04 PM PDT 24 Jul 12 05:55:06 PM PDT 24 458175533 ps
T197 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.156881016 Jul 12 05:54:50 PM PDT 24 Jul 12 05:54:57 PM PDT 24 4682872389 ps
T373 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.942254171 Jul 12 05:55:00 PM PDT 24 Jul 12 05:55:02 PM PDT 24 488434574 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.249424269 Jul 12 05:54:40 PM PDT 24 Jul 12 05:54:45 PM PDT 24 4401121621 ps
T375 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3885630276 Jul 12 05:54:49 PM PDT 24 Jul 12 05:54:52 PM PDT 24 477737944 ps
T376 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3169106198 Jul 12 05:55:03 PM PDT 24 Jul 12 05:55:06 PM PDT 24 511826468 ps
T196 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.427511905 Jul 12 05:54:29 PM PDT 24 Jul 12 05:54:33 PM PDT 24 4442148714 ps
T377 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3569945080 Jul 12 05:54:40 PM PDT 24 Jul 12 05:54:42 PM PDT 24 1801111101 ps
T378 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3717152747 Jul 12 05:54:33 PM PDT 24 Jul 12 05:54:37 PM PDT 24 4049543245 ps
T379 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1451252895 Jul 12 05:55:03 PM PDT 24 Jul 12 05:55:05 PM PDT 24 420850050 ps
T380 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3386750686 Jul 12 05:54:54 PM PDT 24 Jul 12 05:54:57 PM PDT 24 419358539 ps
T381 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2272341636 Jul 12 05:54:44 PM PDT 24 Jul 12 05:54:46 PM PDT 24 443747231 ps
T382 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2266525630 Jul 12 05:54:52 PM PDT 24 Jul 12 05:54:55 PM PDT 24 465009852 ps
T383 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.182630328 Jul 12 05:55:00 PM PDT 24 Jul 12 05:55:03 PM PDT 24 428795114 ps
T384 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1690662340 Jul 12 05:54:58 PM PDT 24 Jul 12 05:55:02 PM PDT 24 2054478950 ps
T385 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3702043213 Jul 12 05:54:43 PM PDT 24 Jul 12 05:54:50 PM PDT 24 4121194424 ps
T386 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3092192432 Jul 12 05:54:50 PM PDT 24 Jul 12 05:54:54 PM PDT 24 567605729 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3586277407 Jul 12 05:54:39 PM PDT 24 Jul 12 05:54:49 PM PDT 24 13419485144 ps
T388 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.427877225 Jul 12 05:54:39 PM PDT 24 Jul 12 05:54:40 PM PDT 24 290628061 ps
T389 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.862601005 Jul 12 05:54:35 PM PDT 24 Jul 12 05:54:44 PM PDT 24 2690149471 ps
T390 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2948468654 Jul 12 05:54:44 PM PDT 24 Jul 12 05:54:46 PM PDT 24 441487059 ps
T69 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.638879748 Jul 12 05:55:04 PM PDT 24 Jul 12 05:55:06 PM PDT 24 417636476 ps
T391 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4236690859 Jul 12 05:54:54 PM PDT 24 Jul 12 05:54:57 PM PDT 24 547305178 ps
T392 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3855721621 Jul 12 05:54:35 PM PDT 24 Jul 12 05:54:38 PM PDT 24 768063591 ps
T393 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2203062115 Jul 12 05:55:01 PM PDT 24 Jul 12 05:55:03 PM PDT 24 415670175 ps
T394 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.964318246 Jul 12 05:54:34 PM PDT 24 Jul 12 05:54:38 PM PDT 24 368244995 ps
T395 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3471335307 Jul 12 05:54:49 PM PDT 24 Jul 12 05:54:53 PM PDT 24 381497776 ps
T396 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.238336191 Jul 12 05:55:00 PM PDT 24 Jul 12 05:55:01 PM PDT 24 418208548 ps
T397 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3838431180 Jul 12 05:55:01 PM PDT 24 Jul 12 05:55:03 PM PDT 24 360876857 ps
T398 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.488655041 Jul 12 05:54:50 PM PDT 24 Jul 12 05:54:53 PM PDT 24 441444068 ps
T399 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1162991135 Jul 12 05:54:53 PM PDT 24 Jul 12 05:54:57 PM PDT 24 485898018 ps
T400 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3222619516 Jul 12 05:54:30 PM PDT 24 Jul 12 05:55:02 PM PDT 24 13855178461 ps
T401 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1817984385 Jul 12 05:54:51 PM PDT 24 Jul 12 05:54:54 PM PDT 24 589408622 ps
T402 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2187750244 Jul 12 05:54:45 PM PDT 24 Jul 12 05:54:47 PM PDT 24 451731149 ps
T403 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1152631623 Jul 12 05:54:30 PM PDT 24 Jul 12 05:54:33 PM PDT 24 476469528 ps
T404 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3024618999 Jul 12 05:54:29 PM PDT 24 Jul 12 05:54:32 PM PDT 24 338109941 ps
T405 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.803001673 Jul 12 05:54:56 PM PDT 24 Jul 12 05:54:59 PM PDT 24 388698424 ps
T406 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2092595227 Jul 12 05:54:55 PM PDT 24 Jul 12 05:54:58 PM PDT 24 472397098 ps
T70 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4225612704 Jul 12 05:54:27 PM PDT 24 Jul 12 05:54:29 PM PDT 24 546040006 ps
T407 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3681291889 Jul 12 05:54:45 PM PDT 24 Jul 12 05:54:47 PM PDT 24 449154417 ps
T408 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3864912656 Jul 12 05:54:49 PM PDT 24 Jul 12 05:54:55 PM PDT 24 4337582408 ps
T409 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.259225965 Jul 12 05:54:40 PM PDT 24 Jul 12 05:54:42 PM PDT 24 279179312 ps
T410 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3786541294 Jul 12 05:54:38 PM PDT 24 Jul 12 05:54:41 PM PDT 24 536484414 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3570335539 Jul 12 05:54:34 PM PDT 24 Jul 12 05:54:38 PM PDT 24 284638226 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3956116511 Jul 12 05:54:27 PM PDT 24 Jul 12 05:54:29 PM PDT 24 412168952 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2103633704 Jul 12 05:54:34 PM PDT 24 Jul 12 05:54:38 PM PDT 24 1391920824 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2005621376 Jul 12 05:54:45 PM PDT 24 Jul 12 05:54:50 PM PDT 24 2248190193 ps
T414 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4093842149 Jul 12 05:54:58 PM PDT 24 Jul 12 05:55:04 PM PDT 24 1734968354 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.828541120 Jul 12 05:54:26 PM PDT 24 Jul 12 05:54:28 PM PDT 24 482984503 ps
T416 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3574324479 Jul 12 05:55:04 PM PDT 24 Jul 12 05:55:06 PM PDT 24 419154178 ps
T417 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2298592387 Jul 12 05:54:40 PM PDT 24 Jul 12 05:54:42 PM PDT 24 494603140 ps
T418 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2690019073 Jul 12 05:55:00 PM PDT 24 Jul 12 05:55:02 PM PDT 24 429036856 ps
T419 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2130822404 Jul 12 05:54:32 PM PDT 24 Jul 12 05:54:35 PM PDT 24 653176070 ps
T420 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1097600684 Jul 12 05:54:49 PM PDT 24 Jul 12 05:54:53 PM PDT 24 450899520 ps
T421 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3035166498 Jul 12 05:55:03 PM PDT 24 Jul 12 05:55:06 PM PDT 24 304852880 ps
T422 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2546130573 Jul 12 05:54:56 PM PDT 24 Jul 12 05:55:10 PM PDT 24 8731825748 ps
T423 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1981927981 Jul 12 05:54:54 PM PDT 24 Jul 12 05:54:58 PM PDT 24 4508684915 ps

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.29893238
Short name T10
Test name
Test status
Simulation time 29770189793 ps
CPU time 222.71 seconds
Started Jul 12 05:54:11 PM PDT 24
Finished Jul 12 05:57:55 PM PDT 24
Peak memory 214092 kb
Host smart-4cbd2c59-6f91-4221-be00-ac9094133320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29893238 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.29893238
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2620305668
Short name T25
Test name
Test status
Simulation time 177187128636 ps
CPU time 316.58 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:59:06 PM PDT 24
Peak memory 209172 kb
Host smart-20a9521d-86d4-467f-88a1-a340ea43d8bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620305668 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2620305668
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4061713437
Short name T32
Test name
Test status
Simulation time 4493677809 ps
CPU time 3.95 seconds
Started Jul 12 05:54:34 PM PDT 24
Finished Jul 12 05:54:41 PM PDT 24
Peak memory 196792 kb
Host smart-6d871e4e-36d7-4242-9a66-38b5dec15292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061713437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.4061713437
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3389691734
Short name T8
Test name
Test status
Simulation time 240092672750 ps
CPU time 435.46 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 06:01:22 PM PDT 24
Peak memory 202904 kb
Host smart-28035c1a-6766-40f9-b96c-bd842fb407c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389691734 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3389691734
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3920336652
Short name T110
Test name
Test status
Simulation time 247834821642 ps
CPU time 325.86 seconds
Started Jul 12 05:54:24 PM PDT 24
Finished Jul 12 05:59:51 PM PDT 24
Peak memory 210288 kb
Host smart-f49cc2c1-80f1-4a36-b154-5a76541f77db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920336652 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3920336652
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.4270527450
Short name T13
Test name
Test status
Simulation time 243665354824 ps
CPU time 91.55 seconds
Started Jul 12 05:54:17 PM PDT 24
Finished Jul 12 05:55:51 PM PDT 24
Peak memory 192428 kb
Host smart-6f1ddfaa-bf6e-4611-8fc2-6158b370298a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270527450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.4270527450
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.636349439
Short name T46
Test name
Test status
Simulation time 445515357236 ps
CPU time 852.23 seconds
Started Jul 12 05:53:53 PM PDT 24
Finished Jul 12 06:08:10 PM PDT 24
Peak memory 209504 kb
Host smart-fedd4633-5c22-44ff-bea2-72baf78a5a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636349439 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.636349439
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1464704961
Short name T1
Test name
Test status
Simulation time 148651483075 ps
CPU time 285.42 seconds
Started Jul 12 05:54:00 PM PDT 24
Finished Jul 12 05:58:51 PM PDT 24
Peak memory 209764 kb
Host smart-7f40451b-51e2-43a0-badd-e0b830a9df63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464704961 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1464704961
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.733715062
Short name T108
Test name
Test status
Simulation time 299451120740 ps
CPU time 197.8 seconds
Started Jul 12 05:54:04 PM PDT 24
Finished Jul 12 05:57:26 PM PDT 24
Peak memory 184796 kb
Host smart-63dcae2a-f1bb-4a4b-97f6-a87e4d181196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733715062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.733715062
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1824304722
Short name T42
Test name
Test status
Simulation time 70242212471 ps
CPU time 510.5 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 06:03:02 PM PDT 24
Peak memory 210876 kb
Host smart-034650a5-46b7-4ab3-a1cb-db08b2e600cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824304722 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1824304722
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.343456491
Short name T15
Test name
Test status
Simulation time 3860191311 ps
CPU time 6.71 seconds
Started Jul 12 05:53:45 PM PDT 24
Finished Jul 12 05:53:55 PM PDT 24
Peak memory 215464 kb
Host smart-7784c12a-bbec-416a-980a-c67e36ef5f81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343456491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.343456491
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.150481525
Short name T154
Test name
Test status
Simulation time 251061048575 ps
CPU time 565.5 seconds
Started Jul 12 05:53:52 PM PDT 24
Finished Jul 12 06:03:22 PM PDT 24
Peak memory 213916 kb
Host smart-11201fa1-6573-44b6-be57-1326d3d46688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150481525 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.150481525
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4163504567
Short name T109
Test name
Test status
Simulation time 26760805440 ps
CPU time 218.95 seconds
Started Jul 12 05:53:51 PM PDT 24
Finished Jul 12 05:57:33 PM PDT 24
Peak memory 198524 kb
Host smart-d0d0322b-53f5-436a-9938-c1c1efc49361
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163504567 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4163504567
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3223997338
Short name T12
Test name
Test status
Simulation time 24295503143 ps
CPU time 164.79 seconds
Started Jul 12 05:53:55 PM PDT 24
Finished Jul 12 05:56:46 PM PDT 24
Peak memory 214520 kb
Host smart-1f8feb98-0ce9-4a6a-934a-b9fd29d37630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223997338 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3223997338
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1219381964
Short name T115
Test name
Test status
Simulation time 102794397746 ps
CPU time 77.82 seconds
Started Jul 12 05:53:50 PM PDT 24
Finished Jul 12 05:55:11 PM PDT 24
Peak memory 193012 kb
Host smart-5c9eaa10-cde8-4b48-8f8d-cf4317e2c006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219381964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1219381964
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.758163873
Short name T103
Test name
Test status
Simulation time 4224019340 ps
CPU time 6.52 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:14 PM PDT 24
Peak memory 192528 kb
Host smart-468c27db-06e8-416f-bf44-d0dff01796bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758163873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.758163873
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1843036412
Short name T91
Test name
Test status
Simulation time 120231922283 ps
CPU time 234.7 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:57:43 PM PDT 24
Peak memory 208844 kb
Host smart-7f78989f-7278-4f00-9c65-2595fcc0e2b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843036412 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1843036412
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3184693090
Short name T107
Test name
Test status
Simulation time 124703217565 ps
CPU time 160.09 seconds
Started Jul 12 05:53:47 PM PDT 24
Finished Jul 12 05:56:31 PM PDT 24
Peak memory 198276 kb
Host smart-a18951d3-3cce-4064-a25e-f90c9c4945c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184693090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3184693090
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2179672488
Short name T88
Test name
Test status
Simulation time 101866632692 ps
CPU time 971.4 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 06:10:29 PM PDT 24
Peak memory 211828 kb
Host smart-69c3ab98-266b-42d5-a559-99ca9daffc14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179672488 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2179672488
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3033183198
Short name T97
Test name
Test status
Simulation time 67286888624 ps
CPU time 23.54 seconds
Started Jul 12 05:53:57 PM PDT 24
Finished Jul 12 05:54:26 PM PDT 24
Peak memory 198232 kb
Host smart-f126c744-7372-429c-b7fc-16b4944c29fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033183198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3033183198
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3084762423
Short name T121
Test name
Test status
Simulation time 106958356300 ps
CPU time 20.89 seconds
Started Jul 12 05:54:17 PM PDT 24
Finished Jul 12 05:54:40 PM PDT 24
Peak memory 192996 kb
Host smart-6e18a6c8-e54c-4520-a238-c53f46312574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084762423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3084762423
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1509340870
Short name T162
Test name
Test status
Simulation time 57425797646 ps
CPU time 609.69 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 06:03:59 PM PDT 24
Peak memory 212084 kb
Host smart-e0536ecf-a03b-406d-8779-f59e716d1c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509340870 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1509340870
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.581727407
Short name T138
Test name
Test status
Simulation time 83546825530 ps
CPU time 343.51 seconds
Started Jul 12 05:53:51 PM PDT 24
Finished Jul 12 05:59:38 PM PDT 24
Peak memory 201464 kb
Host smart-c6543258-0856-415d-957e-20a3279c2c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581727407 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.581727407
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3581460314
Short name T137
Test name
Test status
Simulation time 93975492738 ps
CPU time 99.38 seconds
Started Jul 12 05:53:51 PM PDT 24
Finished Jul 12 05:55:34 PM PDT 24
Peak memory 198268 kb
Host smart-508e8f83-98d7-4302-8b47-2bb6e9d0bd89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581460314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3581460314
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2530007927
Short name T114
Test name
Test status
Simulation time 224781691492 ps
CPU time 624.43 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 06:04:41 PM PDT 24
Peak memory 214092 kb
Host smart-d447259e-eb24-4f07-9796-d7118cba3f44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530007927 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2530007927
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3495754035
Short name T123
Test name
Test status
Simulation time 107158075164 ps
CPU time 877.11 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 06:08:55 PM PDT 24
Peak memory 207316 kb
Host smart-13503e21-20e4-4fdd-a17f-7d631db6e88d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495754035 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3495754035
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.895720185
Short name T89
Test name
Test status
Simulation time 83200625981 ps
CPU time 171.64 seconds
Started Jul 12 05:53:59 PM PDT 24
Finished Jul 12 05:56:56 PM PDT 24
Peak memory 213916 kb
Host smart-78ef74bf-ff8b-4254-a06c-021ee839d997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895720185 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.895720185
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1361136145
Short name T39
Test name
Test status
Simulation time 4994351784 ps
CPU time 2.98 seconds
Started Jul 12 05:54:35 PM PDT 24
Finished Jul 12 05:54:40 PM PDT 24
Peak memory 192220 kb
Host smart-487b15f6-cd3f-415b-a63b-18a6213e6129
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361136145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1361136145
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.705408153
Short name T92
Test name
Test status
Simulation time 32920356531 ps
CPU time 136.15 seconds
Started Jul 12 05:54:13 PM PDT 24
Finished Jul 12 05:56:31 PM PDT 24
Peak memory 206776 kb
Host smart-dad562f4-86b3-443d-b429-8e92f220b85a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705408153 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.705408153
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1372133251
Short name T129
Test name
Test status
Simulation time 334438313467 ps
CPU time 654.25 seconds
Started Jul 12 05:54:19 PM PDT 24
Finished Jul 12 06:05:15 PM PDT 24
Peak memory 206424 kb
Host smart-304c7739-f0ac-409b-b54c-afd79662931b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372133251 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1372133251
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1425621056
Short name T157
Test name
Test status
Simulation time 374517645015 ps
CPU time 37.19 seconds
Started Jul 12 05:54:28 PM PDT 24
Finished Jul 12 05:55:07 PM PDT 24
Peak memory 193160 kb
Host smart-c9cdb736-8b64-46f4-94d0-4cdc37924251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425621056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1425621056
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3409724326
Short name T99
Test name
Test status
Simulation time 123855698338 ps
CPU time 167.91 seconds
Started Jul 12 05:53:38 PM PDT 24
Finished Jul 12 05:56:27 PM PDT 24
Peak memory 192564 kb
Host smart-43045d30-18dc-4d1c-9edd-313272b12426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409724326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3409724326
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1944791977
Short name T163
Test name
Test status
Simulation time 96443272165 ps
CPU time 393.47 seconds
Started Jul 12 05:54:20 PM PDT 24
Finished Jul 12 06:00:55 PM PDT 24
Peak memory 211048 kb
Host smart-dca1be61-7b93-40f3-aa5c-ef5418afbd25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944791977 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1944791977
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3451915788
Short name T85
Test name
Test status
Simulation time 269851816286 ps
CPU time 570.39 seconds
Started Jul 12 05:53:50 PM PDT 24
Finished Jul 12 06:03:24 PM PDT 24
Peak memory 204984 kb
Host smart-cfd09eb8-f104-4f85-b56c-86d1bd041c27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451915788 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3451915788
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1678727424
Short name T130
Test name
Test status
Simulation time 151221559537 ps
CPU time 204 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:57:31 PM PDT 24
Peak memory 198252 kb
Host smart-c9eceb36-5614-44d2-8355-c58d08944913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678727424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1678727424
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.202931156
Short name T124
Test name
Test status
Simulation time 81564953671 ps
CPU time 130.85 seconds
Started Jul 12 05:53:53 PM PDT 24
Finished Jul 12 05:56:09 PM PDT 24
Peak memory 198212 kb
Host smart-60d2ce03-0290-4312-b2ad-fd1a6e760e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202931156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.202931156
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.394761118
Short name T133
Test name
Test status
Simulation time 106620262770 ps
CPU time 143.44 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:56:27 PM PDT 24
Peak memory 192612 kb
Host smart-3be4bec7-1456-43ef-98f4-1685405009a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394761118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.394761118
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1668218494
Short name T28
Test name
Test status
Simulation time 26503094595 ps
CPU time 201.48 seconds
Started Jul 12 05:54:08 PM PDT 24
Finished Jul 12 05:57:31 PM PDT 24
Peak memory 198576 kb
Host smart-2c53d63f-9b97-4716-b34a-191a20fbad52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668218494 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1668218494
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3636834188
Short name T120
Test name
Test status
Simulation time 59853796439 ps
CPU time 333.94 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:59:52 PM PDT 24
Peak memory 208240 kb
Host smart-baba31f0-efcc-441e-adc2-eb9f6b1d322e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636834188 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3636834188
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1841030987
Short name T31
Test name
Test status
Simulation time 64400615940 ps
CPU time 91.72 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:55:21 PM PDT 24
Peak memory 198284 kb
Host smart-0968e765-c89f-43e2-911e-20841f9802f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841030987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1841030987
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3620009214
Short name T22
Test name
Test status
Simulation time 111318507556 ps
CPU time 177.64 seconds
Started Jul 12 05:53:44 PM PDT 24
Finished Jul 12 05:56:43 PM PDT 24
Peak memory 198284 kb
Host smart-58e58cea-bea6-4238-93ff-d1d68b26645c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620009214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3620009214
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.4156408158
Short name T111
Test name
Test status
Simulation time 67047861974 ps
CPU time 23.31 seconds
Started Jul 12 05:54:14 PM PDT 24
Finished Jul 12 05:54:39 PM PDT 24
Peak memory 193016 kb
Host smart-f76d4e16-94e2-499b-b219-eb9092bad051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156408158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.4156408158
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1060898928
Short name T24
Test name
Test status
Simulation time 380186533911 ps
CPU time 46.1 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:54:35 PM PDT 24
Peak memory 198240 kb
Host smart-8545165a-6aa8-4846-8e7f-ff192f45f96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060898928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1060898928
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2801059047
Short name T117
Test name
Test status
Simulation time 87807429793 ps
CPU time 202.88 seconds
Started Jul 12 05:53:47 PM PDT 24
Finished Jul 12 05:57:13 PM PDT 24
Peak memory 200184 kb
Host smart-7992386a-ea7b-4d98-9923-1e4a135fd8af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801059047 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2801059047
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1044746486
Short name T128
Test name
Test status
Simulation time 46956476382 ps
CPU time 283.65 seconds
Started Jul 12 05:54:00 PM PDT 24
Finished Jul 12 05:58:49 PM PDT 24
Peak memory 198544 kb
Host smart-005a298f-1e6b-40f8-bdfe-f72a5c41565e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044746486 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1044746486
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2838074253
Short name T106
Test name
Test status
Simulation time 339701216686 ps
CPU time 123.12 seconds
Started Jul 12 05:54:14 PM PDT 24
Finished Jul 12 05:56:18 PM PDT 24
Peak memory 191912 kb
Host smart-20d33470-57b3-4357-86f9-c908147267a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838074253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2838074253
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2163797795
Short name T94
Test name
Test status
Simulation time 211713262691 ps
CPU time 304.22 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:59:22 PM PDT 24
Peak memory 201288 kb
Host smart-2c64f05b-eec9-4371-9391-f91c5d04ed39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163797795 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2163797795
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2882559770
Short name T23
Test name
Test status
Simulation time 263161006187 ps
CPU time 367.54 seconds
Started Jul 12 05:53:53 PM PDT 24
Finished Jul 12 06:00:05 PM PDT 24
Peak memory 198412 kb
Host smart-f5a966c3-fca3-4f17-9eca-92c0e7805447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882559770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2882559770
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.590934435
Short name T159
Test name
Test status
Simulation time 142917023836 ps
CPU time 332.75 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:59:40 PM PDT 24
Peak memory 210508 kb
Host smart-6458fecb-7dc4-45e4-8082-2cfd37065894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590934435 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.590934435
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1015179032
Short name T95
Test name
Test status
Simulation time 167705043248 ps
CPU time 258.66 seconds
Started Jul 12 05:54:06 PM PDT 24
Finished Jul 12 05:58:28 PM PDT 24
Peak memory 192576 kb
Host smart-e9959351-0761-4966-918a-d5f18334e79c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015179032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1015179032
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.727566590
Short name T104
Test name
Test status
Simulation time 31310061865 ps
CPU time 23.3 seconds
Started Jul 12 05:54:14 PM PDT 24
Finished Jul 12 05:54:39 PM PDT 24
Peak memory 191904 kb
Host smart-46410d39-b82f-49c9-8e33-43ef23ef653f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727566590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.727566590
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1409475153
Short name T171
Test name
Test status
Simulation time 52977045716 ps
CPU time 430.72 seconds
Started Jul 12 05:54:14 PM PDT 24
Finished Jul 12 06:01:26 PM PDT 24
Peak memory 209008 kb
Host smart-7f6cb9bd-bc14-430e-9c2b-181e307978e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409475153 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1409475153
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4158840734
Short name T125
Test name
Test status
Simulation time 61606783242 ps
CPU time 21.41 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 191888 kb
Host smart-b74bf9de-bc91-4a3e-8311-ad583e977700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158840734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4158840734
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.210167882
Short name T75
Test name
Test status
Simulation time 1504815154 ps
CPU time 1.5 seconds
Started Jul 12 05:54:46 PM PDT 24
Finished Jul 12 05:54:50 PM PDT 24
Peak memory 193656 kb
Host smart-7d71f0b4-1c11-4ffc-8bac-6c5159210085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210167882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.210167882
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1055808247
Short name T83
Test name
Test status
Simulation time 21686735067 ps
CPU time 218.59 seconds
Started Jul 12 05:53:51 PM PDT 24
Finished Jul 12 05:57:33 PM PDT 24
Peak memory 198588 kb
Host smart-fb9e2953-c132-4a53-9c56-5e31a58938a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055808247 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1055808247
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.4276858386
Short name T98
Test name
Test status
Simulation time 127601364077 ps
CPU time 524.18 seconds
Started Jul 12 05:54:06 PM PDT 24
Finished Jul 12 06:02:53 PM PDT 24
Peak memory 214948 kb
Host smart-4af093c6-92c8-4e5f-8ef7-080b071cb999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276858386 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.4276858386
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.657621851
Short name T118
Test name
Test status
Simulation time 153887903385 ps
CPU time 48.92 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 05:55:21 PM PDT 24
Peak memory 198236 kb
Host smart-730084f1-21e6-4892-86c2-ae1cfccc95dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657621851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.657621851
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3267762613
Short name T141
Test name
Test status
Simulation time 201930442639 ps
CPU time 274.95 seconds
Started Jul 12 05:54:27 PM PDT 24
Finished Jul 12 05:59:03 PM PDT 24
Peak memory 192556 kb
Host smart-db18b6e5-5dd3-45f2-ac3e-d5a9fbe6bff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267762613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3267762613
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.341280495
Short name T96
Test name
Test status
Simulation time 164931881779 ps
CPU time 713.97 seconds
Started Jul 12 05:53:52 PM PDT 24
Finished Jul 12 06:05:50 PM PDT 24
Peak memory 214672 kb
Host smart-47b6b3f8-e096-4d65-8e83-e87c8b970526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341280495 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.341280495
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2583088238
Short name T44
Test name
Test status
Simulation time 143280207464 ps
CPU time 182.6 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:57:19 PM PDT 24
Peak memory 191920 kb
Host smart-a23e28a2-6e47-4d82-bb69-1675235fe217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583088238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2583088238
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2050442845
Short name T145
Test name
Test status
Simulation time 344493664904 ps
CPU time 120.61 seconds
Started Jul 12 05:54:13 PM PDT 24
Finished Jul 12 05:56:15 PM PDT 24
Peak memory 198244 kb
Host smart-ef5cc9ab-6a29-4131-bdb3-1b8e50329b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050442845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2050442845
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2161130225
Short name T126
Test name
Test status
Simulation time 91226147461 ps
CPU time 113.21 seconds
Started Jul 12 05:54:12 PM PDT 24
Finished Jul 12 05:56:06 PM PDT 24
Peak memory 198236 kb
Host smart-e4314770-1c8d-48a9-89e4-c81567cc7f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161130225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2161130225
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3203628744
Short name T149
Test name
Test status
Simulation time 103682715697 ps
CPU time 33.34 seconds
Started Jul 12 05:54:28 PM PDT 24
Finished Jul 12 05:55:04 PM PDT 24
Peak memory 192500 kb
Host smart-b7ac0a8b-2f48-421e-bda8-ad1c4d6c6492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203628744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3203628744
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2177769724
Short name T29
Test name
Test status
Simulation time 104264305776 ps
CPU time 37.15 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:54:42 PM PDT 24
Peak memory 191984 kb
Host smart-ee96fc21-2e2e-462f-b6b5-2a3df67aec78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177769724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2177769724
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1281340217
Short name T100
Test name
Test status
Simulation time 185416173726 ps
CPU time 126.39 seconds
Started Jul 12 05:54:13 PM PDT 24
Finished Jul 12 05:56:20 PM PDT 24
Peak memory 198248 kb
Host smart-8f25baa8-c0d6-4811-aa52-8fb7b981c08d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281340217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1281340217
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1876197968
Short name T84
Test name
Test status
Simulation time 131037927550 ps
CPU time 259.74 seconds
Started Jul 12 05:53:54 PM PDT 24
Finished Jul 12 05:58:20 PM PDT 24
Peak memory 206744 kb
Host smart-38a295c2-f451-487c-8022-e7a67a709854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876197968 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1876197968
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1961207360
Short name T136
Test name
Test status
Simulation time 451943734 ps
CPU time 0.7 seconds
Started Jul 12 05:53:52 PM PDT 24
Finished Jul 12 05:53:57 PM PDT 24
Peak memory 196740 kb
Host smart-b71a44ca-4d27-4414-965d-6c6b52f63579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961207360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1961207360
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3101023787
Short name T169
Test name
Test status
Simulation time 47337473577 ps
CPU time 529.06 seconds
Started Jul 12 05:54:04 PM PDT 24
Finished Jul 12 06:02:58 PM PDT 24
Peak memory 201888 kb
Host smart-a6572036-72ca-40af-83cf-9eddfe3f251e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101023787 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3101023787
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3503698640
Short name T80
Test name
Test status
Simulation time 521312652 ps
CPU time 0.69 seconds
Started Jul 12 05:54:14 PM PDT 24
Finished Jul 12 05:54:16 PM PDT 24
Peak memory 196752 kb
Host smart-9a67eb0a-9558-40b4-861e-25e77660a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503698640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3503698640
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3994783191
Short name T131
Test name
Test status
Simulation time 91374335559 ps
CPU time 65.18 seconds
Started Jul 12 05:54:19 PM PDT 24
Finished Jul 12 05:55:27 PM PDT 24
Peak memory 191872 kb
Host smart-83d708f8-34b2-4311-87fb-003d5647ea70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994783191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3994783191
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1401777069
Short name T155
Test name
Test status
Simulation time 42800599985 ps
CPU time 176.04 seconds
Started Jul 12 05:54:17 PM PDT 24
Finished Jul 12 05:57:15 PM PDT 24
Peak memory 206764 kb
Host smart-ab1efbd6-399e-4848-90a1-c8ae09b9428a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401777069 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1401777069
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1953047139
Short name T142
Test name
Test status
Simulation time 339144721 ps
CPU time 0.86 seconds
Started Jul 12 05:54:26 PM PDT 24
Finished Jul 12 05:54:28 PM PDT 24
Peak memory 196688 kb
Host smart-a534ffd7-f4de-4407-90f4-7e9faba5a407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953047139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1953047139
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.765714633
Short name T87
Test name
Test status
Simulation time 31870449351 ps
CPU time 184.98 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:56:54 PM PDT 24
Peak memory 198444 kb
Host smart-0df6ca7c-b34b-460d-836b-c4e89f561264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765714633 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.765714633
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3590477741
Short name T140
Test name
Test status
Simulation time 598354810 ps
CPU time 0.81 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:53:50 PM PDT 24
Peak memory 196676 kb
Host smart-1af3adb6-7c57-44a8-af5f-0c26ea312331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590477741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3590477741
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.83410958
Short name T151
Test name
Test status
Simulation time 134272184694 ps
CPU time 172.39 seconds
Started Jul 12 05:53:45 PM PDT 24
Finished Jul 12 05:56:39 PM PDT 24
Peak memory 198228 kb
Host smart-417dba5a-b7cb-4e75-8d00-00ba276ccaa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83410958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all
.83410958
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1598171674
Short name T51
Test name
Test status
Simulation time 250442516169 ps
CPU time 377.26 seconds
Started Jul 12 05:53:56 PM PDT 24
Finished Jul 12 06:00:19 PM PDT 24
Peak memory 198200 kb
Host smart-044ffe35-9570-49ff-b704-ee64d4d7e376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598171674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1598171674
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3841247464
Short name T174
Test name
Test status
Simulation time 189122279161 ps
CPU time 300.3 seconds
Started Jul 12 05:53:39 PM PDT 24
Finished Jul 12 05:58:41 PM PDT 24
Peak memory 201580 kb
Host smart-5c6900f8-9a84-44bc-ae19-b6a4dc1d93dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841247464 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3841247464
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.725912733
Short name T165
Test name
Test status
Simulation time 90557990184 ps
CPU time 136.4 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:56:23 PM PDT 24
Peak memory 192940 kb
Host smart-74fdf3a2-ab7c-4262-b9e7-cf4a68ed5f96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725912733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.725912733
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1948607541
Short name T132
Test name
Test status
Simulation time 565725611 ps
CPU time 0.78 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:54:07 PM PDT 24
Peak memory 196752 kb
Host smart-733000c9-0a7e-458b-98b6-8a784bc6f45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948607541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1948607541
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2051271646
Short name T139
Test name
Test status
Simulation time 226152441424 ps
CPU time 330.57 seconds
Started Jul 12 05:54:10 PM PDT 24
Finished Jul 12 05:59:41 PM PDT 24
Peak memory 193028 kb
Host smart-0660e85c-cae5-468f-8664-2d295470fbfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051271646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2051271646
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.830688767
Short name T112
Test name
Test status
Simulation time 603880869 ps
CPU time 0.68 seconds
Started Jul 12 05:53:39 PM PDT 24
Finished Jul 12 05:53:41 PM PDT 24
Peak memory 196712 kb
Host smart-bc32e0be-4e85-49af-b0f1-f1d4021cc32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830688767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.830688767
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2749471773
Short name T148
Test name
Test status
Simulation time 312729091185 ps
CPU time 242.35 seconds
Started Jul 12 05:53:53 PM PDT 24
Finished Jul 12 05:57:59 PM PDT 24
Peak memory 191928 kb
Host smart-521697c5-00c8-4b56-9df5-cef9c062fe93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749471773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2749471773
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.598267294
Short name T19
Test name
Test status
Simulation time 414727706 ps
CPU time 0.74 seconds
Started Jul 12 05:54:17 PM PDT 24
Finished Jul 12 05:54:21 PM PDT 24
Peak memory 196632 kb
Host smart-8e36ebf4-17a7-4d4c-b2b9-6e6005f2478e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598267294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.598267294
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3183673586
Short name T102
Test name
Test status
Simulation time 364058866 ps
CPU time 0.84 seconds
Started Jul 12 05:54:09 PM PDT 24
Finished Jul 12 05:54:11 PM PDT 24
Peak memory 196700 kb
Host smart-229b3a14-079f-4882-985c-2e940390c018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183673586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3183673586
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3139254994
Short name T144
Test name
Test status
Simulation time 566990584 ps
CPU time 0.97 seconds
Started Jul 12 05:54:09 PM PDT 24
Finished Jul 12 05:54:11 PM PDT 24
Peak memory 196676 kb
Host smart-57c89f5c-08f8-4dc0-9cb5-4193d93610a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139254994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3139254994
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1761873663
Short name T30
Test name
Test status
Simulation time 30969588105 ps
CPU time 42.69 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:55:01 PM PDT 24
Peak memory 191924 kb
Host smart-fc310fec-1645-4797-93ca-ab4b67664372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761873663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1761873663
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2607883103
Short name T143
Test name
Test status
Simulation time 157247088947 ps
CPU time 53.65 seconds
Started Jul 12 05:53:52 PM PDT 24
Finished Jul 12 05:54:49 PM PDT 24
Peak memory 192044 kb
Host smart-e4e9260d-c9c5-46a0-b364-8f41bf91ba52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607883103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2607883103
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.366176758
Short name T160
Test name
Test status
Simulation time 38049067192 ps
CPU time 12.98 seconds
Started Jul 12 05:53:47 PM PDT 24
Finished Jul 12 05:54:04 PM PDT 24
Peak memory 191892 kb
Host smart-7357a644-9f6f-41e4-bbb4-798ac8bea898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366176758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.366176758
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2735533360
Short name T150
Test name
Test status
Simulation time 495695053 ps
CPU time 1.01 seconds
Started Jul 12 05:53:56 PM PDT 24
Finished Jul 12 05:54:02 PM PDT 24
Peak memory 196704 kb
Host smart-80d59927-65a8-4119-8142-78cf1815e0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735533360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2735533360
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.582571754
Short name T134
Test name
Test status
Simulation time 526871328 ps
CPU time 1 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:09 PM PDT 24
Peak memory 196756 kb
Host smart-b1455385-6b3f-4c57-b0cc-6861d05960dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582571754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.582571754
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1795935214
Short name T172
Test name
Test status
Simulation time 112417981276 ps
CPU time 11.04 seconds
Started Jul 12 05:54:03 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 191692 kb
Host smart-8355fd0a-7da6-400a-b504-5f81dd3fd41b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795935214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1795935214
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2875412308
Short name T122
Test name
Test status
Simulation time 532467298 ps
CPU time 0.78 seconds
Started Jul 12 05:53:56 PM PDT 24
Finished Jul 12 05:54:03 PM PDT 24
Peak memory 196712 kb
Host smart-591fd6b5-f250-43e5-a17b-67b54b46ddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875412308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2875412308
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1268798313
Short name T153
Test name
Test status
Simulation time 404799067 ps
CPU time 0.74 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:54:07 PM PDT 24
Peak memory 196972 kb
Host smart-904b1170-b90e-4be0-9711-432d3405f317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268798313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1268798313
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3617673822
Short name T167
Test name
Test status
Simulation time 396530279931 ps
CPU time 139.23 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:56:25 PM PDT 24
Peak memory 191924 kb
Host smart-07bfeafe-e299-41e9-b256-1b670c711ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617673822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3617673822
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.948113187
Short name T127
Test name
Test status
Simulation time 452050415 ps
CPU time 1 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:54:06 PM PDT 24
Peak memory 196744 kb
Host smart-289271f1-14eb-4f8f-a67a-a14a59e31c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948113187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.948113187
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3926478810
Short name T168
Test name
Test status
Simulation time 54023694628 ps
CPU time 420.05 seconds
Started Jul 12 05:54:04 PM PDT 24
Finished Jul 12 06:01:08 PM PDT 24
Peak memory 206720 kb
Host smart-3058c73d-bd7c-4b75-9ff6-b330ba10ca4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926478810 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3926478810
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2138048397
Short name T21
Test name
Test status
Simulation time 99919178555 ps
CPU time 397.66 seconds
Started Jul 12 05:54:08 PM PDT 24
Finished Jul 12 06:00:47 PM PDT 24
Peak memory 214024 kb
Host smart-018ed689-a54f-4cd0-9b4b-b6725a320ba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138048397 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2138048397
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4058000100
Short name T188
Test name
Test status
Simulation time 105889002228 ps
CPU time 38.25 seconds
Started Jul 12 05:54:19 PM PDT 24
Finished Jul 12 05:54:59 PM PDT 24
Peak memory 198288 kb
Host smart-c3406f87-042a-48fa-93c4-fd2133e8fccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058000100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4058000100
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3635172126
Short name T40
Test name
Test status
Simulation time 22930918710 ps
CPU time 226.45 seconds
Started Jul 12 05:54:24 PM PDT 24
Finished Jul 12 05:58:11 PM PDT 24
Peak memory 214944 kb
Host smart-89b32cbc-4b07-4454-a7ea-bd8f9a33bf67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635172126 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3635172126
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3946545238
Short name T158
Test name
Test status
Simulation time 422161760 ps
CPU time 0.73 seconds
Started Jul 12 05:54:28 PM PDT 24
Finished Jul 12 05:54:30 PM PDT 24
Peak memory 196660 kb
Host smart-0835a8ae-962b-482e-bbd3-4b4d918cc418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946545238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3946545238
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2227386053
Short name T152
Test name
Test status
Simulation time 570715390 ps
CPU time 0.92 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:53:50 PM PDT 24
Peak memory 196664 kb
Host smart-c5bd1505-2dbe-4cb2-9f6c-fe90e80a39e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227386053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2227386053
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4132240279
Short name T116
Test name
Test status
Simulation time 366450035 ps
CPU time 0.74 seconds
Started Jul 12 05:53:52 PM PDT 24
Finished Jul 12 05:53:57 PM PDT 24
Peak memory 196716 kb
Host smart-856f1a13-a9be-4a08-acb5-b32fc3a1d712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132240279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4132240279
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2394416008
Short name T156
Test name
Test status
Simulation time 403344903 ps
CPU time 0.66 seconds
Started Jul 12 05:53:57 PM PDT 24
Finished Jul 12 05:54:03 PM PDT 24
Peak memory 196688 kb
Host smart-539cadd9-798f-4b11-8f79-bad9fbb16a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394416008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2394416008
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1566900781
Short name T50
Test name
Test status
Simulation time 446754392 ps
CPU time 1.26 seconds
Started Jul 12 05:53:41 PM PDT 24
Finished Jul 12 05:53:43 PM PDT 24
Peak memory 196776 kb
Host smart-a224f477-ca1f-432f-9e77-7d7c54ac43f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566900781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1566900781
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1520049773
Short name T113
Test name
Test status
Simulation time 563588087 ps
CPU time 0.92 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:54:20 PM PDT 24
Peak memory 196728 kb
Host smart-7be3a275-3702-4405-954b-fb8aa5ff7694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520049773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1520049773
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.242857931
Short name T82
Test name
Test status
Simulation time 489206808 ps
CPU time 0.92 seconds
Started Jul 12 05:54:22 PM PDT 24
Finished Jul 12 05:54:24 PM PDT 24
Peak memory 196688 kb
Host smart-a48bd2b7-8064-448c-90ce-aed68f00231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242857931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.242857931
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2609550614
Short name T195
Test name
Test status
Simulation time 9122722459 ps
CPU time 2.66 seconds
Started Jul 12 05:54:45 PM PDT 24
Finished Jul 12 05:54:49 PM PDT 24
Peak memory 198280 kb
Host smart-6a94e9a4-6b2c-4913-b286-513cb71a5360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609550614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2609550614
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1369552109
Short name T146
Test name
Test status
Simulation time 543674919 ps
CPU time 0.76 seconds
Started Jul 12 05:53:52 PM PDT 24
Finished Jul 12 05:53:56 PM PDT 24
Peak memory 196672 kb
Host smart-ce1f2cb0-507f-4792-b510-d26180e4f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369552109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1369552109
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.558214094
Short name T186
Test name
Test status
Simulation time 577500557 ps
CPU time 0.73 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:08 PM PDT 24
Peak memory 196612 kb
Host smart-9c1a8987-2d3b-44a4-8fa8-331f510bd4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558214094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.558214094
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1587809212
Short name T187
Test name
Test status
Simulation time 462057779 ps
CPU time 0.92 seconds
Started Jul 12 05:54:00 PM PDT 24
Finished Jul 12 05:54:06 PM PDT 24
Peak memory 196620 kb
Host smart-fbb5ae40-8ad1-46e4-ba81-72e564aec8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587809212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1587809212
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2397619262
Short name T161
Test name
Test status
Simulation time 36274876946 ps
CPU time 213.44 seconds
Started Jul 12 05:54:14 PM PDT 24
Finished Jul 12 05:57:49 PM PDT 24
Peak memory 198604 kb
Host smart-7f75ce26-6339-4742-ba41-058306427d27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397619262 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2397619262
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3119198522
Short name T135
Test name
Test status
Simulation time 474215702 ps
CPU time 0.74 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:54:18 PM PDT 24
Peak memory 196636 kb
Host smart-38399f87-4115-412d-b19b-93a922d90cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119198522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3119198522
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1817073397
Short name T185
Test name
Test status
Simulation time 465650344 ps
CPU time 1.22 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 196760 kb
Host smart-34713a96-236d-4bfa-8b31-ac96b09df75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817073397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1817073397
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1963351121
Short name T52
Test name
Test status
Simulation time 457224755 ps
CPU time 0.96 seconds
Started Jul 12 05:54:17 PM PDT 24
Finished Jul 12 05:54:20 PM PDT 24
Peak memory 196608 kb
Host smart-6db2f8f4-3f60-4cfc-8121-9f4ff85b3931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963351121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1963351121
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.646579794
Short name T105
Test name
Test status
Simulation time 513130446 ps
CPU time 0.74 seconds
Started Jul 12 05:54:17 PM PDT 24
Finished Jul 12 05:54:20 PM PDT 24
Peak memory 196628 kb
Host smart-ef0bd062-1ac7-434d-85fb-e9a91d066e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646579794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.646579794
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1162057488
Short name T191
Test name
Test status
Simulation time 542051340 ps
CPU time 1.35 seconds
Started Jul 12 05:53:44 PM PDT 24
Finished Jul 12 05:53:47 PM PDT 24
Peak memory 196624 kb
Host smart-a906d12e-822f-40c6-88d1-781a8d92cedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162057488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1162057488
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.272409307
Short name T5
Test name
Test status
Simulation time 323625769709 ps
CPU time 28.93 seconds
Started Jul 12 05:53:45 PM PDT 24
Finished Jul 12 05:54:17 PM PDT 24
Peak memory 191900 kb
Host smart-098f5cc6-963a-4438-8500-07ee52b7e51e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272409307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.272409307
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.361024280
Short name T43
Test name
Test status
Simulation time 494789599 ps
CPU time 1.25 seconds
Started Jul 12 05:53:47 PM PDT 24
Finished Jul 12 05:53:52 PM PDT 24
Peak memory 196560 kb
Host smart-f267bf3c-eb5c-4623-858f-e13a713ec9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361024280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.361024280
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2904620205
Short name T147
Test name
Test status
Simulation time 437275059 ps
CPU time 1.27 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:53:51 PM PDT 24
Peak memory 196684 kb
Host smart-ad4b03bb-7937-4ce8-ae09-8d889f1bc7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904620205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2904620205
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2265330992
Short name T55
Test name
Test status
Simulation time 486422456 ps
CPU time 1.34 seconds
Started Jul 12 05:53:53 PM PDT 24
Finished Jul 12 05:53:59 PM PDT 24
Peak memory 196756 kb
Host smart-c6a8e643-c8e5-4124-bb8b-2fc70293b5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265330992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2265330992
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1280705255
Short name T192
Test name
Test status
Simulation time 586835009 ps
CPU time 0.73 seconds
Started Jul 12 05:53:47 PM PDT 24
Finished Jul 12 05:53:51 PM PDT 24
Peak memory 196712 kb
Host smart-629fcfc0-5f60-42c5-8446-2d1d4279b9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280705255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1280705255
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3076624520
Short name T11
Test name
Test status
Simulation time 163046346588 ps
CPU time 202.16 seconds
Started Jul 12 05:53:57 PM PDT 24
Finished Jul 12 05:57:25 PM PDT 24
Peak memory 198436 kb
Host smart-36ca7563-d20f-4b1e-a003-1afbad3c88e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076624520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3076624520
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2041972641
Short name T49
Test name
Test status
Simulation time 53833175067 ps
CPU time 76.23 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:55:22 PM PDT 24
Peak memory 191936 kb
Host smart-d83841ec-0521-4800-bf3b-7acd7ba077b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041972641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2041972641
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3629562828
Short name T101
Test name
Test status
Simulation time 440059491 ps
CPU time 0.76 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:08 PM PDT 24
Peak memory 196624 kb
Host smart-d9e8f26a-81de-4c05-828d-93a315fc97f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629562828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3629562828
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2476614128
Short name T86
Test name
Test status
Simulation time 64777231545 ps
CPU time 499.4 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 06:02:26 PM PDT 24
Peak memory 213988 kb
Host smart-9360674f-3186-4658-b096-d881a4847a31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476614128 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2476614128
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2980283009
Short name T189
Test name
Test status
Simulation time 386269820 ps
CPU time 0.71 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 196604 kb
Host smart-0b5a664f-e730-4775-b5f5-515e17d20ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980283009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2980283009
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3652903048
Short name T170
Test name
Test status
Simulation time 171303322640 ps
CPU time 17.45 seconds
Started Jul 12 05:54:14 PM PDT 24
Finished Jul 12 05:54:32 PM PDT 24
Peak memory 192940 kb
Host smart-bc260735-d761-4789-aeed-d1b28d4e0028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652903048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3652903048
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3292148804
Short name T178
Test name
Test status
Simulation time 511625544 ps
CPU time 1.25 seconds
Started Jul 12 05:54:20 PM PDT 24
Finished Jul 12 05:54:23 PM PDT 24
Peak memory 196580 kb
Host smart-45b9c6b7-e5ca-46f1-abed-abf785d0aec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292148804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3292148804
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.42254785
Short name T176
Test name
Test status
Simulation time 574446152 ps
CPU time 1.38 seconds
Started Jul 12 05:54:17 PM PDT 24
Finished Jul 12 05:54:21 PM PDT 24
Peak memory 196616 kb
Host smart-8bd05719-4fb0-4039-b38f-18c694bfefe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42254785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.42254785
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1228622199
Short name T119
Test name
Test status
Simulation time 523845378 ps
CPU time 1.29 seconds
Started Jul 12 05:54:30 PM PDT 24
Finished Jul 12 05:54:33 PM PDT 24
Peak memory 196712 kb
Host smart-98b5094b-f17a-4fb0-b726-f63ce0c79e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228622199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1228622199
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1425710846
Short name T177
Test name
Test status
Simulation time 531239735 ps
CPU time 0.72 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 05:54:32 PM PDT 24
Peak memory 196620 kb
Host smart-84283c24-d681-44dc-bdb6-e8c73ef815e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425710846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1425710846
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1842406515
Short name T175
Test name
Test status
Simulation time 351438083 ps
CPU time 0.99 seconds
Started Jul 12 05:53:56 PM PDT 24
Finished Jul 12 05:54:02 PM PDT 24
Peak memory 196640 kb
Host smart-ace16d56-a75e-471e-bef1-cde47e7815a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842406515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1842406515
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1531359064
Short name T41
Test name
Test status
Simulation time 20749655561 ps
CPU time 224.36 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:57:48 PM PDT 24
Peak memory 214940 kb
Host smart-7c9457ad-41fb-4c90-9024-3a0a53569e73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531359064 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1531359064
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2054622478
Short name T181
Test name
Test status
Simulation time 621970144 ps
CPU time 0.94 seconds
Started Jul 12 05:54:00 PM PDT 24
Finished Jul 12 05:54:06 PM PDT 24
Peak memory 196624 kb
Host smart-27863155-5dd7-4aca-98a7-47910dd6f722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054622478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2054622478
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1392639372
Short name T182
Test name
Test status
Simulation time 439629070 ps
CPU time 0.74 seconds
Started Jul 12 05:54:00 PM PDT 24
Finished Jul 12 05:54:07 PM PDT 24
Peak memory 196620 kb
Host smart-bd5ebd79-93d8-4d8f-ae5a-41053db632cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392639372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1392639372
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.372567408
Short name T173
Test name
Test status
Simulation time 603079487 ps
CPU time 0.65 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:54:17 PM PDT 24
Peak memory 196580 kb
Host smart-12be6bc3-75cc-4e47-bf2d-593b6b096b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372567408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.372567408
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.948587519
Short name T179
Test name
Test status
Simulation time 482492662 ps
CPU time 0.93 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 196576 kb
Host smart-0a6ed143-e12a-4d85-a902-c9ef823f42b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948587519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.948587519
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2265832195
Short name T190
Test name
Test status
Simulation time 621961130 ps
CPU time 0.82 seconds
Started Jul 12 05:53:39 PM PDT 24
Finished Jul 12 05:53:41 PM PDT 24
Peak memory 196648 kb
Host smart-e5c8d622-a2f1-48c8-a65f-fe401c4ec678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265832195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2265832195
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2130822404
Short name T419
Test name
Test status
Simulation time 653176070 ps
CPU time 1.14 seconds
Started Jul 12 05:54:32 PM PDT 24
Finished Jul 12 05:54:35 PM PDT 24
Peak memory 194404 kb
Host smart-e9f54ac6-c5f0-4e33-bd6f-f5bb549346a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130822404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2130822404
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3222619516
Short name T400
Test name
Test status
Simulation time 13855178461 ps
CPU time 29.37 seconds
Started Jul 12 05:54:30 PM PDT 24
Finished Jul 12 05:55:02 PM PDT 24
Peak memory 184012 kb
Host smart-b2c4081e-fedb-43ee-bfa1-92c150c6ef39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222619516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3222619516
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3743573058
Short name T350
Test name
Test status
Simulation time 1179919147 ps
CPU time 2.43 seconds
Started Jul 12 05:54:28 PM PDT 24
Finished Jul 12 05:54:33 PM PDT 24
Peak memory 183792 kb
Host smart-62a3015b-abe5-4a37-820e-64b753dbde68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743573058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3743573058
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1166695508
Short name T357
Test name
Test status
Simulation time 370245357 ps
CPU time 0.78 seconds
Started Jul 12 05:54:32 PM PDT 24
Finished Jul 12 05:54:35 PM PDT 24
Peak memory 195608 kb
Host smart-3523c19c-d394-4ce6-9ad3-156b3a7ca8ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166695508 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1166695508
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4225612704
Short name T70
Test name
Test status
Simulation time 546040006 ps
CPU time 0.91 seconds
Started Jul 12 05:54:27 PM PDT 24
Finished Jul 12 05:54:29 PM PDT 24
Peak memory 193104 kb
Host smart-e266f34e-40ed-4f08-849e-a3a14b766871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225612704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4225612704
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.375964293
Short name T288
Test name
Test status
Simulation time 500375027 ps
CPU time 0.72 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 05:54:32 PM PDT 24
Peak memory 192964 kb
Host smart-d3663d60-43c3-4356-9ad3-81b2ee837d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375964293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.375964293
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3011336728
Short name T300
Test name
Test status
Simulation time 411831693 ps
CPU time 0.66 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 05:54:32 PM PDT 24
Peak memory 183636 kb
Host smart-62f5e435-f533-4346-ab79-d6d3c3772167
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011336728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3011336728
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.236985128
Short name T371
Test name
Test status
Simulation time 557692254 ps
CPU time 0.55 seconds
Started Jul 12 05:54:28 PM PDT 24
Finished Jul 12 05:54:31 PM PDT 24
Peak memory 183716 kb
Host smart-76bf5fbd-496c-4b76-8a8b-252e804e97fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236985128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.236985128
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2349387545
Short name T342
Test name
Test status
Simulation time 2637442688 ps
CPU time 1.59 seconds
Started Jul 12 05:54:32 PM PDT 24
Finished Jul 12 05:54:36 PM PDT 24
Peak memory 195140 kb
Host smart-946bb962-a37a-482d-be67-c52d72658238
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349387545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2349387545
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2880660667
Short name T289
Test name
Test status
Simulation time 650787706 ps
CPU time 1.88 seconds
Started Jul 12 05:54:30 PM PDT 24
Finished Jul 12 05:54:35 PM PDT 24
Peak memory 198588 kb
Host smart-cf48d011-ef92-4d98-ae02-be6e3e41e200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880660667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2880660667
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3717152747
Short name T378
Test name
Test status
Simulation time 4049543245 ps
CPU time 2.05 seconds
Started Jul 12 05:54:33 PM PDT 24
Finished Jul 12 05:54:37 PM PDT 24
Peak memory 197700 kb
Host smart-114b1f92-96d6-4e90-ac0c-9a3d22402685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717152747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3717152747
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3956116511
Short name T411
Test name
Test status
Simulation time 412168952 ps
CPU time 0.79 seconds
Started Jul 12 05:54:27 PM PDT 24
Finished Jul 12 05:54:29 PM PDT 24
Peak memory 193220 kb
Host smart-719e2d5e-2409-45ae-9243-62f3f5068f5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956116511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3956116511
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3446234200
Short name T59
Test name
Test status
Simulation time 7107439315 ps
CPU time 17.18 seconds
Started Jul 12 05:54:32 PM PDT 24
Finished Jul 12 05:54:51 PM PDT 24
Peak memory 184000 kb
Host smart-6c0d84bb-8520-4e1a-9e4a-3cc046a923ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446234200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3446234200
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2264291372
Short name T38
Test name
Test status
Simulation time 702730846 ps
CPU time 0.83 seconds
Started Jul 12 05:54:28 PM PDT 24
Finished Jul 12 05:54:30 PM PDT 24
Peak memory 193012 kb
Host smart-94b3cb09-2221-492f-82e7-efaa6d3b1fc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264291372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2264291372
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3024618999
Short name T404
Test name
Test status
Simulation time 338109941 ps
CPU time 1.07 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 05:54:32 PM PDT 24
Peak memory 195164 kb
Host smart-666f6beb-3e34-47a5-8b71-2aa88790885a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024618999 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3024618999
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3426162863
Short name T62
Test name
Test status
Simulation time 316454292 ps
CPU time 1.02 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 05:54:33 PM PDT 24
Peak memory 193236 kb
Host smart-310c0a57-fde5-4242-855b-aec21e309579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426162863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3426162863
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.828541120
Short name T415
Test name
Test status
Simulation time 482984503 ps
CPU time 1.05 seconds
Started Jul 12 05:54:26 PM PDT 24
Finished Jul 12 05:54:28 PM PDT 24
Peak memory 192968 kb
Host smart-1905be5b-9950-44eb-a79e-953a0ff19e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828541120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.828541120
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.511340541
Short name T319
Test name
Test status
Simulation time 294664132 ps
CPU time 0.94 seconds
Started Jul 12 05:54:28 PM PDT 24
Finished Jul 12 05:54:30 PM PDT 24
Peak memory 183664 kb
Host smart-e6f51e36-2c0a-49f7-8516-11b721357148
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511340541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.511340541
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.305184192
Short name T356
Test name
Test status
Simulation time 312029553 ps
CPU time 0.88 seconds
Started Jul 12 05:54:33 PM PDT 24
Finished Jul 12 05:54:36 PM PDT 24
Peak memory 183668 kb
Host smart-60b62e10-7afa-4218-b764-27470099d8e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305184192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.305184192
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4216139508
Short name T347
Test name
Test status
Simulation time 2023889119 ps
CPU time 1.59 seconds
Started Jul 12 05:54:31 PM PDT 24
Finished Jul 12 05:54:35 PM PDT 24
Peak memory 195164 kb
Host smart-833225ff-7dbc-48c1-9a93-ae396963db75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216139508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4216139508
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.964318246
Short name T394
Test name
Test status
Simulation time 368244995 ps
CPU time 1.32 seconds
Started Jul 12 05:54:34 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 198664 kb
Host smart-6dd06984-9c25-490f-acc3-68cdd20a8c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964318246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.964318246
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3163547943
Short name T360
Test name
Test status
Simulation time 519717469 ps
CPU time 1.14 seconds
Started Jul 12 05:54:44 PM PDT 24
Finished Jul 12 05:54:46 PM PDT 24
Peak memory 196596 kb
Host smart-f7b8d488-daa5-47d2-8f0d-c28850b1c612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163547943 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3163547943
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3996645903
Short name T198
Test name
Test status
Simulation time 550280285 ps
CPU time 0.92 seconds
Started Jul 12 05:54:43 PM PDT 24
Finished Jul 12 05:54:45 PM PDT 24
Peak memory 193084 kb
Host smart-4bb80261-f5a3-427a-90a2-f97df6fde037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996645903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3996645903
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1617337636
Short name T334
Test name
Test status
Simulation time 424384130 ps
CPU time 0.65 seconds
Started Jul 12 05:54:47 PM PDT 24
Finished Jul 12 05:54:51 PM PDT 24
Peak memory 183720 kb
Host smart-dcbac359-5dbe-4f7d-82e6-dfa29307a0d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617337636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1617337636
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3772121769
Short name T327
Test name
Test status
Simulation time 1370322800 ps
CPU time 3.51 seconds
Started Jul 12 05:54:44 PM PDT 24
Finished Jul 12 05:54:48 PM PDT 24
Peak memory 193200 kb
Host smart-a0016e39-516b-4af9-954c-70732a708230
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772121769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3772121769
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.744018093
Short name T338
Test name
Test status
Simulation time 743178786 ps
CPU time 2.57 seconds
Started Jul 12 05:54:48 PM PDT 24
Finished Jul 12 05:54:54 PM PDT 24
Peak memory 198620 kb
Host smart-91a388e9-e509-43c6-824a-f024d1d762c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744018093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.744018093
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3553262960
Short name T296
Test name
Test status
Simulation time 447789125 ps
CPU time 1.12 seconds
Started Jul 12 05:54:45 PM PDT 24
Finished Jul 12 05:54:48 PM PDT 24
Peak memory 196112 kb
Host smart-138a6ea3-3a69-440f-aab2-36ae39f614f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553262960 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3553262960
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2948468654
Short name T390
Test name
Test status
Simulation time 441487059 ps
CPU time 0.63 seconds
Started Jul 12 05:54:44 PM PDT 24
Finished Jul 12 05:54:46 PM PDT 24
Peak memory 193076 kb
Host smart-69cae4e4-01b9-46df-9b68-8ad72b7192da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948468654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2948468654
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3681291889
Short name T407
Test name
Test status
Simulation time 449154417 ps
CPU time 1.16 seconds
Started Jul 12 05:54:45 PM PDT 24
Finished Jul 12 05:54:47 PM PDT 24
Peak memory 183736 kb
Host smart-1e2668e6-c013-4fa1-8af2-b05cd629d065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681291889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3681291889
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.865032049
Short name T352
Test name
Test status
Simulation time 719218528 ps
CPU time 2.12 seconds
Started Jul 12 05:54:48 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 198616 kb
Host smart-e82e3065-811f-4364-ac74-0924f372152c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865032049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.865032049
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2367252641
Short name T333
Test name
Test status
Simulation time 8078146940 ps
CPU time 13.84 seconds
Started Jul 12 05:54:49 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 198224 kb
Host smart-c7ed2bd7-d595-4046-8619-ca22f34cc86b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367252641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2367252641
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3092192432
Short name T386
Test name
Test status
Simulation time 567605729 ps
CPU time 0.96 seconds
Started Jul 12 05:54:50 PM PDT 24
Finished Jul 12 05:54:54 PM PDT 24
Peak memory 195808 kb
Host smart-6747a3c1-b8ba-4d51-b1b6-7084214d3fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092192432 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3092192432
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3885630276
Short name T375
Test name
Test status
Simulation time 477737944 ps
CPU time 0.72 seconds
Started Jul 12 05:54:49 PM PDT 24
Finished Jul 12 05:54:52 PM PDT 24
Peak memory 193004 kb
Host smart-dfd9f43b-d819-41d9-aec1-4ed5e7f13f92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885630276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3885630276
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.588984357
Short name T364
Test name
Test status
Simulation time 506923230 ps
CPU time 1.19 seconds
Started Jul 12 05:54:48 PM PDT 24
Finished Jul 12 05:54:52 PM PDT 24
Peak memory 183724 kb
Host smart-492546d1-c503-4eb6-87cd-01dd8f8f43c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588984357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.588984357
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.535388177
Short name T71
Test name
Test status
Simulation time 1155858240 ps
CPU time 1.91 seconds
Started Jul 12 05:54:48 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 193624 kb
Host smart-ce034e1c-f1a7-4809-880b-9f104f7034fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535388177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.535388177
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2175458807
Short name T363
Test name
Test status
Simulation time 394434315 ps
CPU time 2.46 seconds
Started Jul 12 05:54:46 PM PDT 24
Finished Jul 12 05:54:51 PM PDT 24
Peak memory 198620 kb
Host smart-0edb38ed-126d-432b-99c2-92018392e016
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175458807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2175458807
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.590155106
Short name T35
Test name
Test status
Simulation time 8828032403 ps
CPU time 14.8 seconds
Started Jul 12 05:54:53 PM PDT 24
Finished Jul 12 05:55:10 PM PDT 24
Peak memory 198364 kb
Host smart-679c6345-3e18-404f-a10c-b31d672ff1c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590155106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.590155106
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2487816870
Short name T369
Test name
Test status
Simulation time 592844384 ps
CPU time 1.13 seconds
Started Jul 12 05:54:49 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 197632 kb
Host smart-3acfe526-5932-4f83-a48f-16c2ac54b67d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487816870 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2487816870
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2144625667
Short name T61
Test name
Test status
Simulation time 525730115 ps
CPU time 0.77 seconds
Started Jul 12 05:54:48 PM PDT 24
Finished Jul 12 05:54:52 PM PDT 24
Peak memory 192936 kb
Host smart-b4910d96-ad33-4994-81a3-4bd0064d4198
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144625667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2144625667
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.488655041
Short name T398
Test name
Test status
Simulation time 441444068 ps
CPU time 0.66 seconds
Started Jul 12 05:54:50 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 183732 kb
Host smart-80888ea8-6679-4d1b-877a-f90078dd15b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488655041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.488655041
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.615285349
Short name T73
Test name
Test status
Simulation time 2974964428 ps
CPU time 1.7 seconds
Started Jul 12 05:54:49 PM PDT 24
Finished Jul 12 05:54:54 PM PDT 24
Peak memory 194476 kb
Host smart-68394427-d573-4c4c-a736-f4f26a7332f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615285349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.615285349
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3059849972
Short name T316
Test name
Test status
Simulation time 434838761 ps
CPU time 2.23 seconds
Started Jul 12 05:54:50 PM PDT 24
Finished Jul 12 05:54:55 PM PDT 24
Peak memory 198616 kb
Host smart-992496d9-4f31-4bc6-b1df-ecb00804adb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059849972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3059849972
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.210710565
Short name T312
Test name
Test status
Simulation time 8810764512 ps
CPU time 6.69 seconds
Started Jul 12 05:54:49 PM PDT 24
Finished Jul 12 05:54:59 PM PDT 24
Peak memory 198268 kb
Host smart-4318e4c5-3cdf-42fe-b5f8-e82ff7e592e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210710565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.210710565
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1817984385
Short name T401
Test name
Test status
Simulation time 589408622 ps
CPU time 1.07 seconds
Started Jul 12 05:54:51 PM PDT 24
Finished Jul 12 05:54:54 PM PDT 24
Peak memory 195940 kb
Host smart-7e5f07ed-4af9-4468-95d6-668ef0fbd65a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817984385 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1817984385
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2255183306
Short name T68
Test name
Test status
Simulation time 274144217 ps
CPU time 0.85 seconds
Started Jul 12 05:54:50 PM PDT 24
Finished Jul 12 05:54:54 PM PDT 24
Peak memory 192992 kb
Host smart-f7e154aa-9842-412a-bc9f-bfa8d7766675
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255183306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2255183306
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2266525630
Short name T382
Test name
Test status
Simulation time 465009852 ps
CPU time 1.09 seconds
Started Jul 12 05:54:52 PM PDT 24
Finished Jul 12 05:54:55 PM PDT 24
Peak memory 183652 kb
Host smart-5cd4914f-87c0-4aa1-8344-9e83b5cadef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266525630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2266525630
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1889100604
Short name T324
Test name
Test status
Simulation time 1186455194 ps
CPU time 1.98 seconds
Started Jul 12 05:54:49 PM PDT 24
Finished Jul 12 05:54:54 PM PDT 24
Peak memory 192924 kb
Host smart-f6dd9379-fe47-4fd2-be32-952e002bf79a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889100604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1889100604
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1097600684
Short name T420
Test name
Test status
Simulation time 450899520 ps
CPU time 1.64 seconds
Started Jul 12 05:54:49 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 198392 kb
Host smart-13981ca3-8dc3-4154-82bf-1747a40f0f84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097600684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1097600684
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.156881016
Short name T197
Test name
Test status
Simulation time 4682872389 ps
CPU time 4.31 seconds
Started Jul 12 05:54:50 PM PDT 24
Finished Jul 12 05:54:57 PM PDT 24
Peak memory 197988 kb
Host smart-41486c46-0d7e-4a01-8a3d-16e40cb77b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156881016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.156881016
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2673526286
Short name T287
Test name
Test status
Simulation time 422140072 ps
CPU time 1.24 seconds
Started Jul 12 05:55:04 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 197088 kb
Host smart-cfb2199e-990e-45fe-8753-c7c85ec3715d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673526286 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2673526286
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2618751636
Short name T331
Test name
Test status
Simulation time 495569912 ps
CPU time 1.37 seconds
Started Jul 12 05:54:56 PM PDT 24
Finished Jul 12 05:54:59 PM PDT 24
Peak memory 193424 kb
Host smart-c780ce5d-6dae-4a24-ae5a-481d761587d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618751636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2618751636
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3471335307
Short name T395
Test name
Test status
Simulation time 381497776 ps
CPU time 0.63 seconds
Started Jul 12 05:54:49 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 183740 kb
Host smart-c4c1ac9b-c938-4553-aad1-13a7c823d104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471335307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3471335307
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1690662340
Short name T384
Test name
Test status
Simulation time 2054478950 ps
CPU time 2.2 seconds
Started Jul 12 05:54:58 PM PDT 24
Finished Jul 12 05:55:02 PM PDT 24
Peak memory 183928 kb
Host smart-3b249b0f-8a2e-4c61-acdd-3eaa736d07c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690662340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1690662340
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2820570136
Short name T330
Test name
Test status
Simulation time 606563258 ps
CPU time 2.67 seconds
Started Jul 12 05:54:47 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 198624 kb
Host smart-66ee2275-5410-489d-8fa2-1233122c8e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820570136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2820570136
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3864912656
Short name T408
Test name
Test status
Simulation time 4337582408 ps
CPU time 3.57 seconds
Started Jul 12 05:54:49 PM PDT 24
Finished Jul 12 05:54:55 PM PDT 24
Peak memory 196880 kb
Host smart-1c7bd327-d87e-4321-ba3c-21ad4c816c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864912656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3864912656
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4236690859
Short name T391
Test name
Test status
Simulation time 547305178 ps
CPU time 1.53 seconds
Started Jul 12 05:54:54 PM PDT 24
Finished Jul 12 05:54:57 PM PDT 24
Peak memory 196284 kb
Host smart-1263787e-5bb5-4c4a-896b-02ca761a54a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236690859 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4236690859
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.677711739
Short name T311
Test name
Test status
Simulation time 435656613 ps
CPU time 0.78 seconds
Started Jul 12 05:55:05 PM PDT 24
Finished Jul 12 05:55:07 PM PDT 24
Peak memory 193456 kb
Host smart-9da6afbf-9ecf-4f6a-83cb-e0ea0d7445e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677711739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.677711739
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1162991135
Short name T399
Test name
Test status
Simulation time 485898018 ps
CPU time 1.11 seconds
Started Jul 12 05:54:53 PM PDT 24
Finished Jul 12 05:54:57 PM PDT 24
Peak memory 192968 kb
Host smart-48e60074-5d20-4f2d-871f-ada9bd156465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162991135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1162991135
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4066880894
Short name T33
Test name
Test status
Simulation time 1408613375 ps
CPU time 1.15 seconds
Started Jul 12 05:54:56 PM PDT 24
Finished Jul 12 05:54:59 PM PDT 24
Peak memory 193696 kb
Host smart-62ac59db-126f-4f62-823e-7d0cc13a766e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066880894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.4066880894
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1931846646
Short name T308
Test name
Test status
Simulation time 384100243 ps
CPU time 1.22 seconds
Started Jul 12 05:54:54 PM PDT 24
Finished Jul 12 05:54:57 PM PDT 24
Peak memory 198532 kb
Host smart-f02eecd8-1ea6-4cad-9fee-8ff08b0c72dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931846646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1931846646
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1981927981
Short name T423
Test name
Test status
Simulation time 4508684915 ps
CPU time 1.73 seconds
Started Jul 12 05:54:54 PM PDT 24
Finished Jul 12 05:54:58 PM PDT 24
Peak memory 197868 kb
Host smart-d19a9f36-d21e-4d10-a14c-431d2167f50a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981927981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1981927981
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2321803649
Short name T298
Test name
Test status
Simulation time 562222608 ps
CPU time 1.36 seconds
Started Jul 12 05:55:04 PM PDT 24
Finished Jul 12 05:55:07 PM PDT 24
Peak memory 196192 kb
Host smart-00980a9c-67f6-4681-83c2-57063e62900d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321803649 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2321803649
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2050502297
Short name T372
Test name
Test status
Simulation time 458175533 ps
CPU time 1.09 seconds
Started Jul 12 05:55:04 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 193384 kb
Host smart-f9445163-4c21-49d6-8f96-d274b7a96ed8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050502297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2050502297
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.137701700
Short name T355
Test name
Test status
Simulation time 410204669 ps
CPU time 0.67 seconds
Started Jul 12 05:54:58 PM PDT 24
Finished Jul 12 05:55:00 PM PDT 24
Peak memory 193048 kb
Host smart-75d105c0-2770-4f2c-a63b-b53e1f1926e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137701700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.137701700
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.369567020
Short name T72
Test name
Test status
Simulation time 2715243001 ps
CPU time 4.23 seconds
Started Jul 12 05:54:56 PM PDT 24
Finished Jul 12 05:55:02 PM PDT 24
Peak memory 193224 kb
Host smart-5ed2fd32-665f-45ef-9e05-2a88848b3c8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369567020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.369567020
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.133554233
Short name T332
Test name
Test status
Simulation time 604728895 ps
CPU time 1.32 seconds
Started Jul 12 05:55:04 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 198456 kb
Host smart-c6049914-5945-419a-9111-c3b6fd3e583c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133554233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.133554233
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3543432918
Short name T318
Test name
Test status
Simulation time 4016626112 ps
CPU time 7.36 seconds
Started Jul 12 05:55:03 PM PDT 24
Finished Jul 12 05:55:11 PM PDT 24
Peak memory 197560 kb
Host smart-f37c797b-50b6-41ee-8c29-f1484ef169c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543432918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3543432918
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1559580923
Short name T341
Test name
Test status
Simulation time 528069180 ps
CPU time 1.04 seconds
Started Jul 12 05:55:04 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 197004 kb
Host smart-bacc8697-e324-497b-a651-057945343b79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559580923 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1559580923
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.537773707
Short name T313
Test name
Test status
Simulation time 364627350 ps
CPU time 0.68 seconds
Started Jul 12 05:54:56 PM PDT 24
Finished Jul 12 05:54:59 PM PDT 24
Peak memory 192048 kb
Host smart-78874d30-2b6f-4575-8024-94cbab0931b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537773707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.537773707
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.678924892
Short name T346
Test name
Test status
Simulation time 470966184 ps
CPU time 1.31 seconds
Started Jul 12 05:54:57 PM PDT 24
Finished Jul 12 05:55:01 PM PDT 24
Peak memory 192964 kb
Host smart-c1a7f68d-5b50-49fe-800b-bfe1d3cf8063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678924892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.678924892
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3299904065
Short name T315
Test name
Test status
Simulation time 2798168387 ps
CPU time 4.09 seconds
Started Jul 12 05:54:57 PM PDT 24
Finished Jul 12 05:55:02 PM PDT 24
Peak memory 193968 kb
Host smart-36644635-2f4e-4a26-bf27-23835a20548a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299904065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3299904065
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2904676937
Short name T294
Test name
Test status
Simulation time 680275219 ps
CPU time 1.39 seconds
Started Jul 12 05:54:57 PM PDT 24
Finished Jul 12 05:55:01 PM PDT 24
Peak memory 198604 kb
Host smart-a7a7bf9f-f46a-4fb3-aae2-0e2b286288d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904676937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2904676937
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2546130573
Short name T422
Test name
Test status
Simulation time 8731825748 ps
CPU time 12.57 seconds
Started Jul 12 05:54:56 PM PDT 24
Finished Jul 12 05:55:10 PM PDT 24
Peak memory 198184 kb
Host smart-523598e6-b056-4301-8f3b-0b1b353cb519
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546130573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2546130573
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3574324479
Short name T416
Test name
Test status
Simulation time 419154178 ps
CPU time 0.78 seconds
Started Jul 12 05:55:04 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 195540 kb
Host smart-b346d84a-387c-49dd-96cb-5871351fc0b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574324479 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3574324479
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.638879748
Short name T69
Test name
Test status
Simulation time 417636476 ps
CPU time 0.78 seconds
Started Jul 12 05:55:04 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 192972 kb
Host smart-98ee7640-0c02-471f-ab13-054118529743
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638879748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.638879748
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2722403527
Short name T309
Test name
Test status
Simulation time 328557771 ps
CPU time 0.97 seconds
Started Jul 12 05:54:55 PM PDT 24
Finished Jul 12 05:54:58 PM PDT 24
Peak memory 183740 kb
Host smart-598bd809-775c-4e8d-95de-653cef3c7302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722403527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2722403527
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4093842149
Short name T414
Test name
Test status
Simulation time 1734968354 ps
CPU time 4.97 seconds
Started Jul 12 05:54:58 PM PDT 24
Finished Jul 12 05:55:04 PM PDT 24
Peak memory 194880 kb
Host smart-034485c0-6caf-4a33-bcf2-f1a181699b17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093842149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.4093842149
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.218033372
Short name T367
Test name
Test status
Simulation time 411153404 ps
CPU time 1.58 seconds
Started Jul 12 05:54:53 PM PDT 24
Finished Jul 12 05:54:57 PM PDT 24
Peak memory 198636 kb
Host smart-19019a30-8787-4eff-b5c0-5d9e9ac793e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218033372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.218033372
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.979432037
Short name T343
Test name
Test status
Simulation time 8031623858 ps
CPU time 4.69 seconds
Started Jul 12 05:54:56 PM PDT 24
Finished Jul 12 05:55:03 PM PDT 24
Peak memory 198348 kb
Host smart-3e815a3a-b740-4c98-9766-873eb99d8c59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979432037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.979432037
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3078765076
Short name T65
Test name
Test status
Simulation time 668495013 ps
CPU time 1.59 seconds
Started Jul 12 05:54:35 PM PDT 24
Finished Jul 12 05:54:39 PM PDT 24
Peak memory 183988 kb
Host smart-f3655e15-49c7-4d39-ac79-08e27e6307f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078765076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3078765076
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2830636293
Short name T57
Test name
Test status
Simulation time 13099901612 ps
CPU time 35.56 seconds
Started Jul 12 05:54:33 PM PDT 24
Finished Jul 12 05:55:11 PM PDT 24
Peak memory 192224 kb
Host smart-eb0438f9-3517-4bde-b84a-6c4c80c8a4d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830636293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2830636293
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3855721621
Short name T392
Test name
Test status
Simulation time 768063591 ps
CPU time 0.77 seconds
Started Jul 12 05:54:35 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 193012 kb
Host smart-ac171197-ad23-44a0-9c98-8df98eb467cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855721621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3855721621
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1547669985
Short name T322
Test name
Test status
Simulation time 441878413 ps
CPU time 0.74 seconds
Started Jul 12 05:54:35 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 195364 kb
Host smart-72d22804-6805-4dfd-8532-78ef78bb760e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547669985 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1547669985
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2073489262
Short name T76
Test name
Test status
Simulation time 449937404 ps
CPU time 1.25 seconds
Started Jul 12 05:54:35 PM PDT 24
Finished Jul 12 05:54:39 PM PDT 24
Peak memory 192988 kb
Host smart-4fed2927-27ce-4f71-b08c-c522ff96a986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073489262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2073489262
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2543711619
Short name T325
Test name
Test status
Simulation time 440234662 ps
CPU time 1.22 seconds
Started Jul 12 05:54:34 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 183748 kb
Host smart-d5c17a07-b59a-4c42-8d5e-7a7bc2154bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543711619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2543711619
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1872316301
Short name T359
Test name
Test status
Simulation time 367654152 ps
CPU time 0.8 seconds
Started Jul 12 05:54:33 PM PDT 24
Finished Jul 12 05:54:35 PM PDT 24
Peak memory 183660 kb
Host smart-89678de7-ff33-4cc2-bc34-d897746a45b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872316301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1872316301
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1152631623
Short name T403
Test name
Test status
Simulation time 476469528 ps
CPU time 0.73 seconds
Started Jul 12 05:54:30 PM PDT 24
Finished Jul 12 05:54:33 PM PDT 24
Peak memory 183708 kb
Host smart-73f3da6b-3542-4a69-a135-20bfd9d94922
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152631623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1152631623
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.862601005
Short name T389
Test name
Test status
Simulation time 2690149471 ps
CPU time 6.37 seconds
Started Jul 12 05:54:35 PM PDT 24
Finished Jul 12 05:54:44 PM PDT 24
Peak memory 194116 kb
Host smart-68d55d9b-7485-4c7f-9c14-b0e8515f8d46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862601005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.862601005
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2241194121
Short name T354
Test name
Test status
Simulation time 497580156 ps
CPU time 1.42 seconds
Started Jul 12 05:54:34 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 198632 kb
Host smart-a3b94c0e-cd62-4082-9d57-d2fa0b222e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241194121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2241194121
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.427511905
Short name T196
Test name
Test status
Simulation time 4442148714 ps
CPU time 1.29 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 05:54:33 PM PDT 24
Peak memory 196884 kb
Host smart-b79cb8bc-099b-44ef-8686-70e641f20d62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427511905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.427511905
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1451252895
Short name T379
Test name
Test status
Simulation time 420850050 ps
CPU time 0.84 seconds
Started Jul 12 05:55:03 PM PDT 24
Finished Jul 12 05:55:05 PM PDT 24
Peak memory 192960 kb
Host smart-844bd99c-7228-4638-abc6-ee02ceb196b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451252895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1451252895
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1070404986
Short name T351
Test name
Test status
Simulation time 322737726 ps
CPU time 0.64 seconds
Started Jul 12 05:54:58 PM PDT 24
Finished Jul 12 05:55:00 PM PDT 24
Peak memory 192944 kb
Host smart-90bf3a50-f672-40f5-b29a-d150085946a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070404986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1070404986
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1405571747
Short name T368
Test name
Test status
Simulation time 425490552 ps
CPU time 0.83 seconds
Started Jul 12 05:55:03 PM PDT 24
Finished Jul 12 05:55:04 PM PDT 24
Peak memory 192960 kb
Host smart-3ecccc7e-5a8f-4476-ac5e-f33595408d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405571747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1405571747
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3169106198
Short name T376
Test name
Test status
Simulation time 511826468 ps
CPU time 1.32 seconds
Started Jul 12 05:55:03 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 183740 kb
Host smart-858dbfc3-70b0-457b-b30c-232d704cf5cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169106198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3169106198
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.803001673
Short name T405
Test name
Test status
Simulation time 388698424 ps
CPU time 1.04 seconds
Started Jul 12 05:54:56 PM PDT 24
Finished Jul 12 05:54:59 PM PDT 24
Peak memory 183180 kb
Host smart-b498da52-6a20-42c8-a87b-fe78bd4b3029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803001673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.803001673
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2092595227
Short name T406
Test name
Test status
Simulation time 472397098 ps
CPU time 1.24 seconds
Started Jul 12 05:54:55 PM PDT 24
Finished Jul 12 05:54:58 PM PDT 24
Peak memory 183716 kb
Host smart-7cbc9811-367d-4afe-9bbc-1d276c78f03f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092595227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2092595227
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2325661
Short name T358
Test name
Test status
Simulation time 462384185 ps
CPU time 1.16 seconds
Started Jul 12 05:54:50 PM PDT 24
Finished Jul 12 05:54:54 PM PDT 24
Peak memory 183756 kb
Host smart-f4072726-4409-4067-85dc-3ed8fe64feb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2325661
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3968796112
Short name T328
Test name
Test status
Simulation time 345577019 ps
CPU time 0.68 seconds
Started Jul 12 05:55:03 PM PDT 24
Finished Jul 12 05:55:05 PM PDT 24
Peak memory 192924 kb
Host smart-dc96f45e-8e78-496d-b42e-6cd75657e37d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968796112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3968796112
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3035166498
Short name T421
Test name
Test status
Simulation time 304852880 ps
CPU time 1.02 seconds
Started Jul 12 05:55:03 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 183740 kb
Host smart-8be92319-1d45-4fc2-aab3-36d0e30a2e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035166498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3035166498
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3654903285
Short name T305
Test name
Test status
Simulation time 494840053 ps
CPU time 0.76 seconds
Started Jul 12 05:54:56 PM PDT 24
Finished Jul 12 05:54:58 PM PDT 24
Peak memory 183928 kb
Host smart-b1e9e10c-190d-4516-a4ff-f3c00c0acb59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654903285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3654903285
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4193465063
Short name T64
Test name
Test status
Simulation time 593705345 ps
CPU time 0.76 seconds
Started Jul 12 05:54:35 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 193948 kb
Host smart-bcd46a49-f438-4edc-b4a5-a4c8043107f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193465063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4193465063
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2103633704
Short name T412
Test name
Test status
Simulation time 1391920824 ps
CPU time 1.57 seconds
Started Jul 12 05:54:34 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 194040 kb
Host smart-949a148b-c8b4-42ba-b8c2-a6bfe96377a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103633704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2103633704
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4027385401
Short name T314
Test name
Test status
Simulation time 522279154 ps
CPU time 0.67 seconds
Started Jul 12 05:54:36 PM PDT 24
Finished Jul 12 05:54:39 PM PDT 24
Peak memory 195568 kb
Host smart-b6bd1ab7-18b6-40b4-9441-e9df1328aeb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027385401 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.4027385401
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3570335539
Short name T66
Test name
Test status
Simulation time 284638226 ps
CPU time 0.95 seconds
Started Jul 12 05:54:34 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 193280 kb
Host smart-166a8b69-f7f3-4bda-a00a-d03311b505c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570335539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3570335539
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.94298218
Short name T348
Test name
Test status
Simulation time 339864289 ps
CPU time 0.98 seconds
Started Jul 12 05:54:39 PM PDT 24
Finished Jul 12 05:54:41 PM PDT 24
Peak memory 183832 kb
Host smart-2e061f86-ba91-4953-b8c2-a91c914f6be3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94298218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.94298218
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2146432132
Short name T299
Test name
Test status
Simulation time 384479257 ps
CPU time 0.6 seconds
Started Jul 12 05:54:34 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 183660 kb
Host smart-f6768b26-b1f2-4e55-9ce7-d1a17d739876
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146432132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2146432132
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.259225965
Short name T409
Test name
Test status
Simulation time 279179312 ps
CPU time 0.73 seconds
Started Jul 12 05:54:40 PM PDT 24
Finished Jul 12 05:54:42 PM PDT 24
Peak memory 183816 kb
Host smart-a9b9ad66-1c75-4a27-95e5-d4362ed2c8b6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259225965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.259225965
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1688576018
Short name T344
Test name
Test status
Simulation time 2751482416 ps
CPU time 2.35 seconds
Started Jul 12 05:54:33 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 195236 kb
Host smart-0cd16c16-dbd6-4912-8ce0-229f99e7b5f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688576018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1688576018
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.674810836
Short name T335
Test name
Test status
Simulation time 693515875 ps
CPU time 1.23 seconds
Started Jul 12 05:54:34 PM PDT 24
Finished Jul 12 05:54:38 PM PDT 24
Peak memory 198648 kb
Host smart-0a29cb1b-3f11-42c9-a4a0-c54acb6105f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674810836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.674810836
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3330668341
Short name T36
Test name
Test status
Simulation time 4555623566 ps
CPU time 2.6 seconds
Started Jul 12 05:54:39 PM PDT 24
Finished Jul 12 05:54:43 PM PDT 24
Peak memory 196908 kb
Host smart-17daecee-3e59-4f85-9dd8-8f9837bf5e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330668341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3330668341
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3386750686
Short name T380
Test name
Test status
Simulation time 419358539 ps
CPU time 0.67 seconds
Started Jul 12 05:54:54 PM PDT 24
Finished Jul 12 05:54:57 PM PDT 24
Peak memory 183740 kb
Host smart-a30a5f9f-0c96-4f95-a243-da5bcd3bb8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386750686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3386750686
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3838431180
Short name T397
Test name
Test status
Simulation time 360876857 ps
CPU time 1.13 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:03 PM PDT 24
Peak memory 183736 kb
Host smart-6249c0aa-d31e-455b-b4df-82fca68743f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838431180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3838431180
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2235232100
Short name T366
Test name
Test status
Simulation time 449466922 ps
CPU time 0.7 seconds
Started Jul 12 05:54:59 PM PDT 24
Finished Jul 12 05:55:01 PM PDT 24
Peak memory 192956 kb
Host smart-0534f4d6-e171-44ad-9b7c-f19881f4d4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235232100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2235232100
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.178476602
Short name T336
Test name
Test status
Simulation time 349268279 ps
CPU time 0.63 seconds
Started Jul 12 05:55:02 PM PDT 24
Finished Jul 12 05:55:04 PM PDT 24
Peak memory 183716 kb
Host smart-39c1aab5-6c78-4e90-a855-b80baad9fcb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178476602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.178476602
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.182630328
Short name T383
Test name
Test status
Simulation time 428795114 ps
CPU time 1.19 seconds
Started Jul 12 05:55:00 PM PDT 24
Finished Jul 12 05:55:03 PM PDT 24
Peak memory 183656 kb
Host smart-e689af6d-84de-42b2-b055-801736e8f7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182630328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.182630328
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2302460693
Short name T310
Test name
Test status
Simulation time 483334174 ps
CPU time 0.64 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:03 PM PDT 24
Peak memory 183740 kb
Host smart-6cb28cce-3a4b-4f37-b52e-94b724f4ded0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302460693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2302460693
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.745531183
Short name T301
Test name
Test status
Simulation time 516484197 ps
CPU time 0.63 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:03 PM PDT 24
Peak memory 183764 kb
Host smart-606eb5ca-9d4e-4093-a2db-de1431aaa689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745531183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.745531183
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3999797695
Short name T286
Test name
Test status
Simulation time 319313577 ps
CPU time 0.76 seconds
Started Jul 12 05:55:03 PM PDT 24
Finished Jul 12 05:55:04 PM PDT 24
Peak memory 183728 kb
Host smart-945df3f9-17a9-4fab-9c83-5863a6795998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999797695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3999797695
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.942254171
Short name T373
Test name
Test status
Simulation time 488434574 ps
CPU time 0.76 seconds
Started Jul 12 05:55:00 PM PDT 24
Finished Jul 12 05:55:02 PM PDT 24
Peak memory 183740 kb
Host smart-d73da194-3d7c-4100-9710-6a7f71e7c203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942254171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.942254171
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1115671026
Short name T290
Test name
Test status
Simulation time 473570498 ps
CPU time 1.19 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:03 PM PDT 24
Peak memory 183824 kb
Host smart-4e69149d-e1a0-4890-a11a-39740af3e14d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115671026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1115671026
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.337664436
Short name T58
Test name
Test status
Simulation time 989523721 ps
CPU time 0.84 seconds
Started Jul 12 05:54:40 PM PDT 24
Finished Jul 12 05:54:42 PM PDT 24
Peak memory 194624 kb
Host smart-189bfe18-edc4-4eed-89ac-8155bd44dca5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337664436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.337664436
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3586277407
Short name T387
Test name
Test status
Simulation time 13419485144 ps
CPU time 9.51 seconds
Started Jul 12 05:54:39 PM PDT 24
Finished Jul 12 05:54:49 PM PDT 24
Peak memory 192240 kb
Host smart-00b0da15-30d7-49ac-92fc-0f261b425986
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586277407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3586277407
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3253657115
Short name T56
Test name
Test status
Simulation time 705749846 ps
CPU time 1.52 seconds
Started Jul 12 05:54:41 PM PDT 24
Finished Jul 12 05:54:43 PM PDT 24
Peak memory 192200 kb
Host smart-ef528ebd-6be2-4c5f-be7c-dd38b65b883a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253657115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3253657115
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1550942002
Short name T34
Test name
Test status
Simulation time 402282981 ps
CPU time 0.96 seconds
Started Jul 12 05:54:41 PM PDT 24
Finished Jul 12 05:54:43 PM PDT 24
Peak memory 196336 kb
Host smart-90bc0e38-9c76-4983-b446-ca03b9ba37dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550942002 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1550942002
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2262889243
Short name T60
Test name
Test status
Simulation time 422157247 ps
CPU time 1.1 seconds
Started Jul 12 05:54:39 PM PDT 24
Finished Jul 12 05:54:41 PM PDT 24
Peak memory 193028 kb
Host smart-9bcb4201-227c-4451-b3e0-849282256202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262889243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2262889243
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.427877225
Short name T388
Test name
Test status
Simulation time 290628061 ps
CPU time 0.64 seconds
Started Jul 12 05:54:39 PM PDT 24
Finished Jul 12 05:54:40 PM PDT 24
Peak memory 192964 kb
Host smart-d6a41f07-02e7-43eb-b3f0-7dd4e6ca9e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427877225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.427877225
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.862559123
Short name T362
Test name
Test status
Simulation time 359709263 ps
CPU time 1.01 seconds
Started Jul 12 05:54:42 PM PDT 24
Finished Jul 12 05:54:44 PM PDT 24
Peak memory 183764 kb
Host smart-a648ec59-68e8-4ca8-8c94-023fd5607ce8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862559123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.862559123
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4079547031
Short name T326
Test name
Test status
Simulation time 328771666 ps
CPU time 0.62 seconds
Started Jul 12 05:54:39 PM PDT 24
Finished Jul 12 05:54:41 PM PDT 24
Peak memory 183708 kb
Host smart-20770046-1248-498e-a779-33f16614bf01
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079547031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.4079547031
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.491585166
Short name T77
Test name
Test status
Simulation time 1311690314 ps
CPU time 1.87 seconds
Started Jul 12 05:54:39 PM PDT 24
Finished Jul 12 05:54:42 PM PDT 24
Peak memory 183788 kb
Host smart-5f09c792-a3a9-4ab3-b1b0-882a931822ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491585166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.491585166
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3574242553
Short name T339
Test name
Test status
Simulation time 589073291 ps
CPU time 2.62 seconds
Started Jul 12 05:54:36 PM PDT 24
Finished Jul 12 05:54:40 PM PDT 24
Peak memory 198580 kb
Host smart-7125348e-6198-46bd-94e6-1afd5cec9fde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574242553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3574242553
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.249424269
Short name T374
Test name
Test status
Simulation time 4401121621 ps
CPU time 3.75 seconds
Started Jul 12 05:54:40 PM PDT 24
Finished Jul 12 05:54:45 PM PDT 24
Peak memory 197940 kb
Host smart-a9f618c8-d6fc-45d2-9e6e-94937a4d8ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249424269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.249424269
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2548670178
Short name T307
Test name
Test status
Simulation time 336600658 ps
CPU time 1.02 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:04 PM PDT 24
Peak memory 192956 kb
Host smart-a1b19d7d-5359-498d-8d94-7a4a52a7a8a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548670178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2548670178
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3276475722
Short name T345
Test name
Test status
Simulation time 456534957 ps
CPU time 1.17 seconds
Started Jul 12 05:55:02 PM PDT 24
Finished Jul 12 05:55:04 PM PDT 24
Peak memory 192948 kb
Host smart-1a6a4768-b822-4332-801d-8776863d9b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276475722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3276475722
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.555566425
Short name T303
Test name
Test status
Simulation time 333879393 ps
CPU time 0.81 seconds
Started Jul 12 05:55:03 PM PDT 24
Finished Jul 12 05:55:05 PM PDT 24
Peak memory 192948 kb
Host smart-c424487b-5af5-446d-ae0f-b35b2e68f336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555566425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.555566425
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.133425543
Short name T304
Test name
Test status
Simulation time 376247364 ps
CPU time 1.1 seconds
Started Jul 12 05:55:05 PM PDT 24
Finished Jul 12 05:55:07 PM PDT 24
Peak memory 183748 kb
Host smart-f906b9cb-d3be-4821-88ab-cb5c055e1f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133425543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.133425543
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2751597162
Short name T292
Test name
Test status
Simulation time 292562631 ps
CPU time 1.06 seconds
Started Jul 12 05:55:00 PM PDT 24
Finished Jul 12 05:55:02 PM PDT 24
Peak memory 183716 kb
Host smart-7015430a-060f-4948-95e0-35b0e659acb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751597162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2751597162
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2203062115
Short name T393
Test name
Test status
Simulation time 415670175 ps
CPU time 1.07 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:03 PM PDT 24
Peak memory 192988 kb
Host smart-04c2505a-7920-465a-97d9-ec9d2a7ddd09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203062115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2203062115
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.878352570
Short name T337
Test name
Test status
Simulation time 449378338 ps
CPU time 0.81 seconds
Started Jul 12 05:55:01 PM PDT 24
Finished Jul 12 05:55:03 PM PDT 24
Peak memory 183744 kb
Host smart-8e794e62-e45b-4361-be4f-27e5ef8c0e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878352570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.878352570
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.238336191
Short name T396
Test name
Test status
Simulation time 418208548 ps
CPU time 0.64 seconds
Started Jul 12 05:55:00 PM PDT 24
Finished Jul 12 05:55:01 PM PDT 24
Peak memory 192976 kb
Host smart-74fdfefd-1b8b-40c6-8d70-0103cc333307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238336191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.238336191
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1549232832
Short name T317
Test name
Test status
Simulation time 596203319 ps
CPU time 0.67 seconds
Started Jul 12 05:55:03 PM PDT 24
Finished Jul 12 05:55:04 PM PDT 24
Peak memory 183728 kb
Host smart-5b6d6537-b8eb-4bd0-a123-54d2df5e4119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549232832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1549232832
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2690019073
Short name T418
Test name
Test status
Simulation time 429036856 ps
CPU time 0.72 seconds
Started Jul 12 05:55:00 PM PDT 24
Finished Jul 12 05:55:02 PM PDT 24
Peak memory 183744 kb
Host smart-f3914e62-ae56-4a22-8698-7ef1e4094819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690019073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2690019073
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2676713522
Short name T321
Test name
Test status
Simulation time 539532210 ps
CPU time 1.04 seconds
Started Jul 12 05:54:37 PM PDT 24
Finished Jul 12 05:54:40 PM PDT 24
Peak memory 196796 kb
Host smart-6e01fbd8-c152-44b6-862c-342a25cb37c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676713522 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2676713522
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2298592387
Short name T417
Test name
Test status
Simulation time 494603140 ps
CPU time 1.21 seconds
Started Jul 12 05:54:40 PM PDT 24
Finished Jul 12 05:54:42 PM PDT 24
Peak memory 192848 kb
Host smart-89bdf86e-fa4c-4b59-9179-f407fc352fef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298592387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2298592387
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2103111403
Short name T295
Test name
Test status
Simulation time 325352319 ps
CPU time 0.74 seconds
Started Jul 12 05:54:37 PM PDT 24
Finished Jul 12 05:54:39 PM PDT 24
Peak memory 183716 kb
Host smart-56ee0179-2a79-4674-9369-db42bf9bdcff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103111403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2103111403
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3569945080
Short name T377
Test name
Test status
Simulation time 1801111101 ps
CPU time 0.97 seconds
Started Jul 12 05:54:40 PM PDT 24
Finished Jul 12 05:54:42 PM PDT 24
Peak memory 183800 kb
Host smart-c022a042-9a67-406d-b9c4-c0b33a71c3fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569945080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3569945080
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3087610516
Short name T329
Test name
Test status
Simulation time 753489199 ps
CPU time 2.02 seconds
Started Jul 12 05:54:39 PM PDT 24
Finished Jul 12 05:54:42 PM PDT 24
Peak memory 198632 kb
Host smart-ec3b8948-d34a-4942-80c7-02beda5c4336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087610516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3087610516
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2780982065
Short name T365
Test name
Test status
Simulation time 7612867588 ps
CPU time 4.47 seconds
Started Jul 12 05:54:40 PM PDT 24
Finished Jul 12 05:54:46 PM PDT 24
Peak memory 198360 kb
Host smart-0646d73c-1c28-4c72-99e2-54ba7de6c304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780982065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2780982065
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3449355265
Short name T293
Test name
Test status
Simulation time 648133966 ps
CPU time 1.04 seconds
Started Jul 12 05:54:46 PM PDT 24
Finished Jul 12 05:54:50 PM PDT 24
Peak memory 198460 kb
Host smart-1646ab89-c469-44b3-9f8b-b8b825f88e66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449355265 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3449355265
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1429907190
Short name T63
Test name
Test status
Simulation time 488811334 ps
CPU time 0.92 seconds
Started Jul 12 05:54:43 PM PDT 24
Finished Jul 12 05:54:44 PM PDT 24
Peak memory 193008 kb
Host smart-362692e6-34b5-4b8a-a484-e0156a4b13be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429907190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1429907190
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2144880768
Short name T323
Test name
Test status
Simulation time 506153184 ps
CPU time 1.24 seconds
Started Jul 12 05:54:39 PM PDT 24
Finished Jul 12 05:54:42 PM PDT 24
Peak memory 192784 kb
Host smart-e6d2635e-c9c7-4539-a23a-928809f4926b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144880768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2144880768
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2005621376
Short name T413
Test name
Test status
Simulation time 2248190193 ps
CPU time 3.05 seconds
Started Jul 12 05:54:45 PM PDT 24
Finished Jul 12 05:54:50 PM PDT 24
Peak memory 183948 kb
Host smart-2a35430e-348f-4e1c-a5ca-073108652453
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005621376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2005621376
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3786541294
Short name T410
Test name
Test status
Simulation time 536484414 ps
CPU time 1.81 seconds
Started Jul 12 05:54:38 PM PDT 24
Finished Jul 12 05:54:41 PM PDT 24
Peak memory 198636 kb
Host smart-5c85c56b-1fb1-474a-8e80-b7876e400b59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786541294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3786541294
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2494903372
Short name T320
Test name
Test status
Simulation time 8003042456 ps
CPU time 6.85 seconds
Started Jul 12 05:54:40 PM PDT 24
Finished Jul 12 05:54:48 PM PDT 24
Peak memory 198396 kb
Host smart-921f6ba3-2110-4b56-9812-a09103d707e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494903372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2494903372
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2187750244
Short name T402
Test name
Test status
Simulation time 451731149 ps
CPU time 0.91 seconds
Started Jul 12 05:54:45 PM PDT 24
Finished Jul 12 05:54:47 PM PDT 24
Peak memory 195940 kb
Host smart-42ea9f38-3661-4c78-a3f4-6b544b3c3709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187750244 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2187750244
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.619146082
Short name T361
Test name
Test status
Simulation time 346965501 ps
CPU time 0.81 seconds
Started Jul 12 05:54:44 PM PDT 24
Finished Jul 12 05:54:46 PM PDT 24
Peak memory 192052 kb
Host smart-ecd2345b-7ef8-49c8-9ef7-ceb51674670d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619146082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.619146082
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1810328292
Short name T349
Test name
Test status
Simulation time 312768526 ps
CPU time 0.6 seconds
Started Jul 12 05:54:46 PM PDT 24
Finished Jul 12 05:54:49 PM PDT 24
Peak memory 183436 kb
Host smart-bea6893b-b8e0-492b-a450-a7ad3c59eaca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810328292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1810328292
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2904122496
Short name T78
Test name
Test status
Simulation time 2339318603 ps
CPU time 1.45 seconds
Started Jul 12 05:54:44 PM PDT 24
Finished Jul 12 05:54:47 PM PDT 24
Peak memory 194148 kb
Host smart-cc52f603-facb-4e30-ab95-c8bc4264934c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904122496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2904122496
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2389226467
Short name T297
Test name
Test status
Simulation time 757391129 ps
CPU time 2.51 seconds
Started Jul 12 05:54:43 PM PDT 24
Finished Jul 12 05:54:46 PM PDT 24
Peak memory 198636 kb
Host smart-6d2a2d6f-8956-4e0c-a2a8-e31920005a85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389226467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2389226467
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.202806691
Short name T340
Test name
Test status
Simulation time 8742540176 ps
CPU time 2.92 seconds
Started Jul 12 05:54:44 PM PDT 24
Finished Jul 12 05:54:48 PM PDT 24
Peak memory 198360 kb
Host smart-a7f89018-74c9-404a-9194-6a235cc02e92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202806691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.202806691
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3510852327
Short name T302
Test name
Test status
Simulation time 500619433 ps
CPU time 1.16 seconds
Started Jul 12 05:54:48 PM PDT 24
Finished Jul 12 05:54:52 PM PDT 24
Peak memory 197264 kb
Host smart-d24573af-5067-4b2d-82e2-a66637c9e4e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510852327 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3510852327
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3994943548
Short name T37
Test name
Test status
Simulation time 516562360 ps
CPU time 0.77 seconds
Started Jul 12 05:54:48 PM PDT 24
Finished Jul 12 05:54:52 PM PDT 24
Peak memory 192884 kb
Host smart-22cae2d0-b235-4a74-8cd8-c0ab25c0a61d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994943548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3994943548
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2272341636
Short name T381
Test name
Test status
Simulation time 443747231 ps
CPU time 0.58 seconds
Started Jul 12 05:54:44 PM PDT 24
Finished Jul 12 05:54:46 PM PDT 24
Peak memory 183744 kb
Host smart-a2c504ca-c1f3-4abb-88e5-fd126c8ec10f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272341636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2272341636
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1176870704
Short name T74
Test name
Test status
Simulation time 2198281741 ps
CPU time 6.51 seconds
Started Jul 12 05:54:43 PM PDT 24
Finished Jul 12 05:54:50 PM PDT 24
Peak memory 192036 kb
Host smart-059fc682-ef42-4608-af75-feb6645fa39c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176870704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1176870704
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.103206544
Short name T291
Test name
Test status
Simulation time 616765857 ps
CPU time 1.64 seconds
Started Jul 12 05:54:45 PM PDT 24
Finished Jul 12 05:54:49 PM PDT 24
Peak memory 198660 kb
Host smart-d08cccee-16c7-4c6e-9182-abb8acaa34be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103206544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.103206544
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.822737519
Short name T194
Test name
Test status
Simulation time 8715418041 ps
CPU time 4.32 seconds
Started Jul 12 05:54:44 PM PDT 24
Finished Jul 12 05:54:50 PM PDT 24
Peak memory 198268 kb
Host smart-f8aa3f80-c30d-405b-80cf-8b0549c1a382
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822737519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.822737519
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3738071907
Short name T199
Test name
Test status
Simulation time 428679977 ps
CPU time 0.8 seconds
Started Jul 12 05:54:46 PM PDT 24
Finished Jul 12 05:54:49 PM PDT 24
Peak memory 196076 kb
Host smart-82e22b38-77c0-4db8-b97d-99fef2b96210
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738071907 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3738071907
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1827308575
Short name T67
Test name
Test status
Simulation time 368306680 ps
CPU time 0.69 seconds
Started Jul 12 05:54:42 PM PDT 24
Finished Jul 12 05:54:44 PM PDT 24
Peak memory 193008 kb
Host smart-d3a9f918-323b-464c-8db5-96b72aed6a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827308575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1827308575
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3091067277
Short name T306
Test name
Test status
Simulation time 419955001 ps
CPU time 1.18 seconds
Started Jul 12 05:54:48 PM PDT 24
Finished Jul 12 05:54:52 PM PDT 24
Peak memory 192744 kb
Host smart-6d43d8ec-ef94-4515-ad50-fe56c06068d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091067277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3091067277
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3045473108
Short name T353
Test name
Test status
Simulation time 1212608647 ps
CPU time 2.23 seconds
Started Jul 12 05:54:46 PM PDT 24
Finished Jul 12 05:54:50 PM PDT 24
Peak memory 193376 kb
Host smart-959aed84-2c90-42a1-8513-914c464acaf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045473108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3045473108
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3161415917
Short name T370
Test name
Test status
Simulation time 659340971 ps
CPU time 1.82 seconds
Started Jul 12 05:54:46 PM PDT 24
Finished Jul 12 05:54:51 PM PDT 24
Peak memory 198640 kb
Host smart-3f9fcbe7-ce34-469b-b4e8-ae64544822af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161415917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3161415917
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3702043213
Short name T385
Test name
Test status
Simulation time 4121194424 ps
CPU time 5.8 seconds
Started Jul 12 05:54:43 PM PDT 24
Finished Jul 12 05:54:50 PM PDT 24
Peak memory 196440 kb
Host smart-57f9be04-ef60-4084-b23f-ae97c4a798a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702043213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3702043213
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3774536790
Short name T180
Test name
Test status
Simulation time 405861474 ps
CPU time 0.94 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:53:50 PM PDT 24
Peak memory 196728 kb
Host smart-e9676822-848c-4e49-890f-3cd3faf40792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774536790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3774536790
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1454991578
Short name T243
Test name
Test status
Simulation time 16900951220 ps
CPU time 5.76 seconds
Started Jul 12 05:53:37 PM PDT 24
Finished Jul 12 05:53:44 PM PDT 24
Peak memory 191916 kb
Host smart-11785e8f-c40c-4201-be2f-1262915106d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454991578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1454991578
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3259617116
Short name T274
Test name
Test status
Simulation time 532067713 ps
CPU time 0.77 seconds
Started Jul 12 05:53:39 PM PDT 24
Finished Jul 12 05:53:41 PM PDT 24
Peak memory 191860 kb
Host smart-c37d43cb-a827-4479-9835-872507a92697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259617116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3259617116
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1337394403
Short name T90
Test name
Test status
Simulation time 16786577741 ps
CPU time 34.38 seconds
Started Jul 12 05:53:37 PM PDT 24
Finished Jul 12 05:54:13 PM PDT 24
Peak memory 198568 kb
Host smart-4e3afecd-4641-454d-8e33-07e91858be35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337394403 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1337394403
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2113186627
Short name T278
Test name
Test status
Simulation time 31961960664 ps
CPU time 13.43 seconds
Started Jul 12 05:53:41 PM PDT 24
Finished Jul 12 05:53:55 PM PDT 24
Peak memory 192036 kb
Host smart-0f9c77b2-53f8-4514-ab0d-b8fbe9fbaea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113186627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2113186627
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.221656046
Short name T14
Test name
Test status
Simulation time 7947688645 ps
CPU time 10.83 seconds
Started Jul 12 05:53:40 PM PDT 24
Finished Jul 12 05:53:52 PM PDT 24
Peak memory 215704 kb
Host smart-0f946f33-c773-4a9f-9be2-937d8b94c671
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221656046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.221656046
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2278804130
Short name T4
Test name
Test status
Simulation time 399204630 ps
CPU time 0.89 seconds
Started Jul 12 05:53:38 PM PDT 24
Finished Jul 12 05:53:41 PM PDT 24
Peak memory 196656 kb
Host smart-05d9e071-e7ce-4255-9297-378b200e116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278804130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2278804130
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1430707064
Short name T235
Test name
Test status
Simulation time 45978881596 ps
CPU time 7.3 seconds
Started Jul 12 05:53:47 PM PDT 24
Finished Jul 12 05:53:57 PM PDT 24
Peak memory 196924 kb
Host smart-f1dccd00-b237-4196-83dd-d599bc2510b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430707064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1430707064
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1574939816
Short name T220
Test name
Test status
Simulation time 472601476 ps
CPU time 1.3 seconds
Started Jul 12 05:53:48 PM PDT 24
Finished Jul 12 05:53:53 PM PDT 24
Peak memory 191796 kb
Host smart-9750700b-ca39-4f6a-824c-b2befa8621e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574939816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1574939816
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2024635748
Short name T257
Test name
Test status
Simulation time 12019991846 ps
CPU time 14.19 seconds
Started Jul 12 05:53:53 PM PDT 24
Finished Jul 12 05:54:12 PM PDT 24
Peak memory 197056 kb
Host smart-d3c53cbc-5ed7-441b-8d3a-4352a38245b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024635748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2024635748
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.995743620
Short name T205
Test name
Test status
Simulation time 396190691 ps
CPU time 0.99 seconds
Started Jul 12 05:53:53 PM PDT 24
Finished Jul 12 05:53:58 PM PDT 24
Peak memory 196820 kb
Host smart-31fbc675-6d3e-450f-bf23-3dac022cb87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995743620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.995743620
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3345487996
Short name T166
Test name
Test status
Simulation time 445609043 ps
CPU time 0.73 seconds
Started Jul 12 05:53:50 PM PDT 24
Finished Jul 12 05:53:54 PM PDT 24
Peak memory 196660 kb
Host smart-a10cb2cf-a008-4b15-b631-6277573c81ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345487996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3345487996
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.320002002
Short name T244
Test name
Test status
Simulation time 53126840617 ps
CPU time 20.21 seconds
Started Jul 12 05:53:53 PM PDT 24
Finished Jul 12 05:54:18 PM PDT 24
Peak memory 192036 kb
Host smart-5cb27236-a1f5-46e1-af0b-a3c976056d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320002002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.320002002
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3941997465
Short name T251
Test name
Test status
Simulation time 406516327 ps
CPU time 0.92 seconds
Started Jul 12 05:53:51 PM PDT 24
Finished Jul 12 05:53:56 PM PDT 24
Peak memory 191840 kb
Host smart-c7fff1ff-4f3d-4c70-8736-c1f080e68790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941997465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3941997465
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3424685171
Short name T217
Test name
Test status
Simulation time 59537249089 ps
CPU time 92.88 seconds
Started Jul 12 05:53:51 PM PDT 24
Finished Jul 12 05:55:27 PM PDT 24
Peak memory 191940 kb
Host smart-6cedeb2a-ce72-44aa-a978-8a7e665c7635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424685171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3424685171
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.741123178
Short name T237
Test name
Test status
Simulation time 488709067 ps
CPU time 1.29 seconds
Started Jul 12 05:53:54 PM PDT 24
Finished Jul 12 05:54:01 PM PDT 24
Peak memory 191808 kb
Host smart-c9962fd1-67b2-4d13-9198-52ef753795f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741123178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.741123178
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1643806446
Short name T279
Test name
Test status
Simulation time 8320071729 ps
CPU time 4.07 seconds
Started Jul 12 05:53:59 PM PDT 24
Finished Jul 12 05:54:09 PM PDT 24
Peak memory 196920 kb
Host smart-e0b1574a-aeda-434b-963a-3e3b697d85f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643806446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1643806446
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2874262570
Short name T48
Test name
Test status
Simulation time 487856786 ps
CPU time 0.86 seconds
Started Jul 12 05:53:52 PM PDT 24
Finished Jul 12 05:53:57 PM PDT 24
Peak memory 196616 kb
Host smart-df94046a-6b8e-450d-8944-16ebadfbf0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874262570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2874262570
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2087716555
Short name T283
Test name
Test status
Simulation time 13124163247 ps
CPU time 17.76 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:54:21 PM PDT 24
Peak memory 191928 kb
Host smart-48e694d6-7afc-47b5-98c3-85566c794e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087716555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2087716555
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1214182743
Short name T27
Test name
Test status
Simulation time 361606105 ps
CPU time 1.07 seconds
Started Jul 12 05:53:51 PM PDT 24
Finished Jul 12 05:53:57 PM PDT 24
Peak memory 191860 kb
Host smart-160c7b25-9e3d-4956-89c8-968ba76d1455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214182743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1214182743
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1870934923
Short name T208
Test name
Test status
Simulation time 44898580353 ps
CPU time 29.23 seconds
Started Jul 12 05:54:03 PM PDT 24
Finished Jul 12 05:54:37 PM PDT 24
Peak memory 196952 kb
Host smart-c73ca4ef-91e7-46cb-86b8-6e3c8d6f61dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870934923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1870934923
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2697091849
Short name T225
Test name
Test status
Simulation time 427836869 ps
CPU time 0.79 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:09 PM PDT 24
Peak memory 191648 kb
Host smart-e9df0f3e-2b2d-45b3-a088-2e05743e425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697091849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2697091849
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.291622357
Short name T93
Test name
Test status
Simulation time 18666913885 ps
CPU time 130.32 seconds
Started Jul 12 05:53:56 PM PDT 24
Finished Jul 12 05:56:11 PM PDT 24
Peak memory 214024 kb
Host smart-6c8a10a5-8760-4e72-85d9-c58011afd08f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291622357 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.291622357
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3444254141
Short name T218
Test name
Test status
Simulation time 16530341738 ps
CPU time 5.75 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:13 PM PDT 24
Peak memory 191748 kb
Host smart-1a5697d9-591c-432c-a6bf-bd896eb454dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444254141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3444254141
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1040465796
Short name T241
Test name
Test status
Simulation time 522708645 ps
CPU time 0.83 seconds
Started Jul 12 05:53:52 PM PDT 24
Finished Jul 12 05:53:57 PM PDT 24
Peak memory 196712 kb
Host smart-7e2e8c74-7a47-4625-ae59-6ff488d68b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040465796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1040465796
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1204211949
Short name T210
Test name
Test status
Simulation time 3039883990 ps
CPU time 2.63 seconds
Started Jul 12 05:53:53 PM PDT 24
Finished Jul 12 05:54:01 PM PDT 24
Peak memory 196712 kb
Host smart-f5aacf09-a0c7-4664-ad61-241c5470a96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204211949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1204211949
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.4232016202
Short name T54
Test name
Test status
Simulation time 549563123 ps
CPU time 1.31 seconds
Started Jul 12 05:53:54 PM PDT 24
Finished Jul 12 05:54:00 PM PDT 24
Peak memory 191888 kb
Host smart-e372c779-23e3-4d56-8d69-a9045dfd840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232016202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4232016202
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.4068239518
Short name T45
Test name
Test status
Simulation time 39417050324 ps
CPU time 51.03 seconds
Started Jul 12 05:53:56 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 191924 kb
Host smart-527928f3-f42a-44f4-b36c-70a07caccbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068239518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4068239518
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.156419481
Short name T254
Test name
Test status
Simulation time 552610831 ps
CPU time 0.78 seconds
Started Jul 12 05:53:59 PM PDT 24
Finished Jul 12 05:54:05 PM PDT 24
Peak memory 191856 kb
Host smart-0fcbe2b1-3b3a-4df0-bb87-53219f845b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156419481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.156419481
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3877691242
Short name T219
Test name
Test status
Simulation time 41788987330 ps
CPU time 44.37 seconds
Started Jul 12 05:53:47 PM PDT 24
Finished Jul 12 05:54:35 PM PDT 24
Peak memory 191932 kb
Host smart-005287b3-f8ce-46cc-9a84-2f75b67e2cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877691242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3877691242
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3185844110
Short name T16
Test name
Test status
Simulation time 7808121970 ps
CPU time 10.92 seconds
Started Jul 12 05:53:38 PM PDT 24
Finished Jul 12 05:53:50 PM PDT 24
Peak memory 215732 kb
Host smart-9431e3f5-a2ad-4d10-a093-6db1c329614c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185844110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3185844110
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1588011048
Short name T79
Test name
Test status
Simulation time 561470987 ps
CPU time 0.81 seconds
Started Jul 12 05:53:37 PM PDT 24
Finished Jul 12 05:53:40 PM PDT 24
Peak memory 196664 kb
Host smart-12e10b47-50b5-401d-9c66-b397570a2acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588011048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1588011048
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3692822743
Short name T2
Test name
Test status
Simulation time 14117613314 ps
CPU time 20.51 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:54:24 PM PDT 24
Peak memory 196936 kb
Host smart-f7dd29f8-3478-49b1-b612-1b9c6593c8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692822743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3692822743
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3842817803
Short name T209
Test name
Test status
Simulation time 459556272 ps
CPU time 0.63 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:54:04 PM PDT 24
Peak memory 191868 kb
Host smart-9d46147f-cbf4-4fe5-8ce6-e9447952fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842817803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3842817803
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1040580302
Short name T269
Test name
Test status
Simulation time 60551853303 ps
CPU time 77.2 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:55:21 PM PDT 24
Peak memory 191928 kb
Host smart-c9f82c3d-e50f-435d-b1e9-dc98d8c95bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040580302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1040580302
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2496431374
Short name T285
Test name
Test status
Simulation time 587155637 ps
CPU time 1.53 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:09 PM PDT 24
Peak memory 191844 kb
Host smart-96c75e98-cdb9-44d0-8330-7b494330caf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496431374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2496431374
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1523607817
Short name T207
Test name
Test status
Simulation time 54537095575 ps
CPU time 18.92 seconds
Started Jul 12 05:53:55 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 191900 kb
Host smart-808d2d4b-1a36-4e03-b179-a51072be745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523607817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1523607817
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2669051794
Short name T240
Test name
Test status
Simulation time 471448442 ps
CPU time 0.76 seconds
Started Jul 12 05:53:57 PM PDT 24
Finished Jul 12 05:54:04 PM PDT 24
Peak memory 191820 kb
Host smart-67bac948-c899-4e51-9dfe-0d082eeb0b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669051794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2669051794
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2831103050
Short name T203
Test name
Test status
Simulation time 46670656333 ps
CPU time 9.07 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:54:15 PM PDT 24
Peak memory 192116 kb
Host smart-d6248019-8636-4d45-9951-a988e61f56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831103050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2831103050
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1905733430
Short name T250
Test name
Test status
Simulation time 589158716 ps
CPU time 1.35 seconds
Started Jul 12 05:53:54 PM PDT 24
Finished Jul 12 05:54:01 PM PDT 24
Peak memory 191852 kb
Host smart-e989e4a8-3f38-4865-a6a2-7027824346ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905733430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1905733430
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.790335844
Short name T224
Test name
Test status
Simulation time 15155997435 ps
CPU time 3.02 seconds
Started Jul 12 05:53:55 PM PDT 24
Finished Jul 12 05:54:03 PM PDT 24
Peak memory 191908 kb
Host smart-974de74e-5963-4224-b174-2db0420b44f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790335844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.790335844
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3209863647
Short name T284
Test name
Test status
Simulation time 531502651 ps
CPU time 1.26 seconds
Started Jul 12 05:53:59 PM PDT 24
Finished Jul 12 05:54:06 PM PDT 24
Peak memory 191860 kb
Host smart-69e8e7be-79d5-40ed-b9c6-b8e6f94ba830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209863647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3209863647
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.22022699
Short name T183
Test name
Test status
Simulation time 515624341 ps
CPU time 0.83 seconds
Started Jul 12 05:53:57 PM PDT 24
Finished Jul 12 05:54:04 PM PDT 24
Peak memory 196644 kb
Host smart-62eabb25-a3d8-41d0-b880-0de167066f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22022699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.22022699
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1342173227
Short name T276
Test name
Test status
Simulation time 6869825907 ps
CPU time 9.27 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:54:13 PM PDT 24
Peak memory 191916 kb
Host smart-1afcc65d-8b43-4162-ab1a-adf6e75b69d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342173227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1342173227
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4229693011
Short name T272
Test name
Test status
Simulation time 492706178 ps
CPU time 0.74 seconds
Started Jul 12 05:53:59 PM PDT 24
Finished Jul 12 05:54:06 PM PDT 24
Peak memory 191864 kb
Host smart-074c2bd6-26d9-4423-8730-4fe62910b6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229693011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4229693011
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_jump.405694778
Short name T3
Test name
Test status
Simulation time 480230920 ps
CPU time 0.78 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:08 PM PDT 24
Peak memory 196684 kb
Host smart-320c76c1-8de6-4c00-a14d-4e022cdf9610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405694778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.405694778
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.4014753915
Short name T270
Test name
Test status
Simulation time 27920109506 ps
CPU time 9.64 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:17 PM PDT 24
Peak memory 196952 kb
Host smart-4b70cc51-bfb8-42d2-b9eb-9e28949aedef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014753915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.4014753915
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1809070442
Short name T211
Test name
Test status
Simulation time 542777223 ps
CPU time 1.28 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:54:07 PM PDT 24
Peak memory 191868 kb
Host smart-81e90949-e141-4d1f-8e69-f7a464ce3c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809070442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1809070442
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.673429231
Short name T264
Test name
Test status
Simulation time 25782063578 ps
CPU time 19.16 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:27 PM PDT 24
Peak memory 191924 kb
Host smart-9ff5a321-92e4-4a70-9775-19a91262bc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673429231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.673429231
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3871178904
Short name T236
Test name
Test status
Simulation time 582059691 ps
CPU time 0.77 seconds
Started Jul 12 05:54:00 PM PDT 24
Finished Jul 12 05:54:07 PM PDT 24
Peak memory 191864 kb
Host smart-d4acce0e-b731-4990-bb1a-9d2a7df5a16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871178904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3871178904
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1372172208
Short name T252
Test name
Test status
Simulation time 17044917425 ps
CPU time 3.14 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:54:10 PM PDT 24
Peak memory 191928 kb
Host smart-c2e2eef9-4555-426e-8056-f2d58b62e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372172208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1372172208
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3347206235
Short name T263
Test name
Test status
Simulation time 442381670 ps
CPU time 0.97 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:54:07 PM PDT 24
Peak memory 196640 kb
Host smart-b3ba9f92-f9c1-4d7e-9110-b17014bd175b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347206235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3347206235
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.4004953289
Short name T223
Test name
Test status
Simulation time 18616531283 ps
CPU time 14.4 seconds
Started Jul 12 05:53:58 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 191844 kb
Host smart-e8ffa361-65cf-4303-a4ec-e590b4755736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004953289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.4004953289
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1982093226
Short name T246
Test name
Test status
Simulation time 453381590 ps
CPU time 1.14 seconds
Started Jul 12 05:54:02 PM PDT 24
Finished Jul 12 05:54:09 PM PDT 24
Peak memory 191860 kb
Host smart-a5b73a5b-f673-4337-850b-f754dadf4380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982093226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1982093226
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1806834404
Short name T267
Test name
Test status
Simulation time 20215109926 ps
CPU time 30.5 seconds
Started Jul 12 05:53:49 PM PDT 24
Finished Jul 12 05:54:23 PM PDT 24
Peak memory 196932 kb
Host smart-55153107-bd33-4463-a790-cedbd876f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806834404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1806834404
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.708613629
Short name T18
Test name
Test status
Simulation time 8294073567 ps
CPU time 6.51 seconds
Started Jul 12 05:53:38 PM PDT 24
Finished Jul 12 05:53:46 PM PDT 24
Peak memory 215700 kb
Host smart-51870462-5b32-454b-a984-e05c5252045e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708613629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.708613629
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.449493414
Short name T239
Test name
Test status
Simulation time 541425302 ps
CPU time 0.75 seconds
Started Jul 12 05:53:39 PM PDT 24
Finished Jul 12 05:53:41 PM PDT 24
Peak memory 196612 kb
Host smart-34388ac4-c540-43b9-b868-7915600b21ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449493414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.449493414
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1701718908
Short name T184
Test name
Test status
Simulation time 2802286657 ps
CPU time 2.85 seconds
Started Jul 12 05:53:45 PM PDT 24
Finished Jul 12 05:53:49 PM PDT 24
Peak memory 198260 kb
Host smart-2b4a1a1c-07c9-44af-a50d-2c12cb1b6972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701718908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1701718908
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3226731139
Short name T242
Test name
Test status
Simulation time 44311314362 ps
CPU time 248.51 seconds
Started Jul 12 05:53:49 PM PDT 24
Finished Jul 12 05:58:01 PM PDT 24
Peak memory 206772 kb
Host smart-0d24a7d3-61fd-46f1-9897-f1f0b0f9ca82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226731139 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3226731139
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2729259019
Short name T228
Test name
Test status
Simulation time 36705784578 ps
CPU time 14.3 seconds
Started Jul 12 05:53:59 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 191884 kb
Host smart-38ebc0b4-0802-466c-88e6-bd1b3b4afaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729259019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2729259019
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2922957575
Short name T26
Test name
Test status
Simulation time 526398154 ps
CPU time 0.67 seconds
Started Jul 12 05:54:01 PM PDT 24
Finished Jul 12 05:54:07 PM PDT 24
Peak memory 191876 kb
Host smart-6494ce00-6233-44ef-a47c-3ab9d6c3523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922957575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2922957575
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2513660732
Short name T232
Test name
Test status
Simulation time 16410369839 ps
CPU time 12.53 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:54:31 PM PDT 24
Peak memory 191924 kb
Host smart-d127617d-1b42-41fd-a95b-e72203b7f6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513660732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2513660732
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4159234560
Short name T222
Test name
Test status
Simulation time 486411045 ps
CPU time 0.96 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 191868 kb
Host smart-69effd27-291c-46f7-a12a-01ac74bf5db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159234560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4159234560
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2907868538
Short name T233
Test name
Test status
Simulation time 16873812900 ps
CPU time 6.18 seconds
Started Jul 12 05:54:18 PM PDT 24
Finished Jul 12 05:54:27 PM PDT 24
Peak memory 196920 kb
Host smart-c0e5b41a-106c-47a0-8d1c-9b1b406967c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907868538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2907868538
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2846636587
Short name T206
Test name
Test status
Simulation time 506682543 ps
CPU time 1.44 seconds
Started Jul 12 05:54:18 PM PDT 24
Finished Jul 12 05:54:22 PM PDT 24
Peak memory 191840 kb
Host smart-cdee9389-7a61-431f-9689-7a7d6c7ddc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846636587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2846636587
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1111357654
Short name T214
Test name
Test status
Simulation time 13832711134 ps
CPU time 11.05 seconds
Started Jul 12 05:54:19 PM PDT 24
Finished Jul 12 05:54:32 PM PDT 24
Peak memory 191880 kb
Host smart-0eb8b31d-6841-4ed6-b443-c37de879a90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111357654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1111357654
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3569156228
Short name T234
Test name
Test status
Simulation time 450552862 ps
CPU time 0.76 seconds
Started Jul 12 05:54:13 PM PDT 24
Finished Jul 12 05:54:15 PM PDT 24
Peak memory 191852 kb
Host smart-d6535532-fe70-4477-9793-d4a5d70d70ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569156228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3569156228
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2206936785
Short name T229
Test name
Test status
Simulation time 55003361717 ps
CPU time 74.2 seconds
Started Jul 12 05:54:09 PM PDT 24
Finished Jul 12 05:55:24 PM PDT 24
Peak memory 191900 kb
Host smart-e448e2c8-3857-4a98-872a-002991ab882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206936785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2206936785
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2959145448
Short name T212
Test name
Test status
Simulation time 463304755 ps
CPU time 1.23 seconds
Started Jul 12 05:54:19 PM PDT 24
Finished Jul 12 05:54:23 PM PDT 24
Peak memory 191872 kb
Host smart-53570214-c834-49b3-b4cf-8434ca231b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959145448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2959145448
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3063673392
Short name T261
Test name
Test status
Simulation time 6039503150 ps
CPU time 8.65 seconds
Started Jul 12 05:54:14 PM PDT 24
Finished Jul 12 05:54:25 PM PDT 24
Peak memory 196912 kb
Host smart-5beebc2b-68b0-492d-b882-c0cdac3267f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063673392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3063673392
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3417665346
Short name T47
Test name
Test status
Simulation time 498818336 ps
CPU time 1.31 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:54:18 PM PDT 24
Peak memory 191828 kb
Host smart-b8a3962f-a55d-48f9-a3d4-9a124726631e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417665346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3417665346
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2372286646
Short name T247
Test name
Test status
Simulation time 2302443166 ps
CPU time 1.45 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 196572 kb
Host smart-7ccb845c-b770-410c-ac50-8b62fd00b766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372286646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2372286646
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1100248120
Short name T268
Test name
Test status
Simulation time 471250065 ps
CPU time 0.93 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 196680 kb
Host smart-8a2b3002-6395-467f-bb96-847c898082af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100248120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1100248120
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1601451850
Short name T238
Test name
Test status
Simulation time 17255555480 ps
CPU time 13.11 seconds
Started Jul 12 05:54:08 PM PDT 24
Finished Jul 12 05:54:22 PM PDT 24
Peak memory 191900 kb
Host smart-1aeffaf3-148b-425e-8003-d281ecbbc422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601451850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1601451850
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2058187643
Short name T277
Test name
Test status
Simulation time 611420572 ps
CPU time 1.39 seconds
Started Jul 12 05:54:13 PM PDT 24
Finished Jul 12 05:54:15 PM PDT 24
Peak memory 196592 kb
Host smart-902a8d5c-2078-483f-8517-a18731b564fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058187643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2058187643
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1112603591
Short name T221
Test name
Test status
Simulation time 33690244898 ps
CPU time 12.43 seconds
Started Jul 12 05:54:10 PM PDT 24
Finished Jul 12 05:54:23 PM PDT 24
Peak memory 191812 kb
Host smart-e084f92c-9b4c-4b82-a418-ebbbb918dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112603591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1112603591
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4154347089
Short name T260
Test name
Test status
Simulation time 370772941 ps
CPU time 1.12 seconds
Started Jul 12 05:54:18 PM PDT 24
Finished Jul 12 05:54:21 PM PDT 24
Peak memory 191844 kb
Host smart-0c58a721-d1b9-45ca-abda-1ece8e30ff65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154347089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4154347089
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3784381556
Short name T256
Test name
Test status
Simulation time 26196575285 ps
CPU time 32.54 seconds
Started Jul 12 05:54:14 PM PDT 24
Finished Jul 12 05:54:49 PM PDT 24
Peak memory 191920 kb
Host smart-609d0f3b-7a90-4ce0-927c-e4ad2eaf33a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784381556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3784381556
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1924300895
Short name T258
Test name
Test status
Simulation time 438333868 ps
CPU time 0.88 seconds
Started Jul 12 05:54:17 PM PDT 24
Finished Jul 12 05:54:20 PM PDT 24
Peak memory 196624 kb
Host smart-341a00c8-4911-40f2-be39-d8e292293b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924300895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1924300895
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1708249926
Short name T81
Test name
Test status
Simulation time 14805612664 ps
CPU time 5.84 seconds
Started Jul 12 05:53:39 PM PDT 24
Finished Jul 12 05:53:46 PM PDT 24
Peak memory 196924 kb
Host smart-4ae3c2e9-fb41-489a-a5cc-c7b63f18e04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708249926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1708249926
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3733939045
Short name T17
Test name
Test status
Simulation time 8506497963 ps
CPU time 2.15 seconds
Started Jul 12 05:53:45 PM PDT 24
Finished Jul 12 05:53:49 PM PDT 24
Peak memory 215748 kb
Host smart-1ba651ba-3a2e-49f2-8f83-aba5fab4be5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733939045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3733939045
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2145242700
Short name T255
Test name
Test status
Simulation time 392272751 ps
CPU time 0.72 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:53:50 PM PDT 24
Peak memory 191852 kb
Host smart-5bcb68c4-fa7a-40b9-90b8-d52e747353db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145242700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2145242700
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2640341291
Short name T200
Test name
Test status
Simulation time 20926263460 ps
CPU time 8.42 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:54:27 PM PDT 24
Peak memory 191932 kb
Host smart-f9baf0cc-198f-4d70-a5de-8ad6fc061da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640341291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2640341291
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2618063974
Short name T271
Test name
Test status
Simulation time 627815164 ps
CPU time 0.79 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 196640 kb
Host smart-c61cd33e-fe4f-485a-9ec1-fc5f22507af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618063974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2618063974
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.4014944744
Short name T249
Test name
Test status
Simulation time 20286122221 ps
CPU time 31.75 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:54:50 PM PDT 24
Peak memory 196924 kb
Host smart-5baba742-6fba-420e-aa1d-c8a720b99431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014944744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.4014944744
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.101195242
Short name T273
Test name
Test status
Simulation time 553753785 ps
CPU time 0.79 seconds
Started Jul 12 05:54:15 PM PDT 24
Finished Jul 12 05:54:19 PM PDT 24
Peak memory 196636 kb
Host smart-e8901b8c-884f-44f3-87b0-58f038ba61dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101195242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.101195242
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3751424070
Short name T7
Test name
Test status
Simulation time 41284306045 ps
CPU time 51.64 seconds
Started Jul 12 05:54:18 PM PDT 24
Finished Jul 12 05:55:12 PM PDT 24
Peak memory 196892 kb
Host smart-d2ad5bcd-f881-4ede-ab2d-93ed63d8e056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751424070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3751424070
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2032143355
Short name T215
Test name
Test status
Simulation time 548657983 ps
CPU time 1.12 seconds
Started Jul 12 05:54:19 PM PDT 24
Finished Jul 12 05:54:23 PM PDT 24
Peak memory 191884 kb
Host smart-22d7e523-f121-4810-adf0-b117c42cc4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032143355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2032143355
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.174624754
Short name T262
Test name
Test status
Simulation time 28599933490 ps
CPU time 45.28 seconds
Started Jul 12 05:54:18 PM PDT 24
Finished Jul 12 05:55:06 PM PDT 24
Peak memory 191936 kb
Host smart-34e5a8fe-626d-4be7-ad8e-f5b6481e85a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174624754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.174624754
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3655308723
Short name T9
Test name
Test status
Simulation time 496288419 ps
CPU time 0.75 seconds
Started Jul 12 05:54:19 PM PDT 24
Finished Jul 12 05:54:22 PM PDT 24
Peak memory 191880 kb
Host smart-ba25f5b1-9c48-4a26-8661-f451ecfbe7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655308723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3655308723
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1689380285
Short name T259
Test name
Test status
Simulation time 46568257479 ps
CPU time 32.82 seconds
Started Jul 12 05:54:17 PM PDT 24
Finished Jul 12 05:54:53 PM PDT 24
Peak memory 191904 kb
Host smart-04d10675-a52b-4f59-8ff2-c7344dfdb9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689380285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1689380285
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2874584373
Short name T201
Test name
Test status
Simulation time 548698366 ps
CPU time 0.83 seconds
Started Jul 12 05:54:16 PM PDT 24
Finished Jul 12 05:54:20 PM PDT 24
Peak memory 196664 kb
Host smart-714ab8c9-5361-4178-bb8b-ae5ab2f19e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874584373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2874584373
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3130247645
Short name T202
Test name
Test status
Simulation time 55546424556 ps
CPU time 37.69 seconds
Started Jul 12 05:54:25 PM PDT 24
Finished Jul 12 05:55:03 PM PDT 24
Peak memory 191916 kb
Host smart-49ebf72a-7d71-4471-bb0d-ff1b4149ae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130247645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3130247645
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1096725183
Short name T253
Test name
Test status
Simulation time 520170467 ps
CPU time 0.74 seconds
Started Jul 12 05:54:19 PM PDT 24
Finished Jul 12 05:54:22 PM PDT 24
Peak memory 191820 kb
Host smart-3c6df7e1-b38f-4ce8-8bde-511125bf0b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096725183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1096725183
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1134809348
Short name T230
Test name
Test status
Simulation time 32973424147 ps
CPU time 42.96 seconds
Started Jul 12 05:54:23 PM PDT 24
Finished Jul 12 05:55:07 PM PDT 24
Peak memory 191904 kb
Host smart-93d7982d-20ee-4269-b50a-2fe575a9f606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134809348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1134809348
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4185938628
Short name T282
Test name
Test status
Simulation time 467199392 ps
CPU time 0.62 seconds
Started Jul 12 05:54:23 PM PDT 24
Finished Jul 12 05:54:24 PM PDT 24
Peak memory 191844 kb
Host smart-4f999820-3540-4297-ac3f-547ce31c6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185938628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4185938628
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.667544638
Short name T227
Test name
Test status
Simulation time 5014663202 ps
CPU time 2.52 seconds
Started Jul 12 05:54:26 PM PDT 24
Finished Jul 12 05:54:29 PM PDT 24
Peak memory 196932 kb
Host smart-3cef8ee6-a020-4f8d-9b78-f3c8426d13c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667544638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.667544638
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3683562581
Short name T6
Test name
Test status
Simulation time 378456989 ps
CPU time 0.72 seconds
Started Jul 12 05:54:30 PM PDT 24
Finished Jul 12 05:54:33 PM PDT 24
Peak memory 191844 kb
Host smart-7f559e6d-38b4-4f47-a69b-bdcd3f7052b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683562581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3683562581
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1224854022
Short name T164
Test name
Test status
Simulation time 32434891645 ps
CPU time 156.01 seconds
Started Jul 12 05:54:30 PM PDT 24
Finished Jul 12 05:57:09 PM PDT 24
Peak memory 206760 kb
Host smart-6e96c017-a268-4edc-bddf-aeacd422ed60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224854022 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1224854022
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.733347948
Short name T216
Test name
Test status
Simulation time 8877987042 ps
CPU time 7.34 seconds
Started Jul 12 05:54:29 PM PDT 24
Finished Jul 12 05:54:39 PM PDT 24
Peak memory 191908 kb
Host smart-c3eeec20-961e-481b-b419-057b240bec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733347948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.733347948
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3056911466
Short name T204
Test name
Test status
Simulation time 502702776 ps
CPU time 1.3 seconds
Started Jul 12 05:54:28 PM PDT 24
Finished Jul 12 05:54:31 PM PDT 24
Peak memory 191872 kb
Host smart-b1a94519-13ac-4f0f-8b0a-68b00d27ebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056911466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3056911466
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.76227089
Short name T231
Test name
Test status
Simulation time 30941719547 ps
CPU time 11.32 seconds
Started Jul 12 05:54:33 PM PDT 24
Finished Jul 12 05:54:46 PM PDT 24
Peak memory 196888 kb
Host smart-cdf912b2-a8ff-4dda-9b11-cc9579e8b826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76227089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.76227089
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2051151588
Short name T245
Test name
Test status
Simulation time 542847849 ps
CPU time 1.04 seconds
Started Jul 12 05:54:27 PM PDT 24
Finished Jul 12 05:54:29 PM PDT 24
Peak memory 191812 kb
Host smart-9f991a41-43bb-49e6-95eb-7f1ad5a3fcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051151588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2051151588
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3257170121
Short name T20
Test name
Test status
Simulation time 24626042904 ps
CPU time 34.78 seconds
Started Jul 12 05:53:45 PM PDT 24
Finished Jul 12 05:54:22 PM PDT 24
Peak memory 191936 kb
Host smart-d9f5a2ad-bb7c-4ac8-9e85-6770761aa5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257170121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3257170121
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3345316519
Short name T226
Test name
Test status
Simulation time 364533133 ps
CPU time 0.71 seconds
Started Jul 12 05:53:47 PM PDT 24
Finished Jul 12 05:53:51 PM PDT 24
Peak memory 191888 kb
Host smart-c6ecac39-f6e8-4bf6-8572-a098b48a9e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345316519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3345316519
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2181753174
Short name T193
Test name
Test status
Simulation time 534909761 ps
CPU time 1.34 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:53:50 PM PDT 24
Peak memory 196588 kb
Host smart-c187b805-cf22-43d8-a357-b77e9b6adc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181753174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2181753174
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.576982546
Short name T213
Test name
Test status
Simulation time 32548476733 ps
CPU time 49.4 seconds
Started Jul 12 05:53:50 PM PDT 24
Finished Jul 12 05:54:43 PM PDT 24
Peak memory 191940 kb
Host smart-be4df7fa-1861-43ee-9b60-d0c74619cb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576982546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.576982546
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3233557243
Short name T53
Test name
Test status
Simulation time 481600718 ps
CPU time 0.77 seconds
Started Jul 12 05:53:48 PM PDT 24
Finished Jul 12 05:53:52 PM PDT 24
Peak memory 196608 kb
Host smart-6fe232cf-6f94-4496-9f2c-b3071de292bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233557243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3233557243
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1374569686
Short name T248
Test name
Test status
Simulation time 27466468217 ps
CPU time 39.03 seconds
Started Jul 12 05:53:47 PM PDT 24
Finished Jul 12 05:54:30 PM PDT 24
Peak memory 191948 kb
Host smart-0cd242f9-44b4-44af-9fac-2a5a91cd5433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374569686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1374569686
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.325286096
Short name T275
Test name
Test status
Simulation time 381296357 ps
CPU time 0.69 seconds
Started Jul 12 05:53:45 PM PDT 24
Finished Jul 12 05:53:49 PM PDT 24
Peak memory 191788 kb
Host smart-0ca39da1-3641-4684-968a-d18c5cb1f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325286096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.325286096
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2939504163
Short name T280
Test name
Test status
Simulation time 22908881992 ps
CPU time 8.36 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:53:57 PM PDT 24
Peak memory 191908 kb
Host smart-7ea50cd0-b2c0-4f00-a7db-84f418c5cacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939504163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2939504163
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3950475416
Short name T281
Test name
Test status
Simulation time 552284334 ps
CPU time 1.35 seconds
Started Jul 12 05:53:45 PM PDT 24
Finished Jul 12 05:53:48 PM PDT 24
Peak memory 191872 kb
Host smart-70da2071-0733-4321-9d4b-3628695eef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950475416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3950475416
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.685282977
Short name T265
Test name
Test status
Simulation time 9991756334 ps
CPU time 4.06 seconds
Started Jul 12 05:53:44 PM PDT 24
Finished Jul 12 05:53:48 PM PDT 24
Peak memory 191912 kb
Host smart-62cfdcd8-3b28-44d5-9d32-5df44eed36e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685282977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.685282977
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2976712425
Short name T266
Test name
Test status
Simulation time 584700769 ps
CPU time 0.79 seconds
Started Jul 12 05:53:46 PM PDT 24
Finished Jul 12 05:53:50 PM PDT 24
Peak memory 191848 kb
Host smart-37a41b49-5d4b-4e89-957b-116e62b7dc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976712425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2976712425
Directory /workspace/9.aon_timer_smoke/latest
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