Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	29742	1		T1	11		T2	14		T4	11
bark[1]	312	1		T17	26		T164	40		T88	47
bark[2]	721	1		T13	64		T114	26		T106	51
bark[3]	168	1		T88	21		T72	21		T173	35
bark[4]	255	1		T7	14		T21	69		T36	43
bark[5]	750	1		T34	30		T97	14		T123	52
bark[6]	751	1		T12	250		T13	259		T32	35
bark[7]	177	1		T34	135		T83	21		T112	21
bark[8]	388	1		T20	21		T72	21		T73	26
bark[9]	218	1		T34	21		T164	59		T175	14
bark[10]	225	1		T8	14		T17	21		T68	26
bark[11]	488	1		T13	30		T42	21		T178	14
bark[12]	154	1		T21	21		T34	21		T152	14
bark[13]	454	1		T13	21		T32	56		T21	21
bark[14]	427	1		T10	31		T32	21		T135	59
bark[15]	166	1		T41	14		T149	14		T117	14
bark[16]	957	1		T33	64		T73	21		T83	38
bark[17]	509	1		T21	21		T155	26		T115	21
bark[18]	332	1		T10	21		T37	21		T38	26
bark[19]	499	1		T13	60		T37	258		T79	51
bark[20]	638	1		T10	30		T12	54		T21	21
bark[21]	568	1		T21	42		T37	5		T73	99
bark[22]	599	1		T12	212		T17	21		T20	21
bark[23]	383	1		T17	26		T167	14		T34	21
bark[24]	893	1		T119	14		T146	21		T68	381
bark[25]	776	1		T32	26		T33	26		T34	117
bark[26]	445	1		T32	21		T136	14		T35	21
bark[27]	587	1		T32	21		T164	47		T36	242
bark[28]	216	1		T17	30		T38	21		T184	14
bark[29]	315	1		T32	66		T38	21		T67	21
bark[30]	561	1		T17	21		T38	26		T134	21
bark[31]	496	1		T3	14		T67	154		T73	78
bark_0	4369	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29637	1		T1	10		T4	10		T6	10
bite[1]	679	1		T5	13		T21	21		T152	13
bite[2]	391	1		T88	21		T135	30		T123	52
bite[3]	1089	1		T10	31		T38	25		T68	366
bite[4]	596	1		T17	25		T38	264		T72	6
bite[5]	88	1		T17	4		T20	21		T37	4
bite[6]	264	1		T3	13		T17	30		T32	21
bite[7]	234	1		T12	53		T72	21		T79	21
bite[8]	361	1		T8	13		T33	63		T34	21
bite[9]	586	1		T17	21		T164	13		T37	21
bite[10]	401	1		T7	13		T10	21		T21	21
bite[11]	252	1		T153	30		T177	13		T159	13
bite[12]	231	1		T13	21		T149	13		T21	42
bite[13]	305	1		T2	13		T76	21		T109	21
bite[14]	621	1		T13	71		T34	134		T36	42
bite[15]	270	1		T41	13		T114	26		T132	21
bite[16]	484	1		T164	47		T72	4		T74	148
bite[17]	1057	1		T32	65		T119	13		T34	116
bite[18]	280	1		T32	21		T167	13		T36	21
bite[19]	872	1		T17	42		T32	35		T37	257
bite[20]	555	1		T13	258		T17	21		T32	47
bite[21]	203	1		T10	30		T94	21		T78	91
bite[22]	329	1		T13	30		T73	21		T139	21
bite[23]	288	1		T115	21		T180	13		T87	21
bite[24]	617	1		T20	21		T34	30		T36	241
bite[25]	536	1		T32	35		T34	21		T134	51
bite[26]	554	1		T12	249		T13	59		T67	153
bite[27]	261	1		T35	21		T38	21		T72	39
bite[28]	580	1		T33	25		T34	48		T164	47
bite[29]	478	1		T12	211		T32	21		T88	21
bite[30]	265	1		T21	69		T68	26		T174	21
bite[31]	351	1		T136	13		T161	170		T87	47
bite_0	4824	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	43096	1		T1	18		T2	21		T3	21
auto[1]	5443	1		T4	7		T12	351		T24	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1342	1		T13	123		T32	117		T34	85
prescale[1]	1005	1		T12	104		T17	30		T37	36
prescale[2]	732	1		T13	59		T32	19		T20	28
prescale[3]	642	1		T17	63		T36	23		T38	179
prescale[4]	933	1		T12	9		T13	75		T32	18
prescale[5]	900	1		T13	2		T17	40		T34	91
prescale[6]	973	1		T12	51		T13	61		T33	82
prescale[7]	449	1		T13	19		T15	9		T17	19
prescale[8]	663	1		T10	40		T40	9		T34	19
prescale[9]	521	1		T32	9		T36	19		T37	103
prescale[10]	875	1		T17	19		T32	125		T164	66
prescale[11]	884	1		T12	21		T13	24		T17	28
prescale[12]	601	1		T10	58		T12	87		T17	9
prescale[13]	592	1		T12	133		T13	23		T193	9
prescale[14]	879	1		T13	19		T32	19		T194	9
prescale[15]	934	1		T12	30		T13	2		T17	42
prescale[16]	944	1		T17	146		T32	2		T33	2
prescale[17]	1321	1		T14	9		T37	83		T195	9
prescale[18]	698	1		T12	123		T17	2		T20	9
prescale[19]	573	1		T32	28		T20	29		T34	2
prescale[20]	431	1		T32	104		T34	2		T72	9
prescale[21]	851	1		T12	28		T13	96		T17	2
prescale[22]	690	1		T13	55		T20	19		T34	4
prescale[23]	707	1		T13	16		T32	28		T38	21
prescale[24]	462	1		T10	28		T39	9		T32	41
prescale[25]	802	1		T12	61		T13	2		T17	29
prescale[26]	708	1		T12	28		T35	2		T79	57
prescale[27]	378	1		T12	40		T32	29		T33	2
prescale[28]	957	1		T13	36		T17	148		T34	64
prescale[29]	648	1		T13	2		T196	9		T34	28
prescale[30]	370	1		T32	19		T20	19		T38	19
prescale[31]	1159	1		T17	107		T32	50		T197	9
prescale_0	23915	1		T1	18		T2	21		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36159	1		T1	9		T2	21		T3	9
auto[1]	12380	1		T1	9		T3	12		T4	9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	48539	1		T1	18		T2	21		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	28355	1		T1	13		T2	1		T3	1
wkup[1]	276	1		T13	29		T37	30		T128	15
wkup[2]	232	1		T8	15		T32	21		T37	21
wkup[3]	197	1		T34	8		T36	45		T175	15
wkup[4]	179	1		T13	21		T17	21		T72	6
wkup[5]	150	1		T12	21		T134	25		T139	21
wkup[6]	356	1		T20	21		T72	21		T68	21
wkup[7]	218	1		T21	21		T34	41		T67	21
wkup[8]	186	1		T32	26		T164	26		T36	8
wkup[9]	244	1		T10	21		T32	30		T73	21
wkup[10]	135	1		T38	21		T166	15		T126	15
wkup[11]	178	1		T5	15		T32	26		T36	21
wkup[12]	404	1		T34	30		T36	42		T37	51
wkup[13]	364	1		T21	21		T36	42		T38	20
wkup[14]	355	1		T10	21		T12	21		T34	21
wkup[15]	364	1		T12	21		T13	30		T17	42
wkup[16]	377	1		T12	42		T13	21		T32	21
wkup[17]	255	1		T36	21		T134	21		T135	21
wkup[18]	101	1		T130	15		T106	30		T108	35
wkup[19]	244	1		T12	21		T41	15		T88	21
wkup[20]	179	1		T33	8		T21	21		T72	39
wkup[21]	265	1		T136	15		T88	21		T184	15
wkup[22]	177	1		T13	30		T34	21		T88	21
wkup[23]	382	1		T34	21		T37	21		T130	15
wkup[24]	324	1		T3	15		T13	21		T17	21
wkup[25]	235	1		T123	21		T114	21		T93	29
wkup[26]	277	1		T12	21		T13	36		T32	21
wkup[27]	273	1		T32	21		T88	21		T79	30
wkup[28]	198	1		T12	21		T88	15		T74	21
wkup[29]	215	1		T32	56		T72	51		T42	15
wkup[30]	161	1		T88	21		T72	21		T114	21
wkup[31]	189	1		T32	21		T34	21		T88	21
wkup[32]	431	1		T12	21		T13	21		T17	39
wkup[33]	358	1		T32	35		T88	21		T72	21
wkup[34]	114	1		T88	21		T153	15		T161	21
wkup[35]	419	1		T10	30		T17	15		T33	52
wkup[36]	237	1		T13	42		T73	44		T94	20
wkup[37]	144	1		T38	21		T79	30		T94	21
wkup[38]	250	1		T17	21		T36	21		T73	21
wkup[39]	267	1		T17	21		T124	15		T73	35
wkup[40]	339	1		T10	35		T37	21		T38	21
wkup[41]	331	1		T12	21		T13	21		T21	21
wkup[42]	267	1		T36	21		T73	21		T79	21
wkup[43]	285	1		T12	8		T17	6		T32	21
wkup[44]	365	1		T13	21		T34	21		T88	21
wkup[45]	362	1		T2	15		T12	21		T32	63
wkup[46]	160	1		T12	26		T21	21		T72	21
wkup[47]	328	1		T17	51		T34	21		T164	26
wkup[48]	127	1		T17	21		T91	15		T78	21
wkup[49]	260	1		T7	15		T12	21		T17	21
wkup[50]	337	1		T13	21		T32	21		T149	15
wkup[51]	246	1		T38	21		T155	21		T74	21
wkup[52]	230	1		T12	8		T17	8		T36	21
wkup[53]	376	1		T12	21		T34	42		T164	15
wkup[54]	327	1		T167	15		T34	51		T37	21
wkup[55]	261	1		T10	31		T17	21		T74	21
wkup[56]	255	1		T36	40		T72	15		T73	21
wkup[57]	236	1		T119	15		T20	21		T38	21
wkup[58]	326	1		T12	15		T21	21		T88	21
wkup[59]	320	1		T17	21		T34	21		T164	21
wkup[60]	321	1		T17	21		T74	21		T123	21
wkup[61]	177	1		T13	21		T38	21		T73	30
wkup[62]	279	1		T13	30		T97	15		T134	30
wkup[63]	298	1		T67	21		T73	21		T79	21
wkup_0	3461	1		T1	5		T2	5		T3	5