Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.03 99.33 93.67 100.00 98.40 99.51 49.30


Total test records in report: 421
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T285 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1921571833 Jul 14 06:57:56 PM PDT 24 Jul 14 06:58:00 PM PDT 24 558970583 ps
T27 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4289234505 Jul 14 06:57:14 PM PDT 24 Jul 14 06:57:18 PM PDT 24 396851551 ps
T28 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2249888693 Jul 14 06:57:50 PM PDT 24 Jul 14 06:57:55 PM PDT 24 4258391770 ps
T29 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1677217791 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:45 PM PDT 24 4552898262 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3837827945 Jul 14 06:57:20 PM PDT 24 Jul 14 06:57:23 PM PDT 24 383763107 ps
T286 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2014044637 Jul 14 06:57:52 PM PDT 24 Jul 14 06:57:53 PM PDT 24 464786818 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3896918032 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:24 PM PDT 24 2428465963 ps
T30 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1176388238 Jul 14 06:57:40 PM PDT 24 Jul 14 06:57:43 PM PDT 24 4921912912 ps
T44 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2083785236 Jul 14 06:57:36 PM PDT 24 Jul 14 06:57:40 PM PDT 24 1136954046 ps
T45 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3373723875 Jul 14 06:57:40 PM PDT 24 Jul 14 06:57:44 PM PDT 24 434253186 ps
T287 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3780648497 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:29 PM PDT 24 385159803 ps
T46 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3392804761 Jul 14 06:57:22 PM PDT 24 Jul 14 06:57:26 PM PDT 24 559460732 ps
T288 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1449946078 Jul 14 06:57:16 PM PDT 24 Jul 14 06:57:21 PM PDT 24 305062717 ps
T62 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.896449765 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:43 PM PDT 24 832853561 ps
T289 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1160200370 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:41 PM PDT 24 561762475 ps
T290 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2309659254 Jul 14 06:57:53 PM PDT 24 Jul 14 06:57:55 PM PDT 24 595347089 ps
T47 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.644802689 Jul 14 06:57:46 PM PDT 24 Jul 14 06:57:51 PM PDT 24 366408651 ps
T291 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.476567721 Jul 14 06:57:48 PM PDT 24 Jul 14 06:57:49 PM PDT 24 325150452 ps
T292 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1813475654 Jul 14 06:58:01 PM PDT 24 Jul 14 06:58:03 PM PDT 24 273562751 ps
T293 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1660742630 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:31 PM PDT 24 489151704 ps
T294 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1651219690 Jul 14 06:57:22 PM PDT 24 Jul 14 06:57:26 PM PDT 24 483822012 ps
T48 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.746124831 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:28 PM PDT 24 582936245 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2232090590 Jul 14 06:57:26 PM PDT 24 Jul 14 06:57:29 PM PDT 24 292325029 ps
T49 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4017237850 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:40 PM PDT 24 388698565 ps
T296 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3456132113 Jul 14 06:58:11 PM PDT 24 Jul 14 06:58:18 PM PDT 24 281444973 ps
T297 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3413438659 Jul 14 06:57:33 PM PDT 24 Jul 14 06:57:35 PM PDT 24 650695731 ps
T298 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1920811612 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:44 PM PDT 24 485443136 ps
T299 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3389329637 Jul 14 06:57:44 PM PDT 24 Jul 14 06:57:46 PM PDT 24 399994542 ps
T63 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4177595544 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:44 PM PDT 24 958201383 ps
T300 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1799947918 Jul 14 06:57:49 PM PDT 24 Jul 14 06:57:50 PM PDT 24 301893191 ps
T301 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4030696140 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:28 PM PDT 24 491615081 ps
T302 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.31883132 Jul 14 06:57:48 PM PDT 24 Jul 14 06:57:50 PM PDT 24 336421304 ps
T303 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2558717318 Jul 14 06:57:36 PM PDT 24 Jul 14 06:57:37 PM PDT 24 305240960 ps
T304 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2428129179 Jul 14 06:57:47 PM PDT 24 Jul 14 06:57:48 PM PDT 24 528637446 ps
T198 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.144659117 Jul 14 06:57:43 PM PDT 24 Jul 14 06:57:46 PM PDT 24 405672063 ps
T305 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3543637053 Jul 14 06:57:31 PM PDT 24 Jul 14 06:57:34 PM PDT 24 577032395 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3710713124 Jul 14 06:57:36 PM PDT 24 Jul 14 06:57:43 PM PDT 24 7495206404 ps
T306 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2517183439 Jul 14 06:57:35 PM PDT 24 Jul 14 06:57:37 PM PDT 24 490184715 ps
T307 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1450563377 Jul 14 06:57:54 PM PDT 24 Jul 14 06:57:56 PM PDT 24 308662090 ps
T308 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.949304023 Jul 14 06:57:49 PM PDT 24 Jul 14 06:57:51 PM PDT 24 471553967 ps
T309 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3498191152 Jul 14 06:57:43 PM PDT 24 Jul 14 06:57:46 PM PDT 24 770073224 ps
T310 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1449464825 Jul 14 06:57:40 PM PDT 24 Jul 14 06:57:44 PM PDT 24 305799897 ps
T50 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.378867185 Jul 14 06:57:48 PM PDT 24 Jul 14 06:57:49 PM PDT 24 415310079 ps
T64 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.585790750 Jul 14 06:57:55 PM PDT 24 Jul 14 06:57:58 PM PDT 24 2074336857 ps
T311 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2285734100 Jul 14 06:57:16 PM PDT 24 Jul 14 06:57:21 PM PDT 24 465561858 ps
T312 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2782428980 Jul 14 06:57:49 PM PDT 24 Jul 14 06:57:51 PM PDT 24 372011899 ps
T313 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3156647397 Jul 14 06:57:42 PM PDT 24 Jul 14 06:57:45 PM PDT 24 515866931 ps
T314 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3185268221 Jul 14 06:57:45 PM PDT 24 Jul 14 06:57:47 PM PDT 24 311999735 ps
T315 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1859778914 Jul 14 06:57:51 PM PDT 24 Jul 14 06:57:53 PM PDT 24 544853047 ps
T316 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2501431618 Jul 14 06:57:47 PM PDT 24 Jul 14 06:57:48 PM PDT 24 579138331 ps
T317 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3197819935 Jul 14 06:57:28 PM PDT 24 Jul 14 06:57:31 PM PDT 24 541418956 ps
T55 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1789167943 Jul 14 06:57:32 PM PDT 24 Jul 14 06:57:33 PM PDT 24 454227133 ps
T318 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2987756127 Jul 14 06:57:51 PM PDT 24 Jul 14 06:57:53 PM PDT 24 442657126 ps
T319 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3075367413 Jul 14 06:57:23 PM PDT 24 Jul 14 06:57:26 PM PDT 24 653380541 ps
T65 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1591351887 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:41 PM PDT 24 1237249113 ps
T320 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1161984965 Jul 14 06:58:03 PM PDT 24 Jul 14 06:58:07 PM PDT 24 630089890 ps
T321 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2386762433 Jul 14 06:57:59 PM PDT 24 Jul 14 06:58:02 PM PDT 24 320097312 ps
T66 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.666958702 Jul 14 06:57:50 PM PDT 24 Jul 14 06:57:54 PM PDT 24 1053157036 ps
T322 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3410414689 Jul 14 06:57:39 PM PDT 24 Jul 14 06:57:42 PM PDT 24 557012878 ps
T186 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2854616373 Jul 14 06:57:44 PM PDT 24 Jul 14 06:57:53 PM PDT 24 8814828276 ps
T56 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2462853025 Jul 14 06:58:18 PM PDT 24 Jul 14 06:58:25 PM PDT 24 530452099 ps
T323 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1658699028 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:46 PM PDT 24 329118415 ps
T324 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2015812841 Jul 14 06:57:35 PM PDT 24 Jul 14 06:57:42 PM PDT 24 497414213 ps
T189 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.900773117 Jul 14 06:57:18 PM PDT 24 Jul 14 06:57:25 PM PDT 24 7967218273 ps
T325 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1145980815 Jul 14 06:57:45 PM PDT 24 Jul 14 06:57:47 PM PDT 24 362817172 ps
T326 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2312751877 Jul 14 06:57:47 PM PDT 24 Jul 14 06:57:50 PM PDT 24 1801661582 ps
T327 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1519462852 Jul 14 06:57:39 PM PDT 24 Jul 14 06:57:42 PM PDT 24 468478518 ps
T328 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3687295078 Jul 14 06:57:54 PM PDT 24 Jul 14 06:57:56 PM PDT 24 374883245 ps
T329 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1384660046 Jul 14 06:57:56 PM PDT 24 Jul 14 06:57:59 PM PDT 24 453745253 ps
T330 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.985269727 Jul 14 06:57:30 PM PDT 24 Jul 14 06:57:33 PM PDT 24 2329579951 ps
T190 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1603629399 Jul 14 06:57:31 PM PDT 24 Jul 14 06:57:39 PM PDT 24 8514906251 ps
T331 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3976493104 Jul 14 06:57:42 PM PDT 24 Jul 14 06:57:46 PM PDT 24 528120245 ps
T332 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1604893887 Jul 14 06:57:40 PM PDT 24 Jul 14 06:57:43 PM PDT 24 468345797 ps
T333 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.49371089 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:43 PM PDT 24 384495720 ps
T334 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3886686833 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:44 PM PDT 24 508477834 ps
T335 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.34349493 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:23 PM PDT 24 879771184 ps
T336 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4184701414 Jul 14 06:58:02 PM PDT 24 Jul 14 06:58:04 PM PDT 24 439260288 ps
T337 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3443637307 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:41 PM PDT 24 544327574 ps
T338 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2076139820 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:24 PM PDT 24 4369011641 ps
T57 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1528308395 Jul 14 06:57:40 PM PDT 24 Jul 14 06:57:43 PM PDT 24 473571618 ps
T339 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1128647462 Jul 14 06:57:43 PM PDT 24 Jul 14 06:57:46 PM PDT 24 335565558 ps
T187 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.617946878 Jul 14 06:57:50 PM PDT 24 Jul 14 06:57:54 PM PDT 24 8434451701 ps
T340 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.904902566 Jul 14 06:57:37 PM PDT 24 Jul 14 06:57:40 PM PDT 24 427868350 ps
T341 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1360604598 Jul 14 06:57:29 PM PDT 24 Jul 14 06:57:31 PM PDT 24 1150609612 ps
T342 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1309027735 Jul 14 06:57:32 PM PDT 24 Jul 14 06:57:34 PM PDT 24 420174093 ps
T343 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.957903387 Jul 14 06:57:30 PM PDT 24 Jul 14 06:57:32 PM PDT 24 315319744 ps
T344 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.177875227 Jul 14 06:57:43 PM PDT 24 Jul 14 06:57:47 PM PDT 24 4693689608 ps
T345 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3496481632 Jul 14 06:58:03 PM PDT 24 Jul 14 06:58:06 PM PDT 24 462801752 ps
T346 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2489765729 Jul 14 06:57:47 PM PDT 24 Jul 14 06:57:50 PM PDT 24 516717857 ps
T347 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2387000116 Jul 14 06:58:09 PM PDT 24 Jul 14 06:58:17 PM PDT 24 436325360 ps
T348 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2231728408 Jul 14 06:57:25 PM PDT 24 Jul 14 06:57:29 PM PDT 24 633012047 ps
T349 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1719322932 Jul 14 06:57:37 PM PDT 24 Jul 14 06:57:41 PM PDT 24 1260461211 ps
T350 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.594795953 Jul 14 06:57:42 PM PDT 24 Jul 14 06:57:45 PM PDT 24 2071900714 ps
T351 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3782579953 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:41 PM PDT 24 390440042 ps
T352 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2796830543 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:44 PM PDT 24 387014242 ps
T353 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1466243159 Jul 14 06:57:39 PM PDT 24 Jul 14 06:58:01 PM PDT 24 13684491573 ps
T354 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.377215926 Jul 14 06:57:22 PM PDT 24 Jul 14 06:57:25 PM PDT 24 371304929 ps
T355 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3422701316 Jul 14 06:57:31 PM PDT 24 Jul 14 06:57:34 PM PDT 24 1242445812 ps
T356 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1446712658 Jul 14 06:57:47 PM PDT 24 Jul 14 06:57:49 PM PDT 24 434655467 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.673672209 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:44 PM PDT 24 681507800 ps
T357 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1344332984 Jul 14 06:58:11 PM PDT 24 Jul 14 06:58:20 PM PDT 24 1458133497 ps
T358 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3909140461 Jul 14 06:57:29 PM PDT 24 Jul 14 06:57:31 PM PDT 24 403575387 ps
T359 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4034495036 Jul 14 06:57:17 PM PDT 24 Jul 14 06:57:22 PM PDT 24 381488555 ps
T360 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2153776608 Jul 14 06:57:23 PM PDT 24 Jul 14 06:57:28 PM PDT 24 335570798 ps
T361 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1886232392 Jul 14 06:57:52 PM PDT 24 Jul 14 06:57:53 PM PDT 24 546105116 ps
T362 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.948185367 Jul 14 06:58:26 PM PDT 24 Jul 14 06:58:28 PM PDT 24 322104583 ps
T363 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1125770851 Jul 14 06:57:47 PM PDT 24 Jul 14 06:57:49 PM PDT 24 388821948 ps
T191 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3477958992 Jul 14 06:57:43 PM PDT 24 Jul 14 06:57:57 PM PDT 24 8309939435 ps
T364 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1229062479 Jul 14 06:57:37 PM PDT 24 Jul 14 06:57:39 PM PDT 24 399553235 ps
T365 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4268916699 Jul 14 06:57:29 PM PDT 24 Jul 14 06:57:31 PM PDT 24 567007057 ps
T366 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2345793696 Jul 14 06:57:25 PM PDT 24 Jul 14 06:57:30 PM PDT 24 10354696651 ps
T367 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.788032808 Jul 14 06:57:43 PM PDT 24 Jul 14 06:57:45 PM PDT 24 520858415 ps
T368 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.801776679 Jul 14 06:57:43 PM PDT 24 Jul 14 06:57:46 PM PDT 24 396778391 ps
T369 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.113787364 Jul 14 06:57:23 PM PDT 24 Jul 14 06:57:27 PM PDT 24 1868964857 ps
T370 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3603401624 Jul 14 06:58:03 PM PDT 24 Jul 14 06:58:07 PM PDT 24 330154742 ps
T371 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.747542879 Jul 14 06:57:27 PM PDT 24 Jul 14 06:57:30 PM PDT 24 477515397 ps
T372 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.677275556 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:45 PM PDT 24 586679971 ps
T373 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1802768550 Jul 14 06:57:51 PM PDT 24 Jul 14 06:57:53 PM PDT 24 519882108 ps
T374 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3349544666 Jul 14 06:57:26 PM PDT 24 Jul 14 06:57:29 PM PDT 24 307701407 ps
T375 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.957264150 Jul 14 06:57:33 PM PDT 24 Jul 14 06:57:34 PM PDT 24 468898269 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3976305673 Jul 14 06:57:15 PM PDT 24 Jul 14 06:57:21 PM PDT 24 2515049645 ps
T377 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2360751985 Jul 14 06:57:27 PM PDT 24 Jul 14 06:57:31 PM PDT 24 491967201 ps
T378 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2459145744 Jul 14 06:57:43 PM PDT 24 Jul 14 06:57:46 PM PDT 24 450703151 ps
T379 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3538384120 Jul 14 06:57:40 PM PDT 24 Jul 14 06:57:43 PM PDT 24 910174621 ps
T380 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.580566252 Jul 14 06:57:45 PM PDT 24 Jul 14 06:57:49 PM PDT 24 4269214023 ps
T381 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.373998913 Jul 14 06:57:23 PM PDT 24 Jul 14 06:57:27 PM PDT 24 419741655 ps
T382 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3030830737 Jul 14 06:57:47 PM PDT 24 Jul 14 06:57:50 PM PDT 24 589998171 ps
T383 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3274590946 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:43 PM PDT 24 304051299 ps
T192 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1593888276 Jul 14 06:57:44 PM PDT 24 Jul 14 06:57:48 PM PDT 24 9003352486 ps
T384 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.688322492 Jul 14 06:58:21 PM PDT 24 Jul 14 06:58:26 PM PDT 24 416156246 ps
T385 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2322591946 Jul 14 06:57:37 PM PDT 24 Jul 14 06:57:39 PM PDT 24 1956289438 ps
T386 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.396376939 Jul 14 06:57:37 PM PDT 24 Jul 14 06:57:39 PM PDT 24 1158874860 ps
T387 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1132194860 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:23 PM PDT 24 332144553 ps
T388 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1941002946 Jul 14 06:58:07 PM PDT 24 Jul 14 06:58:14 PM PDT 24 517142279 ps
T389 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1596603410 Jul 14 06:57:32 PM PDT 24 Jul 14 06:57:33 PM PDT 24 544980485 ps
T390 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2953768922 Jul 14 06:57:43 PM PDT 24 Jul 14 06:57:46 PM PDT 24 438221940 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1329813622 Jul 14 06:57:48 PM PDT 24 Jul 14 06:57:50 PM PDT 24 508740818 ps
T392 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1711521 Jul 14 06:57:37 PM PDT 24 Jul 14 06:57:44 PM PDT 24 3990781141 ps
T393 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2367507028 Jul 14 06:57:46 PM PDT 24 Jul 14 06:57:48 PM PDT 24 510213101 ps
T51 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2377676293 Jul 14 06:57:26 PM PDT 24 Jul 14 06:57:37 PM PDT 24 5504676316 ps
T394 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3114020442 Jul 14 06:57:30 PM PDT 24 Jul 14 06:57:44 PM PDT 24 8128927377 ps
T395 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1762216447 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:27 PM PDT 24 344931092 ps
T396 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2443285674 Jul 14 06:57:21 PM PDT 24 Jul 14 06:57:26 PM PDT 24 1984435392 ps
T397 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3001870177 Jul 14 06:57:16 PM PDT 24 Jul 14 06:57:21 PM PDT 24 532740846 ps
T398 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.404715556 Jul 14 06:57:25 PM PDT 24 Jul 14 06:57:35 PM PDT 24 7836662000 ps
T399 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2696894619 Jul 14 06:57:37 PM PDT 24 Jul 14 06:57:40 PM PDT 24 266960623 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2553562870 Jul 14 06:57:53 PM PDT 24 Jul 14 06:57:55 PM PDT 24 347786908 ps
T401 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2432663394 Jul 14 06:57:21 PM PDT 24 Jul 14 06:57:24 PM PDT 24 335642705 ps
T402 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2534872749 Jul 14 06:57:40 PM PDT 24 Jul 14 06:57:43 PM PDT 24 478250272 ps
T403 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2955204624 Jul 14 06:57:13 PM PDT 24 Jul 14 06:57:27 PM PDT 24 8269503428 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.536350864 Jul 14 06:57:39 PM PDT 24 Jul 14 06:57:42 PM PDT 24 286120648 ps
T404 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2021712203 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:43 PM PDT 24 1714949808 ps
T405 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1303593543 Jul 14 06:57:19 PM PDT 24 Jul 14 06:57:24 PM PDT 24 362200346 ps
T406 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2775486870 Jul 14 06:57:37 PM PDT 24 Jul 14 06:57:39 PM PDT 24 364714863 ps
T407 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.322761316 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:40 PM PDT 24 332663351 ps
T408 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1126845585 Jul 14 06:57:44 PM PDT 24 Jul 14 06:57:47 PM PDT 24 318735939 ps
T409 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2630171487 Jul 14 06:57:31 PM PDT 24 Jul 14 06:57:33 PM PDT 24 412621128 ps
T410 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.4059509826 Jul 14 06:57:30 PM PDT 24 Jul 14 06:57:32 PM PDT 24 405637032 ps
T411 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1757000993 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:43 PM PDT 24 384073318 ps
T412 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1175133268 Jul 14 06:57:26 PM PDT 24 Jul 14 06:57:40 PM PDT 24 7753649455 ps
T413 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2769534450 Jul 14 06:57:35 PM PDT 24 Jul 14 06:57:38 PM PDT 24 481810087 ps
T414 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.154229404 Jul 14 06:57:40 PM PDT 24 Jul 14 06:57:42 PM PDT 24 499995951 ps
T188 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4271478791 Jul 14 06:57:44 PM PDT 24 Jul 14 06:57:50 PM PDT 24 8358466818 ps
T415 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.290191000 Jul 14 06:57:25 PM PDT 24 Jul 14 06:57:29 PM PDT 24 632298504 ps
T416 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3506655574 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:42 PM PDT 24 433470032 ps
T417 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4097553113 Jul 14 06:57:18 PM PDT 24 Jul 14 06:57:22 PM PDT 24 444844142 ps
T418 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2586604273 Jul 14 06:57:24 PM PDT 24 Jul 14 06:57:33 PM PDT 24 4481055071 ps
T419 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4117247320 Jul 14 06:57:41 PM PDT 24 Jul 14 06:57:43 PM PDT 24 481664640 ps
T53 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3649734106 Jul 14 06:57:18 PM PDT 24 Jul 14 06:57:23 PM PDT 24 508812496 ps
T420 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1904969526 Jul 14 06:57:39 PM PDT 24 Jul 14 06:57:42 PM PDT 24 439705418 ps
T421 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2285080285 Jul 14 06:57:38 PM PDT 24 Jul 14 06:57:46 PM PDT 24 4420600762 ps

Test location /workspace/coverage/default/7.aon_timer_jump.2262198443
Short name T2
Test name
Test status
Simulation time 466515804 ps
CPU time 1.25 seconds
Started Jul 14 06:47:07 PM PDT 24
Finished Jul 14 06:47:09 PM PDT 24
Peak memory 196788 kb
Host smart-6dfac402-6832-4989-aa53-1a06b1bfa6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262198443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2262198443
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1948128381
Short name T12
Test name
Test status
Simulation time 106475630306 ps
CPU time 723.46 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:59:24 PM PDT 24
Peak memory 205712 kb
Host smart-a7e13215-71bb-40d2-b79a-5d6561f74829
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948128381 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1948128381
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1693201733
Short name T19
Test name
Test status
Simulation time 4368847730 ps
CPU time 6.37 seconds
Started Jul 14 06:46:52 PM PDT 24
Finished Jul 14 06:46:58 PM PDT 24
Peak memory 215628 kb
Host smart-1eabac44-b872-4c0c-8c58-c6bcaa99e9e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693201733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1693201733
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2761899626
Short name T78
Test name
Test status
Simulation time 238020271585 ps
CPU time 518.65 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:56:08 PM PDT 24
Peak memory 212232 kb
Host smart-bb2b77f0-8e83-428f-91bc-476fb1cbf5e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761899626 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2761899626
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.687139530
Short name T10
Test name
Test status
Simulation time 152053909246 ps
CPU time 40.02 seconds
Started Jul 14 06:48:28 PM PDT 24
Finished Jul 14 06:49:09 PM PDT 24
Peak memory 196184 kb
Host smart-8eaaaafd-3a3a-43bd-bd2e-d43c55bc23d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687139530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.687139530
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.750498552
Short name T34
Test name
Test status
Simulation time 147001115397 ps
CPU time 698.93 seconds
Started Jul 14 06:47:29 PM PDT 24
Finished Jul 14 06:59:11 PM PDT 24
Peak memory 206136 kb
Host smart-97c50acc-8950-4f6b-90d5-137a76e3296a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750498552 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.750498552
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2843548509
Short name T107
Test name
Test status
Simulation time 98906729350 ps
CPU time 979.56 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 07:03:26 PM PDT 24
Peak memory 215032 kb
Host smart-233137dd-81a5-446f-99e7-ebdcd93ea787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843548509 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2843548509
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1948228489
Short name T73
Test name
Test status
Simulation time 39312768899 ps
CPU time 274.43 seconds
Started Jul 14 06:47:36 PM PDT 24
Finished Jul 14 06:52:11 PM PDT 24
Peak memory 198624 kb
Host smart-5795d0b5-f6ee-4b82-9614-85b4d8c1c569
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948228489 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1948228489
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2249888693
Short name T28
Test name
Test status
Simulation time 4258391770 ps
CPU time 3.92 seconds
Started Jul 14 06:57:50 PM PDT 24
Finished Jul 14 06:57:55 PM PDT 24
Peak memory 198072 kb
Host smart-19775f40-41c6-402e-8813-38239047651c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249888693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2249888693
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1213065927
Short name T13
Test name
Test status
Simulation time 431722231507 ps
CPU time 630.05 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 214052 kb
Host smart-9921983f-a287-40ba-b3c8-d2751554061f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213065927 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1213065927
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2696193899
Short name T90
Test name
Test status
Simulation time 55440753135 ps
CPU time 216.82 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:51:03 PM PDT 24
Peak memory 213980 kb
Host smart-f69fe39f-d2fd-4f67-b01f-4573a189b3ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696193899 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2696193899
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3411131994
Short name T72
Test name
Test status
Simulation time 27110412532 ps
CPU time 178.59 seconds
Started Jul 14 06:48:44 PM PDT 24
Finished Jul 14 06:51:44 PM PDT 24
Peak memory 198380 kb
Host smart-55059662-2b99-4f89-9bb2-36feb93c3d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411131994 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3411131994
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.709468411
Short name T17
Test name
Test status
Simulation time 203912623010 ps
CPU time 506.8 seconds
Started Jul 14 06:47:06 PM PDT 24
Finished Jul 14 06:55:34 PM PDT 24
Peak memory 212344 kb
Host smart-40c37bf1-822e-41e5-afeb-222b62082caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709468411 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.709468411
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2906155741
Short name T68
Test name
Test status
Simulation time 78622770522 ps
CPU time 392.14 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 201660 kb
Host smart-54baee75-b56f-412a-a26b-1c478240ad08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906155741 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2906155741
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1600250567
Short name T93
Test name
Test status
Simulation time 604016316836 ps
CPU time 640.87 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:58:05 PM PDT 24
Peak memory 214628 kb
Host smart-1187585b-af23-46c4-8ca7-28963ab1992f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600250567 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1600250567
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2594484585
Short name T142
Test name
Test status
Simulation time 59578834362 ps
CPU time 652.09 seconds
Started Jul 14 06:47:16 PM PDT 24
Finished Jul 14 06:58:09 PM PDT 24
Peak memory 204208 kb
Host smart-a98fc623-5109-4447-a8f6-3b8577e007f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594484585 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2594484585
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.757771795
Short name T36
Test name
Test status
Simulation time 382840822950 ps
CPU time 218.74 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:51:07 PM PDT 24
Peak memory 208612 kb
Host smart-70bb2170-58de-401a-b9ec-afa55000ed55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757771795 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.757771795
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.165690527
Short name T101
Test name
Test status
Simulation time 394063286363 ps
CPU time 292.97 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:52:23 PM PDT 24
Peak memory 184448 kb
Host smart-77227dd6-36f6-4753-9da6-497564452d08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165690527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.165690527
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1834747493
Short name T87
Test name
Test status
Simulation time 129786773119 ps
CPU time 44.43 seconds
Started Jul 14 06:48:43 PM PDT 24
Finished Jul 14 06:49:29 PM PDT 24
Peak memory 192496 kb
Host smart-556939ba-c4dd-4731-a8f4-65834df44aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834747493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1834747493
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.638324326
Short name T83
Test name
Test status
Simulation time 87390525988 ps
CPU time 124.01 seconds
Started Jul 14 06:47:11 PM PDT 24
Finished Jul 14 06:49:16 PM PDT 24
Peak memory 198268 kb
Host smart-8dec67aa-042c-47e2-81fe-8637ef14d196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638324326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.638324326
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2202757432
Short name T79
Test name
Test status
Simulation time 3206125470 ps
CPU time 5.49 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:47:34 PM PDT 24
Peak memory 198256 kb
Host smart-318e0077-35f6-455c-8224-3a8d10b1ab12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202757432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2202757432
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2604299712
Short name T21
Test name
Test status
Simulation time 9406393332 ps
CPU time 7.81 seconds
Started Jul 14 06:47:27 PM PDT 24
Finished Jul 14 06:47:39 PM PDT 24
Peak memory 198268 kb
Host smart-1597eb55-664b-48c9-9a24-2bcc3a5af87f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604299712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2604299712
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3991199976
Short name T70
Test name
Test status
Simulation time 172168386220 ps
CPU time 199.34 seconds
Started Jul 14 06:47:13 PM PDT 24
Finished Jul 14 06:50:33 PM PDT 24
Peak memory 200004 kb
Host smart-0b3a913b-07b6-483b-bccc-c870a5abdc0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991199976 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3991199976
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3560492783
Short name T138
Test name
Test status
Simulation time 551133833209 ps
CPU time 207.81 seconds
Started Jul 14 06:47:00 PM PDT 24
Finished Jul 14 06:50:28 PM PDT 24
Peak memory 208560 kb
Host smart-23796831-bf05-4b12-9865-9add51fbff3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560492783 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3560492783
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2672569042
Short name T106
Test name
Test status
Simulation time 22630943682 ps
CPU time 228.44 seconds
Started Jul 14 06:47:30 PM PDT 24
Finished Jul 14 06:51:20 PM PDT 24
Peak memory 206796 kb
Host smart-b991fc05-8a88-4bf7-9b59-211c712999e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672569042 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2672569042
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.876049218
Short name T67
Test name
Test status
Simulation time 113379712831 ps
CPU time 797.74 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 07:00:44 PM PDT 24
Peak memory 213196 kb
Host smart-99e28c7a-f728-4f8b-bd0f-77f7c1d0e738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876049218 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.876049218
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.140125393
Short name T109
Test name
Test status
Simulation time 98768770243 ps
CPU time 153.2 seconds
Started Jul 14 06:47:09 PM PDT 24
Finished Jul 14 06:49:44 PM PDT 24
Peak memory 198504 kb
Host smart-cc2608c3-b2e3-421b-a352-b370af6c9d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140125393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.140125393
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3810096501
Short name T88
Test name
Test status
Simulation time 49421504227 ps
CPU time 81.81 seconds
Started Jul 14 06:47:11 PM PDT 24
Finished Jul 14 06:48:33 PM PDT 24
Peak memory 198580 kb
Host smart-4e169362-600f-47f5-9b60-749ac47eba0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810096501 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3810096501
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3578852071
Short name T81
Test name
Test status
Simulation time 320378461725 ps
CPU time 477.69 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:55:26 PM PDT 24
Peak memory 193036 kb
Host smart-924a1c1e-d46e-4b63-a733-3993ea35f19c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578852071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3578852071
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3260335701
Short name T32
Test name
Test status
Simulation time 172412296149 ps
CPU time 397.03 seconds
Started Jul 14 06:47:23 PM PDT 24
Finished Jul 14 06:54:04 PM PDT 24
Peak memory 206832 kb
Host smart-fcd47b7e-ad09-4613-8d81-6d307a452a4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260335701 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3260335701
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2048393378
Short name T110
Test name
Test status
Simulation time 62418258941 ps
CPU time 87.1 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:48:51 PM PDT 24
Peak memory 193048 kb
Host smart-d9ffe91e-aa13-401b-88ab-96f22d951216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048393378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2048393378
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1988158215
Short name T86
Test name
Test status
Simulation time 130024147356 ps
CPU time 191.34 seconds
Started Jul 14 06:47:00 PM PDT 24
Finished Jul 14 06:50:12 PM PDT 24
Peak memory 184652 kb
Host smart-31c9203d-bec7-40a2-90a6-d94339d71e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988158215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1988158215
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2462853025
Short name T56
Test name
Test status
Simulation time 530452099 ps
CPU time 1.33 seconds
Started Jul 14 06:58:18 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 193008 kb
Host smart-965e9889-d5d9-4709-8475-2ddcb46579c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462853025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2462853025
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3340061311
Short name T112
Test name
Test status
Simulation time 223479585763 ps
CPU time 43.76 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:48:09 PM PDT 24
Peak memory 198308 kb
Host smart-8b766c71-7ce7-4ae2-995e-a7b3c28d175b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340061311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3340061311
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.300233935
Short name T95
Test name
Test status
Simulation time 41400254510 ps
CPU time 17.46 seconds
Started Jul 14 06:47:17 PM PDT 24
Finished Jul 14 06:47:36 PM PDT 24
Peak memory 198360 kb
Host smart-37b0e32a-c2e3-4a88-ac0c-436539f8bdc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300233935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.300233935
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2432495348
Short name T89
Test name
Test status
Simulation time 146078559661 ps
CPU time 58.42 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:48:28 PM PDT 24
Peak memory 191976 kb
Host smart-8558d2d0-745c-41b9-95e6-f32fe05744f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432495348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2432495348
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3331453633
Short name T108
Test name
Test status
Simulation time 80100348528 ps
CPU time 110.3 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:49:21 PM PDT 24
Peak memory 197756 kb
Host smart-3a28d158-9d83-4a69-bb6b-c95ac4bae83c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331453633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3331453633
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3529655609
Short name T111
Test name
Test status
Simulation time 82788616948 ps
CPU time 60.61 seconds
Started Jul 14 06:47:32 PM PDT 24
Finished Jul 14 06:48:33 PM PDT 24
Peak memory 193024 kb
Host smart-570ab522-e89f-421c-9ab2-a4cc6316ac5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529655609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3529655609
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1643301988
Short name T121
Test name
Test status
Simulation time 122090017813 ps
CPU time 180.25 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:50:20 PM PDT 24
Peak memory 192732 kb
Host smart-4b418bf8-cff0-48ed-b933-25ca2ba3ba79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643301988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1643301988
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1067940629
Short name T74
Test name
Test status
Simulation time 24790858554 ps
CPU time 184.13 seconds
Started Jul 14 06:48:28 PM PDT 24
Finished Jul 14 06:51:34 PM PDT 24
Peak memory 196404 kb
Host smart-6a81f52a-8509-43e1-8fbf-d4bf5a1a8344
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067940629 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1067940629
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2507497540
Short name T141
Test name
Test status
Simulation time 287305953229 ps
CPU time 88.24 seconds
Started Jul 14 06:47:03 PM PDT 24
Finished Jul 14 06:48:31 PM PDT 24
Peak memory 198360 kb
Host smart-d161b5c3-761d-481a-8654-97eeb68cf034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507497540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2507497540
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3188514913
Short name T96
Test name
Test status
Simulation time 63520152045 ps
CPU time 24.07 seconds
Started Jul 14 06:47:23 PM PDT 24
Finished Jul 14 06:47:51 PM PDT 24
Peak memory 191996 kb
Host smart-9149c910-3d39-418b-b717-71681007914f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188514913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3188514913
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.4223592594
Short name T92
Test name
Test status
Simulation time 123711065150 ps
CPU time 184.2 seconds
Started Jul 14 06:47:06 PM PDT 24
Finished Jul 14 06:50:12 PM PDT 24
Peak memory 206952 kb
Host smart-94e8c121-0e2b-44fc-bf81-b957149503e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223592594 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.4223592594
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.4211441091
Short name T94
Test name
Test status
Simulation time 5235719708 ps
CPU time 2.77 seconds
Started Jul 14 06:47:30 PM PDT 24
Finished Jul 14 06:47:35 PM PDT 24
Peak memory 192060 kb
Host smart-fa288a66-d546-45b5-bf4b-0bdb363af5c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211441091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.4211441091
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1692956177
Short name T144
Test name
Test status
Simulation time 51235957817 ps
CPU time 17.25 seconds
Started Jul 14 06:47:08 PM PDT 24
Finished Jul 14 06:47:27 PM PDT 24
Peak memory 198272 kb
Host smart-c5b349fa-4b04-4077-8036-6098769b99a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692956177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1692956177
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.393996708
Short name T161
Test name
Test status
Simulation time 69557914088 ps
CPU time 270 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:52:01 PM PDT 24
Peak memory 208264 kb
Host smart-c019c121-b8b5-4f25-b41f-575f46f74fc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393996708 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.393996708
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3013003676
Short name T115
Test name
Test status
Simulation time 199724352394 ps
CPU time 75.89 seconds
Started Jul 14 06:47:41 PM PDT 24
Finished Jul 14 06:48:58 PM PDT 24
Peak memory 198120 kb
Host smart-b1bfafc6-ea3b-411d-bef9-d13fe1e99d60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013003676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3013003676
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1454378925
Short name T139
Test name
Test status
Simulation time 110253971542 ps
CPU time 43.76 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:48:13 PM PDT 24
Peak memory 198328 kb
Host smart-e956a3d0-6491-4cf1-9595-ed12a1516248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454378925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1454378925
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3086808035
Short name T77
Test name
Test status
Simulation time 249298981322 ps
CPU time 365.68 seconds
Started Jul 14 06:47:27 PM PDT 24
Finished Jul 14 06:53:37 PM PDT 24
Peak memory 192560 kb
Host smart-cd23a407-3206-4b7b-ad92-af01f1e41b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086808035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3086808035
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1725062139
Short name T76
Test name
Test status
Simulation time 78315103553 ps
CPU time 519.28 seconds
Started Jul 14 06:47:09 PM PDT 24
Finished Jul 14 06:55:49 PM PDT 24
Peak memory 203828 kb
Host smart-caa69ce4-8689-43e9-914a-2ecfbe6309ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725062139 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1725062139
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3343369215
Short name T100
Test name
Test status
Simulation time 436147264953 ps
CPU time 35.3 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 06:47:41 PM PDT 24
Peak memory 192900 kb
Host smart-d0c0b5fd-853d-4a5a-9b0b-9d0a52f728ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343369215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3343369215
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3024798917
Short name T82
Test name
Test status
Simulation time 123450267338 ps
CPU time 87.85 seconds
Started Jul 14 06:47:08 PM PDT 24
Finished Jul 14 06:48:38 PM PDT 24
Peak memory 193080 kb
Host smart-979b5abd-673e-4694-bf2b-3a8a2e8982fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024798917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3024798917
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.352725298
Short name T132
Test name
Test status
Simulation time 194950042789 ps
CPU time 77.06 seconds
Started Jul 14 06:47:09 PM PDT 24
Finished Jul 14 06:48:27 PM PDT 24
Peak memory 198408 kb
Host smart-e9cbe9a2-589e-4a8d-9e05-2d95db59c7de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352725298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.352725298
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.272275114
Short name T103
Test name
Test status
Simulation time 340628037503 ps
CPU time 517.76 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 191976 kb
Host smart-628990b4-2c31-4be0-8f4a-664393c2f04c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272275114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.272275114
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2080028969
Short name T118
Test name
Test status
Simulation time 94336090478 ps
CPU time 554.91 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:56:41 PM PDT 24
Peak memory 202464 kb
Host smart-f21a723d-33c6-4989-b2c1-b29b1b51d8c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080028969 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2080028969
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3190736769
Short name T123
Test name
Test status
Simulation time 454933221240 ps
CPU time 136.87 seconds
Started Jul 14 06:46:56 PM PDT 24
Finished Jul 14 06:49:13 PM PDT 24
Peak memory 193016 kb
Host smart-47a7b9e7-65a8-4635-9415-7e8173c23b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190736769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3190736769
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2721775365
Short name T38
Test name
Test status
Simulation time 223589043368 ps
CPU time 434.76 seconds
Started Jul 14 06:46:56 PM PDT 24
Finished Jul 14 06:54:11 PM PDT 24
Peak memory 211260 kb
Host smart-15d238db-6f71-4948-8e2c-677c0310610c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721775365 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2721775365
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3857321123
Short name T130
Test name
Test status
Simulation time 107902640839 ps
CPU time 244.06 seconds
Started Jul 14 06:48:43 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 206552 kb
Host smart-dbebde1e-0956-4350-98f9-f626b8cbeaef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857321123 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3857321123
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.968482250
Short name T120
Test name
Test status
Simulation time 30769070846 ps
CPU time 110.55 seconds
Started Jul 14 06:47:01 PM PDT 24
Finished Jul 14 06:48:53 PM PDT 24
Peak memory 214096 kb
Host smart-158efc5c-a8ed-468e-a148-9a8708ed3cf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968482250 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.968482250
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.603286502
Short name T134
Test name
Test status
Simulation time 81380444920 ps
CPU time 61.63 seconds
Started Jul 14 06:47:14 PM PDT 24
Finished Jul 14 06:48:17 PM PDT 24
Peak memory 193260 kb
Host smart-a4c54450-7b75-4d78-9a2d-55bf93d80484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603286502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.603286502
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.560944893
Short name T125
Test name
Test status
Simulation time 214966129328 ps
CPU time 84.52 seconds
Started Jul 14 06:47:14 PM PDT 24
Finished Jul 14 06:48:39 PM PDT 24
Peak memory 198196 kb
Host smart-3bba3c92-acce-4474-8f74-523ef18af209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560944893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.560944893
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.231845076
Short name T105
Test name
Test status
Simulation time 16230104831 ps
CPU time 5.46 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:47:28 PM PDT 24
Peak memory 192988 kb
Host smart-cebeffc3-bd49-46e1-b229-229f761063eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231845076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.231845076
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2514057302
Short name T143
Test name
Test status
Simulation time 294293862941 ps
CPU time 204.19 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:50:49 PM PDT 24
Peak memory 191948 kb
Host smart-6c1fa468-77de-4a2b-80be-2c1216e3cc41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514057302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2514057302
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2516882143
Short name T135
Test name
Test status
Simulation time 175887472149 ps
CPU time 57.56 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 06:48:03 PM PDT 24
Peak memory 192708 kb
Host smart-86ad3866-0c92-4f0e-9ddd-7e9c4b6122b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516882143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2516882143
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.561799481
Short name T69
Test name
Test status
Simulation time 225929976951 ps
CPU time 546.7 seconds
Started Jul 14 06:47:23 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 205020 kb
Host smart-087b3cab-8328-4a61-8baa-7981de0bc38b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561799481 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.561799481
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2071083828
Short name T80
Test name
Test status
Simulation time 441555083 ps
CPU time 1.32 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 06:47:07 PM PDT 24
Peak memory 196860 kb
Host smart-59f771de-6037-4ada-a1e5-c4579962a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071083828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2071083828
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.920444833
Short name T42
Test name
Test status
Simulation time 42086250561 ps
CPU time 297.34 seconds
Started Jul 14 06:47:08 PM PDT 24
Finished Jul 14 06:52:06 PM PDT 24
Peak memory 206844 kb
Host smart-b56a3159-b988-4c05-b56e-720155ac63e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920444833 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.920444833
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.860821309
Short name T164
Test name
Test status
Simulation time 200595401938 ps
CPU time 273.26 seconds
Started Jul 14 06:47:11 PM PDT 24
Finished Jul 14 06:51:45 PM PDT 24
Peak memory 198348 kb
Host smart-9398946b-e2b6-4701-8ac8-10da98b377f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860821309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.860821309
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.212351905
Short name T158
Test name
Test status
Simulation time 589472359926 ps
CPU time 850.66 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 07:01:17 PM PDT 24
Peak memory 193008 kb
Host smart-00021fc3-b57d-4535-a0f0-943ee14672b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212351905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.212351905
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2323070277
Short name T99
Test name
Test status
Simulation time 366321253 ps
CPU time 1.08 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:47:28 PM PDT 24
Peak memory 196716 kb
Host smart-57b443ce-1379-4690-aa10-9f24e6bc04c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323070277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2323070277
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.371517635
Short name T129
Test name
Test status
Simulation time 544548661 ps
CPU time 0.78 seconds
Started Jul 14 06:47:36 PM PDT 24
Finished Jul 14 06:47:38 PM PDT 24
Peak memory 196792 kb
Host smart-96d40045-eb8a-4179-a86c-410b9cbbdf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371517635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.371517635
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2024950987
Short name T137
Test name
Test status
Simulation time 444408044 ps
CPU time 0.76 seconds
Started Jul 14 06:46:54 PM PDT 24
Finished Jul 14 06:46:56 PM PDT 24
Peak memory 196720 kb
Host smart-979cb5aa-fe46-40c5-ae8b-8ad4758c4dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024950987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2024950987
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3066294872
Short name T117
Test name
Test status
Simulation time 465162825 ps
CPU time 1.28 seconds
Started Jul 14 06:47:18 PM PDT 24
Finished Jul 14 06:47:20 PM PDT 24
Peak memory 196828 kb
Host smart-32622b4d-503d-481c-8315-5f59952afb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066294872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3066294872
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4279126215
Short name T114
Test name
Test status
Simulation time 47564997030 ps
CPU time 527.02 seconds
Started Jul 14 06:47:10 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 202120 kb
Host smart-b8e47299-ea27-42d0-a559-19d683a00680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279126215 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4279126215
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1489517261
Short name T97
Test name
Test status
Simulation time 418255194 ps
CPU time 0.72 seconds
Started Jul 14 06:48:28 PM PDT 24
Finished Jul 14 06:48:30 PM PDT 24
Peak memory 194912 kb
Host smart-e8f54b9d-ec75-45d4-b99f-aa9fec1e5518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489517261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1489517261
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3668865464
Short name T140
Test name
Test status
Simulation time 560478535 ps
CPU time 0.9 seconds
Started Jul 14 06:47:42 PM PDT 24
Finished Jul 14 06:47:44 PM PDT 24
Peak memory 196520 kb
Host smart-2c361201-8ec7-44e7-8775-10f781ddb068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668865464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3668865464
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3492958948
Short name T122
Test name
Test status
Simulation time 436811066 ps
CPU time 0.64 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:47:30 PM PDT 24
Peak memory 196544 kb
Host smart-1d53c165-c52a-4015-9fe2-e32d3a23fbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492958948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3492958948
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1116615051
Short name T154
Test name
Test status
Simulation time 117579481231 ps
CPU time 137.43 seconds
Started Jul 14 06:47:07 PM PDT 24
Finished Jul 14 06:49:26 PM PDT 24
Peak memory 192320 kb
Host smart-b793ad01-2b09-4677-bde8-69a2b6116875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116615051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1116615051
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3761072564
Short name T162
Test name
Test status
Simulation time 76143311641 ps
CPU time 231.38 seconds
Started Jul 14 06:47:10 PM PDT 24
Finished Jul 14 06:51:03 PM PDT 24
Peak memory 199880 kb
Host smart-b14bfce6-7a45-47a8-b21e-a14367353e64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761072564 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3761072564
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.497100114
Short name T124
Test name
Test status
Simulation time 379625940 ps
CPU time 0.9 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:47:27 PM PDT 24
Peak memory 196628 kb
Host smart-09261db9-3031-4788-a567-4a5cfb13c3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497100114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.497100114
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2704160780
Short name T116
Test name
Test status
Simulation time 390907003498 ps
CPU time 551.83 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 191984 kb
Host smart-83570f45-a3b9-40d0-8247-a23c9206a54b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704160780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2704160780
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3588660147
Short name T43
Test name
Test status
Simulation time 55680632764 ps
CPU time 369.83 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 207516 kb
Host smart-84d34076-b074-45d8-8c49-16235b26bbad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588660147 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3588660147
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2151161565
Short name T8
Test name
Test status
Simulation time 491893559 ps
CPU time 1.27 seconds
Started Jul 14 06:48:28 PM PDT 24
Finished Jul 14 06:48:31 PM PDT 24
Peak memory 196132 kb
Host smart-979ef6bf-0182-4ce4-b54d-e6bf184b8c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151161565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2151161565
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2521368101
Short name T113
Test name
Test status
Simulation time 205928010846 ps
CPU time 74.65 seconds
Started Jul 14 06:49:00 PM PDT 24
Finished Jul 14 06:50:18 PM PDT 24
Peak memory 190352 kb
Host smart-e05829ec-c49e-4a43-b4f4-ac8a3fa45b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521368101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2521368101
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.669107586
Short name T136
Test name
Test status
Simulation time 533648188 ps
CPU time 1.03 seconds
Started Jul 14 06:46:43 PM PDT 24
Finished Jul 14 06:46:45 PM PDT 24
Peak memory 196636 kb
Host smart-30ba2a60-3087-4320-8b23-63a3b3491710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669107586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.669107586
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3009352534
Short name T20
Test name
Test status
Simulation time 75705778521 ps
CPU time 27.64 seconds
Started Jul 14 06:47:07 PM PDT 24
Finished Jul 14 06:47:36 PM PDT 24
Peak memory 191980 kb
Host smart-0066675e-2c6a-4015-b8cd-8d71886ba194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009352534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3009352534
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3811063747
Short name T102
Test name
Test status
Simulation time 433830993 ps
CPU time 1.19 seconds
Started Jul 14 06:47:02 PM PDT 24
Finished Jul 14 06:47:04 PM PDT 24
Peak memory 196732 kb
Host smart-fa45b4ba-721a-4da4-91c8-50817d44f2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811063747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3811063747
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3019283706
Short name T119
Test name
Test status
Simulation time 537244638 ps
CPU time 0.73 seconds
Started Jul 14 06:47:16 PM PDT 24
Finished Jul 14 06:47:18 PM PDT 24
Peak memory 196808 kb
Host smart-6a9c40af-34b5-4b23-92ec-085fb97a1d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019283706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3019283706
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2597060328
Short name T37
Test name
Test status
Simulation time 46372370157 ps
CPU time 390.82 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 214376 kb
Host smart-f31f83fd-8020-4c48-b2c4-96f54c620881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597060328 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2597060328
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3576158353
Short name T35
Test name
Test status
Simulation time 101110792736 ps
CPU time 188.78 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:50:39 PM PDT 24
Peak memory 206748 kb
Host smart-899343d0-5186-470a-80ac-0de54d9af95f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576158353 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3576158353
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.891876679
Short name T147
Test name
Test status
Simulation time 354364239984 ps
CPU time 578.44 seconds
Started Jul 14 06:47:45 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 193120 kb
Host smart-26769740-0cf3-427b-b81d-7ae0547113e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891876679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.891876679
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3903457302
Short name T91
Test name
Test status
Simulation time 524178866 ps
CPU time 0.8 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 06:47:06 PM PDT 24
Peak memory 196736 kb
Host smart-2370b807-4f99-4d1b-8921-bb263b10d238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903457302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3903457302
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2507691037
Short name T174
Test name
Test status
Simulation time 98763139925 ps
CPU time 33.5 seconds
Started Jul 14 06:47:06 PM PDT 24
Finished Jul 14 06:47:41 PM PDT 24
Peak memory 198308 kb
Host smart-c227631e-020f-43f3-bba4-d3e456656331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507691037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2507691037
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.4152696123
Short name T168
Test name
Test status
Simulation time 89677118499 ps
CPU time 183.5 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:50:29 PM PDT 24
Peak memory 207920 kb
Host smart-bd1cde4a-a3c3-49ec-a7bb-f5a88767c64a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152696123 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.4152696123
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.436468044
Short name T128
Test name
Test status
Simulation time 381833284 ps
CPU time 0.72 seconds
Started Jul 14 06:47:18 PM PDT 24
Finished Jul 14 06:47:20 PM PDT 24
Peak memory 196840 kb
Host smart-33eec17d-2ee0-4597-aaa8-25dbcc167b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436468044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.436468044
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1091369043
Short name T104
Test name
Test status
Simulation time 59255579185 ps
CPU time 22.96 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:47:45 PM PDT 24
Peak memory 191952 kb
Host smart-402db800-693a-434d-869c-95a0b68fc76f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091369043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1091369043
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1732649010
Short name T33
Test name
Test status
Simulation time 97062865381 ps
CPU time 354.85 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:53:24 PM PDT 24
Peak memory 210196 kb
Host smart-b2dc19ca-5673-4ffe-bb9f-63d7a9c76c8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732649010 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1732649010
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2691221737
Short name T131
Test name
Test status
Simulation time 447716208 ps
CPU time 1.18 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:47:22 PM PDT 24
Peak memory 196760 kb
Host smart-eb0acd29-09c2-497e-8b7d-6264447ed536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691221737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2691221737
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4007004646
Short name T126
Test name
Test status
Simulation time 518877553 ps
CPU time 1.41 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:47:30 PM PDT 24
Peak memory 196796 kb
Host smart-d744712d-f804-48ab-b8d2-d664b21022ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007004646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4007004646
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2158172030
Short name T155
Test name
Test status
Simulation time 35037377848 ps
CPU time 184.48 seconds
Started Jul 14 06:47:32 PM PDT 24
Finished Jul 14 06:50:38 PM PDT 24
Peak memory 198604 kb
Host smart-e6ebc52a-85fe-4cf8-b6db-48d3c965368a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158172030 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2158172030
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.900773117
Short name T189
Test name
Test status
Simulation time 7967218273 ps
CPU time 4.08 seconds
Started Jul 14 06:57:18 PM PDT 24
Finished Jul 14 06:57:25 PM PDT 24
Peak memory 198280 kb
Host smart-cdb550bb-5e04-4b5a-bae2-a371449e4e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900773117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.900773117
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.aon_timer_jump.915198260
Short name T179
Test name
Test status
Simulation time 570722700 ps
CPU time 0.71 seconds
Started Jul 14 06:47:16 PM PDT 24
Finished Jul 14 06:47:18 PM PDT 24
Peak memory 196688 kb
Host smart-bb3d7620-9ddd-4d39-9639-f892c2f9e44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915198260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.915198260
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2403091190
Short name T176
Test name
Test status
Simulation time 413186505 ps
CPU time 1.17 seconds
Started Jul 14 06:47:08 PM PDT 24
Finished Jul 14 06:47:11 PM PDT 24
Peak memory 196708 kb
Host smart-624f6e57-6ab3-4038-b627-347ff9de8943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403091190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2403091190
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2269239792
Short name T133
Test name
Test status
Simulation time 496103324 ps
CPU time 0.75 seconds
Started Jul 14 06:47:09 PM PDT 24
Finished Jul 14 06:47:11 PM PDT 24
Peak memory 196664 kb
Host smart-8959cc68-1e4b-49d7-91c7-52194edf2653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269239792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2269239792
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1286261679
Short name T3
Test name
Test status
Simulation time 437221531 ps
CPU time 0.74 seconds
Started Jul 14 06:47:12 PM PDT 24
Finished Jul 14 06:47:13 PM PDT 24
Peak memory 196748 kb
Host smart-f8ecccbc-3902-4a1e-bc69-7b6979ab12eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286261679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1286261679
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2211459295
Short name T75
Test name
Test status
Simulation time 207849340215 ps
CPU time 384.08 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:53:48 PM PDT 24
Peak memory 202564 kb
Host smart-e2cc2c6b-2abe-4b9b-bd06-3324731cc537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211459295 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2211459295
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2387570075
Short name T160
Test name
Test status
Simulation time 218516546429 ps
CPU time 167.28 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:50:13 PM PDT 24
Peak memory 198312 kb
Host smart-75eb65aa-47fa-4c82-bb34-9997576e45cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387570075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2387570075
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.620911450
Short name T170
Test name
Test status
Simulation time 124235704328 ps
CPU time 162.86 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:50:09 PM PDT 24
Peak memory 193092 kb
Host smart-9005b700-4465-4048-ac8b-e7a69333b249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620911450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.620911450
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2916330402
Short name T182
Test name
Test status
Simulation time 390220580 ps
CPU time 1.16 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 06:47:07 PM PDT 24
Peak memory 196732 kb
Host smart-022a365d-9484-4004-88a7-627e906522fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916330402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2916330402
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3776230950
Short name T146
Test name
Test status
Simulation time 116476428619 ps
CPU time 43.4 seconds
Started Jul 14 06:47:08 PM PDT 24
Finished Jul 14 06:47:52 PM PDT 24
Peak memory 191972 kb
Host smart-7ee447a4-b4cc-4f32-ac4e-8290cd6c42dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776230950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3776230950
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2001981594
Short name T7
Test name
Test status
Simulation time 465665307 ps
CPU time 0.68 seconds
Started Jul 14 06:47:09 PM PDT 24
Finished Jul 14 06:47:11 PM PDT 24
Peak memory 196744 kb
Host smart-6b010f0b-67b6-4bc7-b74f-a0fb92f91108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001981594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2001981594
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2902838480
Short name T178
Test name
Test status
Simulation time 613537649 ps
CPU time 1.52 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:47:32 PM PDT 24
Peak memory 196764 kb
Host smart-a1a559cc-48c5-497f-9cd3-bd8803896943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902838480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2902838480
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2305860179
Short name T173
Test name
Test status
Simulation time 21344991888 ps
CPU time 33.34 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:48:03 PM PDT 24
Peak memory 192480 kb
Host smart-3a478cf4-5f4a-4baf-8274-0c25636d5c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305860179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2305860179
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1665210257
Short name T169
Test name
Test status
Simulation time 28481760244 ps
CPU time 120.16 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 06:49:07 PM PDT 24
Peak memory 206856 kb
Host smart-d2f04961-ca88-434a-9daa-5d9f393c301d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665210257 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1665210257
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1163672327
Short name T5
Test name
Test status
Simulation time 378803812 ps
CPU time 1.09 seconds
Started Jul 14 06:47:16 PM PDT 24
Finished Jul 14 06:47:18 PM PDT 24
Peak memory 196660 kb
Host smart-3b59325f-faa5-43ed-b3a5-4cbf78334792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163672327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1163672327
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2937226120
Short name T183
Test name
Test status
Simulation time 444057829 ps
CPU time 1.03 seconds
Started Jul 14 06:47:23 PM PDT 24
Finished Jul 14 06:47:27 PM PDT 24
Peak memory 196664 kb
Host smart-eaef821d-c94a-40ab-bca4-0a6f777538a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937226120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2937226120
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2173579940
Short name T153
Test name
Test status
Simulation time 451586833003 ps
CPU time 295.53 seconds
Started Jul 14 06:47:23 PM PDT 24
Finished Jul 14 06:52:23 PM PDT 24
Peak memory 198328 kb
Host smart-feb732ea-a110-43f2-abf1-8b96be531ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173579940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2173579940
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.706986537
Short name T167
Test name
Test status
Simulation time 478807029 ps
CPU time 1.01 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:47:30 PM PDT 24
Peak memory 196700 kb
Host smart-648e719f-fdcd-4d23-b733-fdc4fdd405d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706986537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.706986537
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.58456781
Short name T166
Test name
Test status
Simulation time 441433293 ps
CPU time 0.86 seconds
Started Jul 14 06:47:27 PM PDT 24
Finished Jul 14 06:47:32 PM PDT 24
Peak memory 196796 kb
Host smart-81f4b897-4d60-48b1-9b49-8be13add1037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58456781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.58456781
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.594682640
Short name T172
Test name
Test status
Simulation time 368481472 ps
CPU time 1.08 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:47:34 PM PDT 24
Peak memory 196692 kb
Host smart-d7cf57d7-be80-4537-acb8-7f209fa91adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594682640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.594682640
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3722278907
Short name T156
Test name
Test status
Simulation time 41963660226 ps
CPU time 462.03 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 208692 kb
Host smart-b1b70032-083f-4c00-8776-ffde8ecd9652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722278907 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3722278907
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1605114275
Short name T41
Test name
Test status
Simulation time 600997356 ps
CPU time 0.79 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:47:24 PM PDT 24
Peak memory 196704 kb
Host smart-a05770aa-e7c4-4caa-b536-d70d76ab6dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605114275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1605114275
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1044009669
Short name T163
Test name
Test status
Simulation time 429794731 ps
CPU time 1.21 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 06:47:06 PM PDT 24
Peak memory 196688 kb
Host smart-fc12cfa5-95fd-43b0-b314-267ff013fb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044009669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1044009669
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1247126189
Short name T175
Test name
Test status
Simulation time 476349335 ps
CPU time 0.73 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:47:30 PM PDT 24
Peak memory 196672 kb
Host smart-252f303f-6254-46e0-a6be-b2962ec86aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247126189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1247126189
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3391799132
Short name T152
Test name
Test status
Simulation time 428081990 ps
CPU time 1.17 seconds
Started Jul 14 06:47:34 PM PDT 24
Finished Jul 14 06:47:36 PM PDT 24
Peak memory 196604 kb
Host smart-6eb17364-3648-46ca-9565-66c24a54bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391799132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3391799132
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.617946878
Short name T187
Test name
Test status
Simulation time 8434451701 ps
CPU time 2.04 seconds
Started Jul 14 06:57:50 PM PDT 24
Finished Jul 14 06:57:54 PM PDT 24
Peak memory 198368 kb
Host smart-24f2d8f3-baf8-40d5-842a-a3d3d227e431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617946878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.617946878
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2954618298
Short name T145
Test name
Test status
Simulation time 490414559 ps
CPU time 1.27 seconds
Started Jul 14 06:47:10 PM PDT 24
Finished Jul 14 06:47:13 PM PDT 24
Peak memory 196792 kb
Host smart-9c0f968b-68de-4371-9fc9-936687b623b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954618298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2954618298
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1248448084
Short name T127
Test name
Test status
Simulation time 527073036 ps
CPU time 0.71 seconds
Started Jul 14 06:47:15 PM PDT 24
Finished Jul 14 06:47:16 PM PDT 24
Peak memory 196808 kb
Host smart-4528e284-2dd7-49de-9c54-81e4d496a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248448084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1248448084
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2941083186
Short name T148
Test name
Test status
Simulation time 450995768 ps
CPU time 0.96 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:47:25 PM PDT 24
Peak memory 196788 kb
Host smart-fa101027-5b6d-4882-a8a6-b04d46b94573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941083186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2941083186
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1757403288
Short name T98
Test name
Test status
Simulation time 105776753882 ps
CPU time 210.21 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 06:50:36 PM PDT 24
Peak memory 215024 kb
Host smart-ce13bc5f-4487-48b6-9735-afdd4e3c39d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757403288 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1757403288
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2452517937
Short name T157
Test name
Test status
Simulation time 448095778 ps
CPU time 0.72 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:47:20 PM PDT 24
Peak memory 196660 kb
Host smart-49572c6c-cdf0-44d7-a540-955830f7b0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452517937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2452517937
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.468324253
Short name T180
Test name
Test status
Simulation time 538424472 ps
CPU time 1.3 seconds
Started Jul 14 06:47:20 PM PDT 24
Finished Jul 14 06:47:22 PM PDT 24
Peak memory 196788 kb
Host smart-6865ae50-442a-490b-b25c-2606018e8ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468324253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.468324253
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.442462891
Short name T171
Test name
Test status
Simulation time 526310975 ps
CPU time 0.81 seconds
Started Jul 14 06:47:27 PM PDT 24
Finished Jul 14 06:47:32 PM PDT 24
Peak memory 196468 kb
Host smart-1d2f3b77-bbee-4e64-9f6a-9a4b8207a3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442462891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.442462891
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.657021169
Short name T149
Test name
Test status
Simulation time 568221633 ps
CPU time 1.42 seconds
Started Jul 14 06:48:28 PM PDT 24
Finished Jul 14 06:48:31 PM PDT 24
Peak memory 194384 kb
Host smart-adaaa135-e5db-4d74-a0dc-41e6fd28fb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657021169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.657021169
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1010412086
Short name T165
Test name
Test status
Simulation time 334853982 ps
CPU time 1.09 seconds
Started Jul 14 06:47:20 PM PDT 24
Finished Jul 14 06:47:23 PM PDT 24
Peak memory 196592 kb
Host smart-95be8ef9-64c4-49d4-b2d2-7a1ed4e4ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010412086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1010412086
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3421946290
Short name T177
Test name
Test status
Simulation time 533740350 ps
CPU time 1.33 seconds
Started Jul 14 06:47:31 PM PDT 24
Finished Jul 14 06:47:33 PM PDT 24
Peak memory 196708 kb
Host smart-adf268a8-94c8-44d6-966c-fee8f708f913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421946290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3421946290
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3094512557
Short name T159
Test name
Test status
Simulation time 535933121 ps
CPU time 0.92 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:47:28 PM PDT 24
Peak memory 196628 kb
Host smart-081a3b8f-a6f9-4fb2-99e1-190e1ef7b56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094512557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3094512557
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1384584495
Short name T181
Test name
Test status
Simulation time 486369682 ps
CPU time 0.78 seconds
Started Jul 14 06:47:06 PM PDT 24
Finished Jul 14 06:47:08 PM PDT 24
Peak memory 196708 kb
Host smart-1ff73330-5178-48d7-a14d-34f32f72c0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384584495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1384584495
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2318474534
Short name T71
Test name
Test status
Simulation time 93484386971 ps
CPU time 1005.43 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 07:03:51 PM PDT 24
Peak memory 211828 kb
Host smart-8460e8de-2970-491b-bc68-24aec4f0acf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318474534 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2318474534
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4273892588
Short name T84
Test name
Test status
Simulation time 397410758 ps
CPU time 1.16 seconds
Started Jul 14 06:47:08 PM PDT 24
Finished Jul 14 06:47:10 PM PDT 24
Peak memory 196736 kb
Host smart-91a601cd-d38d-4133-a87c-daa4dbf7c669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273892588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4273892588
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3649734106
Short name T53
Test name
Test status
Simulation time 508812496 ps
CPU time 1.36 seconds
Started Jul 14 06:57:18 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 183908 kb
Host smart-3f770ae8-b9d8-47a3-8411-6c64385084c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649734106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3649734106
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2377676293
Short name T51
Test name
Test status
Simulation time 5504676316 ps
CPU time 8.46 seconds
Started Jul 14 06:57:26 PM PDT 24
Finished Jul 14 06:57:37 PM PDT 24
Peak memory 196336 kb
Host smart-ee58b29b-31b5-457b-8881-a4a86f16625f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377676293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2377676293
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.34349493
Short name T335
Test name
Test status
Simulation time 879771184 ps
CPU time 0.85 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 183800 kb
Host smart-b9d4c1ee-f98a-4711-ba8e-fdb2bb7d8c88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_
reset.34349493
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4289234505
Short name T27
Test name
Test status
Simulation time 396851551 ps
CPU time 1.39 seconds
Started Jul 14 06:57:14 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 196328 kb
Host smart-bd3963e2-defd-4777-be35-c9d6cf796e2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289234505 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.4289234505
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1789167943
Short name T55
Test name
Test status
Simulation time 454227133 ps
CPU time 0.77 seconds
Started Jul 14 06:57:32 PM PDT 24
Finished Jul 14 06:57:33 PM PDT 24
Peak memory 193320 kb
Host smart-c90907a1-8f6a-497b-b131-6ef62031950f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789167943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1789167943
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1132194860
Short name T387
Test name
Test status
Simulation time 332144553 ps
CPU time 1.07 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 183764 kb
Host smart-cd77330f-8b81-4737-9c74-cf5d00a04d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132194860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1132194860
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2558717318
Short name T303
Test name
Test status
Simulation time 305240960 ps
CPU time 0.93 seconds
Started Jul 14 06:57:36 PM PDT 24
Finished Jul 14 06:57:37 PM PDT 24
Peak memory 183660 kb
Host smart-e36c45eb-fc25-493f-b82f-e753fb4c656c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558717318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2558717318
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.322761316
Short name T407
Test name
Test status
Simulation time 332663351 ps
CPU time 0.7 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:40 PM PDT 24
Peak memory 183720 kb
Host smart-d48d78fd-3752-4c1a-94d1-6df436e39b40
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322761316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.322761316
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3976305673
Short name T376
Test name
Test status
Simulation time 2515049645 ps
CPU time 3.48 seconds
Started Jul 14 06:57:15 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 194936 kb
Host smart-6b45a05e-39ec-44e9-86b7-592134eca84d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976305673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3976305673
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3506655574
Short name T416
Test name
Test status
Simulation time 433470032 ps
CPU time 2.38 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:42 PM PDT 24
Peak memory 198660 kb
Host smart-e4526e0d-1e0c-4711-bd9d-51e774d3e01c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506655574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3506655574
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2955204624
Short name T403
Test name
Test status
Simulation time 8269503428 ps
CPU time 11.76 seconds
Started Jul 14 06:57:13 PM PDT 24
Finished Jul 14 06:57:27 PM PDT 24
Peak memory 198168 kb
Host smart-266b9347-28b5-485d-aaa5-f6b54e842edf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955204624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2955204624
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4097553113
Short name T417
Test name
Test status
Simulation time 444844142 ps
CPU time 0.98 seconds
Started Jul 14 06:57:18 PM PDT 24
Finished Jul 14 06:57:22 PM PDT 24
Peak memory 193236 kb
Host smart-c5f209a8-d150-4b21-b7f5-0bc2a8f54387
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097553113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.4097553113
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3710713124
Short name T54
Test name
Test status
Simulation time 7495206404 ps
CPU time 6.04 seconds
Started Jul 14 06:57:36 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 192212 kb
Host smart-f251724a-3495-4906-8d16-ac639341b8e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710713124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3710713124
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2083785236
Short name T44
Test name
Test status
Simulation time 1136954046 ps
CPU time 0.72 seconds
Started Jul 14 06:57:36 PM PDT 24
Finished Jul 14 06:57:40 PM PDT 24
Peak memory 193232 kb
Host smart-de1a4fd9-9349-4795-b04e-78f0980faa41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083785236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2083785236
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3782579953
Short name T351
Test name
Test status
Simulation time 390440042 ps
CPU time 1.13 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:41 PM PDT 24
Peak memory 195908 kb
Host smart-bb11f7f0-969f-4ddc-8142-e9a7493c965b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782579953 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3782579953
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4117247320
Short name T419
Test name
Test status
Simulation time 481664640 ps
CPU time 0.77 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 192092 kb
Host smart-f2bc6ac5-edc9-4405-ac0d-8cd79482daf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117247320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.4117247320
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2285734100
Short name T311
Test name
Test status
Simulation time 465561858 ps
CPU time 1.21 seconds
Started Jul 14 06:57:16 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 183720 kb
Host smart-0f480f7c-329a-4d2a-ab12-985b469c5548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285734100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2285734100
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3909140461
Short name T358
Test name
Test status
Simulation time 403575387 ps
CPU time 0.82 seconds
Started Jul 14 06:57:29 PM PDT 24
Finished Jul 14 06:57:31 PM PDT 24
Peak memory 183684 kb
Host smart-6796abb1-3dcd-42e1-8668-9920d8c57b25
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909140461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3909140461
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.154229404
Short name T414
Test name
Test status
Simulation time 499995951 ps
CPU time 0.84 seconds
Started Jul 14 06:57:40 PM PDT 24
Finished Jul 14 06:57:42 PM PDT 24
Peak memory 183744 kb
Host smart-0bb8754e-e59c-4021-b232-f7fb8a2ce218
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154229404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.154229404
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3896918032
Short name T61
Test name
Test status
Simulation time 2428465963 ps
CPU time 1.75 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 194112 kb
Host smart-7d6a5546-a411-4ffe-9984-7aa453af8bc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896918032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3896918032
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1449946078
Short name T288
Test name
Test status
Simulation time 305062717 ps
CPU time 2.12 seconds
Started Jul 14 06:57:16 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 198628 kb
Host smart-2e2f7bd6-919f-45d8-956e-44410dd6ac08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449946078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1449946078
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3075367413
Short name T319
Test name
Test status
Simulation time 653380541 ps
CPU time 1.13 seconds
Started Jul 14 06:57:23 PM PDT 24
Finished Jul 14 06:57:26 PM PDT 24
Peak memory 198480 kb
Host smart-e44536b1-2fe2-4874-9ca3-2920bc4caef5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075367413 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3075367413
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.378867185
Short name T50
Test name
Test status
Simulation time 415310079 ps
CPU time 0.76 seconds
Started Jul 14 06:57:48 PM PDT 24
Finished Jul 14 06:57:49 PM PDT 24
Peak memory 193500 kb
Host smart-3d2dd15e-537f-4e80-8269-52d0d255d7a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378867185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.378867185
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3349544666
Short name T374
Test name
Test status
Simulation time 307701407 ps
CPU time 0.61 seconds
Started Jul 14 06:57:26 PM PDT 24
Finished Jul 14 06:57:29 PM PDT 24
Peak memory 183720 kb
Host smart-c634ecb9-f370-4aa5-b9d3-b6ea25a5c832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349544666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3349544666
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4177595544
Short name T63
Test name
Test status
Simulation time 958201383 ps
CPU time 1.2 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 193364 kb
Host smart-273ec73f-9237-4b52-94dd-7231eee00ae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177595544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.4177595544
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2360751985
Short name T377
Test name
Test status
Simulation time 491967201 ps
CPU time 1.93 seconds
Started Jul 14 06:57:27 PM PDT 24
Finished Jul 14 06:57:31 PM PDT 24
Peak memory 198608 kb
Host smart-5766d229-31f5-4323-b216-026c885aa80d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360751985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2360751985
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3114020442
Short name T394
Test name
Test status
Simulation time 8128927377 ps
CPU time 12.86 seconds
Started Jul 14 06:57:30 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 198252 kb
Host smart-b04675a7-214b-4dd7-98af-51362705a755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114020442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3114020442
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1384660046
Short name T329
Test name
Test status
Simulation time 453745253 ps
CPU time 1.19 seconds
Started Jul 14 06:57:56 PM PDT 24
Finished Jul 14 06:57:59 PM PDT 24
Peak memory 195268 kb
Host smart-95f28cb5-a1e0-4e82-964c-53afa356f0b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384660046 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1384660046
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1528308395
Short name T57
Test name
Test status
Simulation time 473571618 ps
CPU time 0.97 seconds
Started Jul 14 06:57:40 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 193024 kb
Host smart-fe92fe50-aa55-4c26-93dd-000c4e68b533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528308395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1528308395
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2489765729
Short name T346
Test name
Test status
Simulation time 516717857 ps
CPU time 0.71 seconds
Started Jul 14 06:57:47 PM PDT 24
Finished Jul 14 06:57:50 PM PDT 24
Peak memory 183744 kb
Host smart-7130d6a5-c064-4b3b-ae7a-76de8737321f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489765729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2489765729
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.585790750
Short name T64
Test name
Test status
Simulation time 2074336857 ps
CPU time 1.33 seconds
Started Jul 14 06:57:55 PM PDT 24
Finished Jul 14 06:57:58 PM PDT 24
Peak memory 192876 kb
Host smart-a86493aa-1f3e-440c-89a9-cfa7048f0849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585790750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.585790750
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3780648497
Short name T287
Test name
Test status
Simulation time 385159803 ps
CPU time 1.7 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:29 PM PDT 24
Peak memory 198656 kb
Host smart-f330a4c4-72db-4576-a95f-01d02b3089fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780648497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3780648497
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2285080285
Short name T421
Test name
Test status
Simulation time 4420600762 ps
CPU time 5.53 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 197852 kb
Host smart-f0d445a0-21bd-44f5-aa8b-d707ca0b55ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285080285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2285080285
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2367507028
Short name T393
Test name
Test status
Simulation time 510213101 ps
CPU time 0.77 seconds
Started Jul 14 06:57:46 PM PDT 24
Finished Jul 14 06:57:48 PM PDT 24
Peak memory 195916 kb
Host smart-2aa85db5-20cd-42f5-83ad-46fba4b17bd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367507028 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2367507028
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3156647397
Short name T313
Test name
Test status
Simulation time 515866931 ps
CPU time 0.99 seconds
Started Jul 14 06:57:42 PM PDT 24
Finished Jul 14 06:57:45 PM PDT 24
Peak memory 193448 kb
Host smart-e758665c-cd30-4a88-9f7a-8cf72b0f0e67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156647397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3156647397
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.957264150
Short name T375
Test name
Test status
Simulation time 468898269 ps
CPU time 0.85 seconds
Started Jul 14 06:57:33 PM PDT 24
Finished Jul 14 06:57:34 PM PDT 24
Peak memory 183764 kb
Host smart-15436e31-01b8-4d40-8c75-fbabd9ad55b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957264150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.957264150
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2021712203
Short name T404
Test name
Test status
Simulation time 1714949808 ps
CPU time 3.71 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 193268 kb
Host smart-5f024846-9a90-46c1-a857-eaedac33edd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021712203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2021712203
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.290191000
Short name T415
Test name
Test status
Simulation time 632298504 ps
CPU time 1.53 seconds
Started Jul 14 06:57:25 PM PDT 24
Finished Jul 14 06:57:29 PM PDT 24
Peak memory 198676 kb
Host smart-df00e9be-3d0f-4e9f-9225-0e9cac258fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290191000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.290191000
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.580566252
Short name T380
Test name
Test status
Simulation time 4269214023 ps
CPU time 2.39 seconds
Started Jul 14 06:57:45 PM PDT 24
Finished Jul 14 06:57:49 PM PDT 24
Peak memory 197864 kb
Host smart-24ed5666-dc0c-480d-9ef0-60a43061a88f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580566252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.580566252
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.4059509826
Short name T410
Test name
Test status
Simulation time 405637032 ps
CPU time 0.84 seconds
Started Jul 14 06:57:30 PM PDT 24
Finished Jul 14 06:57:32 PM PDT 24
Peak memory 196284 kb
Host smart-6f42d39a-ae4f-4359-a4d3-ec7d0aaeeb7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059509826 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.4059509826
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2630171487
Short name T409
Test name
Test status
Simulation time 412621128 ps
CPU time 0.76 seconds
Started Jul 14 06:57:31 PM PDT 24
Finished Jul 14 06:57:33 PM PDT 24
Peak memory 193320 kb
Host smart-20b9a232-290d-413b-b636-fec4a1a83891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630171487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2630171487
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1920811612
Short name T298
Test name
Test status
Simulation time 485443136 ps
CPU time 0.88 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 183784 kb
Host smart-380b1cda-a245-4439-b99c-17962aa5d44c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920811612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1920811612
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.396376939
Short name T386
Test name
Test status
Simulation time 1158874860 ps
CPU time 0.96 seconds
Started Jul 14 06:57:37 PM PDT 24
Finished Jul 14 06:57:39 PM PDT 24
Peak memory 193008 kb
Host smart-9532016b-3afb-4a26-be42-9d69bdc2eb86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396376939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.396376939
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3030830737
Short name T382
Test name
Test status
Simulation time 589998171 ps
CPU time 1.98 seconds
Started Jul 14 06:57:47 PM PDT 24
Finished Jul 14 06:57:50 PM PDT 24
Peak memory 198644 kb
Host smart-fbcff580-5b8b-41a5-a577-7340dc146319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030830737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3030830737
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.177875227
Short name T344
Test name
Test status
Simulation time 4693689608 ps
CPU time 1.34 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:47 PM PDT 24
Peak memory 196712 kb
Host smart-0c087d5e-d5a4-44b0-97ee-67f6b263dbb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177875227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.177875227
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1161984965
Short name T320
Test name
Test status
Simulation time 630089890 ps
CPU time 0.94 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:07 PM PDT 24
Peak memory 197300 kb
Host smart-93a659bb-f352-4608-be76-23dd1e32ccd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161984965 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1161984965
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.644802689
Short name T47
Test name
Test status
Simulation time 366408651 ps
CPU time 1.03 seconds
Started Jul 14 06:57:46 PM PDT 24
Finished Jul 14 06:57:51 PM PDT 24
Peak memory 193012 kb
Host smart-984ed39a-99af-4d67-b9c1-90302b88ce53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644802689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.644802689
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2953768922
Short name T390
Test name
Test status
Simulation time 438221940 ps
CPU time 1.21 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 183768 kb
Host smart-18e0e70e-b9c3-4b2c-b4d3-7d1918fcec9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953768922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2953768922
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.594795953
Short name T350
Test name
Test status
Simulation time 2071900714 ps
CPU time 1.43 seconds
Started Jul 14 06:57:42 PM PDT 24
Finished Jul 14 06:57:45 PM PDT 24
Peak memory 193712 kb
Host smart-943c649f-599c-407a-80a9-953ac6a31ea5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594795953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.594795953
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1309027735
Short name T342
Test name
Test status
Simulation time 420174093 ps
CPU time 1.56 seconds
Started Jul 14 06:57:32 PM PDT 24
Finished Jul 14 06:57:34 PM PDT 24
Peak memory 198644 kb
Host smart-36045819-fd9e-4929-bade-a2bda8494c09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309027735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1309027735
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2309659254
Short name T290
Test name
Test status
Simulation time 595347089 ps
CPU time 0.98 seconds
Started Jul 14 06:57:53 PM PDT 24
Finished Jul 14 06:57:55 PM PDT 24
Peak memory 198244 kb
Host smart-17c312fb-c73c-4910-8696-7a0866f2eb4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309659254 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2309659254
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2796830543
Short name T352
Test name
Test status
Simulation time 387014242 ps
CPU time 1.04 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 192060 kb
Host smart-7f4152e3-d270-4488-ad14-06e160d2168d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796830543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2796830543
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3028603004
Short name T283
Test name
Test status
Simulation time 323069975 ps
CPU time 0.96 seconds
Started Jul 14 06:57:30 PM PDT 24
Finished Jul 14 06:57:33 PM PDT 24
Peak memory 183776 kb
Host smart-f98a2ca0-ddc3-4fc9-b5fe-f7e6d3a1b6d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028603004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3028603004
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1719322932
Short name T349
Test name
Test status
Simulation time 1260461211 ps
CPU time 2.86 seconds
Started Jul 14 06:57:37 PM PDT 24
Finished Jul 14 06:57:41 PM PDT 24
Peak memory 193356 kb
Host smart-417c0a65-a356-460f-9fac-9af6e98f7d72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719322932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1719322932
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2386762433
Short name T321
Test name
Test status
Simulation time 320097312 ps
CPU time 1.98 seconds
Started Jul 14 06:57:59 PM PDT 24
Finished Jul 14 06:58:02 PM PDT 24
Peak memory 198600 kb
Host smart-097da0ca-e4f0-4bb8-a741-a07709cca98b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386762433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2386762433
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4271478791
Short name T188
Test name
Test status
Simulation time 8358466818 ps
CPU time 4.43 seconds
Started Jul 14 06:57:44 PM PDT 24
Finished Jul 14 06:57:50 PM PDT 24
Peak memory 198072 kb
Host smart-e84712b9-b7b5-481b-88aa-055d6659691e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271478791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4271478791
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1128647462
Short name T339
Test name
Test status
Simulation time 335565558 ps
CPU time 1.07 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 195972 kb
Host smart-61674f81-3a19-4852-91fb-52655206b7d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128647462 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1128647462
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3687295078
Short name T328
Test name
Test status
Simulation time 374883245 ps
CPU time 0.71 seconds
Started Jul 14 06:57:54 PM PDT 24
Finished Jul 14 06:57:56 PM PDT 24
Peak memory 193148 kb
Host smart-0fdce53d-1c19-45c6-ae82-9d74a9fa89ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687295078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3687295078
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2517183439
Short name T306
Test name
Test status
Simulation time 490184715 ps
CPU time 0.72 seconds
Started Jul 14 06:57:35 PM PDT 24
Finished Jul 14 06:57:37 PM PDT 24
Peak memory 192936 kb
Host smart-35c6bff3-7cd4-40ba-84c8-c980bc192d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517183439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2517183439
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1360604598
Short name T341
Test name
Test status
Simulation time 1150609612 ps
CPU time 0.98 seconds
Started Jul 14 06:57:29 PM PDT 24
Finished Jul 14 06:57:31 PM PDT 24
Peak memory 193060 kb
Host smart-a22fdf25-b6b0-46a9-8a05-677ff0c25875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360604598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1360604598
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.904902566
Short name T340
Test name
Test status
Simulation time 427868350 ps
CPU time 1.99 seconds
Started Jul 14 06:57:37 PM PDT 24
Finished Jul 14 06:57:40 PM PDT 24
Peak memory 198656 kb
Host smart-46593988-c269-4787-a36b-8990476f9818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904902566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.904902566
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1593888276
Short name T192
Test name
Test status
Simulation time 9003352486 ps
CPU time 1.88 seconds
Started Jul 14 06:57:44 PM PDT 24
Finished Jul 14 06:57:48 PM PDT 24
Peak memory 198204 kb
Host smart-20c2b817-fddc-4218-b03c-1e11015885a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593888276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1593888276
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3410414689
Short name T322
Test name
Test status
Simulation time 557012878 ps
CPU time 0.7 seconds
Started Jul 14 06:57:39 PM PDT 24
Finished Jul 14 06:57:42 PM PDT 24
Peak memory 195732 kb
Host smart-dee9828b-04e2-4f89-8713-d75915afb744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410414689 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3410414689
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.144659117
Short name T198
Test name
Test status
Simulation time 405672063 ps
CPU time 0.7 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 193256 kb
Host smart-a7126061-f2a2-42fa-9519-ac15d8c6ff12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144659117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.144659117
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1229062479
Short name T364
Test name
Test status
Simulation time 399553235 ps
CPU time 1.09 seconds
Started Jul 14 06:57:37 PM PDT 24
Finished Jul 14 06:57:39 PM PDT 24
Peak memory 192988 kb
Host smart-1a57e06b-6fa6-447d-ad24-46d1a0ec313c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229062479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1229062479
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2322591946
Short name T385
Test name
Test status
Simulation time 1956289438 ps
CPU time 1.31 seconds
Started Jul 14 06:57:37 PM PDT 24
Finished Jul 14 06:57:39 PM PDT 24
Peak memory 183816 kb
Host smart-d29f68a4-ef4e-44ff-9b3c-e671680259c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322591946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2322591946
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1921571833
Short name T285
Test name
Test status
Simulation time 558970583 ps
CPU time 2.32 seconds
Started Jul 14 06:57:56 PM PDT 24
Finished Jul 14 06:58:00 PM PDT 24
Peak memory 198616 kb
Host smart-5c0775ce-7d7f-448a-9382-355eccbfe11e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921571833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1921571833
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3477958992
Short name T191
Test name
Test status
Simulation time 8309939435 ps
CPU time 12.21 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:57 PM PDT 24
Peak memory 198204 kb
Host smart-8a4c2b99-5b29-49ac-a050-bc8ae8b4b99f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477958992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3477958992
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2387000116
Short name T347
Test name
Test status
Simulation time 436325360 ps
CPU time 1.27 seconds
Started Jul 14 06:58:09 PM PDT 24
Finished Jul 14 06:58:17 PM PDT 24
Peak memory 196012 kb
Host smart-498d0c15-8a23-44be-87d8-d68f5c259efa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387000116 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2387000116
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1886232392
Short name T361
Test name
Test status
Simulation time 546105116 ps
CPU time 0.78 seconds
Started Jul 14 06:57:52 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 193328 kb
Host smart-cfacc769-05b7-4387-8b7d-4095c3e236a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886232392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1886232392
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.31883132
Short name T302
Test name
Test status
Simulation time 336421304 ps
CPU time 0.68 seconds
Started Jul 14 06:57:48 PM PDT 24
Finished Jul 14 06:57:50 PM PDT 24
Peak memory 183584 kb
Host smart-b52bad5e-f6c0-42fc-88de-38ce42436471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31883132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.31883132
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.666958702
Short name T66
Test name
Test status
Simulation time 1053157036 ps
CPU time 2.14 seconds
Started Jul 14 06:57:50 PM PDT 24
Finished Jul 14 06:57:54 PM PDT 24
Peak memory 193056 kb
Host smart-7fd7b6c2-de15-473a-87bf-fd6986249c38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666958702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.666958702
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3976493104
Short name T331
Test name
Test status
Simulation time 528120245 ps
CPU time 1.94 seconds
Started Jul 14 06:57:42 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 198640 kb
Host smart-9fbf9cd5-1d83-47a5-ab7d-8769c901ac79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976493104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3976493104
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1603629399
Short name T190
Test name
Test status
Simulation time 8514906251 ps
CPU time 6.87 seconds
Started Jul 14 06:57:31 PM PDT 24
Finished Jul 14 06:57:39 PM PDT 24
Peak memory 198368 kb
Host smart-551b42e3-02b9-44a0-95fb-ce3e6c7a7263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603629399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1603629399
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1859778914
Short name T315
Test name
Test status
Simulation time 544853047 ps
CPU time 0.79 seconds
Started Jul 14 06:57:51 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 196160 kb
Host smart-b15dfc06-3c6e-4b4c-b0c3-aedb612fab51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859778914 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1859778914
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2553562870
Short name T400
Test name
Test status
Simulation time 347786908 ps
CPU time 0.72 seconds
Started Jul 14 06:57:53 PM PDT 24
Finished Jul 14 06:57:55 PM PDT 24
Peak memory 192092 kb
Host smart-f171f71d-d391-4b43-94f8-8bf31d349361
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553562870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2553562870
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2501431618
Short name T316
Test name
Test status
Simulation time 579138331 ps
CPU time 0.57 seconds
Started Jul 14 06:57:47 PM PDT 24
Finished Jul 14 06:57:48 PM PDT 24
Peak memory 183756 kb
Host smart-5206d551-5896-4b36-956b-bb654896d1ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501431618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2501431618
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2312751877
Short name T326
Test name
Test status
Simulation time 1801661582 ps
CPU time 1.87 seconds
Started Jul 14 06:57:47 PM PDT 24
Finished Jul 14 06:57:50 PM PDT 24
Peak memory 193036 kb
Host smart-5c090d11-3a65-4021-bf6c-a85360641ca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312751877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2312751877
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1941002946
Short name T388
Test name
Test status
Simulation time 517142279 ps
CPU time 2.91 seconds
Started Jul 14 06:58:07 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 198572 kb
Host smart-b58c1e73-a77a-4b9b-b64d-436468ac54a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941002946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1941002946
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3392804761
Short name T46
Test name
Test status
Simulation time 559460732 ps
CPU time 0.96 seconds
Started Jul 14 06:57:22 PM PDT 24
Finished Jul 14 06:57:26 PM PDT 24
Peak memory 194724 kb
Host smart-4d4ccbf5-7b19-4e05-90ea-236e32680a77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392804761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3392804761
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2345793696
Short name T366
Test name
Test status
Simulation time 10354696651 ps
CPU time 2.7 seconds
Started Jul 14 06:57:25 PM PDT 24
Finished Jul 14 06:57:30 PM PDT 24
Peak memory 196152 kb
Host smart-0788823f-06e4-4087-9865-733d5a4423f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345793696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2345793696
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3413438659
Short name T297
Test name
Test status
Simulation time 650695731 ps
CPU time 1.31 seconds
Started Jul 14 06:57:33 PM PDT 24
Finished Jul 14 06:57:35 PM PDT 24
Peak memory 192164 kb
Host smart-93e85bb4-3b65-49af-8751-765caa36d576
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413438659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3413438659
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3886686833
Short name T334
Test name
Test status
Simulation time 508477834 ps
CPU time 0.8 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 196736 kb
Host smart-3386e713-06c1-41d4-be57-67f259b23665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886686833 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3886686833
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2769534450
Short name T413
Test name
Test status
Simulation time 481810087 ps
CPU time 1.25 seconds
Started Jul 14 06:57:35 PM PDT 24
Finished Jul 14 06:57:38 PM PDT 24
Peak memory 193308 kb
Host smart-8e31ad3b-f999-4330-95d7-802f240aba38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769534450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2769534450
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2432663394
Short name T401
Test name
Test status
Simulation time 335642705 ps
CPU time 0.63 seconds
Started Jul 14 06:57:21 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 183744 kb
Host smart-d9081eaa-5b3c-4ad8-9a75-fee38e915234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432663394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2432663394
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1329813622
Short name T391
Test name
Test status
Simulation time 508740818 ps
CPU time 0.86 seconds
Started Jul 14 06:57:48 PM PDT 24
Finished Jul 14 06:57:50 PM PDT 24
Peak memory 183660 kb
Host smart-6503d527-2ee0-4f73-bc63-f6dbbeedc57d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329813622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1329813622
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3001870177
Short name T397
Test name
Test status
Simulation time 532740846 ps
CPU time 0.7 seconds
Started Jul 14 06:57:16 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 183740 kb
Host smart-64abd524-41a1-435b-adbf-72f21eeaf7a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001870177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3001870177
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.113787364
Short name T369
Test name
Test status
Simulation time 1868964857 ps
CPU time 1.79 seconds
Started Jul 14 06:57:23 PM PDT 24
Finished Jul 14 06:57:27 PM PDT 24
Peak memory 192020 kb
Host smart-225ab163-3a26-4ac3-8334-ba81d27fa8d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113787364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.113787364
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4034495036
Short name T359
Test name
Test status
Simulation time 381488555 ps
CPU time 1.57 seconds
Started Jul 14 06:57:17 PM PDT 24
Finished Jul 14 06:57:22 PM PDT 24
Peak memory 198464 kb
Host smart-f645c031-8fae-4b5d-bd60-dae188256f68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034495036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4034495036
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2076139820
Short name T338
Test name
Test status
Simulation time 4369011641 ps
CPU time 2.45 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 196880 kb
Host smart-c55246bf-d887-46be-95d2-2f39838f70af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076139820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2076139820
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2428129179
Short name T304
Test name
Test status
Simulation time 528637446 ps
CPU time 0.56 seconds
Started Jul 14 06:57:47 PM PDT 24
Finished Jul 14 06:57:48 PM PDT 24
Peak memory 183712 kb
Host smart-fdd84ed4-e4ca-4617-a451-5245b351aad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428129179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2428129179
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.788032808
Short name T367
Test name
Test status
Simulation time 520858415 ps
CPU time 0.75 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:45 PM PDT 24
Peak memory 183744 kb
Host smart-bd765a66-f9fc-432e-bf05-c5db6a2defb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788032808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.788032808
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1799947918
Short name T300
Test name
Test status
Simulation time 301893191 ps
CPU time 0.93 seconds
Started Jul 14 06:57:49 PM PDT 24
Finished Jul 14 06:57:50 PM PDT 24
Peak memory 183748 kb
Host smart-d9a38b8f-535c-40c1-9937-709cfc28aff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799947918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1799947918
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.4184701414
Short name T336
Test name
Test status
Simulation time 439260288 ps
CPU time 0.72 seconds
Started Jul 14 06:58:02 PM PDT 24
Finished Jul 14 06:58:04 PM PDT 24
Peak memory 192996 kb
Host smart-8f4606e8-57ae-4fa1-94b3-54dfd3219d93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184701414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.4184701414
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1757000993
Short name T411
Test name
Test status
Simulation time 384073318 ps
CPU time 0.8 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 183924 kb
Host smart-8b3a3205-c20d-4df3-824b-9741e7ea21ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757000993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1757000993
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3185268221
Short name T314
Test name
Test status
Simulation time 311999735 ps
CPU time 0.66 seconds
Started Jul 14 06:57:45 PM PDT 24
Finished Jul 14 06:57:47 PM PDT 24
Peak memory 193004 kb
Host smart-5ccdcf92-3044-4002-9997-b4846c9a3814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185268221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3185268221
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.476567721
Short name T291
Test name
Test status
Simulation time 325150452 ps
CPU time 0.7 seconds
Started Jul 14 06:57:48 PM PDT 24
Finished Jul 14 06:57:49 PM PDT 24
Peak memory 183772 kb
Host smart-ecfe83c9-ab5e-44fb-97db-2e9f730512a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476567721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.476567721
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2459145744
Short name T378
Test name
Test status
Simulation time 450703151 ps
CPU time 1.21 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 183776 kb
Host smart-32e5a3ed-ce92-498a-887f-55af44d2eab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459145744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2459145744
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.688322492
Short name T384
Test name
Test status
Simulation time 416156246 ps
CPU time 0.84 seconds
Started Jul 14 06:58:21 PM PDT 24
Finished Jul 14 06:58:26 PM PDT 24
Peak memory 183736 kb
Host smart-7cecdea7-789c-463e-91f4-91f79e7b42c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688322492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.688322492
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.49371089
Short name T333
Test name
Test status
Simulation time 384495720 ps
CPU time 0.8 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 192980 kb
Host smart-58a3cb3a-98a5-4396-b07a-ceff63defe32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49371089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.49371089
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.673672209
Short name T58
Test name
Test status
Simulation time 681507800 ps
CPU time 1.02 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 183788 kb
Host smart-9f2b2e02-439a-403f-bbab-330ac95908e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673672209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.673672209
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1466243159
Short name T353
Test name
Test status
Simulation time 13684491573 ps
CPU time 19.77 seconds
Started Jul 14 06:57:39 PM PDT 24
Finished Jul 14 06:58:01 PM PDT 24
Peak memory 184060 kb
Host smart-aeccad6e-6bc7-4473-b131-e4a859ea3a4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466243159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1466243159
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3538384120
Short name T379
Test name
Test status
Simulation time 910174621 ps
CPU time 2.03 seconds
Started Jul 14 06:57:40 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 183784 kb
Host smart-42bdf100-535e-4043-86a1-707dd4cba2cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538384120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3538384120
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1904969526
Short name T420
Test name
Test status
Simulation time 439705418 ps
CPU time 1.22 seconds
Started Jul 14 06:57:39 PM PDT 24
Finished Jul 14 06:57:42 PM PDT 24
Peak memory 196740 kb
Host smart-a37d8c8c-d966-4627-8ffb-9abd249e23e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904969526 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1904969526
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.536350864
Short name T52
Test name
Test status
Simulation time 286120648 ps
CPU time 0.94 seconds
Started Jul 14 06:57:39 PM PDT 24
Finished Jul 14 06:57:42 PM PDT 24
Peak memory 193184 kb
Host smart-312c4205-0914-480f-b7ed-7c9711e33fb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536350864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.536350864
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2232090590
Short name T295
Test name
Test status
Simulation time 292325029 ps
CPU time 0.64 seconds
Started Jul 14 06:57:26 PM PDT 24
Finished Jul 14 06:57:29 PM PDT 24
Peak memory 183788 kb
Host smart-bd23c6c2-ed59-4e40-a20d-910433efdc25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232090590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2232090590
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.957903387
Short name T343
Test name
Test status
Simulation time 315319744 ps
CPU time 0.64 seconds
Started Jul 14 06:57:30 PM PDT 24
Finished Jul 14 06:57:32 PM PDT 24
Peak memory 183692 kb
Host smart-16c50b31-2727-4efb-a7c1-1f910279313d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957903387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.957903387
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4030696140
Short name T301
Test name
Test status
Simulation time 491615081 ps
CPU time 0.84 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:28 PM PDT 24
Peak memory 183708 kb
Host smart-c0ed60f1-52c2-4764-92c2-41ccfb44cc6c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030696140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.4030696140
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1344332984
Short name T357
Test name
Test status
Simulation time 1458133497 ps
CPU time 2.12 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 193072 kb
Host smart-f8509851-bef1-4018-ba68-2dceec88a712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344332984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1344332984
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2231728408
Short name T348
Test name
Test status
Simulation time 633012047 ps
CPU time 1.2 seconds
Started Jul 14 06:57:25 PM PDT 24
Finished Jul 14 06:57:29 PM PDT 24
Peak memory 198492 kb
Host smart-2d496b69-be9b-4e3c-bd0b-f41e8389bb15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231728408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2231728408
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1176388238
Short name T30
Test name
Test status
Simulation time 4921912912 ps
CPU time 1.56 seconds
Started Jul 14 06:57:40 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 196764 kb
Host smart-041db3c8-0d74-4deb-b6bc-d1a6d7155aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176388238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1176388238
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3496481632
Short name T345
Test name
Test status
Simulation time 462801752 ps
CPU time 0.89 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:06 PM PDT 24
Peak memory 183740 kb
Host smart-8ec35635-71f7-43c0-9b04-76be2486aaaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496481632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3496481632
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2696894619
Short name T399
Test name
Test status
Simulation time 266960623 ps
CPU time 0.88 seconds
Started Jul 14 06:57:37 PM PDT 24
Finished Jul 14 06:57:40 PM PDT 24
Peak memory 183736 kb
Host smart-c874a326-214b-42b8-bd54-ffad05e0667c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696894619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2696894619
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1450563377
Short name T307
Test name
Test status
Simulation time 308662090 ps
CPU time 0.95 seconds
Started Jul 14 06:57:54 PM PDT 24
Finished Jul 14 06:57:56 PM PDT 24
Peak memory 183548 kb
Host smart-0596321e-32d9-403f-99bb-6817105e5747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450563377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1450563377
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2609823811
Short name T284
Test name
Test status
Simulation time 308981486 ps
CPU time 0.7 seconds
Started Jul 14 06:58:12 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 192976 kb
Host smart-c0154606-3a8e-447c-bb93-a2fc98d6d3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609823811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2609823811
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1813475654
Short name T292
Test name
Test status
Simulation time 273562751 ps
CPU time 0.95 seconds
Started Jul 14 06:58:01 PM PDT 24
Finished Jul 14 06:58:03 PM PDT 24
Peak memory 183616 kb
Host smart-b0a587d6-1518-441d-99c2-6f07f9bedb28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813475654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1813475654
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2782428980
Short name T312
Test name
Test status
Simulation time 372011899 ps
CPU time 0.61 seconds
Started Jul 14 06:57:49 PM PDT 24
Finished Jul 14 06:57:51 PM PDT 24
Peak memory 183748 kb
Host smart-40aee975-1089-4495-bad3-5ed1d4866189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782428980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2782428980
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1802768550
Short name T373
Test name
Test status
Simulation time 519882108 ps
CPU time 1.31 seconds
Started Jul 14 06:57:51 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 183760 kb
Host smart-faeaa2b5-ba32-4a10-9072-cd5c1d716656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802768550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1802768550
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3274590946
Short name T383
Test name
Test status
Simulation time 304051299 ps
CPU time 0.93 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 183748 kb
Host smart-f435124a-d7a6-45d3-bff1-22fd4c18d9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274590946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3274590946
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.949304023
Short name T308
Test name
Test status
Simulation time 471553967 ps
CPU time 0.92 seconds
Started Jul 14 06:57:49 PM PDT 24
Finished Jul 14 06:57:51 PM PDT 24
Peak memory 192996 kb
Host smart-522c4244-dd3f-4f6b-a36c-9faacfafc7fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949304023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.949304023
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3456132113
Short name T296
Test name
Test status
Simulation time 281444973 ps
CPU time 0.73 seconds
Started Jul 14 06:58:11 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 183768 kb
Host smart-1480cba9-8a44-4476-95b9-d2e61dfb8c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456132113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3456132113
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3373723875
Short name T45
Test name
Test status
Simulation time 434253186 ps
CPU time 1.42 seconds
Started Jul 14 06:57:40 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 192012 kb
Host smart-51bbb99e-f690-4882-bebe-96bb9ab688ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373723875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3373723875
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.746124831
Short name T48
Test name
Test status
Simulation time 582936245 ps
CPU time 2.02 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:28 PM PDT 24
Peak memory 192200 kb
Host smart-067cfbe1-1317-4972-8e9a-861e134c163f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746124831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.746124831
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2977519768
Short name T31
Test name
Test status
Simulation time 1216132481 ps
CPU time 1.45 seconds
Started Jul 14 06:57:28 PM PDT 24
Finished Jul 14 06:57:31 PM PDT 24
Peak memory 193312 kb
Host smart-708e1df6-94df-4f51-b97c-154ab2ad7bf0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977519768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2977519768
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.377215926
Short name T354
Test name
Test status
Simulation time 371304929 ps
CPU time 0.91 seconds
Started Jul 14 06:57:22 PM PDT 24
Finished Jul 14 06:57:25 PM PDT 24
Peak memory 196228 kb
Host smart-f6c668aa-9a4a-4e4e-901d-b5e41c609b7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377215926 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.377215926
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3837827945
Short name T60
Test name
Test status
Simulation time 383763107 ps
CPU time 0.71 seconds
Started Jul 14 06:57:20 PM PDT 24
Finished Jul 14 06:57:23 PM PDT 24
Peak memory 194040 kb
Host smart-6be1787b-20ce-4be6-9061-1b23f8b26bac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837827945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3837827945
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1762216447
Short name T395
Test name
Test status
Simulation time 344931092 ps
CPU time 0.64 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:27 PM PDT 24
Peak memory 183752 kb
Host smart-534dfaec-7315-4f47-836e-21da686e8a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762216447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1762216447
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1596603410
Short name T389
Test name
Test status
Simulation time 544980485 ps
CPU time 0.6 seconds
Started Jul 14 06:57:32 PM PDT 24
Finished Jul 14 06:57:33 PM PDT 24
Peak memory 183708 kb
Host smart-029c456d-b434-426b-9470-c88fdee1ab5a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596603410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1596603410
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2534872749
Short name T402
Test name
Test status
Simulation time 478250272 ps
CPU time 1.17 seconds
Started Jul 14 06:57:40 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 183728 kb
Host smart-19d66465-eb58-4f88-9054-3be26063b6ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534872749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2534872749
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2443285674
Short name T396
Test name
Test status
Simulation time 1984435392 ps
CPU time 3.08 seconds
Started Jul 14 06:57:21 PM PDT 24
Finished Jul 14 06:57:26 PM PDT 24
Peak memory 184020 kb
Host smart-9ea83995-beaf-4865-9bb9-609da031db26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443285674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2443285674
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1303593543
Short name T405
Test name
Test status
Simulation time 362200346 ps
CPU time 1.68 seconds
Started Jul 14 06:57:19 PM PDT 24
Finished Jul 14 06:57:24 PM PDT 24
Peak memory 198672 kb
Host smart-a3a25419-4671-4d18-b022-221e067976b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303593543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1303593543
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2586604273
Short name T418
Test name
Test status
Simulation time 4481055071 ps
CPU time 6.73 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:33 PM PDT 24
Peak memory 197920 kb
Host smart-91044ef5-a832-48ca-8c10-8834f8e870b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586604273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2586604273
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3389329637
Short name T299
Test name
Test status
Simulation time 399994542 ps
CPU time 1.12 seconds
Started Jul 14 06:57:44 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 183652 kb
Host smart-76ff5219-8938-444e-af3a-81a3c7de5b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389329637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3389329637
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3603401624
Short name T370
Test name
Test status
Simulation time 330154742 ps
CPU time 0.68 seconds
Started Jul 14 06:58:03 PM PDT 24
Finished Jul 14 06:58:07 PM PDT 24
Peak memory 183760 kb
Host smart-20fed7d5-7843-4a59-acd9-91b1d81931ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603401624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3603401624
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1126845585
Short name T408
Test name
Test status
Simulation time 318735939 ps
CPU time 1 seconds
Started Jul 14 06:57:44 PM PDT 24
Finished Jul 14 06:57:47 PM PDT 24
Peak memory 192948 kb
Host smart-4ec60064-8b1c-43ef-ad18-82847f55497f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126845585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1126845585
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1145980815
Short name T325
Test name
Test status
Simulation time 362817172 ps
CPU time 0.81 seconds
Started Jul 14 06:57:45 PM PDT 24
Finished Jul 14 06:57:47 PM PDT 24
Peak memory 183768 kb
Host smart-d276b5b2-d32e-497d-abf9-56fbc9ab3692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145980815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1145980815
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1446712658
Short name T356
Test name
Test status
Simulation time 434655467 ps
CPU time 0.7 seconds
Started Jul 14 06:57:47 PM PDT 24
Finished Jul 14 06:57:49 PM PDT 24
Peak memory 183768 kb
Host smart-811936ff-57f2-4d6c-a8b7-7b8fd23d8aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446712658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1446712658
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2987756127
Short name T318
Test name
Test status
Simulation time 442657126 ps
CPU time 0.96 seconds
Started Jul 14 06:57:51 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 183780 kb
Host smart-fe534d18-e7d6-40ae-a019-c5baec53af7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987756127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2987756127
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2014044637
Short name T286
Test name
Test status
Simulation time 464786818 ps
CPU time 0.62 seconds
Started Jul 14 06:57:52 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 183768 kb
Host smart-ec934224-beef-483e-88e6-b7c8c310c44c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014044637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2014044637
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.948185367
Short name T362
Test name
Test status
Simulation time 322104583 ps
CPU time 0.94 seconds
Started Jul 14 06:58:26 PM PDT 24
Finished Jul 14 06:58:28 PM PDT 24
Peak memory 192988 kb
Host smart-05e23462-1a6a-46a0-81cc-a22f75864a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948185367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.948185367
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1658699028
Short name T323
Test name
Test status
Simulation time 329118415 ps
CPU time 0.79 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 183772 kb
Host smart-1e8b17c2-bd39-42da-a1a2-7e15c98a231a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658699028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1658699028
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1125770851
Short name T363
Test name
Test status
Simulation time 388821948 ps
CPU time 0.83 seconds
Started Jul 14 06:57:47 PM PDT 24
Finished Jul 14 06:57:49 PM PDT 24
Peak memory 192976 kb
Host smart-32c652ef-1180-4337-b3c6-94af06f29dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125770851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1125770851
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1160200370
Short name T289
Test name
Test status
Simulation time 561762475 ps
CPU time 1.55 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:41 PM PDT 24
Peak memory 197040 kb
Host smart-729a80c3-ecfb-48f3-ae19-6725745be324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160200370 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1160200370
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.373998913
Short name T381
Test name
Test status
Simulation time 419741655 ps
CPU time 1.13 seconds
Started Jul 14 06:57:23 PM PDT 24
Finished Jul 14 06:57:27 PM PDT 24
Peak memory 193216 kb
Host smart-83eb2267-c4f3-4110-9994-d540831a8f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373998913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.373998913
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1651219690
Short name T294
Test name
Test status
Simulation time 483822012 ps
CPU time 1.29 seconds
Started Jul 14 06:57:22 PM PDT 24
Finished Jul 14 06:57:26 PM PDT 24
Peak memory 192992 kb
Host smart-43aa09d1-e088-4f21-ae8b-6d12a2f8879b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651219690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1651219690
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1591351887
Short name T65
Test name
Test status
Simulation time 1237249113 ps
CPU time 0.97 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:41 PM PDT 24
Peak memory 183656 kb
Host smart-96fa0531-03e8-4b4f-9eef-3f5b46a70f3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591351887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1591351887
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.677275556
Short name T372
Test name
Test status
Simulation time 586679971 ps
CPU time 1.35 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:45 PM PDT 24
Peak memory 198644 kb
Host smart-4ea7a5f2-d378-4d39-bdca-b674ea3d17e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677275556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.677275556
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1711521
Short name T392
Test name
Test status
Simulation time 3990781141 ps
CPU time 6.85 seconds
Started Jul 14 06:57:37 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 197652 kb
Host smart-852e174d-1984-4844-807b-f1d35baf0705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_in
tg_err.1711521
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3197819935
Short name T317
Test name
Test status
Simulation time 541418956 ps
CPU time 1.08 seconds
Started Jul 14 06:57:28 PM PDT 24
Finished Jul 14 06:57:31 PM PDT 24
Peak memory 196400 kb
Host smart-cd770ac9-8114-43f7-9e28-0393318730cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197819935 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3197819935
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4017237850
Short name T49
Test name
Test status
Simulation time 388698565 ps
CPU time 0.71 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:40 PM PDT 24
Peak memory 193024 kb
Host smart-9589791c-6cf9-4f89-bccd-a52de5cc07f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017237850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4017237850
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.747542879
Short name T371
Test name
Test status
Simulation time 477515397 ps
CPU time 0.79 seconds
Started Jul 14 06:57:27 PM PDT 24
Finished Jul 14 06:57:30 PM PDT 24
Peak memory 183724 kb
Host smart-45819321-d364-4667-b7ba-c1f14092fcdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747542879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.747542879
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.985269727
Short name T330
Test name
Test status
Simulation time 2329579951 ps
CPU time 2.19 seconds
Started Jul 14 06:57:30 PM PDT 24
Finished Jul 14 06:57:33 PM PDT 24
Peak memory 195196 kb
Host smart-a6a4ca0f-1f34-4b34-a329-acbcbaad316b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985269727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.985269727
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1449464825
Short name T310
Test name
Test status
Simulation time 305799897 ps
CPU time 2.14 seconds
Started Jul 14 06:57:40 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 198684 kb
Host smart-2e9d76a2-944a-4edb-b84a-9d7a66ee8930
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449464825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1449464825
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1677217791
Short name T29
Test name
Test status
Simulation time 4552898262 ps
CPU time 5.64 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:45 PM PDT 24
Peak memory 197804 kb
Host smart-0e3ea533-0328-4f26-b72d-66dc6e7477c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677217791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1677217791
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2015812841
Short name T324
Test name
Test status
Simulation time 497414213 ps
CPU time 1.31 seconds
Started Jul 14 06:57:35 PM PDT 24
Finished Jul 14 06:57:42 PM PDT 24
Peak memory 196052 kb
Host smart-64bfb0ea-079a-4c3f-bc8a-59f6256f731f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015812841 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2015812841
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1519462852
Short name T327
Test name
Test status
Simulation time 468478518 ps
CPU time 1.16 seconds
Started Jul 14 06:57:39 PM PDT 24
Finished Jul 14 06:57:42 PM PDT 24
Peak memory 193868 kb
Host smart-44b392e7-b5a7-42ae-a779-192ef55f1c36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519462852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1519462852
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1660742630
Short name T293
Test name
Test status
Simulation time 489151704 ps
CPU time 1.1 seconds
Started Jul 14 06:57:24 PM PDT 24
Finished Jul 14 06:57:31 PM PDT 24
Peak memory 183744 kb
Host smart-59f103cb-7c0f-459f-8148-66600b0e6da3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660742630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1660742630
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.896449765
Short name T62
Test name
Test status
Simulation time 832853561 ps
CPU time 0.67 seconds
Started Jul 14 06:57:41 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 192868 kb
Host smart-fad1f7c8-9f08-4a1a-bdae-5530737d5a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896449765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.896449765
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3498191152
Short name T309
Test name
Test status
Simulation time 770073224 ps
CPU time 1.14 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 198488 kb
Host smart-05d36ee1-bcf5-441a-b6ba-ce908d61d8f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498191152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3498191152
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.404715556
Short name T398
Test name
Test status
Simulation time 7836662000 ps
CPU time 6.5 seconds
Started Jul 14 06:57:25 PM PDT 24
Finished Jul 14 06:57:35 PM PDT 24
Peak memory 198352 kb
Host smart-7e997b64-d9c7-459e-a488-54d8031abecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404715556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.404715556
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3543637053
Short name T305
Test name
Test status
Simulation time 577032395 ps
CPU time 1.46 seconds
Started Jul 14 06:57:31 PM PDT 24
Finished Jul 14 06:57:34 PM PDT 24
Peak memory 196796 kb
Host smart-43879ec7-1063-43e3-a3ed-47eb570d17a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543637053 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3543637053
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2775486870
Short name T406
Test name
Test status
Simulation time 364714863 ps
CPU time 0.67 seconds
Started Jul 14 06:57:37 PM PDT 24
Finished Jul 14 06:57:39 PM PDT 24
Peak memory 183736 kb
Host smart-8d555790-47c6-4356-9e49-2ec337996e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775486870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2775486870
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1550376095
Short name T26
Test name
Test status
Simulation time 1213357994 ps
CPU time 1.28 seconds
Started Jul 14 06:57:53 PM PDT 24
Finished Jul 14 06:57:56 PM PDT 24
Peak memory 192876 kb
Host smart-1bc27ed5-6f63-4ecf-b6ca-d347dfbae1a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550376095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1550376095
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.801776679
Short name T368
Test name
Test status
Simulation time 396778391 ps
CPU time 1.55 seconds
Started Jul 14 06:57:43 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 198620 kb
Host smart-f8c386c9-cf42-4cb6-a921-4173f87ea59a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801776679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.801776679
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2854616373
Short name T186
Test name
Test status
Simulation time 8814828276 ps
CPU time 7.42 seconds
Started Jul 14 06:57:44 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 198280 kb
Host smart-72a17f45-bfdc-4e47-a0f2-b92c36ccb175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854616373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2854616373
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1604893887
Short name T332
Test name
Test status
Simulation time 468345797 ps
CPU time 1.23 seconds
Started Jul 14 06:57:40 PM PDT 24
Finished Jul 14 06:57:43 PM PDT 24
Peak memory 195416 kb
Host smart-0bc372a5-13a6-4d45-a4d0-0b882442e048
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604893887 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1604893887
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4268916699
Short name T365
Test name
Test status
Simulation time 567007057 ps
CPU time 0.75 seconds
Started Jul 14 06:57:29 PM PDT 24
Finished Jul 14 06:57:31 PM PDT 24
Peak memory 193448 kb
Host smart-f87bc496-fb93-4985-bc05-9c06c5b930d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268916699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4268916699
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3443637307
Short name T337
Test name
Test status
Simulation time 544327574 ps
CPU time 0.72 seconds
Started Jul 14 06:57:38 PM PDT 24
Finished Jul 14 06:57:41 PM PDT 24
Peak memory 183572 kb
Host smart-8871d5e2-0ff1-400a-ba60-46fd655b4dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443637307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3443637307
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3422701316
Short name T355
Test name
Test status
Simulation time 1242445812 ps
CPU time 1.35 seconds
Started Jul 14 06:57:31 PM PDT 24
Finished Jul 14 06:57:34 PM PDT 24
Peak memory 193024 kb
Host smart-710c1510-21fd-4fc6-8ef5-5f3a8dd43f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422701316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3422701316
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2153776608
Short name T360
Test name
Test status
Simulation time 335570798 ps
CPU time 2.19 seconds
Started Jul 14 06:57:23 PM PDT 24
Finished Jul 14 06:57:28 PM PDT 24
Peak memory 198816 kb
Host smart-caed617a-5925-4fa4-b88d-10be8bdddf14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153776608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2153776608
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1175133268
Short name T412
Test name
Test status
Simulation time 7753649455 ps
CPU time 11.7 seconds
Started Jul 14 06:57:26 PM PDT 24
Finished Jul 14 06:57:40 PM PDT 24
Peak memory 198092 kb
Host smart-85553798-82cb-48a9-9649-515e23724413
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175133268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1175133268
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3821756637
Short name T238
Test name
Test status
Simulation time 49057537166 ps
CPU time 43.1 seconds
Started Jul 14 06:46:40 PM PDT 24
Finished Jul 14 06:47:24 PM PDT 24
Peak memory 191924 kb
Host smart-9da55919-df33-411b-adc6-74b0800495c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821756637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3821756637
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1912694108
Short name T226
Test name
Test status
Simulation time 433819308 ps
CPU time 0.75 seconds
Started Jul 14 06:46:57 PM PDT 24
Finished Jul 14 06:46:58 PM PDT 24
Peak memory 196756 kb
Host smart-161a1645-64f9-4929-babe-1e3c0f6550d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912694108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1912694108
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.625111298
Short name T204
Test name
Test status
Simulation time 951939397 ps
CPU time 1.31 seconds
Started Jul 14 06:47:01 PM PDT 24
Finished Jul 14 06:47:03 PM PDT 24
Peak memory 191872 kb
Host smart-ab873ed0-8eab-42c6-b679-8033605dbb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625111298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.625111298
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2655785300
Short name T22
Test name
Test status
Simulation time 7670590961 ps
CPU time 2.13 seconds
Started Jul 14 06:46:57 PM PDT 24
Finished Jul 14 06:47:00 PM PDT 24
Peak memory 215812 kb
Host smart-4950def5-0189-416b-8461-ddf823b98da5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655785300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2655785300
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.671753027
Short name T24
Test name
Test status
Simulation time 445107487 ps
CPU time 1.28 seconds
Started Jul 14 06:46:41 PM PDT 24
Finished Jul 14 06:46:42 PM PDT 24
Peak memory 191780 kb
Host smart-4cf00125-e449-4430-90e0-53430eb60983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671753027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.671753027
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4092417914
Short name T85
Test name
Test status
Simulation time 38861703138 ps
CPU time 307.16 seconds
Started Jul 14 06:46:47 PM PDT 24
Finished Jul 14 06:51:54 PM PDT 24
Peak memory 213244 kb
Host smart-2892a169-7aeb-44e6-a00c-cea9be818d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092417914 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4092417914
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3728884685
Short name T265
Test name
Test status
Simulation time 25797593221 ps
CPU time 20.75 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 06:47:26 PM PDT 24
Peak memory 196980 kb
Host smart-485b1271-191c-4944-a8ba-555cf4395211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728884685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3728884685
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3722985280
Short name T219
Test name
Test status
Simulation time 456758198 ps
CPU time 1.03 seconds
Started Jul 14 06:47:07 PM PDT 24
Finished Jul 14 06:47:09 PM PDT 24
Peak memory 191932 kb
Host smart-43e9946f-19db-4706-8e74-892e48c13307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722985280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3722985280
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.421066010
Short name T40
Test name
Test status
Simulation time 15823091652 ps
CPU time 12.17 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 06:47:17 PM PDT 24
Peak memory 192004 kb
Host smart-1c64c72b-fc34-4c64-913d-a24b38078a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421066010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.421066010
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2666856341
Short name T249
Test name
Test status
Simulation time 563109666 ps
CPU time 0.68 seconds
Started Jul 14 06:47:08 PM PDT 24
Finished Jul 14 06:47:10 PM PDT 24
Peak memory 191900 kb
Host smart-f2636f42-9d77-4f11-a38e-abd7db9210b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666856341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2666856341
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2966494260
Short name T206
Test name
Test status
Simulation time 17804863904 ps
CPU time 15.16 seconds
Started Jul 14 06:47:11 PM PDT 24
Finished Jul 14 06:47:27 PM PDT 24
Peak memory 196968 kb
Host smart-d2ebe754-c95c-4475-b49f-0d7837747ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966494260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2966494260
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.4251440851
Short name T270
Test name
Test status
Simulation time 549569107 ps
CPU time 0.81 seconds
Started Jul 14 06:47:08 PM PDT 24
Finished Jul 14 06:47:10 PM PDT 24
Peak memory 191904 kb
Host smart-054d3b30-9924-420a-8370-423b149f76d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251440851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.4251440851
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.700534079
Short name T221
Test name
Test status
Simulation time 10539344229 ps
CPU time 4.22 seconds
Started Jul 14 06:47:11 PM PDT 24
Finished Jul 14 06:47:16 PM PDT 24
Peak memory 197000 kb
Host smart-4d948c6c-4465-4eab-b451-b68cf82e4f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700534079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.700534079
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2340053991
Short name T266
Test name
Test status
Simulation time 612164031 ps
CPU time 0.81 seconds
Started Jul 14 06:47:16 PM PDT 24
Finished Jul 14 06:47:17 PM PDT 24
Peak memory 191908 kb
Host smart-489b0a4e-6990-4e6a-9998-b61e795bd93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340053991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2340053991
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2020908739
Short name T247
Test name
Test status
Simulation time 12175988824 ps
CPU time 6.3 seconds
Started Jul 14 06:47:11 PM PDT 24
Finished Jul 14 06:47:18 PM PDT 24
Peak memory 191992 kb
Host smart-86cea794-dd2b-4280-85dd-793a932698ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020908739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2020908739
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2155661634
Short name T245
Test name
Test status
Simulation time 538151499 ps
CPU time 1.02 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:47:25 PM PDT 24
Peak memory 196672 kb
Host smart-eb90ccca-9ccc-45a5-a373-e6a0ed6255d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155661634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2155661634
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2886628854
Short name T242
Test name
Test status
Simulation time 38389310491 ps
CPU time 8.18 seconds
Started Jul 14 06:47:18 PM PDT 24
Finished Jul 14 06:47:27 PM PDT 24
Peak memory 191980 kb
Host smart-3ff70082-3eff-4370-96bf-9898652e9d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886628854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2886628854
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3292870182
Short name T25
Test name
Test status
Simulation time 494634491 ps
CPU time 0.66 seconds
Started Jul 14 06:47:08 PM PDT 24
Finished Jul 14 06:47:10 PM PDT 24
Peak memory 191924 kb
Host smart-30b56a23-34f3-4184-abe5-0a87cc0fd7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292870182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3292870182
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3436811853
Short name T250
Test name
Test status
Simulation time 24644576655 ps
CPU time 36.88 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:48:04 PM PDT 24
Peak memory 196984 kb
Host smart-f488b086-f0f9-4feb-9c3c-8e7bab61f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436811853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3436811853
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2504000125
Short name T275
Test name
Test status
Simulation time 439226684 ps
CPU time 0.76 seconds
Started Jul 14 06:47:06 PM PDT 24
Finished Jul 14 06:47:08 PM PDT 24
Peak memory 191916 kb
Host smart-708ae336-5074-4de1-9267-d04bd5684d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504000125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2504000125
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.152644442
Short name T257
Test name
Test status
Simulation time 11315918774 ps
CPU time 1.46 seconds
Started Jul 14 06:47:10 PM PDT 24
Finished Jul 14 06:47:12 PM PDT 24
Peak memory 191928 kb
Host smart-1df29ede-40ba-401f-916e-081174a8e2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152644442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.152644442
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1490729438
Short name T231
Test name
Test status
Simulation time 647190535 ps
CPU time 0.66 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:47:31 PM PDT 24
Peak memory 191916 kb
Host smart-ad934c93-5661-4117-ab39-ea9b825f68c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490729438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1490729438
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2021549939
Short name T255
Test name
Test status
Simulation time 11598579519 ps
CPU time 5.07 seconds
Started Jul 14 06:47:09 PM PDT 24
Finished Jul 14 06:47:15 PM PDT 24
Peak memory 196936 kb
Host smart-fe9680d6-f1a2-441d-85f9-e43929324c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021549939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2021549939
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.921041356
Short name T271
Test name
Test status
Simulation time 648214776 ps
CPU time 0.8 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:47:24 PM PDT 24
Peak memory 196700 kb
Host smart-38c5fbf2-9d1d-4b0e-a826-f1bee7666297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921041356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.921041356
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1706618338
Short name T272
Test name
Test status
Simulation time 15822090095 ps
CPU time 3.9 seconds
Started Jul 14 06:47:11 PM PDT 24
Finished Jul 14 06:47:16 PM PDT 24
Peak memory 191932 kb
Host smart-1e0b663d-9511-4bf2-a2e2-ac954772b517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706618338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1706618338
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3226019874
Short name T230
Test name
Test status
Simulation time 412067178 ps
CPU time 0.82 seconds
Started Jul 14 06:47:18 PM PDT 24
Finished Jul 14 06:47:20 PM PDT 24
Peak memory 191920 kb
Host smart-7c29912b-9858-4885-8804-dcfd6dd48e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226019874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3226019874
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2818936546
Short name T248
Test name
Test status
Simulation time 53812700798 ps
CPU time 42.5 seconds
Started Jul 14 06:46:52 PM PDT 24
Finished Jul 14 06:47:35 PM PDT 24
Peak memory 191980 kb
Host smart-704562c6-79e6-4b56-bc88-00ceb18b46dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818936546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2818936546
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2887100785
Short name T11
Test name
Test status
Simulation time 4015882152 ps
CPU time 6.11 seconds
Started Jul 14 06:47:06 PM PDT 24
Finished Jul 14 06:47:14 PM PDT 24
Peak memory 215320 kb
Host smart-71874d63-6a7f-460e-9d2f-9d5ccb05f57b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887100785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2887100785
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.4136193419
Short name T280
Test name
Test status
Simulation time 430968614 ps
CPU time 0.72 seconds
Started Jul 14 06:46:39 PM PDT 24
Finished Jul 14 06:46:41 PM PDT 24
Peak memory 191820 kb
Host smart-6bd35663-4b27-42e1-923d-00f7ac10bc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136193419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.4136193419
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3228402189
Short name T269
Test name
Test status
Simulation time 5980960901 ps
CPU time 1.58 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:47:25 PM PDT 24
Peak memory 191980 kb
Host smart-afa35b9e-7a89-4a95-a58b-643f6fed8988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228402189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3228402189
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.774157242
Short name T252
Test name
Test status
Simulation time 613301822 ps
CPU time 1.31 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:47:21 PM PDT 24
Peak memory 191792 kb
Host smart-a82b0553-56f7-4531-a7d9-f4dcf85f251a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774157242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.774157242
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3937430096
Short name T223
Test name
Test status
Simulation time 12734294332 ps
CPU time 8.08 seconds
Started Jul 14 06:47:14 PM PDT 24
Finished Jul 14 06:47:22 PM PDT 24
Peak memory 191976 kb
Host smart-dda6afc1-811d-4a8a-932b-e0e556339caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937430096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3937430096
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.194582321
Short name T263
Test name
Test status
Simulation time 361788233 ps
CPU time 0.67 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:47:21 PM PDT 24
Peak memory 191864 kb
Host smart-cd986876-22d7-4caa-869a-fd6b19f1369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194582321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.194582321
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.453304052
Short name T194
Test name
Test status
Simulation time 19316056168 ps
CPU time 25.93 seconds
Started Jul 14 06:47:40 PM PDT 24
Finished Jul 14 06:48:07 PM PDT 24
Peak memory 191756 kb
Host smart-96ab04f1-622a-426a-ab82-908b1e7f8a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453304052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.453304052
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3494062386
Short name T200
Test name
Test status
Simulation time 495538756 ps
CPU time 1.21 seconds
Started Jul 14 06:47:27 PM PDT 24
Finished Jul 14 06:47:32 PM PDT 24
Peak memory 191920 kb
Host smart-41b70e37-f850-452f-b953-bc45f82ddb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494062386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3494062386
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2731214732
Short name T240
Test name
Test status
Simulation time 42195862777 ps
CPU time 41.2 seconds
Started Jul 14 06:47:28 PM PDT 24
Finished Jul 14 06:48:15 PM PDT 24
Peak memory 192016 kb
Host smart-b7eecc96-82ce-46c5-8471-3bf94281faf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731214732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2731214732
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1086319480
Short name T279
Test name
Test status
Simulation time 562649037 ps
CPU time 1.45 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:47:24 PM PDT 24
Peak memory 191932 kb
Host smart-be155728-476f-42a7-bca3-7be8fc4ce38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086319480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1086319480
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.629500884
Short name T251
Test name
Test status
Simulation time 27888297503 ps
CPU time 19.06 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:47:40 PM PDT 24
Peak memory 191972 kb
Host smart-c0845e5b-14de-40e4-8d8d-ce2f92a93478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629500884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.629500884
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3458278607
Short name T207
Test name
Test status
Simulation time 460561373 ps
CPU time 0.73 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:47:21 PM PDT 24
Peak memory 191924 kb
Host smart-c10f0b0d-d26f-4945-b9b8-79b7700a1e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458278607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3458278607
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4003424841
Short name T228
Test name
Test status
Simulation time 2303494759 ps
CPU time 2.06 seconds
Started Jul 14 06:47:15 PM PDT 24
Finished Jul 14 06:47:18 PM PDT 24
Peak memory 191980 kb
Host smart-1587ea4a-9ed3-4620-8de4-bfba299f88cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003424841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4003424841
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3460230882
Short name T227
Test name
Test status
Simulation time 575346463 ps
CPU time 0.7 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:47:26 PM PDT 24
Peak memory 191844 kb
Host smart-930a94f2-7cc9-4582-b31c-3f03a7de1d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460230882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3460230882
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.690458322
Short name T281
Test name
Test status
Simulation time 21078457498 ps
CPU time 4.58 seconds
Started Jul 14 06:47:23 PM PDT 24
Finished Jul 14 06:47:31 PM PDT 24
Peak memory 191980 kb
Host smart-0bcd6bd7-23c5-4d7a-baeb-d632a96a6a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690458322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.690458322
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2791631823
Short name T203
Test name
Test status
Simulation time 372988536 ps
CPU time 1.06 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:47:29 PM PDT 24
Peak memory 191920 kb
Host smart-92ea4114-6dbc-4097-b9f2-1767a09b66be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791631823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2791631823
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3596393577
Short name T197
Test name
Test status
Simulation time 40107867023 ps
CPU time 27.01 seconds
Started Jul 14 06:47:18 PM PDT 24
Finished Jul 14 06:47:46 PM PDT 24
Peak memory 191976 kb
Host smart-1bc4832e-6fd9-4429-9691-a5eb3f706339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596393577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3596393577
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1876536920
Short name T216
Test name
Test status
Simulation time 591548209 ps
CPU time 0.81 seconds
Started Jul 14 06:47:16 PM PDT 24
Finished Jul 14 06:47:17 PM PDT 24
Peak memory 196724 kb
Host smart-faa48a4f-0d5e-43bb-8aa8-48a6b819d5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876536920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1876536920
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_jump.370887874
Short name T150
Test name
Test status
Simulation time 562984707 ps
CPU time 1.46 seconds
Started Jul 14 06:47:18 PM PDT 24
Finished Jul 14 06:47:26 PM PDT 24
Peak memory 196756 kb
Host smart-b5fc0fad-59dc-43a3-a3e6-70b82ec00aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370887874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.370887874
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1086736407
Short name T195
Test name
Test status
Simulation time 34539445317 ps
CPU time 4.69 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:47:35 PM PDT 24
Peak memory 191756 kb
Host smart-711460fd-91c5-4da9-bb36-b983577a859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086736407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1086736407
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3224504227
Short name T276
Test name
Test status
Simulation time 403338151 ps
CPU time 0.75 seconds
Started Jul 14 06:47:11 PM PDT 24
Finished Jul 14 06:47:13 PM PDT 24
Peak memory 196740 kb
Host smart-3d385af6-f686-47ef-bbe3-f06887432560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224504227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3224504227
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1483414095
Short name T209
Test name
Test status
Simulation time 33132568802 ps
CPU time 13.44 seconds
Started Jul 14 06:47:39 PM PDT 24
Finished Jul 14 06:47:53 PM PDT 24
Peak memory 196756 kb
Host smart-1851d5a2-b271-40fe-9c69-d6ad07d7545e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483414095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1483414095
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.215231666
Short name T212
Test name
Test status
Simulation time 557828943 ps
CPU time 0.7 seconds
Started Jul 14 06:47:16 PM PDT 24
Finished Jul 14 06:47:18 PM PDT 24
Peak memory 196712 kb
Host smart-80a79c7f-17e6-4cf0-a7c1-5adcecdc0a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215231666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.215231666
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1756189275
Short name T253
Test name
Test status
Simulation time 10902817916 ps
CPU time 10.88 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 06:47:17 PM PDT 24
Peak memory 196964 kb
Host smart-427ffcf3-89d7-4f91-8d1e-a097fb07f728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756189275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1756189275
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2605468267
Short name T23
Test name
Test status
Simulation time 8284833713 ps
CPU time 13.93 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 06:47:18 PM PDT 24
Peak memory 215788 kb
Host smart-0d854c4c-be67-43cc-933d-3d98cb04272b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605468267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2605468267
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2100651287
Short name T213
Test name
Test status
Simulation time 620014223 ps
CPU time 0.8 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 06:47:05 PM PDT 24
Peak memory 191908 kb
Host smart-62f522a9-7589-4a0e-ba35-f7099b0b233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100651287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2100651287
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2064448586
Short name T224
Test name
Test status
Simulation time 35439624225 ps
CPU time 26.4 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:47:54 PM PDT 24
Peak memory 191968 kb
Host smart-bad9c99e-6f3c-466f-ae7f-2694c070b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064448586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2064448586
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.839686982
Short name T264
Test name
Test status
Simulation time 543972899 ps
CPU time 0.77 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:47:31 PM PDT 24
Peak memory 196168 kb
Host smart-f215ca16-56ac-41ca-bd6f-f42133de7fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839686982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.839686982
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.935679414
Short name T225
Test name
Test status
Simulation time 49254354408 ps
CPU time 16.27 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:47:45 PM PDT 24
Peak memory 196752 kb
Host smart-04987ccd-c90f-4113-b5ef-cf3b721acaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935679414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.935679414
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1623140181
Short name T254
Test name
Test status
Simulation time 547455646 ps
CPU time 0.77 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:47:24 PM PDT 24
Peak memory 191912 kb
Host smart-c66b24ef-2a1c-4560-8d4b-21ba55de4564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623140181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1623140181
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3033279420
Short name T202
Test name
Test status
Simulation time 25798937453 ps
CPU time 18.62 seconds
Started Jul 14 06:47:20 PM PDT 24
Finished Jul 14 06:47:40 PM PDT 24
Peak memory 192000 kb
Host smart-b5f7de02-2679-4b6a-811d-8dce0bc03dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033279420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3033279420
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1954065836
Short name T232
Test name
Test status
Simulation time 526315862 ps
CPU time 0.76 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:47:30 PM PDT 24
Peak memory 191916 kb
Host smart-d591e87d-56d6-4f9a-8398-8262ce931eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954065836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1954065836
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.484265623
Short name T235
Test name
Test status
Simulation time 6254721337 ps
CPU time 5.26 seconds
Started Jul 14 06:47:24 PM PDT 24
Finished Jul 14 06:47:34 PM PDT 24
Peak memory 191952 kb
Host smart-98228832-8e4a-4e3e-88e6-be0e073cdcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484265623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.484265623
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1202581993
Short name T199
Test name
Test status
Simulation time 558690876 ps
CPU time 1.47 seconds
Started Jul 14 06:48:28 PM PDT 24
Finished Jul 14 06:48:31 PM PDT 24
Peak memory 189748 kb
Host smart-fe49a1e8-8d00-4792-a5b9-2088801c0de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202581993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1202581993
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1424444756
Short name T237
Test name
Test status
Simulation time 22343753180 ps
CPU time 8.96 seconds
Started Jul 14 06:47:14 PM PDT 24
Finished Jul 14 06:47:24 PM PDT 24
Peak memory 191992 kb
Host smart-ddefae31-4126-406b-a473-0ec98e3c1550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424444756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1424444756
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.577724914
Short name T6
Test name
Test status
Simulation time 496508288 ps
CPU time 0.73 seconds
Started Jul 14 06:47:43 PM PDT 24
Finished Jul 14 06:47:45 PM PDT 24
Peak memory 191692 kb
Host smart-291ae455-a7cb-4106-870f-5d1d5215ad78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577724914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.577724914
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3689329544
Short name T211
Test name
Test status
Simulation time 22493712581 ps
CPU time 9.08 seconds
Started Jul 14 06:47:20 PM PDT 24
Finished Jul 14 06:47:30 PM PDT 24
Peak memory 191928 kb
Host smart-f0cdd228-c478-4159-9306-4046bf447f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689329544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3689329544
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2033426723
Short name T1
Test name
Test status
Simulation time 409479195 ps
CPU time 0.98 seconds
Started Jul 14 06:47:38 PM PDT 24
Finished Jul 14 06:47:40 PM PDT 24
Peak memory 191692 kb
Host smart-3d362b60-3e43-4aa4-aae5-af40367de0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033426723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2033426723
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2927185690
Short name T220
Test name
Test status
Simulation time 38818212148 ps
CPU time 15.1 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:47:39 PM PDT 24
Peak memory 191968 kb
Host smart-84a10150-f54d-4b65-8199-b8bb2b32f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927185690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2927185690
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1267324524
Short name T59
Test name
Test status
Simulation time 415428571 ps
CPU time 0.84 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:47:30 PM PDT 24
Peak memory 191924 kb
Host smart-769384a0-4251-48be-a12f-069f99cf24af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267324524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1267324524
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3727845006
Short name T15
Test name
Test status
Simulation time 9558264382 ps
CPU time 13.09 seconds
Started Jul 14 06:47:38 PM PDT 24
Finished Jul 14 06:47:52 PM PDT 24
Peak memory 197012 kb
Host smart-b5e7e6c1-6515-4b1a-b25d-cb71ba24f84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727845006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3727845006
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2887930007
Short name T273
Test name
Test status
Simulation time 579153432 ps
CPU time 1.43 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:47:31 PM PDT 24
Peak memory 196712 kb
Host smart-e8293445-0592-43a5-a666-3e09782b9121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887930007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2887930007
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.4269933793
Short name T244
Test name
Test status
Simulation time 37440738922 ps
CPU time 13.29 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:47:42 PM PDT 24
Peak memory 191972 kb
Host smart-5a479fc1-3e63-4241-a75b-833a6bc3e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269933793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.4269933793
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1887683483
Short name T210
Test name
Test status
Simulation time 494406438 ps
CPU time 1.15 seconds
Started Jul 14 06:47:20 PM PDT 24
Finished Jul 14 06:47:23 PM PDT 24
Peak memory 196776 kb
Host smart-f5aeca8a-e5cd-4a03-969b-5590bc9e7dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887683483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1887683483
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2814688772
Short name T14
Test name
Test status
Simulation time 22635248191 ps
CPU time 6.02 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:47:36 PM PDT 24
Peak memory 191992 kb
Host smart-c138aa2b-b3e9-41f6-b68b-424111563cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814688772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2814688772
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2994159098
Short name T268
Test name
Test status
Simulation time 420483996 ps
CPU time 1.17 seconds
Started Jul 14 06:47:27 PM PDT 24
Finished Jul 14 06:47:32 PM PDT 24
Peak memory 196732 kb
Host smart-4f6710bf-926d-435d-9901-09df9a2a0371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994159098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2994159098
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3488463852
Short name T277
Test name
Test status
Simulation time 476405033 ps
CPU time 0.87 seconds
Started Jul 14 06:47:11 PM PDT 24
Finished Jul 14 06:47:13 PM PDT 24
Peak memory 191896 kb
Host smart-c3fe00d6-8a86-4a18-869f-d7d0bdcad1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488463852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3488463852
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.395519366
Short name T18
Test name
Test status
Simulation time 7100908199 ps
CPU time 5.93 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 06:47:11 PM PDT 24
Peak memory 215924 kb
Host smart-ddc2d90f-2662-4890-93e5-f70b04cb2eb0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395519366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.395519366
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2337274098
Short name T4
Test name
Test status
Simulation time 475998948 ps
CPU time 0.78 seconds
Started Jul 14 06:47:04 PM PDT 24
Finished Jul 14 06:47:06 PM PDT 24
Peak memory 191920 kb
Host smart-73176b94-7a44-471d-9887-b4499820e945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337274098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2337274098
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.466634526
Short name T184
Test name
Test status
Simulation time 410994756 ps
CPU time 0.83 seconds
Started Jul 14 06:47:19 PM PDT 24
Finished Jul 14 06:47:21 PM PDT 24
Peak memory 196656 kb
Host smart-de36e764-a5db-483f-9eb2-25e9c5225536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466634526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.466634526
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3887387702
Short name T282
Test name
Test status
Simulation time 51094753452 ps
CPU time 6.06 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:47:35 PM PDT 24
Peak memory 191972 kb
Host smart-bedb34c8-f763-4c6a-9eb8-66470b999118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887387702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3887387702
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3668405172
Short name T214
Test name
Test status
Simulation time 400519568 ps
CPU time 0.74 seconds
Started Jul 14 06:47:23 PM PDT 24
Finished Jul 14 06:47:27 PM PDT 24
Peak memory 191936 kb
Host smart-e87aeab6-3042-4e94-a36e-937617e44b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668405172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3668405172
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.742489866
Short name T278
Test name
Test status
Simulation time 35075857129 ps
CPU time 13.41 seconds
Started Jul 14 06:47:20 PM PDT 24
Finished Jul 14 06:47:35 PM PDT 24
Peak memory 191920 kb
Host smart-deb46b9f-ddb2-4304-87ee-ae454378c447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742489866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.742489866
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.83303240
Short name T233
Test name
Test status
Simulation time 414726990 ps
CPU time 1.2 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:47:30 PM PDT 24
Peak memory 191916 kb
Host smart-280355fb-6887-4472-a394-945e2a68bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83303240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.83303240
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_jump.4219687301
Short name T185
Test name
Test status
Simulation time 596356473 ps
CPU time 1.34 seconds
Started Jul 14 06:47:23 PM PDT 24
Finished Jul 14 06:47:35 PM PDT 24
Peak memory 196704 kb
Host smart-eecac2a7-498b-45d4-8e99-970ff63ffb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219687301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.4219687301
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1537893474
Short name T229
Test name
Test status
Simulation time 55134748066 ps
CPU time 78.32 seconds
Started Jul 14 06:47:25 PM PDT 24
Finished Jul 14 06:48:47 PM PDT 24
Peak memory 196988 kb
Host smart-b6cebef9-80f1-4420-b9bf-9133e5d20494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537893474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1537893474
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2184674908
Short name T218
Test name
Test status
Simulation time 457820781 ps
CPU time 1.15 seconds
Started Jul 14 06:47:27 PM PDT 24
Finished Jul 14 06:47:32 PM PDT 24
Peak memory 191932 kb
Host smart-c0f3de00-011d-440f-a043-fdedc5b55144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184674908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2184674908
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2577259057
Short name T274
Test name
Test status
Simulation time 33235555133 ps
CPU time 8.93 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:47:33 PM PDT 24
Peak memory 196864 kb
Host smart-887034ed-1add-4802-9d69-5bc50db062e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577259057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2577259057
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3540073267
Short name T208
Test name
Test status
Simulation time 373625921 ps
CPU time 1.07 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:47:32 PM PDT 24
Peak memory 191920 kb
Host smart-439e7046-d24f-4b8d-8fb5-7a835a2bca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540073267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3540073267
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1031366475
Short name T193
Test name
Test status
Simulation time 25327056940 ps
CPU time 30.65 seconds
Started Jul 14 06:47:23 PM PDT 24
Finished Jul 14 06:47:58 PM PDT 24
Peak memory 191980 kb
Host smart-414c3784-d19c-42a9-bfd0-b79fec87a96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031366475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1031366475
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3393212042
Short name T215
Test name
Test status
Simulation time 489420447 ps
CPU time 0.87 seconds
Started Jul 14 06:47:26 PM PDT 24
Finished Jul 14 06:47:31 PM PDT 24
Peak memory 191920 kb
Host smart-4553859a-b3bc-47ee-bf64-4690edb65638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393212042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3393212042
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1909638053
Short name T196
Test name
Test status
Simulation time 37607360642 ps
CPU time 21.1 seconds
Started Jul 14 06:47:21 PM PDT 24
Finished Jul 14 06:47:44 PM PDT 24
Peak memory 191980 kb
Host smart-b56cd7fd-c768-4584-bafe-7f3f24241d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909638053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1909638053
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.98133179
Short name T239
Test name
Test status
Simulation time 553791542 ps
CPU time 0.93 seconds
Started Jul 14 06:49:11 PM PDT 24
Finished Jul 14 06:49:13 PM PDT 24
Peak memory 191632 kb
Host smart-8584c75a-04a8-483c-98bb-52fb1d6af6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98133179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.98133179
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.4217741240
Short name T39
Test name
Test status
Simulation time 46817758102 ps
CPU time 17.99 seconds
Started Jul 14 06:48:28 PM PDT 24
Finished Jul 14 06:48:47 PM PDT 24
Peak memory 189684 kb
Host smart-c3516e49-a486-4920-8bfa-a2951b0b154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217741240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4217741240
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1143176824
Short name T258
Test name
Test status
Simulation time 416675745 ps
CPU time 1.27 seconds
Started Jul 14 06:49:00 PM PDT 24
Finished Jul 14 06:49:04 PM PDT 24
Peak memory 190240 kb
Host smart-af31a878-769e-439e-a41f-79644fcd2a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143176824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1143176824
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.4276575061
Short name T256
Test name
Test status
Simulation time 4125456560 ps
CPU time 2.25 seconds
Started Jul 14 06:47:22 PM PDT 24
Finished Jul 14 06:47:28 PM PDT 24
Peak memory 183760 kb
Host smart-f3c602c8-5edd-441b-b284-67f69c31f998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276575061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.4276575061
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2474635907
Short name T201
Test name
Test status
Simulation time 15499770537 ps
CPU time 20.67 seconds
Started Jul 14 06:47:29 PM PDT 24
Finished Jul 14 06:47:52 PM PDT 24
Peak memory 196868 kb
Host smart-d65091c6-bea4-4f60-b496-eb274aef0205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474635907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2474635907
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4000326259
Short name T9
Test name
Test status
Simulation time 466535009 ps
CPU time 0.71 seconds
Started Jul 14 06:47:43 PM PDT 24
Finished Jul 14 06:47:45 PM PDT 24
Peak memory 191932 kb
Host smart-80b98513-92cd-43bd-8b53-a8ee6b12b447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000326259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4000326259
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1468262482
Short name T262
Test name
Test status
Simulation time 18295445659 ps
CPU time 21.05 seconds
Started Jul 14 06:47:36 PM PDT 24
Finished Jul 14 06:47:57 PM PDT 24
Peak memory 196976 kb
Host smart-0a45150b-b9ff-4f2c-90d8-edcb16e1fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468262482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1468262482
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2536741010
Short name T259
Test name
Test status
Simulation time 488618637 ps
CPU time 1.35 seconds
Started Jul 14 06:47:33 PM PDT 24
Finished Jul 14 06:47:35 PM PDT 24
Peak memory 196680 kb
Host smart-3ebd8855-6954-4c0c-befa-b90577b7e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536741010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2536741010
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1183723033
Short name T151
Test name
Test status
Simulation time 541935724 ps
CPU time 1.52 seconds
Started Jul 14 06:47:29 PM PDT 24
Finished Jul 14 06:47:33 PM PDT 24
Peak memory 196764 kb
Host smart-12155368-943b-4c0e-9434-539f3cc64889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183723033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1183723033
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2745138006
Short name T236
Test name
Test status
Simulation time 6494756102 ps
CPU time 9.69 seconds
Started Jul 14 06:47:43 PM PDT 24
Finished Jul 14 06:47:53 PM PDT 24
Peak memory 191996 kb
Host smart-a7244b0d-5465-40b4-a7ed-c68a1721f734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745138006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2745138006
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1211035242
Short name T234
Test name
Test status
Simulation time 435136745 ps
CPU time 1.3 seconds
Started Jul 14 06:47:55 PM PDT 24
Finished Jul 14 06:47:57 PM PDT 24
Peak memory 191908 kb
Host smart-94e29fe4-6d60-45c4-8808-b90dd3ead83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211035242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1211035242
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1452864320
Short name T205
Test name
Test status
Simulation time 11901997953 ps
CPU time 18.8 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 06:47:26 PM PDT 24
Peak memory 191968 kb
Host smart-74e145b7-ba4c-4250-a06b-5871efc60b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452864320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1452864320
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2984898348
Short name T16
Test name
Test status
Simulation time 627603451 ps
CPU time 0.85 seconds
Started Jul 14 06:47:01 PM PDT 24
Finished Jul 14 06:47:03 PM PDT 24
Peak memory 191900 kb
Host smart-8715f572-2ddb-41b0-84e3-65810be7f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984898348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2984898348
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3535174185
Short name T217
Test name
Test status
Simulation time 13407143912 ps
CPU time 19.43 seconds
Started Jul 14 06:47:09 PM PDT 24
Finished Jul 14 06:47:30 PM PDT 24
Peak memory 191964 kb
Host smart-8bda2303-7e68-4427-b19f-dd57814127c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535174185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3535174185
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1271428545
Short name T243
Test name
Test status
Simulation time 414051251 ps
CPU time 0.65 seconds
Started Jul 14 06:47:05 PM PDT 24
Finished Jul 14 06:47:07 PM PDT 24
Peak memory 196752 kb
Host smart-27909f82-f98f-4a44-8ff5-48fff0cf940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271428545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1271428545
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3558369305
Short name T241
Test name
Test status
Simulation time 35915647772 ps
CPU time 24.27 seconds
Started Jul 14 06:46:58 PM PDT 24
Finished Jul 14 06:47:22 PM PDT 24
Peak memory 191972 kb
Host smart-4b11d22f-adf0-4713-814a-8ad676fcbe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558369305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3558369305
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2690495202
Short name T261
Test name
Test status
Simulation time 584353732 ps
CPU time 1.38 seconds
Started Jul 14 06:47:06 PM PDT 24
Finished Jul 14 06:47:09 PM PDT 24
Peak memory 191884 kb
Host smart-e4e21d5d-2411-4a4e-8e7d-7fd7b36a65dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690495202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2690495202
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2108942461
Short name T246
Test name
Test status
Simulation time 7958263009 ps
CPU time 10.94 seconds
Started Jul 14 06:47:07 PM PDT 24
Finished Jul 14 06:47:19 PM PDT 24
Peak memory 196960 kb
Host smart-43e0dc8b-5d61-4d5c-995f-30ece3084ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108942461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2108942461
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1931500272
Short name T260
Test name
Test status
Simulation time 427454083 ps
CPU time 0.66 seconds
Started Jul 14 06:47:07 PM PDT 24
Finished Jul 14 06:47:09 PM PDT 24
Peak memory 191820 kb
Host smart-9ffcd964-4cc1-4e2a-afb0-c8f28bff673c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931500272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1931500272
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2922845167
Short name T222
Test name
Test status
Simulation time 39259121439 ps
CPU time 5.68 seconds
Started Jul 14 06:47:06 PM PDT 24
Finished Jul 14 06:47:13 PM PDT 24
Peak memory 196980 kb
Host smart-836d1337-b6c9-4ba6-bda0-45324042e9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922845167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2922845167
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2592604134
Short name T267
Test name
Test status
Simulation time 415208004 ps
CPU time 1.13 seconds
Started Jul 14 06:47:12 PM PDT 24
Finished Jul 14 06:47:14 PM PDT 24
Peak memory 191832 kb
Host smart-7fe6c5b7-8518-4ae7-bf52-1e9398ddcfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592604134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2592604134
Directory /workspace/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%