Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 26396 1 T1 239 T2 419 T4 234
bark[1] 724 1 T2 21 T85 79 T187 14
bark[2] 923 1 T2 26 T98 45 T86 246
bark[3] 231 1 T102 38 T36 21 T98 21
bark[4] 570 1 T9 45 T34 135 T41 14
bark[5] 692 1 T1 21 T11 258 T37 21
bark[6] 197 1 T2 26 T4 26 T40 21
bark[7] 584 1 T13 30 T14 21 T25 21
bark[8] 645 1 T1 21 T9 21 T21 14
bark[9] 508 1 T1 21 T9 21 T12 338
bark[10] 150 1 T34 43 T107 14 T159 30
bark[11] 355 1 T9 26 T40 21 T114 14
bark[12] 1173 1 T1 21 T12 162 T102 42
bark[13] 557 1 T3 14 T11 21 T102 14
bark[14] 242 1 T25 42 T103 40 T52 82
bark[15] 484 1 T4 28 T7 59 T11 21
bark[16] 533 1 T4 21 T169 125 T36 148
bark[17] 933 1 T4 26 T12 21 T125 21
bark[18] 522 1 T2 21 T6 14 T39 14
bark[19] 570 1 T13 38 T85 21 T103 45
bark[20] 284 1 T34 21 T136 21 T169 43
bark[21] 856 1 T12 136 T36 91 T86 21
bark[22] 716 1 T13 39 T14 30 T40 21
bark[23] 254 1 T11 47 T148 26 T136 21
bark[24] 250 1 T22 14 T88 116 T163 23
bark[25] 260 1 T11 21 T98 26 T143 21
bark[26] 708 1 T11 171 T86 7 T87 283
bark[27] 755 1 T1 26 T34 210 T90 14
bark[28] 657 1 T112 14 T37 43 T85 26
bark[29] 762 1 T35 39 T40 68 T102 89
bark[30] 487 1 T7 21 T9 21 T11 21
bark[31] 435 1 T2 206 T11 87 T98 21
bark_0 4355 1 T1 7 T2 94 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 26240 1 T1 238 T2 410 T4 232
bite[1] 971 1 T34 42 T169 43 T25 42
bite[2] 133 1 T2 26 T38 21 T24 13
bite[3] 481 1 T1 21 T2 26 T4 27
bite[4] 470 1 T4 25 T9 21 T36 147
bite[5] 422 1 T102 21 T103 21 T52 80
bite[6] 405 1 T2 21 T11 132 T35 39
bite[7] 503 1 T1 21 T4 25 T40 21
bite[8] 489 1 T14 21 T40 38 T87 152
bite[9] 1011 1 T7 38 T12 343 T13 30
bite[10] 612 1 T34 209 T108 21 T95 21
bite[11] 893 1 T1 26 T36 21 T87 251
bite[12] 175 1 T37 42 T85 78 T88 21
bite[13] 168 1 T90 13 T21 13 T119 13
bite[14] 189 1 T186 13 T99 26 T121 23
bite[15] 238 1 T37 21 T86 6 T63 190
bite[16] 302 1 T11 21 T37 26 T86 21
bite[17] 1323 1 T39 13 T136 21 T36 251
bite[18] 467 1 T14 30 T125 21 T152 26
bite[19] 949 1 T3 13 T11 257 T40 21
bite[20] 493 1 T7 21 T40 30 T156 13
bite[21] 506 1 T6 13 T9 47 T11 21
bite[22] 145 1 T40 21 T38 21 T114 13
bite[23] 514 1 T102 21 T98 26 T85 200
bite[24] 754 1 T4 21 T9 21 T13 39
bite[25] 1041 1 T2 205 T11 21 T12 163
bite[26] 1295 1 T9 44 T11 170 T125 21
bite[27] 389 1 T148 26 T102 30 T37 63
bite[28] 133 1 T2 21 T11 21 T152 21
bite[29] 199 1 T1 21 T108 21 T95 21
bite[30] 195 1 T12 161 T95 21 T161 13
bite[31] 846 1 T1 21 T98 21 T157 21
bite_0 4817 1 T1 8 T2 104 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 41386 1 T1 338 T2 593 T3 21
auto[1] 6382 1 T1 18 T2 220 T4 42


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1426 1 T9 47 T12 49 T35 19
prescale[1] 821 1 T4 64 T42 9 T169 87
prescale[2] 1084 1 T2 64 T4 66 T8 9
prescale[3] 957 1 T2 21 T34 129 T35 39
prescale[4] 397 1 T2 40 T196 9 T38 19
prescale[5] 770 1 T1 54 T9 40 T11 102
prescale[6] 422 1 T9 19 T11 26 T12 2
prescale[7] 820 1 T7 19 T9 63 T12 40
prescale[8] 797 1 T2 21 T11 2 T40 19
prescale[9] 859 1 T11 92 T125 40 T36 69
prescale[10] 609 1 T9 21 T11 45 T12 9
prescale[11] 566 1 T1 36 T2 118 T11 2
prescale[12] 1008 1 T2 51 T12 85 T13 23
prescale[13] 812 1 T2 62 T7 24 T12 19
prescale[14] 497 1 T1 49 T9 2 T11 28
prescale[15] 810 1 T4 2 T9 19 T12 100
prescale[16] 856 1 T148 19 T102 19 T36 62
prescale[17] 691 1 T2 26 T11 2 T34 2
prescale[18] 834 1 T11 53 T12 95 T37 9
prescale[19] 480 1 T2 62 T172 2 T85 26
prescale[20] 669 1 T2 19 T12 2 T40 19
prescale[21] 719 1 T2 2 T4 2 T9 19
prescale[22] 762 1 T12 21 T197 9 T38 19
prescale[23] 895 1 T11 40 T14 62 T34 2
prescale[24] 609 1 T4 2 T9 19 T11 51
prescale[25] 811 1 T2 2 T9 19 T198 9
prescale[26] 704 1 T9 19 T35 19 T148 19
prescale[27] 340 1 T11 2 T102 19 T36 52
prescale[28] 612 1 T7 53 T11 65 T148 28
prescale[29] 643 1 T7 19 T9 2 T34 2
prescale[30] 678 1 T1 19 T2 2 T44 9
prescale[31] 763 1 T11 26 T136 19 T37 2
prescale_0 24047 1 T1 198 T2 323 T3 21


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35650 1 T1 187 T2 574 T3 21
auto[1] 12118 1 T1 169 T2 239 T4 80


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 47768 1 T1 356 T2 813 T3 21


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 27936 1 T1 215 T2 499 T3 1
wkup[1] 357 1 T7 42 T148 26 T102 15
wkup[2] 262 1 T2 21 T9 21 T169 21
wkup[3] 217 1 T36 21 T38 35 T159 21
wkup[4] 114 1 T52 21 T110 21 T83 30
wkup[5] 236 1 T102 21 T87 21 T150 21
wkup[6] 345 1 T7 21 T11 42 T36 21
wkup[7] 365 1 T11 30 T38 21 T85 21
wkup[8] 231 1 T169 26 T36 21 T22 15
wkup[9] 227 1 T2 29 T12 21 T13 21
wkup[10] 235 1 T11 21 T12 42 T25 21
wkup[11] 167 1 T1 21 T4 8 T11 21
wkup[12] 313 1 T11 21 T102 21 T38 21
wkup[13] 222 1 T1 26 T12 21 T90 15
wkup[14] 321 1 T2 21 T3 15 T39 15
wkup[15] 373 1 T34 21 T136 21 T38 21
wkup[16] 188 1 T2 21 T37 21 T20 30
wkup[17] 304 1 T2 21 T12 21 T139 30
wkup[18] 414 1 T11 42 T12 79 T102 60
wkup[19] 314 1 T4 21 T11 21 T12 26
wkup[20] 263 1 T9 21 T34 21 T36 21
wkup[21] 260 1 T34 42 T169 21 T172 21
wkup[22] 159 1 T36 72 T26 15 T156 15
wkup[23] 309 1 T4 21 T34 21 T35 21
wkup[24] 271 1 T11 21 T13 30 T38 21
wkup[25] 309 1 T12 21 T40 51 T20 21
wkup[26] 162 1 T169 21 T36 21 T85 42
wkup[27] 347 1 T2 49 T4 21 T34 21
wkup[28] 335 1 T12 21 T125 21 T85 8
wkup[29] 221 1 T11 65 T131 15 T85 21
wkup[30] 171 1 T87 21 T108 21 T52 42
wkup[31] 128 1 T36 50 T157 21 T180 15
wkup[32] 206 1 T169 21 T172 21 T137 29
wkup[33] 275 1 T12 21 T125 21 T98 21
wkup[34] 279 1 T4 36 T41 15 T36 47
wkup[35] 392 1 T1 26 T4 26 T11 21
wkup[36] 191 1 T11 21 T36 21 T86 24
wkup[37] 190 1 T12 8 T14 30 T37 8
wkup[38] 264 1 T14 21 T102 21 T152 26
wkup[39] 272 1 T11 21 T172 21 T86 21
wkup[40] 270 1 T9 21 T12 25 T151 30
wkup[41] 186 1 T4 30 T36 21 T98 30
wkup[42] 285 1 T9 21 T40 21 T185 15
wkup[43] 278 1 T125 21 T159 15 T150 39
wkup[44] 417 1 T11 35 T12 30 T85 21
wkup[45] 219 1 T34 21 T27 15 T52 30
wkup[46] 135 1 T108 21 T137 21 T45 21
wkup[47] 319 1 T11 15 T13 42 T35 39
wkup[48] 176 1 T1 21 T2 26 T159 21
wkup[49] 251 1 T103 21 T99 15 T121 46
wkup[50] 272 1 T4 21 T9 15 T159 51
wkup[51] 282 1 T11 21 T98 21 T159 71
wkup[52] 404 1 T1 21 T11 35 T37 21
wkup[53] 257 1 T11 21 T102 21 T169 21
wkup[54] 194 1 T9 21 T11 21 T36 26
wkup[55] 334 1 T9 26 T11 21 T36 21
wkup[56] 279 1 T34 21 T102 21 T37 21
wkup[57] 287 1 T40 21 T36 45 T152 26
wkup[58] 301 1 T2 26 T12 81 T40 21
wkup[59] 199 1 T6 15 T35 15 T36 21
wkup[60] 262 1 T1 21 T37 21 T85 26
wkup[61] 245 1 T2 26 T136 21 T36 21
wkup[62] 188 1 T9 21 T36 26 T85 21
wkup[63] 141 1 T85 21 T159 21 T99 21
wkup_0 3442 1 T1 5 T2 74 T3 5

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