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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.85 99.33 93.67 100.00 98.40 99.51 48.20


Total test records in report: 421
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T288 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1725593283 Jul 15 05:31:20 PM PDT 24 Jul 15 05:31:21 PM PDT 24 316355957 ps
T199 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2112388760 Jul 15 05:31:37 PM PDT 24 Jul 15 05:31:39 PM PDT 24 536811203 ps
T289 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.81375695 Jul 15 05:31:56 PM PDT 24 Jul 15 05:31:57 PM PDT 24 399581259 ps
T56 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.296307666 Jul 15 05:31:07 PM PDT 24 Jul 15 05:31:08 PM PDT 24 341061212 ps
T200 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4192440467 Jul 15 05:31:47 PM PDT 24 Jul 15 05:31:49 PM PDT 24 396752983 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3800662818 Jul 15 05:31:11 PM PDT 24 Jul 15 05:31:13 PM PDT 24 346135558 ps
T201 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1795674323 Jul 15 05:31:46 PM PDT 24 Jul 15 05:31:48 PM PDT 24 387375026 ps
T202 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2763618361 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:46 PM PDT 24 534263474 ps
T73 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1604173042 Jul 15 05:31:28 PM PDT 24 Jul 15 05:31:29 PM PDT 24 510531015 ps
T291 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3103136574 Jul 15 05:31:57 PM PDT 24 Jul 15 05:31:59 PM PDT 24 284589947 ps
T292 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.564073792 Jul 15 05:31:12 PM PDT 24 Jul 15 05:31:14 PM PDT 24 1022434007 ps
T293 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2553188575 Jul 15 05:31:21 PM PDT 24 Jul 15 05:31:23 PM PDT 24 329468976 ps
T74 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1158293834 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:47 PM PDT 24 1088446484 ps
T294 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.358252092 Jul 15 05:31:57 PM PDT 24 Jul 15 05:31:59 PM PDT 24 505603229 ps
T295 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.982289741 Jul 15 05:31:13 PM PDT 24 Jul 15 05:31:15 PM PDT 24 469889072 ps
T296 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4226106095 Jul 15 05:31:59 PM PDT 24 Jul 15 05:32:01 PM PDT 24 463650544 ps
T297 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1925806248 Jul 15 05:31:48 PM PDT 24 Jul 15 05:31:50 PM PDT 24 420749025 ps
T298 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2954857388 Jul 15 05:31:48 PM PDT 24 Jul 15 05:31:50 PM PDT 24 493502042 ps
T299 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1643814151 Jul 15 05:31:58 PM PDT 24 Jul 15 05:32:00 PM PDT 24 364943902 ps
T75 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3487911641 Jul 15 05:31:45 PM PDT 24 Jul 15 05:31:49 PM PDT 24 1287739822 ps
T300 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1187095217 Jul 15 05:31:14 PM PDT 24 Jul 15 05:31:15 PM PDT 24 484648922 ps
T301 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.468958803 Jul 15 05:31:56 PM PDT 24 Jul 15 05:31:57 PM PDT 24 331037279 ps
T302 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1516109794 Jul 15 05:31:23 PM PDT 24 Jul 15 05:31:24 PM PDT 24 366855271 ps
T303 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1529167375 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:47 PM PDT 24 507082450 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.64082773 Jul 15 05:31:11 PM PDT 24 Jul 15 05:31:13 PM PDT 24 769080134 ps
T305 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2200936256 Jul 15 05:31:47 PM PDT 24 Jul 15 05:31:49 PM PDT 24 511565734 ps
T306 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4292594653 Jul 15 05:31:59 PM PDT 24 Jul 15 05:32:01 PM PDT 24 487938389 ps
T307 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3882177434 Jul 15 05:31:37 PM PDT 24 Jul 15 05:31:38 PM PDT 24 422412394 ps
T76 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1921239160 Jul 15 05:31:33 PM PDT 24 Jul 15 05:31:34 PM PDT 24 526497390 ps
T308 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.366607186 Jul 15 05:31:22 PM PDT 24 Jul 15 05:31:23 PM PDT 24 511522268 ps
T309 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1373874684 Jul 15 05:31:48 PM PDT 24 Jul 15 05:31:50 PM PDT 24 614735791 ps
T310 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.714929832 Jul 15 05:31:29 PM PDT 24 Jul 15 05:31:32 PM PDT 24 657627973 ps
T32 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.173913222 Jul 15 05:31:28 PM PDT 24 Jul 15 05:31:37 PM PDT 24 7908623369 ps
T311 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1304138808 Jul 15 05:31:56 PM PDT 24 Jul 15 05:31:58 PM PDT 24 527418642 ps
T312 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2775647354 Jul 15 05:31:55 PM PDT 24 Jul 15 05:31:56 PM PDT 24 326640229 ps
T57 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1306523949 Jul 15 05:31:38 PM PDT 24 Jul 15 05:31:40 PM PDT 24 320237065 ps
T33 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.831070390 Jul 15 05:31:40 PM PDT 24 Jul 15 05:31:47 PM PDT 24 4354650149 ps
T313 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2672013189 Jul 15 05:31:56 PM PDT 24 Jul 15 05:31:58 PM PDT 24 342882303 ps
T314 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.844988725 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:46 PM PDT 24 398016894 ps
T315 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2681544208 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:47 PM PDT 24 487855531 ps
T188 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2066079040 Jul 15 05:31:49 PM PDT 24 Jul 15 05:31:57 PM PDT 24 4299926547 ps
T189 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4209669129 Jul 15 05:31:47 PM PDT 24 Jul 15 05:32:00 PM PDT 24 8429380853 ps
T316 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2926671163 Jul 15 05:31:47 PM PDT 24 Jul 15 05:31:50 PM PDT 24 677630136 ps
T317 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1235335415 Jul 15 05:31:45 PM PDT 24 Jul 15 05:31:49 PM PDT 24 422801436 ps
T318 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.198196633 Jul 15 05:31:28 PM PDT 24 Jul 15 05:31:30 PM PDT 24 461921226 ps
T319 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2963771844 Jul 15 05:31:38 PM PDT 24 Jul 15 05:31:40 PM PDT 24 516338168 ps
T320 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3466038513 Jul 15 05:31:30 PM PDT 24 Jul 15 05:31:31 PM PDT 24 339837980 ps
T321 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2148436750 Jul 15 05:31:46 PM PDT 24 Jul 15 05:31:49 PM PDT 24 626883153 ps
T322 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2097020825 Jul 15 05:31:28 PM PDT 24 Jul 15 05:31:30 PM PDT 24 592480271 ps
T323 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1760895184 Jul 15 05:31:25 PM PDT 24 Jul 15 05:31:26 PM PDT 24 355832062 ps
T324 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1581636180 Jul 15 05:31:38 PM PDT 24 Jul 15 05:31:40 PM PDT 24 376004320 ps
T325 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1907584532 Jul 15 05:31:43 PM PDT 24 Jul 15 05:31:46 PM PDT 24 376307141 ps
T326 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2953999917 Jul 15 05:31:36 PM PDT 24 Jul 15 05:31:38 PM PDT 24 571137365 ps
T327 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3171447986 Jul 15 05:31:58 PM PDT 24 Jul 15 05:32:00 PM PDT 24 397820010 ps
T328 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3510945301 Jul 15 05:31:11 PM PDT 24 Jul 15 05:31:12 PM PDT 24 298113530 ps
T77 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1451587035 Jul 15 05:31:27 PM PDT 24 Jul 15 05:31:34 PM PDT 24 2179818084 ps
T329 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2181049500 Jul 15 05:31:33 PM PDT 24 Jul 15 05:31:34 PM PDT 24 630757590 ps
T58 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4101886457 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:46 PM PDT 24 518058333 ps
T330 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2494405860 Jul 15 05:31:15 PM PDT 24 Jul 15 05:31:17 PM PDT 24 409650527 ps
T191 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2942051783 Jul 15 05:31:45 PM PDT 24 Jul 15 05:31:54 PM PDT 24 4314083658 ps
T331 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2057501426 Jul 15 05:31:29 PM PDT 24 Jul 15 05:31:30 PM PDT 24 304735237 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3377058046 Jul 15 05:31:10 PM PDT 24 Jul 15 05:31:37 PM PDT 24 11687981994 ps
T190 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.583105357 Jul 15 05:31:38 PM PDT 24 Jul 15 05:31:40 PM PDT 24 4272568523 ps
T332 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1343270242 Jul 15 05:31:05 PM PDT 24 Jul 15 05:31:06 PM PDT 24 427523540 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3842894017 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:46 PM PDT 24 297197250 ps
T334 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3957448903 Jul 15 05:31:59 PM PDT 24 Jul 15 05:32:01 PM PDT 24 429124387 ps
T335 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2452942782 Jul 15 05:31:48 PM PDT 24 Jul 15 05:31:51 PM PDT 24 293842845 ps
T336 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3973487079 Jul 15 05:31:38 PM PDT 24 Jul 15 05:31:40 PM PDT 24 427876436 ps
T337 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2406124910 Jul 15 05:31:38 PM PDT 24 Jul 15 05:31:42 PM PDT 24 922329982 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3548648866 Jul 15 05:31:23 PM PDT 24 Jul 15 05:31:24 PM PDT 24 664561700 ps
T78 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3779177521 Jul 15 05:31:13 PM PDT 24 Jul 15 05:31:17 PM PDT 24 2022120434 ps
T338 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.725240262 Jul 15 05:31:56 PM PDT 24 Jul 15 05:31:58 PM PDT 24 369931549 ps
T79 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.125903020 Jul 15 05:31:12 PM PDT 24 Jul 15 05:31:14 PM PDT 24 316080630 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3211162510 Jul 15 05:31:13 PM PDT 24 Jul 15 05:31:23 PM PDT 24 12378661692 ps
T339 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1867296878 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:49 PM PDT 24 674386053 ps
T340 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.231812242 Jul 15 05:31:21 PM PDT 24 Jul 15 05:31:22 PM PDT 24 438570779 ps
T341 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3706942687 Jul 15 05:31:17 PM PDT 24 Jul 15 05:31:19 PM PDT 24 573188088 ps
T342 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1761288146 Jul 15 05:31:58 PM PDT 24 Jul 15 05:32:00 PM PDT 24 434843274 ps
T343 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2893938371 Jul 15 05:31:28 PM PDT 24 Jul 15 05:31:30 PM PDT 24 509877207 ps
T344 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4076605980 Jul 15 05:31:40 PM PDT 24 Jul 15 05:31:45 PM PDT 24 2265986619 ps
T345 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4209807557 Jul 15 05:31:43 PM PDT 24 Jul 15 05:31:45 PM PDT 24 1132262927 ps
T192 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1132317737 Jul 15 05:31:40 PM PDT 24 Jul 15 05:31:45 PM PDT 24 8282360880 ps
T346 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1615313199 Jul 15 05:31:40 PM PDT 24 Jul 15 05:31:45 PM PDT 24 7873582790 ps
T347 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.624735881 Jul 15 05:31:37 PM PDT 24 Jul 15 05:31:40 PM PDT 24 301891448 ps
T62 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.493307041 Jul 15 05:31:39 PM PDT 24 Jul 15 05:31:41 PM PDT 24 368048371 ps
T348 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2426128537 Jul 15 05:31:10 PM PDT 24 Jul 15 05:31:12 PM PDT 24 483687425 ps
T349 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3231196475 Jul 15 05:31:47 PM PDT 24 Jul 15 05:31:49 PM PDT 24 610276766 ps
T350 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3801823618 Jul 15 05:31:39 PM PDT 24 Jul 15 05:31:43 PM PDT 24 2424851116 ps
T351 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1510737877 Jul 15 05:31:21 PM PDT 24 Jul 15 05:31:23 PM PDT 24 396881093 ps
T352 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2271529552 Jul 15 05:31:25 PM PDT 24 Jul 15 05:31:27 PM PDT 24 375856684 ps
T353 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.405506209 Jul 15 05:31:14 PM PDT 24 Jul 15 05:31:17 PM PDT 24 372342271 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4177873074 Jul 15 05:31:16 PM PDT 24 Jul 15 05:31:20 PM PDT 24 657600700 ps
T355 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2323994391 Jul 15 05:31:59 PM PDT 24 Jul 15 05:32:01 PM PDT 24 458048235 ps
T356 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3817749898 Jul 15 05:31:41 PM PDT 24 Jul 15 05:31:47 PM PDT 24 8787757684 ps
T357 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2568048093 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:46 PM PDT 24 2119645554 ps
T64 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1030451068 Jul 15 05:31:12 PM PDT 24 Jul 15 05:31:14 PM PDT 24 510372395 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2250960250 Jul 15 05:31:17 PM PDT 24 Jul 15 05:31:30 PM PDT 24 8344951028 ps
T359 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2261446775 Jul 15 05:31:48 PM PDT 24 Jul 15 05:31:52 PM PDT 24 2935817756 ps
T65 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.465751904 Jul 15 05:31:39 PM PDT 24 Jul 15 05:31:42 PM PDT 24 320325231 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1181303521 Jul 15 05:31:20 PM PDT 24 Jul 15 05:31:21 PM PDT 24 598476741 ps
T360 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.130375255 Jul 15 05:31:23 PM PDT 24 Jul 15 05:31:28 PM PDT 24 4127538470 ps
T69 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2562277683 Jul 15 05:31:18 PM PDT 24 Jul 15 05:31:20 PM PDT 24 924978161 ps
T361 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.374067942 Jul 15 05:31:16 PM PDT 24 Jul 15 05:31:21 PM PDT 24 2105607122 ps
T362 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1926241794 Jul 15 05:31:57 PM PDT 24 Jul 15 05:31:58 PM PDT 24 380032065 ps
T363 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2454162543 Jul 15 05:31:41 PM PDT 24 Jul 15 05:31:44 PM PDT 24 417537962 ps
T364 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.613135882 Jul 15 05:31:24 PM PDT 24 Jul 15 05:31:27 PM PDT 24 581866834 ps
T365 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2602926780 Jul 15 05:31:57 PM PDT 24 Jul 15 05:31:59 PM PDT 24 445918345 ps
T366 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.745397189 Jul 15 05:31:56 PM PDT 24 Jul 15 05:31:58 PM PDT 24 315283323 ps
T367 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1626248918 Jul 15 05:31:27 PM PDT 24 Jul 15 05:31:30 PM PDT 24 349806728 ps
T368 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1080363547 Jul 15 05:31:28 PM PDT 24 Jul 15 05:31:29 PM PDT 24 352891862 ps
T369 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1265812640 Jul 15 05:31:23 PM PDT 24 Jul 15 05:31:25 PM PDT 24 456191867 ps
T370 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.563450279 Jul 15 05:31:12 PM PDT 24 Jul 15 05:31:14 PM PDT 24 547708147 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.565489502 Jul 15 05:31:40 PM PDT 24 Jul 15 05:31:42 PM PDT 24 443954885 ps
T372 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3109840437 Jul 15 05:31:56 PM PDT 24 Jul 15 05:31:57 PM PDT 24 346906668 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.724294136 Jul 15 05:31:13 PM PDT 24 Jul 15 05:31:18 PM PDT 24 11921203310 ps
T373 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2058624239 Jul 15 05:31:29 PM PDT 24 Jul 15 05:31:31 PM PDT 24 2669002551 ps
T71 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.663089558 Jul 15 05:31:44 PM PDT 24 Jul 15 05:31:47 PM PDT 24 334898282 ps
T374 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.201906692 Jul 15 05:31:39 PM PDT 24 Jul 15 05:31:41 PM PDT 24 445731641 ps
T375 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.207478025 Jul 15 05:31:11 PM PDT 24 Jul 15 05:31:13 PM PDT 24 304825032 ps
T376 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3817066798 Jul 15 05:31:29 PM PDT 24 Jul 15 05:31:31 PM PDT 24 639306272 ps
T377 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.766991048 Jul 15 05:31:17 PM PDT 24 Jul 15 05:31:19 PM PDT 24 330780749 ps
T378 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2544793895 Jul 15 05:31:17 PM PDT 24 Jul 15 05:31:19 PM PDT 24 316733782 ps
T379 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1724758693 Jul 15 05:31:07 PM PDT 24 Jul 15 05:31:09 PM PDT 24 420612063 ps
T380 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2704691174 Jul 15 05:31:48 PM PDT 24 Jul 15 05:31:51 PM PDT 24 342410717 ps
T381 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1010901795 Jul 15 05:31:17 PM PDT 24 Jul 15 05:31:26 PM PDT 24 4457316238 ps
T382 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.850900119 Jul 15 05:31:19 PM PDT 24 Jul 15 05:31:23 PM PDT 24 1234716082 ps
T383 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2651885266 Jul 15 05:31:07 PM PDT 24 Jul 15 05:31:10 PM PDT 24 2135560960 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1033929372 Jul 15 05:31:25 PM PDT 24 Jul 15 05:31:27 PM PDT 24 309785324 ps
T384 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.720578186 Jul 15 05:31:20 PM PDT 24 Jul 15 05:31:23 PM PDT 24 1121755734 ps
T385 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3581871236 Jul 15 05:31:57 PM PDT 24 Jul 15 05:31:59 PM PDT 24 468919821 ps
T386 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3646332788 Jul 15 05:31:57 PM PDT 24 Jul 15 05:31:59 PM PDT 24 344753812 ps
T387 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1708727798 Jul 15 05:31:48 PM PDT 24 Jul 15 05:31:52 PM PDT 24 484748592 ps
T388 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.131056603 Jul 15 05:31:12 PM PDT 24 Jul 15 05:31:20 PM PDT 24 8410961019 ps
T389 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3465638971 Jul 15 05:31:15 PM PDT 24 Jul 15 05:31:17 PM PDT 24 454827058 ps
T390 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1127480576 Jul 15 05:31:48 PM PDT 24 Jul 15 05:31:50 PM PDT 24 307852083 ps
T193 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4119643012 Jul 15 05:31:23 PM PDT 24 Jul 15 05:31:27 PM PDT 24 8727981081 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.130375148 Jul 15 05:31:13 PM PDT 24 Jul 15 05:31:16 PM PDT 24 490368794 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2597614128 Jul 15 05:31:27 PM PDT 24 Jul 15 05:31:30 PM PDT 24 6240851014 ps
T393 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1278523677 Jul 15 05:31:55 PM PDT 24 Jul 15 05:31:57 PM PDT 24 311955706 ps
T394 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.4242530057 Jul 15 05:31:58 PM PDT 24 Jul 15 05:32:00 PM PDT 24 434023668 ps
T395 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2682887095 Jul 15 05:31:21 PM PDT 24 Jul 15 05:31:22 PM PDT 24 280845800 ps
T396 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.691570274 Jul 15 05:31:57 PM PDT 24 Jul 15 05:31:59 PM PDT 24 313031815 ps
T397 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.431762622 Jul 15 05:31:10 PM PDT 24 Jul 15 05:31:11 PM PDT 24 1137326664 ps
T398 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.967066225 Jul 15 05:31:46 PM PDT 24 Jul 15 05:31:51 PM PDT 24 1270003139 ps
T399 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4249446388 Jul 15 05:31:38 PM PDT 24 Jul 15 05:31:40 PM PDT 24 1256163101 ps
T400 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4054257908 Jul 15 05:31:19 PM PDT 24 Jul 15 05:31:26 PM PDT 24 3935230463 ps
T72 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2592081480 Jul 15 05:31:38 PM PDT 24 Jul 15 05:31:40 PM PDT 24 410230654 ps
T401 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3702911398 Jul 15 05:31:55 PM PDT 24 Jul 15 05:31:56 PM PDT 24 280389803 ps
T402 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1092769936 Jul 15 05:31:55 PM PDT 24 Jul 15 05:31:56 PM PDT 24 501713525 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1101061042 Jul 15 05:31:20 PM PDT 24 Jul 15 05:31:30 PM PDT 24 12564307355 ps
T404 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3979104062 Jul 15 05:31:46 PM PDT 24 Jul 15 05:31:49 PM PDT 24 421469270 ps
T405 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1672761486 Jul 15 05:31:45 PM PDT 24 Jul 15 05:31:53 PM PDT 24 4606177037 ps
T406 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2664877891 Jul 15 05:31:56 PM PDT 24 Jul 15 05:31:58 PM PDT 24 308272228 ps
T194 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2402525437 Jul 15 05:31:41 PM PDT 24 Jul 15 05:31:44 PM PDT 24 7959104379 ps
T407 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.862693156 Jul 15 05:31:14 PM PDT 24 Jul 15 05:31:16 PM PDT 24 528944332 ps
T408 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.355997919 Jul 15 05:31:59 PM PDT 24 Jul 15 05:32:00 PM PDT 24 358793242 ps
T409 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2317973515 Jul 15 05:31:45 PM PDT 24 Jul 15 05:31:49 PM PDT 24 532188292 ps
T410 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3186781071 Jul 15 05:31:15 PM PDT 24 Jul 15 05:31:17 PM PDT 24 297686179 ps
T411 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2866132425 Jul 15 05:32:01 PM PDT 24 Jul 15 05:32:03 PM PDT 24 497902397 ps
T412 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1828327887 Jul 15 05:31:46 PM PDT 24 Jul 15 05:31:49 PM PDT 24 1332747382 ps
T413 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4175764246 Jul 15 05:31:24 PM PDT 24 Jul 15 05:31:26 PM PDT 24 1441222913 ps
T414 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4223826583 Jul 15 05:31:39 PM PDT 24 Jul 15 05:31:42 PM PDT 24 488122920 ps
T415 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2083595787 Jul 15 05:31:39 PM PDT 24 Jul 15 05:31:40 PM PDT 24 408614848 ps
T68 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3675907153 Jul 15 05:31:48 PM PDT 24 Jul 15 05:31:50 PM PDT 24 443333268 ps
T416 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2925377500 Jul 15 05:31:37 PM PDT 24 Jul 15 05:31:39 PM PDT 24 492473411 ps
T417 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2319294667 Jul 15 05:31:29 PM PDT 24 Jul 15 05:31:30 PM PDT 24 944438911 ps
T418 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4137893109 Jul 15 05:31:31 PM PDT 24 Jul 15 05:31:35 PM PDT 24 4322619175 ps
T195 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1191126517 Jul 15 05:31:05 PM PDT 24 Jul 15 05:31:13 PM PDT 24 4042971110 ps
T419 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2667457864 Jul 15 05:32:01 PM PDT 24 Jul 15 05:32:03 PM PDT 24 369242924 ps
T420 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4123533219 Jul 15 05:31:27 PM PDT 24 Jul 15 05:31:30 PM PDT 24 2238812274 ps
T421 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.479819870 Jul 15 05:31:38 PM PDT 24 Jul 15 05:31:40 PM PDT 24 1129739469 ps

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3887637745
Short name T9
Test name
Test status
Simulation time 116011074043 ps
CPU time 387.71 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:07:55 PM PDT 24
Peak memory 200656 kb
Host smart-92c2d633-2f0a-4c00-82b9-04f12e83c776
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887637745 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3887637745
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3836671192
Short name T12
Test name
Test status
Simulation time 132595508532 ps
CPU time 509.67 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:09:56 PM PDT 24
Peak memory 212260 kb
Host smart-409d2b75-bef8-4132-96c4-2439507730dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836671192 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3836671192
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3664418078
Short name T31
Test name
Test status
Simulation time 4288829187 ps
CPU time 2.07 seconds
Started Jul 15 05:31:46 PM PDT 24
Finished Jul 15 05:31:50 PM PDT 24
Peak memory 197868 kb
Host smart-3ece3675-1322-4b5b-8120-a856258584e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664418078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3664418078
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3395353976
Short name T1
Test name
Test status
Simulation time 165572770270 ps
CPU time 252.87 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:05:30 PM PDT 24
Peak memory 193028 kb
Host smart-89fbd441-58be-42f0-89f5-2d199aea8118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395353976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3395353976
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1306523949
Short name T57
Test name
Test status
Simulation time 320237065 ps
CPU time 0.97 seconds
Started Jul 15 05:31:38 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 193924 kb
Host smart-37e7d2d0-71e6-4749-aa3b-b4aa15ef1a06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306523949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1306523949
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3418345392
Short name T36
Test name
Test status
Simulation time 381475558880 ps
CPU time 961.12 seconds
Started Jul 15 06:01:23 PM PDT 24
Finished Jul 15 06:17:25 PM PDT 24
Peak memory 210452 kb
Host smart-02160c96-20cc-4ed6-8e91-3c210948c717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418345392 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3418345392
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3934735587
Short name T106
Test name
Test status
Simulation time 102050101212 ps
CPU time 590.73 seconds
Started Jul 15 06:01:01 PM PDT 24
Finished Jul 15 06:10:52 PM PDT 24
Peak memory 202036 kb
Host smart-71943598-8809-4025-9c3d-c9e3dd7e1072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934735587 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3934735587
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4112025224
Short name T80
Test name
Test status
Simulation time 281759622591 ps
CPU time 515.66 seconds
Started Jul 15 06:01:32 PM PDT 24
Finished Jul 15 06:10:08 PM PDT 24
Peak memory 214916 kb
Host smart-7d92e504-d911-4493-ab15-516d1f13a2a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112025224 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4112025224
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1230031028
Short name T11
Test name
Test status
Simulation time 83414630842 ps
CPU time 506.04 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:10:17 PM PDT 24
Peak memory 203652 kb
Host smart-81c338c0-afcd-495f-81ea-1193a639e55f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230031028 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1230031028
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.474230234
Short name T118
Test name
Test status
Simulation time 535375878780 ps
CPU time 348.35 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:07:15 PM PDT 24
Peak memory 210436 kb
Host smart-e673a7bf-a195-4da8-a2ac-5bfee185a8a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474230234 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.474230234
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2840197677
Short name T18
Test name
Test status
Simulation time 3796809936 ps
CPU time 3.24 seconds
Started Jul 15 06:00:58 PM PDT 24
Finished Jul 15 06:01:02 PM PDT 24
Peak memory 215364 kb
Host smart-831401d5-dba7-431f-9d2a-8f0337e5ff9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840197677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2840197677
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3222229843
Short name T99
Test name
Test status
Simulation time 145161175146 ps
CPU time 183.95 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:04:33 PM PDT 24
Peak memory 184492 kb
Host smart-b240b4e7-195a-41d4-8792-63977d41dd58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222229843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3222229843
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3192042241
Short name T88
Test name
Test status
Simulation time 91843713983 ps
CPU time 159.94 seconds
Started Jul 15 06:01:59 PM PDT 24
Finished Jul 15 06:04:39 PM PDT 24
Peak memory 207800 kb
Host smart-b1ec3dc8-8799-4f58-9ee9-99da4b2e1702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192042241 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3192042241
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1814006730
Short name T2
Test name
Test status
Simulation time 308618093188 ps
CPU time 496.23 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:09:33 PM PDT 24
Peak memory 212148 kb
Host smart-9be9becf-2a3a-4d25-9378-79b06901b9de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814006730 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1814006730
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.739159417
Short name T108
Test name
Test status
Simulation time 34162889170 ps
CPU time 11.35 seconds
Started Jul 15 06:01:37 PM PDT 24
Finished Jul 15 06:01:48 PM PDT 24
Peak memory 198248 kb
Host smart-b68dcfac-960f-4180-ba68-ad64ed2501fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739159417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.739159417
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.757758241
Short name T82
Test name
Test status
Simulation time 81265097908 ps
CPU time 370.15 seconds
Started Jul 15 06:01:38 PM PDT 24
Finished Jul 15 06:07:49 PM PDT 24
Peak memory 202088 kb
Host smart-20fdedfe-5efb-4d13-9367-f21567f699df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757758241 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.757758241
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.565046664
Short name T87
Test name
Test status
Simulation time 391736171365 ps
CPU time 687.62 seconds
Started Jul 15 06:01:39 PM PDT 24
Finished Jul 15 06:13:08 PM PDT 24
Peak memory 214956 kb
Host smart-a0835d8e-360a-4ebb-96bc-7cac17caca1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565046664 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.565046664
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.929657144
Short name T37
Test name
Test status
Simulation time 191926768870 ps
CPU time 170.74 seconds
Started Jul 15 06:01:40 PM PDT 24
Finished Jul 15 06:04:32 PM PDT 24
Peak memory 199836 kb
Host smart-bf4a8708-3ede-4383-b97e-f16fec604681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929657144 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.929657144
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1804381553
Short name T104
Test name
Test status
Simulation time 94343379902 ps
CPU time 10.66 seconds
Started Jul 15 06:01:28 PM PDT 24
Finished Jul 15 06:01:40 PM PDT 24
Peak memory 191916 kb
Host smart-df6f447b-abeb-4acc-a40f-e6a40fcf24b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804381553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1804381553
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1595717666
Short name T95
Test name
Test status
Simulation time 57789516525 ps
CPU time 88.53 seconds
Started Jul 15 06:01:45 PM PDT 24
Finished Jul 15 06:03:14 PM PDT 24
Peak memory 191952 kb
Host smart-d21e5c83-47e5-4746-b023-5e870f6a362c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595717666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1595717666
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2069712181
Short name T98
Test name
Test status
Simulation time 350741067910 ps
CPU time 471.84 seconds
Started Jul 15 06:01:39 PM PDT 24
Finished Jul 15 06:09:32 PM PDT 24
Peak memory 198280 kb
Host smart-90a6a1e7-eaff-4c3b-9ec8-6a9c62e9673e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069712181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2069712181
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2026913213
Short name T86
Test name
Test status
Simulation time 112762119859 ps
CPU time 158.53 seconds
Started Jul 15 06:01:02 PM PDT 24
Finished Jul 15 06:03:41 PM PDT 24
Peak memory 199716 kb
Host smart-b06257d6-e18e-4947-83d5-3bcbf6e0ee1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026913213 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2026913213
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1350829908
Short name T124
Test name
Test status
Simulation time 192173526248 ps
CPU time 287.47 seconds
Started Jul 15 06:01:58 PM PDT 24
Finished Jul 15 06:06:46 PM PDT 24
Peak memory 198272 kb
Host smart-06e105f9-9c5f-4128-93f8-4372fb0fb976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350829908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1350829908
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3170116481
Short name T103
Test name
Test status
Simulation time 190332668748 ps
CPU time 63.67 seconds
Started Jul 15 06:01:50 PM PDT 24
Finished Jul 15 06:02:56 PM PDT 24
Peak memory 193012 kb
Host smart-ae7e4a36-08ed-4d77-bca8-e66208d70349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170116481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3170116481
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2918762241
Short name T81
Test name
Test status
Simulation time 63100471926 ps
CPU time 121.64 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:03:19 PM PDT 24
Peak memory 198556 kb
Host smart-f522a321-cca8-4a52-89a4-6e976a8c34db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918762241 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2918762241
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.4029567073
Short name T85
Test name
Test status
Simulation time 209992751756 ps
CPU time 402.86 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:08:10 PM PDT 24
Peak memory 202968 kb
Host smart-e5c3e7e5-d895-48d7-8173-3e61cd1adde8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029567073 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.4029567073
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1753483476
Short name T52
Test name
Test status
Simulation time 171515682472 ps
CPU time 134.58 seconds
Started Jul 15 06:01:46 PM PDT 24
Finished Jul 15 06:04:01 PM PDT 24
Peak memory 214320 kb
Host smart-0dc49c26-8bb9-4afb-92f0-10b53def20da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753483476 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1753483476
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3458240473
Short name T101
Test name
Test status
Simulation time 85273356134 ps
CPU time 62.84 seconds
Started Jul 15 06:01:29 PM PDT 24
Finished Jul 15 06:02:33 PM PDT 24
Peak memory 184164 kb
Host smart-3121aee9-dd9b-4337-a106-d39965182cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458240473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3458240473
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2964760998
Short name T83
Test name
Test status
Simulation time 71557875870 ps
CPU time 713.21 seconds
Started Jul 15 06:01:47 PM PDT 24
Finished Jul 15 06:13:41 PM PDT 24
Peak memory 205640 kb
Host smart-1696d59c-d2aa-431c-96f1-645498dc0b5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964760998 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2964760998
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.521494038
Short name T4
Test name
Test status
Simulation time 66304777480 ps
CPU time 146.72 seconds
Started Jul 15 06:01:45 PM PDT 24
Finished Jul 15 06:04:12 PM PDT 24
Peak memory 198548 kb
Host smart-6b2393ad-c53c-4dde-b82d-7de6b95fadf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521494038 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.521494038
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3992258159
Short name T121
Test name
Test status
Simulation time 24596424805 ps
CPU time 10.63 seconds
Started Jul 15 06:01:50 PM PDT 24
Finished Jul 15 06:02:03 PM PDT 24
Peak memory 191900 kb
Host smart-8c1b414a-0387-46b7-b9e0-58725cbd22fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992258159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3992258159
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.412818781
Short name T105
Test name
Test status
Simulation time 24547453709 ps
CPU time 175.07 seconds
Started Jul 15 06:01:47 PM PDT 24
Finished Jul 15 06:04:42 PM PDT 24
Peak memory 206980 kb
Host smart-6c778ce0-b02a-4619-992f-cb5a1e2dbc98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412818781 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.412818781
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.861160042
Short name T40
Test name
Test status
Simulation time 33173558607 ps
CPU time 45.39 seconds
Started Jul 15 06:01:42 PM PDT 24
Finished Jul 15 06:02:28 PM PDT 24
Peak memory 191868 kb
Host smart-4f69f9f2-3f7e-4e6a-868b-0ffe15b7065d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861160042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.861160042
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2258034016
Short name T110
Test name
Test status
Simulation time 219123201332 ps
CPU time 28.25 seconds
Started Jul 15 06:01:51 PM PDT 24
Finished Jul 15 06:02:21 PM PDT 24
Peak memory 193012 kb
Host smart-adb48159-69ca-4852-8e21-9a4565950fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258034016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2258034016
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2492404827
Short name T102
Test name
Test status
Simulation time 283442104260 ps
CPU time 100.95 seconds
Started Jul 15 06:01:58 PM PDT 24
Finished Jul 15 06:03:40 PM PDT 24
Peak memory 192460 kb
Host smart-47fdf81f-3bf8-43ec-8996-64d879d4ab37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492404827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2492404827
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3479309202
Short name T126
Test name
Test status
Simulation time 45201716357 ps
CPU time 359.53 seconds
Started Jul 15 06:01:47 PM PDT 24
Finished Jul 15 06:07:48 PM PDT 24
Peak memory 206780 kb
Host smart-b7c27c5d-5b30-47ad-a37c-913bcfdfe4d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479309202 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3479309202
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3530900398
Short name T109
Test name
Test status
Simulation time 152333115347 ps
CPU time 277.56 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:05:55 PM PDT 24
Peak memory 201120 kb
Host smart-b9597b85-068f-457b-9a76-f13ee5e4c55e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530900398 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3530900398
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2906075084
Short name T89
Test name
Test status
Simulation time 172487165735 ps
CPU time 133.42 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:03:42 PM PDT 24
Peak memory 207624 kb
Host smart-d9f2e27a-b6fc-4fd3-a438-e5e64c59e323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906075084 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2906075084
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3398154386
Short name T159
Test name
Test status
Simulation time 114639702488 ps
CPU time 275.75 seconds
Started Jul 15 06:01:20 PM PDT 24
Finished Jul 15 06:05:56 PM PDT 24
Peak memory 207560 kb
Host smart-f39e2738-29bc-403d-a404-26c816647bd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398154386 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3398154386
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2070370536
Short name T113
Test name
Test status
Simulation time 115309656852 ps
CPU time 302.26 seconds
Started Jul 15 06:01:53 PM PDT 24
Finished Jul 15 06:06:56 PM PDT 24
Peak memory 214028 kb
Host smart-02de63c8-1c07-47aa-aae5-816ba969d3be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070370536 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2070370536
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4195979768
Short name T130
Test name
Test status
Simulation time 43270784767 ps
CPU time 113.37 seconds
Started Jul 15 06:02:01 PM PDT 24
Finished Jul 15 06:03:55 PM PDT 24
Peak memory 206760 kb
Host smart-a138e310-81d7-4e7f-94c4-61bc774839ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195979768 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4195979768
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.265470150
Short name T155
Test name
Test status
Simulation time 247407612250 ps
CPU time 25.38 seconds
Started Jul 15 06:01:51 PM PDT 24
Finished Jul 15 06:02:18 PM PDT 24
Peak memory 192948 kb
Host smart-8708077c-101a-43fc-bf58-ec79fee5869c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265470150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.265470150
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2171286279
Short name T167
Test name
Test status
Simulation time 260326672043 ps
CPU time 726.46 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:13:22 PM PDT 24
Peak memory 214956 kb
Host smart-3a361d4d-fc69-4ef7-b9fd-83877807a100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171286279 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2171286279
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3371320093
Short name T120
Test name
Test status
Simulation time 63306946448 ps
CPU time 95.49 seconds
Started Jul 15 06:01:22 PM PDT 24
Finished Jul 15 06:02:58 PM PDT 24
Peak memory 184236 kb
Host smart-151472d2-795f-458a-95ed-c30e0bab8816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371320093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3371320093
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2493053196
Short name T100
Test name
Test status
Simulation time 54526656873 ps
CPU time 42.65 seconds
Started Jul 15 06:01:11 PM PDT 24
Finished Jul 15 06:01:54 PM PDT 24
Peak memory 193108 kb
Host smart-857086a0-e701-41d0-947a-6b31dd071cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493053196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2493053196
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3547045288
Short name T94
Test name
Test status
Simulation time 26480422030 ps
CPU time 18.87 seconds
Started Jul 15 06:01:28 PM PDT 24
Finished Jul 15 06:01:49 PM PDT 24
Peak memory 191844 kb
Host smart-f312d556-0ab5-4614-ac69-ef970cb75d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547045288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3547045288
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.239128481
Short name T157
Test name
Test status
Simulation time 93296202779 ps
CPU time 70.03 seconds
Started Jul 15 06:01:29 PM PDT 24
Finished Jul 15 06:02:40 PM PDT 24
Peak memory 198280 kb
Host smart-9d100be9-d8bc-4a5b-adac-1f9948ecc950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239128481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.239128481
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2367456855
Short name T63
Test name
Test status
Simulation time 106162682790 ps
CPU time 303.2 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:06:31 PM PDT 24
Peak memory 201668 kb
Host smart-6c6adc97-564b-4eaf-9e21-f7a79c91e9bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367456855 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2367456855
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2480949264
Short name T111
Test name
Test status
Simulation time 143584547569 ps
CPU time 202.99 seconds
Started Jul 15 06:01:47 PM PDT 24
Finished Jul 15 06:05:11 PM PDT 24
Peak memory 191884 kb
Host smart-a90c1643-cfae-450d-87fb-05c0d6222d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480949264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2480949264
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.574106144
Short name T141
Test name
Test status
Simulation time 99218943556 ps
CPU time 35.52 seconds
Started Jul 15 06:01:19 PM PDT 24
Finished Jul 15 06:01:55 PM PDT 24
Peak memory 198312 kb
Host smart-0820c3b2-c098-459e-8d46-414a33091d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574106144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.574106144
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.915492479
Short name T92
Test name
Test status
Simulation time 649730135582 ps
CPU time 502.72 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:10:13 PM PDT 24
Peak memory 214732 kb
Host smart-77430028-4e11-4cfb-ae0c-04220ff80940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915492479 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.915492479
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3884005808
Short name T147
Test name
Test status
Simulation time 83848428757 ps
CPU time 59.68 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:02:16 PM PDT 24
Peak memory 191912 kb
Host smart-6dff48bc-72b9-440a-96dd-d00365e15689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884005808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3884005808
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3235535102
Short name T7
Test name
Test status
Simulation time 483784815850 ps
CPU time 183.35 seconds
Started Jul 15 06:01:40 PM PDT 24
Finished Jul 15 06:04:44 PM PDT 24
Peak memory 198256 kb
Host smart-14a71c06-4237-4109-9acf-9003210000cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235535102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3235535102
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.756158852
Short name T158
Test name
Test status
Simulation time 10432047806 ps
CPU time 78.96 seconds
Started Jul 15 06:01:28 PM PDT 24
Finished Jul 15 06:02:48 PM PDT 24
Peak memory 198552 kb
Host smart-6b638e5c-3020-408d-93b8-9426e26c065a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756158852 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.756158852
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2683449400
Short name T55
Test name
Test status
Simulation time 104815074760 ps
CPU time 339.02 seconds
Started Jul 15 06:01:38 PM PDT 24
Finished Jul 15 06:07:18 PM PDT 24
Peak memory 200092 kb
Host smart-f11f2e2e-d195-4289-9445-b1ca742c52ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683449400 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2683449400
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.690063882
Short name T173
Test name
Test status
Simulation time 50494598049 ps
CPU time 268.44 seconds
Started Jul 15 06:01:39 PM PDT 24
Finished Jul 15 06:06:08 PM PDT 24
Peak memory 214356 kb
Host smart-8a423b4e-54b7-4307-80de-b187bdcd8996
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690063882 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.690063882
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1839139608
Short name T13
Test name
Test status
Simulation time 34500457035 ps
CPU time 52.52 seconds
Started Jul 15 06:01:40 PM PDT 24
Finished Jul 15 06:02:33 PM PDT 24
Peak memory 198292 kb
Host smart-c7183303-a35c-4c44-bf2f-0908ca974b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839139608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1839139608
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3574646546
Short name T93
Test name
Test status
Simulation time 72848856697 ps
CPU time 25.53 seconds
Started Jul 15 06:02:03 PM PDT 24
Finished Jul 15 06:02:30 PM PDT 24
Peak memory 191888 kb
Host smart-19bc1b13-a524-49fe-9971-48053fd52f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574646546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3574646546
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.169444140
Short name T168
Test name
Test status
Simulation time 22600699868 ps
CPU time 9.79 seconds
Started Jul 15 06:01:47 PM PDT 24
Finished Jul 15 06:01:58 PM PDT 24
Peak memory 198244 kb
Host smart-995f4dd5-86a1-490a-a079-01de29db520f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169444140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.169444140
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3450086367
Short name T137
Test name
Test status
Simulation time 70643892001 ps
CPU time 129.35 seconds
Started Jul 15 06:01:38 PM PDT 24
Finished Jul 15 06:03:47 PM PDT 24
Peak memory 206668 kb
Host smart-41ce21d5-f0ae-4000-b859-bfbe9403a69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450086367 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3450086367
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.968760544
Short name T20
Test name
Test status
Simulation time 39816010310 ps
CPU time 168.75 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:04:04 PM PDT 24
Peak memory 206764 kb
Host smart-fa9eb1f1-1959-4d28-9e57-bc208aeceb3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968760544 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.968760544
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.799108434
Short name T97
Test name
Test status
Simulation time 102636010417 ps
CPU time 34.17 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:01:51 PM PDT 24
Peak memory 191872 kb
Host smart-be9d3318-896f-4d9a-b51a-85ee1f143a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799108434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.799108434
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4117357286
Short name T154
Test name
Test status
Simulation time 76162523202 ps
CPU time 117.01 seconds
Started Jul 15 06:01:00 PM PDT 24
Finished Jul 15 06:02:58 PM PDT 24
Peak memory 198248 kb
Host smart-0fd9d9f0-17e9-42c2-a2c2-be250312c3ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117357286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4117357286
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2555768579
Short name T14
Test name
Test status
Simulation time 93607413910 ps
CPU time 118.24 seconds
Started Jul 15 06:01:13 PM PDT 24
Finished Jul 15 06:03:12 PM PDT 24
Peak memory 192908 kb
Host smart-0d70f894-d78e-46fb-b2bd-908b91e100f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555768579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2555768579
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3399255629
Short name T115
Test name
Test status
Simulation time 242469901701 ps
CPU time 317.74 seconds
Started Jul 15 06:01:24 PM PDT 24
Finished Jul 15 06:06:42 PM PDT 24
Peak memory 192568 kb
Host smart-09e68ed8-405e-42be-a499-a59b7c318eea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399255629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3399255629
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2014843796
Short name T176
Test name
Test status
Simulation time 510896468696 ps
CPU time 748.35 seconds
Started Jul 15 06:01:24 PM PDT 24
Finished Jul 15 06:13:53 PM PDT 24
Peak memory 184708 kb
Host smart-c9300703-2fb7-4a6d-bf15-5e723ab33008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014843796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2014843796
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3911147207
Short name T125
Test name
Test status
Simulation time 145869775415 ps
CPU time 74.78 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:02:42 PM PDT 24
Peak memory 192980 kb
Host smart-775c17e0-2bde-4b0f-98eb-9694e762eec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911147207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3911147207
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1495211429
Short name T34
Test name
Test status
Simulation time 80307053995 ps
CPU time 292.18 seconds
Started Jul 15 06:01:08 PM PDT 24
Finished Jul 15 06:06:01 PM PDT 24
Peak memory 200524 kb
Host smart-afcc2789-c98f-4a2a-aa66-10f03cab7fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495211429 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1495211429
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3074113436
Short name T119
Test name
Test status
Simulation time 559648589 ps
CPU time 0.89 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:01:27 PM PDT 24
Peak memory 196648 kb
Host smart-5e98d6c3-2c2b-4cdf-8082-0df697c568d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074113436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3074113436
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2483438407
Short name T116
Test name
Test status
Simulation time 574016363 ps
CPU time 0.67 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:01:51 PM PDT 24
Peak memory 196664 kb
Host smart-a0fb5272-5b3f-4ad7-a994-a3aa5d6118e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483438407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2483438407
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.4280343216
Short name T169
Test name
Test status
Simulation time 200692628986 ps
CPU time 135.23 seconds
Started Jul 15 06:01:20 PM PDT 24
Finished Jul 15 06:03:36 PM PDT 24
Peak memory 191828 kb
Host smart-27c33773-5267-4feb-9297-1f0dd1cbad30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280343216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.4280343216
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3215439802
Short name T134
Test name
Test status
Simulation time 57088545899 ps
CPU time 6.1 seconds
Started Jul 15 06:01:10 PM PDT 24
Finished Jul 15 06:01:17 PM PDT 24
Peak memory 191856 kb
Host smart-34b79376-e02d-480b-a442-bd90919c6bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215439802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3215439802
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3400087300
Short name T149
Test name
Test status
Simulation time 367639363 ps
CPU time 0.91 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:01:28 PM PDT 24
Peak memory 196680 kb
Host smart-b83059e5-b22f-4d8b-8829-5167745dd469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400087300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3400087300
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1798003129
Short name T153
Test name
Test status
Simulation time 460703240 ps
CPU time 1.3 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:01:28 PM PDT 24
Peak memory 196652 kb
Host smart-bd4d7162-6809-45b6-859c-658a5409d80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798003129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1798003129
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2000641181
Short name T41
Test name
Test status
Simulation time 512924199 ps
CPU time 0.82 seconds
Started Jul 15 06:01:40 PM PDT 24
Finished Jul 15 06:01:41 PM PDT 24
Peak memory 196680 kb
Host smart-409aa2cb-4c78-4c8d-8c37-9820833f39d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000641181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2000641181
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3770067059
Short name T132
Test name
Test status
Simulation time 503891667 ps
CPU time 0.76 seconds
Started Jul 15 06:01:11 PM PDT 24
Finished Jul 15 06:01:12 PM PDT 24
Peak memory 196596 kb
Host smart-51a7131a-2a54-4e4f-8423-544263115d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770067059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3770067059
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1764172884
Short name T144
Test name
Test status
Simulation time 165288978339 ps
CPU time 238.19 seconds
Started Jul 15 06:01:38 PM PDT 24
Finished Jul 15 06:05:37 PM PDT 24
Peak memory 198284 kb
Host smart-33899258-449b-4459-a142-41dc07070547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764172884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1764172884
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3605327701
Short name T136
Test name
Test status
Simulation time 263796908411 ps
CPU time 103.09 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:03:32 PM PDT 24
Peak memory 198268 kb
Host smart-be3258d0-0ee1-4714-9132-1a6729b3ac4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605327701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3605327701
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4271697898
Short name T122
Test name
Test status
Simulation time 291847711745 ps
CPU time 444.16 seconds
Started Jul 15 06:01:14 PM PDT 24
Finished Jul 15 06:08:39 PM PDT 24
Peak memory 191884 kb
Host smart-54cce57f-7179-4dcc-a378-d987dd05a830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271697898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4271697898
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3897891344
Short name T22
Test name
Test status
Simulation time 392548411 ps
CPU time 0.74 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:01:29 PM PDT 24
Peak memory 196596 kb
Host smart-27a81427-2093-4d88-9b99-b9dfc8c848c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897891344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3897891344
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2508778603
Short name T146
Test name
Test status
Simulation time 486798501 ps
CPU time 0.69 seconds
Started Jul 15 06:01:40 PM PDT 24
Finished Jul 15 06:01:42 PM PDT 24
Peak memory 196768 kb
Host smart-a35a2910-245f-4947-b273-45b904336ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508778603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2508778603
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3590527549
Short name T150
Test name
Test status
Simulation time 98537891257 ps
CPU time 8.44 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:01:58 PM PDT 24
Peak memory 193016 kb
Host smart-6873e811-5595-4a4c-aa2d-7e40c63fe6d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590527549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3590527549
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2235947716
Short name T112
Test name
Test status
Simulation time 561474266 ps
CPU time 1.38 seconds
Started Jul 15 06:01:14 PM PDT 24
Finished Jul 15 06:01:17 PM PDT 24
Peak memory 196756 kb
Host smart-ae53722c-f954-49ba-bdb3-7c5a491d81d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235947716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2235947716
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.4055653825
Short name T148
Test name
Test status
Simulation time 241177072840 ps
CPU time 345.28 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:07:14 PM PDT 24
Peak memory 198320 kb
Host smart-588ad96e-bc76-4f27-ba4f-c2dd655e68d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055653825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.4055653825
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2036018517
Short name T163
Test name
Test status
Simulation time 127947083770 ps
CPU time 50.57 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:02:18 PM PDT 24
Peak memory 191924 kb
Host smart-0cc38fe3-fc10-453e-b522-271ef124eafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036018517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2036018517
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2473111390
Short name T96
Test name
Test status
Simulation time 3472214643 ps
CPU time 5.74 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:01:34 PM PDT 24
Peak memory 191820 kb
Host smart-23489efa-4149-4cca-9f83-42959f6944dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473111390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2473111390
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.985565176
Short name T171
Test name
Test status
Simulation time 17853023092 ps
CPU time 174.99 seconds
Started Jul 15 06:01:32 PM PDT 24
Finished Jul 15 06:04:27 PM PDT 24
Peak memory 198616 kb
Host smart-9a92874f-abfc-4025-9685-f24e68d3813d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985565176 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.985565176
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3401555750
Short name T166
Test name
Test status
Simulation time 563420660043 ps
CPU time 217.53 seconds
Started Jul 15 06:01:18 PM PDT 24
Finished Jul 15 06:04:56 PM PDT 24
Peak memory 198264 kb
Host smart-66a28298-0f0e-4b3d-b828-6f44ae6efbec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401555750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3401555750
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.7399294
Short name T156
Test name
Test status
Simulation time 365221720 ps
CPU time 0.86 seconds
Started Jul 15 06:01:41 PM PDT 24
Finished Jul 15 06:01:42 PM PDT 24
Peak memory 196680 kb
Host smart-9b6a59c0-c269-47ea-b083-12ffffc415a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7399294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.7399294
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2820687683
Short name T133
Test name
Test status
Simulation time 375458218 ps
CPU time 1.16 seconds
Started Jul 15 06:01:40 PM PDT 24
Finished Jul 15 06:01:42 PM PDT 24
Peak memory 196704 kb
Host smart-26ff2c34-3811-4916-a4e7-b4b0f7dad794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820687683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2820687683
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4247040440
Short name T143
Test name
Test status
Simulation time 144904771600 ps
CPU time 116.49 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:03:14 PM PDT 24
Peak memory 198280 kb
Host smart-bc1585ae-ffa4-4b46-afcf-3c60cdbde1b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247040440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4247040440
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2454141022
Short name T161
Test name
Test status
Simulation time 417274718 ps
CPU time 1.27 seconds
Started Jul 15 06:01:58 PM PDT 24
Finished Jul 15 06:02:00 PM PDT 24
Peak memory 196740 kb
Host smart-86bdf8c3-bf08-4c9e-8a95-857fe4c0206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454141022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2454141022
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3102248860
Short name T177
Test name
Test status
Simulation time 181525529591 ps
CPU time 388.16 seconds
Started Jul 15 06:02:01 PM PDT 24
Finished Jul 15 06:08:30 PM PDT 24
Peak memory 210376 kb
Host smart-bd1c64ac-e1f2-4d33-bf35-fa1ae2957212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102248860 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3102248860
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2820544140
Short name T128
Test name
Test status
Simulation time 426616942 ps
CPU time 0.75 seconds
Started Jul 15 06:01:46 PM PDT 24
Finished Jul 15 06:01:47 PM PDT 24
Peak memory 196664 kb
Host smart-b62c8d2f-d2c6-4e8b-a88e-e72243358d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820544140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2820544140
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2421343246
Short name T25
Test name
Test status
Simulation time 47504041318 ps
CPU time 40.76 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:02:31 PM PDT 24
Peak memory 198320 kb
Host smart-d2115577-f486-478c-9c10-5fc466d2b416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421343246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2421343246
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.881946523
Short name T140
Test name
Test status
Simulation time 524410753 ps
CPU time 0.76 seconds
Started Jul 15 06:01:13 PM PDT 24
Finished Jul 15 06:01:15 PM PDT 24
Peak memory 196748 kb
Host smart-115875f8-0ba7-4fb1-9bd9-3b0ef9f4579a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881946523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.881946523
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.4008541189
Short name T114
Test name
Test status
Simulation time 502841293 ps
CPU time 1.04 seconds
Started Jul 15 06:01:22 PM PDT 24
Finished Jul 15 06:01:23 PM PDT 24
Peak memory 196696 kb
Host smart-bf4aa3f8-a76b-42d2-bedb-6f3771aa84c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008541189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.4008541189
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2493514963
Short name T21
Test name
Test status
Simulation time 431403021 ps
CPU time 1.23 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:01:30 PM PDT 24
Peak memory 196796 kb
Host smart-37a40cdf-3a05-4b3f-a518-3e0e8689eedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493514963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2493514963
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2776711572
Short name T127
Test name
Test status
Simulation time 468062222 ps
CPU time 0.74 seconds
Started Jul 15 06:01:29 PM PDT 24
Finished Jul 15 06:01:30 PM PDT 24
Peak memory 196672 kb
Host smart-46809eff-db8f-4895-8a4d-7b1337ed9dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776711572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2776711572
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2395274579
Short name T151
Test name
Test status
Simulation time 68724206111 ps
CPU time 24.77 seconds
Started Jul 15 06:01:24 PM PDT 24
Finished Jul 15 06:01:50 PM PDT 24
Peak memory 191928 kb
Host smart-760ff233-1457-481d-b04e-96edacacad3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395274579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2395274579
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2220055995
Short name T123
Test name
Test status
Simulation time 499035950 ps
CPU time 1.27 seconds
Started Jul 15 06:01:57 PM PDT 24
Finished Jul 15 06:01:59 PM PDT 24
Peak memory 196652 kb
Host smart-8ab64374-cb15-46f2-93bc-9f92f5c20870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220055995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2220055995
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2485464759
Short name T139
Test name
Test status
Simulation time 256563579762 ps
CPU time 330.5 seconds
Started Jul 15 06:02:00 PM PDT 24
Finished Jul 15 06:07:32 PM PDT 24
Peak memory 198288 kb
Host smart-17fb5fc8-dd2f-46ce-aab9-41957be0a485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485464759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2485464759
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2130657873
Short name T172
Test name
Test status
Simulation time 63114609132 ps
CPU time 130.66 seconds
Started Jul 15 06:01:49 PM PDT 24
Finished Jul 15 06:04:02 PM PDT 24
Peak memory 198752 kb
Host smart-ebb192da-f098-405b-a020-e804b2278cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130657873 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2130657873
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4209669129
Short name T189
Test name
Test status
Simulation time 8429380853 ps
CPU time 11.29 seconds
Started Jul 15 05:31:47 PM PDT 24
Finished Jul 15 05:32:00 PM PDT 24
Peak memory 198172 kb
Host smart-47753457-119d-4acb-8df2-5bd676abe98a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209669129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.4209669129
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/21.aon_timer_jump.505595503
Short name T107
Test name
Test status
Simulation time 451205324 ps
CPU time 0.9 seconds
Started Jul 15 06:01:24 PM PDT 24
Finished Jul 15 06:01:25 PM PDT 24
Peak memory 196660 kb
Host smart-426cd259-17cf-4b8f-a6c6-5d2a9dd2e3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505595503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.505595503
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2287733601
Short name T117
Test name
Test status
Simulation time 457127711 ps
CPU time 1.26 seconds
Started Jul 15 06:01:47 PM PDT 24
Finished Jul 15 06:01:49 PM PDT 24
Peak memory 196656 kb
Host smart-719dee11-776a-4d9e-b7e7-395470e81ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287733601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2287733601
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3161543122
Short name T90
Test name
Test status
Simulation time 355354742 ps
CPU time 1.06 seconds
Started Jul 15 06:01:40 PM PDT 24
Finished Jul 15 06:01:42 PM PDT 24
Peak memory 196628 kb
Host smart-7a0893b1-12de-41d2-a710-8a5cce26c283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161543122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3161543122
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3255643796
Short name T135
Test name
Test status
Simulation time 446164491 ps
CPU time 0.64 seconds
Started Jul 15 06:01:49 PM PDT 24
Finished Jul 15 06:01:51 PM PDT 24
Peak memory 196684 kb
Host smart-47c5c423-c7c6-44c4-8253-99d52e54f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255643796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3255643796
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1089812513
Short name T142
Test name
Test status
Simulation time 421239231 ps
CPU time 0.73 seconds
Started Jul 15 06:01:19 PM PDT 24
Finished Jul 15 06:01:20 PM PDT 24
Peak memory 196700 kb
Host smart-5671282f-119f-4c6b-b6ca-6274c3af0e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089812513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1089812513
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2906881252
Short name T38
Test name
Test status
Simulation time 189501867902 ps
CPU time 363.08 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:07:20 PM PDT 24
Peak memory 202124 kb
Host smart-6c3e9dfb-42ef-43bb-94fd-dfe2978b34b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906881252 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2906881252
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2223667390
Short name T181
Test name
Test status
Simulation time 374373139 ps
CPU time 1.15 seconds
Started Jul 15 06:01:08 PM PDT 24
Finished Jul 15 06:01:09 PM PDT 24
Peak memory 196672 kb
Host smart-cbe26409-fdec-4e12-8e80-31e308223829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223667390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2223667390
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2240818025
Short name T162
Test name
Test status
Simulation time 174802240281 ps
CPU time 261.68 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:05:37 PM PDT 24
Peak memory 192904 kb
Host smart-482ec15a-3a01-4bc7-97cd-f4f8b073901e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240818025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2240818025
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1983207766
Short name T26
Test name
Test status
Simulation time 524000115 ps
CPU time 1.3 seconds
Started Jul 15 06:01:21 PM PDT 24
Finished Jul 15 06:01:22 PM PDT 24
Peak memory 196540 kb
Host smart-b80bb7d7-a8f5-4ee6-8717-ea9ac8e94f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983207766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1983207766
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2510984488
Short name T129
Test name
Test status
Simulation time 364975310 ps
CPU time 0.75 seconds
Started Jul 15 06:01:22 PM PDT 24
Finished Jul 15 06:01:23 PM PDT 24
Peak memory 196724 kb
Host smart-148be264-fe5e-45e8-b831-c762857dd5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510984488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2510984488
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3175799988
Short name T138
Test name
Test status
Simulation time 555822682 ps
CPU time 1.29 seconds
Started Jul 15 06:01:28 PM PDT 24
Finished Jul 15 06:01:31 PM PDT 24
Peak memory 196788 kb
Host smart-b1677d00-0325-414a-a435-fb61ceb388b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175799988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3175799988
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2557497294
Short name T39
Test name
Test status
Simulation time 473967206 ps
CPU time 1.07 seconds
Started Jul 15 06:01:08 PM PDT 24
Finished Jul 15 06:01:09 PM PDT 24
Peak memory 196628 kb
Host smart-b778d7c8-973c-46c7-82aa-47919f63f0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557497294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2557497294
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3717028075
Short name T46
Test name
Test status
Simulation time 165033276028 ps
CPU time 345.79 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:07:14 PM PDT 24
Peak memory 209664 kb
Host smart-c1ce995c-5ac2-4930-b290-992bbf896eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717028075 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3717028075
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.510940265
Short name T175
Test name
Test status
Simulation time 518673533 ps
CPU time 0.77 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:01:29 PM PDT 24
Peak memory 196636 kb
Host smart-1c362aeb-8f1b-47fe-a01c-12026d55f697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510940265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.510940265
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.51979570
Short name T152
Test name
Test status
Simulation time 204331674729 ps
CPU time 64.77 seconds
Started Jul 15 06:01:38 PM PDT 24
Finished Jul 15 06:02:44 PM PDT 24
Peak memory 192624 kb
Host smart-28f674e8-29b5-4c96-b505-2fa5f2e87b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51979570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_al
l.51979570
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2361235308
Short name T24
Test name
Test status
Simulation time 423980111 ps
CPU time 1.15 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:18 PM PDT 24
Peak memory 196728 kb
Host smart-4af32b7e-8504-45d0-b18a-43bfa193e221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361235308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2361235308
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2711316234
Short name T6
Test name
Test status
Simulation time 539257223 ps
CPU time 0.75 seconds
Started Jul 15 06:02:00 PM PDT 24
Finished Jul 15 06:02:01 PM PDT 24
Peak memory 196652 kb
Host smart-6925df90-6c51-4209-8e8d-3e57ba3b1dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711316234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2711316234
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3704227367
Short name T145
Test name
Test status
Simulation time 448190483 ps
CPU time 0.81 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:01:51 PM PDT 24
Peak memory 196752 kb
Host smart-8a5e8826-41f4-43ef-8a72-3b91519ce0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704227367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3704227367
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2824673439
Short name T27
Test name
Test status
Simulation time 476383522 ps
CPU time 0.72 seconds
Started Jul 15 06:01:47 PM PDT 24
Finished Jul 15 06:01:49 PM PDT 24
Peak memory 196708 kb
Host smart-ebeb982b-7bec-435c-a7c5-f7a89c53980f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824673439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2824673439
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3438103331
Short name T170
Test name
Test status
Simulation time 554457749 ps
CPU time 1.43 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:01:52 PM PDT 24
Peak memory 196768 kb
Host smart-9f66bab6-67c2-4095-b4ef-9d8c79617ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438103331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3438103331
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3370775171
Short name T179
Test name
Test status
Simulation time 574135685 ps
CPU time 1.19 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:01:18 PM PDT 24
Peak memory 196720 kb
Host smart-6352bfee-974c-4aa5-bf32-817fb996b141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370775171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3370775171
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1322590260
Short name T186
Test name
Test status
Simulation time 482467022 ps
CPU time 1.24 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:01:27 PM PDT 24
Peak memory 196612 kb
Host smart-0e0e484b-265d-47ab-8f56-1511dc496da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322590260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1322590260
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1667131403
Short name T160
Test name
Test status
Simulation time 574172021 ps
CPU time 1.41 seconds
Started Jul 15 06:01:24 PM PDT 24
Finished Jul 15 06:01:26 PM PDT 24
Peak memory 196700 kb
Host smart-35ec5470-2e32-4512-a517-431cc8d0ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667131403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1667131403
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2757768156
Short name T131
Test name
Test status
Simulation time 362824082 ps
CPU time 1.09 seconds
Started Jul 15 06:02:00 PM PDT 24
Finished Jul 15 06:02:02 PM PDT 24
Peak memory 196644 kb
Host smart-6ec3ccad-d5a5-42ec-90fe-1ce6244fa763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757768156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2757768156
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1699804468
Short name T184
Test name
Test status
Simulation time 584354451 ps
CPU time 0.8 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:01:50 PM PDT 24
Peak memory 196712 kb
Host smart-e435923c-4fec-47ad-b80d-8ea0c029f157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699804468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1699804468
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1796164972
Short name T180
Test name
Test status
Simulation time 595315412 ps
CPU time 0.82 seconds
Started Jul 15 06:01:17 PM PDT 24
Finished Jul 15 06:01:19 PM PDT 24
Peak memory 196632 kb
Host smart-47584991-4da1-4c7a-b3ca-eda31f4e16d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796164972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1796164972
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1191126517
Short name T195
Test name
Test status
Simulation time 4042971110 ps
CPU time 6.8 seconds
Started Jul 15 05:31:05 PM PDT 24
Finished Jul 15 05:31:13 PM PDT 24
Peak memory 197596 kb
Host smart-27d03760-cf37-4fca-881d-50a4bc628840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191126517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1191126517
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/24.aon_timer_jump.508143630
Short name T165
Test name
Test status
Simulation time 363836962 ps
CPU time 1.1 seconds
Started Jul 15 06:01:23 PM PDT 24
Finished Jul 15 06:01:24 PM PDT 24
Peak memory 196632 kb
Host smart-392b4b80-fd9f-49f1-bc42-ea06fab0b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508143630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.508143630
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3168559431
Short name T164
Test name
Test status
Simulation time 600792698 ps
CPU time 1.02 seconds
Started Jul 15 06:01:40 PM PDT 24
Finished Jul 15 06:01:42 PM PDT 24
Peak memory 196652 kb
Host smart-b7d34f87-f31e-49e0-a6ad-d956286c580e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168559431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3168559431
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.141898878
Short name T182
Test name
Test status
Simulation time 581755709 ps
CPU time 0.79 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:01:51 PM PDT 24
Peak memory 196636 kb
Host smart-1cb98630-dd9f-4848-9730-d987df1ab11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141898878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.141898878
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3351998626
Short name T3
Test name
Test status
Simulation time 567501954 ps
CPU time 1.39 seconds
Started Jul 15 06:01:51 PM PDT 24
Finished Jul 15 06:01:54 PM PDT 24
Peak memory 196724 kb
Host smart-4b44c94b-7790-4685-aee9-34ec9f063981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351998626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3351998626
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3242538879
Short name T183
Test name
Test status
Simulation time 449288547 ps
CPU time 1.23 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:18 PM PDT 24
Peak memory 196652 kb
Host smart-c4f299ee-f9fc-4623-9d58-42898ce79829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242538879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3242538879
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1030451068
Short name T64
Test name
Test status
Simulation time 510372395 ps
CPU time 1.66 seconds
Started Jul 15 05:31:12 PM PDT 24
Finished Jul 15 05:31:14 PM PDT 24
Peak memory 194408 kb
Host smart-e75538d3-1eb2-46d5-b3d6-237e165251df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030451068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1030451068
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3377058046
Short name T59
Test name
Test status
Simulation time 11687981994 ps
CPU time 26.47 seconds
Started Jul 15 05:31:10 PM PDT 24
Finished Jul 15 05:31:37 PM PDT 24
Peak memory 192176 kb
Host smart-2176051d-a05b-4de5-a584-5245d89d035d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377058046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3377058046
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.431762622
Short name T397
Test name
Test status
Simulation time 1137326664 ps
CPU time 0.95 seconds
Started Jul 15 05:31:10 PM PDT 24
Finished Jul 15 05:31:11 PM PDT 24
Peak memory 193120 kb
Host smart-ba4d8a8d-c647-4f84-87ce-78452f701321
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431762622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.431762622
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1724758693
Short name T379
Test name
Test status
Simulation time 420612063 ps
CPU time 0.8 seconds
Started Jul 15 05:31:07 PM PDT 24
Finished Jul 15 05:31:09 PM PDT 24
Peak memory 197048 kb
Host smart-63ef805c-3e1c-47b0-b2c8-1f91ac4120f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724758693 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1724758693
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.296307666
Short name T56
Test name
Test status
Simulation time 341061212 ps
CPU time 0.67 seconds
Started Jul 15 05:31:07 PM PDT 24
Finished Jul 15 05:31:08 PM PDT 24
Peak memory 191992 kb
Host smart-96ba3b60-bcc8-48ce-94c2-b151aeb3cfc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296307666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.296307666
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3510945301
Short name T328
Test name
Test status
Simulation time 298113530 ps
CPU time 0.74 seconds
Started Jul 15 05:31:11 PM PDT 24
Finished Jul 15 05:31:12 PM PDT 24
Peak memory 183732 kb
Host smart-aee13bb4-525e-4b2c-af20-0972234b37da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510945301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3510945301
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3800662818
Short name T290
Test name
Test status
Simulation time 346135558 ps
CPU time 0.57 seconds
Started Jul 15 05:31:11 PM PDT 24
Finished Jul 15 05:31:13 PM PDT 24
Peak memory 183656 kb
Host smart-1a3b0997-5c92-45ad-a57b-78ccba553d02
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800662818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3800662818
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1343270242
Short name T332
Test name
Test status
Simulation time 427523540 ps
CPU time 0.56 seconds
Started Jul 15 05:31:05 PM PDT 24
Finished Jul 15 05:31:06 PM PDT 24
Peak memory 183612 kb
Host smart-acb1bdef-c1e1-4df8-bb15-94d851f26424
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343270242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1343270242
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2651885266
Short name T383
Test name
Test status
Simulation time 2135560960 ps
CPU time 1.81 seconds
Started Jul 15 05:31:07 PM PDT 24
Finished Jul 15 05:31:10 PM PDT 24
Peak memory 194368 kb
Host smart-af884f9f-2a62-4bde-a7f6-7c94b357bc37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651885266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2651885266
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.207478025
Short name T375
Test name
Test status
Simulation time 304825032 ps
CPU time 2.02 seconds
Started Jul 15 05:31:11 PM PDT 24
Finished Jul 15 05:31:13 PM PDT 24
Peak memory 198624 kb
Host smart-f569eebc-c07c-45f5-812f-2ea6aedde086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207478025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.207478025
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.563450279
Short name T370
Test name
Test status
Simulation time 547708147 ps
CPU time 0.94 seconds
Started Jul 15 05:31:12 PM PDT 24
Finished Jul 15 05:31:14 PM PDT 24
Peak memory 183704 kb
Host smart-a7e4bd2b-9a84-4994-ba26-99779cb8133e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563450279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.563450279
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.724294136
Short name T70
Test name
Test status
Simulation time 11921203310 ps
CPU time 4.16 seconds
Started Jul 15 05:31:13 PM PDT 24
Finished Jul 15 05:31:18 PM PDT 24
Peak memory 196260 kb
Host smart-63a62467-af81-481c-8e8a-39a3cfa5b4f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724294136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.724294136
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.564073792
Short name T292
Test name
Test status
Simulation time 1022434007 ps
CPU time 0.76 seconds
Started Jul 15 05:31:12 PM PDT 24
Finished Jul 15 05:31:14 PM PDT 24
Peak memory 193256 kb
Host smart-fcbff464-d773-445c-a6c8-9edbd9472578
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564073792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.564073792
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.982289741
Short name T295
Test name
Test status
Simulation time 469889072 ps
CPU time 0.92 seconds
Started Jul 15 05:31:13 PM PDT 24
Finished Jul 15 05:31:15 PM PDT 24
Peak memory 195852 kb
Host smart-33d4e808-f320-4d2d-bbf5-e5998c98c2f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982289741 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.982289741
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.125903020
Short name T79
Test name
Test status
Simulation time 316080630 ps
CPU time 0.94 seconds
Started Jul 15 05:31:12 PM PDT 24
Finished Jul 15 05:31:14 PM PDT 24
Peak memory 193420 kb
Host smart-3f9b0646-6c27-4916-b6be-19f47eab7ef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125903020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.125903020
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3465638971
Short name T389
Test name
Test status
Simulation time 454827058 ps
CPU time 0.65 seconds
Started Jul 15 05:31:15 PM PDT 24
Finished Jul 15 05:31:17 PM PDT 24
Peak memory 183724 kb
Host smart-f46406bf-31ff-48ff-8512-8add6b15d064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465638971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3465638971
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1187095217
Short name T300
Test name
Test status
Simulation time 484648922 ps
CPU time 0.82 seconds
Started Jul 15 05:31:14 PM PDT 24
Finished Jul 15 05:31:15 PM PDT 24
Peak memory 183588 kb
Host smart-b65b7296-5554-4031-9c6f-a709f13a6bd9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187095217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1187095217
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.766991048
Short name T377
Test name
Test status
Simulation time 330780749 ps
CPU time 0.61 seconds
Started Jul 15 05:31:17 PM PDT 24
Finished Jul 15 05:31:19 PM PDT 24
Peak memory 183680 kb
Host smart-8698d8bf-0d72-403c-a3e2-30df05d84ded
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766991048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.766991048
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.374067942
Short name T361
Test name
Test status
Simulation time 2105607122 ps
CPU time 3.75 seconds
Started Jul 15 05:31:16 PM PDT 24
Finished Jul 15 05:31:21 PM PDT 24
Peak memory 193924 kb
Host smart-fbbd0308-42e3-49b6-ae84-c68848c08818
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374067942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.374067942
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2426128537
Short name T348
Test name
Test status
Simulation time 483687425 ps
CPU time 1.89 seconds
Started Jul 15 05:31:10 PM PDT 24
Finished Jul 15 05:31:12 PM PDT 24
Peak memory 198368 kb
Host smart-2de0fdbc-996f-4b94-b669-1036beb61818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426128537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2426128537
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.131056603
Short name T388
Test name
Test status
Simulation time 8410961019 ps
CPU time 7.34 seconds
Started Jul 15 05:31:12 PM PDT 24
Finished Jul 15 05:31:20 PM PDT 24
Peak memory 198228 kb
Host smart-ec232f0b-520f-4269-a21d-696176e5d183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131056603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.131056603
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2763618361
Short name T202
Test name
Test status
Simulation time 534263474 ps
CPU time 1.06 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:46 PM PDT 24
Peak memory 196592 kb
Host smart-c6fd16f4-e3a4-4060-b7c4-eed3ba947b12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763618361 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2763618361
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.493307041
Short name T62
Test name
Test status
Simulation time 368048371 ps
CPU time 1.23 seconds
Started Jul 15 05:31:39 PM PDT 24
Finished Jul 15 05:31:41 PM PDT 24
Peak memory 193896 kb
Host smart-b3299fb0-c05a-4f1c-b775-5105dbc3bd87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493307041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.493307041
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2925377500
Short name T416
Test name
Test status
Simulation time 492473411 ps
CPU time 0.66 seconds
Started Jul 15 05:31:37 PM PDT 24
Finished Jul 15 05:31:39 PM PDT 24
Peak memory 183704 kb
Host smart-d9cf6cce-2b8c-490c-a7fc-4ea080bd470b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925377500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2925377500
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4076605980
Short name T344
Test name
Test status
Simulation time 2265986619 ps
CPU time 4.71 seconds
Started Jul 15 05:31:40 PM PDT 24
Finished Jul 15 05:31:45 PM PDT 24
Peak memory 193888 kb
Host smart-641b0641-d6f6-42c1-a2df-068d199305bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076605980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.4076605980
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2406124910
Short name T337
Test name
Test status
Simulation time 922329982 ps
CPU time 2.6 seconds
Started Jul 15 05:31:38 PM PDT 24
Finished Jul 15 05:31:42 PM PDT 24
Peak memory 198596 kb
Host smart-6c96ee57-4396-4dc7-acce-7090ba0f456a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406124910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2406124910
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1132317737
Short name T192
Test name
Test status
Simulation time 8282360880 ps
CPU time 4.38 seconds
Started Jul 15 05:31:40 PM PDT 24
Finished Jul 15 05:31:45 PM PDT 24
Peak memory 198284 kb
Host smart-7284c932-3e33-4ac5-9389-e7ab4b7752de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132317737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1132317737
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2953999917
Short name T326
Test name
Test status
Simulation time 571137365 ps
CPU time 1.05 seconds
Started Jul 15 05:31:36 PM PDT 24
Finished Jul 15 05:31:38 PM PDT 24
Peak memory 195712 kb
Host smart-ec984f15-1a5d-4bf9-9824-7ee07a6adccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953999917 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2953999917
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4101886457
Short name T58
Test name
Test status
Simulation time 518058333 ps
CPU time 0.76 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:46 PM PDT 24
Peak memory 193300 kb
Host smart-eadcc896-348b-4f25-8bf7-c5c5a2731dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101886457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4101886457
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1581636180
Short name T324
Test name
Test status
Simulation time 376004320 ps
CPU time 1.09 seconds
Started Jul 15 05:31:38 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 183720 kb
Host smart-2a612b81-3779-424d-9917-8b9f7251389a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581636180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1581636180
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4209807557
Short name T345
Test name
Test status
Simulation time 1132262927 ps
CPU time 1.3 seconds
Started Jul 15 05:31:43 PM PDT 24
Finished Jul 15 05:31:45 PM PDT 24
Peak memory 193000 kb
Host smart-e9103876-72c9-4795-bbe2-d8f3a6956b61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209807557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.4209807557
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2454162543
Short name T363
Test name
Test status
Simulation time 417537962 ps
CPU time 2.1 seconds
Started Jul 15 05:31:41 PM PDT 24
Finished Jul 15 05:31:44 PM PDT 24
Peak memory 198516 kb
Host smart-eb5c2b22-58f1-4665-a9b7-4e09ca4fa440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454162543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2454162543
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.831070390
Short name T33
Test name
Test status
Simulation time 4354650149 ps
CPU time 5.93 seconds
Started Jul 15 05:31:40 PM PDT 24
Finished Jul 15 05:31:47 PM PDT 24
Peak memory 196616 kb
Host smart-0b7068b9-73ec-4129-b468-40e6b9f75f60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831070390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.831070390
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2112388760
Short name T199
Test name
Test status
Simulation time 536811203 ps
CPU time 0.92 seconds
Started Jul 15 05:31:37 PM PDT 24
Finished Jul 15 05:31:39 PM PDT 24
Peak memory 197076 kb
Host smart-42cc76b1-305c-4754-88a5-b66fdfa5ac1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112388760 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2112388760
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.465751904
Short name T65
Test name
Test status
Simulation time 320325231 ps
CPU time 1.06 seconds
Started Jul 15 05:31:39 PM PDT 24
Finished Jul 15 05:31:42 PM PDT 24
Peak memory 193420 kb
Host smart-c5aa3ffd-6cc5-4047-b885-ddf4b0c4f967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465751904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.465751904
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.565489502
Short name T371
Test name
Test status
Simulation time 443954885 ps
CPU time 1.26 seconds
Started Jul 15 05:31:40 PM PDT 24
Finished Jul 15 05:31:42 PM PDT 24
Peak memory 183728 kb
Host smart-c34bc244-3274-4157-891d-6e2d1ca0a518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565489502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.565489502
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3801823618
Short name T350
Test name
Test status
Simulation time 2424851116 ps
CPU time 2.42 seconds
Started Jul 15 05:31:39 PM PDT 24
Finished Jul 15 05:31:43 PM PDT 24
Peak memory 183948 kb
Host smart-5976a5d6-0605-4833-8f74-afe1f3f5c5ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801823618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3801823618
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4223826583
Short name T414
Test name
Test status
Simulation time 488122920 ps
CPU time 1.98 seconds
Started Jul 15 05:31:39 PM PDT 24
Finished Jul 15 05:31:42 PM PDT 24
Peak memory 198740 kb
Host smart-c6a07ba9-43fd-41a6-9f43-0f3ffca78974
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223826583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4223826583
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3817749898
Short name T356
Test name
Test status
Simulation time 8787757684 ps
CPU time 4.62 seconds
Started Jul 15 05:31:41 PM PDT 24
Finished Jul 15 05:31:47 PM PDT 24
Peak memory 198100 kb
Host smart-b26516d9-05f9-4d4a-a1bb-7580f0916a60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817749898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3817749898
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3973487079
Short name T336
Test name
Test status
Simulation time 427876436 ps
CPU time 1.24 seconds
Started Jul 15 05:31:38 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 196240 kb
Host smart-aad2ed3e-56d9-476c-884e-a70f4c60b448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973487079 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3973487079
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2083595787
Short name T415
Test name
Test status
Simulation time 408614848 ps
CPU time 0.81 seconds
Started Jul 15 05:31:39 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 183588 kb
Host smart-45f4fcb5-06b8-4a33-892f-1051bf1da17e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083595787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2083595787
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4249446388
Short name T399
Test name
Test status
Simulation time 1256163101 ps
CPU time 1.84 seconds
Started Jul 15 05:31:38 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 193932 kb
Host smart-e49ff543-0457-4332-9e13-330ae93bfc4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249446388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.4249446388
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1907584532
Short name T325
Test name
Test status
Simulation time 376307141 ps
CPU time 1.82 seconds
Started Jul 15 05:31:43 PM PDT 24
Finished Jul 15 05:31:46 PM PDT 24
Peak memory 198640 kb
Host smart-abe5b062-ade1-44a9-bf02-c3e7d17f6680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907584532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1907584532
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1615313199
Short name T346
Test name
Test status
Simulation time 7873582790 ps
CPU time 4.11 seconds
Started Jul 15 05:31:40 PM PDT 24
Finished Jul 15 05:31:45 PM PDT 24
Peak memory 198156 kb
Host smart-24778c23-0609-42ba-8cdb-0a6ff697694e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615313199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1615313199
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2148436750
Short name T321
Test name
Test status
Simulation time 626883153 ps
CPU time 1.59 seconds
Started Jul 15 05:31:46 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 196524 kb
Host smart-3b446262-725e-4143-94fb-48838f326c87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148436750 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2148436750
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2200936256
Short name T305
Test name
Test status
Simulation time 511565734 ps
CPU time 0.76 seconds
Started Jul 15 05:31:47 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 192712 kb
Host smart-2cfecb4f-e1b8-40d5-a48c-7ee3d9088ca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200936256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2200936256
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2954857388
Short name T298
Test name
Test status
Simulation time 493502042 ps
CPU time 0.67 seconds
Started Jul 15 05:31:48 PM PDT 24
Finished Jul 15 05:31:50 PM PDT 24
Peak memory 183700 kb
Host smart-9d0a7a71-b19a-4704-bb04-69df974be628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954857388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2954857388
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1158293834
Short name T74
Test name
Test status
Simulation time 1088446484 ps
CPU time 1.88 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:47 PM PDT 24
Peak memory 183820 kb
Host smart-24370f5d-639f-48ae-810c-a24b1471ed7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158293834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1158293834
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.624735881
Short name T347
Test name
Test status
Simulation time 301891448 ps
CPU time 2.48 seconds
Started Jul 15 05:31:37 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 198520 kb
Host smart-e6acbd32-59f1-4e3d-b42d-d069a530dde2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624735881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.624735881
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.583105357
Short name T190
Test name
Test status
Simulation time 4272568523 ps
CPU time 2.1 seconds
Started Jul 15 05:31:38 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 197568 kb
Host smart-6e11c612-73b1-4e03-9918-0389bbda7da4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583105357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.583105357
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2681544208
Short name T315
Test name
Test status
Simulation time 487855531 ps
CPU time 1.18 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:47 PM PDT 24
Peak memory 198432 kb
Host smart-0bbd4500-0aed-473d-b0a1-45e300d1a9ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681544208 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2681544208
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2452942782
Short name T335
Test name
Test status
Simulation time 293842845 ps
CPU time 0.87 seconds
Started Jul 15 05:31:48 PM PDT 24
Finished Jul 15 05:31:51 PM PDT 24
Peak memory 192968 kb
Host smart-e1a2bd10-1870-4ddc-94db-42dce41d55ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452942782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2452942782
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3842894017
Short name T333
Test name
Test status
Simulation time 297197250 ps
CPU time 0.64 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:46 PM PDT 24
Peak memory 183740 kb
Host smart-31859314-fe36-4e44-86ba-3f8226c0092c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842894017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3842894017
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2568048093
Short name T357
Test name
Test status
Simulation time 2119645554 ps
CPU time 1.15 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:46 PM PDT 24
Peak memory 191888 kb
Host smart-41fa8c25-3214-4d46-9867-b10bd970576c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568048093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2568048093
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1373874684
Short name T309
Test name
Test status
Simulation time 614735791 ps
CPU time 1.53 seconds
Started Jul 15 05:31:48 PM PDT 24
Finished Jul 15 05:31:50 PM PDT 24
Peak memory 198516 kb
Host smart-c3a980e2-99bd-4c8b-b243-7e74fa653922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373874684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1373874684
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2066079040
Short name T188
Test name
Test status
Simulation time 4299926547 ps
CPU time 7.13 seconds
Started Jul 15 05:31:49 PM PDT 24
Finished Jul 15 05:31:57 PM PDT 24
Peak memory 197800 kb
Host smart-317cafc7-8c29-4901-9d76-7075dfdd85a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066079040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2066079040
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1795674323
Short name T201
Test name
Test status
Simulation time 387375026 ps
CPU time 1.21 seconds
Started Jul 15 05:31:46 PM PDT 24
Finished Jul 15 05:31:48 PM PDT 24
Peak memory 195948 kb
Host smart-d8644ff0-5796-446c-ad4a-7e1ccdab3f70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795674323 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1795674323
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3675907153
Short name T68
Test name
Test status
Simulation time 443333268 ps
CPU time 1.1 seconds
Started Jul 15 05:31:48 PM PDT 24
Finished Jul 15 05:31:50 PM PDT 24
Peak memory 192992 kb
Host smart-5be5a388-265d-448a-8c9c-ad02961f356c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675907153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3675907153
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2704691174
Short name T380
Test name
Test status
Simulation time 342410717 ps
CPU time 0.98 seconds
Started Jul 15 05:31:48 PM PDT 24
Finished Jul 15 05:31:51 PM PDT 24
Peak memory 192688 kb
Host smart-c6c4f267-1a6a-4d5e-9a05-734980b94837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704691174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2704691174
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3487911641
Short name T75
Test name
Test status
Simulation time 1287739822 ps
CPU time 2.39 seconds
Started Jul 15 05:31:45 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 193120 kb
Host smart-1b704211-cfe0-49f6-ac5e-b442728e878c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487911641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3487911641
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1235335415
Short name T317
Test name
Test status
Simulation time 422801436 ps
CPU time 2.69 seconds
Started Jul 15 05:31:45 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 198644 kb
Host smart-cc50c38e-154e-4395-bb87-c2c1c8d27b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235335415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1235335415
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1672761486
Short name T405
Test name
Test status
Simulation time 4606177037 ps
CPU time 6.59 seconds
Started Jul 15 05:31:45 PM PDT 24
Finished Jul 15 05:31:53 PM PDT 24
Peak memory 197764 kb
Host smart-767877b9-55f6-4415-83de-790242c21bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672761486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1672761486
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3231196475
Short name T349
Test name
Test status
Simulation time 610276766 ps
CPU time 1.09 seconds
Started Jul 15 05:31:47 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 198352 kb
Host smart-58249adb-c01a-4a85-8560-a0fb2131c738
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231196475 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3231196475
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2317973515
Short name T409
Test name
Test status
Simulation time 532188292 ps
CPU time 1.34 seconds
Started Jul 15 05:31:45 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 192056 kb
Host smart-042174df-d3a6-426b-954b-b961d3271464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317973515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2317973515
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.844988725
Short name T314
Test name
Test status
Simulation time 398016894 ps
CPU time 1.04 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:46 PM PDT 24
Peak memory 183672 kb
Host smart-7ed92bf5-cbdf-4636-94ed-458f2096497a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844988725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.844988725
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.967066225
Short name T398
Test name
Test status
Simulation time 1270003139 ps
CPU time 3.03 seconds
Started Jul 15 05:31:46 PM PDT 24
Finished Jul 15 05:31:51 PM PDT 24
Peak memory 193696 kb
Host smart-1620250c-6b10-4b16-8373-b5b5e29c11ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967066225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.967066225
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1867296878
Short name T339
Test name
Test status
Simulation time 674386053 ps
CPU time 2.74 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 198568 kb
Host smart-b1f88825-d5af-4dd3-a386-8a891df1b020
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867296878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1867296878
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.4192440467
Short name T200
Test name
Test status
Simulation time 396752983 ps
CPU time 0.99 seconds
Started Jul 15 05:31:47 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 196532 kb
Host smart-7e52d8cc-edc7-4d7d-8da4-0d6211a46305
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192440467 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.4192440467
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.663089558
Short name T71
Test name
Test status
Simulation time 334898282 ps
CPU time 1.03 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:47 PM PDT 24
Peak memory 193408 kb
Host smart-4fccd20a-55e6-48fe-9c4a-dcbd47dd038a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663089558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.663089558
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3979104062
Short name T404
Test name
Test status
Simulation time 421469270 ps
CPU time 0.69 seconds
Started Jul 15 05:31:46 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 192952 kb
Host smart-d9f647fe-f3f3-4631-b438-3b8c22509302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979104062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3979104062
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1828327887
Short name T412
Test name
Test status
Simulation time 1332747382 ps
CPU time 1.5 seconds
Started Jul 15 05:31:46 PM PDT 24
Finished Jul 15 05:31:49 PM PDT 24
Peak memory 193008 kb
Host smart-78bed243-311d-4d4f-85b0-8e423c4da864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828327887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1828327887
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1708727798
Short name T387
Test name
Test status
Simulation time 484748592 ps
CPU time 1.91 seconds
Started Jul 15 05:31:48 PM PDT 24
Finished Jul 15 05:31:52 PM PDT 24
Peak memory 198344 kb
Host smart-5654f20d-9215-4b47-9941-c0e4d9341ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708727798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1708727798
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1127480576
Short name T390
Test name
Test status
Simulation time 307852083 ps
CPU time 1.01 seconds
Started Jul 15 05:31:48 PM PDT 24
Finished Jul 15 05:31:50 PM PDT 24
Peak memory 196060 kb
Host smart-e4d5ddf7-4b70-4977-a82e-8f68650ce430
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127480576 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1127480576
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1925806248
Short name T297
Test name
Test status
Simulation time 420749025 ps
CPU time 0.69 seconds
Started Jul 15 05:31:48 PM PDT 24
Finished Jul 15 05:31:50 PM PDT 24
Peak memory 192896 kb
Host smart-339d33a4-610d-49f9-91ab-30b7cc1423af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925806248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1925806248
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1529167375
Short name T303
Test name
Test status
Simulation time 507082450 ps
CPU time 1.22 seconds
Started Jul 15 05:31:44 PM PDT 24
Finished Jul 15 05:31:47 PM PDT 24
Peak memory 183728 kb
Host smart-86b19b9f-18b5-48d2-84f5-0a0869409bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529167375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1529167375
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2261446775
Short name T359
Test name
Test status
Simulation time 2935817756 ps
CPU time 2.49 seconds
Started Jul 15 05:31:48 PM PDT 24
Finished Jul 15 05:31:52 PM PDT 24
Peak memory 194436 kb
Host smart-0ffd462f-240c-4d4d-b7a9-18e6b01afeeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261446775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2261446775
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2926671163
Short name T316
Test name
Test status
Simulation time 677630136 ps
CPU time 1.47 seconds
Started Jul 15 05:31:47 PM PDT 24
Finished Jul 15 05:31:50 PM PDT 24
Peak memory 198300 kb
Host smart-56e649e9-aca3-4378-ae46-82799ca06f61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926671163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2926671163
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2942051783
Short name T191
Test name
Test status
Simulation time 4314083658 ps
CPU time 7.56 seconds
Started Jul 15 05:31:45 PM PDT 24
Finished Jul 15 05:31:54 PM PDT 24
Peak memory 197812 kb
Host smart-68ca35d1-280a-4fb0-803a-3a74fcd62a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942051783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2942051783
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.130375148
Short name T391
Test name
Test status
Simulation time 490368794 ps
CPU time 1.65 seconds
Started Jul 15 05:31:13 PM PDT 24
Finished Jul 15 05:31:16 PM PDT 24
Peak memory 191944 kb
Host smart-d20f3c0c-89f9-4091-bdf3-bf0b414a80e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130375148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.130375148
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3211162510
Short name T61
Test name
Test status
Simulation time 12378661692 ps
CPU time 8.36 seconds
Started Jul 15 05:31:13 PM PDT 24
Finished Jul 15 05:31:23 PM PDT 24
Peak memory 192232 kb
Host smart-b38335bc-fbb7-4025-a3f2-a18d16e4aff4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211162510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3211162510
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.64082773
Short name T304
Test name
Test status
Simulation time 769080134 ps
CPU time 0.77 seconds
Started Jul 15 05:31:11 PM PDT 24
Finished Jul 15 05:31:13 PM PDT 24
Peak memory 183676 kb
Host smart-7666c45a-e135-40e2-b926-aa465843968e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64082773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_
reset.64082773
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.862693156
Short name T407
Test name
Test status
Simulation time 528944332 ps
CPU time 1.14 seconds
Started Jul 15 05:31:14 PM PDT 24
Finished Jul 15 05:31:16 PM PDT 24
Peak memory 198316 kb
Host smart-bb9f1698-b63c-4a3c-b5a9-6fbe0267b863
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862693156 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.862693156
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2544793895
Short name T378
Test name
Test status
Simulation time 316733782 ps
CPU time 0.77 seconds
Started Jul 15 05:31:17 PM PDT 24
Finished Jul 15 05:31:19 PM PDT 24
Peak memory 192968 kb
Host smart-3034960b-bbad-4e81-a364-0c83af39ad51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544793895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2544793895
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3706942687
Short name T341
Test name
Test status
Simulation time 573188088 ps
CPU time 0.59 seconds
Started Jul 15 05:31:17 PM PDT 24
Finished Jul 15 05:31:19 PM PDT 24
Peak memory 192924 kb
Host smart-b6af99eb-7d08-4220-9ba7-b845534abec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706942687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3706942687
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3186781071
Short name T410
Test name
Test status
Simulation time 297686179 ps
CPU time 0.63 seconds
Started Jul 15 05:31:15 PM PDT 24
Finished Jul 15 05:31:17 PM PDT 24
Peak memory 183676 kb
Host smart-24f10630-b6a4-4b96-9125-9363ba5570ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186781071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3186781071
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2494405860
Short name T330
Test name
Test status
Simulation time 409650527 ps
CPU time 0.69 seconds
Started Jul 15 05:31:15 PM PDT 24
Finished Jul 15 05:31:17 PM PDT 24
Peak memory 183684 kb
Host smart-994504e3-51ec-4559-9460-5466abcac7d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494405860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2494405860
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3779177521
Short name T78
Test name
Test status
Simulation time 2022120434 ps
CPU time 2.68 seconds
Started Jul 15 05:31:13 PM PDT 24
Finished Jul 15 05:31:17 PM PDT 24
Peak memory 193620 kb
Host smart-8475a71d-7757-4832-bc59-0e162859ac87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779177521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3779177521
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.405506209
Short name T353
Test name
Test status
Simulation time 372342271 ps
CPU time 1.73 seconds
Started Jul 15 05:31:14 PM PDT 24
Finished Jul 15 05:31:17 PM PDT 24
Peak memory 198648 kb
Host smart-1eb8e3bb-5068-427e-bf44-ee07acf6ac93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405506209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.405506209
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2250960250
Short name T358
Test name
Test status
Simulation time 8344951028 ps
CPU time 12.14 seconds
Started Jul 15 05:31:17 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 198404 kb
Host smart-efc8c488-0d7d-4c36-bf4e-f18994f2f649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250960250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2250960250
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.358252092
Short name T294
Test name
Test status
Simulation time 505603229 ps
CPU time 1.17 seconds
Started Jul 15 05:31:57 PM PDT 24
Finished Jul 15 05:31:59 PM PDT 24
Peak memory 183732 kb
Host smart-82870f25-03c3-4b07-a17c-fde79b33cc05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358252092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.358252092
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1304138808
Short name T311
Test name
Test status
Simulation time 527418642 ps
CPU time 0.66 seconds
Started Jul 15 05:31:56 PM PDT 24
Finished Jul 15 05:31:58 PM PDT 24
Peak memory 192912 kb
Host smart-180cb126-a69c-4be5-af85-40cb64d1cf77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304138808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1304138808
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3646332788
Short name T386
Test name
Test status
Simulation time 344753812 ps
CPU time 0.75 seconds
Started Jul 15 05:31:57 PM PDT 24
Finished Jul 15 05:31:59 PM PDT 24
Peak memory 192868 kb
Host smart-f35eb5cd-452a-4c45-8d55-e099a7dc37d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646332788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3646332788
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2866132425
Short name T411
Test name
Test status
Simulation time 497902397 ps
CPU time 0.71 seconds
Started Jul 15 05:32:01 PM PDT 24
Finished Jul 15 05:32:03 PM PDT 24
Peak memory 183752 kb
Host smart-c9b9df45-298f-4583-ac69-755ab19aea0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866132425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2866132425
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3103136574
Short name T291
Test name
Test status
Simulation time 284589947 ps
CPU time 0.9 seconds
Started Jul 15 05:31:57 PM PDT 24
Finished Jul 15 05:31:59 PM PDT 24
Peak memory 192936 kb
Host smart-940a11c9-3e00-4bbc-bb19-1d94c07a6ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103136574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3103136574
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3109840437
Short name T372
Test name
Test status
Simulation time 346906668 ps
CPU time 0.69 seconds
Started Jul 15 05:31:56 PM PDT 24
Finished Jul 15 05:31:57 PM PDT 24
Peak memory 183624 kb
Host smart-0cbff4e2-cfe3-43c5-90c9-8d54be9ddd98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109840437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3109840437
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3957448903
Short name T334
Test name
Test status
Simulation time 429124387 ps
CPU time 1.07 seconds
Started Jul 15 05:31:59 PM PDT 24
Finished Jul 15 05:32:01 PM PDT 24
Peak memory 192944 kb
Host smart-b27cd6c0-4e8d-4da2-af1e-d0700f00cd42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957448903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3957448903
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2323994391
Short name T355
Test name
Test status
Simulation time 458048235 ps
CPU time 0.72 seconds
Started Jul 15 05:31:59 PM PDT 24
Finished Jul 15 05:32:01 PM PDT 24
Peak memory 183704 kb
Host smart-0cc9fbc4-33d5-4393-9834-78b05183e75c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323994391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2323994391
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2664877891
Short name T406
Test name
Test status
Simulation time 308272228 ps
CPU time 0.65 seconds
Started Jul 15 05:31:56 PM PDT 24
Finished Jul 15 05:31:58 PM PDT 24
Peak memory 183740 kb
Host smart-bfe9ccac-2061-44b7-92ae-064aeb0a1f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664877891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2664877891
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.725240262
Short name T338
Test name
Test status
Simulation time 369931549 ps
CPU time 0.65 seconds
Started Jul 15 05:31:56 PM PDT 24
Finished Jul 15 05:31:58 PM PDT 24
Peak memory 192920 kb
Host smart-88358172-f4e0-47c5-b6fc-0e8c563b0524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725240262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.725240262
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1181303521
Short name T66
Test name
Test status
Simulation time 598476741 ps
CPU time 0.97 seconds
Started Jul 15 05:31:20 PM PDT 24
Finished Jul 15 05:31:21 PM PDT 24
Peak memory 194228 kb
Host smart-86217fb6-be66-46b4-8709-8fcf0fc62649
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181303521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1181303521
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1101061042
Short name T403
Test name
Test status
Simulation time 12564307355 ps
CPU time 9.85 seconds
Started Jul 15 05:31:20 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 195580 kb
Host smart-5ad8e70c-998e-4fa8-8b39-449fed4013d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101061042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1101061042
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2319294667
Short name T417
Test name
Test status
Simulation time 944438911 ps
CPU time 0.69 seconds
Started Jul 15 05:31:29 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 193184 kb
Host smart-a1b49ebc-6ad2-452c-87e9-131e98942997
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319294667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2319294667
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.613135882
Short name T364
Test name
Test status
Simulation time 581866834 ps
CPU time 1.55 seconds
Started Jul 15 05:31:24 PM PDT 24
Finished Jul 15 05:31:27 PM PDT 24
Peak memory 196544 kb
Host smart-5b64bb2f-472e-4c0c-8118-9d1766f06ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613135882 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.613135882
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3548648866
Short name T60
Test name
Test status
Simulation time 664561700 ps
CPU time 0.62 seconds
Started Jul 15 05:31:23 PM PDT 24
Finished Jul 15 05:31:24 PM PDT 24
Peak memory 193388 kb
Host smart-6ea4c437-fddc-4eae-8a6f-72047f1f10a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548648866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3548648866
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1760895184
Short name T323
Test name
Test status
Simulation time 355832062 ps
CPU time 1.07 seconds
Started Jul 15 05:31:25 PM PDT 24
Finished Jul 15 05:31:26 PM PDT 24
Peak memory 183700 kb
Host smart-0b48a644-3a45-4891-b51c-1767a1f6a20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760895184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1760895184
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.198196633
Short name T318
Test name
Test status
Simulation time 461921226 ps
CPU time 1.2 seconds
Started Jul 15 05:31:28 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 183628 kb
Host smart-9930d9b7-c068-49f6-9fd5-82221c5c2460
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198196633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.198196633
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2553188575
Short name T293
Test name
Test status
Simulation time 329468976 ps
CPU time 0.74 seconds
Started Jul 15 05:31:21 PM PDT 24
Finished Jul 15 05:31:23 PM PDT 24
Peak memory 183736 kb
Host smart-3df95fc9-33e2-4c7c-a335-fd8cfe8dd460
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553188575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2553188575
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4175764246
Short name T413
Test name
Test status
Simulation time 1441222913 ps
CPU time 1.81 seconds
Started Jul 15 05:31:24 PM PDT 24
Finished Jul 15 05:31:26 PM PDT 24
Peak memory 183712 kb
Host smart-50af6c69-305d-4917-b453-918442082e38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175764246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.4175764246
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4177873074
Short name T354
Test name
Test status
Simulation time 657600700 ps
CPU time 2.18 seconds
Started Jul 15 05:31:16 PM PDT 24
Finished Jul 15 05:31:20 PM PDT 24
Peak memory 198612 kb
Host smart-18777a6a-3728-4c66-ae81-3ac624978c71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177873074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4177873074
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4119643012
Short name T193
Test name
Test status
Simulation time 8727981081 ps
CPU time 2.85 seconds
Started Jul 15 05:31:23 PM PDT 24
Finished Jul 15 05:31:27 PM PDT 24
Peak memory 198148 kb
Host smart-bf6a5426-a89b-4147-bb14-0e9865c1b362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119643012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.4119643012
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2672013189
Short name T313
Test name
Test status
Simulation time 342882303 ps
CPU time 0.63 seconds
Started Jul 15 05:31:56 PM PDT 24
Finished Jul 15 05:31:58 PM PDT 24
Peak memory 183696 kb
Host smart-bbac5d10-9d75-47dc-907c-aea49bc5e4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672013189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2672013189
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.355997919
Short name T408
Test name
Test status
Simulation time 358793242 ps
CPU time 0.71 seconds
Started Jul 15 05:31:59 PM PDT 24
Finished Jul 15 05:32:00 PM PDT 24
Peak memory 183724 kb
Host smart-ff0797ab-7f2e-4c9b-ad9e-226c9d0ae1f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355997919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.355997919
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3702911398
Short name T401
Test name
Test status
Simulation time 280389803 ps
CPU time 0.92 seconds
Started Jul 15 05:31:55 PM PDT 24
Finished Jul 15 05:31:56 PM PDT 24
Peak memory 183648 kb
Host smart-1fb939c9-ba6d-4528-a393-dd97ea9bd146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702911398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3702911398
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.4242530057
Short name T394
Test name
Test status
Simulation time 434023668 ps
CPU time 0.58 seconds
Started Jul 15 05:31:58 PM PDT 24
Finished Jul 15 05:32:00 PM PDT 24
Peak memory 183732 kb
Host smart-a1c01800-a649-4efa-b413-e2d7c618ac84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242530057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.4242530057
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2775647354
Short name T312
Test name
Test status
Simulation time 326640229 ps
CPU time 0.61 seconds
Started Jul 15 05:31:55 PM PDT 24
Finished Jul 15 05:31:56 PM PDT 24
Peak memory 183668 kb
Host smart-3d6672c7-0d6b-434b-9c84-d93fe755e289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775647354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2775647354
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3171447986
Short name T327
Test name
Test status
Simulation time 397820010 ps
CPU time 0.7 seconds
Started Jul 15 05:31:58 PM PDT 24
Finished Jul 15 05:32:00 PM PDT 24
Peak memory 183184 kb
Host smart-11ef037d-0a66-4e59-a75c-e600bbc65c82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171447986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3171447986
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3581871236
Short name T385
Test name
Test status
Simulation time 468919821 ps
CPU time 0.71 seconds
Started Jul 15 05:31:57 PM PDT 24
Finished Jul 15 05:31:59 PM PDT 24
Peak memory 183732 kb
Host smart-cf9b9df3-0813-4ed4-9cae-1785a1e32917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581871236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3581871236
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1643814151
Short name T299
Test name
Test status
Simulation time 364943902 ps
CPU time 0.68 seconds
Started Jul 15 05:31:58 PM PDT 24
Finished Jul 15 05:32:00 PM PDT 24
Peak memory 183208 kb
Host smart-30195cbd-bea1-4a4c-b5cb-5f409bcb8cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643814151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1643814151
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1278523677
Short name T393
Test name
Test status
Simulation time 311955706 ps
CPU time 0.97 seconds
Started Jul 15 05:31:55 PM PDT 24
Finished Jul 15 05:31:57 PM PDT 24
Peak memory 183712 kb
Host smart-c240292c-8d31-4c98-b634-24deebb98550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278523677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1278523677
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.691570274
Short name T396
Test name
Test status
Simulation time 313031815 ps
CPU time 0.6 seconds
Started Jul 15 05:31:57 PM PDT 24
Finished Jul 15 05:31:59 PM PDT 24
Peak memory 183596 kb
Host smart-d1876f1b-fbd8-42dd-a682-b9670b70143c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691570274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.691570274
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1510737877
Short name T351
Test name
Test status
Simulation time 396881093 ps
CPU time 0.94 seconds
Started Jul 15 05:31:21 PM PDT 24
Finished Jul 15 05:31:23 PM PDT 24
Peak memory 183748 kb
Host smart-c113039e-d3dd-4ead-bc60-d158bf3e5364
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510737877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1510737877
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2597614128
Short name T392
Test name
Test status
Simulation time 6240851014 ps
CPU time 2.5 seconds
Started Jul 15 05:31:27 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 195440 kb
Host smart-7da36428-592a-42f9-a68a-b373a56fbb7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597614128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2597614128
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2562277683
Short name T69
Test name
Test status
Simulation time 924978161 ps
CPU time 0.81 seconds
Started Jul 15 05:31:18 PM PDT 24
Finished Jul 15 05:31:20 PM PDT 24
Peak memory 193004 kb
Host smart-c367d456-df8a-4586-b1e3-5e6965d10783
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562277683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2562277683
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1516109794
Short name T302
Test name
Test status
Simulation time 366855271 ps
CPU time 0.77 seconds
Started Jul 15 05:31:23 PM PDT 24
Finished Jul 15 05:31:24 PM PDT 24
Peak memory 195816 kb
Host smart-77c1e1b9-67a3-4f11-afd5-efb2c9db6444
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516109794 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1516109794
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1033929372
Short name T67
Test name
Test status
Simulation time 309785324 ps
CPU time 1.01 seconds
Started Jul 15 05:31:25 PM PDT 24
Finished Jul 15 05:31:27 PM PDT 24
Peak memory 192980 kb
Host smart-4887c18c-3be8-4ddf-819e-40b3251d7242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033929372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1033929372
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2271529552
Short name T352
Test name
Test status
Simulation time 375856684 ps
CPU time 1.06 seconds
Started Jul 15 05:31:25 PM PDT 24
Finished Jul 15 05:31:27 PM PDT 24
Peak memory 183660 kb
Host smart-299b425d-a290-412e-b9a4-5b2a4109c164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271529552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2271529552
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2682887095
Short name T395
Test name
Test status
Simulation time 280845800 ps
CPU time 0.7 seconds
Started Jul 15 05:31:21 PM PDT 24
Finished Jul 15 05:31:22 PM PDT 24
Peak memory 183676 kb
Host smart-89d10e3a-1f0d-48bc-8d1a-a8a5b99c5f41
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682887095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2682887095
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1080363547
Short name T368
Test name
Test status
Simulation time 352891862 ps
CPU time 0.64 seconds
Started Jul 15 05:31:28 PM PDT 24
Finished Jul 15 05:31:29 PM PDT 24
Peak memory 183720 kb
Host smart-6bef4efe-a8e0-47c2-9932-3d4b7fe1641a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080363547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1080363547
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1451587035
Short name T77
Test name
Test status
Simulation time 2179818084 ps
CPU time 6.45 seconds
Started Jul 15 05:31:27 PM PDT 24
Finished Jul 15 05:31:34 PM PDT 24
Peak memory 194040 kb
Host smart-decced55-f564-44db-8d5a-786b4ae4ca84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451587035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1451587035
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.720578186
Short name T384
Test name
Test status
Simulation time 1121755734 ps
CPU time 2.9 seconds
Started Jul 15 05:31:20 PM PDT 24
Finished Jul 15 05:31:23 PM PDT 24
Peak memory 198608 kb
Host smart-1f60baa4-2ae1-4bd6-abc4-0f832f50f582
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720578186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.720578186
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.130375255
Short name T360
Test name
Test status
Simulation time 4127538470 ps
CPU time 4.22 seconds
Started Jul 15 05:31:23 PM PDT 24
Finished Jul 15 05:31:28 PM PDT 24
Peak memory 197608 kb
Host smart-44a42f57-61c8-45a6-ab7f-4d0fcd06545d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130375255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.130375255
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.81375695
Short name T289
Test name
Test status
Simulation time 399581259 ps
CPU time 0.84 seconds
Started Jul 15 05:31:56 PM PDT 24
Finished Jul 15 05:31:57 PM PDT 24
Peak memory 183728 kb
Host smart-352f20c1-9d46-4e98-9d6c-9c4099dcdf16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81375695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.81375695
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4292594653
Short name T306
Test name
Test status
Simulation time 487938389 ps
CPU time 1.15 seconds
Started Jul 15 05:31:59 PM PDT 24
Finished Jul 15 05:32:01 PM PDT 24
Peak memory 183644 kb
Host smart-b171a1f6-ec0f-432e-b1bf-b21a9e597a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292594653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4292594653
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1761288146
Short name T342
Test name
Test status
Simulation time 434843274 ps
CPU time 0.89 seconds
Started Jul 15 05:31:58 PM PDT 24
Finished Jul 15 05:32:00 PM PDT 24
Peak memory 192952 kb
Host smart-59704e98-cdfc-4085-8f48-c92d024ad836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761288146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1761288146
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2602926780
Short name T365
Test name
Test status
Simulation time 445918345 ps
CPU time 0.57 seconds
Started Jul 15 05:31:57 PM PDT 24
Finished Jul 15 05:31:59 PM PDT 24
Peak memory 183740 kb
Host smart-5940f55a-2f70-40df-8a05-afb756864bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602926780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2602926780
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1926241794
Short name T362
Test name
Test status
Simulation time 380032065 ps
CPU time 0.66 seconds
Started Jul 15 05:31:57 PM PDT 24
Finished Jul 15 05:31:58 PM PDT 24
Peak memory 183596 kb
Host smart-e5379af2-5a40-4dd2-95a1-1bffa62af9b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926241794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1926241794
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.745397189
Short name T366
Test name
Test status
Simulation time 315283323 ps
CPU time 1.02 seconds
Started Jul 15 05:31:56 PM PDT 24
Finished Jul 15 05:31:58 PM PDT 24
Peak memory 192856 kb
Host smart-173d2b8d-fe4a-45e9-8016-f923161f5149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745397189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.745397189
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2667457864
Short name T419
Test name
Test status
Simulation time 369242924 ps
CPU time 1.07 seconds
Started Jul 15 05:32:01 PM PDT 24
Finished Jul 15 05:32:03 PM PDT 24
Peak memory 192972 kb
Host smart-0d08e501-c378-4649-aad0-368d4c2744ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667457864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2667457864
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.468958803
Short name T301
Test name
Test status
Simulation time 331037279 ps
CPU time 0.67 seconds
Started Jul 15 05:31:56 PM PDT 24
Finished Jul 15 05:31:57 PM PDT 24
Peak memory 192964 kb
Host smart-c378c1fa-6f21-4217-bc0a-263f7834ba5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468958803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.468958803
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1092769936
Short name T402
Test name
Test status
Simulation time 501713525 ps
CPU time 0.69 seconds
Started Jul 15 05:31:55 PM PDT 24
Finished Jul 15 05:31:56 PM PDT 24
Peak memory 183620 kb
Host smart-e64dd337-204b-40c0-abd4-a4088f384061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092769936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1092769936
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4226106095
Short name T296
Test name
Test status
Simulation time 463650544 ps
CPU time 1.27 seconds
Started Jul 15 05:31:59 PM PDT 24
Finished Jul 15 05:32:01 PM PDT 24
Peak memory 192940 kb
Host smart-94628230-a5ba-44f1-8a66-4276b8d20ca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226106095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4226106095
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.231812242
Short name T340
Test name
Test status
Simulation time 438570779 ps
CPU time 0.93 seconds
Started Jul 15 05:31:21 PM PDT 24
Finished Jul 15 05:31:22 PM PDT 24
Peak memory 195944 kb
Host smart-3a18d3bf-9ff1-4143-9d25-6331b22d9f48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231812242 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.231812242
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1604173042
Short name T73
Test name
Test status
Simulation time 510531015 ps
CPU time 0.98 seconds
Started Jul 15 05:31:28 PM PDT 24
Finished Jul 15 05:31:29 PM PDT 24
Peak memory 192064 kb
Host smart-49599b9f-56df-4a24-b728-9f5c35b30474
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604173042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1604173042
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.366607186
Short name T308
Test name
Test status
Simulation time 511522268 ps
CPU time 1.31 seconds
Started Jul 15 05:31:22 PM PDT 24
Finished Jul 15 05:31:23 PM PDT 24
Peak memory 192948 kb
Host smart-6d49cccd-6eed-4c35-80d4-ad4df42e7aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366607186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.366607186
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.850900119
Short name T382
Test name
Test status
Simulation time 1234716082 ps
CPU time 2.73 seconds
Started Jul 15 05:31:19 PM PDT 24
Finished Jul 15 05:31:23 PM PDT 24
Peak memory 183812 kb
Host smart-c26fb6d8-4848-4599-a64c-5d99a389ab50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850900119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.850900119
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1626248918
Short name T367
Test name
Test status
Simulation time 349806728 ps
CPU time 1.93 seconds
Started Jul 15 05:31:27 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 198484 kb
Host smart-e51d0563-431e-48c6-80f1-6858df4a0462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626248918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1626248918
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1010901795
Short name T381
Test name
Test status
Simulation time 4457316238 ps
CPU time 7.68 seconds
Started Jul 15 05:31:17 PM PDT 24
Finished Jul 15 05:31:26 PM PDT 24
Peak memory 197656 kb
Host smart-43abf334-fe25-4bb7-82e6-1bb112caa1d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010901795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1010901795
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2097020825
Short name T322
Test name
Test status
Simulation time 592480271 ps
CPU time 1.09 seconds
Started Jul 15 05:31:28 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 196264 kb
Host smart-10ad494d-d0cf-416e-9e3b-bf4a481d57a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097020825 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2097020825
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2686686265
Short name T29
Test name
Test status
Simulation time 535297240 ps
CPU time 1.21 seconds
Started Jul 15 05:31:27 PM PDT 24
Finished Jul 15 05:31:29 PM PDT 24
Peak memory 193204 kb
Host smart-72086655-84ad-437e-a41e-b657cb51cabc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686686265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2686686265
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1725593283
Short name T288
Test name
Test status
Simulation time 316355957 ps
CPU time 0.64 seconds
Started Jul 15 05:31:20 PM PDT 24
Finished Jul 15 05:31:21 PM PDT 24
Peak memory 183728 kb
Host smart-dbb35e4e-1868-4400-860d-6a754ed8204a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725593283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1725593283
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2058624239
Short name T373
Test name
Test status
Simulation time 2669002551 ps
CPU time 1.36 seconds
Started Jul 15 05:31:29 PM PDT 24
Finished Jul 15 05:31:31 PM PDT 24
Peak memory 194416 kb
Host smart-713aad48-7032-4a87-93fb-ce7d450de661
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058624239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2058624239
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1265812640
Short name T369
Test name
Test status
Simulation time 456191867 ps
CPU time 1.37 seconds
Started Jul 15 05:31:23 PM PDT 24
Finished Jul 15 05:31:25 PM PDT 24
Peak memory 198628 kb
Host smart-82191304-89bb-43b8-9079-9f6f16a5e25a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265812640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1265812640
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4054257908
Short name T400
Test name
Test status
Simulation time 3935230463 ps
CPU time 6.18 seconds
Started Jul 15 05:31:19 PM PDT 24
Finished Jul 15 05:31:26 PM PDT 24
Peak memory 197948 kb
Host smart-9ad5d19b-89ab-4ade-959f-a1115355997e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054257908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.4054257908
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3817066798
Short name T376
Test name
Test status
Simulation time 639306272 ps
CPU time 1.19 seconds
Started Jul 15 05:31:29 PM PDT 24
Finished Jul 15 05:31:31 PM PDT 24
Peak memory 197108 kb
Host smart-6c5fc84d-f33a-4927-9d7b-980127fa9682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817066798 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3817066798
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3466038513
Short name T320
Test name
Test status
Simulation time 339837980 ps
CPU time 0.73 seconds
Started Jul 15 05:31:30 PM PDT 24
Finished Jul 15 05:31:31 PM PDT 24
Peak memory 193252 kb
Host smart-4c491b81-5e5e-43a2-a21b-ab102eab5a89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466038513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3466038513
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2057501426
Short name T331
Test name
Test status
Simulation time 304735237 ps
CPU time 0.9 seconds
Started Jul 15 05:31:29 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 183704 kb
Host smart-f34d8c85-a39d-4889-86ff-e173a49ba611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057501426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2057501426
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4123533219
Short name T420
Test name
Test status
Simulation time 2238812274 ps
CPU time 3.13 seconds
Started Jul 15 05:31:27 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 194784 kb
Host smart-ea61aa62-5aca-4fb5-93a9-31ea25ea05a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123533219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.4123533219
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3947252016
Short name T287
Test name
Test status
Simulation time 1066502093 ps
CPU time 2.29 seconds
Started Jul 15 05:31:28 PM PDT 24
Finished Jul 15 05:31:31 PM PDT 24
Peak memory 198628 kb
Host smart-aeef849f-b43f-4f32-afe1-6f9bfbfe551b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947252016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3947252016
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4137893109
Short name T418
Test name
Test status
Simulation time 4322619175 ps
CPU time 3.88 seconds
Started Jul 15 05:31:31 PM PDT 24
Finished Jul 15 05:31:35 PM PDT 24
Peak memory 197648 kb
Host smart-d844a2d2-d873-4c74-8f9e-79c7dca92468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137893109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.4137893109
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2181049500
Short name T329
Test name
Test status
Simulation time 630757590 ps
CPU time 1.02 seconds
Started Jul 15 05:31:33 PM PDT 24
Finished Jul 15 05:31:34 PM PDT 24
Peak memory 198348 kb
Host smart-5b1275a6-c47b-4721-b5ae-a0fe7d730969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181049500 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2181049500
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1921239160
Short name T76
Test name
Test status
Simulation time 526497390 ps
CPU time 1.02 seconds
Started Jul 15 05:31:33 PM PDT 24
Finished Jul 15 05:31:34 PM PDT 24
Peak memory 192896 kb
Host smart-fd9669be-aedd-4fb7-815d-b19d0bdc0e07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921239160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1921239160
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2893938371
Short name T343
Test name
Test status
Simulation time 509877207 ps
CPU time 0.74 seconds
Started Jul 15 05:31:28 PM PDT 24
Finished Jul 15 05:31:30 PM PDT 24
Peak memory 183744 kb
Host smart-05c01203-c678-4916-a70d-55e63e202837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893938371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2893938371
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1400932082
Short name T30
Test name
Test status
Simulation time 1446552709 ps
CPU time 3.1 seconds
Started Jul 15 05:31:29 PM PDT 24
Finished Jul 15 05:31:33 PM PDT 24
Peak memory 193740 kb
Host smart-198129f7-bf3f-4e78-a07e-71909a34a269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400932082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1400932082
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.714929832
Short name T310
Test name
Test status
Simulation time 657627973 ps
CPU time 2.1 seconds
Started Jul 15 05:31:29 PM PDT 24
Finished Jul 15 05:31:32 PM PDT 24
Peak memory 198480 kb
Host smart-192dfcbd-6600-411e-ae2c-7aa8d273420a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714929832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.714929832
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.173913222
Short name T32
Test name
Test status
Simulation time 7908623369 ps
CPU time 8.73 seconds
Started Jul 15 05:31:28 PM PDT 24
Finished Jul 15 05:31:37 PM PDT 24
Peak memory 198312 kb
Host smart-1dea3918-2630-42c4-a6f1-e500edb5e207
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173913222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.173913222
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.201906692
Short name T374
Test name
Test status
Simulation time 445731641 ps
CPU time 1.08 seconds
Started Jul 15 05:31:39 PM PDT 24
Finished Jul 15 05:31:41 PM PDT 24
Peak memory 198452 kb
Host smart-fb9ec26f-b86b-403b-8f34-64e6364d1d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201906692 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.201906692
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2592081480
Short name T72
Test name
Test status
Simulation time 410230654 ps
CPU time 1.18 seconds
Started Jul 15 05:31:38 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 193144 kb
Host smart-364b199d-eecc-49da-bb98-1fa313139385
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592081480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2592081480
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3882177434
Short name T307
Test name
Test status
Simulation time 422412394 ps
CPU time 0.85 seconds
Started Jul 15 05:31:37 PM PDT 24
Finished Jul 15 05:31:38 PM PDT 24
Peak memory 183624 kb
Host smart-222516fb-be6d-4a7d-bc7a-616dfbe423eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882177434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3882177434
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.479819870
Short name T421
Test name
Test status
Simulation time 1129739469 ps
CPU time 0.86 seconds
Started Jul 15 05:31:38 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 193536 kb
Host smart-0caa5d8d-4fb4-4cad-93d5-a56c8f057c0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479819870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.479819870
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2963771844
Short name T319
Test name
Test status
Simulation time 516338168 ps
CPU time 1.1 seconds
Started Jul 15 05:31:38 PM PDT 24
Finished Jul 15 05:31:40 PM PDT 24
Peak memory 198228 kb
Host smart-7c476ffd-cdf7-4e23-88da-8fcf47bc47d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963771844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2963771844
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2402525437
Short name T194
Test name
Test status
Simulation time 7959104379 ps
CPU time 2.83 seconds
Started Jul 15 05:31:41 PM PDT 24
Finished Jul 15 05:31:44 PM PDT 24
Peak memory 198276 kb
Host smart-ff41437f-1e7b-404c-9b06-353b62413bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402525437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2402525437
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.951256296
Short name T207
Test name
Test status
Simulation time 42160424504 ps
CPU time 17.71 seconds
Started Jul 15 06:01:00 PM PDT 24
Finished Jul 15 06:01:19 PM PDT 24
Peak memory 196904 kb
Host smart-16aa5b2e-7de6-4dfb-8857-0d48a12e3111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951256296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.951256296
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2686782991
Short name T217
Test name
Test status
Simulation time 693933467 ps
CPU time 0.7 seconds
Started Jul 15 06:01:03 PM PDT 24
Finished Jul 15 06:01:04 PM PDT 24
Peak memory 191824 kb
Host smart-17101164-9eb4-4d86-ae6e-019745ddb8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686782991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2686782991
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.330508980
Short name T174
Test name
Test status
Simulation time 632878207 ps
CPU time 0.68 seconds
Started Jul 15 06:01:00 PM PDT 24
Finished Jul 15 06:01:01 PM PDT 24
Peak memory 196724 kb
Host smart-68474170-64b1-498d-bd3e-1a29b06e7b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330508980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.330508980
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.59291790
Short name T234
Test name
Test status
Simulation time 2375792024 ps
CPU time 1.31 seconds
Started Jul 15 06:01:00 PM PDT 24
Finished Jul 15 06:01:02 PM PDT 24
Peak memory 191884 kb
Host smart-59903564-56ae-4f75-9beb-d1f96baecb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59291790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.59291790
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3781194147
Short name T15
Test name
Test status
Simulation time 4224089776 ps
CPU time 2.09 seconds
Started Jul 15 06:01:06 PM PDT 24
Finished Jul 15 06:01:09 PM PDT 24
Peak memory 215336 kb
Host smart-968c24ab-69b2-464f-b419-790b1d34d2ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781194147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3781194147
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1126683566
Short name T237
Test name
Test status
Simulation time 516270588 ps
CPU time 0.67 seconds
Started Jul 15 06:01:00 PM PDT 24
Finished Jul 15 06:01:01 PM PDT 24
Peak memory 191756 kb
Host smart-e836f02d-be40-42b9-9957-de68e23a0792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126683566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1126683566
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3317458602
Short name T185
Test name
Test status
Simulation time 453539409 ps
CPU time 0.77 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:01:18 PM PDT 24
Peak memory 196708 kb
Host smart-d4b59e1d-86cb-40b6-9231-059bd438add7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317458602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3317458602
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2334095849
Short name T210
Test name
Test status
Simulation time 17352583696 ps
CPU time 24.65 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:40 PM PDT 24
Peak memory 191856 kb
Host smart-7fae9432-5c11-4dba-ae2a-f89c9396e990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334095849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2334095849
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3532760454
Short name T84
Test name
Test status
Simulation time 581976148 ps
CPU time 1.53 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:18 PM PDT 24
Peak memory 196648 kb
Host smart-f4e719d9-4e24-4c0e-8ceb-5f438fac7ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532760454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3532760454
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.465983451
Short name T286
Test name
Test status
Simulation time 32637392424 ps
CPU time 50.21 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:02:06 PM PDT 24
Peak memory 196944 kb
Host smart-8590f06e-b884-453c-ab57-10b25e07866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465983451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.465983451
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3777498693
Short name T218
Test name
Test status
Simulation time 440842251 ps
CPU time 1.08 seconds
Started Jul 15 06:01:17 PM PDT 24
Finished Jul 15 06:01:19 PM PDT 24
Peak memory 196628 kb
Host smart-7e83b662-acfc-4645-8d28-bf4a7bb5dd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777498693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3777498693
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.480646065
Short name T278
Test name
Test status
Simulation time 1607773147 ps
CPU time 1.11 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:01:18 PM PDT 24
Peak memory 191824 kb
Host smart-779f5acc-be5f-43c6-9f1c-0e38b27ba4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480646065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.480646065
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2132231828
Short name T256
Test name
Test status
Simulation time 437189485 ps
CPU time 1.25 seconds
Started Jul 15 06:01:18 PM PDT 24
Finished Jul 15 06:01:20 PM PDT 24
Peak memory 196720 kb
Host smart-d0ce94c3-b668-4341-9c73-3e61f705c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132231828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2132231828
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3276927456
Short name T35
Test name
Test status
Simulation time 23383204265 ps
CPU time 86.42 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:02:42 PM PDT 24
Peak memory 214748 kb
Host smart-37c00c28-3f14-4dc0-9be9-4bf79af66805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276927456 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3276927456
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.959168336
Short name T203
Test name
Test status
Simulation time 18421334860 ps
CPU time 6.48 seconds
Started Jul 15 06:01:20 PM PDT 24
Finished Jul 15 06:01:26 PM PDT 24
Peak memory 191948 kb
Host smart-e468d1f2-b487-4d97-9d69-253fa0d4c83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959168336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.959168336
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3440220975
Short name T257
Test name
Test status
Simulation time 489355540 ps
CPU time 0.74 seconds
Started Jul 15 06:01:13 PM PDT 24
Finished Jul 15 06:01:14 PM PDT 24
Peak memory 196680 kb
Host smart-665c7a9c-6743-4f1d-87bd-6fbde6c59eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440220975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3440220975
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.916316380
Short name T53
Test name
Test status
Simulation time 30837893416 ps
CPU time 49.09 seconds
Started Jul 15 06:01:18 PM PDT 24
Finished Jul 15 06:02:08 PM PDT 24
Peak memory 196944 kb
Host smart-3410b77c-0a02-4f99-82fd-c102dd3d44d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916316380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.916316380
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1250686677
Short name T232
Test name
Test status
Simulation time 512421995 ps
CPU time 0.97 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:01:19 PM PDT 24
Peak memory 191876 kb
Host smart-660a7f5d-f103-498d-a80d-2cd5f5ff599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250686677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1250686677
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.4150949369
Short name T258
Test name
Test status
Simulation time 19871725494 ps
CPU time 8.38 seconds
Started Jul 15 06:01:23 PM PDT 24
Finished Jul 15 06:01:32 PM PDT 24
Peak memory 191956 kb
Host smart-68748f89-33b3-44a8-9ec4-e99931d619ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150949369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.4150949369
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2826043972
Short name T247
Test name
Test status
Simulation time 572153017 ps
CPU time 0.95 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:01:28 PM PDT 24
Peak memory 191828 kb
Host smart-7e6f2647-96f8-42f1-932c-1c08763a1bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826043972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2826043972
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3071716580
Short name T44
Test name
Test status
Simulation time 59293309224 ps
CPU time 44.22 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:02:10 PM PDT 24
Peak memory 191916 kb
Host smart-1e3eb74b-f7a7-453e-8cce-73075428286f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071716580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3071716580
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2523209558
Short name T242
Test name
Test status
Simulation time 523129878 ps
CPU time 0.77 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:01:30 PM PDT 24
Peak memory 191248 kb
Host smart-3d559423-7889-4873-b685-d64cbfd96bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523209558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2523209558
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2053707486
Short name T274
Test name
Test status
Simulation time 23136986067 ps
CPU time 16.11 seconds
Started Jul 15 06:01:22 PM PDT 24
Finished Jul 15 06:01:39 PM PDT 24
Peak memory 196860 kb
Host smart-ae8a734e-6067-41ac-8c04-fd7fb383370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053707486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2053707486
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.312372787
Short name T264
Test name
Test status
Simulation time 388323274 ps
CPU time 0.72 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:01:28 PM PDT 24
Peak memory 196720 kb
Host smart-2ecaa2d8-0b0b-4ac7-b7f5-dcaf06f7f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312372787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.312372787
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1471542509
Short name T248
Test name
Test status
Simulation time 15768202305 ps
CPU time 164.03 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:04:10 PM PDT 24
Peak memory 198688 kb
Host smart-ae17c5a8-e55d-4394-92e0-52b1794bc56a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471542509 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1471542509
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2229465441
Short name T213
Test name
Test status
Simulation time 22402197139 ps
CPU time 15.27 seconds
Started Jul 15 06:01:23 PM PDT 24
Finished Jul 15 06:01:39 PM PDT 24
Peak memory 196944 kb
Host smart-cd853b2d-f97d-4a42-aca3-194f32e19f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229465441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2229465441
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3759743507
Short name T50
Test name
Test status
Simulation time 443323235 ps
CPU time 0.88 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:01:27 PM PDT 24
Peak memory 191852 kb
Host smart-f1b04eb4-6b17-4388-a231-7591833a5ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759743507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3759743507
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1597405385
Short name T240
Test name
Test status
Simulation time 9822730137 ps
CPU time 1.43 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:01:30 PM PDT 24
Peak memory 196516 kb
Host smart-be385ef0-1f31-40d9-b711-ad70829b4221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597405385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1597405385
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.4164762479
Short name T263
Test name
Test status
Simulation time 470431701 ps
CPU time 1.32 seconds
Started Jul 15 06:01:24 PM PDT 24
Finished Jul 15 06:01:26 PM PDT 24
Peak memory 191848 kb
Host smart-54c1a4d9-377e-4109-b540-70b93562b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164762479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.4164762479
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3862436376
Short name T267
Test name
Test status
Simulation time 29400257625 ps
CPU time 23.09 seconds
Started Jul 15 06:01:11 PM PDT 24
Finished Jul 15 06:01:34 PM PDT 24
Peak memory 192112 kb
Host smart-ff4188b7-7988-46d8-b585-64f6ee4b27e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862436376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3862436376
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3534589924
Short name T19
Test name
Test status
Simulation time 8019678618 ps
CPU time 13.14 seconds
Started Jul 15 06:01:09 PM PDT 24
Finished Jul 15 06:01:23 PM PDT 24
Peak memory 215748 kb
Host smart-aeb72f9e-5249-4e3e-9a38-000495bd8f5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534589924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3534589924
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2222409332
Short name T231
Test name
Test status
Simulation time 566694679 ps
CPU time 0.74 seconds
Started Jul 15 06:01:07 PM PDT 24
Finished Jul 15 06:01:08 PM PDT 24
Peak memory 191792 kb
Host smart-fd914e7a-e046-4222-9ee1-7d5fe9dfeddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222409332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2222409332
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2894043572
Short name T273
Test name
Test status
Simulation time 59764701564 ps
CPU time 23.64 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:01:49 PM PDT 24
Peak memory 191916 kb
Host smart-4819294e-30f9-444d-a1f5-8ec3dd6e0d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894043572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2894043572
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3626087554
Short name T10
Test name
Test status
Simulation time 438149163 ps
CPU time 0.82 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:01:28 PM PDT 24
Peak memory 191864 kb
Host smart-8be49b89-78fc-4b26-8af0-dca0e4a3380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626087554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3626087554
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1422447627
Short name T255
Test name
Test status
Simulation time 30110930612 ps
CPU time 39.08 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:02:05 PM PDT 24
Peak memory 191920 kb
Host smart-38f18a61-d12b-4d7e-bad8-002d4d959e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422447627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1422447627
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.4251873174
Short name T280
Test name
Test status
Simulation time 603691185 ps
CPU time 0.68 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:01:29 PM PDT 24
Peak memory 196704 kb
Host smart-ed9b38b9-7106-4718-ac1e-9811d98209e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251873174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4251873174
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2143306119
Short name T238
Test name
Test status
Simulation time 12904393204 ps
CPU time 18.36 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:01:44 PM PDT 24
Peak memory 196864 kb
Host smart-7eb75363-a1e0-43d4-986d-13be468206af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143306119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2143306119
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2160568095
Short name T246
Test name
Test status
Simulation time 364218378 ps
CPU time 0.75 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:01:28 PM PDT 24
Peak memory 196676 kb
Host smart-3203c954-e88b-4871-8a41-216f455c8cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160568095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2160568095
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1720288431
Short name T212
Test name
Test status
Simulation time 48709548464 ps
CPU time 74.02 seconds
Started Jul 15 06:01:22 PM PDT 24
Finished Jul 15 06:02:37 PM PDT 24
Peak memory 191928 kb
Host smart-c7b7edf1-ea8d-4f71-b7e3-d969bd49082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720288431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1720288431
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1702056561
Short name T251
Test name
Test status
Simulation time 577509159 ps
CPU time 1.47 seconds
Started Jul 15 06:01:22 PM PDT 24
Finished Jul 15 06:01:23 PM PDT 24
Peak memory 191808 kb
Host smart-f92e8d2e-e050-4de2-94fa-a77be19322a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702056561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1702056561
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.138971386
Short name T45
Test name
Test status
Simulation time 21978488723 ps
CPU time 114.67 seconds
Started Jul 15 06:01:25 PM PDT 24
Finished Jul 15 06:03:21 PM PDT 24
Peak memory 198584 kb
Host smart-06c8990f-d864-408c-ae1a-1a84863254e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138971386 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.138971386
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2818513720
Short name T198
Test name
Test status
Simulation time 33168454335 ps
CPU time 3.15 seconds
Started Jul 15 06:01:24 PM PDT 24
Finished Jul 15 06:01:27 PM PDT 24
Peak memory 191932 kb
Host smart-a029aea9-b230-45c6-b1ef-ea5f23c85c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818513720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2818513720
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4028425898
Short name T284
Test name
Test status
Simulation time 449917956 ps
CPU time 0.79 seconds
Started Jul 15 06:01:28 PM PDT 24
Finished Jul 15 06:01:30 PM PDT 24
Peak memory 191864 kb
Host smart-163a76f4-d15c-4284-9ebe-ae58319d12a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028425898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4028425898
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4240329257
Short name T228
Test name
Test status
Simulation time 27564968106 ps
CPU time 9.14 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:01:38 PM PDT 24
Peak memory 191956 kb
Host smart-28f21f19-cad0-44f7-af83-eb8b1565f4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240329257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4240329257
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.306284331
Short name T259
Test name
Test status
Simulation time 458907609 ps
CPU time 1.32 seconds
Started Jul 15 06:01:26 PM PDT 24
Finished Jul 15 06:01:28 PM PDT 24
Peak memory 196640 kb
Host smart-19dc11ae-d53f-485e-9c14-f13ea01843ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306284331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.306284331
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3862592628
Short name T43
Test name
Test status
Simulation time 51893136342 ps
CPU time 79.86 seconds
Started Jul 15 06:01:29 PM PDT 24
Finished Jul 15 06:02:50 PM PDT 24
Peak memory 191900 kb
Host smart-6863cc76-f470-415c-82d0-92a76a563bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862592628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3862592628
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3048244345
Short name T23
Test name
Test status
Simulation time 408418131 ps
CPU time 0.95 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:01:30 PM PDT 24
Peak memory 196472 kb
Host smart-db59aa85-680b-4e04-b2a5-20498e2b7e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048244345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3048244345
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2670848189
Short name T266
Test name
Test status
Simulation time 36279869783 ps
CPU time 8.15 seconds
Started Jul 15 06:01:27 PM PDT 24
Finished Jul 15 06:01:37 PM PDT 24
Peak memory 191920 kb
Host smart-d8613ac3-46b6-4fb4-8b9a-f862e3c2a26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670848189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2670848189
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.758778721
Short name T276
Test name
Test status
Simulation time 615454217 ps
CPU time 0.98 seconds
Started Jul 15 06:01:29 PM PDT 24
Finished Jul 15 06:01:31 PM PDT 24
Peak memory 191780 kb
Host smart-f44cdd97-52e6-4646-9a6b-e4543b1132f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758778721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.758778721
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1837952886
Short name T282
Test name
Test status
Simulation time 8756349367 ps
CPU time 14.03 seconds
Started Jul 15 06:01:39 PM PDT 24
Finished Jul 15 06:01:54 PM PDT 24
Peak memory 191916 kb
Host smart-790f06f6-ae04-4263-9c74-091e54981698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837952886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1837952886
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1363266559
Short name T211
Test name
Test status
Simulation time 540322149 ps
CPU time 0.99 seconds
Started Jul 15 06:01:45 PM PDT 24
Finished Jul 15 06:01:47 PM PDT 24
Peak memory 196664 kb
Host smart-0e22c9bc-b7a5-4359-8bc1-99d90455fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363266559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1363266559
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1234783376
Short name T209
Test name
Test status
Simulation time 10164147113 ps
CPU time 3.55 seconds
Started Jul 15 06:01:42 PM PDT 24
Finished Jul 15 06:01:46 PM PDT 24
Peak memory 191924 kb
Host smart-fc3cb4c9-c6e8-4d7f-b7e4-72edf968aed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234783376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1234783376
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1860382654
Short name T235
Test name
Test status
Simulation time 415035093 ps
CPU time 0.71 seconds
Started Jul 15 06:01:39 PM PDT 24
Finished Jul 15 06:01:40 PM PDT 24
Peak memory 196692 kb
Host smart-d9c82818-d64c-4ff3-9539-be9e77e7bf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860382654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1860382654
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3195604873
Short name T265
Test name
Test status
Simulation time 21197175211 ps
CPU time 32.68 seconds
Started Jul 15 06:01:08 PM PDT 24
Finished Jul 15 06:01:41 PM PDT 24
Peak memory 191928 kb
Host smart-0fd94185-645b-475e-8128-e9e14f6e6a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195604873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3195604873
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3904925258
Short name T16
Test name
Test status
Simulation time 3779900125 ps
CPU time 2.16 seconds
Started Jul 15 06:01:17 PM PDT 24
Finished Jul 15 06:01:20 PM PDT 24
Peak memory 215288 kb
Host smart-d2ac5a6e-e0fc-4ed8-ab57-0eb1c99cc6a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904925258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3904925258
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.818542133
Short name T5
Test name
Test status
Simulation time 378615852 ps
CPU time 1.12 seconds
Started Jul 15 06:01:08 PM PDT 24
Finished Jul 15 06:01:10 PM PDT 24
Peak memory 196632 kb
Host smart-b5c3768b-7e6f-49cd-8a4e-050791b52bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818542133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.818542133
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3259351853
Short name T47
Test name
Test status
Simulation time 543723878 ps
CPU time 0.72 seconds
Started Jul 15 06:01:46 PM PDT 24
Finished Jul 15 06:01:47 PM PDT 24
Peak memory 196640 kb
Host smart-da7ebded-3668-4718-9b96-4048eea89630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259351853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3259351853
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3229484570
Short name T91
Test name
Test status
Simulation time 47087743341 ps
CPU time 62.77 seconds
Started Jul 15 06:01:37 PM PDT 24
Finished Jul 15 06:02:40 PM PDT 24
Peak memory 191860 kb
Host smart-4748d825-ecbd-4ee6-8e2c-0739059368cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229484570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3229484570
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2451004269
Short name T220
Test name
Test status
Simulation time 477174535 ps
CPU time 0.65 seconds
Started Jul 15 06:01:38 PM PDT 24
Finished Jul 15 06:01:40 PM PDT 24
Peak memory 191760 kb
Host smart-48a338b6-113f-4880-a161-1b65c57fddb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451004269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2451004269
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3748970570
Short name T219
Test name
Test status
Simulation time 22450449784 ps
CPU time 2.17 seconds
Started Jul 15 06:01:38 PM PDT 24
Finished Jul 15 06:01:41 PM PDT 24
Peak memory 191900 kb
Host smart-daeb4a29-471c-408f-8ae1-00400b7eb470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748970570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3748970570
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2360878154
Short name T206
Test name
Test status
Simulation time 340675965 ps
CPU time 1.04 seconds
Started Jul 15 06:01:39 PM PDT 24
Finished Jul 15 06:01:41 PM PDT 24
Peak memory 196672 kb
Host smart-b2bd2cb9-a0e9-4a1e-99c3-7fb6b86dcaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360878154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2360878154
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1941006907
Short name T268
Test name
Test status
Simulation time 46823053495 ps
CPU time 30.03 seconds
Started Jul 15 06:01:45 PM PDT 24
Finished Jul 15 06:02:15 PM PDT 24
Peak memory 196924 kb
Host smart-e8227925-424e-4470-a972-ff84dac6b96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941006907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1941006907
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3897471502
Short name T222
Test name
Test status
Simulation time 395847869 ps
CPU time 0.65 seconds
Started Jul 15 06:01:37 PM PDT 24
Finished Jul 15 06:01:38 PM PDT 24
Peak memory 196672 kb
Host smart-3331a9d5-bc83-4c70-87a0-762fa8441d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897471502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3897471502
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3299071658
Short name T178
Test name
Test status
Simulation time 472195737 ps
CPU time 0.81 seconds
Started Jul 15 06:01:47 PM PDT 24
Finished Jul 15 06:01:49 PM PDT 24
Peak memory 196588 kb
Host smart-5109aaa3-d635-46e0-8ec6-e96c17d17bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299071658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3299071658
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.13057323
Short name T244
Test name
Test status
Simulation time 54455434612 ps
CPU time 79.46 seconds
Started Jul 15 06:01:40 PM PDT 24
Finished Jul 15 06:03:00 PM PDT 24
Peak memory 191872 kb
Host smart-7c2b01fa-432a-434b-9c50-8c777f60f63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13057323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.13057323
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3333920188
Short name T279
Test name
Test status
Simulation time 602901515 ps
CPU time 1.04 seconds
Started Jul 15 06:01:37 PM PDT 24
Finished Jul 15 06:01:38 PM PDT 24
Peak memory 196652 kb
Host smart-a683882e-3d47-4fc7-b160-4182b7e00fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333920188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3333920188
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2026173414
Short name T226
Test name
Test status
Simulation time 13362260771 ps
CPU time 9.99 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:01:59 PM PDT 24
Peak memory 191916 kb
Host smart-6da25270-cd0f-45e7-8fbb-cdaab84c7521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026173414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2026173414
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2714929783
Short name T261
Test name
Test status
Simulation time 518622424 ps
CPU time 1.25 seconds
Started Jul 15 06:01:50 PM PDT 24
Finished Jul 15 06:01:53 PM PDT 24
Peak memory 191868 kb
Host smart-05451be0-fbeb-49df-9c6d-93bdca52bc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714929783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2714929783
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1787798612
Short name T196
Test name
Test status
Simulation time 5763149321 ps
CPU time 8.89 seconds
Started Jul 15 06:01:39 PM PDT 24
Finished Jul 15 06:01:48 PM PDT 24
Peak memory 196916 kb
Host smart-ef2e8308-3001-4c90-8ec4-a2783edc2ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787798612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1787798612
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2295383154
Short name T269
Test name
Test status
Simulation time 514698144 ps
CPU time 0.84 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:01:51 PM PDT 24
Peak memory 191848 kb
Host smart-bca7b974-dfdd-4746-ae6b-6818427b3710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295383154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2295383154
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1979750688
Short name T8
Test name
Test status
Simulation time 5965637074 ps
CPU time 8.21 seconds
Started Jul 15 06:01:49 PM PDT 24
Finished Jul 15 06:01:59 PM PDT 24
Peak memory 191912 kb
Host smart-cd21cfee-5363-430c-8679-e78b5e979f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979750688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1979750688
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1064192759
Short name T277
Test name
Test status
Simulation time 519896264 ps
CPU time 0.9 seconds
Started Jul 15 06:01:42 PM PDT 24
Finished Jul 15 06:01:43 PM PDT 24
Peak memory 196692 kb
Host smart-28872e54-7f3f-4a26-86c9-86e579f0c27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064192759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1064192759
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3523494114
Short name T229
Test name
Test status
Simulation time 3504283587 ps
CPU time 5.03 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:01:55 PM PDT 24
Peak memory 191916 kb
Host smart-911d26fc-84b8-44a2-825a-648c48ef49e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523494114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3523494114
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.325837592
Short name T262
Test name
Test status
Simulation time 341116632 ps
CPU time 0.7 seconds
Started Jul 15 06:01:50 PM PDT 24
Finished Jul 15 06:01:53 PM PDT 24
Peak memory 191836 kb
Host smart-58f79fa5-65cf-4ee9-95b0-bb68390be31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325837592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.325837592
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.4152940322
Short name T281
Test name
Test status
Simulation time 3710456476 ps
CPU time 3.43 seconds
Started Jul 15 06:01:51 PM PDT 24
Finished Jul 15 06:01:56 PM PDT 24
Peak memory 196704 kb
Host smart-e8d17eb6-e1c3-4cee-86ac-91154dcb6b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152940322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.4152940322
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.817968985
Short name T239
Test name
Test status
Simulation time 563547505 ps
CPU time 0.74 seconds
Started Jul 15 06:01:51 PM PDT 24
Finished Jul 15 06:01:53 PM PDT 24
Peak memory 191844 kb
Host smart-2d57d796-59d0-4b84-8a41-8b06c6b7e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817968985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.817968985
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.7808581
Short name T204
Test name
Test status
Simulation time 11426204153 ps
CPU time 9.29 seconds
Started Jul 15 06:01:52 PM PDT 24
Finished Jul 15 06:02:03 PM PDT 24
Peak memory 191912 kb
Host smart-283320c3-263b-451c-87a5-b35ac94763ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7808581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.7808581
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1197363893
Short name T225
Test name
Test status
Simulation time 404365868 ps
CPU time 1.16 seconds
Started Jul 15 06:01:54 PM PDT 24
Finished Jul 15 06:01:56 PM PDT 24
Peak memory 191860 kb
Host smart-dca90b55-ac77-4e88-8898-b3a33f8f4463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197363893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1197363893
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1899880759
Short name T272
Test name
Test status
Simulation time 6710632158 ps
CPU time 1.96 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:19 PM PDT 24
Peak memory 191896 kb
Host smart-d50f53e8-705e-4974-b13f-2db288899c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899880759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1899880759
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.832881939
Short name T17
Test name
Test status
Simulation time 4148263366 ps
CPU time 6.84 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:22 PM PDT 24
Peak memory 215384 kb
Host smart-8a9fcfe1-f353-417c-967e-0f21cade7741
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832881939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.832881939
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.821677019
Short name T270
Test name
Test status
Simulation time 444921339 ps
CPU time 1.11 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:01:18 PM PDT 24
Peak memory 191808 kb
Host smart-e93e1e93-ea92-41a5-af8a-2b4c3860bbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821677019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.821677019
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.890220077
Short name T48
Test name
Test status
Simulation time 1575074443 ps
CPU time 0.85 seconds
Started Jul 15 06:01:56 PM PDT 24
Finished Jul 15 06:01:57 PM PDT 24
Peak memory 191864 kb
Host smart-7560bf61-64f8-424e-9060-26319cc1adba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890220077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.890220077
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.868002487
Short name T283
Test name
Test status
Simulation time 375147364 ps
CPU time 1.12 seconds
Started Jul 15 06:01:59 PM PDT 24
Finished Jul 15 06:02:01 PM PDT 24
Peak memory 191892 kb
Host smart-2ebdfc29-5585-47ea-b72c-70cccb74d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868002487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.868002487
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.536366293
Short name T197
Test name
Test status
Simulation time 29113490535 ps
CPU time 39.86 seconds
Started Jul 15 06:02:00 PM PDT 24
Finished Jul 15 06:02:40 PM PDT 24
Peak memory 196952 kb
Host smart-4476e2c8-cf9a-4c3f-8f51-04eb2d861a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536366293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.536366293
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3670525801
Short name T236
Test name
Test status
Simulation time 385043148 ps
CPU time 1.26 seconds
Started Jul 15 06:01:57 PM PDT 24
Finished Jul 15 06:01:59 PM PDT 24
Peak memory 191836 kb
Host smart-952ce967-5320-4ebd-9bb2-afe6d2a593ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670525801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3670525801
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.287097211
Short name T252
Test name
Test status
Simulation time 14240625169 ps
CPU time 4.6 seconds
Started Jul 15 06:02:01 PM PDT 24
Finished Jul 15 06:02:06 PM PDT 24
Peak memory 196908 kb
Host smart-d4750d9e-713e-4296-9b3b-da9dbeeeb6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287097211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.287097211
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3575813848
Short name T243
Test name
Test status
Simulation time 341738197 ps
CPU time 1.12 seconds
Started Jul 15 06:02:03 PM PDT 24
Finished Jul 15 06:02:04 PM PDT 24
Peak memory 191844 kb
Host smart-bbccf9bd-442f-4030-9304-2d1985f637ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575813848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3575813848
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2499487392
Short name T223
Test name
Test status
Simulation time 13036410151 ps
CPU time 8.3 seconds
Started Jul 15 06:01:46 PM PDT 24
Finished Jul 15 06:01:55 PM PDT 24
Peak memory 191880 kb
Host smart-f7526cd9-1b4a-46e9-9d76-c0352cb356c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499487392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2499487392
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4284706236
Short name T221
Test name
Test status
Simulation time 510395464 ps
CPU time 0.72 seconds
Started Jul 15 06:02:00 PM PDT 24
Finished Jul 15 06:02:01 PM PDT 24
Peak memory 191768 kb
Host smart-bd063f08-48a2-4bc9-99bb-5d9edfb53775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284706236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4284706236
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2310320533
Short name T205
Test name
Test status
Simulation time 54580204338 ps
CPU time 17.47 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:02:07 PM PDT 24
Peak memory 191908 kb
Host smart-67b2ff10-10ac-4783-9ad0-bb0b555596ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310320533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2310320533
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3540843218
Short name T241
Test name
Test status
Simulation time 619894922 ps
CPU time 0.67 seconds
Started Jul 15 06:01:39 PM PDT 24
Finished Jul 15 06:01:41 PM PDT 24
Peak memory 191860 kb
Host smart-d770d149-4c6f-4a7b-8f9d-30191cf39323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540843218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3540843218
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3084791917
Short name T224
Test name
Test status
Simulation time 26438021356 ps
CPU time 36.7 seconds
Started Jul 15 06:01:48 PM PDT 24
Finished Jul 15 06:02:26 PM PDT 24
Peak memory 191868 kb
Host smart-d329898f-d889-4a87-b13f-3102feb358b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084791917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3084791917
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1689384589
Short name T216
Test name
Test status
Simulation time 521484414 ps
CPU time 1.29 seconds
Started Jul 15 06:01:51 PM PDT 24
Finished Jul 15 06:01:54 PM PDT 24
Peak memory 191840 kb
Host smart-0f919f11-5f1b-4416-b907-28db4eb4066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689384589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1689384589
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1181348569
Short name T253
Test name
Test status
Simulation time 125353301600 ps
CPU time 85.57 seconds
Started Jul 15 06:01:49 PM PDT 24
Finished Jul 15 06:03:16 PM PDT 24
Peak memory 184380 kb
Host smart-689480c9-0475-4489-a304-64ad06740028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181348569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1181348569
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1746529625
Short name T49
Test name
Test status
Simulation time 13810927678 ps
CPU time 19.61 seconds
Started Jul 15 06:01:50 PM PDT 24
Finished Jul 15 06:02:12 PM PDT 24
Peak memory 196904 kb
Host smart-a500b66c-2836-4e38-8f0f-a163f7bd66cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746529625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1746529625
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2644206000
Short name T233
Test name
Test status
Simulation time 375352809 ps
CPU time 0.71 seconds
Started Jul 15 06:01:47 PM PDT 24
Finished Jul 15 06:01:49 PM PDT 24
Peak memory 196692 kb
Host smart-9788aa3d-74fc-40db-bbe1-35a771204415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644206000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2644206000
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2206279898
Short name T249
Test name
Test status
Simulation time 27554412295 ps
CPU time 3.8 seconds
Started Jul 15 06:01:50 PM PDT 24
Finished Jul 15 06:01:56 PM PDT 24
Peak memory 196936 kb
Host smart-edf5aa47-0259-4448-ab8f-bce694ae10a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206279898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2206279898
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2281999385
Short name T230
Test name
Test status
Simulation time 515684356 ps
CPU time 1.2 seconds
Started Jul 15 06:01:50 PM PDT 24
Finished Jul 15 06:01:54 PM PDT 24
Peak memory 191868 kb
Host smart-fc32a69a-75fe-41c8-a785-5310f64c89e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281999385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2281999385
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.304963631
Short name T214
Test name
Test status
Simulation time 27390632554 ps
CPU time 18.7 seconds
Started Jul 15 06:01:50 PM PDT 24
Finished Jul 15 06:02:11 PM PDT 24
Peak memory 191896 kb
Host smart-84be3c17-f138-4555-bd55-b3450ab5c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304963631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.304963631
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.916274566
Short name T275
Test name
Test status
Simulation time 399494211 ps
CPU time 0.68 seconds
Started Jul 15 06:01:46 PM PDT 24
Finished Jul 15 06:01:47 PM PDT 24
Peak memory 196660 kb
Host smart-bf3c7711-1438-4b29-b486-a115fd39d214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916274566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.916274566
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.635176914
Short name T285
Test name
Test status
Simulation time 49672973627 ps
CPU time 72.12 seconds
Started Jul 15 06:01:50 PM PDT 24
Finished Jul 15 06:03:04 PM PDT 24
Peak memory 191940 kb
Host smart-7bf0ba0f-e6c8-4f2c-a7be-19965ff84049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635176914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.635176914
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1265458835
Short name T54
Test name
Test status
Simulation time 363589024 ps
CPU time 1.14 seconds
Started Jul 15 06:01:49 PM PDT 24
Finished Jul 15 06:01:52 PM PDT 24
Peak memory 196672 kb
Host smart-37c0aa42-2175-45fd-adc7-2235f2a52ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265458835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1265458835
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.189576818
Short name T51
Test name
Test status
Simulation time 18490636617 ps
CPU time 30.58 seconds
Started Jul 15 06:01:21 PM PDT 24
Finished Jul 15 06:01:52 PM PDT 24
Peak memory 191820 kb
Host smart-2fd45dbb-a104-4b85-bd95-cdb8acfcc2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189576818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.189576818
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.130977497
Short name T215
Test name
Test status
Simulation time 404936997 ps
CPU time 0.9 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:01:18 PM PDT 24
Peak memory 191848 kb
Host smart-be88803a-3f2e-43f2-8bd6-85f5a220948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130977497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.130977497
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3115938068
Short name T271
Test name
Test status
Simulation time 48302919941 ps
CPU time 70.17 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:02:27 PM PDT 24
Peak memory 191924 kb
Host smart-f53bc1a5-eb6e-440c-9fd4-a1c7356b1128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115938068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3115938068
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1983210353
Short name T208
Test name
Test status
Simulation time 501460082 ps
CPU time 0.7 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:17 PM PDT 24
Peak memory 196668 kb
Host smart-12af4bd6-15d1-4309-89cf-4661fcbaabb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983210353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1983210353
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2676200522
Short name T28
Test name
Test status
Simulation time 105985663502 ps
CPU time 143.39 seconds
Started Jul 15 06:01:21 PM PDT 24
Finished Jul 15 06:03:45 PM PDT 24
Peak memory 183628 kb
Host smart-75f35c5a-859f-4cec-a5b1-5e6b8fdd5443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676200522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2676200522
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2545079069
Short name T250
Test name
Test status
Simulation time 35175744207 ps
CPU time 46.84 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:02:04 PM PDT 24
Peak memory 191924 kb
Host smart-73bd1429-550f-4176-9b9c-48a379356737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545079069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2545079069
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.779807099
Short name T227
Test name
Test status
Simulation time 502535031 ps
CPU time 0.64 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:16 PM PDT 24
Peak memory 196700 kb
Host smart-3e40ab7e-cf56-40b3-baa0-c22430f2bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779807099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.779807099
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2022285157
Short name T187
Test name
Test status
Simulation time 373037486 ps
CPU time 0.74 seconds
Started Jul 15 06:01:13 PM PDT 24
Finished Jul 15 06:01:15 PM PDT 24
Peak memory 196644 kb
Host smart-4ce3f2e7-6c7e-4018-a345-b1bb2aa26a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022285157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2022285157
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3722111097
Short name T42
Test name
Test status
Simulation time 3784287564 ps
CPU time 5.74 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:21 PM PDT 24
Peak memory 191896 kb
Host smart-584a51a9-b2d2-415c-a5b5-e2c417eaae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722111097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3722111097
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.855442785
Short name T245
Test name
Test status
Simulation time 512886392 ps
CPU time 0.76 seconds
Started Jul 15 06:01:15 PM PDT 24
Finished Jul 15 06:01:17 PM PDT 24
Peak memory 191808 kb
Host smart-bdea72ed-733a-40fa-a04f-20d85d73d138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855442785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.855442785
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2739795283
Short name T260
Test name
Test status
Simulation time 2584521581 ps
CPU time 1.54 seconds
Started Jul 15 06:01:14 PM PDT 24
Finished Jul 15 06:01:16 PM PDT 24
Peak memory 196712 kb
Host smart-230a0df6-e236-41d4-a17a-00f9fd35c776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739795283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2739795283
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2430190302
Short name T254
Test name
Test status
Simulation time 410288699 ps
CPU time 0.88 seconds
Started Jul 15 06:01:16 PM PDT 24
Finished Jul 15 06:01:18 PM PDT 24
Peak memory 196588 kb
Host smart-16811590-8819-46c6-a4bd-19e885d01802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430190302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2430190302
Directory /workspace/9.aon_timer_smoke/latest
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