Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	29670	1		T1	10		T3	489		T4	535
bark[1]	396	1		T6	21		T49	14		T45	26
bark[2]	407	1		T3	19		T159	21		T31	30
bark[3]	696	1		T32	70		T17	375		T105	42
bark[4]	281	1		T86	21		T80	138		T103	21
bark[5]	509	1		T7	21		T33	21		T46	21
bark[6]	405	1		T44	21		T45	21		T86	90
bark[7]	314	1		T45	7		T159	90		T157	14
bark[8]	541	1		T44	149		T85	36		T115	52
bark[9]	191	1		T5	21		T48	21		T28	30
bark[10]	722	1		T4	21		T33	21		T17	47
bark[11]	785	1		T3	203		T4	295		T106	21
bark[12]	310	1		T118	40		T48	21		T126	14
bark[13]	568	1		T167	190		T147	154		T143	69
bark[14]	558	1		T2	14		T7	21		T32	21
bark[15]	564	1		T118	26		T115	21		T127	142
bark[16]	319	1		T94	14		T96	39		T51	14
bark[17]	141	1		T34	14		T124	64		T87	21
bark[18]	489	1		T95	14		T79	7		T148	21
bark[19]	281	1		T12	14		T45	47		T124	21
bark[20]	526	1		T17	52		T85	21		T127	56
bark[21]	264	1		T10	14		T124	21		T79	21
bark[22]	452	1		T14	14		T43	21		T99	14
bark[23]	698	1		T4	87		T13	14		T124	21
bark[24]	510	1		T7	21		T85	121		T148	21
bark[25]	426	1		T123	106		T103	21		T174	14
bark[26]	954	1		T3	43		T6	31		T45	21
bark[27]	546	1		T46	102		T118	21		T48	116
bark[28]	1504	1		T3	39		T17	233		T85	31
bark[29]	913	1		T5	77		T13	111		T47	21
bark[30]	259	1		T32	47		T43	84		T124	21
bark[31]	362	1		T167	7		T148	21		T100	21
bark_0	4777	1		T1	7		T2	7		T3	84

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29101	1		T1	9		T3	482		T4	527
bite[1]	415	1		T3	18		T43	83		T45	52
bite[2]	710	1		T32	47		T148	21		T58	25
bite[3]	557	1		T17	202		T44	100		T48	21
bite[4]	700	1		T85	36		T120	21		T106	26
bite[5]	405	1		T2	13		T4	73		T12	13
bite[6]	379	1		T95	13		T120	13		T148	38
bite[7]	525	1		T23	13		T28	30		T166	39
bite[8]	1111	1		T17	374		T118	21		T115	21
bite[9]	554	1		T17	30		T79	63		T126	13
bite[10]	554	1		T5	47		T33	21		T45	21
bite[11]	244	1		T10	13		T102	26		T82	163
bite[12]	940	1		T3	42		T4	294		T7	21
bite[13]	413	1		T5	21		T17	21		T46	132
bite[14]	984	1		T32	21		T44	48		T157	13
bite[15]	237	1		T115	21		T148	21		T123	38
bite[16]	762	1		T118	18		T124	21		T120	26
bite[17]	216	1		T33	21		T45	26		T124	21
bite[18]	165	1		T4	21		T13	13		T49	13
bite[19]	284	1		T46	21		T118	26		T79	6
bite[20]	705	1		T5	30		T6	31		T34	13
bite[21]	688	1		T44	21		T159	26		T85	120
bite[22]	795	1		T33	64		T17	51		T46	101
bite[23]	184	1		T159	26		T28	38		T81	35
bite[24]	535	1		T32	70		T127	21		T50	42
bite[25]	687	1		T7	21		T45	21		T105	21
bite[26]	267	1		T79	6		T30	21		T119	49
bite[27]	550	1		T3	202		T17	26		T118	21
bite[28]	326	1		T7	21		T124	64		T59	21
bite[29]	395	1		T43	21		T48	21		T105	21
bite[30]	254	1		T3	39		T4	21		T6	21
bite[31]	509	1		T13	111		T14	13		T44	90
bite_0	5187	1		T1	8		T2	8		T3	94

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	42283	1		T1	17		T2	21		T3	426
auto[1]	8055	1		T3	451		T4	282		T5	24

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1145	1		T3	160		T17	26		T177	89
prescale[1]	661	1		T6	9		T16	37		T17	19
prescale[2]	993	1		T5	19		T11	9		T32	19
prescale[3]	949	1		T4	2		T33	19		T17	26
prescale[4]	1163	1		T4	173		T7	19		T16	19
prescale[5]	897	1		T13	80		T16	40		T45	19
prescale[6]	924	1		T32	40		T45	24		T85	73
prescale[7]	525	1		T33	44		T17	53		T42	2
prescale[8]	721	1		T3	2		T44	2		T46	19
prescale[9]	1254	1		T17	167		T44	30		T96	19
prescale[10]	630	1		T3	30		T7	23		T45	113
prescale[11]	627	1		T6	23		T17	2		T48	125
prescale[12]	676	1		T3	19		T4	38		T17	83
prescale[13]	652	1		T4	97		T96	19		T115	9
prescale[14]	254	1		T3	19		T17	2		T96	28
prescale[15]	380	1		T33	9		T42	2		T43	2
prescale[16]	465	1		T4	57		T85	19		T79	2
prescale[17]	576	1		T3	54		T4	2		T15	9
prescale[18]	857	1		T6	19		T17	36		T85	21
prescale[19]	1045	1		T4	78		T6	19		T13	23
prescale[20]	669	1		T3	55		T4	43		T5	9
prescale[21]	717	1		T16	45		T45	21		T105	60
prescale[22]	327	1		T3	2		T4	2		T45	19
prescale[23]	681	1		T3	19		T16	38		T17	2
prescale[24]	554	1		T4	2		T159	28		T47	21
prescale[25]	828	1		T44	2		T177	19		T50	19
prescale[26]	952	1		T3	2		T6	19		T13	19
prescale[27]	787	1		T4	52		T42	2		T44	92
prescale[28]	792	1		T4	19		T5	42		T33	28
prescale[29]	1004	1		T16	19		T17	149		T45	28
prescale[30]	1068	1		T3	24		T4	12		T17	52
prescale[31]	1185	1		T3	74		T4	2		T38	9
prescale_0	25380	1		T1	17		T2	21		T3	417

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37330	1		T1	17		T2	21		T3	654
auto[1]	13008	1		T3	223		T4	210		T5	92

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	50338	1		T1	17		T2	21		T3	877

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	28859	1		T1	12		T2	1		T3	540
wkup[1]	254	1		T97	15		T177	15		T50	21
wkup[2]	248	1		T16	21		T17	21		T85	21
wkup[3]	251	1		T17	21		T182	15		T58	30
wkup[4]	281	1		T17	29		T48	21		T85	42
wkup[5]	303	1		T6	21		T43	8		T45	21
wkup[6]	289	1		T115	21		T58	8		T86	21
wkup[7]	348	1		T3	21		T4	21		T5	30
wkup[8]	320	1		T2	15		T17	26		T105	21
wkup[9]	340	1		T3	39		T94	15		T47	21
wkup[10]	287	1		T33	21		T17	21		T42	21
wkup[11]	313	1		T4	21		T33	21		T17	51
wkup[12]	288	1		T4	21		T5	21		T85	24
wkup[13]	295	1		T33	21		T45	21		T159	26
wkup[14]	386	1		T159	21		T85	21		T52	21
wkup[15]	271	1		T95	15		T157	15		T50	8
wkup[16]	148	1		T4	42		T51	15		T58	15
wkup[17]	295	1		T4	21		T43	26		T126	15
wkup[18]	250	1		T3	21		T4	42		T45	21
wkup[19]	365	1		T43	21		T127	63		T120	21
wkup[20]	259	1		T16	21		T44	35		T127	21
wkup[21]	367	1		T32	21		T85	21		T115	31
wkup[22]	208	1		T4	21		T17	21		T45	8
wkup[23]	257	1		T3	21		T159	21		T124	26
wkup[24]	270	1		T3	20		T45	21		T48	21
wkup[25]	196	1		T4	21		T17	26		T48	21
wkup[26]	350	1		T33	21		T45	21		T85	21
wkup[27]	442	1		T4	21		T6	21		T10	15
wkup[28]	178	1		T3	8		T17	21		T44	21
wkup[29]	253	1		T3	21		T4	21		T47	21
wkup[30]	361	1		T17	21		T44	30		T46	30
wkup[31]	347	1		T3	21		T13	15		T48	21
wkup[32]	353	1		T4	21		T17	21		T48	35
wkup[33]	260	1		T4	31		T7	21		T105	21
wkup[34]	334	1		T106	56		T162	15		T80	21
wkup[35]	329	1		T4	21		T13	26		T32	21
wkup[36]	316	1		T50	56		T86	47		T30	21
wkup[37]	217	1		T17	15		T118	21		T120	21
wkup[38]	243	1		T17	21		T48	26		T124	21
wkup[39]	384	1		T7	21		T17	36		T44	15
wkup[40]	381	1		T3	59		T7	21		T16	26
wkup[41]	258	1		T59	21		T25	15		T30	21
wkup[42]	385	1		T4	21		T12	15		T17	21
wkup[43]	127	1		T4	21		T44	35		T127	15
wkup[44]	412	1		T17	21		T45	30		T159	26
wkup[45]	300	1		T6	31		T96	39		T46	21
wkup[46]	341	1		T3	21		T17	65		T106	21
wkup[47]	267	1		T34	15		T148	21		T28	21
wkup[48]	278	1		T13	21		T17	21		T45	21
wkup[49]	301	1		T4	21		T13	21		T45	21
wkup[50]	306	1		T4	26		T48	21		T85	21
wkup[51]	246	1		T79	21		T167	21		T58	21
wkup[52]	280	1		T3	21		T32	21		T49	15
wkup[53]	274	1		T79	21		T167	21		T115	21
wkup[54]	105	1		T45	21		T118	21		T114	21
wkup[55]	185	1		T30	15		T80	21		T142	26
wkup[56]	449	1		T6	21		T44	48		T118	21
wkup[57]	183	1		T43	21		T79	21		T59	42
wkup[58]	183	1		T13	21		T45	21		T105	15
wkup[59]	218	1		T17	21		T58	42		T155	21
wkup[60]	176	1		T32	26		T17	21		T120	21
wkup[61]	169	1		T7	21		T14	15		T46	30
wkup[62]	295	1		T47	21		T85	21		T127	35
wkup[63]	183	1		T45	21		T46	21		T147	21
wkup_0	3721	1		T1	5		T2	5		T3	64