Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.07 99.33 93.67 100.00 98.40 99.51 49.52


Total test records in report: 420
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T71 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1511606820 Jul 16 06:40:48 PM PDT 24 Jul 16 06:40:50 PM PDT 24 532241349 ps
T277 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.672504728 Jul 16 06:41:13 PM PDT 24 Jul 16 06:41:17 PM PDT 24 551753287 ps
T72 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2201866590 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:50 PM PDT 24 2099956890 ps
T189 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4087543582 Jul 16 06:41:04 PM PDT 24 Jul 16 06:41:06 PM PDT 24 502840335 ps
T60 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.200344017 Jul 16 06:40:46 PM PDT 24 Jul 16 06:40:48 PM PDT 24 448711448 ps
T39 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.687510601 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:20 PM PDT 24 8761085755 ps
T278 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.844420027 Jul 16 06:41:03 PM PDT 24 Jul 16 06:41:06 PM PDT 24 486065812 ps
T73 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.612066196 Jul 16 06:41:16 PM PDT 24 Jul 16 06:41:18 PM PDT 24 381115784 ps
T40 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1855894373 Jul 16 06:41:28 PM PDT 24 Jul 16 06:41:33 PM PDT 24 7681452868 ps
T279 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3591708920 Jul 16 06:41:01 PM PDT 24 Jul 16 06:41:11 PM PDT 24 4767257223 ps
T280 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1571628937 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:49 PM PDT 24 476229012 ps
T281 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3311173975 Jul 16 06:41:12 PM PDT 24 Jul 16 06:41:14 PM PDT 24 484556022 ps
T74 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1337149083 Jul 16 06:41:26 PM PDT 24 Jul 16 06:41:30 PM PDT 24 1458351157 ps
T282 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3151382486 Jul 16 06:40:57 PM PDT 24 Jul 16 06:40:58 PM PDT 24 466959198 ps
T283 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4000781114 Jul 16 06:41:13 PM PDT 24 Jul 16 06:41:14 PM PDT 24 452336973 ps
T75 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2512211990 Jul 16 06:40:33 PM PDT 24 Jul 16 06:40:35 PM PDT 24 3105777920 ps
T76 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1429742298 Jul 16 06:41:13 PM PDT 24 Jul 16 06:41:17 PM PDT 24 2454762255 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1085356121 Jul 16 06:40:36 PM PDT 24 Jul 16 06:40:39 PM PDT 24 425003573 ps
T190 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.917858994 Jul 16 06:40:36 PM PDT 24 Jul 16 06:40:50 PM PDT 24 8315316951 ps
T284 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4214523650 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:06 PM PDT 24 688399306 ps
T285 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2048286122 Jul 16 06:41:30 PM PDT 24 Jul 16 06:41:33 PM PDT 24 313980885 ps
T286 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.786472288 Jul 16 06:40:48 PM PDT 24 Jul 16 06:40:50 PM PDT 24 1048955007 ps
T287 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1770509158 Jul 16 06:41:12 PM PDT 24 Jul 16 06:41:15 PM PDT 24 4760535179 ps
T288 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3405724133 Jul 16 06:40:38 PM PDT 24 Jul 16 06:40:39 PM PDT 24 298680806 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3802975829 Jul 16 06:40:35 PM PDT 24 Jul 16 06:40:37 PM PDT 24 520532582 ps
T290 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3995741231 Jul 16 06:41:32 PM PDT 24 Jul 16 06:41:34 PM PDT 24 511966737 ps
T291 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.558984124 Jul 16 06:40:46 PM PDT 24 Jul 16 06:40:48 PM PDT 24 411966115 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2504515244 Jul 16 06:40:36 PM PDT 24 Jul 16 06:40:39 PM PDT 24 433245175 ps
T77 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.668195507 Jul 16 06:41:00 PM PDT 24 Jul 16 06:41:01 PM PDT 24 1355317064 ps
T293 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3264208376 Jul 16 06:41:16 PM PDT 24 Jul 16 06:41:19 PM PDT 24 334502247 ps
T294 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2038045273 Jul 16 06:41:13 PM PDT 24 Jul 16 06:41:17 PM PDT 24 476784181 ps
T295 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2455426173 Jul 16 06:41:30 PM PDT 24 Jul 16 06:41:33 PM PDT 24 387578273 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2913807684 Jul 16 06:40:36 PM PDT 24 Jul 16 06:40:38 PM PDT 24 507935772 ps
T297 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4020082823 Jul 16 06:40:48 PM PDT 24 Jul 16 06:40:50 PM PDT 24 335222354 ps
T298 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3214352137 Jul 16 06:41:03 PM PDT 24 Jul 16 06:41:06 PM PDT 24 589759483 ps
T299 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2170739657 Jul 16 06:41:03 PM PDT 24 Jul 16 06:41:05 PM PDT 24 300650446 ps
T300 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2836794366 Jul 16 06:41:13 PM PDT 24 Jul 16 06:41:16 PM PDT 24 465430134 ps
T301 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4282243848 Jul 16 06:40:34 PM PDT 24 Jul 16 06:40:37 PM PDT 24 515777701 ps
T302 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.296190505 Jul 16 06:41:30 PM PDT 24 Jul 16 06:41:33 PM PDT 24 493677058 ps
T78 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1067309060 Jul 16 06:41:06 PM PDT 24 Jul 16 06:41:08 PM PDT 24 519312181 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1971381533 Jul 16 06:40:36 PM PDT 24 Jul 16 06:40:41 PM PDT 24 4534217157 ps
T304 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1874713606 Jul 16 06:41:29 PM PDT 24 Jul 16 06:41:32 PM PDT 24 362094237 ps
T305 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2830726497 Jul 16 06:40:46 PM PDT 24 Jul 16 06:40:49 PM PDT 24 4425711707 ps
T306 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2706289733 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:07 PM PDT 24 2175957967 ps
T307 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2421170416 Jul 16 06:41:13 PM PDT 24 Jul 16 06:41:15 PM PDT 24 513045988 ps
T308 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3923825843 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:07 PM PDT 24 1419589437 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4214323462 Jul 16 06:40:47 PM PDT 24 Jul 16 06:41:11 PM PDT 24 10372551906 ps
T63 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.225679142 Jul 16 06:41:04 PM PDT 24 Jul 16 06:41:06 PM PDT 24 575269765 ps
T309 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.678107695 Jul 16 06:41:36 PM PDT 24 Jul 16 06:41:37 PM PDT 24 293467816 ps
T310 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1603388810 Jul 16 06:40:45 PM PDT 24 Jul 16 06:40:47 PM PDT 24 496131845 ps
T311 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4167175259 Jul 16 06:41:14 PM PDT 24 Jul 16 06:41:16 PM PDT 24 433914093 ps
T312 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2168265038 Jul 16 06:40:57 PM PDT 24 Jul 16 06:40:58 PM PDT 24 439298915 ps
T313 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.589259063 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:18 PM PDT 24 1369836940 ps
T314 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1539129525 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:06 PM PDT 24 510030946 ps
T64 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.687187574 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:17 PM PDT 24 480068842 ps
T65 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1968744450 Jul 16 06:41:27 PM PDT 24 Jul 16 06:41:29 PM PDT 24 308367238 ps
T315 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4209529885 Jul 16 06:40:38 PM PDT 24 Jul 16 06:40:39 PM PDT 24 486167387 ps
T316 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2055498384 Jul 16 06:41:32 PM PDT 24 Jul 16 06:41:35 PM PDT 24 467363293 ps
T317 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4272883236 Jul 16 06:41:07 PM PDT 24 Jul 16 06:41:09 PM PDT 24 439181761 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.22434135 Jul 16 06:40:57 PM PDT 24 Jul 16 06:41:00 PM PDT 24 7503565474 ps
T318 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2288924156 Jul 16 06:41:03 PM PDT 24 Jul 16 06:41:09 PM PDT 24 4705966793 ps
T319 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3703783251 Jul 16 06:41:28 PM PDT 24 Jul 16 06:41:30 PM PDT 24 441626529 ps
T186 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2760180337 Jul 16 06:41:03 PM PDT 24 Jul 16 06:41:08 PM PDT 24 8205163781 ps
T187 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2242887680 Jul 16 06:41:12 PM PDT 24 Jul 16 06:41:18 PM PDT 24 8442705850 ps
T320 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2202560665 Jul 16 06:41:30 PM PDT 24 Jul 16 06:41:33 PM PDT 24 289229385 ps
T321 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1389872360 Jul 16 06:40:39 PM PDT 24 Jul 16 06:40:42 PM PDT 24 984420104 ps
T322 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2063079444 Jul 16 06:40:45 PM PDT 24 Jul 16 06:40:47 PM PDT 24 478575786 ps
T323 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3818277658 Jul 16 06:41:29 PM PDT 24 Jul 16 06:41:32 PM PDT 24 389273260 ps
T324 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3060489642 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:49 PM PDT 24 339599798 ps
T325 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1621252995 Jul 16 06:41:32 PM PDT 24 Jul 16 06:41:34 PM PDT 24 356911736 ps
T326 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1653469826 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:51 PM PDT 24 376220449 ps
T327 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.221048230 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:04 PM PDT 24 485390203 ps
T328 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4084005306 Jul 16 06:41:06 PM PDT 24 Jul 16 06:41:08 PM PDT 24 485715280 ps
T329 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1209792098 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:49 PM PDT 24 481800126 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4055475062 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:51 PM PDT 24 516670116 ps
T331 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.325410973 Jul 16 06:40:36 PM PDT 24 Jul 16 06:40:38 PM PDT 24 304394677 ps
T67 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2427134734 Jul 16 06:41:14 PM PDT 24 Jul 16 06:41:15 PM PDT 24 630047192 ps
T68 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3989341071 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:04 PM PDT 24 592985647 ps
T332 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.139277635 Jul 16 06:41:27 PM PDT 24 Jul 16 06:41:29 PM PDT 24 548624697 ps
T333 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3072515452 Jul 16 06:40:39 PM PDT 24 Jul 16 06:40:48 PM PDT 24 7150068526 ps
T334 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1743525052 Jul 16 06:41:14 PM PDT 24 Jul 16 06:41:15 PM PDT 24 314665355 ps
T335 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3407771913 Jul 16 06:40:48 PM PDT 24 Jul 16 06:40:50 PM PDT 24 323529935 ps
T336 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2546216932 Jul 16 06:40:42 PM PDT 24 Jul 16 06:40:44 PM PDT 24 341597751 ps
T337 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.180680749 Jul 16 06:41:16 PM PDT 24 Jul 16 06:41:23 PM PDT 24 8895514285 ps
T338 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.359117963 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:20 PM PDT 24 7978697347 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1844482765 Jul 16 06:40:35 PM PDT 24 Jul 16 06:40:37 PM PDT 24 413267489 ps
T340 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2734422861 Jul 16 06:41:01 PM PDT 24 Jul 16 06:41:03 PM PDT 24 471156843 ps
T341 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1756483751 Jul 16 06:41:11 PM PDT 24 Jul 16 06:41:14 PM PDT 24 1223814513 ps
T342 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3551200746 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:18 PM PDT 24 491223111 ps
T343 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2733148407 Jul 16 06:41:32 PM PDT 24 Jul 16 06:41:35 PM PDT 24 412581823 ps
T344 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.288490646 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:05 PM PDT 24 2233997487 ps
T345 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2809359647 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:19 PM PDT 24 607398331 ps
T346 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1017409959 Jul 16 06:40:39 PM PDT 24 Jul 16 06:40:41 PM PDT 24 463896862 ps
T347 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1835529342 Jul 16 06:41:00 PM PDT 24 Jul 16 06:41:05 PM PDT 24 8072341965 ps
T348 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2351835368 Jul 16 06:41:01 PM PDT 24 Jul 16 06:41:03 PM PDT 24 308735431 ps
T349 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.931046332 Jul 16 06:40:41 PM PDT 24 Jul 16 06:40:43 PM PDT 24 403141558 ps
T350 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3785435298 Jul 16 06:41:03 PM PDT 24 Jul 16 06:41:11 PM PDT 24 4618789804 ps
T351 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3023140430 Jul 16 06:40:35 PM PDT 24 Jul 16 06:40:37 PM PDT 24 1187785048 ps
T352 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2165134466 Jul 16 06:41:07 PM PDT 24 Jul 16 06:41:10 PM PDT 24 1227473291 ps
T353 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4195015895 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:51 PM PDT 24 657329477 ps
T354 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1422492617 Jul 16 06:41:11 PM PDT 24 Jul 16 06:41:13 PM PDT 24 323259723 ps
T355 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3369070863 Jul 16 06:41:13 PM PDT 24 Jul 16 06:41:15 PM PDT 24 4993594641 ps
T356 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2409104180 Jul 16 06:41:14 PM PDT 24 Jul 16 06:41:15 PM PDT 24 431286111 ps
T357 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2510317879 Jul 16 06:40:46 PM PDT 24 Jul 16 06:40:48 PM PDT 24 400634550 ps
T358 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.620992679 Jul 16 06:40:49 PM PDT 24 Jul 16 06:40:52 PM PDT 24 502253873 ps
T359 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.190075886 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:17 PM PDT 24 364806080 ps
T360 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.16288241 Jul 16 06:41:30 PM PDT 24 Jul 16 06:41:33 PM PDT 24 493207824 ps
T361 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4249803255 Jul 16 06:41:06 PM PDT 24 Jul 16 06:41:08 PM PDT 24 415070836 ps
T362 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1389496739 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:04 PM PDT 24 323388055 ps
T363 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3182719384 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:06 PM PDT 24 450100956 ps
T364 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.343591773 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:49 PM PDT 24 555560131 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2158153455 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:51 PM PDT 24 2507077252 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1654192882 Jul 16 06:41:01 PM PDT 24 Jul 16 06:41:03 PM PDT 24 466744450 ps
T367 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.207473360 Jul 16 06:41:32 PM PDT 24 Jul 16 06:41:35 PM PDT 24 529102305 ps
T368 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3322802831 Jul 16 06:40:57 PM PDT 24 Jul 16 06:40:58 PM PDT 24 773625608 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3052360363 Jul 16 06:40:41 PM PDT 24 Jul 16 06:40:46 PM PDT 24 6584472024 ps
T369 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2108501017 Jul 16 06:40:48 PM PDT 24 Jul 16 06:40:53 PM PDT 24 4270082408 ps
T370 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3137383662 Jul 16 06:41:32 PM PDT 24 Jul 16 06:41:35 PM PDT 24 312922546 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1330337089 Jul 16 06:40:34 PM PDT 24 Jul 16 06:40:36 PM PDT 24 511191499 ps
T372 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3159805057 Jul 16 06:41:30 PM PDT 24 Jul 16 06:41:33 PM PDT 24 282878328 ps
T373 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3055183789 Jul 16 06:41:30 PM PDT 24 Jul 16 06:41:33 PM PDT 24 294204105 ps
T374 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2131276287 Jul 16 06:41:14 PM PDT 24 Jul 16 06:41:17 PM PDT 24 345043092 ps
T375 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2841057567 Jul 16 06:40:47 PM PDT 24 Jul 16 06:40:51 PM PDT 24 525383106 ps
T376 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1664738355 Jul 16 06:40:55 PM PDT 24 Jul 16 06:40:56 PM PDT 24 370853380 ps
T377 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3957521651 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:06 PM PDT 24 4413475803 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2631316307 Jul 16 06:40:39 PM PDT 24 Jul 16 06:40:41 PM PDT 24 392084534 ps
T378 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3903280728 Jul 16 06:41:30 PM PDT 24 Jul 16 06:41:33 PM PDT 24 513084924 ps
T379 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.230370449 Jul 16 06:41:32 PM PDT 24 Jul 16 06:41:35 PM PDT 24 441231997 ps
T380 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2173462126 Jul 16 06:41:04 PM PDT 24 Jul 16 06:41:07 PM PDT 24 1599688151 ps
T381 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1024899983 Jul 16 06:41:31 PM PDT 24 Jul 16 06:41:34 PM PDT 24 437196123 ps
T382 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3948723670 Jul 16 06:41:29 PM PDT 24 Jul 16 06:41:32 PM PDT 24 453501604 ps
T383 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3805885853 Jul 16 06:41:00 PM PDT 24 Jul 16 06:41:02 PM PDT 24 486370222 ps
T384 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.729897493 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:19 PM PDT 24 597498640 ps
T385 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.148063789 Jul 16 06:41:06 PM PDT 24 Jul 16 06:41:08 PM PDT 24 517711712 ps
T386 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1728918055 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:17 PM PDT 24 425853872 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2198361379 Jul 16 06:40:49 PM PDT 24 Jul 16 06:40:51 PM PDT 24 1356070076 ps
T388 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3239871740 Jul 16 06:41:03 PM PDT 24 Jul 16 06:41:06 PM PDT 24 520723194 ps
T389 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2772811619 Jul 16 06:41:27 PM PDT 24 Jul 16 06:41:28 PM PDT 24 318181076 ps
T390 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2595266617 Jul 16 06:40:49 PM PDT 24 Jul 16 06:40:51 PM PDT 24 433147080 ps
T391 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1428676963 Jul 16 06:40:59 PM PDT 24 Jul 16 06:41:01 PM PDT 24 377182199 ps
T392 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2755676963 Jul 16 06:41:33 PM PDT 24 Jul 16 06:41:35 PM PDT 24 396228673 ps
T393 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.771332249 Jul 16 06:41:29 PM PDT 24 Jul 16 06:41:32 PM PDT 24 317242248 ps
T394 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.795564314 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:18 PM PDT 24 489132960 ps
T395 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2713891738 Jul 16 06:41:28 PM PDT 24 Jul 16 06:41:30 PM PDT 24 583619011 ps
T396 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2437866955 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:04 PM PDT 24 498017971 ps
T397 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1283683550 Jul 16 06:40:59 PM PDT 24 Jul 16 06:41:02 PM PDT 24 4686023847 ps
T398 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2439223660 Jul 16 06:40:39 PM PDT 24 Jul 16 06:40:41 PM PDT 24 414419087 ps
T399 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.223702460 Jul 16 06:40:34 PM PDT 24 Jul 16 06:40:36 PM PDT 24 295583768 ps
T400 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.310443759 Jul 16 06:41:02 PM PDT 24 Jul 16 06:41:04 PM PDT 24 365228314 ps
T401 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1079034493 Jul 16 06:41:03 PM PDT 24 Jul 16 06:41:06 PM PDT 24 449600451 ps
T402 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1352809090 Jul 16 06:40:40 PM PDT 24 Jul 16 06:40:43 PM PDT 24 1138381727 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1472674155 Jul 16 06:40:48 PM PDT 24 Jul 16 06:40:52 PM PDT 24 7266601522 ps
T404 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3387850586 Jul 16 06:41:15 PM PDT 24 Jul 16 06:41:19 PM PDT 24 1476195738 ps
T405 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2225045857 Jul 16 06:41:28 PM PDT 24 Jul 16 06:41:30 PM PDT 24 387802053 ps
T406 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2813604021 Jul 16 06:41:29 PM PDT 24 Jul 16 06:41:32 PM PDT 24 375033058 ps
T407 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2005915638 Jul 16 06:41:00 PM PDT 24 Jul 16 06:41:02 PM PDT 24 379474292 ps
T408 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.473880029 Jul 16 06:40:46 PM PDT 24 Jul 16 06:40:51 PM PDT 24 2827878046 ps
T409 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1633341873 Jul 16 06:40:38 PM PDT 24 Jul 16 06:40:40 PM PDT 24 783964950 ps
T188 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.723610581 Jul 16 06:40:57 PM PDT 24 Jul 16 06:41:02 PM PDT 24 4046829471 ps
T410 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3071329561 Jul 16 06:41:31 PM PDT 24 Jul 16 06:41:34 PM PDT 24 400543014 ps
T411 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.241629778 Jul 16 06:41:12 PM PDT 24 Jul 16 06:41:14 PM PDT 24 410540677 ps
T412 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2803356780 Jul 16 06:41:38 PM PDT 24 Jul 16 06:41:39 PM PDT 24 378895206 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3766415590 Jul 16 06:41:00 PM PDT 24 Jul 16 06:41:02 PM PDT 24 277712352 ps
T414 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3066722375 Jul 16 06:41:27 PM PDT 24 Jul 16 06:41:30 PM PDT 24 389858139 ps
T415 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3254619198 Jul 16 06:41:27 PM PDT 24 Jul 16 06:41:29 PM PDT 24 388538483 ps
T416 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1003605701 Jul 16 06:41:28 PM PDT 24 Jul 16 06:41:31 PM PDT 24 1114110195 ps
T417 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3625370629 Jul 16 06:41:32 PM PDT 24 Jul 16 06:41:34 PM PDT 24 503804518 ps
T418 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4294741753 Jul 16 06:41:03 PM PDT 24 Jul 16 06:41:08 PM PDT 24 1135134820 ps
T419 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2124489811 Jul 16 06:41:32 PM PDT 24 Jul 16 06:41:35 PM PDT 24 462556710 ps
T420 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.602607470 Jul 16 06:41:29 PM PDT 24 Jul 16 06:41:33 PM PDT 24 580749664 ps

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1169181775
Short name T4
Test name
Test status
Simulation time 82196665470 ps
CPU time 897.95 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:55:05 PM PDT 24
Peak memory 209396 kb
Host smart-bd3fe7cd-9fc4-48de-b741-ccbc445784fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169181775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1169181775
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1718736079
Short name T17
Test name
Test status
Simulation time 97323866868 ps
CPU time 1057.53 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:57:44 PM PDT 24
Peak memory 214920 kb
Host smart-e969b597-1e26-44c1-bfc2-29d5e350025c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718736079 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1718736079
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3202410873
Short name T35
Test name
Test status
Simulation time 8542055665 ps
CPU time 14.37 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:51 PM PDT 24
Peak memory 198136 kb
Host smart-4dfec74a-6d88-40d7-9e2d-8c4454eba8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202410873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3202410873
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.587950357
Short name T80
Test name
Test status
Simulation time 159492453116 ps
CPU time 1004.46 seconds
Started Jul 16 06:39:29 PM PDT 24
Finished Jul 16 06:56:15 PM PDT 24
Peak memory 215036 kb
Host smart-41accf47-be34-4c98-8171-84c113f58359
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587950357 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.587950357
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3981440684
Short name T7
Test name
Test status
Simulation time 26746200473 ps
CPU time 40.68 seconds
Started Jul 16 06:39:45 PM PDT 24
Finished Jul 16 06:40:27 PM PDT 24
Peak memory 191956 kb
Host smart-347cf333-3024-49f1-8b47-0153c849d813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981440684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3981440684
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2722823426
Short name T50
Test name
Test status
Simulation time 374668873239 ps
CPU time 870.64 seconds
Started Jul 16 06:39:44 PM PDT 24
Finished Jul 16 06:54:16 PM PDT 24
Peak memory 214988 kb
Host smart-5f428a5c-faec-418d-a9f8-6f82fb4a7a24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722823426 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2722823426
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.582302289
Short name T84
Test name
Test status
Simulation time 1052464144104 ps
CPU time 1427.8 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 07:03:56 PM PDT 24
Peak memory 215180 kb
Host smart-4242fff5-70f0-4279-af6a-3885978b0bcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582302289 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.582302289
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2236928389
Short name T59
Test name
Test status
Simulation time 154916817784 ps
CPU time 489.44 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:47:54 PM PDT 24
Peak memory 214100 kb
Host smart-0690cc48-0631-45b7-ad3c-43fb728a747b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236928389 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2236928389
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1380336145
Short name T108
Test name
Test status
Simulation time 467046590775 ps
CPU time 661.23 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:51:38 PM PDT 24
Peak memory 207072 kb
Host smart-a2344c78-4b6e-4e6d-a322-b0706742c5d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380336145 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1380336145
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3229744197
Short name T81
Test name
Test status
Simulation time 38435225153 ps
CPU time 248.86 seconds
Started Jul 16 06:39:44 PM PDT 24
Finished Jul 16 06:43:54 PM PDT 24
Peak memory 206844 kb
Host smart-26f61b39-6765-40fb-a742-f93b7759a250
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229744197 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3229744197
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3860316129
Short name T127
Test name
Test status
Simulation time 42033811977 ps
CPU time 333.05 seconds
Started Jul 16 06:40:32 PM PDT 24
Finished Jul 16 06:46:06 PM PDT 24
Peak memory 207460 kb
Host smart-8585a3b5-8bdd-4805-96b8-8475d1dd9121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860316129 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3860316129
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4136047144
Short name T22
Test name
Test status
Simulation time 3836127798 ps
CPU time 3.49 seconds
Started Jul 16 06:39:31 PM PDT 24
Finished Jul 16 06:39:35 PM PDT 24
Peak memory 215252 kb
Host smart-549836bd-00fe-4577-ab23-db32d7840b4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136047144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4136047144
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4195118071
Short name T140
Test name
Test status
Simulation time 105749696365 ps
CPU time 191.26 seconds
Started Jul 16 06:39:33 PM PDT 24
Finished Jul 16 06:42:45 PM PDT 24
Peak memory 213964 kb
Host smart-da5aa4c0-0f8f-46e3-94b8-0c51164e065f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195118071 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4195118071
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3067305867
Short name T147
Test name
Test status
Simulation time 67085999551 ps
CPU time 711.37 seconds
Started Jul 16 06:40:06 PM PDT 24
Finished Jul 16 06:52:00 PM PDT 24
Peak memory 205424 kb
Host smart-70980f8f-d717-481d-aa40-ae2728417ef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067305867 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3067305867
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3112171130
Short name T135
Test name
Test status
Simulation time 95464472842 ps
CPU time 811.02 seconds
Started Jul 16 06:40:32 PM PDT 24
Finished Jul 16 06:54:03 PM PDT 24
Peak memory 208040 kb
Host smart-a9f05a75-7fe1-4d31-bf0e-d29406b02f20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112171130 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3112171130
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2190149070
Short name T121
Test name
Test status
Simulation time 145402078782 ps
CPU time 500.09 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:48:48 PM PDT 24
Peak memory 203700 kb
Host smart-b963e67e-6027-4ae9-8d58-b702071b6e2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190149070 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2190149070
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.181263004
Short name T113
Test name
Test status
Simulation time 76571968886 ps
CPU time 28.21 seconds
Started Jul 16 06:39:37 PM PDT 24
Finished Jul 16 06:40:06 PM PDT 24
Peak memory 184268 kb
Host smart-59ddec1b-c3ae-460f-9a36-88ff3f2335f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181263004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.181263004
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3010988640
Short name T118
Test name
Test status
Simulation time 240237309428 ps
CPU time 321.47 seconds
Started Jul 16 06:40:03 PM PDT 24
Finished Jul 16 06:45:25 PM PDT 24
Peak memory 192008 kb
Host smart-4fbc1e64-0929-4e01-88ea-b891741d94b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010988640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3010988640
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3997143118
Short name T128
Test name
Test status
Simulation time 188660544088 ps
CPU time 93.07 seconds
Started Jul 16 06:39:55 PM PDT 24
Finished Jul 16 06:41:29 PM PDT 24
Peak memory 198328 kb
Host smart-6c0faa48-1989-446c-ae66-ac67acb35348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997143118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3997143118
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3023392470
Short name T91
Test name
Test status
Simulation time 202469518260 ps
CPU time 785.25 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:53:33 PM PDT 24
Peak memory 214912 kb
Host smart-4a5ea31c-3db9-4ccf-8dd9-3d0b4b159399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023392470 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3023392470
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3946064802
Short name T82
Test name
Test status
Simulation time 476682430092 ps
CPU time 399.76 seconds
Started Jul 16 06:39:44 PM PDT 24
Finished Jul 16 06:46:25 PM PDT 24
Peak memory 211176 kb
Host smart-3ace3dae-232d-40e0-8d7b-e21fe79c381b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946064802 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3946064802
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.93016733
Short name T3
Test name
Test status
Simulation time 205372566892 ps
CPU time 547.89 seconds
Started Jul 16 06:39:44 PM PDT 24
Finished Jul 16 06:48:53 PM PDT 24
Peak memory 214932 kb
Host smart-4657021a-0c04-478a-afee-87186dd3f336
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93016733 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.93016733
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1817273532
Short name T124
Test name
Test status
Simulation time 63197748265 ps
CPU time 87.07 seconds
Started Jul 16 06:39:39 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 184456 kb
Host smart-48e5957f-e456-4d03-8922-a61927643e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817273532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1817273532
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3446871276
Short name T100
Test name
Test status
Simulation time 3683638539 ps
CPU time 2.31 seconds
Started Jul 16 06:39:45 PM PDT 24
Finished Jul 16 06:39:48 PM PDT 24
Peak memory 191968 kb
Host smart-2b87dabb-b173-4a55-a2e0-fdb1a21d381e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446871276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3446871276
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2528235343
Short name T106
Test name
Test status
Simulation time 227615601436 ps
CPU time 173.58 seconds
Started Jul 16 06:39:26 PM PDT 24
Finished Jul 16 06:42:21 PM PDT 24
Peak memory 198308 kb
Host smart-87729c69-34aa-43ee-bcf4-206d409eac59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528235343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2528235343
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.751153989
Short name T114
Test name
Test status
Simulation time 139483358624 ps
CPU time 82.39 seconds
Started Jul 16 06:40:06 PM PDT 24
Finished Jul 16 06:41:31 PM PDT 24
Peak memory 192584 kb
Host smart-66f0121b-b3d0-4e7f-94c8-e3874834e2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751153989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.751153989
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1766693669
Short name T45
Test name
Test status
Simulation time 67874195413 ps
CPU time 135.93 seconds
Started Jul 16 06:40:27 PM PDT 24
Finished Jul 16 06:42:44 PM PDT 24
Peak memory 206840 kb
Host smart-63cc2a70-0cfe-4115-b11d-04c05e5da0d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766693669 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1766693669
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1162201665
Short name T102
Test name
Test status
Simulation time 103514843385 ps
CPU time 10.69 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:40:05 PM PDT 24
Peak memory 192728 kb
Host smart-5c2ae4ea-3851-4af1-8e38-fe4080c74567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162201665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1162201665
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.416114037
Short name T104
Test name
Test status
Simulation time 281750166514 ps
CPU time 177.42 seconds
Started Jul 16 06:40:07 PM PDT 24
Finished Jul 16 06:43:06 PM PDT 24
Peak memory 198212 kb
Host smart-ebb7ab91-ef1e-4cf2-a32b-e2a0ca3fca74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416114037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.416114037
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4214323462
Short name T62
Test name
Test status
Simulation time 10372551906 ps
CPU time 22.94 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:41:11 PM PDT 24
Peak memory 196076 kb
Host smart-d234802c-9e4e-415e-b4e9-f15d5b0ea5d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214323462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4214323462
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2641951822
Short name T48
Test name
Test status
Simulation time 30019246602 ps
CPU time 299.88 seconds
Started Jul 16 06:39:38 PM PDT 24
Finished Jul 16 06:44:39 PM PDT 24
Peak memory 198644 kb
Host smart-16c5410a-75ce-440f-a5ae-0b201b5f0fc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641951822 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2641951822
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.707407907
Short name T86
Test name
Test status
Simulation time 36006102659 ps
CPU time 256.63 seconds
Started Jul 16 06:40:07 PM PDT 24
Finished Jul 16 06:44:26 PM PDT 24
Peak memory 214984 kb
Host smart-8074db8c-c701-45e8-ab4f-6f191b1321d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707407907 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.707407907
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.62148386
Short name T115
Test name
Test status
Simulation time 255210721393 ps
CPU time 321.04 seconds
Started Jul 16 06:40:25 PM PDT 24
Finished Jul 16 06:45:48 PM PDT 24
Peak memory 198308 kb
Host smart-9db9f745-81d2-406f-a6dc-d60a797d0fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62148386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_al
l.62148386
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3288095768
Short name T107
Test name
Test status
Simulation time 370845714278 ps
CPU time 474.07 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:47:36 PM PDT 24
Peak memory 192980 kb
Host smart-fccc6cd3-dd0a-4206-9ede-9cff49d1ac23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288095768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3288095768
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1269858808
Short name T143
Test name
Test status
Simulation time 32521180919 ps
CPU time 10.91 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:40:05 PM PDT 24
Peak memory 198348 kb
Host smart-302489b8-189b-4f45-ab0a-553074930a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269858808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1269858808
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2116042369
Short name T103
Test name
Test status
Simulation time 152846963876 ps
CPU time 221.46 seconds
Started Jul 16 06:40:08 PM PDT 24
Finished Jul 16 06:43:51 PM PDT 24
Peak memory 193048 kb
Host smart-53fed4a3-c2b3-4be8-8edd-3d27814e566f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116042369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2116042369
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2754891282
Short name T43
Test name
Test status
Simulation time 9638241482 ps
CPU time 62.31 seconds
Started Jul 16 06:39:44 PM PDT 24
Finished Jul 16 06:40:48 PM PDT 24
Peak memory 206800 kb
Host smart-4b589422-fe8f-4ce1-9146-e0a14cee6b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754891282 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2754891282
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3263257932
Short name T142
Test name
Test status
Simulation time 164173227319 ps
CPU time 131.02 seconds
Started Jul 16 06:40:27 PM PDT 24
Finished Jul 16 06:42:40 PM PDT 24
Peak memory 198260 kb
Host smart-c0355d68-2066-4974-94d4-791c2b3bd243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263257932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3263257932
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2231570802
Short name T141
Test name
Test status
Simulation time 69759130571 ps
CPU time 106.88 seconds
Started Jul 16 06:40:39 PM PDT 24
Finished Jul 16 06:42:27 PM PDT 24
Peak memory 193024 kb
Host smart-88d85178-3fea-445f-adf8-d245d8511d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231570802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2231570802
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3897998163
Short name T123
Test name
Test status
Simulation time 176773373697 ps
CPU time 174.96 seconds
Started Jul 16 06:39:48 PM PDT 24
Finished Jul 16 06:42:44 PM PDT 24
Peak memory 198140 kb
Host smart-b3a0fac3-76b8-472e-9e87-058742c36813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897998163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3897998163
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2572460691
Short name T85
Test name
Test status
Simulation time 64914536787 ps
CPU time 122.16 seconds
Started Jul 16 06:40:02 PM PDT 24
Finished Jul 16 06:42:05 PM PDT 24
Peak memory 214248 kb
Host smart-82565324-eafc-4926-a5a3-126271cc8571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572460691 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2572460691
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.677862906
Short name T87
Test name
Test status
Simulation time 41215932556 ps
CPU time 330.6 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:45:38 PM PDT 24
Peak memory 214128 kb
Host smart-db98e8ef-24a9-494d-89b1-8d6804a8aa23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677862906 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.677862906
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3137986217
Short name T44
Test name
Test status
Simulation time 35772366711 ps
CPU time 285.9 seconds
Started Jul 16 06:39:31 PM PDT 24
Finished Jul 16 06:44:18 PM PDT 24
Peak memory 198548 kb
Host smart-e2e3b583-a7f1-452a-a8f3-a342b0712042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137986217 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3137986217
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3605898493
Short name T101
Test name
Test status
Simulation time 176929826184 ps
CPU time 47.64 seconds
Started Jul 16 06:39:46 PM PDT 24
Finished Jul 16 06:40:34 PM PDT 24
Peak memory 193012 kb
Host smart-190e97f3-5384-4399-92c1-4a5be744d19c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605898493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3605898493
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1801849493
Short name T31
Test name
Test status
Simulation time 45417796783 ps
CPU time 188.02 seconds
Started Jul 16 06:39:56 PM PDT 24
Finished Jul 16 06:43:04 PM PDT 24
Peak memory 206820 kb
Host smart-35dde372-eaab-4659-bb41-c1b830a4937a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801849493 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1801849493
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1934107786
Short name T88
Test name
Test status
Simulation time 74932756850 ps
CPU time 550.96 seconds
Started Jul 16 06:40:39 PM PDT 24
Finished Jul 16 06:49:51 PM PDT 24
Peak memory 203936 kb
Host smart-65196d33-eb5a-40b2-ba3f-ae9122ff7ad5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934107786 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1934107786
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.512354973
Short name T153
Test name
Test status
Simulation time 103404227613 ps
CPU time 552.04 seconds
Started Jul 16 06:39:30 PM PDT 24
Finished Jul 16 06:48:44 PM PDT 24
Peak memory 205480 kb
Host smart-c948b575-5ca5-4783-8f76-c38774040f37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512354973 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.512354973
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2207646606
Short name T105
Test name
Test status
Simulation time 382528078205 ps
CPU time 567.14 seconds
Started Jul 16 06:39:47 PM PDT 24
Finished Jul 16 06:49:15 PM PDT 24
Peak memory 193028 kb
Host smart-18b00177-3120-4d27-b6af-508a93dc1ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207646606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2207646606
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1608956212
Short name T32
Test name
Test status
Simulation time 45963673886 ps
CPU time 12.64 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:40:40 PM PDT 24
Peak memory 198348 kb
Host smart-6c1a802d-cee6-46f2-9abe-0ee52d0c7e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608956212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1608956212
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1263886497
Short name T33
Test name
Test status
Simulation time 80192674629 ps
CPU time 29.5 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:40:23 PM PDT 24
Peak memory 193028 kb
Host smart-6ed70de9-8473-431f-99d6-89d84697dcaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263886497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1263886497
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2139103874
Short name T138
Test name
Test status
Simulation time 75857212131 ps
CPU time 104.32 seconds
Started Jul 16 06:39:32 PM PDT 24
Finished Jul 16 06:41:17 PM PDT 24
Peak memory 198296 kb
Host smart-e4ba16be-3a38-43c7-ae97-e63884c5084a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139103874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2139103874
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3541417491
Short name T28
Test name
Test status
Simulation time 337371407351 ps
CPU time 75.83 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:41:43 PM PDT 24
Peak memory 198472 kb
Host smart-13c2e85a-7a33-4083-85b7-2b3766467cf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541417491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3541417491
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3252215331
Short name T47
Test name
Test status
Simulation time 62938955265 ps
CPU time 547.24 seconds
Started Jul 16 06:39:35 PM PDT 24
Finished Jul 16 06:48:43 PM PDT 24
Peak memory 211388 kb
Host smart-acccb585-b80c-4e49-a462-58fee11bfd23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252215331 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3252215331
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1952783974
Short name T89
Test name
Test status
Simulation time 176311235916 ps
CPU time 355.53 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:46:23 PM PDT 24
Peak memory 202092 kb
Host smart-1af44360-ed37-47fe-8dc2-8c7e64dea840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952783974 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1952783974
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3091752082
Short name T120
Test name
Test status
Simulation time 49396889074 ps
CPU time 52.49 seconds
Started Jul 16 06:40:04 PM PDT 24
Finished Jul 16 06:40:58 PM PDT 24
Peak memory 198368 kb
Host smart-30b0eb14-c294-4a56-8188-89e3fd56455c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091752082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3091752082
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1334794978
Short name T52
Test name
Test status
Simulation time 172823911363 ps
CPU time 57.55 seconds
Started Jul 16 06:39:35 PM PDT 24
Finished Jul 16 06:40:33 PM PDT 24
Peak memory 191988 kb
Host smart-93d8e38f-8f03-4755-a965-3906b60200bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334794978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1334794978
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3559755435
Short name T46
Test name
Test status
Simulation time 401110968730 ps
CPU time 552.02 seconds
Started Jul 16 06:40:34 PM PDT 24
Finished Jul 16 06:49:47 PM PDT 24
Peak memory 212896 kb
Host smart-5e716dc4-48fd-449c-a761-37707b05e44e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559755435 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3559755435
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2021867541
Short name T5
Test name
Test status
Simulation time 85520425846 ps
CPU time 15.4 seconds
Started Jul 16 06:39:30 PM PDT 24
Finished Jul 16 06:39:47 PM PDT 24
Peak memory 198272 kb
Host smart-9945a9bb-407b-405b-a2d4-52015b4b7d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021867541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2021867541
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2512211990
Short name T75
Test name
Test status
Simulation time 3105777920 ps
CPU time 0.9 seconds
Started Jul 16 06:40:33 PM PDT 24
Finished Jul 16 06:40:35 PM PDT 24
Peak memory 183988 kb
Host smart-ea7deafe-e18d-4731-bebc-8faf841b0741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512211990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2512211990
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3183740259
Short name T132
Test name
Test status
Simulation time 157174103310 ps
CPU time 232.14 seconds
Started Jul 16 06:40:40 PM PDT 24
Finished Jul 16 06:44:33 PM PDT 24
Peak memory 193000 kb
Host smart-1587c9c2-3fcd-4c53-8a82-8045b2204587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183740259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3183740259
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2821412194
Short name T137
Test name
Test status
Simulation time 119231787340 ps
CPU time 244.11 seconds
Started Jul 16 06:39:42 PM PDT 24
Finished Jul 16 06:43:47 PM PDT 24
Peak memory 214952 kb
Host smart-300bfb2b-c697-4194-8f14-89fd982d947f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821412194 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2821412194
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2695465084
Short name T155
Test name
Test status
Simulation time 187455789033 ps
CPU time 374.73 seconds
Started Jul 16 06:39:44 PM PDT 24
Finished Jul 16 06:46:01 PM PDT 24
Peak memory 202332 kb
Host smart-c1183307-da78-4fba-9d21-251f99cb7127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695465084 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2695465084
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.136521251
Short name T151
Test name
Test status
Simulation time 80179002323 ps
CPU time 158.23 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:42:21 PM PDT 24
Peak memory 214268 kb
Host smart-451bc412-87e2-4bda-a6eb-226e5091904c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136521251 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.136521251
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1898690565
Short name T133
Test name
Test status
Simulation time 110467891007 ps
CPU time 607.88 seconds
Started Jul 16 06:40:29 PM PDT 24
Finished Jul 16 06:50:38 PM PDT 24
Peak memory 207144 kb
Host smart-102adb44-fb4e-420c-a35e-9157c34f8d4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898690565 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1898690565
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.338621767
Short name T58
Test name
Test status
Simulation time 196909986894 ps
CPU time 397.15 seconds
Started Jul 16 06:40:28 PM PDT 24
Finished Jul 16 06:47:07 PM PDT 24
Peak memory 206844 kb
Host smart-c847cf39-8438-4b11-9168-ff7eb46d8df3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338621767 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.338621767
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2777728479
Short name T122
Test name
Test status
Simulation time 29951776752 ps
CPU time 11.41 seconds
Started Jul 16 06:40:37 PM PDT 24
Finished Jul 16 06:40:49 PM PDT 24
Peak memory 192052 kb
Host smart-94eec5fe-ce3e-48fc-bac7-f65c8cef6340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777728479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2777728479
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1887091321
Short name T110
Test name
Test status
Simulation time 63194602923 ps
CPU time 692.07 seconds
Started Jul 16 06:40:01 PM PDT 24
Finished Jul 16 06:51:35 PM PDT 24
Peak memory 213508 kb
Host smart-88d3e8de-cd42-48a2-953a-eff9ef849e63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887091321 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1887091321
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1237170623
Short name T159
Test name
Test status
Simulation time 101722454038 ps
CPU time 19.24 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:25 PM PDT 24
Peak memory 191984 kb
Host smart-82eea6af-3178-45fe-ac2b-0a5cea16f085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237170623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1237170623
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3775287598
Short name T25
Test name
Test status
Simulation time 382676542 ps
CPU time 1.09 seconds
Started Jul 16 06:40:25 PM PDT 24
Finished Jul 16 06:40:27 PM PDT 24
Peak memory 196748 kb
Host smart-2d9ed9b9-f4a8-44ba-9e67-c32bcde7c818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775287598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3775287598
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.915092478
Short name T146
Test name
Test status
Simulation time 219793230297 ps
CPU time 157.4 seconds
Started Jul 16 06:39:42 PM PDT 24
Finished Jul 16 06:42:20 PM PDT 24
Peak memory 198344 kb
Host smart-b82addaf-9ff2-4d05-9d22-6866833944c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915092478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.915092478
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2412609956
Short name T6
Test name
Test status
Simulation time 121345337016 ps
CPU time 179.41 seconds
Started Jul 16 06:39:45 PM PDT 24
Finished Jul 16 06:42:45 PM PDT 24
Peak memory 191976 kb
Host smart-41842e60-769d-4223-b466-0dc7a9112127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412609956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2412609956
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1434530266
Short name T126
Test name
Test status
Simulation time 373341043 ps
CPU time 0.7 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:39:54 PM PDT 24
Peak memory 196884 kb
Host smart-2f0a7669-a650-4a54-a123-4c719f17dae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434530266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1434530266
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3863089360
Short name T148
Test name
Test status
Simulation time 346950984055 ps
CPU time 141.49 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:42:28 PM PDT 24
Peak memory 192772 kb
Host smart-e2df89d9-e604-44a3-90cf-71cbb93e1e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863089360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3863089360
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4289632705
Short name T99
Test name
Test status
Simulation time 557055859 ps
CPU time 0.98 seconds
Started Jul 16 06:40:06 PM PDT 24
Finished Jul 16 06:40:09 PM PDT 24
Peak memory 196772 kb
Host smart-e8cd92e6-b5dc-4b1e-8fc2-d48502028964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289632705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4289632705
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.410601792
Short name T90
Test name
Test status
Simulation time 98300460367 ps
CPU time 343.04 seconds
Started Jul 16 06:40:27 PM PDT 24
Finished Jul 16 06:46:12 PM PDT 24
Peak memory 210208 kb
Host smart-c31fec54-390c-4e56-a4fb-832bfc6c552b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410601792 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.410601792
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.652587140
Short name T131
Test name
Test status
Simulation time 509058298 ps
CPU time 1.31 seconds
Started Jul 16 06:40:28 PM PDT 24
Finished Jul 16 06:40:31 PM PDT 24
Peak memory 196804 kb
Host smart-3d6446fd-8e92-43b3-ab72-3d3ce1c2b1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652587140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.652587140
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4098321488
Short name T130
Test name
Test status
Simulation time 349306878 ps
CPU time 1.08 seconds
Started Jul 16 06:39:44 PM PDT 24
Finished Jul 16 06:39:46 PM PDT 24
Peak memory 196720 kb
Host smart-38de6a08-c548-4ece-bcff-9dd9bcd09ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098321488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4098321488
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3750592515
Short name T163
Test name
Test status
Simulation time 72300494376 ps
CPU time 535.41 seconds
Started Jul 16 06:40:03 PM PDT 24
Finished Jul 16 06:48:59 PM PDT 24
Peak memory 206836 kb
Host smart-eb538f11-4d0a-4c03-a7d0-253c2c2bd0c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750592515 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3750592515
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2579474915
Short name T125
Test name
Test status
Simulation time 593585541 ps
CPU time 0.71 seconds
Started Jul 16 06:40:06 PM PDT 24
Finished Jul 16 06:40:09 PM PDT 24
Peak memory 196704 kb
Host smart-f094df01-87c9-46f6-a149-4c920175c1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579474915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2579474915
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.539235565
Short name T119
Test name
Test status
Simulation time 146718062732 ps
CPU time 12.95 seconds
Started Jul 16 06:40:27 PM PDT 24
Finished Jul 16 06:40:42 PM PDT 24
Peak memory 191960 kb
Host smart-f7a1ecd1-dbbf-4029-84a2-539d3db557c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539235565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.539235565
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.75829503
Short name T117
Test name
Test status
Simulation time 435497464 ps
CPU time 0.9 seconds
Started Jul 16 06:39:31 PM PDT 24
Finished Jul 16 06:39:33 PM PDT 24
Peak memory 196736 kb
Host smart-13818483-2843-44ea-a11e-a6cffa5a7db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75829503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.75829503
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3788275747
Short name T13
Test name
Test status
Simulation time 79172076018 ps
CPU time 27.17 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:40:19 PM PDT 24
Peak memory 191924 kb
Host smart-cd2773e4-3d4a-4e6e-8b75-4ee41a7d530d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788275747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3788275747
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.113353888
Short name T136
Test name
Test status
Simulation time 441712357 ps
CPU time 0.71 seconds
Started Jul 16 06:39:54 PM PDT 24
Finished Jul 16 06:39:55 PM PDT 24
Peak memory 196700 kb
Host smart-38e2be98-a696-4313-b294-857ab1275a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113353888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.113353888
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2931948835
Short name T30
Test name
Test status
Simulation time 59227027933 ps
CPU time 461.04 seconds
Started Jul 16 06:40:03 PM PDT 24
Finished Jul 16 06:47:45 PM PDT 24
Peak memory 213992 kb
Host smart-92bc290d-9e45-4e75-bd8b-4affe0f090c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931948835 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2931948835
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1506902368
Short name T95
Test name
Test status
Simulation time 602077721 ps
CPU time 0.79 seconds
Started Jul 16 06:40:29 PM PDT 24
Finished Jul 16 06:40:31 PM PDT 24
Peak memory 196752 kb
Host smart-e933c3a8-a8d1-44c1-b75c-3240bd0b6c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506902368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1506902368
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.392868655
Short name T109
Test name
Test status
Simulation time 403868119 ps
CPU time 0.73 seconds
Started Jul 16 06:39:36 PM PDT 24
Finished Jul 16 06:39:37 PM PDT 24
Peak memory 196620 kb
Host smart-d2042029-5aa5-4637-80fc-6faa8e8a1089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392868655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.392868655
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1790039436
Short name T116
Test name
Test status
Simulation time 527239132 ps
CPU time 1.38 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:39:46 PM PDT 24
Peak memory 196648 kb
Host smart-6c42bce5-4dd4-4304-8948-4678cfaf13ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790039436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1790039436
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1177326663
Short name T111
Test name
Test status
Simulation time 572164160 ps
CPU time 1.33 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:39:56 PM PDT 24
Peak memory 196780 kb
Host smart-dcdaec25-dc8a-457f-9357-ee2c342ee9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177326663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1177326663
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.539148061
Short name T129
Test name
Test status
Simulation time 424152886 ps
CPU time 1.21 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:39:56 PM PDT 24
Peak memory 196808 kb
Host smart-fde678e9-bd46-484a-80b4-12442962d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539148061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.539148061
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.808388053
Short name T177
Test name
Test status
Simulation time 174265105280 ps
CPU time 208.82 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:43:23 PM PDT 24
Peak memory 191832 kb
Host smart-8c75f1bf-5c0b-4060-83ee-b91d1fd3640b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808388053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.808388053
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.50714920
Short name T34
Test name
Test status
Simulation time 565988770 ps
CPU time 0.79 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:07 PM PDT 24
Peak memory 196732 kb
Host smart-967517c8-eb0c-4f6b-be46-ba8933249f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50714920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.50714920
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2304330618
Short name T144
Test name
Test status
Simulation time 555261189 ps
CPU time 1.38 seconds
Started Jul 16 06:39:35 PM PDT 24
Finished Jul 16 06:39:37 PM PDT 24
Peak memory 196676 kb
Host smart-030d6d2b-3959-4133-a7eb-025d695ee54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304330618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2304330618
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1500622579
Short name T169
Test name
Test status
Simulation time 218415322446 ps
CPU time 75.27 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:41:43 PM PDT 24
Peak memory 193012 kb
Host smart-e4c3504e-bd20-470d-acef-f251719cbdb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500622579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1500622579
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2037320617
Short name T16
Test name
Test status
Simulation time 237952831633 ps
CPU time 301.08 seconds
Started Jul 16 06:40:28 PM PDT 24
Finished Jul 16 06:45:31 PM PDT 24
Peak memory 191976 kb
Host smart-70858a80-0b52-473f-b603-6290fc72378b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037320617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2037320617
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1894581588
Short name T97
Test name
Test status
Simulation time 569394070 ps
CPU time 1.41 seconds
Started Jul 16 06:40:29 PM PDT 24
Finished Jul 16 06:40:31 PM PDT 24
Peak memory 196728 kb
Host smart-a4600b7b-9bc4-4087-8b58-b1bd3d378f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894581588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1894581588
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3411292323
Short name T139
Test name
Test status
Simulation time 446613226 ps
CPU time 0.73 seconds
Started Jul 16 06:40:28 PM PDT 24
Finished Jul 16 06:40:30 PM PDT 24
Peak memory 196616 kb
Host smart-d56ecc7d-faf4-463e-8012-f1b8f07eeeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411292323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3411292323
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3905350583
Short name T112
Test name
Test status
Simulation time 450977893 ps
CPU time 0.77 seconds
Started Jul 16 06:39:48 PM PDT 24
Finished Jul 16 06:39:50 PM PDT 24
Peak memory 196560 kb
Host smart-074e4f07-915c-46c0-b934-2339b641a8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905350583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3905350583
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.106473393
Short name T10
Test name
Test status
Simulation time 428589082 ps
CPU time 1.2 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:39:56 PM PDT 24
Peak memory 196664 kb
Host smart-86e5b387-4240-482e-9898-a96111dbaf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106473393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.106473393
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2920727207
Short name T168
Test name
Test status
Simulation time 123286782701 ps
CPU time 33.24 seconds
Started Jul 16 06:40:30 PM PDT 24
Finished Jul 16 06:41:05 PM PDT 24
Peak memory 198332 kb
Host smart-f4ef74e9-c59e-4bf8-91cd-546b9ceb1d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920727207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2920727207
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.4026869976
Short name T175
Test name
Test status
Simulation time 533398460874 ps
CPU time 841.15 seconds
Started Jul 16 06:40:36 PM PDT 24
Finished Jul 16 06:54:38 PM PDT 24
Peak memory 191984 kb
Host smart-29c9ee4a-fba2-400a-af9e-7e1540a9c95f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026869976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.4026869976
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1684780763
Short name T49
Test name
Test status
Simulation time 351653941 ps
CPU time 1.16 seconds
Started Jul 16 06:39:37 PM PDT 24
Finished Jul 16 06:39:38 PM PDT 24
Peak memory 196704 kb
Host smart-047c085d-3f0c-431b-8a5c-a15c22152977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684780763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1684780763
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1043334808
Short name T161
Test name
Test status
Simulation time 499880004 ps
CPU time 0.74 seconds
Started Jul 16 06:39:45 PM PDT 24
Finished Jul 16 06:39:47 PM PDT 24
Peak memory 196664 kb
Host smart-1869c877-c907-463a-9491-e40b5782554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043334808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1043334808
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4222940552
Short name T162
Test name
Test status
Simulation time 381756683 ps
CPU time 1.17 seconds
Started Jul 16 06:39:29 PM PDT 24
Finished Jul 16 06:39:31 PM PDT 24
Peak memory 196720 kb
Host smart-1e7fbd2d-c2c7-4395-8f88-a51cca9e555f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222940552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4222940552
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.555048291
Short name T79
Test name
Test status
Simulation time 107663157518 ps
CPU time 754.73 seconds
Started Jul 16 06:40:01 PM PDT 24
Finished Jul 16 06:52:37 PM PDT 24
Peak memory 205132 kb
Host smart-2937fd81-76a9-454f-b212-f3912d13791b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555048291 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.555048291
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.4012554376
Short name T83
Test name
Test status
Simulation time 58928704103 ps
CPU time 499.23 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:48:27 PM PDT 24
Peak memory 206728 kb
Host smart-6891c64f-8af6-46f5-a67a-dc9e93fadbc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012554376 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.4012554376
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2101779102
Short name T158
Test name
Test status
Simulation time 308876165070 ps
CPU time 118.01 seconds
Started Jul 16 06:40:07 PM PDT 24
Finished Jul 16 06:42:07 PM PDT 24
Peak memory 191836 kb
Host smart-9efc851b-874e-4204-88e3-c4d512faca70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101779102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2101779102
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.544704628
Short name T12
Test name
Test status
Simulation time 609981456 ps
CPU time 0.69 seconds
Started Jul 16 06:40:08 PM PDT 24
Finished Jul 16 06:40:10 PM PDT 24
Peak memory 196548 kb
Host smart-75ec8f16-9d81-497d-a7f9-b59006da970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544704628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.544704628
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.654567807
Short name T166
Test name
Test status
Simulation time 252682487558 ps
CPU time 190.93 seconds
Started Jul 16 06:40:07 PM PDT 24
Finished Jul 16 06:43:20 PM PDT 24
Peak memory 192536 kb
Host smart-33933136-bce1-4e4b-b165-e61480fbf7e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654567807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.654567807
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1248273027
Short name T27
Test name
Test status
Simulation time 347615593852 ps
CPU time 187.18 seconds
Started Jul 16 06:40:28 PM PDT 24
Finished Jul 16 06:43:37 PM PDT 24
Peak memory 198324 kb
Host smart-340f07ce-7a37-4fd8-bbe0-1e3e277afe64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248273027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1248273027
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.4172298625
Short name T176
Test name
Test status
Simulation time 413933617288 ps
CPU time 141.18 seconds
Started Jul 16 06:40:38 PM PDT 24
Finished Jul 16 06:43:01 PM PDT 24
Peak memory 193000 kb
Host smart-c2c8d10d-f94a-4a8c-8019-5a9d49e685c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172298625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.4172298625
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.479993082
Short name T152
Test name
Test status
Simulation time 374116947 ps
CPU time 1.12 seconds
Started Jul 16 06:40:37 PM PDT 24
Finished Jul 16 06:40:39 PM PDT 24
Peak memory 196596 kb
Host smart-9fd915a4-b2cd-4a14-a69d-82e1cb198351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479993082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.479993082
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4178095259
Short name T173
Test name
Test status
Simulation time 420302159 ps
CPU time 0.91 seconds
Started Jul 16 06:39:42 PM PDT 24
Finished Jul 16 06:39:44 PM PDT 24
Peak memory 196712 kb
Host smart-e0ef3791-d73c-47e5-9756-6db95108566d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178095259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4178095259
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2242887680
Short name T187
Test name
Test status
Simulation time 8442705850 ps
CPU time 4.43 seconds
Started Jul 16 06:41:12 PM PDT 24
Finished Jul 16 06:41:18 PM PDT 24
Peak memory 198388 kb
Host smart-bf710861-e61e-4355-ae00-62c15720ca90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242887680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2242887680
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1888470695
Short name T150
Test name
Test status
Simulation time 343563721956 ps
CPU time 428.38 seconds
Started Jul 16 06:39:42 PM PDT 24
Finished Jul 16 06:46:51 PM PDT 24
Peak memory 198332 kb
Host smart-3b087df7-8863-46e1-a7c0-dd2d07d3bd4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888470695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1888470695
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3278978968
Short name T96
Test name
Test status
Simulation time 171650793491 ps
CPU time 245.88 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:43:51 PM PDT 24
Peak memory 191884 kb
Host smart-19f6d526-d552-4fcd-b9a0-f59b839eaaf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278978968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3278978968
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3084315691
Short name T14
Test name
Test status
Simulation time 479839027 ps
CPU time 0.73 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:39:45 PM PDT 24
Peak memory 196820 kb
Host smart-bf25d685-98dc-4a0d-941a-a47dd1d828ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084315691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3084315691
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4175743491
Short name T180
Test name
Test status
Simulation time 381068575 ps
CPU time 1.07 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:39:54 PM PDT 24
Peak memory 196652 kb
Host smart-2e7783a8-256c-4886-803c-02e2226e8932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175743491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4175743491
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2446226986
Short name T51
Test name
Test status
Simulation time 364226807 ps
CPU time 1.04 seconds
Started Jul 16 06:40:08 PM PDT 24
Finished Jul 16 06:40:11 PM PDT 24
Peak memory 196496 kb
Host smart-544cff0d-88b1-4cdb-bd61-a2f152f6477a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446226986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2446226986
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.339779983
Short name T94
Test name
Test status
Simulation time 546618693 ps
CPU time 0.82 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:07 PM PDT 24
Peak memory 196700 kb
Host smart-2cb1e39c-1de4-4a64-8f39-b7110e57b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339779983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.339779983
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1304558968
Short name T134
Test name
Test status
Simulation time 491444404 ps
CPU time 1.29 seconds
Started Jul 16 06:39:37 PM PDT 24
Finished Jul 16 06:39:39 PM PDT 24
Peak memory 196776 kb
Host smart-c44320a3-ffb7-4ff8-81ed-969e48fa5938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304558968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1304558968
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3782895950
Short name T23
Test name
Test status
Simulation time 475108821 ps
CPU time 1.29 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:09 PM PDT 24
Peak memory 196708 kb
Host smart-f8ba80c2-b2e5-42e9-94f5-dc7e40de96d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782895950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3782895950
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1541116783
Short name T145
Test name
Test status
Simulation time 448301024 ps
CPU time 0.63 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:40:28 PM PDT 24
Peak memory 196728 kb
Host smart-2b6b74c1-6c3e-43c8-a298-40f35394543a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541116783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1541116783
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.937380016
Short name T182
Test name
Test status
Simulation time 537329763 ps
CPU time 1.3 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:37 PM PDT 24
Peak memory 196560 kb
Host smart-47a35564-7cc0-4708-b438-2de8f9de1a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937380016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.937380016
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1343893157
Short name T164
Test name
Test status
Simulation time 587340453 ps
CPU time 1.58 seconds
Started Jul 16 06:39:37 PM PDT 24
Finished Jul 16 06:39:40 PM PDT 24
Peak memory 196668 kb
Host smart-901634fa-97da-4e17-81d0-cf271f985f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343893157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1343893157
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3806561473
Short name T172
Test name
Test status
Simulation time 561194860 ps
CPU time 1.39 seconds
Started Jul 16 06:39:47 PM PDT 24
Finished Jul 16 06:39:49 PM PDT 24
Peak memory 196644 kb
Host smart-ad083c87-bdd6-407e-b7a0-ff150d7e7fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806561473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3806561473
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2252344505
Short name T171
Test name
Test status
Simulation time 590514332 ps
CPU time 1.42 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:39:43 PM PDT 24
Peak memory 196736 kb
Host smart-418ffabc-9a43-45c8-8abd-6c214e45b613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252344505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2252344505
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1290639537
Short name T181
Test name
Test status
Simulation time 86896882254 ps
CPU time 19.99 seconds
Started Jul 16 06:40:07 PM PDT 24
Finished Jul 16 06:40:29 PM PDT 24
Peak memory 198332 kb
Host smart-68f8dcba-f7c3-4f51-a748-ce5b320b8a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290639537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1290639537
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2827388097
Short name T42
Test name
Test status
Simulation time 24923308413 ps
CPU time 102.22 seconds
Started Jul 16 06:39:32 PM PDT 24
Finished Jul 16 06:41:16 PM PDT 24
Peak memory 198800 kb
Host smart-2fd834c7-e4e0-487a-8126-8f565d627972
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827388097 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2827388097
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1460293854
Short name T29
Test name
Test status
Simulation time 440375355 ps
CPU time 1 seconds
Started Jul 16 06:40:07 PM PDT 24
Finished Jul 16 06:40:10 PM PDT 24
Peak memory 196600 kb
Host smart-c206ab11-3f26-47bb-afba-aae193912357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460293854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1460293854
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2305989577
Short name T165
Test name
Test status
Simulation time 568475127 ps
CPU time 1.1 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:09 PM PDT 24
Peak memory 196684 kb
Host smart-87057f11-42ca-410c-9c0c-8a4f88e19264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305989577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2305989577
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3673438550
Short name T2
Test name
Test status
Simulation time 420291401 ps
CPU time 1.1 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:40:28 PM PDT 24
Peak memory 196580 kb
Host smart-82a55783-7be4-4d2b-a088-ff2aee126ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673438550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3673438550
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1984549708
Short name T154
Test name
Test status
Simulation time 599186267 ps
CPU time 1.48 seconds
Started Jul 16 06:40:27 PM PDT 24
Finished Jul 16 06:40:30 PM PDT 24
Peak memory 196724 kb
Host smart-71652f51-3db3-4e2c-be65-4d13c2a3e962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984549708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1984549708
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3393649968
Short name T174
Test name
Test status
Simulation time 498901466 ps
CPU time 1.34 seconds
Started Jul 16 06:40:27 PM PDT 24
Finished Jul 16 06:40:30 PM PDT 24
Peak memory 196636 kb
Host smart-ad4932c1-0bfa-458e-8012-713488128c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393649968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3393649968
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3854136283
Short name T184
Test name
Test status
Simulation time 292618548915 ps
CPU time 212.13 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:43:14 PM PDT 24
Peak memory 192500 kb
Host smart-e9aafe07-6e05-42e2-958e-e07558658ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854136283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3854136283
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1624416621
Short name T167
Test name
Test status
Simulation time 12189684868 ps
CPU time 109.31 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:41:31 PM PDT 24
Peak memory 206696 kb
Host smart-4b3a54bb-5ff3-4374-b2f5-bf486767dd6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624416621 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1624416621
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2631316307
Short name T69
Test name
Test status
Simulation time 392084534 ps
CPU time 0.77 seconds
Started Jul 16 06:40:39 PM PDT 24
Finished Jul 16 06:40:41 PM PDT 24
Peak memory 193172 kb
Host smart-0e828083-b358-438f-9002-34274ba63c24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631316307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2631316307
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3072515452
Short name T333
Test name
Test status
Simulation time 7150068526 ps
CPU time 7.81 seconds
Started Jul 16 06:40:39 PM PDT 24
Finished Jul 16 06:40:48 PM PDT 24
Peak memory 192268 kb
Host smart-0c398791-9590-4a5d-ad75-7f9dba3249d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072515452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3072515452
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3023140430
Short name T351
Test name
Test status
Simulation time 1187785048 ps
CPU time 1.18 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:37 PM PDT 24
Peak memory 193436 kb
Host smart-4aa06619-08f7-4067-b991-25212e8480ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023140430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3023140430
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2439223660
Short name T398
Test name
Test status
Simulation time 414419087 ps
CPU time 0.81 seconds
Started Jul 16 06:40:39 PM PDT 24
Finished Jul 16 06:40:41 PM PDT 24
Peak memory 195880 kb
Host smart-0f98a165-8874-45e8-83b4-f8d7716a685d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439223660 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2439223660
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1017409959
Short name T346
Test name
Test status
Simulation time 463896862 ps
CPU time 0.9 seconds
Started Jul 16 06:40:39 PM PDT 24
Finished Jul 16 06:40:41 PM PDT 24
Peak memory 192048 kb
Host smart-40d85d1a-0fdb-4d79-b63f-50a01ba1d359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017409959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1017409959
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3802975829
Short name T289
Test name
Test status
Simulation time 520532582 ps
CPU time 0.69 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:37 PM PDT 24
Peak memory 192988 kb
Host smart-bb01c3aa-1eb8-4bc4-9c0a-18e005c041db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802975829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3802975829
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1330337089
Short name T371
Test name
Test status
Simulation time 511191499 ps
CPU time 1.21 seconds
Started Jul 16 06:40:34 PM PDT 24
Finished Jul 16 06:40:36 PM PDT 24
Peak memory 183676 kb
Host smart-6be5fd09-817d-4780-b8e6-7bd2abe5b90b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330337089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1330337089
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1844482765
Short name T339
Test name
Test status
Simulation time 413267489 ps
CPU time 1.11 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:37 PM PDT 24
Peak memory 183720 kb
Host smart-f813a789-0d05-41b6-9975-c21d155954e4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844482765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1844482765
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1352809090
Short name T402
Test name
Test status
Simulation time 1138381727 ps
CPU time 2.07 seconds
Started Jul 16 06:40:40 PM PDT 24
Finished Jul 16 06:40:43 PM PDT 24
Peak memory 193512 kb
Host smart-ebf19c0f-02ee-49ce-b20b-638305329a38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352809090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1352809090
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4282243848
Short name T301
Test name
Test status
Simulation time 515777701 ps
CPU time 2.19 seconds
Started Jul 16 06:40:34 PM PDT 24
Finished Jul 16 06:40:37 PM PDT 24
Peak memory 198680 kb
Host smart-642317d2-a318-429f-a16f-ac477ca812cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282243848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.4282243848
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.917858994
Short name T190
Test name
Test status
Simulation time 8315316951 ps
CPU time 13.26 seconds
Started Jul 16 06:40:36 PM PDT 24
Finished Jul 16 06:40:50 PM PDT 24
Peak memory 198312 kb
Host smart-1ba1a920-6b31-433b-acba-9f680d151da8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917858994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.917858994
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1085356121
Short name T61
Test name
Test status
Simulation time 425003573 ps
CPU time 1.54 seconds
Started Jul 16 06:40:36 PM PDT 24
Finished Jul 16 06:40:39 PM PDT 24
Peak memory 194724 kb
Host smart-d0697aa6-b498-4ff8-89d1-8864680a0cec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085356121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1085356121
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3052360363
Short name T70
Test name
Test status
Simulation time 6584472024 ps
CPU time 3.26 seconds
Started Jul 16 06:40:41 PM PDT 24
Finished Jul 16 06:40:46 PM PDT 24
Peak memory 192236 kb
Host smart-cf703fc9-a007-46ab-8b7e-9cb63e04e313
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052360363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3052360363
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1633341873
Short name T409
Test name
Test status
Simulation time 783964950 ps
CPU time 0.88 seconds
Started Jul 16 06:40:38 PM PDT 24
Finished Jul 16 06:40:40 PM PDT 24
Peak memory 192152 kb
Host smart-f4b9b33b-1ed7-4004-b4cf-c59da51e2212
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633341873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1633341873
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4209529885
Short name T315
Test name
Test status
Simulation time 486167387 ps
CPU time 1.07 seconds
Started Jul 16 06:40:38 PM PDT 24
Finished Jul 16 06:40:39 PM PDT 24
Peak memory 195152 kb
Host smart-84aac4c6-8da7-444a-92ff-25efadca6224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209529885 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.4209529885
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.931046332
Short name T349
Test name
Test status
Simulation time 403141558 ps
CPU time 0.68 seconds
Started Jul 16 06:40:41 PM PDT 24
Finished Jul 16 06:40:43 PM PDT 24
Peak memory 192996 kb
Host smart-98cc65f9-b2de-4ee0-a3b1-c5cb9f374837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931046332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.931046332
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3405724133
Short name T288
Test name
Test status
Simulation time 298680806 ps
CPU time 0.9 seconds
Started Jul 16 06:40:38 PM PDT 24
Finished Jul 16 06:40:39 PM PDT 24
Peak memory 183772 kb
Host smart-bc6592a8-d6a0-46da-aea0-19f5b9a2d3b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405724133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3405724133
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.223702460
Short name T399
Test name
Test status
Simulation time 295583768 ps
CPU time 0.73 seconds
Started Jul 16 06:40:34 PM PDT 24
Finished Jul 16 06:40:36 PM PDT 24
Peak memory 183612 kb
Host smart-bf5e73fe-120b-45a3-b3f0-d6cce6c002ac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223702460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.223702460
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.325410973
Short name T331
Test name
Test status
Simulation time 304394677 ps
CPU time 0.65 seconds
Started Jul 16 06:40:36 PM PDT 24
Finished Jul 16 06:40:38 PM PDT 24
Peak memory 183744 kb
Host smart-18b737dc-4a12-4257-9f24-eb065d9b9a59
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325410973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.325410973
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1389872360
Short name T321
Test name
Test status
Simulation time 984420104 ps
CPU time 2.39 seconds
Started Jul 16 06:40:39 PM PDT 24
Finished Jul 16 06:40:42 PM PDT 24
Peak memory 198608 kb
Host smart-91696444-c752-4173-bf87-75da207c6022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389872360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1389872360
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1971381533
Short name T303
Test name
Test status
Simulation time 4534217157 ps
CPU time 3.94 seconds
Started Jul 16 06:40:36 PM PDT 24
Finished Jul 16 06:40:41 PM PDT 24
Peak memory 198112 kb
Host smart-115233e0-347e-46bf-aab1-1da1b78902b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971381533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1971381533
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4249803255
Short name T361
Test name
Test status
Simulation time 415070836 ps
CPU time 0.77 seconds
Started Jul 16 06:41:06 PM PDT 24
Finished Jul 16 06:41:08 PM PDT 24
Peak memory 195424 kb
Host smart-a75bc807-558f-4f4b-8e21-010765e47699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249803255 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4249803255
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.148063789
Short name T385
Test name
Test status
Simulation time 517711712 ps
CPU time 1.22 seconds
Started Jul 16 06:41:06 PM PDT 24
Finished Jul 16 06:41:08 PM PDT 24
Peak memory 193412 kb
Host smart-6ffea3bb-15d7-48b0-b8f0-526f7672356c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148063789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.148063789
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4084005306
Short name T328
Test name
Test status
Simulation time 485715280 ps
CPU time 1.25 seconds
Started Jul 16 06:41:06 PM PDT 24
Finished Jul 16 06:41:08 PM PDT 24
Peak memory 192936 kb
Host smart-fd03d41f-d154-418d-b0c2-92610c7fec47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084005306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4084005306
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4294741753
Short name T418
Test name
Test status
Simulation time 1135134820 ps
CPU time 3.39 seconds
Started Jul 16 06:41:03 PM PDT 24
Finished Jul 16 06:41:08 PM PDT 24
Peak memory 194028 kb
Host smart-12b4a967-878c-45c6-b728-e076dcc792e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294741753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.4294741753
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1664738355
Short name T376
Test name
Test status
Simulation time 370853380 ps
CPU time 1.57 seconds
Started Jul 16 06:40:55 PM PDT 24
Finished Jul 16 06:40:56 PM PDT 24
Peak memory 198584 kb
Host smart-2d7a2cb8-10ec-4dca-b0d2-e691e10497f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664738355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1664738355
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2760180337
Short name T186
Test name
Test status
Simulation time 8205163781 ps
CPU time 3.75 seconds
Started Jul 16 06:41:03 PM PDT 24
Finished Jul 16 06:41:08 PM PDT 24
Peak memory 198256 kb
Host smart-8f3bf53c-ffec-416c-8418-84aa0d6627df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760180337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2760180337
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3805885853
Short name T383
Test name
Test status
Simulation time 486370222 ps
CPU time 1.13 seconds
Started Jul 16 06:41:00 PM PDT 24
Finished Jul 16 06:41:02 PM PDT 24
Peak memory 196464 kb
Host smart-99ecd651-14a0-444e-8d99-03f2f3669327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805885853 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3805885853
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.844420027
Short name T278
Test name
Test status
Simulation time 486065812 ps
CPU time 1.32 seconds
Started Jul 16 06:41:03 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 193056 kb
Host smart-1fcebade-7837-44aa-abde-dcbfbd6549c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844420027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.844420027
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2170739657
Short name T299
Test name
Test status
Simulation time 300650446 ps
CPU time 0.75 seconds
Started Jul 16 06:41:03 PM PDT 24
Finished Jul 16 06:41:05 PM PDT 24
Peak memory 183688 kb
Host smart-2843c54b-3c3a-4078-a1b0-33fa0fdafadd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170739657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2170739657
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3923825843
Short name T308
Test name
Test status
Simulation time 1419589437 ps
CPU time 3.67 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:07 PM PDT 24
Peak memory 193580 kb
Host smart-021ff316-d2e4-4e53-b710-1533ad9fdd95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923825843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3923825843
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3239871740
Short name T388
Test name
Test status
Simulation time 520723194 ps
CPU time 1.57 seconds
Started Jul 16 06:41:03 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 198800 kb
Host smart-fe128639-86c8-4230-8396-daeeda387370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239871740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3239871740
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3957521651
Short name T377
Test name
Test status
Simulation time 4413475803 ps
CPU time 2.48 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 196736 kb
Host smart-eb4e948f-7dcc-40b1-8177-bffbac25bcd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957521651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3957521651
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.4167175259
Short name T311
Test name
Test status
Simulation time 433914093 ps
CPU time 0.78 seconds
Started Jul 16 06:41:14 PM PDT 24
Finished Jul 16 06:41:16 PM PDT 24
Peak memory 195952 kb
Host smart-cef477f8-98fb-46bf-8016-4a33bcd7a410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167175259 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.4167175259
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1067309060
Short name T78
Test name
Test status
Simulation time 519312181 ps
CPU time 1.31 seconds
Started Jul 16 06:41:06 PM PDT 24
Finished Jul 16 06:41:08 PM PDT 24
Peak memory 193008 kb
Host smart-e97fab30-94e9-4317-9c22-e629fc895ccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067309060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1067309060
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4272883236
Short name T317
Test name
Test status
Simulation time 439181761 ps
CPU time 1.2 seconds
Started Jul 16 06:41:07 PM PDT 24
Finished Jul 16 06:41:09 PM PDT 24
Peak memory 183716 kb
Host smart-3eb8f825-7a1b-491a-9276-95fea3a1f409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272883236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.4272883236
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2165134466
Short name T352
Test name
Test status
Simulation time 1227473291 ps
CPU time 1.44 seconds
Started Jul 16 06:41:07 PM PDT 24
Finished Jul 16 06:41:10 PM PDT 24
Peak memory 192992 kb
Host smart-b64a23b2-2403-4f5f-8aa0-e574f58dc65d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165134466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2165134466
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3214352137
Short name T298
Test name
Test status
Simulation time 589759483 ps
CPU time 1.25 seconds
Started Jul 16 06:41:03 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 198432 kb
Host smart-7c42ed3d-c4fa-484b-aeae-d193cefa9517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214352137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3214352137
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3785435298
Short name T350
Test name
Test status
Simulation time 4618789804 ps
CPU time 6.63 seconds
Started Jul 16 06:41:03 PM PDT 24
Finished Jul 16 06:41:11 PM PDT 24
Peak memory 197856 kb
Host smart-aef8f909-8699-4c93-9b89-2ab356e32818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785435298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3785435298
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3311173975
Short name T281
Test name
Test status
Simulation time 484556022 ps
CPU time 0.91 seconds
Started Jul 16 06:41:12 PM PDT 24
Finished Jul 16 06:41:14 PM PDT 24
Peak memory 195828 kb
Host smart-ffce7120-43e2-434e-ad86-8f2aea6cb49b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311173975 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3311173975
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2427134734
Short name T67
Test name
Test status
Simulation time 630047192 ps
CPU time 0.7 seconds
Started Jul 16 06:41:14 PM PDT 24
Finished Jul 16 06:41:15 PM PDT 24
Peak memory 193348 kb
Host smart-44d05e2a-9788-4385-979c-153136385df1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427134734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2427134734
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1422492617
Short name T354
Test name
Test status
Simulation time 323259723 ps
CPU time 0.99 seconds
Started Jul 16 06:41:11 PM PDT 24
Finished Jul 16 06:41:13 PM PDT 24
Peak memory 183912 kb
Host smart-68b773b0-8536-4df9-a482-39e1fdf813c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422492617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1422492617
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1429742298
Short name T76
Test name
Test status
Simulation time 2454762255 ps
CPU time 3.58 seconds
Started Jul 16 06:41:13 PM PDT 24
Finished Jul 16 06:41:17 PM PDT 24
Peak memory 193920 kb
Host smart-4becdbae-71a0-4284-a933-20e139e17556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429742298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1429742298
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.241629778
Short name T411
Test name
Test status
Simulation time 410540677 ps
CPU time 1.45 seconds
Started Jul 16 06:41:12 PM PDT 24
Finished Jul 16 06:41:14 PM PDT 24
Peak memory 198652 kb
Host smart-d5845ae4-da9c-4b16-88e9-db4da709a963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241629778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.241629778
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3369070863
Short name T355
Test name
Test status
Simulation time 4993594641 ps
CPU time 1.56 seconds
Started Jul 16 06:41:13 PM PDT 24
Finished Jul 16 06:41:15 PM PDT 24
Peak memory 197508 kb
Host smart-b998a32f-d43c-4afa-a092-84f66442031e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369070863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3369070863
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.190075886
Short name T359
Test name
Test status
Simulation time 364806080 ps
CPU time 1.26 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:17 PM PDT 24
Peak memory 196416 kb
Host smart-d2d85437-6c23-4011-a05a-68dc2fe0714c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190075886 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.190075886
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1728918055
Short name T386
Test name
Test status
Simulation time 425853872 ps
CPU time 1.19 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:17 PM PDT 24
Peak memory 192108 kb
Host smart-44786eb9-862a-4a7f-b37b-47a01f108f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728918055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1728918055
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2421170416
Short name T307
Test name
Test status
Simulation time 513045988 ps
CPU time 0.6 seconds
Started Jul 16 06:41:13 PM PDT 24
Finished Jul 16 06:41:15 PM PDT 24
Peak memory 192920 kb
Host smart-8b3f5ebd-7350-4791-9eb5-2883afac01bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421170416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2421170416
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1756483751
Short name T341
Test name
Test status
Simulation time 1223814513 ps
CPU time 2.2 seconds
Started Jul 16 06:41:11 PM PDT 24
Finished Jul 16 06:41:14 PM PDT 24
Peak memory 194044 kb
Host smart-6809e9d6-53d5-451d-a33f-65683ee57ee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756483751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1756483751
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.672504728
Short name T277
Test name
Test status
Simulation time 551753287 ps
CPU time 3.05 seconds
Started Jul 16 06:41:13 PM PDT 24
Finished Jul 16 06:41:17 PM PDT 24
Peak memory 198640 kb
Host smart-c60f32e7-ced1-4a5b-9f8f-b7eee5b3f457
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672504728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.672504728
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3551200746
Short name T342
Test name
Test status
Simulation time 491223111 ps
CPU time 1.08 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:18 PM PDT 24
Peak memory 195888 kb
Host smart-ffbd6a28-eb22-4810-9e2d-389ccebd0824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551200746 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3551200746
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1743525052
Short name T334
Test name
Test status
Simulation time 314665355 ps
CPU time 0.73 seconds
Started Jul 16 06:41:14 PM PDT 24
Finished Jul 16 06:41:15 PM PDT 24
Peak memory 193012 kb
Host smart-cdeadeee-5b98-4cf4-9e6b-5e1f91c30311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743525052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1743525052
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4000781114
Short name T283
Test name
Test status
Simulation time 452336973 ps
CPU time 0.55 seconds
Started Jul 16 06:41:13 PM PDT 24
Finished Jul 16 06:41:14 PM PDT 24
Peak memory 183700 kb
Host smart-de09729a-23f3-4119-b0f2-54d32ef1ae7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000781114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.4000781114
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.589259063
Short name T313
Test name
Test status
Simulation time 1369836940 ps
CPU time 1.15 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:18 PM PDT 24
Peak memory 193384 kb
Host smart-eb0a1493-dec8-466e-afed-2d1fd362fcf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589259063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.589259063
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2131276287
Short name T374
Test name
Test status
Simulation time 345043092 ps
CPU time 2 seconds
Started Jul 16 06:41:14 PM PDT 24
Finished Jul 16 06:41:17 PM PDT 24
Peak memory 198636 kb
Host smart-606fe1ee-dcc5-4936-90c9-c1618a1d8dd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131276287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2131276287
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1770509158
Short name T287
Test name
Test status
Simulation time 4760535179 ps
CPU time 2.58 seconds
Started Jul 16 06:41:12 PM PDT 24
Finished Jul 16 06:41:15 PM PDT 24
Peak memory 196496 kb
Host smart-404c2b64-3f7c-4d60-93ab-b82c57e1c1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770509158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1770509158
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2409104180
Short name T356
Test name
Test status
Simulation time 431286111 ps
CPU time 0.98 seconds
Started Jul 16 06:41:14 PM PDT 24
Finished Jul 16 06:41:15 PM PDT 24
Peak memory 195816 kb
Host smart-f2948971-cfb1-4d9c-975e-26607c87c2d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409104180 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2409104180
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.687187574
Short name T64
Test name
Test status
Simulation time 480068842 ps
CPU time 0.72 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:17 PM PDT 24
Peak memory 192892 kb
Host smart-3ce06a54-83bb-4f55-b7d4-0f96c99b58c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687187574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.687187574
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.795564314
Short name T394
Test name
Test status
Simulation time 489132960 ps
CPU time 1.2 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:18 PM PDT 24
Peak memory 183820 kb
Host smart-8c6fb3ef-25d6-482c-9438-5d03d9c16351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795564314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.795564314
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4121949210
Short name T37
Test name
Test status
Simulation time 2108706297 ps
CPU time 0.95 seconds
Started Jul 16 06:41:14 PM PDT 24
Finished Jul 16 06:41:17 PM PDT 24
Peak memory 195136 kb
Host smart-fe54f964-ae47-49d4-973c-fcba74a90f69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121949210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.4121949210
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2836794366
Short name T300
Test name
Test status
Simulation time 465430134 ps
CPU time 1.67 seconds
Started Jul 16 06:41:13 PM PDT 24
Finished Jul 16 06:41:16 PM PDT 24
Peak memory 198572 kb
Host smart-8f2aa7b4-e96c-425d-8c56-72a7399ec6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836794366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2836794366
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.180680749
Short name T337
Test name
Test status
Simulation time 8895514285 ps
CPU time 4.67 seconds
Started Jul 16 06:41:16 PM PDT 24
Finished Jul 16 06:41:23 PM PDT 24
Peak memory 198288 kb
Host smart-e87a30de-c446-40e7-8495-702e07d57410
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180680749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.180680749
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.729897493
Short name T384
Test name
Test status
Simulation time 597498640 ps
CPU time 1.56 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:19 PM PDT 24
Peak memory 195764 kb
Host smart-c356c6b5-1523-4960-8789-9d516f3d4932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729897493 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.729897493
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.612066196
Short name T73
Test name
Test status
Simulation time 381115784 ps
CPU time 0.83 seconds
Started Jul 16 06:41:16 PM PDT 24
Finished Jul 16 06:41:18 PM PDT 24
Peak memory 192960 kb
Host smart-c3ba29d6-8875-421e-8c51-2119139baf48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612066196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.612066196
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3264208376
Short name T293
Test name
Test status
Simulation time 334502247 ps
CPU time 0.96 seconds
Started Jul 16 06:41:16 PM PDT 24
Finished Jul 16 06:41:19 PM PDT 24
Peak memory 192988 kb
Host smart-1a7a22e1-cdb0-4927-a24f-707f071f4738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264208376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3264208376
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3387850586
Short name T404
Test name
Test status
Simulation time 1476195738 ps
CPU time 1.13 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:19 PM PDT 24
Peak memory 193236 kb
Host smart-7368d172-5963-42a3-9766-fac481a26f01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387850586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3387850586
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2038045273
Short name T294
Test name
Test status
Simulation time 476784181 ps
CPU time 2.43 seconds
Started Jul 16 06:41:13 PM PDT 24
Finished Jul 16 06:41:17 PM PDT 24
Peak memory 198648 kb
Host smart-6bb73a15-b773-4442-9cc9-930cde0c1662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038045273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2038045273
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.359117963
Short name T338
Test name
Test status
Simulation time 7978697347 ps
CPU time 4.23 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:20 PM PDT 24
Peak memory 198260 kb
Host smart-4d5b229d-fda0-42f1-9fdc-f31fdf7973fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359117963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.359117963
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.602607470
Short name T420
Test name
Test status
Simulation time 580749664 ps
CPU time 1.49 seconds
Started Jul 16 06:41:29 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 196312 kb
Host smart-99483249-d1c1-42b0-b47c-b45810dd1ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602607470 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.602607470
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2772811619
Short name T389
Test name
Test status
Simulation time 318181076 ps
CPU time 0.65 seconds
Started Jul 16 06:41:27 PM PDT 24
Finished Jul 16 06:41:28 PM PDT 24
Peak memory 192108 kb
Host smart-d8a5a8dd-90c1-4e5c-b434-f90301f36e05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772811619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2772811619
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3903280728
Short name T378
Test name
Test status
Simulation time 513084924 ps
CPU time 0.73 seconds
Started Jul 16 06:41:30 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 183764 kb
Host smart-b4acef3c-6eb1-4a28-b9ee-777062323f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903280728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3903280728
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1337149083
Short name T74
Test name
Test status
Simulation time 1458351157 ps
CPU time 3.32 seconds
Started Jul 16 06:41:26 PM PDT 24
Finished Jul 16 06:41:30 PM PDT 24
Peak memory 192920 kb
Host smart-79b720dd-7706-4823-9d06-e37fd2edda70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337149083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1337149083
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2809359647
Short name T345
Test name
Test status
Simulation time 607398331 ps
CPU time 1.44 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:19 PM PDT 24
Peak memory 198652 kb
Host smart-c9bee6f3-81db-4c58-839d-283f6615df8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809359647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2809359647
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.687510601
Short name T39
Test name
Test status
Simulation time 8761085755 ps
CPU time 3.29 seconds
Started Jul 16 06:41:15 PM PDT 24
Finished Jul 16 06:41:20 PM PDT 24
Peak memory 198388 kb
Host smart-12bf6c32-a133-4144-bd9d-7e4e0ba98ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687510601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.687510601
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.139277635
Short name T332
Test name
Test status
Simulation time 548624697 ps
CPU time 1.38 seconds
Started Jul 16 06:41:27 PM PDT 24
Finished Jul 16 06:41:29 PM PDT 24
Peak memory 197172 kb
Host smart-ecc15792-5aad-4ba8-bd56-9ca7bca4013f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139277635 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.139277635
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1968744450
Short name T65
Test name
Test status
Simulation time 308367238 ps
CPU time 0.77 seconds
Started Jul 16 06:41:27 PM PDT 24
Finished Jul 16 06:41:29 PM PDT 24
Peak memory 192096 kb
Host smart-8779abed-f1b0-4106-b2e0-fd98196c374c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968744450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1968744450
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2713891738
Short name T395
Test name
Test status
Simulation time 583619011 ps
CPU time 0.65 seconds
Started Jul 16 06:41:28 PM PDT 24
Finished Jul 16 06:41:30 PM PDT 24
Peak memory 183820 kb
Host smart-194fe8a8-4eed-4809-ab40-0f8a78a95a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713891738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2713891738
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1003605701
Short name T416
Test name
Test status
Simulation time 1114110195 ps
CPU time 1.38 seconds
Started Jul 16 06:41:28 PM PDT 24
Finished Jul 16 06:41:31 PM PDT 24
Peak memory 193552 kb
Host smart-2b313be0-172e-43dd-9396-b5b72fc90aa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003605701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1003605701
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3066722375
Short name T414
Test name
Test status
Simulation time 389858139 ps
CPU time 2.04 seconds
Started Jul 16 06:41:27 PM PDT 24
Finished Jul 16 06:41:30 PM PDT 24
Peak memory 198632 kb
Host smart-f7354603-71db-4e7d-bc43-bb8cb3174c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066722375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3066722375
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1855894373
Short name T40
Test name
Test status
Simulation time 7681452868 ps
CPU time 3.99 seconds
Started Jul 16 06:41:28 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 198232 kb
Host smart-529274b5-d0ed-4420-9c95-ba5c797bb1ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855894373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1855894373
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.200344017
Short name T60
Test name
Test status
Simulation time 448711448 ps
CPU time 1.21 seconds
Started Jul 16 06:40:46 PM PDT 24
Finished Jul 16 06:40:48 PM PDT 24
Peak memory 193152 kb
Host smart-afbb989e-4adb-4904-b083-4d5c42966850
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200344017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.200344017
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3322802831
Short name T368
Test name
Test status
Simulation time 773625608 ps
CPU time 0.78 seconds
Started Jul 16 06:40:57 PM PDT 24
Finished Jul 16 06:40:58 PM PDT 24
Peak memory 183788 kb
Host smart-0bb81bc1-5edb-4cea-bcf4-624d804fd45a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322802831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3322802831
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2595266617
Short name T390
Test name
Test status
Simulation time 433147080 ps
CPU time 1.27 seconds
Started Jul 16 06:40:49 PM PDT 24
Finished Jul 16 06:40:51 PM PDT 24
Peak memory 197380 kb
Host smart-08d0c8d5-84b8-4c42-a25c-97317bc9baba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595266617 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2595266617
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3407771913
Short name T335
Test name
Test status
Simulation time 323529935 ps
CPU time 0.86 seconds
Started Jul 16 06:40:48 PM PDT 24
Finished Jul 16 06:40:50 PM PDT 24
Peak memory 193448 kb
Host smart-d49fe8af-a691-4835-928c-5f29aa522fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407771913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3407771913
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2913807684
Short name T296
Test name
Test status
Simulation time 507935772 ps
CPU time 0.68 seconds
Started Jul 16 06:40:36 PM PDT 24
Finished Jul 16 06:40:38 PM PDT 24
Peak memory 183776 kb
Host smart-db5c10ae-3ffe-46b7-a705-7baa1eaa2205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913807684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2913807684
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1209792098
Short name T329
Test name
Test status
Simulation time 481800126 ps
CPU time 1.22 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:49 PM PDT 24
Peak memory 183668 kb
Host smart-083d5989-10ae-4936-80cc-fd6c07ab695c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209792098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1209792098
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2546216932
Short name T336
Test name
Test status
Simulation time 341597751 ps
CPU time 0.8 seconds
Started Jul 16 06:40:42 PM PDT 24
Finished Jul 16 06:40:44 PM PDT 24
Peak memory 183708 kb
Host smart-b8c74f6b-137a-46e6-a3c6-be907ddb27ce
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546216932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2546216932
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.473880029
Short name T408
Test name
Test status
Simulation time 2827878046 ps
CPU time 4.19 seconds
Started Jul 16 06:40:46 PM PDT 24
Finished Jul 16 06:40:51 PM PDT 24
Peak memory 193872 kb
Host smart-5cd3cc55-3370-4ed9-9c35-5c49aed13ed8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473880029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.473880029
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2504515244
Short name T292
Test name
Test status
Simulation time 433245175 ps
CPU time 1.85 seconds
Started Jul 16 06:40:36 PM PDT 24
Finished Jul 16 06:40:39 PM PDT 24
Peak memory 198660 kb
Host smart-c3e8bae6-6688-4236-be5c-530f11dfe923
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504515244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2504515244
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.787768318
Short name T276
Test name
Test status
Simulation time 415387908 ps
CPU time 0.68 seconds
Started Jul 16 06:41:28 PM PDT 24
Finished Jul 16 06:41:31 PM PDT 24
Peak memory 183684 kb
Host smart-4546154d-2753-45ac-8ff2-e38a51e93a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787768318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.787768318
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3254619198
Short name T415
Test name
Test status
Simulation time 388538483 ps
CPU time 0.68 seconds
Started Jul 16 06:41:27 PM PDT 24
Finished Jul 16 06:41:29 PM PDT 24
Peak memory 183728 kb
Host smart-2a7a55f3-1b71-46ab-8ef6-f3d8edd143a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254619198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3254619198
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3055183789
Short name T373
Test name
Test status
Simulation time 294204105 ps
CPU time 0.65 seconds
Started Jul 16 06:41:30 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 183764 kb
Host smart-5bc30412-f3f7-4017-b0ca-a147bd84ae91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055183789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3055183789
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2813604021
Short name T406
Test name
Test status
Simulation time 375033058 ps
CPU time 1.05 seconds
Started Jul 16 06:41:29 PM PDT 24
Finished Jul 16 06:41:32 PM PDT 24
Peak memory 183732 kb
Host smart-2911fe32-bf6c-42ba-921b-803165027c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813604021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2813604021
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1874713606
Short name T304
Test name
Test status
Simulation time 362094237 ps
CPU time 0.62 seconds
Started Jul 16 06:41:29 PM PDT 24
Finished Jul 16 06:41:32 PM PDT 24
Peak memory 183616 kb
Host smart-058f88a4-bfb3-41a4-9ef6-6c555964d12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874713606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1874713606
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.16288241
Short name T360
Test name
Test status
Simulation time 493207824 ps
CPU time 0.68 seconds
Started Jul 16 06:41:30 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 183768 kb
Host smart-730bfd1d-f09e-4dbd-87f1-d290eff73ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16288241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.16288241
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2048286122
Short name T285
Test name
Test status
Simulation time 313980885 ps
CPU time 0.6 seconds
Started Jul 16 06:41:30 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 183708 kb
Host smart-0f76e12f-5a57-49b0-9351-e71ed967e591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048286122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2048286122
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2225045857
Short name T405
Test name
Test status
Simulation time 387802053 ps
CPU time 1.17 seconds
Started Jul 16 06:41:28 PM PDT 24
Finished Jul 16 06:41:30 PM PDT 24
Peak memory 183756 kb
Host smart-49f397fb-a8f1-4f9d-86ce-30dbfb1acea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225045857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2225045857
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.296190505
Short name T302
Test name
Test status
Simulation time 493677058 ps
CPU time 0.85 seconds
Started Jul 16 06:41:30 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 183716 kb
Host smart-293e65ae-1b59-44bc-b487-3a82c96cbaf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296190505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.296190505
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3071329561
Short name T410
Test name
Test status
Simulation time 400543014 ps
CPU time 0.63 seconds
Started Jul 16 06:41:31 PM PDT 24
Finished Jul 16 06:41:34 PM PDT 24
Peak memory 183768 kb
Host smart-5683fae3-b56f-45f7-9d4d-bd02d3ed14f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071329561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3071329561
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.343591773
Short name T364
Test name
Test status
Simulation time 555560131 ps
CPU time 1.03 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:49 PM PDT 24
Peak memory 193900 kb
Host smart-782c9273-b03a-4aea-b970-4b84fd9566fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343591773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.343591773
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1472674155
Short name T403
Test name
Test status
Simulation time 7266601522 ps
CPU time 2.83 seconds
Started Jul 16 06:40:48 PM PDT 24
Finished Jul 16 06:40:52 PM PDT 24
Peak memory 192260 kb
Host smart-3fa28cca-e0e8-44c0-9da7-541d56caafdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472674155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1472674155
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2198361379
Short name T387
Test name
Test status
Simulation time 1356070076 ps
CPU time 1.04 seconds
Started Jul 16 06:40:49 PM PDT 24
Finished Jul 16 06:40:51 PM PDT 24
Peak memory 194036 kb
Host smart-0a21be15-4d96-41a8-bd99-79ef909e2174
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198361379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2198361379
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3151382486
Short name T282
Test name
Test status
Simulation time 466959198 ps
CPU time 0.76 seconds
Started Jul 16 06:40:57 PM PDT 24
Finished Jul 16 06:40:58 PM PDT 24
Peak memory 196408 kb
Host smart-9058c800-c008-401d-8582-31cf2d81b77f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151382486 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3151382486
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1603388810
Short name T310
Test name
Test status
Simulation time 496131845 ps
CPU time 0.66 seconds
Started Jul 16 06:40:45 PM PDT 24
Finished Jul 16 06:40:47 PM PDT 24
Peak memory 193460 kb
Host smart-5bbe1089-bc22-488f-945f-c3e6f58e2223
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603388810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1603388810
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3060489642
Short name T324
Test name
Test status
Simulation time 339599798 ps
CPU time 0.96 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:49 PM PDT 24
Peak memory 183772 kb
Host smart-ac04e56d-cb6d-455f-82a7-1a32c45e23f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060489642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3060489642
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.4020082823
Short name T297
Test name
Test status
Simulation time 335222354 ps
CPU time 1.11 seconds
Started Jul 16 06:40:48 PM PDT 24
Finished Jul 16 06:40:50 PM PDT 24
Peak memory 183688 kb
Host smart-d0c09ebc-d171-4ccf-9785-d3543f8a2a1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020082823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.4020082823
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.558984124
Short name T291
Test name
Test status
Simulation time 411966115 ps
CPU time 1.16 seconds
Started Jul 16 06:40:46 PM PDT 24
Finished Jul 16 06:40:48 PM PDT 24
Peak memory 183720 kb
Host smart-18dd6e73-4cb2-4829-9b8a-cfa8d5e10c5b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558984124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.558984124
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2201866590
Short name T72
Test name
Test status
Simulation time 2099956890 ps
CPU time 1.16 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:50 PM PDT 24
Peak memory 193980 kb
Host smart-2cac6fbe-8d96-4acc-9e4c-505ab05ec0cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201866590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2201866590
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4055475062
Short name T330
Test name
Test status
Simulation time 516670116 ps
CPU time 2.52 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:51 PM PDT 24
Peak memory 198668 kb
Host smart-9da75059-219f-487f-9fab-bc82f95257bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055475062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4055475062
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.723610581
Short name T188
Test name
Test status
Simulation time 4046829471 ps
CPU time 3.98 seconds
Started Jul 16 06:40:57 PM PDT 24
Finished Jul 16 06:41:02 PM PDT 24
Peak memory 198028 kb
Host smart-6cdfebb0-bc4c-4103-81b9-410b4d04a8ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723610581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.723610581
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3703783251
Short name T319
Test name
Test status
Simulation time 441626529 ps
CPU time 0.87 seconds
Started Jul 16 06:41:28 PM PDT 24
Finished Jul 16 06:41:30 PM PDT 24
Peak memory 183660 kb
Host smart-b6826cb4-4112-4a74-8dec-a81a2d894b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703783251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3703783251
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3159805057
Short name T372
Test name
Test status
Simulation time 282878328 ps
CPU time 0.68 seconds
Started Jul 16 06:41:30 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 192976 kb
Host smart-90cf8460-b1f6-4689-8cae-ef78bc38c2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159805057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3159805057
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3948723670
Short name T382
Test name
Test status
Simulation time 453501604 ps
CPU time 0.61 seconds
Started Jul 16 06:41:29 PM PDT 24
Finished Jul 16 06:41:32 PM PDT 24
Peak memory 183792 kb
Host smart-223541a3-0592-496c-9ae6-e6f52eeca230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948723670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3948723670
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.771332249
Short name T393
Test name
Test status
Simulation time 317242248 ps
CPU time 0.93 seconds
Started Jul 16 06:41:29 PM PDT 24
Finished Jul 16 06:41:32 PM PDT 24
Peak memory 183708 kb
Host smart-4e0a4158-b75a-4dc4-826f-bf026f8fc76f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771332249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.771332249
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2455426173
Short name T295
Test name
Test status
Simulation time 387578273 ps
CPU time 1.05 seconds
Started Jul 16 06:41:30 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 183792 kb
Host smart-e636c146-462d-488a-b5c4-6430e7e4b8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455426173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2455426173
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2202560665
Short name T320
Test name
Test status
Simulation time 289229385 ps
CPU time 0.68 seconds
Started Jul 16 06:41:30 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 192952 kb
Host smart-210e9e57-1f4d-4bef-a1d2-8ffeeb59f88b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202560665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2202560665
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3818277658
Short name T323
Test name
Test status
Simulation time 389273260 ps
CPU time 0.8 seconds
Started Jul 16 06:41:29 PM PDT 24
Finished Jul 16 06:41:32 PM PDT 24
Peak memory 192928 kb
Host smart-513a3524-6757-41d3-8551-0622b56513bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818277658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3818277658
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1024899983
Short name T381
Test name
Test status
Simulation time 437196123 ps
CPU time 1.18 seconds
Started Jul 16 06:41:31 PM PDT 24
Finished Jul 16 06:41:34 PM PDT 24
Peak memory 183756 kb
Host smart-b6ef8929-600b-49cd-8e0f-270412489c96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024899983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1024899983
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3995741231
Short name T290
Test name
Test status
Simulation time 511966737 ps
CPU time 0.62 seconds
Started Jul 16 06:41:32 PM PDT 24
Finished Jul 16 06:41:34 PM PDT 24
Peak memory 193000 kb
Host smart-80af7887-a501-464a-976a-19ef9bf89d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995741231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3995741231
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3625370629
Short name T417
Test name
Test status
Simulation time 503804518 ps
CPU time 0.66 seconds
Started Jul 16 06:41:32 PM PDT 24
Finished Jul 16 06:41:34 PM PDT 24
Peak memory 192948 kb
Host smart-6fbf1902-b455-424f-bc32-ee132d19d7c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625370629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3625370629
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2841057567
Short name T375
Test name
Test status
Simulation time 525383106 ps
CPU time 1.47 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:51 PM PDT 24
Peak memory 183784 kb
Host smart-ecad9eb1-00c6-4aca-b70e-727facb88aee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841057567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2841057567
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.22434135
Short name T66
Test name
Test status
Simulation time 7503565474 ps
CPU time 2.98 seconds
Started Jul 16 06:40:57 PM PDT 24
Finished Jul 16 06:41:00 PM PDT 24
Peak memory 192216 kb
Host smart-27678667-774e-4261-be99-43936c9a974a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22434135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit
_bash.22434135
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.786472288
Short name T286
Test name
Test status
Simulation time 1048955007 ps
CPU time 0.81 seconds
Started Jul 16 06:40:48 PM PDT 24
Finished Jul 16 06:40:50 PM PDT 24
Peak memory 183656 kb
Host smart-0130227c-f955-4422-b697-651972d7e8b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786472288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.786472288
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.37159698
Short name T41
Test name
Test status
Simulation time 500149287 ps
CPU time 0.78 seconds
Started Jul 16 06:40:57 PM PDT 24
Finished Jul 16 06:40:58 PM PDT 24
Peak memory 196372 kb
Host smart-c4c74b15-0144-4841-9c27-270274771ef7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37159698 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.37159698
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2063079444
Short name T322
Test name
Test status
Simulation time 478575786 ps
CPU time 1.32 seconds
Started Jul 16 06:40:45 PM PDT 24
Finished Jul 16 06:40:47 PM PDT 24
Peak memory 193216 kb
Host smart-713322df-817e-4fab-9655-63dd9d1e2619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063079444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2063079444
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1571628937
Short name T280
Test name
Test status
Simulation time 476229012 ps
CPU time 1.26 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:49 PM PDT 24
Peak memory 183796 kb
Host smart-17b69352-006e-4b02-81a5-c3d3aed91931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571628937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1571628937
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2510317879
Short name T357
Test name
Test status
Simulation time 400634550 ps
CPU time 1.15 seconds
Started Jul 16 06:40:46 PM PDT 24
Finished Jul 16 06:40:48 PM PDT 24
Peak memory 183624 kb
Host smart-f5051cc5-5b74-4c20-868d-81a0ec13c697
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510317879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2510317879
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2168265038
Short name T312
Test name
Test status
Simulation time 439298915 ps
CPU time 0.72 seconds
Started Jul 16 06:40:57 PM PDT 24
Finished Jul 16 06:40:58 PM PDT 24
Peak memory 183012 kb
Host smart-2cae9c75-b8b6-467b-a693-7518e1c830fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168265038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2168265038
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2158153455
Short name T365
Test name
Test status
Simulation time 2507077252 ps
CPU time 2.6 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:51 PM PDT 24
Peak memory 195224 kb
Host smart-70cf9e8f-8ad8-43ee-bbb1-dc97d9d51248
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158153455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2158153455
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4195015895
Short name T353
Test name
Test status
Simulation time 657329477 ps
CPU time 2.47 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:51 PM PDT 24
Peak memory 198668 kb
Host smart-e89bdbb1-d754-4bfe-9ba6-89c679d2c3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195015895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4195015895
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2830726497
Short name T305
Test name
Test status
Simulation time 4425711707 ps
CPU time 2.21 seconds
Started Jul 16 06:40:46 PM PDT 24
Finished Jul 16 06:40:49 PM PDT 24
Peak memory 196848 kb
Host smart-cc71d603-cd21-4cbf-8e0c-fd2bb916aa55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830726497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2830726497
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2803356780
Short name T412
Test name
Test status
Simulation time 378895206 ps
CPU time 0.67 seconds
Started Jul 16 06:41:38 PM PDT 24
Finished Jul 16 06:41:39 PM PDT 24
Peak memory 192952 kb
Host smart-829ac36f-15cf-4588-8c57-8c7398f00894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803356780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2803356780
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3137383662
Short name T370
Test name
Test status
Simulation time 312922546 ps
CPU time 0.63 seconds
Started Jul 16 06:41:32 PM PDT 24
Finished Jul 16 06:41:35 PM PDT 24
Peak memory 183752 kb
Host smart-1212cab3-c264-4d5e-aa7d-6ba9b879b9fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137383662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3137383662
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2055498384
Short name T316
Test name
Test status
Simulation time 467363293 ps
CPU time 0.69 seconds
Started Jul 16 06:41:32 PM PDT 24
Finished Jul 16 06:41:35 PM PDT 24
Peak memory 183780 kb
Host smart-6c449bb0-06c7-436d-bbaf-6fd75c1ad177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055498384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2055498384
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2124489811
Short name T419
Test name
Test status
Simulation time 462556710 ps
CPU time 0.8 seconds
Started Jul 16 06:41:32 PM PDT 24
Finished Jul 16 06:41:35 PM PDT 24
Peak memory 192992 kb
Host smart-b947b7e3-f7ce-48c7-9e60-590a1cf0e62f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124489811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2124489811
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1621252995
Short name T325
Test name
Test status
Simulation time 356911736 ps
CPU time 0.66 seconds
Started Jul 16 06:41:32 PM PDT 24
Finished Jul 16 06:41:34 PM PDT 24
Peak memory 183732 kb
Host smart-a33ccc2b-c0fd-43ea-9870-f55ebe798393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621252995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1621252995
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.678107695
Short name T309
Test name
Test status
Simulation time 293467816 ps
CPU time 0.97 seconds
Started Jul 16 06:41:36 PM PDT 24
Finished Jul 16 06:41:37 PM PDT 24
Peak memory 192956 kb
Host smart-a2f8f52d-95f1-417d-868c-4eff5944a43f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678107695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.678107695
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.207473360
Short name T367
Test name
Test status
Simulation time 529102305 ps
CPU time 0.78 seconds
Started Jul 16 06:41:32 PM PDT 24
Finished Jul 16 06:41:35 PM PDT 24
Peak memory 192956 kb
Host smart-f6bcc331-70f9-499f-909c-fba4cb3a3221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207473360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.207473360
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2733148407
Short name T343
Test name
Test status
Simulation time 412581823 ps
CPU time 0.67 seconds
Started Jul 16 06:41:32 PM PDT 24
Finished Jul 16 06:41:35 PM PDT 24
Peak memory 192972 kb
Host smart-7a8e5856-ba83-4cc2-b4ef-91cb8ce5bfc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733148407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2733148407
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.230370449
Short name T379
Test name
Test status
Simulation time 441231997 ps
CPU time 0.56 seconds
Started Jul 16 06:41:32 PM PDT 24
Finished Jul 16 06:41:35 PM PDT 24
Peak memory 183780 kb
Host smart-450f8678-a7bd-4ba2-9801-0f0722977297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230370449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.230370449
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2755676963
Short name T392
Test name
Test status
Simulation time 396228673 ps
CPU time 0.77 seconds
Started Jul 16 06:41:33 PM PDT 24
Finished Jul 16 06:41:35 PM PDT 24
Peak memory 192992 kb
Host smart-339f77d4-a166-4e68-af5b-d2bc4618f204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755676963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2755676963
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1428676963
Short name T391
Test name
Test status
Simulation time 377182199 ps
CPU time 1.15 seconds
Started Jul 16 06:40:59 PM PDT 24
Finished Jul 16 06:41:01 PM PDT 24
Peak memory 196336 kb
Host smart-d56f87f3-b604-480c-b529-f58120d11083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428676963 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1428676963
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1511606820
Short name T71
Test name
Test status
Simulation time 532241349 ps
CPU time 1.05 seconds
Started Jul 16 06:40:48 PM PDT 24
Finished Jul 16 06:40:50 PM PDT 24
Peak memory 193472 kb
Host smart-c2215e4e-e39b-455c-8df3-d3d7c7d97dad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511606820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1511606820
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.620992679
Short name T358
Test name
Test status
Simulation time 502253873 ps
CPU time 1.25 seconds
Started Jul 16 06:40:49 PM PDT 24
Finished Jul 16 06:40:52 PM PDT 24
Peak memory 183768 kb
Host smart-89d8c9d4-7b3c-4b7c-9227-ba380332fb98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620992679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.620992679
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2980611004
Short name T36
Test name
Test status
Simulation time 2929135125 ps
CPU time 4.17 seconds
Started Jul 16 06:41:00 PM PDT 24
Finished Jul 16 06:41:05 PM PDT 24
Peak memory 195036 kb
Host smart-b242152b-dc93-46ce-a91b-beb91b2662e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980611004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2980611004
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1653469826
Short name T326
Test name
Test status
Simulation time 376220449 ps
CPU time 1.75 seconds
Started Jul 16 06:40:47 PM PDT 24
Finished Jul 16 06:40:51 PM PDT 24
Peak memory 198684 kb
Host smart-4d1843e7-2264-4425-b589-a889c9b2bc89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653469826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1653469826
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2108501017
Short name T369
Test name
Test status
Simulation time 4270082408 ps
CPU time 3.84 seconds
Started Jul 16 06:40:48 PM PDT 24
Finished Jul 16 06:40:53 PM PDT 24
Peak memory 197760 kb
Host smart-590fc20b-6c6a-44bd-bef4-a5a0c7aa0879
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108501017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2108501017
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1654192882
Short name T366
Test name
Test status
Simulation time 466744450 ps
CPU time 0.97 seconds
Started Jul 16 06:41:01 PM PDT 24
Finished Jul 16 06:41:03 PM PDT 24
Peak memory 195812 kb
Host smart-479000fd-7892-438c-a4ff-ff9d6dd37521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654192882 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1654192882
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2351835368
Short name T348
Test name
Test status
Simulation time 308735431 ps
CPU time 0.98 seconds
Started Jul 16 06:41:01 PM PDT 24
Finished Jul 16 06:41:03 PM PDT 24
Peak memory 193280 kb
Host smart-0a9c106c-e18a-4da0-b49f-c11b434e66ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351835368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2351835368
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3766415590
Short name T413
Test name
Test status
Simulation time 277712352 ps
CPU time 0.73 seconds
Started Jul 16 06:41:00 PM PDT 24
Finished Jul 16 06:41:02 PM PDT 24
Peak memory 183688 kb
Host smart-61f291b0-8f44-41c3-b5cc-f987ec31be8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766415590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3766415590
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.668195507
Short name T77
Test name
Test status
Simulation time 1355317064 ps
CPU time 0.89 seconds
Started Jul 16 06:41:00 PM PDT 24
Finished Jul 16 06:41:01 PM PDT 24
Peak memory 194132 kb
Host smart-f1f0661a-6ae6-4cdc-8bbc-e40569525bb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668195507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.668195507
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4214523650
Short name T284
Test name
Test status
Simulation time 688399306 ps
CPU time 2.74 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 198624 kb
Host smart-52841c11-9445-4557-9533-34c41b6b6167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214523650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4214523650
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1835529342
Short name T347
Test name
Test status
Simulation time 8072341965 ps
CPU time 4.85 seconds
Started Jul 16 06:41:00 PM PDT 24
Finished Jul 16 06:41:05 PM PDT 24
Peak memory 198160 kb
Host smart-1fe10848-7476-4939-8fe1-0dcdd3e5e34c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835529342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1835529342
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1079034493
Short name T401
Test name
Test status
Simulation time 449600451 ps
CPU time 1.32 seconds
Started Jul 16 06:41:03 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 196164 kb
Host smart-ecbca67c-6dfc-427d-bbe6-3501e48043a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079034493 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1079034493
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3989341071
Short name T68
Test name
Test status
Simulation time 592985647 ps
CPU time 0.58 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:04 PM PDT 24
Peak memory 192092 kb
Host smart-e3a19c89-9343-4179-8544-e7ae52e1c0ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989341071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3989341071
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1389496739
Short name T362
Test name
Test status
Simulation time 323388055 ps
CPU time 0.71 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:04 PM PDT 24
Peak memory 183752 kb
Host smart-63861e2c-86e9-4d19-8e82-c6f1d23c60cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389496739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1389496739
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.288490646
Short name T344
Test name
Test status
Simulation time 2233997487 ps
CPU time 1.61 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:05 PM PDT 24
Peak memory 194076 kb
Host smart-d5b507ef-fe06-479b-8584-983b92e94c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288490646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.288490646
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2005915638
Short name T407
Test name
Test status
Simulation time 379474292 ps
CPU time 1.73 seconds
Started Jul 16 06:41:00 PM PDT 24
Finished Jul 16 06:41:02 PM PDT 24
Peak memory 198632 kb
Host smart-d928d838-2490-4f10-8c82-35eddbedf408
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005915638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2005915638
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1283683550
Short name T397
Test name
Test status
Simulation time 4686023847 ps
CPU time 2.36 seconds
Started Jul 16 06:40:59 PM PDT 24
Finished Jul 16 06:41:02 PM PDT 24
Peak memory 197948 kb
Host smart-28fb5906-1300-4162-8740-00273d076ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283683550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1283683550
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.310443759
Short name T400
Test name
Test status
Simulation time 365228314 ps
CPU time 1.08 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:04 PM PDT 24
Peak memory 196556 kb
Host smart-9797e88d-6ba3-4e3b-b575-0f0f50103287
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310443759 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.310443759
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.221048230
Short name T327
Test name
Test status
Simulation time 485390203 ps
CPU time 1.33 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:04 PM PDT 24
Peak memory 193212 kb
Host smart-3c8dbc0d-9932-42c8-b7df-b69a2be48a23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221048230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.221048230
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2437866955
Short name T396
Test name
Test status
Simulation time 498017971 ps
CPU time 0.84 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:04 PM PDT 24
Peak memory 192972 kb
Host smart-ef2b0631-c15d-4d80-afff-8131cac6397b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437866955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2437866955
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2173462126
Short name T380
Test name
Test status
Simulation time 1599688151 ps
CPU time 1.65 seconds
Started Jul 16 06:41:04 PM PDT 24
Finished Jul 16 06:41:07 PM PDT 24
Peak memory 194076 kb
Host smart-9ca67966-3f58-4018-a8ee-587d8c7dc699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173462126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2173462126
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1539129525
Short name T314
Test name
Test status
Simulation time 510030946 ps
CPU time 2 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 198604 kb
Host smart-423bcb9e-9e37-40b4-b8f7-19c28ce81737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539129525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1539129525
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3591708920
Short name T279
Test name
Test status
Simulation time 4767257223 ps
CPU time 8.24 seconds
Started Jul 16 06:41:01 PM PDT 24
Finished Jul 16 06:41:11 PM PDT 24
Peak memory 197968 kb
Host smart-5223d44f-a3af-4b54-bba8-e3b98388cfc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591708920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3591708920
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.4087543582
Short name T189
Test name
Test status
Simulation time 502840335 ps
CPU time 1.13 seconds
Started Jul 16 06:41:04 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 195348 kb
Host smart-ea3c13df-2401-430f-972d-5ac27f16eeb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087543582 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.4087543582
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.225679142
Short name T63
Test name
Test status
Simulation time 575269765 ps
CPU time 0.71 seconds
Started Jul 16 06:41:04 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 193292 kb
Host smart-1ab403c0-dae2-4da7-8b98-372be4e4ed70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225679142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.225679142
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2734422861
Short name T340
Test name
Test status
Simulation time 471156843 ps
CPU time 0.69 seconds
Started Jul 16 06:41:01 PM PDT 24
Finished Jul 16 06:41:03 PM PDT 24
Peak memory 192988 kb
Host smart-c1f7d85a-24fd-4ab7-b027-fd083d59a8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734422861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2734422861
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2706289733
Short name T306
Test name
Test status
Simulation time 2175957967 ps
CPU time 3.45 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:07 PM PDT 24
Peak memory 191968 kb
Host smart-bc09b492-78fd-4b75-9b0e-52578fd61a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706289733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2706289733
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3182719384
Short name T363
Test name
Test status
Simulation time 450100956 ps
CPU time 1.91 seconds
Started Jul 16 06:41:02 PM PDT 24
Finished Jul 16 06:41:06 PM PDT 24
Peak memory 198684 kb
Host smart-4a636c53-a4d5-4de2-8b20-8e79993b5451
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182719384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3182719384
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2288924156
Short name T318
Test name
Test status
Simulation time 4705966793 ps
CPU time 3.96 seconds
Started Jul 16 06:41:03 PM PDT 24
Finished Jul 16 06:41:09 PM PDT 24
Peak memory 197664 kb
Host smart-2c968a4e-9716-4c4e-98b2-bf87bc9e7ec9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288924156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2288924156
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.637678642
Short name T271
Test name
Test status
Simulation time 7620794060 ps
CPU time 10.81 seconds
Started Jul 16 06:39:32 PM PDT 24
Finished Jul 16 06:39:43 PM PDT 24
Peak memory 191984 kb
Host smart-263e47e2-12c7-4b4c-9d5b-a35362f25241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637678642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.637678642
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3649098286
Short name T274
Test name
Test status
Simulation time 593223543 ps
CPU time 1.09 seconds
Started Jul 16 06:39:38 PM PDT 24
Finished Jul 16 06:39:40 PM PDT 24
Peak memory 196688 kb
Host smart-d450cabe-faac-49d4-86fc-c492ebbafe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649098286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3649098286
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.163830927
Short name T179
Test name
Test status
Simulation time 564862151 ps
CPU time 0.81 seconds
Started Jul 16 06:39:37 PM PDT 24
Finished Jul 16 06:39:38 PM PDT 24
Peak memory 196688 kb
Host smart-3d38ace9-a622-45ab-b671-fbb60bc11b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163830927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.163830927
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2528928795
Short name T210
Test name
Test status
Simulation time 30849705062 ps
CPU time 42.24 seconds
Started Jul 16 06:39:31 PM PDT 24
Finished Jul 16 06:40:14 PM PDT 24
Peak memory 196984 kb
Host smart-6a8fca15-e462-4b0c-9ffd-b4982db0fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528928795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2528928795
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2178435618
Short name T19
Test name
Test status
Simulation time 8580904833 ps
CPU time 3.12 seconds
Started Jul 16 06:39:29 PM PDT 24
Finished Jul 16 06:39:32 PM PDT 24
Peak memory 215816 kb
Host smart-9daa6659-2850-4cf4-b438-6da113c29203
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178435618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2178435618
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2201711821
Short name T273
Test name
Test status
Simulation time 531648378 ps
CPU time 1.38 seconds
Started Jul 16 06:39:38 PM PDT 24
Finished Jul 16 06:39:40 PM PDT 24
Peak memory 191864 kb
Host smart-e341cb3f-e860-4be2-b2cf-686efb315588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201711821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2201711821
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2382448338
Short name T253
Test name
Test status
Simulation time 40914553025 ps
CPU time 13.03 seconds
Started Jul 16 06:39:47 PM PDT 24
Finished Jul 16 06:40:00 PM PDT 24
Peak memory 196928 kb
Host smart-b0150e1d-8122-4e09-9bf9-c8f53570084d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382448338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2382448338
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3656369559
Short name T208
Test name
Test status
Simulation time 562943792 ps
CPU time 0.74 seconds
Started Jul 16 06:39:48 PM PDT 24
Finished Jul 16 06:39:50 PM PDT 24
Peak memory 196560 kb
Host smart-163c1239-2dd6-447d-8291-73b799a461bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656369559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3656369559
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.532669966
Short name T231
Test name
Test status
Simulation time 34882927942 ps
CPU time 52.94 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:40:36 PM PDT 24
Peak memory 192000 kb
Host smart-8c148776-73b7-4a19-87fd-1bf61b83da77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532669966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.532669966
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.702254938
Short name T203
Test name
Test status
Simulation time 425723863 ps
CPU time 0.75 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:39:45 PM PDT 24
Peak memory 196740 kb
Host smart-f517fe42-373e-425c-bcc2-b2eb99b56406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702254938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.702254938
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1786676549
Short name T170
Test name
Test status
Simulation time 607873209 ps
CPU time 1.42 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:39:44 PM PDT 24
Peak memory 196732 kb
Host smart-cbe2dfce-ada5-4cb1-ac64-378db7014b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786676549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1786676549
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1793007126
Short name T24
Test name
Test status
Simulation time 23754041956 ps
CPU time 33.2 seconds
Started Jul 16 06:39:44 PM PDT 24
Finished Jul 16 06:40:18 PM PDT 24
Peak memory 191896 kb
Host smart-bbcea0df-201a-4691-9b3a-d19a18a5c306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793007126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1793007126
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1493601321
Short name T259
Test name
Test status
Simulation time 393195701 ps
CPU time 0.76 seconds
Started Jul 16 06:39:46 PM PDT 24
Finished Jul 16 06:39:47 PM PDT 24
Peak memory 191888 kb
Host smart-52614aa8-0961-4368-8d85-0864567fdbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493601321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1493601321
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2298431996
Short name T252
Test name
Test status
Simulation time 21350629023 ps
CPU time 26.99 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:40:10 PM PDT 24
Peak memory 191992 kb
Host smart-55a6ad3c-75b8-4660-ba8b-7841faab518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298431996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2298431996
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.697805455
Short name T220
Test name
Test status
Simulation time 447648572 ps
CPU time 0.75 seconds
Started Jul 16 06:39:42 PM PDT 24
Finished Jul 16 06:39:45 PM PDT 24
Peak memory 191892 kb
Host smart-831cb95b-48b7-42a2-8143-7c74f18ed649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697805455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.697805455
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2938619831
Short name T218
Test name
Test status
Simulation time 62040445692 ps
CPU time 12.71 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:39:57 PM PDT 24
Peak memory 191900 kb
Host smart-e9795044-805a-46e9-b1cf-5b4806cb15d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938619831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2938619831
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2081619158
Short name T250
Test name
Test status
Simulation time 543362293 ps
CPU time 0.75 seconds
Started Jul 16 06:39:45 PM PDT 24
Finished Jul 16 06:39:47 PM PDT 24
Peak memory 191856 kb
Host smart-4b620507-0099-4bdb-8ab3-a784e418b960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081619158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2081619158
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1826942465
Short name T93
Test name
Test status
Simulation time 49955734702 ps
CPU time 17.11 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:40:01 PM PDT 24
Peak memory 196872 kb
Host smart-50dad610-60b0-4c9f-b7de-c28feff47b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826942465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1826942465
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2164013073
Short name T205
Test name
Test status
Simulation time 482549529 ps
CPU time 0.74 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:39:45 PM PDT 24
Peak memory 191792 kb
Host smart-ac850f43-4c24-4369-ae72-431a16c06a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164013073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2164013073
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2662523102
Short name T207
Test name
Test status
Simulation time 12382028305 ps
CPU time 5.39 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:39:49 PM PDT 24
Peak memory 196964 kb
Host smart-3051b117-d2f1-44c1-9c03-32f7e19b7269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662523102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2662523102
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2384071756
Short name T245
Test name
Test status
Simulation time 602520126 ps
CPU time 0.76 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:39:43 PM PDT 24
Peak memory 191912 kb
Host smart-b1d07fed-e891-41a4-b167-2482dfb01906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384071756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2384071756
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2724599657
Short name T156
Test name
Test status
Simulation time 442655961 ps
CPU time 0.95 seconds
Started Jul 16 06:39:48 PM PDT 24
Finished Jul 16 06:39:50 PM PDT 24
Peak memory 196596 kb
Host smart-64957224-8ea7-4e97-acea-2ea9a6bba95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724599657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2724599657
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1139510633
Short name T200
Test name
Test status
Simulation time 38527393339 ps
CPU time 11.91 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:39:53 PM PDT 24
Peak memory 191852 kb
Host smart-0e272dec-9732-4b80-abae-b9c480b6508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139510633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1139510633
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3122351704
Short name T249
Test name
Test status
Simulation time 412454025 ps
CPU time 0.6 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:39:45 PM PDT 24
Peak memory 196748 kb
Host smart-00b9aed9-c6fe-479b-9db0-d6e960e1a738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122351704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3122351704
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2450303086
Short name T263
Test name
Test status
Simulation time 545071313 ps
CPU time 1.31 seconds
Started Jul 16 06:39:44 PM PDT 24
Finished Jul 16 06:39:47 PM PDT 24
Peak memory 196676 kb
Host smart-5a255216-5530-4ede-bd28-8ece0e9a10db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450303086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2450303086
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.4066219375
Short name T209
Test name
Test status
Simulation time 55791629418 ps
CPU time 73.91 seconds
Started Jul 16 06:39:42 PM PDT 24
Finished Jul 16 06:40:58 PM PDT 24
Peak memory 191980 kb
Host smart-8b3bcaa9-87b8-45fc-aa65-9ccc24755e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066219375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.4066219375
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.538201166
Short name T269
Test name
Test status
Simulation time 595590864 ps
CPU time 0.91 seconds
Started Jul 16 06:39:42 PM PDT 24
Finished Jul 16 06:39:44 PM PDT 24
Peak memory 191920 kb
Host smart-934b98df-b6ee-4887-8a20-bdf8aa335174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538201166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.538201166
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2926467356
Short name T38
Test name
Test status
Simulation time 59511343737 ps
CPU time 13.41 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:40:07 PM PDT 24
Peak memory 196992 kb
Host smart-a41f5d15-9588-4679-8c90-ad12ccb7a9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926467356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2926467356
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3488335191
Short name T149
Test name
Test status
Simulation time 577322837 ps
CPU time 0.92 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:39:55 PM PDT 24
Peak memory 191920 kb
Host smart-a104e9b8-6699-4b3f-9640-ad27a36c4c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488335191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3488335191
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2158316263
Short name T206
Test name
Test status
Simulation time 39997084133 ps
CPU time 57.5 seconds
Started Jul 16 06:39:30 PM PDT 24
Finished Jul 16 06:40:29 PM PDT 24
Peak memory 191972 kb
Host smart-afa75a80-18d5-4f8d-b1a9-50051c12d527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158316263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2158316263
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.383354232
Short name T20
Test name
Test status
Simulation time 9323506706 ps
CPU time 1.95 seconds
Started Jul 16 06:39:39 PM PDT 24
Finished Jul 16 06:39:41 PM PDT 24
Peak memory 215788 kb
Host smart-65efd6a8-34c1-4456-a09c-18ec9afe5827
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383354232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.383354232
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1238298896
Short name T260
Test name
Test status
Simulation time 360102835 ps
CPU time 0.83 seconds
Started Jul 16 06:39:30 PM PDT 24
Finished Jul 16 06:39:31 PM PDT 24
Peak memory 196720 kb
Host smart-c45a58a9-2352-40dd-ae43-7c2b303c6569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238298896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1238298896
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1776088834
Short name T92
Test name
Test status
Simulation time 9785325458 ps
CPU time 4.35 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:39:58 PM PDT 24
Peak memory 191884 kb
Host smart-3cf0fa44-8dc1-42af-bb28-a8b8b8d7073b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776088834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1776088834
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1233979887
Short name T215
Test name
Test status
Simulation time 474511264 ps
CPU time 0.71 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:39:53 PM PDT 24
Peak memory 191940 kb
Host smart-64fb9a93-215d-464f-b511-d71b62f42ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233979887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1233979887
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.138531551
Short name T248
Test name
Test status
Simulation time 25594387110 ps
CPU time 10.15 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:40:03 PM PDT 24
Peak memory 196992 kb
Host smart-243f3266-84ce-4206-a85e-bd381d73dac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138531551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.138531551
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1478630489
Short name T229
Test name
Test status
Simulation time 434156744 ps
CPU time 0.74 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:39:55 PM PDT 24
Peak memory 191904 kb
Host smart-320fe79d-c085-4159-b5a1-4d0e384a924c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478630489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1478630489
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2090793525
Short name T261
Test name
Test status
Simulation time 10354903331 ps
CPU time 16.69 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:40:09 PM PDT 24
Peak memory 192052 kb
Host smart-63b5928a-4d17-4fa3-b1ad-1525c46468b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090793525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2090793525
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1052958426
Short name T255
Test name
Test status
Simulation time 614371225 ps
CPU time 1.37 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:39:55 PM PDT 24
Peak memory 196744 kb
Host smart-27d84f83-ed5a-4138-8c01-dc9288e0ef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052958426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1052958426
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3970149045
Short name T178
Test name
Test status
Simulation time 520844011 ps
CPU time 1.35 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:39:56 PM PDT 24
Peak memory 196816 kb
Host smart-ba9da909-39b6-43d8-a113-e0cfb506f657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970149045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3970149045
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3191950197
Short name T246
Test name
Test status
Simulation time 20208623025 ps
CPU time 9.1 seconds
Started Jul 16 06:40:01 PM PDT 24
Finished Jul 16 06:40:11 PM PDT 24
Peak memory 196924 kb
Host smart-3bc46dcb-bce6-456b-9fe3-824efed680ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191950197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3191950197
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4134641339
Short name T54
Test name
Test status
Simulation time 429541772 ps
CPU time 0.89 seconds
Started Jul 16 06:39:52 PM PDT 24
Finished Jul 16 06:39:55 PM PDT 24
Peak memory 191856 kb
Host smart-aad78259-9bea-43f6-aded-7d1438ed2e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134641339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4134641339
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1978627387
Short name T219
Test name
Test status
Simulation time 72287474446 ps
CPU time 367.09 seconds
Started Jul 16 06:40:03 PM PDT 24
Finished Jul 16 06:46:11 PM PDT 24
Peak memory 206760 kb
Host smart-3e1b65e8-e580-41d2-8703-2af0245055a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978627387 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1978627387
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2889284494
Short name T216
Test name
Test status
Simulation time 8379774371 ps
CPU time 13.53 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:40:08 PM PDT 24
Peak memory 191992 kb
Host smart-113433a4-3b2d-45e3-ae32-65f0abc3f6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889284494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2889284494
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2604044840
Short name T194
Test name
Test status
Simulation time 587229414 ps
CPU time 1.36 seconds
Started Jul 16 06:40:01 PM PDT 24
Finished Jul 16 06:40:03 PM PDT 24
Peak memory 196692 kb
Host smart-9395667b-7586-41cc-b8ef-a5775b841931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604044840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2604044840
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.160479718
Short name T53
Test name
Test status
Simulation time 9461511679 ps
CPU time 1.67 seconds
Started Jul 16 06:40:01 PM PDT 24
Finished Jul 16 06:40:04 PM PDT 24
Peak memory 196932 kb
Host smart-9e9e3c54-6482-4bc0-b989-d70549c8d470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160479718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.160479718
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3358460736
Short name T233
Test name
Test status
Simulation time 391870525 ps
CPU time 0.87 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:39:56 PM PDT 24
Peak memory 191928 kb
Host smart-c5adc97c-66f1-4a32-a28f-713544dfbb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358460736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3358460736
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2052824717
Short name T157
Test name
Test status
Simulation time 571299325 ps
CPU time 1.04 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:09 PM PDT 24
Peak memory 196704 kb
Host smart-8418b3c5-3db1-4fe5-8f0b-6707a301dc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052824717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2052824717
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2191272953
Short name T222
Test name
Test status
Simulation time 3601115098 ps
CPU time 3.97 seconds
Started Jul 16 06:39:56 PM PDT 24
Finished Jul 16 06:40:00 PM PDT 24
Peak memory 191984 kb
Host smart-e8d33b88-bc8c-478f-b487-c9b9f4c59308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191272953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2191272953
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4192096097
Short name T221
Test name
Test status
Simulation time 560541997 ps
CPU time 1.36 seconds
Started Jul 16 06:39:53 PM PDT 24
Finished Jul 16 06:39:56 PM PDT 24
Peak memory 196628 kb
Host smart-5b2fd8f4-e39d-4227-a861-36b61676edd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192096097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4192096097
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2114913095
Short name T266
Test name
Test status
Simulation time 21325135453 ps
CPU time 23.18 seconds
Started Jul 16 06:40:07 PM PDT 24
Finished Jul 16 06:40:32 PM PDT 24
Peak memory 196880 kb
Host smart-c20801d3-5d49-44ad-a305-cc265b4fa3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114913095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2114913095
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2820929314
Short name T262
Test name
Test status
Simulation time 398649357 ps
CPU time 0.77 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:07 PM PDT 24
Peak memory 191912 kb
Host smart-858318cf-7ac0-41af-9eab-aedc365f9b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820929314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2820929314
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.655543543
Short name T192
Test name
Test status
Simulation time 8566829817 ps
CPU time 13.9 seconds
Started Jul 16 06:40:07 PM PDT 24
Finished Jul 16 06:40:23 PM PDT 24
Peak memory 192004 kb
Host smart-e2f69bf8-6d61-4192-b860-6b018857614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655543543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.655543543
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2314060946
Short name T254
Test name
Test status
Simulation time 586852284 ps
CPU time 0.83 seconds
Started Jul 16 06:40:04 PM PDT 24
Finished Jul 16 06:40:05 PM PDT 24
Peak memory 196720 kb
Host smart-b8bec4eb-ffca-42cd-bc1a-57c66f8782cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314060946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2314060946
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.434155934
Short name T98
Test name
Test status
Simulation time 37733870340 ps
CPU time 14.34 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:22 PM PDT 24
Peak memory 191964 kb
Host smart-3f33d143-7752-4638-9309-e732bf43532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434155934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.434155934
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4139611649
Short name T202
Test name
Test status
Simulation time 491029306 ps
CPU time 0.94 seconds
Started Jul 16 06:40:06 PM PDT 24
Finished Jul 16 06:40:09 PM PDT 24
Peak memory 191572 kb
Host smart-48e8cd48-93e4-4fd1-8b4c-312d6a12a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139611649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4139611649
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1704090958
Short name T244
Test name
Test status
Simulation time 33899969733 ps
CPU time 26.5 seconds
Started Jul 16 06:39:38 PM PDT 24
Finished Jul 16 06:40:05 PM PDT 24
Peak memory 191976 kb
Host smart-38df483d-a77f-4d52-8b9f-deb8a9d32cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704090958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1704090958
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1798540856
Short name T18
Test name
Test status
Simulation time 4472959468 ps
CPU time 1.16 seconds
Started Jul 16 06:39:33 PM PDT 24
Finished Jul 16 06:39:35 PM PDT 24
Peak memory 215696 kb
Host smart-46fab101-d144-435a-8503-a680098b5714
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798540856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1798540856
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3218182809
Short name T257
Test name
Test status
Simulation time 494911571 ps
CPU time 1.38 seconds
Started Jul 16 06:39:31 PM PDT 24
Finished Jul 16 06:39:33 PM PDT 24
Peak memory 196752 kb
Host smart-2307e6fc-b78b-41d7-9b0b-47a5f262aaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218182809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3218182809
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.653095268
Short name T211
Test name
Test status
Simulation time 14644715522 ps
CPU time 21.54 seconds
Started Jul 16 06:40:06 PM PDT 24
Finished Jul 16 06:40:30 PM PDT 24
Peak memory 191908 kb
Host smart-e270fee3-a49a-4bd4-85f3-60914de8b056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653095268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.653095268
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1096520598
Short name T9
Test name
Test status
Simulation time 412190357 ps
CPU time 0.9 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:09 PM PDT 24
Peak memory 191904 kb
Host smart-0b642e5b-b87e-4d1a-b656-574af65aadca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096520598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1096520598
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.129962808
Short name T237
Test name
Test status
Simulation time 27086064429 ps
CPU time 11.48 seconds
Started Jul 16 06:40:03 PM PDT 24
Finished Jul 16 06:40:15 PM PDT 24
Peak memory 197012 kb
Host smart-dbe2120f-db5b-40b8-a192-7ee91307f69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129962808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.129962808
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3539465673
Short name T201
Test name
Test status
Simulation time 584515486 ps
CPU time 0.76 seconds
Started Jul 16 06:40:07 PM PDT 24
Finished Jul 16 06:40:10 PM PDT 24
Peak memory 196676 kb
Host smart-bd310d9b-da43-4e45-bdca-f7a8067e39ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539465673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3539465673
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.4006718702
Short name T26
Test name
Test status
Simulation time 30623745606 ps
CPU time 36.64 seconds
Started Jul 16 06:40:06 PM PDT 24
Finished Jul 16 06:40:45 PM PDT 24
Peak memory 191896 kb
Host smart-ade53a88-4987-46fa-869b-cae3c79a67f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006718702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.4006718702
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3159440897
Short name T232
Test name
Test status
Simulation time 685798811 ps
CPU time 0.64 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:08 PM PDT 24
Peak memory 196560 kb
Host smart-85d94b57-03f5-46f6-89f1-701f603f90a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159440897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3159440897
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3773002051
Short name T243
Test name
Test status
Simulation time 38984648379 ps
CPU time 12.82 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:20 PM PDT 24
Peak memory 191968 kb
Host smart-c463e440-8eed-4ca0-8d9a-b67b4b0575e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773002051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3773002051
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.4042013099
Short name T234
Test name
Test status
Simulation time 432578950 ps
CPU time 1.29 seconds
Started Jul 16 06:40:04 PM PDT 24
Finished Jul 16 06:40:07 PM PDT 24
Peak memory 196708 kb
Host smart-1a49bb4a-ecdd-44d5-84d1-1649373e719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042013099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.4042013099
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2718190888
Short name T11
Test name
Test status
Simulation time 4542780196 ps
CPU time 7.7 seconds
Started Jul 16 06:40:06 PM PDT 24
Finished Jul 16 06:40:16 PM PDT 24
Peak memory 191564 kb
Host smart-0ecfb47f-91a8-4d67-b8af-eada3923a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718190888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2718190888
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1225150577
Short name T268
Test name
Test status
Simulation time 397483789 ps
CPU time 1.11 seconds
Started Jul 16 06:40:05 PM PDT 24
Finished Jul 16 06:40:08 PM PDT 24
Peak memory 191932 kb
Host smart-156d4aaf-b310-4e41-a64f-dc5a2b21071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225150577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1225150577
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.290384030
Short name T217
Test name
Test status
Simulation time 39552257467 ps
CPU time 32.05 seconds
Started Jul 16 06:40:04 PM PDT 24
Finished Jul 16 06:40:37 PM PDT 24
Peak memory 191972 kb
Host smart-d3cf222f-4119-44e9-9ac3-c9c80de9717a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290384030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.290384030
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3985518233
Short name T1
Test name
Test status
Simulation time 610737838 ps
CPU time 1 seconds
Started Jul 16 06:40:09 PM PDT 24
Finished Jul 16 06:40:11 PM PDT 24
Peak memory 191920 kb
Host smart-72cbb87b-d74c-4711-a653-b9f18863011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985518233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3985518233
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.426513296
Short name T212
Test name
Test status
Simulation time 30390626617 ps
CPU time 11.03 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:40:38 PM PDT 24
Peak memory 191944 kb
Host smart-a06af854-4cad-48c1-82bf-a14efe7acea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426513296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.426513296
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2942270415
Short name T225
Test name
Test status
Simulation time 403904990 ps
CPU time 0.74 seconds
Started Jul 16 06:40:24 PM PDT 24
Finished Jul 16 06:40:25 PM PDT 24
Peak memory 191840 kb
Host smart-255fa73a-06fb-472b-ae80-5867abcb6987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942270415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2942270415
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2353045601
Short name T160
Test name
Test status
Simulation time 395576228 ps
CPU time 1.11 seconds
Started Jul 16 06:40:30 PM PDT 24
Finished Jul 16 06:40:32 PM PDT 24
Peak memory 196688 kb
Host smart-8ba561c3-9b69-449f-8b0c-3d3b7987cac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353045601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2353045601
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2437095296
Short name T275
Test name
Test status
Simulation time 35930121859 ps
CPU time 44.01 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:41:12 PM PDT 24
Peak memory 191976 kb
Host smart-263f9a07-10a2-4a68-95a3-adbb15b6fdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437095296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2437095296
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3646788238
Short name T227
Test name
Test status
Simulation time 449590998 ps
CPU time 0.72 seconds
Started Jul 16 06:40:25 PM PDT 24
Finished Jul 16 06:40:27 PM PDT 24
Peak memory 196628 kb
Host smart-060ca297-80a6-49ab-9c24-44bf4db4518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646788238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3646788238
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1819458949
Short name T270
Test name
Test status
Simulation time 55139862002 ps
CPU time 39.48 seconds
Started Jul 16 06:40:25 PM PDT 24
Finished Jul 16 06:41:05 PM PDT 24
Peak memory 196928 kb
Host smart-048321be-b5f5-4afe-a97e-4cef079ae35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819458949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1819458949
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1101719412
Short name T238
Test name
Test status
Simulation time 470306481 ps
CPU time 0.67 seconds
Started Jul 16 06:40:24 PM PDT 24
Finished Jul 16 06:40:26 PM PDT 24
Peak memory 196720 kb
Host smart-f54170f9-b879-4a67-b1d5-c512185dc35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101719412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1101719412
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2345815888
Short name T204
Test name
Test status
Simulation time 5460558447 ps
CPU time 2.85 seconds
Started Jul 16 06:40:29 PM PDT 24
Finished Jul 16 06:40:33 PM PDT 24
Peak memory 191988 kb
Host smart-1a3187a4-ebf4-4a79-b16a-2f6d10c47f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345815888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2345815888
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.524116875
Short name T272
Test name
Test status
Simulation time 405338678 ps
CPU time 0.63 seconds
Started Jul 16 06:40:25 PM PDT 24
Finished Jul 16 06:40:26 PM PDT 24
Peak memory 196800 kb
Host smart-a28f6c50-5ae8-43b5-a258-505478b7f50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524116875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.524116875
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4226317341
Short name T213
Test name
Test status
Simulation time 6987516358 ps
CPU time 5.59 seconds
Started Jul 16 06:39:35 PM PDT 24
Finished Jul 16 06:39:42 PM PDT 24
Peak memory 196932 kb
Host smart-e6fb8867-da1c-4b4f-b5eb-d60fd0c27080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226317341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4226317341
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3567322799
Short name T21
Test name
Test status
Simulation time 8399826547 ps
CPU time 3.91 seconds
Started Jul 16 06:39:30 PM PDT 24
Finished Jul 16 06:39:35 PM PDT 24
Peak memory 215680 kb
Host smart-5a2003a1-8a0c-48af-9263-844508566f20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567322799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3567322799
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.466558140
Short name T196
Test name
Test status
Simulation time 485687637 ps
CPU time 0.75 seconds
Started Jul 16 06:39:30 PM PDT 24
Finished Jul 16 06:39:32 PM PDT 24
Peak memory 196696 kb
Host smart-a30f994c-feb7-4ba1-b6ae-61dbad8826ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466558140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.466558140
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.24826152
Short name T15
Test name
Test status
Simulation time 34448260724 ps
CPU time 7.75 seconds
Started Jul 16 06:40:27 PM PDT 24
Finished Jul 16 06:40:37 PM PDT 24
Peak memory 191996 kb
Host smart-45c86248-d62b-47b3-a9f3-643dae71c993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24826152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.24826152
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3726141124
Short name T256
Test name
Test status
Simulation time 367844266 ps
CPU time 0.82 seconds
Started Jul 16 06:40:25 PM PDT 24
Finished Jul 16 06:40:27 PM PDT 24
Peak memory 191768 kb
Host smart-4541d17a-2dfc-4d16-8f86-736182a87bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726141124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3726141124
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.4024389895
Short name T55
Test name
Test status
Simulation time 3119660187 ps
CPU time 4.58 seconds
Started Jul 16 06:40:28 PM PDT 24
Finished Jul 16 06:40:34 PM PDT 24
Peak memory 191992 kb
Host smart-b7923d94-20c7-4f40-933c-6b25c45e1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024389895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.4024389895
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.813838599
Short name T267
Test name
Test status
Simulation time 513953400 ps
CPU time 1.31 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:40:28 PM PDT 24
Peak memory 191864 kb
Host smart-f160d5bd-7d16-4bb1-9f41-11c5b71b3330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813838599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.813838599
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1553507010
Short name T228
Test name
Test status
Simulation time 37560930183 ps
CPU time 3.49 seconds
Started Jul 16 06:40:28 PM PDT 24
Finished Jul 16 06:40:33 PM PDT 24
Peak memory 197000 kb
Host smart-5885d74d-30f5-463b-ae85-91b3f1739b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553507010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1553507010
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2388537945
Short name T199
Test name
Test status
Simulation time 416314240 ps
CPU time 0.71 seconds
Started Jul 16 06:40:25 PM PDT 24
Finished Jul 16 06:40:26 PM PDT 24
Peak memory 191820 kb
Host smart-bae2781b-4cba-4ca4-b154-be43b95bf1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388537945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2388537945
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.4036235247
Short name T230
Test name
Test status
Simulation time 24876141877 ps
CPU time 2.46 seconds
Started Jul 16 06:40:27 PM PDT 24
Finished Jul 16 06:40:30 PM PDT 24
Peak memory 191980 kb
Host smart-da443741-970e-47ea-87da-44e672b67b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036235247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.4036235247
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3364177669
Short name T191
Test name
Test status
Simulation time 392387350 ps
CPU time 0.69 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:40:28 PM PDT 24
Peak memory 191936 kb
Host smart-43a9b280-1d6d-4acd-a187-d2ef2bfa7b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364177669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3364177669
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2765537970
Short name T56
Test name
Test status
Simulation time 40327345129 ps
CPU time 13.91 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:40:42 PM PDT 24
Peak memory 191980 kb
Host smart-c007183f-1f07-4ed1-a6b2-81a9ccb1fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765537970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2765537970
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.50243651
Short name T235
Test name
Test status
Simulation time 544914520 ps
CPU time 1.36 seconds
Started Jul 16 06:40:26 PM PDT 24
Finished Jul 16 06:40:28 PM PDT 24
Peak memory 191772 kb
Host smart-4b9d4ec3-1f03-4b86-85e1-1c32e3835055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50243651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.50243651
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2158047564
Short name T242
Test name
Test status
Simulation time 29267904106 ps
CPU time 40.48 seconds
Started Jul 16 06:40:31 PM PDT 24
Finished Jul 16 06:41:12 PM PDT 24
Peak memory 191968 kb
Host smart-9cf51443-ef45-4837-95d2-e3b9a3a337ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158047564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2158047564
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3672396793
Short name T236
Test name
Test status
Simulation time 515538940 ps
CPU time 1.16 seconds
Started Jul 16 06:40:28 PM PDT 24
Finished Jul 16 06:40:31 PM PDT 24
Peak memory 196760 kb
Host smart-506000fc-2275-4634-a657-3e50f12fa0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672396793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3672396793
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3251628489
Short name T185
Test name
Test status
Simulation time 512535505 ps
CPU time 0.77 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:37 PM PDT 24
Peak memory 196696 kb
Host smart-cf6f095c-65cd-48ab-8b54-7b2cf045aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251628489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3251628489
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1941684170
Short name T239
Test name
Test status
Simulation time 26592022918 ps
CPU time 9.28 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:45 PM PDT 24
Peak memory 191924 kb
Host smart-04a71372-5efc-402e-a1b6-5c0aba7b9b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941684170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1941684170
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.39859292
Short name T195
Test name
Test status
Simulation time 378337005 ps
CPU time 1.14 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:37 PM PDT 24
Peak memory 196616 kb
Host smart-b3450424-9bd0-44b6-b72c-7e01a78eefb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39859292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.39859292
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_jump.4108368762
Short name T183
Test name
Test status
Simulation time 593419621 ps
CPU time 0.94 seconds
Started Jul 16 06:40:40 PM PDT 24
Finished Jul 16 06:40:42 PM PDT 24
Peak memory 196652 kb
Host smart-8160bc23-8134-4adb-a4f8-e71af2202100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108368762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4108368762
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3098514426
Short name T224
Test name
Test status
Simulation time 40163119810 ps
CPU time 11.42 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:48 PM PDT 24
Peak memory 191984 kb
Host smart-f91e1762-355f-49ba-bf70-e2525ce25bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098514426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3098514426
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1428407216
Short name T223
Test name
Test status
Simulation time 391926004 ps
CPU time 0.85 seconds
Started Jul 16 06:40:34 PM PDT 24
Finished Jul 16 06:40:36 PM PDT 24
Peak memory 196676 kb
Host smart-21c10045-2413-4e18-af64-8e5ddd562cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428407216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1428407216
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1755456409
Short name T258
Test name
Test status
Simulation time 5339307124 ps
CPU time 2.39 seconds
Started Jul 16 06:40:37 PM PDT 24
Finished Jul 16 06:40:41 PM PDT 24
Peak memory 196860 kb
Host smart-46960989-729c-49bb-b8fb-721bf01804e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755456409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1755456409
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3620386684
Short name T57
Test name
Test status
Simulation time 491141859 ps
CPU time 0.93 seconds
Started Jul 16 06:40:37 PM PDT 24
Finished Jul 16 06:40:39 PM PDT 24
Peak memory 196588 kb
Host smart-19e46faa-a423-44c2-87a7-fe9ba9b87924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620386684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3620386684
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2561762304
Short name T214
Test name
Test status
Simulation time 28508874515 ps
CPU time 21.25 seconds
Started Jul 16 06:40:35 PM PDT 24
Finished Jul 16 06:40:58 PM PDT 24
Peak memory 191972 kb
Host smart-62800317-ad49-4599-8a4e-efcf38a2721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561762304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2561762304
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.534172665
Short name T197
Test name
Test status
Simulation time 379806759 ps
CPU time 0.82 seconds
Started Jul 16 06:40:42 PM PDT 24
Finished Jul 16 06:40:43 PM PDT 24
Peak memory 191864 kb
Host smart-0c945569-6f0e-49b2-b8ac-f02a806f49fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534172665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.534172665
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.334729938
Short name T264
Test name
Test status
Simulation time 38670684734 ps
CPU time 10.07 seconds
Started Jul 16 06:39:37 PM PDT 24
Finished Jul 16 06:39:48 PM PDT 24
Peak memory 192004 kb
Host smart-bc13f654-d4e4-4f9f-9f56-503f13a08fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334729938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.334729938
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3483566644
Short name T193
Test name
Test status
Simulation time 513243272 ps
CPU time 0.94 seconds
Started Jul 16 06:39:35 PM PDT 24
Finished Jul 16 06:39:37 PM PDT 24
Peak memory 196592 kb
Host smart-12e766d7-45aa-4c88-8566-e0cf8c18d5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483566644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3483566644
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4089824375
Short name T251
Test name
Test status
Simulation time 27856521661 ps
CPU time 14.71 seconds
Started Jul 16 06:39:33 PM PDT 24
Finished Jul 16 06:39:48 PM PDT 24
Peak memory 191960 kb
Host smart-e6f03daf-62e6-492c-8ad5-aa459df07e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089824375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4089824375
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.523939301
Short name T8
Test name
Test status
Simulation time 526839768 ps
CPU time 1.29 seconds
Started Jul 16 06:39:35 PM PDT 24
Finished Jul 16 06:39:37 PM PDT 24
Peak memory 191844 kb
Host smart-cec8be77-491a-4421-9b56-fbf981cea200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523939301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.523939301
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2288359227
Short name T198
Test name
Test status
Simulation time 52993017270 ps
CPU time 69.68 seconds
Started Jul 16 06:39:30 PM PDT 24
Finished Jul 16 06:40:41 PM PDT 24
Peak memory 191988 kb
Host smart-711eb8c8-a36f-487a-b0f5-359c1ead85db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288359227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2288359227
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3620105400
Short name T240
Test name
Test status
Simulation time 494183113 ps
CPU time 0.75 seconds
Started Jul 16 06:39:32 PM PDT 24
Finished Jul 16 06:39:33 PM PDT 24
Peak memory 191960 kb
Host smart-f77faa3f-c297-41b9-be7e-5f9c893e3b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620105400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3620105400
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3021962831
Short name T226
Test name
Test status
Simulation time 31090928065 ps
CPU time 24.61 seconds
Started Jul 16 06:39:43 PM PDT 24
Finished Jul 16 06:40:09 PM PDT 24
Peak memory 191988 kb
Host smart-8cab39f0-351c-42b9-9d29-6a24e6739a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021962831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3021962831
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1618603482
Short name T265
Test name
Test status
Simulation time 510373151 ps
CPU time 1.41 seconds
Started Jul 16 06:39:41 PM PDT 24
Finished Jul 16 06:39:43 PM PDT 24
Peak memory 196772 kb
Host smart-f1c4fee5-f4b2-4db2-a6b7-78df6f0932c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618603482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1618603482
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2280585374
Short name T241
Test name
Test status
Simulation time 48925069981 ps
CPU time 34.45 seconds
Started Jul 16 06:39:42 PM PDT 24
Finished Jul 16 06:40:18 PM PDT 24
Peak memory 191996 kb
Host smart-7cf36f38-b00e-475e-8b32-6f1d37bd2b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280585374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2280585374
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3693217655
Short name T247
Test name
Test status
Simulation time 561747755 ps
CPU time 0.84 seconds
Started Jul 16 06:39:42 PM PDT 24
Finished Jul 16 06:39:44 PM PDT 24
Peak memory 196712 kb
Host smart-11ffd67b-af7c-4319-b616-3ab2d1171aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693217655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3693217655
Directory /workspace/9.aon_timer_smoke/latest
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