Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.27	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	3	170	98.27

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	24714	1		T2	27		T5	12		T6	12
bark[1]	597	1		T3	14		T62	14		T89	21
bark[2]	584	1		T43	52		T116	14		T101	254
bark[3]	654	1		T13	14		T42	83		T107	14
bark[4]	245	1		T28	21		T88	21		T89	21
bark[5]	360	1		T14	14		T22	70		T49	14
bark[6]	270	1		T28	47		T39	7		T115	47
bark[7]	664	1		T28	21		T132	21		T52	238
bark[8]	346	1		T28	21		T88	180		T123	14
bark[9]	581	1		T39	33		T42	235		T68	45
bark[10]	715	1		T132	51		T53	26		T163	14
bark[11]	631	1		T89	214		T113	14		T181	14
bark[12]	423	1		T1	14		T7	14		T87	14
bark[13]	706	1		T24	21		T133	21		T110	21
bark[14]	494	1		T69	14		T168	14		T135	21
bark[15]	519	1		T28	174		T183	55		T84	21
bark[16]	1522	1		T2	865		T43	170		T101	157
bark[17]	1063	1		T46	14		T19	192		T29	92
bark[18]	425	1		T22	21		T124	30		T122	31
bark[19]	360	1		T30	14		T28	227		T124	42
bark[20]	120	1		T89	21		T142	26		T130	52
bark[21]	429	1		T44	14		T42	5		T158	64
bark[22]	164	1		T51	14		T158	35		T135	66
bark[23]	817	1		T42	21		T83	485		T131	42
bark[24]	907	1		T42	294		T158	14		T163	129
bark[25]	425	1		T28	21		T89	26		T124	21
bark[26]	641	1		T15	21		T102	14		T135	61
bark[27]	256	1		T133	100		T84	69		T136	21
bark[28]	175	1		T28	30		T39	21		T42	26
bark[29]	208	1		T24	39		T114	14		T113	43
bark[30]	182	1		T22	35		T112	21		T184	21
bark[31]	642	1		T2	21		T29	21		T88	21
bark_0	4286	1		T1	7		T2	23		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	24652	1		T2	26		T5	11		T6	11
bite[1]	531	1		T13	13		T87	13		T171	30
bite[2]	988	1		T2	864		T28	30		T62	13
bite[3]	641	1		T3	13		T28	21		T150	26
bite[4]	864	1		T22	70		T46	13		T52	237
bite[5]	496	1		T7	13		T22	21		T101	253
bite[6]	332	1		T22	34		T28	21		T42	26
bite[7]	283	1		T183	55		T126	21		T84	26
bite[8]	766	1		T28	173		T39	21		T101	291
bite[9]	523	1		T28	247		T133	21		T127	21
bite[10]	699	1		T1	13		T42	90		T24	30
bite[11]	738	1		T89	21		T83	484		T131	21
bite[12]	350	1		T42	4		T132	21		T89	21
bite[13]	295	1		T29	91		T43	51		T183	42
bite[14]	232	1		T158	34		T135	42		T113	43
bite[15]	309	1		T2	21		T29	21		T163	129
bite[16]	435	1		T24	39		T89	21		T83	30
bite[17]	584	1		T15	21		T28	21		T42	21
bite[18]	484	1		T43	169		T24	21		T69	13
bite[19]	448	1		T42	21		T82	262		T167	13
bite[20]	433	1		T150	21		T135	87		T110	21
bite[21]	422	1		T39	6		T88	21		T104	40
bite[22]	635	1		T88	179		T158	44		T133	99
bite[23]	446	1		T49	13		T158	63		T89	21
bite[24]	439	1		T19	191		T39	32		T89	26
bite[25]	170	1		T84	68		T147	21		T120	13
bite[26]	546	1		T14	13		T42	293		T113	35
bite[27]	526	1		T44	13		T124	21		T104	21
bite[28]	550	1		T132	51		T171	21		T90	21
bite[29]	455	1		T51	13		T158	13		T98	83
bite[30]	846	1		T30	13		T88	21		T68	136
bite[31]	252	1		T101	26		T163	21		T160	13
bite_0	4755	1		T1	8		T2	25		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36962	1		T1	21		T2	936		T3	21
auto[1]	8163	1		T11	7		T22	97		T198	7

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	58	1		T40	58		-	-		-	-
prescale[0]	753	1		T199	9		T28	19		T41	30
prescale[1]	684	1		T15	68		T28	106		T40	71
prescale[2]	1034	1		T15	19		T200	9		T28	40
prescale[3]	698	1		T19	28		T28	223		T39	28
prescale[4]	1014	1		T2	144		T16	9		T28	23
prescale[5]	863	1		T8	9		T201	9		T39	83
prescale[6]	1065	1		T2	116		T19	2		T23	33
prescale[7]	685	1		T15	2		T41	74		T42	19
prescale[8]	961	1		T29	19		T39	49		T40	99
prescale[9]	860	1		T19	2		T23	42		T28	119
prescale[10]	493	1		T15	19		T202	9		T39	19
prescale[11]	792	1		T2	87		T5	9		T19	36
prescale[12]	214	1		T42	2		T24	40		T82	54
prescale[13]	515	1		T2	28		T28	23		T158	2
prescale[14]	779	1		T2	40		T28	19		T41	19
prescale[15]	412	1		T9	9		T29	86		T82	2
prescale[16]	560	1		T2	19		T28	50		T40	26
prescale[17]	781	1		T15	24		T28	82		T41	40
prescale[18]	610	1		T28	97		T29	28		T39	19
prescale[19]	677	1		T2	186		T19	115		T39	19
prescale[20]	843	1		T29	49		T40	40		T88	115
prescale[21]	639	1		T23	19		T29	45		T39	19
prescale[22]	878	1		T22	40		T29	212		T40	38
prescale[23]	422	1		T22	19		T29	2		T40	45
prescale[24]	619	1		T2	36		T6	9		T15	19
prescale[25]	552	1		T28	14		T40	40		T41	49
prescale[26]	1002	1		T22	79		T19	47		T28	161
prescale[27]	991	1		T17	9		T28	99		T40	2
prescale[28]	666	1		T2	36		T22	23		T19	2
prescale[29]	762	1		T2	128		T12	9		T19	23
prescale[30]	577	1		T15	19		T28	47		T158	19
prescale[31]	549	1		T40	77		T42	19		T158	28
prescale_0	22175	1		T1	21		T2	116		T3	21

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33753	1		T1	9		T2	872		T3	9
auto[1]	11372	1		T1	12		T2	64		T3	12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	45125	1		T1	21		T2	936		T3	21

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	26163	1		T1	1		T2	614		T3	1
wkup[1]	313	1		T22	30		T42	21		T158	41
wkup[2]	275	1		T40	21		T101	21		T89	42
wkup[3]	285	1		T29	45		T41	21		T43	42
wkup[4]	286	1		T28	21		T42	26		T24	21
wkup[5]	254	1		T28	21		T89	21		T131	21
wkup[6]	128	1		T28	29		T40	21		T183	21
wkup[7]	278	1		T2	21		T42	42		T116	15
wkup[8]	228	1		T2	21		T22	21		T28	21
wkup[9]	305	1		T13	15		T28	42		T171	21
wkup[10]	245	1		T43	30		T158	29		T133	20
wkup[11]	217	1		T22	21		T49	15		T42	21
wkup[12]	254	1		T2	21		T19	21		T28	21
wkup[13]	366	1		T15	21		T41	21		T158	21
wkup[14]	289	1		T1	15		T2	21		T101	51
wkup[15]	105	1		T101	21		T110	21		T104	21
wkup[16]	284	1		T22	26		T28	30		T42	39
wkup[17]	227	1		T28	63		T68	21		T83	21
wkup[18]	123	1		T2	21		T114	15		T83	15
wkup[19]	72	1		T84	21		T127	21		T118	15
wkup[20]	434	1		T40	21		T41	21		T43	21
wkup[21]	271	1		T40	21		T41	42		T42	21
wkup[22]	197	1		T15	21		T39	8		T40	21
wkup[23]	204	1		T22	21		T51	15		T113	35
wkup[24]	234	1		T15	21		T82	21		T101	21
wkup[25]	165	1		T41	21		T100	15		T123	15
wkup[26]	185	1		T2	21		T19	39		T41	15
wkup[27]	324	1		T28	31		T158	21		T89	21
wkup[28]	220	1		T89	24		T135	21		T91	21
wkup[29]	261	1		T87	15		T29	21		T158	21
wkup[30]	157	1		T40	8		T42	21		T24	21
wkup[31]	287	1		T7	15		T28	21		T40	21
wkup[32]	302	1		T41	21		T89	35		T112	21
wkup[33]	98	1		T19	21		T40	26		T113	15
wkup[34]	255	1		T28	30		T82	21		T101	21
wkup[35]	248	1		T2	72		T30	15		T39	21
wkup[36]	155	1		T28	21		T39	8		T88	42
wkup[37]	194	1		T2	21		T89	21		T124	21
wkup[38]	305	1		T28	42		T29	42		T98	21
wkup[39]	263	1		T2	21		T3	15		T90	26
wkup[40]	275	1		T40	39		T42	21		T101	21
wkup[41]	215	1		T89	21		T113	21		T104	21
wkup[42]	213	1		T19	21		T101	21		T98	21
wkup[43]	228	1		T2	21		T88	21		T101	8
wkup[44]	374	1		T28	21		T88	21		T132	15
wkup[45]	242	1		T46	15		T19	8		T42	30
wkup[46]	380	1		T2	21		T19	21		T28	42
wkup[47]	285	1		T43	21		T158	21		T171	30
wkup[48]	208	1		T28	34		T29	66		T42	21
wkup[49]	367	1		T28	42		T40	21		T41	21
wkup[50]	249	1		T28	21		T158	21		T89	21
wkup[51]	410	1		T28	15		T29	21		T39	30
wkup[52]	242	1		T28	29		T42	21		T133	21
wkup[53]	398	1		T2	21		T42	21		T158	42
wkup[54]	258	1		T40	21		T41	21		T82	21
wkup[55]	247	1		T14	15		T15	21		T28	26
wkup[56]	262	1		T19	30		T89	21		T107	15
wkup[57]	156	1		T28	26		T88	21		T127	21
wkup[58]	211	1		T29	30		T82	47		T127	21
wkup[59]	248	1		T42	21		T158	15		T132	21
wkup[60]	265	1		T28	42		T42	15		T101	21
wkup[61]	214	1		T44	15		T28	8		T29	47
wkup[62]	237	1		T22	15		T41	39		T42	21
wkup[63]	168	1		T132	30		T53	21		T91	8
wkup_0	3317	1		T1	5		T2	19		T3	5