Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 2 0 2 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 8 0 8 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 3235 1 T1 4 T4 1 T2 8
all_pins[1] 3235 1 T1 4 T4 1 T2 8



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 4572 1 T1 4 T4 2 T2 7
values[0x1] 1898 1 T1 4 T2 9 T3 1
transitions[0x0=>0x1] 1519 1 T1 2 T2 4 T3 1
transitions[0x1=>0x0] 1462 1 T1 1 T2 4 T3 1



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 2689 1 T1 1 T4 1 T2 2
all_pins[0] values[0x1] 546 1 T1 3 T2 6 T11 3
all_pins[0] transitions[0x0=>0x1] 291 1 T1 2 T2 3 T11 1
all_pins[0] transitions[0x1=>0x0] 1097 1 T3 1 T5 1 T6 1
all_pins[1] values[0x0] 1883 1 T1 3 T4 1 T2 5
all_pins[1] values[0x1] 1352 1 T1 1 T2 3 T3 1
all_pins[1] transitions[0x0=>0x1] 1228 1 T2 1 T3 1 T5 1
all_pins[1] transitions[0x1=>0x0] 365 1 T1 1 T2 4 T11 1

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