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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.84 99.33 93.67 100.00 98.40 99.51 48.13


Total test records in report: 421
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T33 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2906046576 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:48 PM PDT 24 356923927 ps
T37 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1264122436 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:50 PM PDT 24 812768405 ps
T281 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2224365999 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:28 PM PDT 24 434003523 ps
T282 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.780527393 Jul 18 05:57:39 PM PDT 24 Jul 18 05:57:43 PM PDT 24 331353567 ps
T38 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.630506226 Jul 18 05:58:04 PM PDT 24 Jul 18 05:58:14 PM PDT 24 1136302992 ps
T283 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2929948960 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:10 PM PDT 24 340974612 ps
T77 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1123711202 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:02 PM PDT 24 368730447 ps
T55 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.673387144 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:10 PM PDT 24 516397148 ps
T34 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3825731325 Jul 18 05:59:02 PM PDT 24 Jul 18 05:59:16 PM PDT 24 4149001237 ps
T78 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.732709700 Jul 18 05:57:47 PM PDT 24 Jul 18 05:57:53 PM PDT 24 1359393191 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.620990206 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:05 PM PDT 24 566066058 ps
T284 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.442443808 Jul 18 05:57:46 PM PDT 24 Jul 18 05:57:54 PM PDT 24 7437419005 ps
T79 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1365875892 Jul 18 05:57:40 PM PDT 24 Jul 18 05:57:43 PM PDT 24 1127845541 ps
T57 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1445896331 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:49 PM PDT 24 434695912 ps
T285 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.4075436261 Jul 18 05:57:55 PM PDT 24 Jul 18 05:57:57 PM PDT 24 371058922 ps
T80 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.553138407 Jul 18 05:58:01 PM PDT 24 Jul 18 05:58:12 PM PDT 24 1041042278 ps
T81 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2752428685 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:03 PM PDT 24 517609899 ps
T203 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.156840649 Jul 18 05:58:01 PM PDT 24 Jul 18 05:58:15 PM PDT 24 7373120743 ps
T286 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2709039816 Jul 18 05:58:02 PM PDT 24 Jul 18 05:58:13 PM PDT 24 524200425 ps
T287 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.502126426 Jul 18 05:57:45 PM PDT 24 Jul 18 05:57:52 PM PDT 24 307932701 ps
T288 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1970564424 Jul 18 05:57:45 PM PDT 24 Jul 18 05:57:51 PM PDT 24 295415570 ps
T289 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1735657191 Jul 18 05:57:42 PM PDT 24 Jul 18 05:57:47 PM PDT 24 495637410 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.934565586 Jul 18 05:57:44 PM PDT 24 Jul 18 05:57:51 PM PDT 24 336744481 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3465265968 Jul 18 05:59:22 PM PDT 24 Jul 18 05:59:41 PM PDT 24 2570633460 ps
T292 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1948158167 Jul 18 05:57:56 PM PDT 24 Jul 18 05:58:00 PM PDT 24 1048202931 ps
T293 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2428804791 Jul 18 05:57:46 PM PDT 24 Jul 18 05:57:52 PM PDT 24 566020376 ps
T294 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1447970651 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:03 PM PDT 24 630281931 ps
T295 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3978907985 Jul 18 05:57:41 PM PDT 24 Jul 18 05:57:44 PM PDT 24 342985848 ps
T296 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4287604222 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:01 PM PDT 24 495414692 ps
T35 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3807149679 Jul 18 05:57:46 PM PDT 24 Jul 18 05:58:03 PM PDT 24 7950482492 ps
T36 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.972967704 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:52 PM PDT 24 4538209767 ps
T70 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1605054986 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:14 PM PDT 24 14110501083 ps
T297 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2009046787 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:08 PM PDT 24 325974567 ps
T298 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2599103039 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:07 PM PDT 24 682945010 ps
T299 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3501513637 Jul 18 05:57:47 PM PDT 24 Jul 18 05:57:53 PM PDT 24 402969157 ps
T300 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.558452014 Jul 18 05:58:01 PM PDT 24 Jul 18 05:58:11 PM PDT 24 312755137 ps
T301 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.548163975 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:10 PM PDT 24 1275053356 ps
T302 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1436730505 Jul 18 05:57:46 PM PDT 24 Jul 18 05:57:53 PM PDT 24 1065989891 ps
T303 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2118038423 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:08 PM PDT 24 500862794 ps
T193 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.988647202 Jul 18 05:57:55 PM PDT 24 Jul 18 05:58:08 PM PDT 24 8139683409 ps
T304 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2211320055 Jul 18 05:58:05 PM PDT 24 Jul 18 05:58:15 PM PDT 24 687268359 ps
T305 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2547596558 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:11 PM PDT 24 4173027967 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2831523201 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:01 PM PDT 24 385993266 ps
T306 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3614323879 Jul 18 05:57:55 PM PDT 24 Jul 18 05:57:58 PM PDT 24 478190052 ps
T307 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.192518061 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:09 PM PDT 24 333435844 ps
T308 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1682925523 Jul 18 05:57:44 PM PDT 24 Jul 18 05:57:51 PM PDT 24 469000426 ps
T309 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3127045351 Jul 18 05:58:01 PM PDT 24 Jul 18 05:58:12 PM PDT 24 434988601 ps
T310 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3023664832 Jul 18 05:58:06 PM PDT 24 Jul 18 05:58:17 PM PDT 24 580325052 ps
T311 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.190534574 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:10 PM PDT 24 2482804391 ps
T312 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3527886041 Jul 18 05:57:41 PM PDT 24 Jul 18 05:57:45 PM PDT 24 616242371 ps
T197 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4272612259 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:10 PM PDT 24 8679611883 ps
T313 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2837030200 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:10 PM PDT 24 4369016014 ps
T314 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.222855237 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:05 PM PDT 24 449645021 ps
T315 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3135606270 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:05 PM PDT 24 408724955 ps
T316 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2084444283 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:03 PM PDT 24 1278671078 ps
T317 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1646414423 Jul 18 05:57:56 PM PDT 24 Jul 18 05:57:59 PM PDT 24 539476013 ps
T318 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.283616647 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:49 PM PDT 24 705023877 ps
T319 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1022424506 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:11 PM PDT 24 387679484 ps
T320 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2556115445 Jul 18 05:58:15 PM PDT 24 Jul 18 05:58:22 PM PDT 24 366627031 ps
T72 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.414400764 Jul 18 05:57:43 PM PDT 24 Jul 18 05:58:11 PM PDT 24 11803828079 ps
T321 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.381483428 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:05 PM PDT 24 523256943 ps
T322 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.30719062 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:03 PM PDT 24 543631559 ps
T323 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1653832153 Jul 18 05:57:46 PM PDT 24 Jul 18 05:57:53 PM PDT 24 1395373228 ps
T324 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2781293818 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:08 PM PDT 24 297671388 ps
T325 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2316844190 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:01 PM PDT 24 1455300629 ps
T326 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3037276357 Jul 18 05:57:56 PM PDT 24 Jul 18 05:57:58 PM PDT 24 417317462 ps
T327 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3266515051 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:04 PM PDT 24 315747093 ps
T328 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.186534191 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:06 PM PDT 24 500838115 ps
T329 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.307661820 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:06 PM PDT 24 321588395 ps
T330 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4013188585 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:30 PM PDT 24 418904306 ps
T331 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2418135084 Jul 18 05:57:49 PM PDT 24 Jul 18 05:57:54 PM PDT 24 488499248 ps
T332 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2634640132 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:08 PM PDT 24 393703873 ps
T333 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1016450289 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:10 PM PDT 24 326194613 ps
T334 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2499338618 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:06 PM PDT 24 463796125 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2831847359 Jul 18 05:57:54 PM PDT 24 Jul 18 05:58:00 PM PDT 24 2432208574 ps
T336 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3568778916 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:11 PM PDT 24 450377227 ps
T337 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.724297185 Jul 18 05:58:02 PM PDT 24 Jul 18 05:58:13 PM PDT 24 452215035 ps
T338 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2427801829 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:10 PM PDT 24 417626862 ps
T339 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3492659123 Jul 18 05:58:02 PM PDT 24 Jul 18 05:58:13 PM PDT 24 495844903 ps
T58 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4100769619 Jul 18 05:58:18 PM PDT 24 Jul 18 05:58:24 PM PDT 24 391816322 ps
T340 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1436671012 Jul 18 05:57:46 PM PDT 24 Jul 18 05:57:52 PM PDT 24 332629551 ps
T341 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2648780909 Jul 18 05:58:04 PM PDT 24 Jul 18 05:58:15 PM PDT 24 388574340 ps
T342 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3317749453 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:06 PM PDT 24 478948280 ps
T343 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2691620504 Jul 18 05:58:13 PM PDT 24 Jul 18 05:58:21 PM PDT 24 331541570 ps
T194 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2833139306 Jul 18 05:58:17 PM PDT 24 Jul 18 05:58:24 PM PDT 24 4426053403 ps
T344 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4178469756 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:05 PM PDT 24 464075841 ps
T345 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1882766257 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:07 PM PDT 24 3238703508 ps
T346 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.271911504 Jul 18 05:57:56 PM PDT 24 Jul 18 05:58:00 PM PDT 24 2665802617 ps
T347 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4165665745 Jul 18 05:58:05 PM PDT 24 Jul 18 05:58:16 PM PDT 24 562239335 ps
T348 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1368395915 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:04 PM PDT 24 443712178 ps
T349 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2080281302 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:06 PM PDT 24 508872974 ps
T350 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.35263201 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:07 PM PDT 24 489798905 ps
T351 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.865349189 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:09 PM PDT 24 447819337 ps
T352 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1908956059 Jul 18 05:58:02 PM PDT 24 Jul 18 05:58:20 PM PDT 24 4436329296 ps
T353 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3603054363 Jul 18 05:57:44 PM PDT 24 Jul 18 05:57:52 PM PDT 24 402026237 ps
T354 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2219614588 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:05 PM PDT 24 584384256 ps
T355 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3820608045 Jul 18 05:57:55 PM PDT 24 Jul 18 05:57:58 PM PDT 24 376048884 ps
T356 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1676723542 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:36 PM PDT 24 431302072 ps
T74 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.645333299 Jul 18 05:57:39 PM PDT 24 Jul 18 05:57:42 PM PDT 24 384764516 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1164980397 Jul 18 05:57:42 PM PDT 24 Jul 18 05:57:47 PM PDT 24 6998406253 ps
T75 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3081959624 Jul 18 05:58:07 PM PDT 24 Jul 18 05:58:18 PM PDT 24 405188617 ps
T76 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.259694535 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:08 PM PDT 24 393179830 ps
T358 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.953951439 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:09 PM PDT 24 467059001 ps
T359 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3694010451 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:49 PM PDT 24 8410132573 ps
T360 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2067633560 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:03 PM PDT 24 483901608 ps
T73 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.635625008 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:01 PM PDT 24 443509071 ps
T361 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.445241647 Jul 18 05:58:04 PM PDT 24 Jul 18 05:58:14 PM PDT 24 437897359 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3753457887 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:49 PM PDT 24 440158918 ps
T363 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3004107422 Jul 18 05:58:12 PM PDT 24 Jul 18 05:58:20 PM PDT 24 341106580 ps
T364 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2003655737 Jul 18 05:57:54 PM PDT 24 Jul 18 05:57:57 PM PDT 24 429950563 ps
T195 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1450589383 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:21 PM PDT 24 8303956541 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.197136228 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:08 PM PDT 24 407464988 ps
T366 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4212027529 Jul 18 05:57:44 PM PDT 24 Jul 18 05:57:52 PM PDT 24 9101300689 ps
T367 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1666524499 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:09 PM PDT 24 431142647 ps
T368 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3848352635 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:09 PM PDT 24 264237588 ps
T369 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2893872678 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:06 PM PDT 24 710350726 ps
T370 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3934872946 Jul 18 05:58:18 PM PDT 24 Jul 18 05:58:24 PM PDT 24 470383424 ps
T371 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1317833860 Jul 18 05:58:14 PM PDT 24 Jul 18 05:58:21 PM PDT 24 502261860 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2962325737 Jul 18 05:58:01 PM PDT 24 Jul 18 05:58:12 PM PDT 24 417654588 ps
T373 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3146934246 Jul 18 05:57:55 PM PDT 24 Jul 18 05:57:58 PM PDT 24 436416719 ps
T196 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3267299018 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:15 PM PDT 24 8111656087 ps
T374 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1622800599 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:00 PM PDT 24 335629615 ps
T375 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.863592644 Jul 18 05:58:05 PM PDT 24 Jul 18 05:58:16 PM PDT 24 348950184 ps
T376 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3603231811 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:50 PM PDT 24 487720929 ps
T377 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3739494493 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:01 PM PDT 24 375804334 ps
T59 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2303642694 Jul 18 05:57:42 PM PDT 24 Jul 18 05:57:48 PM PDT 24 432753233 ps
T378 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3620550265 Jul 18 05:58:07 PM PDT 24 Jul 18 05:58:17 PM PDT 24 365570166 ps
T379 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.288806003 Jul 18 05:58:05 PM PDT 24 Jul 18 05:58:16 PM PDT 24 1179081884 ps
T380 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2605086072 Jul 18 05:58:01 PM PDT 24 Jul 18 05:58:12 PM PDT 24 1212747192 ps
T381 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2761371853 Jul 18 05:57:54 PM PDT 24 Jul 18 05:57:58 PM PDT 24 8530801785 ps
T382 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2356410308 Jul 18 05:58:07 PM PDT 24 Jul 18 05:58:21 PM PDT 24 1709243145 ps
T383 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3014811738 Jul 18 05:58:04 PM PDT 24 Jul 18 05:58:14 PM PDT 24 409565074 ps
T384 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3104974426 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:01 PM PDT 24 382130893 ps
T385 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3798121 Jul 18 05:57:44 PM PDT 24 Jul 18 05:57:52 PM PDT 24 864109256 ps
T386 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4214354648 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:15 PM PDT 24 4212169431 ps
T387 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1937074624 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:31 PM PDT 24 296159869 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3743389066 Jul 18 05:57:42 PM PDT 24 Jul 18 05:57:47 PM PDT 24 454776892 ps
T389 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3435637875 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:12 PM PDT 24 2354592028 ps
T390 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2761777778 Jul 18 05:58:01 PM PDT 24 Jul 18 05:58:13 PM PDT 24 1189525596 ps
T391 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3245448917 Jul 18 05:57:58 PM PDT 24 Jul 18 05:58:05 PM PDT 24 2525945390 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2431913265 Jul 18 05:57:36 PM PDT 24 Jul 18 05:57:39 PM PDT 24 516497324 ps
T393 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1065493975 Jul 18 05:58:04 PM PDT 24 Jul 18 05:58:14 PM PDT 24 409963936 ps
T394 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2869981686 Jul 18 05:57:56 PM PDT 24 Jul 18 05:58:09 PM PDT 24 7970815805 ps
T395 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3885340255 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:06 PM PDT 24 341693616 ps
T396 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.270922580 Jul 18 05:57:56 PM PDT 24 Jul 18 05:57:59 PM PDT 24 534081989 ps
T397 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.986064136 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:12 PM PDT 24 1594874519 ps
T398 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2689047692 Jul 18 05:58:02 PM PDT 24 Jul 18 05:58:14 PM PDT 24 499754786 ps
T399 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2952022581 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:02 PM PDT 24 421700551 ps
T400 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2864196410 Jul 18 05:57:55 PM PDT 24 Jul 18 05:57:57 PM PDT 24 568542170 ps
T401 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3716265853 Jul 18 05:58:05 PM PDT 24 Jul 18 05:58:16 PM PDT 24 340185242 ps
T402 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2666980530 Jul 18 05:58:19 PM PDT 24 Jul 18 05:58:25 PM PDT 24 450098525 ps
T403 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4005214608 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:12 PM PDT 24 7868272663 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2543189037 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:49 PM PDT 24 400286941 ps
T405 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.88380137 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:09 PM PDT 24 452624188 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3549569754 Jul 18 05:57:42 PM PDT 24 Jul 18 05:57:46 PM PDT 24 449056619 ps
T407 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4230214818 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:11 PM PDT 24 449825618 ps
T408 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4033480928 Jul 18 05:58:02 PM PDT 24 Jul 18 05:58:25 PM PDT 24 8306958174 ps
T409 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3557240498 Jul 18 05:57:55 PM PDT 24 Jul 18 05:57:57 PM PDT 24 456256388 ps
T410 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.571964076 Jul 18 05:57:57 PM PDT 24 Jul 18 05:58:05 PM PDT 24 8039998999 ps
T411 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4772252 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:49 PM PDT 24 296810963 ps
T412 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1157588441 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:51 PM PDT 24 840473313 ps
T413 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.633718690 Jul 18 05:57:47 PM PDT 24 Jul 18 05:57:53 PM PDT 24 420917466 ps
T414 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3727893614 Jul 18 05:57:59 PM PDT 24 Jul 18 05:58:10 PM PDT 24 724180313 ps
T60 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2525217104 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:10 PM PDT 24 375114753 ps
T415 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2000369485 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:10 PM PDT 24 525764517 ps
T416 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.112023631 Jul 18 05:58:00 PM PDT 24 Jul 18 05:58:10 PM PDT 24 379075263 ps
T417 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1378449236 Jul 18 05:58:05 PM PDT 24 Jul 18 05:58:16 PM PDT 24 2373547018 ps
T418 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2639251525 Jul 18 05:57:43 PM PDT 24 Jul 18 05:57:50 PM PDT 24 491607252 ps
T419 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1974958950 Jul 18 05:57:41 PM PDT 24 Jul 18 05:57:53 PM PDT 24 7739124216 ps
T420 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2915414106 Jul 18 05:57:42 PM PDT 24 Jul 18 05:57:47 PM PDT 24 535652913 ps
T421 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.179333351 Jul 18 05:57:42 PM PDT 24 Jul 18 05:57:46 PM PDT 24 855049025 ps

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2425743242
Short name T2
Test name
Test status
Simulation time 13187236066 ps
CPU time 72.51 seconds
Started Jul 18 05:57:41 PM PDT 24
Finished Jul 18 05:58:56 PM PDT 24
Peak memory 198216 kb
Host smart-41429a53-fc62-4d02-879b-15d5726c1b17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425743242 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2425743242
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2425252922
Short name T28
Test name
Test status
Simulation time 792006619574 ps
CPU time 971.61 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 06:13:16 PM PDT 24
Peak memory 214656 kb
Host smart-96125fe5-bca8-4b87-81d3-aaf6f19dc5b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425252922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2425252922
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3825731325
Short name T34
Test name
Test status
Simulation time 4149001237 ps
CPU time 6.47 seconds
Started Jul 18 05:59:02 PM PDT 24
Finished Jul 18 05:59:16 PM PDT 24
Peak memory 197920 kb
Host smart-20048d31-d6c7-4e1d-8fcc-4c6e928ec0db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825731325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3825731325
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/27.aon_timer_jump.340239746
Short name T1
Test name
Test status
Simulation time 568043176 ps
CPU time 1.45 seconds
Started Jul 18 05:57:15 PM PDT 24
Finished Jul 18 05:57:20 PM PDT 24
Peak memory 196304 kb
Host smart-192afd54-cfe3-477c-857d-f1b6a897fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340239746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.340239746
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.304624018
Short name T22
Test name
Test status
Simulation time 482858804851 ps
CPU time 629.11 seconds
Started Jul 18 05:57:14 PM PDT 24
Finished Jul 18 06:07:47 PM PDT 24
Peak memory 197884 kb
Host smart-8d6f7e94-2f40-4d6f-8afa-b1d2918759d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304624018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.304624018
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3618396518
Short name T89
Test name
Test status
Simulation time 100097580313 ps
CPU time 212.27 seconds
Started Jul 18 05:57:01 PM PDT 24
Finished Jul 18 06:00:41 PM PDT 24
Peak memory 208052 kb
Host smart-527f9157-6984-4cf0-bd40-bc7b306a8bde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618396518 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3618396518
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3793625940
Short name T140
Test name
Test status
Simulation time 155874678309 ps
CPU time 334.05 seconds
Started Jul 18 05:57:41 PM PDT 24
Finished Jul 18 06:03:17 PM PDT 24
Peak memory 201480 kb
Host smart-3fe79800-7a33-459a-9c82-1cfdf21ec845
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793625940 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3793625940
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.815522504
Short name T158
Test name
Test status
Simulation time 45805789016 ps
CPU time 374.35 seconds
Started Jul 18 05:57:16 PM PDT 24
Finished Jul 18 06:03:34 PM PDT 24
Peak memory 199040 kb
Host smart-22317e35-bb7a-4605-8002-2c03b20b99b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815522504 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.815522504
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2974659235
Short name T137
Test name
Test status
Simulation time 143196474819 ps
CPU time 143.29 seconds
Started Jul 18 05:57:30 PM PDT 24
Finished Jul 18 05:59:56 PM PDT 24
Peak memory 198068 kb
Host smart-90a3f1d7-26c5-43e6-aa51-9d5b7fcacd6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974659235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2974659235
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.367064689
Short name T93
Test name
Test status
Simulation time 65103166717 ps
CPU time 393.28 seconds
Started Jul 18 05:57:04 PM PDT 24
Finished Jul 18 06:03:44 PM PDT 24
Peak memory 199776 kb
Host smart-af8545a4-1da3-46e1-b431-c78fcabf36a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367064689 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.367064689
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.619825586
Short name T92
Test name
Test status
Simulation time 86278094939 ps
CPU time 636.97 seconds
Started Jul 18 05:57:33 PM PDT 24
Finished Jul 18 06:08:12 PM PDT 24
Peak memory 213244 kb
Host smart-375431d8-970f-4502-a069-8cfcbf3d701d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619825586 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.619825586
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.451107260
Short name T20
Test name
Test status
Simulation time 4203176625 ps
CPU time 1.45 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:04 PM PDT 24
Peak memory 215148 kb
Host smart-1fa4414f-87c5-4baa-94ee-8293d3c024ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451107260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.451107260
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2448429248
Short name T32
Test name
Test status
Simulation time 486880645 ps
CPU time 0.77 seconds
Started Jul 18 05:58:02 PM PDT 24
Finished Jul 18 05:58:12 PM PDT 24
Peak memory 193332 kb
Host smart-b3fa2461-aaa0-4784-a2fd-a2c64f391976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448429248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2448429248
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2482167552
Short name T94
Test name
Test status
Simulation time 143830507434 ps
CPU time 1198.16 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 06:17:05 PM PDT 24
Peak memory 211252 kb
Host smart-900b3f72-cbb6-4d26-9740-a213dfb6a5f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482167552 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2482167552
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.27864197
Short name T131
Test name
Test status
Simulation time 48682097421 ps
CPU time 33.28 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:36 PM PDT 24
Peak memory 197856 kb
Host smart-ee6ceb06-f5a8-4260-aee6-ace1aa893f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27864197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all
.27864197
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.461584333
Short name T105
Test name
Test status
Simulation time 119876298169 ps
CPU time 182.82 seconds
Started Jul 18 05:57:36 PM PDT 24
Finished Jul 18 06:00:41 PM PDT 24
Peak memory 192660 kb
Host smart-df9b46e4-ff51-445f-bb6a-f0d7092034b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461584333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.461584333
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3102298858
Short name T101
Test name
Test status
Simulation time 435364700555 ps
CPU time 1061.04 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 06:14:51 PM PDT 24
Peak memory 211224 kb
Host smart-b6113ba6-8b4b-4968-af49-db96dedca0a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102298858 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3102298858
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.316030575
Short name T86
Test name
Test status
Simulation time 204673383973 ps
CPU time 383.2 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 06:03:45 PM PDT 24
Peak memory 201796 kb
Host smart-69467667-b2de-4f76-84e2-4322874d27c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316030575 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.316030575
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2532186190
Short name T42
Test name
Test status
Simulation time 66173402421 ps
CPU time 693.95 seconds
Started Jul 18 05:57:10 PM PDT 24
Finished Jul 18 06:08:48 PM PDT 24
Peak memory 213288 kb
Host smart-a566b475-0270-4c42-9a7a-ff8f06f06c37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532186190 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2532186190
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.839901673
Short name T122
Test name
Test status
Simulation time 77365081726 ps
CPU time 203.24 seconds
Started Jul 18 05:57:20 PM PDT 24
Finished Jul 18 06:00:46 PM PDT 24
Peak memory 199600 kb
Host smart-df84b253-f7c1-45e8-8dfc-e65761cd1382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839901673 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.839901673
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1781930878
Short name T130
Test name
Test status
Simulation time 4789705492 ps
CPU time 2.46 seconds
Started Jul 18 05:57:44 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 191528 kb
Host smart-81d5c122-5a45-44a4-abe8-5d46b303bcb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781930878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1781930878
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2938706767
Short name T98
Test name
Test status
Simulation time 102107268921 ps
CPU time 142.15 seconds
Started Jul 18 05:57:02 PM PDT 24
Finished Jul 18 05:59:32 PM PDT 24
Peak memory 192640 kb
Host smart-51065e42-2734-413e-9071-d75127df7175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938706767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2938706767
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2679596007
Short name T136
Test name
Test status
Simulation time 292619817212 ps
CPU time 405.13 seconds
Started Jul 18 05:57:02 PM PDT 24
Finished Jul 18 06:03:55 PM PDT 24
Peak memory 191568 kb
Host smart-ef7eef8a-56b9-46db-a7f1-93686d8da210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679596007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2679596007
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3618804418
Short name T128
Test name
Test status
Simulation time 149085491022 ps
CPU time 873.26 seconds
Started Jul 18 05:57:32 PM PDT 24
Finished Jul 18 06:12:08 PM PDT 24
Peak memory 208456 kb
Host smart-61fdb49d-5e7a-461a-8c8e-639a49a7bc87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618804418 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3618804418
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.340267377
Short name T126
Test name
Test status
Simulation time 69612854864 ps
CPU time 46.39 seconds
Started Jul 18 05:57:45 PM PDT 24
Finished Jul 18 05:58:37 PM PDT 24
Peak memory 191556 kb
Host smart-52c31f49-0e51-4c16-85c9-d955bc675e08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340267377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.340267377
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1309633450
Short name T24
Test name
Test status
Simulation time 207006611110 ps
CPU time 309.58 seconds
Started Jul 18 05:57:30 PM PDT 24
Finished Jul 18 06:02:42 PM PDT 24
Peak memory 192660 kb
Host smart-e28c97e3-6377-4a74-9c25-c3e6c056922e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309633450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1309633450
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3436138435
Short name T85
Test name
Test status
Simulation time 302995292700 ps
CPU time 776.4 seconds
Started Jul 18 05:57:45 PM PDT 24
Finished Jul 18 06:10:47 PM PDT 24
Peak memory 214628 kb
Host smart-1e86ee1a-2690-4722-b7a2-ce610a949534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436138435 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3436138435
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.329929774
Short name T54
Test name
Test status
Simulation time 124634463807 ps
CPU time 753.37 seconds
Started Jul 18 05:57:07 PM PDT 24
Finished Jul 18 06:09:46 PM PDT 24
Peak memory 212076 kb
Host smart-dc693d75-0b3c-4611-b836-4bfe83e761d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329929774 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.329929774
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2998171399
Short name T99
Test name
Test status
Simulation time 112835944311 ps
CPU time 126.65 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 05:59:13 PM PDT 24
Peak memory 197848 kb
Host smart-7652d68a-f34f-4b8c-b639-cd994cce39fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998171399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2998171399
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2481086269
Short name T106
Test name
Test status
Simulation time 18113774425 ps
CPU time 191.64 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 06:00:22 PM PDT 24
Peak memory 206388 kb
Host smart-13536e4e-52f9-410b-b9e6-72373110ab25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481086269 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2481086269
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.823221533
Short name T148
Test name
Test status
Simulation time 24958143198 ps
CPU time 196.97 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 06:00:39 PM PDT 24
Peak memory 198200 kb
Host smart-9e73e3af-8998-4048-b7fb-404f560895e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823221533 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.823221533
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.995495223
Short name T40
Test name
Test status
Simulation time 71036313987 ps
CPU time 585.5 seconds
Started Jul 18 05:57:09 PM PDT 24
Finished Jul 18 06:06:59 PM PDT 24
Peak memory 206396 kb
Host smart-558036f0-b4be-4667-94c4-22184dd722da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995495223 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.995495223
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2264826941
Short name T112
Test name
Test status
Simulation time 152790277155 ps
CPU time 183.35 seconds
Started Jul 18 05:57:01 PM PDT 24
Finished Jul 18 06:00:12 PM PDT 24
Peak memory 192256 kb
Host smart-b8e007bf-6a4f-45ba-966e-435abe84fe77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264826941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2264826941
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3817239283
Short name T135
Test name
Test status
Simulation time 95098600990 ps
CPU time 23.96 seconds
Started Jul 18 05:57:20 PM PDT 24
Finished Jul 18 05:57:47 PM PDT 24
Peak memory 192652 kb
Host smart-b3f5e347-864f-49c5-8ad3-1f6b7abcd86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817239283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3817239283
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2298035909
Short name T120
Test name
Test status
Simulation time 131942298908 ps
CPU time 205.14 seconds
Started Jul 18 05:57:29 PM PDT 24
Finished Jul 18 06:00:56 PM PDT 24
Peak memory 192648 kb
Host smart-86768a8f-635e-47b0-b89f-4429af1bfe87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298035909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2298035909
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1506128964
Short name T109
Test name
Test status
Simulation time 72902192179 ps
CPU time 18.32 seconds
Started Jul 18 05:57:26 PM PDT 24
Finished Jul 18 05:57:45 PM PDT 24
Peak memory 192376 kb
Host smart-80a203bb-f593-47e6-b4e5-32aaf1468644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506128964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1506128964
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.710260551
Short name T157
Test name
Test status
Simulation time 54956392588 ps
CPU time 459.99 seconds
Started Jul 18 05:57:26 PM PDT 24
Finished Jul 18 06:05:07 PM PDT 24
Peak memory 213748 kb
Host smart-a5a3d7c6-b235-452c-a584-ae3c64f8bec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710260551 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.710260551
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1710787136
Short name T84
Test name
Test status
Simulation time 109035855533 ps
CPU time 260.69 seconds
Started Jul 18 05:57:02 PM PDT 24
Finished Jul 18 06:01:31 PM PDT 24
Peak memory 214084 kb
Host smart-a374ad56-e3de-4acc-a931-ca34ff37f817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710787136 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1710787136
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.119630357
Short name T113
Test name
Test status
Simulation time 61477611702 ps
CPU time 42.67 seconds
Started Jul 18 05:57:12 PM PDT 24
Finished Jul 18 05:57:59 PM PDT 24
Peak memory 192588 kb
Host smart-6d71a16d-00a8-4459-afa7-cea36f7a11e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119630357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.119630357
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.4145844874
Short name T125
Test name
Test status
Simulation time 25403531315 ps
CPU time 17.81 seconds
Started Jul 18 05:57:16 PM PDT 24
Finished Jul 18 05:57:38 PM PDT 24
Peak memory 192732 kb
Host smart-cc2e695d-1145-489b-86b4-bd18b9992f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145844874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.4145844874
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3489599748
Short name T152
Test name
Test status
Simulation time 222114739030 ps
CPU time 58.54 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:58:03 PM PDT 24
Peak memory 191636 kb
Host smart-87db571a-ccc7-48a1-ba2a-fd5d631713aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489599748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3489599748
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2651628609
Short name T29
Test name
Test status
Simulation time 73314039892 ps
CPU time 306.01 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 06:02:12 PM PDT 24
Peak memory 208548 kb
Host smart-77378766-8453-42ba-93e1-fdbf888c0aec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651628609 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2651628609
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.290725399
Short name T124
Test name
Test status
Simulation time 265828933666 ps
CPU time 205.8 seconds
Started Jul 18 05:57:29 PM PDT 24
Finished Jul 18 06:00:57 PM PDT 24
Peak memory 197872 kb
Host smart-0fbac386-d602-4c08-98d5-e750a97166e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290725399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.290725399
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.665638533
Short name T115
Test name
Test status
Simulation time 146143820764 ps
CPU time 113.38 seconds
Started Jul 18 05:57:07 PM PDT 24
Finished Jul 18 05:59:06 PM PDT 24
Peak memory 197824 kb
Host smart-5b0f5f27-fbcc-4708-818e-51bde3b90a66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665638533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.665638533
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3528120159
Short name T110
Test name
Test status
Simulation time 164867323436 ps
CPU time 112.95 seconds
Started Jul 18 05:57:29 PM PDT 24
Finished Jul 18 05:59:25 PM PDT 24
Peak memory 191612 kb
Host smart-15390f5a-e498-4a34-aaec-d32f56b1cfbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528120159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3528120159
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2895841074
Short name T88
Test name
Test status
Simulation time 114013278200 ps
CPU time 143.11 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 06:00:10 PM PDT 24
Peak memory 207452 kb
Host smart-7738fb26-0573-4db5-937e-8515815c4a83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895841074 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2895841074
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3551652894
Short name T83
Test name
Test status
Simulation time 409543477318 ps
CPU time 571.09 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 06:06:35 PM PDT 24
Peak memory 204576 kb
Host smart-0563d1e6-cfad-4282-91ac-209c15873e5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551652894 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3551652894
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1184634925
Short name T119
Test name
Test status
Simulation time 107275983299 ps
CPU time 156.34 seconds
Started Jul 18 05:57:06 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 192540 kb
Host smart-b0e8aa47-bfad-465b-bf04-c2e5e0df7b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184634925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1184634925
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1766115774
Short name T142
Test name
Test status
Simulation time 244433548345 ps
CPU time 179.98 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 06:00:06 PM PDT 24
Peak memory 191556 kb
Host smart-71040a39-817f-4a57-b5f0-605c159cf637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766115774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1766115774
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.570086525
Short name T103
Test name
Test status
Simulation time 145663173714 ps
CPU time 390.62 seconds
Started Jul 18 05:57:20 PM PDT 24
Finished Jul 18 06:03:53 PM PDT 24
Peak memory 206396 kb
Host smart-33ebf378-aef5-43f0-9851-b0c371b3a652
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570086525 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.570086525
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2304015924
Short name T151
Test name
Test status
Simulation time 122167285950 ps
CPU time 25.56 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:30 PM PDT 24
Peak memory 197892 kb
Host smart-fe2fcc12-083d-482a-8776-cba1d269da0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304015924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2304015924
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2139069679
Short name T91
Test name
Test status
Simulation time 128845856278 ps
CPU time 149.19 seconds
Started Jul 18 05:57:23 PM PDT 24
Finished Jul 18 05:59:53 PM PDT 24
Peak memory 207252 kb
Host smart-6276c2df-5c47-4cd5-956c-490ea8703f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139069679 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2139069679
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.281975375
Short name T156
Test name
Test status
Simulation time 39160055450 ps
CPU time 11.65 seconds
Started Jul 18 05:57:39 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 190604 kb
Host smart-affc6d2c-2ba2-4076-b661-b0f4209b4557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281975375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.281975375
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3397466829
Short name T150
Test name
Test status
Simulation time 48808383961 ps
CPU time 68.76 seconds
Started Jul 18 05:57:38 PM PDT 24
Finished Jul 18 05:58:48 PM PDT 24
Peak memory 197908 kb
Host smart-826ed12b-cfef-4497-b7ff-20d0e4c19d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397466829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3397466829
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.751831734
Short name T138
Test name
Test status
Simulation time 139474602272 ps
CPU time 25.02 seconds
Started Jul 18 05:57:00 PM PDT 24
Finished Jul 18 05:57:33 PM PDT 24
Peak memory 197900 kb
Host smart-3fc9bd6c-3415-4b8d-887d-c05f0c04cb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751831734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.751831734
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1923095054
Short name T133
Test name
Test status
Simulation time 283864526807 ps
CPU time 38.9 seconds
Started Jul 18 05:57:32 PM PDT 24
Finished Jul 18 05:58:13 PM PDT 24
Peak memory 192636 kb
Host smart-70eda2ba-7f6e-4cba-b172-08da7df7705d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923095054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1923095054
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.427128177
Short name T104
Test name
Test status
Simulation time 125364129224 ps
CPU time 90.79 seconds
Started Jul 18 05:57:02 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 192560 kb
Host smart-99294148-4c78-4c01-9858-96c35bbdb1b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427128177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.427128177
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.613218565
Short name T15
Test name
Test status
Simulation time 33203201851 ps
CPU time 97.43 seconds
Started Jul 18 05:57:32 PM PDT 24
Finished Jul 18 05:59:12 PM PDT 24
Peak memory 198228 kb
Host smart-c0a592ce-8506-43ff-82b5-24b56ebcec4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613218565 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.613218565
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2107698566
Short name T127
Test name
Test status
Simulation time 27134686138 ps
CPU time 246.29 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 06:01:12 PM PDT 24
Peak memory 198212 kb
Host smart-935f9953-2b24-45da-874e-30bb2b6f239b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107698566 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2107698566
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2241374307
Short name T117
Test name
Test status
Simulation time 77616965575 ps
CPU time 124.73 seconds
Started Jul 18 05:57:00 PM PDT 24
Finished Jul 18 05:59:12 PM PDT 24
Peak memory 191508 kb
Host smart-73970310-d102-4105-bd55-d5c2c830adf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241374307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2241374307
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.759528812
Short name T173
Test name
Test status
Simulation time 61804046594 ps
CPU time 43.86 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:54 PM PDT 24
Peak memory 192644 kb
Host smart-05a2cf1a-0954-4ec4-9221-8e4bb3b574c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759528812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.759528812
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.629133927
Short name T39
Test name
Test status
Simulation time 97351791165 ps
CPU time 184.5 seconds
Started Jul 18 05:57:32 PM PDT 24
Finished Jul 18 06:00:39 PM PDT 24
Peak memory 206404 kb
Host smart-a034b128-8e46-4a44-99ef-829d41bc5a96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629133927 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.629133927
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2604856377
Short name T153
Test name
Test status
Simulation time 71781258772 ps
CPU time 26.37 seconds
Started Jul 18 05:57:31 PM PDT 24
Finished Jul 18 05:57:59 PM PDT 24
Peak memory 192604 kb
Host smart-c9c897d7-a9f3-46b9-864e-c9ae7dc6bf90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604856377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2604856377
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1947021439
Short name T43
Test name
Test status
Simulation time 6572558001 ps
CPU time 46.72 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:58:34 PM PDT 24
Peak memory 198256 kb
Host smart-0ace2506-8ff2-47af-8be2-a20bc0e9875a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947021439 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1947021439
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2676975338
Short name T41
Test name
Test status
Simulation time 39129396116 ps
CPU time 410.15 seconds
Started Jul 18 05:57:34 PM PDT 24
Finished Jul 18 06:04:26 PM PDT 24
Peak memory 207716 kb
Host smart-cc9df0bd-da7c-4afa-8157-0fb688c4d16b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676975338 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2676975338
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2271225507
Short name T132
Test name
Test status
Simulation time 102390192066 ps
CPU time 25.21 seconds
Started Jul 18 05:57:47 PM PDT 24
Finished Jul 18 05:58:17 PM PDT 24
Peak memory 197484 kb
Host smart-756fe9e4-5a5f-4c8a-a6ef-4b7251cd6801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271225507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2271225507
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3249368290
Short name T100
Test name
Test status
Simulation time 372614076 ps
CPU time 1.11 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 05:57:09 PM PDT 24
Peak memory 196364 kb
Host smart-35547922-29be-42f1-9257-75561fc69721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249368290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3249368290
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1480013437
Short name T129
Test name
Test status
Simulation time 44362650216 ps
CPU time 71.87 seconds
Started Jul 18 05:57:26 PM PDT 24
Finished Jul 18 05:58:39 PM PDT 24
Peak memory 192552 kb
Host smart-57658b03-ec6e-4bf6-a090-ecce49cdf9b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480013437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1480013437
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.154397591
Short name T82
Test name
Test status
Simulation time 25639919603 ps
CPU time 249.64 seconds
Started Jul 18 05:57:16 PM PDT 24
Finished Jul 18 06:01:30 PM PDT 24
Peak memory 206368 kb
Host smart-39ec8683-d3f6-4c09-b8cd-97c202ab33cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154397591 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.154397591
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1481638245
Short name T163
Test name
Test status
Simulation time 486580403209 ps
CPU time 623.67 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 06:07:27 PM PDT 24
Peak memory 192024 kb
Host smart-1f9e5235-b46f-4b77-b44c-a6182208e65a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481638245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1481638245
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2303156271
Short name T144
Test name
Test status
Simulation time 105550999632 ps
CPU time 170.09 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 05:59:57 PM PDT 24
Peak memory 191552 kb
Host smart-7cfd7670-e773-4535-be7a-331cce415709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303156271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2303156271
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1517465373
Short name T95
Test name
Test status
Simulation time 30790953356 ps
CPU time 227.93 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 06:01:10 PM PDT 24
Peak memory 206404 kb
Host smart-29ed7d3d-7388-4b47-a292-3c2ef5df440c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517465373 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1517465373
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2975434253
Short name T68
Test name
Test status
Simulation time 74515180856 ps
CPU time 195.55 seconds
Started Jul 18 05:57:35 PM PDT 24
Finished Jul 18 06:00:52 PM PDT 24
Peak memory 206372 kb
Host smart-9e9dab77-8ca7-4645-9e7b-b8c955ef98f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975434253 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2975434253
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.929568972
Short name T159
Test name
Test status
Simulation time 296512735050 ps
CPU time 442.75 seconds
Started Jul 18 05:57:36 PM PDT 24
Finished Jul 18 06:05:00 PM PDT 24
Peak memory 192648 kb
Host smart-c3cebf18-f8f0-45c8-a4da-b048c5c0d231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929568972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.929568972
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1171686971
Short name T97
Test name
Test status
Simulation time 550925539 ps
CPU time 0.69 seconds
Started Jul 18 05:57:39 PM PDT 24
Finished Jul 18 05:57:41 PM PDT 24
Peak memory 196328 kb
Host smart-c78918b8-0c4f-429c-9a5a-32322e6e202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171686971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1171686971
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2129675791
Short name T90
Test name
Test status
Simulation time 43633866695 ps
CPU time 88.95 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:59:15 PM PDT 24
Peak memory 213616 kb
Host smart-0dd18a94-e2d9-46ae-9738-23fd153a6c5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129675791 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2129675791
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.554731118
Short name T30
Test name
Test status
Simulation time 607555261 ps
CPU time 0.77 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:03 PM PDT 24
Peak memory 196384 kb
Host smart-31d46348-f8fa-487f-81e9-fca0f976cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554731118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.554731118
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1945612739
Short name T114
Test name
Test status
Simulation time 586889166 ps
CPU time 0.95 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:11 PM PDT 24
Peak memory 196388 kb
Host smart-67c2572d-54c9-49b1-96d2-d6ce24c489e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945612739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1945612739
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.4211067340
Short name T134
Test name
Test status
Simulation time 360046717 ps
CPU time 0.69 seconds
Started Jul 18 05:57:00 PM PDT 24
Finished Jul 18 05:57:09 PM PDT 24
Peak memory 196288 kb
Host smart-269662aa-0a60-4da6-ad44-222a6acef2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211067340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.4211067340
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3307192699
Short name T155
Test name
Test status
Simulation time 371950739 ps
CPU time 0.71 seconds
Started Jul 18 05:57:18 PM PDT 24
Finished Jul 18 05:57:22 PM PDT 24
Peak memory 196396 kb
Host smart-376b8444-6082-4554-906e-eaefc757a1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307192699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3307192699
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.931335782
Short name T154
Test name
Test status
Simulation time 421504792 ps
CPU time 1.33 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:12 PM PDT 24
Peak memory 196416 kb
Host smart-9628feba-4afc-452c-b6d8-7243699836fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931335782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.931335782
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2352135057
Short name T19
Test name
Test status
Simulation time 45041552606 ps
CPU time 366.25 seconds
Started Jul 18 05:57:33 PM PDT 24
Finished Jul 18 06:03:41 PM PDT 24
Peak memory 206464 kb
Host smart-b5151085-d92f-4524-985b-d4eaeb7afe62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352135057 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2352135057
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.215208828
Short name T178
Test name
Test status
Simulation time 416637424554 ps
CPU time 167.05 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 06:00:09 PM PDT 24
Peak memory 197908 kb
Host smart-cf52dae3-780f-42c8-b4e9-3c2eb3187276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215208828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.215208828
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2877678261
Short name T96
Test name
Test status
Simulation time 55955757460 ps
CPU time 173.1 seconds
Started Jul 18 05:57:40 PM PDT 24
Finished Jul 18 06:00:35 PM PDT 24
Peak memory 214456 kb
Host smart-15ae5141-224e-400c-a8fd-bffc00bf1c71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877678261 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2877678261
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1832593920
Short name T121
Test name
Test status
Simulation time 463516603 ps
CPU time 1.22 seconds
Started Jul 18 05:57:02 PM PDT 24
Finished Jul 18 05:57:11 PM PDT 24
Peak memory 196420 kb
Host smart-5dd40b56-259e-4abf-8c72-c5f8308377d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832593920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1832593920
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.431621804
Short name T149
Test name
Test status
Simulation time 375088820 ps
CPU time 1.19 seconds
Started Jul 18 05:57:12 PM PDT 24
Finished Jul 18 05:57:17 PM PDT 24
Peak memory 196328 kb
Host smart-eb5c4818-d5b6-4ac9-9c4e-a374a54d4332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431621804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.431621804
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.593032180
Short name T146
Test name
Test status
Simulation time 457409096 ps
CPU time 0.77 seconds
Started Jul 18 05:57:16 PM PDT 24
Finished Jul 18 05:57:21 PM PDT 24
Peak memory 196320 kb
Host smart-e1f47f34-1ebe-414a-a4c2-b7309c068558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593032180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.593032180
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2403870817
Short name T107
Test name
Test status
Simulation time 490995413 ps
CPU time 1.53 seconds
Started Jul 18 05:57:33 PM PDT 24
Finished Jul 18 05:57:37 PM PDT 24
Peak memory 196416 kb
Host smart-9c5e1fdb-9646-44cc-ac00-c1407ff2e030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403870817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2403870817
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2550949987
Short name T145
Test name
Test status
Simulation time 107493879355 ps
CPU time 12.23 seconds
Started Jul 18 05:57:32 PM PDT 24
Finished Jul 18 05:57:47 PM PDT 24
Peak memory 197928 kb
Host smart-3ea098e6-a6c3-4399-9329-d0b157760afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550949987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2550949987
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1097175289
Short name T170
Test name
Test status
Simulation time 25129523227 ps
CPU time 273.34 seconds
Started Jul 18 05:57:01 PM PDT 24
Finished Jul 18 06:01:42 PM PDT 24
Peak memory 214664 kb
Host smart-cf651e5c-1890-4985-8a47-5ad85e55a82c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097175289 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1097175289
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.4057876005
Short name T3
Test name
Test status
Simulation time 530442945 ps
CPU time 1.28 seconds
Started Jul 18 05:57:09 PM PDT 24
Finished Jul 18 05:57:15 PM PDT 24
Peak memory 196376 kb
Host smart-57e3d69c-f95c-4563-9ee2-9f9adabd5d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057876005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.4057876005
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1925318897
Short name T147
Test name
Test status
Simulation time 28441861033 ps
CPU time 288.16 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 06:01:53 PM PDT 24
Peak memory 206480 kb
Host smart-6789d72e-4b08-4018-bf22-eacc2c630212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925318897 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1925318897
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.4080966529
Short name T118
Test name
Test status
Simulation time 535709082 ps
CPU time 0.99 seconds
Started Jul 18 05:57:29 PM PDT 24
Finished Jul 18 05:57:32 PM PDT 24
Peak memory 196620 kb
Host smart-0c0511c2-f575-4623-9357-7ea587296dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080966529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.4080966529
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2252699762
Short name T102
Test name
Test status
Simulation time 356624892 ps
CPU time 0.94 seconds
Started Jul 18 05:57:12 PM PDT 24
Finished Jul 18 05:57:16 PM PDT 24
Peak memory 196348 kb
Host smart-784369bb-cd78-4d7d-ad85-2ad9ac5a2f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252699762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2252699762
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2488279041
Short name T166
Test name
Test status
Simulation time 155001724875 ps
CPU time 58.88 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 05:58:21 PM PDT 24
Peak memory 191500 kb
Host smart-fefc68a0-7f23-41f2-b71a-dd64778aeb5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488279041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2488279041
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3696422564
Short name T143
Test name
Test status
Simulation time 152488662264 ps
CPU time 56.85 seconds
Started Jul 18 05:57:31 PM PDT 24
Finished Jul 18 05:58:30 PM PDT 24
Peak memory 197852 kb
Host smart-728eec65-e138-4e2a-a6aa-435e87947617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696422564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3696422564
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.332796762
Short name T111
Test name
Test status
Simulation time 48971939353 ps
CPU time 405.25 seconds
Started Jul 18 05:57:32 PM PDT 24
Finished Jul 18 06:04:19 PM PDT 24
Peak memory 206468 kb
Host smart-add5566b-67ab-45d0-8a15-b8497513ebaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332796762 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.332796762
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.632443835
Short name T171
Test name
Test status
Simulation time 623193635268 ps
CPU time 924.37 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 06:13:11 PM PDT 24
Peak memory 192592 kb
Host smart-bd1ef226-5b3c-472f-b0f5-e5ce85ff7196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632443835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.632443835
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.254191900
Short name T184
Test name
Test status
Simulation time 72231194009 ps
CPU time 55.98 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 191592 kb
Host smart-d16c2d7b-fe12-40d7-81c9-34c984f0f12c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254191900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.254191900
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2187173819
Short name T139
Test name
Test status
Simulation time 425820514 ps
CPU time 0.76 seconds
Started Jul 18 05:57:06 PM PDT 24
Finished Jul 18 05:57:13 PM PDT 24
Peak memory 196284 kb
Host smart-8c4f450c-06ba-4f22-b818-485394786895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187173819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2187173819
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3807149679
Short name T35
Test name
Test status
Simulation time 7950482492 ps
CPU time 11.36 seconds
Started Jul 18 05:57:46 PM PDT 24
Finished Jul 18 05:58:03 PM PDT 24
Peak memory 198636 kb
Host smart-eea5bf68-70a2-434f-b81c-b06580450b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807149679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3807149679
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1852873946
Short name T123
Test name
Test status
Simulation time 461214823 ps
CPU time 0.97 seconds
Started Jul 18 05:57:08 PM PDT 24
Finished Jul 18 05:57:14 PM PDT 24
Peak memory 196180 kb
Host smart-b8c1a79e-c4df-44a3-91cc-9b4337d4ec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852873946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1852873946
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3439506573
Short name T187
Test name
Test status
Simulation time 74354900913 ps
CPU time 54.52 seconds
Started Jul 18 05:57:32 PM PDT 24
Finished Jul 18 05:58:29 PM PDT 24
Peak memory 191500 kb
Host smart-ab08bbaf-8879-49ea-839a-bda3358dff20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439506573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3439506573
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1627367146
Short name T141
Test name
Test status
Simulation time 368747966 ps
CPU time 1.12 seconds
Started Jul 18 05:57:45 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 196380 kb
Host smart-a9a06503-8e7b-47b7-abaa-366ed4699849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627367146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1627367146
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3784831869
Short name T52
Test name
Test status
Simulation time 62965108538 ps
CPU time 621.7 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 06:07:27 PM PDT 24
Peak memory 206420 kb
Host smart-6852d668-d312-4085-96ce-62421dc89e00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784831869 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3784831869
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.954529366
Short name T116
Test name
Test status
Simulation time 532191939 ps
CPU time 1.31 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 05:57:09 PM PDT 24
Peak memory 196340 kb
Host smart-31cb280a-7102-4413-a37e-6b96f952c6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954529366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.954529366
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.751153011
Short name T160
Test name
Test status
Simulation time 525620727 ps
CPU time 1.34 seconds
Started Jul 18 05:57:16 PM PDT 24
Finished Jul 18 05:57:22 PM PDT 24
Peak memory 195716 kb
Host smart-99df57b2-4d54-4a12-90e6-100ea724952b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751153011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.751153011
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2821736157
Short name T53
Test name
Test status
Simulation time 37431308746 ps
CPU time 368.22 seconds
Started Jul 18 05:57:15 PM PDT 24
Finished Jul 18 06:03:27 PM PDT 24
Peak memory 213788 kb
Host smart-fba975c2-6794-4fed-924b-c6cc570ef6c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821736157 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2821736157
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4092618878
Short name T191
Test name
Test status
Simulation time 569477333 ps
CPU time 1.38 seconds
Started Jul 18 05:57:15 PM PDT 24
Finished Jul 18 05:57:21 PM PDT 24
Peak memory 196264 kb
Host smart-1ac7c534-07c3-457b-a13f-1665ae09dfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092618878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4092618878
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1757876511
Short name T177
Test name
Test status
Simulation time 414981065 ps
CPU time 1.2 seconds
Started Jul 18 05:57:14 PM PDT 24
Finished Jul 18 05:57:19 PM PDT 24
Peak memory 196260 kb
Host smart-450c8e4d-1fdd-40f0-a784-13b464f4fa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757876511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1757876511
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1138744985
Short name T108
Test name
Test status
Simulation time 536850337 ps
CPU time 1.05 seconds
Started Jul 18 05:57:47 PM PDT 24
Finished Jul 18 05:57:53 PM PDT 24
Peak memory 196040 kb
Host smart-68233ff2-0ffc-4c29-b23f-80665730de82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138744985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1138744985
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2102845045
Short name T62
Test name
Test status
Simulation time 434179441 ps
CPU time 0.85 seconds
Started Jul 18 05:57:04 PM PDT 24
Finished Jul 18 05:57:12 PM PDT 24
Peak memory 196280 kb
Host smart-88676340-969c-4414-a948-7009db6a07c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102845045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2102845045
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.4034284758
Short name T185
Test name
Test status
Simulation time 109936336101 ps
CPU time 344.98 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 06:02:52 PM PDT 24
Peak memory 210096 kb
Host smart-c2b50784-45b3-4dbd-a9d8-bb3bd4771482
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034284758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.4034284758
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2984111161
Short name T180
Test name
Test status
Simulation time 539459396 ps
CPU time 0.83 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:11 PM PDT 24
Peak memory 196360 kb
Host smart-d1aee74c-3095-4494-b269-9524230a0a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984111161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2984111161
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.121992567
Short name T183
Test name
Test status
Simulation time 16067625768 ps
CPU time 21.84 seconds
Started Jul 18 05:57:24 PM PDT 24
Finished Jul 18 05:57:47 PM PDT 24
Peak memory 191548 kb
Host smart-89c03aba-5764-462b-be5f-5fe2052ad2db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121992567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.121992567
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.4102012880
Short name T46
Test name
Test status
Simulation time 394192518 ps
CPU time 1.17 seconds
Started Jul 18 05:57:12 PM PDT 24
Finished Jul 18 05:57:17 PM PDT 24
Peak memory 196412 kb
Host smart-fcd6fd58-32cb-472d-9dea-b50ab9979c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102012880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.4102012880
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1053385198
Short name T49
Test name
Test status
Simulation time 495058587 ps
CPU time 0.94 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 05:57:23 PM PDT 24
Peak memory 196408 kb
Host smart-115b5de1-4c8d-4bb9-b480-9901062c86f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053385198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1053385198
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.205093773
Short name T7
Test name
Test status
Simulation time 481912985 ps
CPU time 0.99 seconds
Started Jul 18 05:57:31 PM PDT 24
Finished Jul 18 05:57:35 PM PDT 24
Peak memory 196264 kb
Host smart-1f039f2a-ba5f-431f-a9c5-37c76350d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205093773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.205093773
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.4151102887
Short name T167
Test name
Test status
Simulation time 499085874 ps
CPU time 0.95 seconds
Started Jul 18 05:57:39 PM PDT 24
Finished Jul 18 05:57:42 PM PDT 24
Peak memory 195336 kb
Host smart-c8e54e00-fc38-4104-a42e-05b2f4e100d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151102887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.4151102887
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.4000260197
Short name T69
Test name
Test status
Simulation time 460367551 ps
CPU time 1.39 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:05 PM PDT 24
Peak memory 196388 kb
Host smart-84078582-d48b-4c41-9d75-0fe5d6c556d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000260197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.4000260197
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3739644644
Short name T179
Test name
Test status
Simulation time 621462948 ps
CPU time 0.84 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 05:57:06 PM PDT 24
Peak memory 196280 kb
Host smart-fe30e85c-4fb7-439c-8711-fe007902b56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739644644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3739644644
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3139996120
Short name T189
Test name
Test status
Simulation time 12848317859 ps
CPU time 105.03 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 05:58:51 PM PDT 24
Peak memory 206532 kb
Host smart-446f6e7f-04a9-4d53-8845-2c05a420aa3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139996120 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3139996120
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2761371853
Short name T381
Test name
Test status
Simulation time 8530801785 ps
CPU time 3.73 seconds
Started Jul 18 05:57:54 PM PDT 24
Finished Jul 18 05:57:58 PM PDT 24
Peak memory 198684 kb
Host smart-9f294bc6-a617-4273-95de-5edb7e0c68ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761371853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2761371853
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3213434293
Short name T164
Test name
Test status
Simulation time 390488620 ps
CPU time 1.16 seconds
Started Jul 18 05:57:00 PM PDT 24
Finished Jul 18 05:57:10 PM PDT 24
Peak memory 196256 kb
Host smart-ce7b83a9-e13f-4eb9-9f97-21994178f343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213434293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3213434293
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3270308467
Short name T44
Test name
Test status
Simulation time 453622097 ps
CPU time 1.16 seconds
Started Jul 18 05:57:00 PM PDT 24
Finished Jul 18 05:57:09 PM PDT 24
Peak memory 196308 kb
Host smart-7855187c-8eb6-4350-adfb-3556126c070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270308467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3270308467
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2544812357
Short name T176
Test name
Test status
Simulation time 516083517 ps
CPU time 1.37 seconds
Started Jul 18 05:57:07 PM PDT 24
Finished Jul 18 05:57:14 PM PDT 24
Peak memory 196272 kb
Host smart-3178edfb-78f7-434a-8a81-cb28ce437776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544812357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2544812357
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3076491419
Short name T14
Test name
Test status
Simulation time 467638470 ps
CPU time 0.8 seconds
Started Jul 18 05:57:16 PM PDT 24
Finished Jul 18 05:57:21 PM PDT 24
Peak memory 195672 kb
Host smart-8bc17b0a-e0d6-43b1-9ec1-f298209e2f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076491419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3076491419
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3546489413
Short name T192
Test name
Test status
Simulation time 529703971 ps
CPU time 1.3 seconds
Started Jul 18 05:57:17 PM PDT 24
Finished Jul 18 05:57:22 PM PDT 24
Peak memory 196288 kb
Host smart-d18c82b4-10f1-4b6a-bf9c-6f06894c5487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546489413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3546489413
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.350523589
Short name T182
Test name
Test status
Simulation time 75173295894 ps
CPU time 423.5 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 06:04:26 PM PDT 24
Peak memory 213796 kb
Host smart-ad6edb8c-1f25-43f0-9281-c29d1f7a6e1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350523589 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.350523589
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4066055883
Short name T174
Test name
Test status
Simulation time 573684841 ps
CPU time 1.16 seconds
Started Jul 18 05:57:41 PM PDT 24
Finished Jul 18 05:57:45 PM PDT 24
Peak memory 196304 kb
Host smart-a92207ce-a954-419b-8bb2-f13d03a2b41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066055883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4066055883
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1445896331
Short name T57
Test name
Test status
Simulation time 434695912 ps
CPU time 1.5 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:49 PM PDT 24
Peak memory 194932 kb
Host smart-4fb95dfb-1f14-4abb-88f2-7ebc1f38a438
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445896331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1445896331
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1164980397
Short name T357
Test name
Test status
Simulation time 6998406253 ps
CPU time 2.74 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:57:47 PM PDT 24
Peak memory 196124 kb
Host smart-edb21f26-2ea4-4ada-af27-85b8b3029131
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164980397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1164980397
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1436730505
Short name T302
Test name
Test status
Simulation time 1065989891 ps
CPU time 1.06 seconds
Started Jul 18 05:57:46 PM PDT 24
Finished Jul 18 05:57:53 PM PDT 24
Peak memory 193352 kb
Host smart-6932d8e5-b6d1-4c8b-9172-7ab847c5ef95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436730505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1436730505
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3603054363
Short name T353
Test name
Test status
Simulation time 402026237 ps
CPU time 1.29 seconds
Started Jul 18 05:57:44 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 196448 kb
Host smart-64185443-6d6f-4a9d-8493-cbdbd889fdbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603054363 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3603054363
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2906046576
Short name T33
Test name
Test status
Simulation time 356923927 ps
CPU time 0.67 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:48 PM PDT 24
Peak memory 193596 kb
Host smart-ef75f051-bd18-407f-acd4-ebcacb151e14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906046576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2906046576
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3978907985
Short name T295
Test name
Test status
Simulation time 342985848 ps
CPU time 0.69 seconds
Started Jul 18 05:57:41 PM PDT 24
Finished Jul 18 05:57:44 PM PDT 24
Peak memory 184180 kb
Host smart-ca16b070-835e-42fe-b736-821c5834e3f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978907985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3978907985
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2431913265
Short name T392
Test name
Test status
Simulation time 516497324 ps
CPU time 0.71 seconds
Started Jul 18 05:57:36 PM PDT 24
Finished Jul 18 05:57:39 PM PDT 24
Peak memory 184104 kb
Host smart-4dc2e8c9-4fef-45c5-a3a4-4c371fdb28f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431913265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2431913265
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.633718690
Short name T413
Test name
Test status
Simulation time 420917466 ps
CPU time 0.83 seconds
Started Jul 18 05:57:47 PM PDT 24
Finished Jul 18 05:57:53 PM PDT 24
Peak memory 183916 kb
Host smart-7ea07e00-7766-47e1-adfc-40e22b747602
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633718690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.633718690
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3465265968
Short name T291
Test name
Test status
Simulation time 2570633460 ps
CPU time 6.49 seconds
Started Jul 18 05:59:22 PM PDT 24
Finished Jul 18 05:59:41 PM PDT 24
Peak memory 184360 kb
Host smart-a49d83ea-a548-458c-875a-25ac6a32cca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465265968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3465265968
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.934565586
Short name T290
Test name
Test status
Simulation time 336744481 ps
CPU time 1.75 seconds
Started Jul 18 05:57:44 PM PDT 24
Finished Jul 18 05:57:51 PM PDT 24
Peak memory 198976 kb
Host smart-2790b2f0-7fb3-4f23-aeeb-ad0a76017f79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934565586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.934565586
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1264122436
Short name T37
Test name
Test status
Simulation time 812768405 ps
CPU time 0.9 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:50 PM PDT 24
Peak memory 194204 kb
Host smart-d63f6e0a-6a18-413d-a914-f5386cc21497
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264122436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1264122436
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.156840649
Short name T203
Test name
Test status
Simulation time 7373120743 ps
CPU time 4.88 seconds
Started Jul 18 05:58:01 PM PDT 24
Finished Jul 18 05:58:15 PM PDT 24
Peak memory 192620 kb
Host smart-28d42e67-3bb7-4d0a-9f14-4b590ce272ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156840649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.156840649
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3798121
Short name T385
Test name
Test status
Simulation time 864109256 ps
CPU time 1.92 seconds
Started Jul 18 05:57:44 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 192496 kb
Host smart-d7e3c544-7735-49af-bbc2-13182a7fb85e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_r
eset.3798121
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3527886041
Short name T312
Test name
Test status
Simulation time 616242371 ps
CPU time 0.96 seconds
Started Jul 18 05:57:41 PM PDT 24
Finished Jul 18 05:57:45 PM PDT 24
Peak memory 197960 kb
Host smart-e2e42de3-13af-4082-995b-cd6b5d1f549f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527886041 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3527886041
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3753457887
Short name T362
Test name
Test status
Simulation time 440158918 ps
CPU time 1.22 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:49 PM PDT 24
Peak memory 193588 kb
Host smart-e3be9099-3de5-4de6-8fb1-cba484c10af7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753457887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3753457887
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.502126426
Short name T287
Test name
Test status
Simulation time 307932701 ps
CPU time 1.06 seconds
Started Jul 18 05:57:45 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 184160 kb
Host smart-807c9ab3-8a8c-4f98-8949-b9358eb62bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502126426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.502126426
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1823052578
Short name T280
Test name
Test status
Simulation time 450239263 ps
CPU time 0.91 seconds
Started Jul 18 05:57:45 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 184084 kb
Host smart-f5e20b26-9919-42cc-b57d-001b2631299b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823052578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1823052578
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3549569754
Short name T406
Test name
Test status
Simulation time 449056619 ps
CPU time 1.23 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:57:46 PM PDT 24
Peak memory 184104 kb
Host smart-1523e176-423d-4eb5-b19b-9df578af4dba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549569754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3549569754
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.732709700
Short name T78
Test name
Test status
Simulation time 1359393191 ps
CPU time 1.28 seconds
Started Jul 18 05:57:47 PM PDT 24
Finished Jul 18 05:57:53 PM PDT 24
Peak memory 194420 kb
Host smart-d9f38c5b-4542-4c28-9b76-0940b192e41c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732709700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.732709700
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.780527393
Short name T282
Test name
Test status
Simulation time 331353567 ps
CPU time 1.9 seconds
Started Jul 18 05:57:39 PM PDT 24
Finished Jul 18 05:57:43 PM PDT 24
Peak memory 199028 kb
Host smart-a20c636a-a4a5-4015-8370-f89f8f70c0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780527393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.780527393
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4212027529
Short name T366
Test name
Test status
Simulation time 9101300689 ps
CPU time 1.97 seconds
Started Jul 18 05:57:44 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 198412 kb
Host smart-11f31c96-e0b0-4954-b5a8-fc4f575b38b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212027529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.4212027529
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.865349189
Short name T351
Test name
Test status
Simulation time 447819337 ps
CPU time 0.79 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:09 PM PDT 24
Peak memory 196588 kb
Host smart-869e39f6-a4c1-4402-91e1-10033ee04648
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865349189 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.865349189
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3266515051
Short name T327
Test name
Test status
Simulation time 315747093 ps
CPU time 0.79 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:04 PM PDT 24
Peak memory 193416 kb
Host smart-a642d834-1aa2-4793-a521-0ae392e408e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266515051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3266515051
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2118038423
Short name T303
Test name
Test status
Simulation time 500862794 ps
CPU time 0.69 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:08 PM PDT 24
Peak memory 184204 kb
Host smart-d1ece834-5829-48b9-af36-dff5c14a09bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118038423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2118038423
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1882766257
Short name T345
Test name
Test status
Simulation time 3238703508 ps
CPU time 1.88 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:07 PM PDT 24
Peak memory 195668 kb
Host smart-e88956eb-5776-411a-949c-742c9000c3a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882766257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1882766257
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.222855237
Short name T314
Test name
Test status
Simulation time 449645021 ps
CPU time 2.32 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:05 PM PDT 24
Peak memory 199012 kb
Host smart-4dcf0769-df69-447f-84d1-d7626b19319a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222855237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.222855237
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2709039816
Short name T286
Test name
Test status
Simulation time 524200425 ps
CPU time 1.38 seconds
Started Jul 18 05:58:02 PM PDT 24
Finished Jul 18 05:58:13 PM PDT 24
Peak memory 196308 kb
Host smart-1535b51f-3fbc-4824-bf2c-00ecc0307ab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709039816 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2709039816
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.635625008
Short name T73
Test name
Test status
Simulation time 443509071 ps
CPU time 0.72 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:01 PM PDT 24
Peak memory 193424 kb
Host smart-51d50f01-ac5c-47ca-8957-d966626f2d67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635625008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.635625008
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4178469756
Short name T344
Test name
Test status
Simulation time 464075841 ps
CPU time 1.22 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:05 PM PDT 24
Peak memory 184112 kb
Host smart-c652819f-6050-45c4-9838-899bd5496d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178469756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4178469756
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.271911504
Short name T346
Test name
Test status
Simulation time 2665802617 ps
CPU time 2.43 seconds
Started Jul 18 05:57:56 PM PDT 24
Finished Jul 18 05:58:00 PM PDT 24
Peak memory 194296 kb
Host smart-19dcb48b-f9c2-4510-9f83-92f4a14622a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271911504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.271911504
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1948158167
Short name T292
Test name
Test status
Simulation time 1048202931 ps
CPU time 2.36 seconds
Started Jul 18 05:57:56 PM PDT 24
Finished Jul 18 05:58:00 PM PDT 24
Peak memory 198996 kb
Host smart-0916bf0c-17a8-419a-bd02-76c047ce2b53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948158167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1948158167
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.988647202
Short name T193
Test name
Test status
Simulation time 8139683409 ps
CPU time 10.97 seconds
Started Jul 18 05:57:55 PM PDT 24
Finished Jul 18 05:58:08 PM PDT 24
Peak memory 198736 kb
Host smart-9aa61dde-4167-4d64-9af8-67fc96a653c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988647202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.988647202
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2599103039
Short name T298
Test name
Test status
Simulation time 682945010 ps
CPU time 1.1 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:07 PM PDT 24
Peak memory 198792 kb
Host smart-c4c590bc-1ee2-497f-a2f4-3f6025d6cfad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599103039 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2599103039
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1666524499
Short name T367
Test name
Test status
Simulation time 431142647 ps
CPU time 1.18 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:09 PM PDT 24
Peak memory 193412 kb
Host smart-064eb9ab-1104-425c-b107-cebff650dcc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666524499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1666524499
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3146934246
Short name T373
Test name
Test status
Simulation time 436416719 ps
CPU time 1.05 seconds
Started Jul 18 05:57:55 PM PDT 24
Finished Jul 18 05:57:58 PM PDT 24
Peak memory 184200 kb
Host smart-7932c015-6127-4967-9dc7-5f92bd4c5b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146934246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3146934246
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2316844190
Short name T325
Test name
Test status
Simulation time 1455300629 ps
CPU time 1.28 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:01 PM PDT 24
Peak memory 192772 kb
Host smart-94294c39-4068-4024-a0d8-e26739b0a9a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316844190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2316844190
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3557240498
Short name T409
Test name
Test status
Simulation time 456256388 ps
CPU time 0.94 seconds
Started Jul 18 05:57:55 PM PDT 24
Finished Jul 18 05:57:57 PM PDT 24
Peak memory 197552 kb
Host smart-b13ac6ed-b385-4437-93f9-af3824bdfd4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557240498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3557240498
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.4005214608
Short name T403
Test name
Test status
Simulation time 7868272663 ps
CPU time 4.01 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:12 PM PDT 24
Peak memory 198788 kb
Host smart-f43386d6-49e9-4538-a21f-2faf7a291708
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005214608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.4005214608
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3739494493
Short name T377
Test name
Test status
Simulation time 375804334 ps
CPU time 1.15 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:01 PM PDT 24
Peak memory 196740 kb
Host smart-203e7c6e-4364-4c38-8e71-b5a55786dc07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739494493 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3739494493
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3104974426
Short name T384
Test name
Test status
Simulation time 382130893 ps
CPU time 0.78 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:01 PM PDT 24
Peak memory 193360 kb
Host smart-8032075f-0896-424a-a1d9-c8764802c073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104974426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3104974426
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2084444283
Short name T316
Test name
Test status
Simulation time 1278671078 ps
CPU time 2.72 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:03 PM PDT 24
Peak memory 184200 kb
Host smart-6e058a5d-d299-4476-b429-586ee06ad7d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084444283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2084444283
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.270922580
Short name T396
Test name
Test status
Simulation time 534081989 ps
CPU time 2.3 seconds
Started Jul 18 05:57:56 PM PDT 24
Finished Jul 18 05:57:59 PM PDT 24
Peak memory 199020 kb
Host smart-9af1b4bf-3992-469d-8e25-cf3b5a21302b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270922580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.270922580
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2869981686
Short name T394
Test name
Test status
Simulation time 7970815805 ps
CPU time 11.43 seconds
Started Jul 18 05:57:56 PM PDT 24
Finished Jul 18 05:58:09 PM PDT 24
Peak memory 198628 kb
Host smart-be2ac995-668d-45e3-a0e2-83ccf8d8d240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869981686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2869981686
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3037276357
Short name T326
Test name
Test status
Simulation time 417317462 ps
CPU time 1.17 seconds
Started Jul 18 05:57:56 PM PDT 24
Finished Jul 18 05:57:58 PM PDT 24
Peak memory 198856 kb
Host smart-0549401c-a52c-4013-8042-6d9ffba87194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037276357 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3037276357
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1123711202
Short name T77
Test name
Test status
Simulation time 368730447 ps
CPU time 0.67 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:02 PM PDT 24
Peak memory 192472 kb
Host smart-e76365a0-5884-4204-a0ee-292bd22f0f8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123711202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1123711202
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.88380137
Short name T405
Test name
Test status
Simulation time 452624188 ps
CPU time 1.14 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:09 PM PDT 24
Peak memory 184396 kb
Host smart-69762fff-6d1c-41e2-8784-32571455b3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88380137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.88380137
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2356410308
Short name T382
Test name
Test status
Simulation time 1709243145 ps
CPU time 4.6 seconds
Started Jul 18 05:58:07 PM PDT 24
Finished Jul 18 05:58:21 PM PDT 24
Peak memory 193416 kb
Host smart-5509523c-073d-48c2-b314-85a117a0a5d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356410308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2356410308
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2952022581
Short name T399
Test name
Test status
Simulation time 421700551 ps
CPU time 2.18 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:02 PM PDT 24
Peak memory 198888 kb
Host smart-d40a84dc-9aa1-4846-9b0e-44aef0c5ccf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952022581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2952022581
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4272612259
Short name T197
Test name
Test status
Simulation time 8679611883 ps
CPU time 2.71 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 198912 kb
Host smart-cf9f0ef3-dffb-41bf-9151-bb3e94d9e823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272612259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4272612259
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2219614588
Short name T354
Test name
Test status
Simulation time 584384256 ps
CPU time 1.1 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:05 PM PDT 24
Peak memory 198800 kb
Host smart-e0d63dc0-6241-43d4-9c17-1902c016b828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219614588 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2219614588
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3081959624
Short name T75
Test name
Test status
Simulation time 405188617 ps
CPU time 1.17 seconds
Started Jul 18 05:58:07 PM PDT 24
Finished Jul 18 05:58:18 PM PDT 24
Peak memory 193512 kb
Host smart-cef8840d-3895-4eb2-a94d-4fc8666fdcc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081959624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3081959624
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3620550265
Short name T378
Test name
Test status
Simulation time 365570166 ps
CPU time 0.72 seconds
Started Jul 18 05:58:07 PM PDT 24
Finished Jul 18 05:58:17 PM PDT 24
Peak memory 184200 kb
Host smart-ae7d4696-1df3-4a55-939e-4ba12f61c98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620550265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3620550265
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.190534574
Short name T311
Test name
Test status
Simulation time 2482804391 ps
CPU time 1.88 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 193284 kb
Host smart-d74ce71a-ba25-4c22-b973-e68b284f87dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190534574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.190534574
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.112023631
Short name T416
Test name
Test status
Simulation time 379075263 ps
CPU time 1.17 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 198832 kb
Host smart-928849f9-a12a-45bb-958e-9b654ad9e350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112023631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.112023631
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2547596558
Short name T305
Test name
Test status
Simulation time 4173027967 ps
CPU time 5.91 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:11 PM PDT 24
Peak memory 197852 kb
Host smart-a4f35f74-20c7-4fe7-aae1-aad567a317d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547596558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2547596558
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2000369485
Short name T415
Test name
Test status
Simulation time 525764517 ps
CPU time 0.95 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 196308 kb
Host smart-a71cce78-b798-438c-95f6-f581d2f01bf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000369485 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2000369485
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.673387144
Short name T55
Test name
Test status
Simulation time 516397148 ps
CPU time 0.8 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 193756 kb
Host smart-28c084e5-4eea-4b3f-a7dd-4647e071fd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673387144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.673387144
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3127045351
Short name T309
Test name
Test status
Simulation time 434988601 ps
CPU time 1.11 seconds
Started Jul 18 05:58:01 PM PDT 24
Finished Jul 18 05:58:12 PM PDT 24
Peak memory 193424 kb
Host smart-8cee3e96-a6ac-4280-a71c-d4a50726658e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127045351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3127045351
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.986064136
Short name T397
Test name
Test status
Simulation time 1594874519 ps
CPU time 2.68 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:12 PM PDT 24
Peak memory 194432 kb
Host smart-a6bf6306-e87f-45cf-8b80-c67dad115cae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986064136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.986064136
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2893872678
Short name T369
Test name
Test status
Simulation time 710350726 ps
CPU time 1.71 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:06 PM PDT 24
Peak memory 198672 kb
Host smart-e9b31bfd-dfb6-47cc-9241-2a61ef79d49e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893872678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2893872678
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4214354648
Short name T386
Test name
Test status
Simulation time 4212169431 ps
CPU time 7.55 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:15 PM PDT 24
Peak memory 198124 kb
Host smart-78712afd-e3f4-4dc3-86df-0b97f8f07e71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214354648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.4214354648
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4230214818
Short name T407
Test name
Test status
Simulation time 449825618 ps
CPU time 1.14 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:11 PM PDT 24
Peak memory 196652 kb
Host smart-bad0ec34-4b61-4895-ab29-6a70a6ef06f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230214818 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4230214818
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2525217104
Short name T60
Test name
Test status
Simulation time 375114753 ps
CPU time 0.69 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 193504 kb
Host smart-337076a9-694c-46fe-b9ad-53d5ce2c3974
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525217104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2525217104
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1022424506
Short name T319
Test name
Test status
Simulation time 387679484 ps
CPU time 0.73 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:11 PM PDT 24
Peak memory 184140 kb
Host smart-b66cee8b-3584-45cf-801c-ef0c0fca7c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022424506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1022424506
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3435637875
Short name T389
Test name
Test status
Simulation time 2354592028 ps
CPU time 3.67 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:12 PM PDT 24
Peak memory 194456 kb
Host smart-392d0d69-20f1-4431-a70f-072d5efd68b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435637875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3435637875
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2962325737
Short name T372
Test name
Test status
Simulation time 417654588 ps
CPU time 1.32 seconds
Started Jul 18 05:58:01 PM PDT 24
Finished Jul 18 05:58:12 PM PDT 24
Peak memory 198944 kb
Host smart-82925205-2389-4414-a435-e3f973c52c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962325737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2962325737
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2833139306
Short name T194
Test name
Test status
Simulation time 4426053403 ps
CPU time 2.09 seconds
Started Jul 18 05:58:17 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 197360 kb
Host smart-73b77070-f5ac-4666-a895-8d059deea1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833139306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2833139306
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2648780909
Short name T341
Test name
Test status
Simulation time 388574340 ps
CPU time 1.21 seconds
Started Jul 18 05:58:04 PM PDT 24
Finished Jul 18 05:58:15 PM PDT 24
Peak memory 196064 kb
Host smart-aa71fe28-2e1b-462b-b57a-6be8c14a47ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648780909 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2648780909
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3492659123
Short name T339
Test name
Test status
Simulation time 495844903 ps
CPU time 0.86 seconds
Started Jul 18 05:58:02 PM PDT 24
Finished Jul 18 05:58:13 PM PDT 24
Peak memory 193640 kb
Host smart-a435651d-5b9e-4f83-91a6-dcf263942520
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492659123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3492659123
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.192518061
Short name T307
Test name
Test status
Simulation time 333435844 ps
CPU time 1.03 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:09 PM PDT 24
Peak memory 184252 kb
Host smart-a8d3a37f-22b9-4460-b735-30464eaefdeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192518061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.192518061
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.630506226
Short name T38
Test name
Test status
Simulation time 1136302992 ps
CPU time 0.86 seconds
Started Jul 18 05:58:04 PM PDT 24
Finished Jul 18 05:58:14 PM PDT 24
Peak memory 194392 kb
Host smart-c44297b8-31df-4ec6-85e4-3ffc00e79c92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630506226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.630506226
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2689047692
Short name T398
Test name
Test status
Simulation time 499754786 ps
CPU time 1.77 seconds
Started Jul 18 05:58:02 PM PDT 24
Finished Jul 18 05:58:14 PM PDT 24
Peak memory 199016 kb
Host smart-d7f0d529-bfd7-4a06-8436-5c26d2fa666c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689047692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2689047692
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1908956059
Short name T352
Test name
Test status
Simulation time 4436329296 ps
CPU time 7.71 seconds
Started Jul 18 05:58:02 PM PDT 24
Finished Jul 18 05:58:20 PM PDT 24
Peak memory 198668 kb
Host smart-78d9c1e9-9af6-4ed8-af3a-530cd4d9ca60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908956059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1908956059
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4165665745
Short name T347
Test name
Test status
Simulation time 562239335 ps
CPU time 1.08 seconds
Started Jul 18 05:58:05 PM PDT 24
Finished Jul 18 05:58:16 PM PDT 24
Peak memory 196260 kb
Host smart-6f9eb173-49e1-4e4f-8fcb-1f9356b9b2a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165665745 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4165665745
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1065493975
Short name T393
Test name
Test status
Simulation time 409963936 ps
CPU time 0.79 seconds
Started Jul 18 05:58:04 PM PDT 24
Finished Jul 18 05:58:14 PM PDT 24
Peak memory 193768 kb
Host smart-e3a8fcf6-08b5-4446-b843-adbaf3e5788b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065493975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1065493975
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.445241647
Short name T361
Test name
Test status
Simulation time 437897359 ps
CPU time 1.19 seconds
Started Jul 18 05:58:04 PM PDT 24
Finished Jul 18 05:58:14 PM PDT 24
Peak memory 193368 kb
Host smart-81dd9c76-fd8e-48ec-ae9f-87cedfc68758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445241647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.445241647
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.288806003
Short name T379
Test name
Test status
Simulation time 1179081884 ps
CPU time 0.9 seconds
Started Jul 18 05:58:05 PM PDT 24
Finished Jul 18 05:58:16 PM PDT 24
Peak memory 193648 kb
Host smart-d4f974a2-3d80-444e-8095-f01e7ed1cc43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288806003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.288806003
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2761777778
Short name T390
Test name
Test status
Simulation time 1189525596 ps
CPU time 2.22 seconds
Started Jul 18 05:58:01 PM PDT 24
Finished Jul 18 05:58:13 PM PDT 24
Peak memory 199032 kb
Host smart-59e1b778-511b-4287-937f-6334001f30e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761777778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2761777778
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4033480928
Short name T408
Test name
Test status
Simulation time 8306958174 ps
CPU time 12.91 seconds
Started Jul 18 05:58:02 PM PDT 24
Finished Jul 18 05:58:25 PM PDT 24
Peak memory 198756 kb
Host smart-47551fd9-803f-4d6a-9ecc-12fa55f6ecc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033480928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.4033480928
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2639251525
Short name T418
Test name
Test status
Simulation time 491607252 ps
CPU time 1.35 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:50 PM PDT 24
Peak memory 194416 kb
Host smart-753b75cb-8040-4b0f-a6c6-911f01afda45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639251525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2639251525
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.414400764
Short name T72
Test name
Test status
Simulation time 11803828079 ps
CPU time 23.43 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:58:11 PM PDT 24
Peak memory 196464 kb
Host smart-41ebb01f-e736-46c3-a3af-15ba7bbf2594
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414400764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.414400764
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.179333351
Short name T421
Test name
Test status
Simulation time 855049025 ps
CPU time 1.84 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:57:46 PM PDT 24
Peak memory 193612 kb
Host smart-2f742544-e303-4929-8fa9-9b554d0f995d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179333351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.179333351
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1682925523
Short name T308
Test name
Test status
Simulation time 469000426 ps
CPU time 1.1 seconds
Started Jul 18 05:57:44 PM PDT 24
Finished Jul 18 05:57:51 PM PDT 24
Peak memory 196908 kb
Host smart-0acfab6b-17bb-4d1f-adda-d9f990708714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682925523 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1682925523
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1735657191
Short name T289
Test name
Test status
Simulation time 495637410 ps
CPU time 1.35 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:57:47 PM PDT 24
Peak memory 193828 kb
Host smart-51db0e78-9438-41a2-8f0d-29871077fd3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735657191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1735657191
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3743389066
Short name T388
Test name
Test status
Simulation time 454776892 ps
CPU time 0.86 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:57:47 PM PDT 24
Peak memory 193420 kb
Host smart-e58112eb-fec7-45b5-a581-33d23066c778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743389066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3743389066
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3501513637
Short name T299
Test name
Test status
Simulation time 402969157 ps
CPU time 0.61 seconds
Started Jul 18 05:57:47 PM PDT 24
Finished Jul 18 05:57:53 PM PDT 24
Peak memory 184000 kb
Host smart-b050c944-a39b-4ea8-9d7d-1d63c8628995
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501513637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3501513637
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1970564424
Short name T288
Test name
Test status
Simulation time 295415570 ps
CPU time 0.71 seconds
Started Jul 18 05:57:45 PM PDT 24
Finished Jul 18 05:57:51 PM PDT 24
Peak memory 184076 kb
Host smart-edb634c7-3d8b-49ca-a6b6-baabdd7a7bd8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970564424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1970564424
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.1365875892
Short name T79
Test name
Test status
Simulation time 1127845541 ps
CPU time 0.98 seconds
Started Jul 18 05:57:40 PM PDT 24
Finished Jul 18 05:57:43 PM PDT 24
Peak memory 193416 kb
Host smart-aba01226-bfb5-4d09-8449-58064d92726d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365875892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.1365875892
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1157588441
Short name T412
Test name
Test status
Simulation time 840473313 ps
CPU time 2.38 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:51 PM PDT 24
Peak memory 199060 kb
Host smart-9f21f187-0587-448f-8944-4af3b4f8fc26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157588441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1157588441
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1974958950
Short name T419
Test name
Test status
Simulation time 7739124216 ps
CPU time 10.66 seconds
Started Jul 18 05:57:41 PM PDT 24
Finished Jul 18 05:57:53 PM PDT 24
Peak memory 198640 kb
Host smart-9fdb19f4-2c58-4b3a-9156-4799f71c10f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974958950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1974958950
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2634640132
Short name T332
Test name
Test status
Simulation time 393703873 ps
CPU time 0.59 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:08 PM PDT 24
Peak memory 184204 kb
Host smart-be2c9b64-f70b-49f3-8a66-f212866308b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634640132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2634640132
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.35263201
Short name T350
Test name
Test status
Simulation time 489798905 ps
CPU time 0.87 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:07 PM PDT 24
Peak memory 184144 kb
Host smart-7299a07e-c62f-4a7d-8bad-da1cb82c3ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35263201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.35263201
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2588766013
Short name T279
Test name
Test status
Simulation time 297780575 ps
CPU time 0.92 seconds
Started Jul 18 05:58:03 PM PDT 24
Finished Jul 18 05:58:13 PM PDT 24
Peak memory 184148 kb
Host smart-5db498fe-3c12-4309-a5d8-5c4e37e07fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588766013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2588766013
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2009046787
Short name T297
Test name
Test status
Simulation time 325974567 ps
CPU time 1.04 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:08 PM PDT 24
Peak memory 193424 kb
Host smart-0d460ad4-a165-46fb-acd2-6a6f089c4ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009046787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2009046787
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.558452014
Short name T300
Test name
Test status
Simulation time 312755137 ps
CPU time 0.88 seconds
Started Jul 18 05:58:01 PM PDT 24
Finished Jul 18 05:58:11 PM PDT 24
Peak memory 184148 kb
Host smart-e5a4c3b7-21cb-4e8c-8516-47644ade8fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558452014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.558452014
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.186534191
Short name T328
Test name
Test status
Simulation time 500838115 ps
CPU time 1.24 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:06 PM PDT 24
Peak memory 184204 kb
Host smart-795eb1a0-f0eb-4c28-84a4-d77895048b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186534191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.186534191
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3014811738
Short name T383
Test name
Test status
Simulation time 409565074 ps
CPU time 0.74 seconds
Started Jul 18 05:58:04 PM PDT 24
Finished Jul 18 05:58:14 PM PDT 24
Peak memory 184140 kb
Host smart-0d7dc27e-0d76-48c5-8c69-1744c667ade4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014811738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3014811738
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3716265853
Short name T401
Test name
Test status
Simulation time 340185242 ps
CPU time 0.99 seconds
Started Jul 18 05:58:05 PM PDT 24
Finished Jul 18 05:58:16 PM PDT 24
Peak memory 184140 kb
Host smart-c7476465-671d-4694-b03d-fe92f1369694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716265853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3716265853
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2067633560
Short name T360
Test name
Test status
Simulation time 483901608 ps
CPU time 0.87 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:03 PM PDT 24
Peak memory 184188 kb
Host smart-49f240c9-ebfa-4eb5-88dc-81f4ac16c8f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067633560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2067633560
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3023664832
Short name T310
Test name
Test status
Simulation time 580325052 ps
CPU time 0.57 seconds
Started Jul 18 05:58:06 PM PDT 24
Finished Jul 18 05:58:17 PM PDT 24
Peak memory 184200 kb
Host smart-53ea6f35-ba1c-4a49-a242-2ebe02e34af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023664832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3023664832
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2303642694
Short name T59
Test name
Test status
Simulation time 432753233 ps
CPU time 1.12 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:57:48 PM PDT 24
Peak memory 194676 kb
Host smart-64b001ea-204c-4997-96d3-54ac776232e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303642694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2303642694
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.442443808
Short name T284
Test name
Test status
Simulation time 7437419005 ps
CPU time 2.48 seconds
Started Jul 18 05:57:46 PM PDT 24
Finished Jul 18 05:57:54 PM PDT 24
Peak memory 192572 kb
Host smart-dd22e81e-9865-4aa0-b6e2-c6f8bf3e1416
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442443808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.442443808
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.283616647
Short name T318
Test name
Test status
Simulation time 705023877 ps
CPU time 1.07 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:49 PM PDT 24
Peak memory 184180 kb
Host smart-37667d89-210f-41b5-af17-142880ec7789
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283616647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.283616647
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2428804791
Short name T293
Test name
Test status
Simulation time 566020376 ps
CPU time 1.18 seconds
Started Jul 18 05:57:46 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 198808 kb
Host smart-42059720-c2ff-4887-ad52-d66c49bc5c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428804791 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2428804791
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.645333299
Short name T74
Test name
Test status
Simulation time 384764516 ps
CPU time 1.09 seconds
Started Jul 18 05:57:39 PM PDT 24
Finished Jul 18 05:57:42 PM PDT 24
Peak memory 193364 kb
Host smart-a915ddee-ebe6-4271-b091-ff76a7305c75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645333299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.645333299
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4772252
Short name T411
Test name
Test status
Simulation time 296810963 ps
CPU time 0.73 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:49 PM PDT 24
Peak memory 184212 kb
Host smart-76485661-d2bd-49ac-b77e-dc3dbe17ff8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4772252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4772252
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1436671012
Short name T340
Test name
Test status
Simulation time 332629551 ps
CPU time 1.03 seconds
Started Jul 18 05:57:46 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 184116 kb
Host smart-55a5d0d2-6166-49a1-a2ba-b769fb8b1dec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436671012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1436671012
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2543189037
Short name T404
Test name
Test status
Simulation time 400286941 ps
CPU time 0.7 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:49 PM PDT 24
Peak memory 184124 kb
Host smart-4cbd6d0d-75f7-42c2-97b5-c4a5f144415d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543189037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2543189037
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1653832153
Short name T323
Test name
Test status
Simulation time 1395373228 ps
CPU time 1.39 seconds
Started Jul 18 05:57:46 PM PDT 24
Finished Jul 18 05:57:53 PM PDT 24
Peak memory 193880 kb
Host smart-a6538f2f-3e7a-4d61-a2d5-aced651bde2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653832153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1653832153
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3603231811
Short name T376
Test name
Test status
Simulation time 487720929 ps
CPU time 1.41 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:50 PM PDT 24
Peak memory 198412 kb
Host smart-1160c6f4-9dd3-40fd-8478-76097333276f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603231811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3603231811
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.972967704
Short name T36
Test name
Test status
Simulation time 4538209767 ps
CPU time 3.59 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 198220 kb
Host smart-211fa1ec-f57c-44df-8718-abdeba7c3a46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972967704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.972967704
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2499338618
Short name T334
Test name
Test status
Simulation time 463796125 ps
CPU time 1.26 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:06 PM PDT 24
Peak memory 193416 kb
Host smart-28502a4a-bc28-44ce-a172-b1e38562597d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499338618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2499338618
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3568778916
Short name T336
Test name
Test status
Simulation time 450377227 ps
CPU time 0.76 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:11 PM PDT 24
Peak memory 193416 kb
Host smart-352f921e-626c-4f5b-839b-a9b5a750f699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568778916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3568778916
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3135606270
Short name T315
Test name
Test status
Simulation time 408724955 ps
CPU time 0.68 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:05 PM PDT 24
Peak memory 193420 kb
Host smart-7b95ee5b-83e8-4f22-9e25-b1a2e925646a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135606270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3135606270
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.863592644
Short name T375
Test name
Test status
Simulation time 348950184 ps
CPU time 0.92 seconds
Started Jul 18 05:58:05 PM PDT 24
Finished Jul 18 05:58:16 PM PDT 24
Peak memory 184192 kb
Host smart-86cf13ee-712e-4283-8438-a4c815e088f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863592644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.863592644
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2929948960
Short name T283
Test name
Test status
Simulation time 340974612 ps
CPU time 1.05 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 193412 kb
Host smart-75032d7f-59c2-43f3-a9f6-3d2ae7c11a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929948960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2929948960
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2418135084
Short name T331
Test name
Test status
Simulation time 488499248 ps
CPU time 0.72 seconds
Started Jul 18 05:57:49 PM PDT 24
Finished Jul 18 05:57:54 PM PDT 24
Peak memory 184204 kb
Host smart-002a4de5-84f2-410c-a53c-2692e0fd6fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418135084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2418135084
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3885340255
Short name T395
Test name
Test status
Simulation time 341693616 ps
CPU time 0.81 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:06 PM PDT 24
Peak memory 184200 kb
Host smart-91e21bba-864c-4248-8544-90835b2e1f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885340255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3885340255
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2427801829
Short name T338
Test name
Test status
Simulation time 417626862 ps
CPU time 0.65 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 184196 kb
Host smart-3b19e5d9-0192-4646-aefc-cf8d4f2dfd3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427801829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2427801829
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.381483428
Short name T321
Test name
Test status
Simulation time 523256943 ps
CPU time 0.93 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:05 PM PDT 24
Peak memory 184192 kb
Host smart-cb42f214-1dee-44b9-9ab0-99757b575e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381483428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.381483428
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3317749453
Short name T342
Test name
Test status
Simulation time 478948280 ps
CPU time 0.87 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:06 PM PDT 24
Peak memory 184156 kb
Host smart-3abe489a-b210-408b-adbc-01763442aca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317749453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3317749453
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.620990206
Short name T56
Test name
Test status
Simulation time 566066058 ps
CPU time 1.44 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:05 PM PDT 24
Peak memory 184184 kb
Host smart-edbd4f57-b0cd-4eb9-9467-d3218080ceb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620990206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.620990206
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1605054986
Short name T70
Test name
Test status
Simulation time 14110501083 ps
CPU time 6.15 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:14 PM PDT 24
Peak memory 192492 kb
Host smart-a3371ee8-249c-4ca9-be53-4685e32d8ea3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605054986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1605054986
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.548163975
Short name T301
Test name
Test status
Simulation time 1275053356 ps
CPU time 2.49 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 193400 kb
Host smart-e5f18d97-e9cc-48ed-8723-a7912cd0b643
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548163975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.548163975
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.197136228
Short name T365
Test name
Test status
Simulation time 407464988 ps
CPU time 0.82 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:08 PM PDT 24
Peak memory 197496 kb
Host smart-1acbf098-8d40-403a-90d5-58c44aeaea93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197136228 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.197136228
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2831523201
Short name T71
Test name
Test status
Simulation time 385993266 ps
CPU time 0.84 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:01 PM PDT 24
Peak memory 193432 kb
Host smart-ae6d9376-5960-4eb2-ba5e-62a5a2e1c173
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831523201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2831523201
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.307661820
Short name T329
Test name
Test status
Simulation time 321588395 ps
CPU time 0.68 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:06 PM PDT 24
Peak memory 184148 kb
Host smart-07fe869d-cc3d-4449-82b1-4e9cdfdb0a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307661820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.307661820
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3820608045
Short name T355
Test name
Test status
Simulation time 376048884 ps
CPU time 1.1 seconds
Started Jul 18 05:57:55 PM PDT 24
Finished Jul 18 05:57:58 PM PDT 24
Peak memory 184132 kb
Host smart-b449e5a6-6097-4c19-a76e-4d156e3af3fa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820608045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3820608045
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2781293818
Short name T324
Test name
Test status
Simulation time 297671388 ps
CPU time 0.63 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:08 PM PDT 24
Peak memory 183248 kb
Host smart-fccb6ddb-faa4-48fb-a0cd-a619150bddd3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781293818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2781293818
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2831847359
Short name T335
Test name
Test status
Simulation time 2432208574 ps
CPU time 5 seconds
Started Jul 18 05:57:54 PM PDT 24
Finished Jul 18 05:58:00 PM PDT 24
Peak memory 194556 kb
Host smart-eb6b05b1-b93a-41f0-b6dd-e41174e52333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831847359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2831847359
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2915414106
Short name T420
Test name
Test status
Simulation time 535652913 ps
CPU time 2.25 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:57:47 PM PDT 24
Peak memory 199228 kb
Host smart-8d57b19c-2d24-4d10-b57f-9ab53aa8e5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915414106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2915414106
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3694010451
Short name T359
Test name
Test status
Simulation time 8410132573 ps
CPU time 1.83 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:49 PM PDT 24
Peak memory 198692 kb
Host smart-8614f1af-fbcc-459f-8b4f-165cb03c3bad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694010451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3694010451
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2556115445
Short name T320
Test name
Test status
Simulation time 366627031 ps
CPU time 0.69 seconds
Started Jul 18 05:58:15 PM PDT 24
Finished Jul 18 05:58:22 PM PDT 24
Peak memory 193352 kb
Host smart-792215e6-e114-4ad9-aacc-c9129e657a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556115445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2556115445
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1317833860
Short name T371
Test name
Test status
Simulation time 502261860 ps
CPU time 0.7 seconds
Started Jul 18 05:58:14 PM PDT 24
Finished Jul 18 05:58:21 PM PDT 24
Peak memory 184168 kb
Host smart-b64e0f4d-d378-4b2e-9e92-c44b236daa96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317833860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1317833860
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3934872946
Short name T370
Test name
Test status
Simulation time 470383424 ps
CPU time 1.17 seconds
Started Jul 18 05:58:18 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 184200 kb
Host smart-ea45991b-4673-4e80-b2ce-b755ec1eb331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934872946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3934872946
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2666980530
Short name T402
Test name
Test status
Simulation time 450098525 ps
CPU time 0.73 seconds
Started Jul 18 05:58:19 PM PDT 24
Finished Jul 18 05:58:25 PM PDT 24
Peak memory 193412 kb
Host smart-53963448-0157-47c9-b1ce-35e72d95e7eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666980530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2666980530
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1937074624
Short name T387
Test name
Test status
Simulation time 296159869 ps
CPU time 0.93 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:31 PM PDT 24
Peak memory 193428 kb
Host smart-81324556-320a-4a77-9169-7771e8c67b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937074624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1937074624
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1676723542
Short name T356
Test name
Test status
Simulation time 431302072 ps
CPU time 0.83 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:36 PM PDT 24
Peak memory 193416 kb
Host smart-8ecc24a6-abbb-4730-b881-c893d42bd2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676723542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1676723542
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2224365999
Short name T281
Test name
Test status
Simulation time 434003523 ps
CPU time 0.68 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:28 PM PDT 24
Peak memory 184140 kb
Host smart-7098563b-f2c3-450d-8242-4cdbc9bc0a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224365999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2224365999
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3004107422
Short name T363
Test name
Test status
Simulation time 341106580 ps
CPU time 0.75 seconds
Started Jul 18 05:58:12 PM PDT 24
Finished Jul 18 05:58:20 PM PDT 24
Peak memory 184204 kb
Host smart-c45f06a6-a736-4028-a9e6-5b77a89e1db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004107422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3004107422
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4013188585
Short name T330
Test name
Test status
Simulation time 418904306 ps
CPU time 0.91 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:30 PM PDT 24
Peak memory 184140 kb
Host smart-041452fe-2c3c-469a-88c6-8539a10aecb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013188585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.4013188585
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2691620504
Short name T343
Test name
Test status
Simulation time 331541570 ps
CPU time 0.6 seconds
Started Jul 18 05:58:13 PM PDT 24
Finished Jul 18 05:58:21 PM PDT 24
Peak memory 184188 kb
Host smart-fdd855eb-3f5c-4877-a849-a4e47fb7eeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691620504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2691620504
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4287604222
Short name T296
Test name
Test status
Simulation time 495414692 ps
CPU time 1.01 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:01 PM PDT 24
Peak memory 198768 kb
Host smart-4bfc2997-3076-4e61-be68-030145fa05b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287604222 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.4287604222
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.4100769619
Short name T58
Test name
Test status
Simulation time 391816322 ps
CPU time 0.68 seconds
Started Jul 18 05:58:18 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 192484 kb
Host smart-06bb0ab4-60a3-4dc4-bf2a-65a5baa33096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100769619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.4100769619
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1016450289
Short name T333
Test name
Test status
Simulation time 326194613 ps
CPU time 1.05 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 184160 kb
Host smart-ef036fd1-4624-44df-aabe-3f5608ba4487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016450289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1016450289
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1378449236
Short name T417
Test name
Test status
Simulation time 2373547018 ps
CPU time 1.06 seconds
Started Jul 18 05:58:05 PM PDT 24
Finished Jul 18 05:58:16 PM PDT 24
Peak memory 195108 kb
Host smart-c6671b29-cc6c-4d1b-8948-a901df679499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378449236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1378449236
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3727893614
Short name T414
Test name
Test status
Simulation time 724180313 ps
CPU time 2.07 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 198964 kb
Host smart-c3bb415e-d684-40ae-a716-ec536a3b65b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727893614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3727893614
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1646414423
Short name T317
Test name
Test status
Simulation time 539476013 ps
CPU time 1.44 seconds
Started Jul 18 05:57:56 PM PDT 24
Finished Jul 18 05:57:59 PM PDT 24
Peak memory 196912 kb
Host smart-6e33d8a8-7444-4b4b-8b05-9e6a4d4950bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646414423 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1646414423
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.259694535
Short name T76
Test name
Test status
Simulation time 393179830 ps
CPU time 1.2 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:08 PM PDT 24
Peak memory 193416 kb
Host smart-c5e30a1b-95bf-4b30-bdf9-1596695287bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259694535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.259694535
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1622800599
Short name T374
Test name
Test status
Simulation time 335629615 ps
CPU time 0.62 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:00 PM PDT 24
Peak memory 182748 kb
Host smart-e97bb0ea-95cf-4368-bd9a-182b85c8af43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622800599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1622800599
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2605086072
Short name T380
Test name
Test status
Simulation time 1212747192 ps
CPU time 0.71 seconds
Started Jul 18 05:58:01 PM PDT 24
Finished Jul 18 05:58:12 PM PDT 24
Peak memory 193728 kb
Host smart-37ea110e-b3dc-4523-ba8f-69cc2ee12324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605086072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2605086072
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2080281302
Short name T349
Test name
Test status
Simulation time 508872974 ps
CPU time 2.12 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:06 PM PDT 24
Peak memory 199036 kb
Host smart-8dca9aae-b8e6-4f3d-a431-39ae86c2fc71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080281302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2080281302
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.571964076
Short name T410
Test name
Test status
Simulation time 8039998999 ps
CPU time 3.94 seconds
Started Jul 18 05:57:57 PM PDT 24
Finished Jul 18 05:58:05 PM PDT 24
Peak memory 198584 kb
Host smart-024526b4-cf32-4167-b41d-6de911498416
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571964076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.571964076
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1447970651
Short name T294
Test name
Test status
Simulation time 630281931 ps
CPU time 0.91 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:03 PM PDT 24
Peak memory 196984 kb
Host smart-fdc27349-4c76-4dfa-90ec-aee579cff448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447970651 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1447970651
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2752428685
Short name T81
Test name
Test status
Simulation time 517609899 ps
CPU time 0.96 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:03 PM PDT 24
Peak memory 192428 kb
Host smart-05ff56c3-d1de-4c7c-9d50-9ab8c0adb9c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752428685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2752428685
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3848352635
Short name T368
Test name
Test status
Simulation time 264237588 ps
CPU time 0.89 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:09 PM PDT 24
Peak memory 184056 kb
Host smart-e5e8df34-d665-42ef-b9b5-441b4630f218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848352635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3848352635
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.553138407
Short name T80
Test name
Test status
Simulation time 1041042278 ps
CPU time 1.09 seconds
Started Jul 18 05:58:01 PM PDT 24
Finished Jul 18 05:58:12 PM PDT 24
Peak memory 193424 kb
Host smart-ee328357-6803-47a2-a120-a06b492e7c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553138407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.553138407
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.724297185
Short name T337
Test name
Test status
Simulation time 452215035 ps
CPU time 1.71 seconds
Started Jul 18 05:58:02 PM PDT 24
Finished Jul 18 05:58:13 PM PDT 24
Peak memory 198760 kb
Host smart-5170fc39-ffd7-4eda-b351-fc714dff9ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724297185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.724297185
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2837030200
Short name T313
Test name
Test status
Simulation time 4369016014 ps
CPU time 4.03 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:10 PM PDT 24
Peak memory 198244 kb
Host smart-78c16b74-53c7-4e70-9c79-ff76cd7d3fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837030200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2837030200
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2864196410
Short name T400
Test name
Test status
Simulation time 568542170 ps
CPU time 0.78 seconds
Started Jul 18 05:57:55 PM PDT 24
Finished Jul 18 05:57:57 PM PDT 24
Peak memory 198044 kb
Host smart-13a1baa7-9f47-4050-97d3-01adcdc0a396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864196410 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2864196410
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2211320055
Short name T304
Test name
Test status
Simulation time 687268359 ps
CPU time 0.63 seconds
Started Jul 18 05:58:05 PM PDT 24
Finished Jul 18 05:58:15 PM PDT 24
Peak memory 193624 kb
Host smart-99a70699-19ce-46e5-b1df-30dbe37c4342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211320055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2211320055
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.953951439
Short name T358
Test name
Test status
Simulation time 467059001 ps
CPU time 0.68 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:09 PM PDT 24
Peak memory 184208 kb
Host smart-a4f6aed4-a778-4dcd-9984-5575a6f6fdaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953951439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.953951439
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3245448917
Short name T391
Test name
Test status
Simulation time 2525945390 ps
CPU time 1.06 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:05 PM PDT 24
Peak memory 195468 kb
Host smart-ec91d241-2ea4-4308-a10e-69086b4978cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245448917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3245448917
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.30719062
Short name T322
Test name
Test status
Simulation time 543631559 ps
CPU time 1.29 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:03 PM PDT 24
Peak memory 198836 kb
Host smart-c6942f9a-f8da-4b9d-9b36-79bd4d2f05da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30719062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.30719062
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1450589383
Short name T195
Test name
Test status
Simulation time 8303956541 ps
CPU time 13.19 seconds
Started Jul 18 05:57:59 PM PDT 24
Finished Jul 18 05:58:21 PM PDT 24
Peak memory 198528 kb
Host smart-bf451e69-f883-4d31-897a-9c7cb0329e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450589383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1450589383
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1368395915
Short name T348
Test name
Test status
Simulation time 443712178 ps
CPU time 0.98 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:04 PM PDT 24
Peak memory 196544 kb
Host smart-c0d6d181-af87-48f9-a675-e2e2ccade31a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368395915 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1368395915
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3614323879
Short name T306
Test name
Test status
Simulation time 478190052 ps
CPU time 1.23 seconds
Started Jul 18 05:57:55 PM PDT 24
Finished Jul 18 05:57:58 PM PDT 24
Peak memory 193404 kb
Host smart-2539aa4d-05b6-40c6-b940-6287b7f84a85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614323879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3614323879
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.4075436261
Short name T285
Test name
Test status
Simulation time 371058922 ps
CPU time 1.03 seconds
Started Jul 18 05:57:55 PM PDT 24
Finished Jul 18 05:57:57 PM PDT 24
Peak memory 184168 kb
Host smart-578ad65f-fba0-413d-abae-10c1c63708d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075436261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.4075436261
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2706963944
Short name T31
Test name
Test status
Simulation time 1167587574 ps
CPU time 3.55 seconds
Started Jul 18 05:58:00 PM PDT 24
Finished Jul 18 05:58:13 PM PDT 24
Peak memory 184148 kb
Host smart-cdb6221e-f563-43ba-911b-48e6b538c703
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706963944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2706963944
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2003655737
Short name T364
Test name
Test status
Simulation time 429950563 ps
CPU time 2.01 seconds
Started Jul 18 05:57:54 PM PDT 24
Finished Jul 18 05:57:57 PM PDT 24
Peak memory 199004 kb
Host smart-9923be89-78e0-4997-9dbe-78728255f8df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003655737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2003655737
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3267299018
Short name T196
Test name
Test status
Simulation time 8111656087 ps
CPU time 13.15 seconds
Started Jul 18 05:57:58 PM PDT 24
Finished Jul 18 05:58:15 PM PDT 24
Peak memory 198656 kb
Host smart-3085955e-3fb4-4e78-8482-0c571b2c24d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267299018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3267299018
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.52423432
Short name T5
Test name
Test status
Simulation time 22104507185 ps
CPU time 7.66 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:11 PM PDT 24
Peak memory 196548 kb
Host smart-3f7545c3-e420-435f-8f3d-5dab9cf5fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52423432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.52423432
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2466644485
Short name T206
Test name
Test status
Simulation time 597761170 ps
CPU time 1 seconds
Started Jul 18 05:57:01 PM PDT 24
Finished Jul 18 05:57:10 PM PDT 24
Peak memory 191476 kb
Host smart-e8a610db-8f77-4135-9fee-ce45a5663153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466644485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2466644485
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3451315357
Short name T274
Test name
Test status
Simulation time 15143648399 ps
CPU time 4.13 seconds
Started Jul 18 05:57:01 PM PDT 24
Finished Jul 18 05:57:13 PM PDT 24
Peak memory 196536 kb
Host smart-1acc2434-fd78-4709-b170-031914e59881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451315357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3451315357
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3631601380
Short name T4
Test name
Test status
Simulation time 7797086951 ps
CPU time 3.89 seconds
Started Jul 18 05:56:53 PM PDT 24
Finished Jul 18 05:57:04 PM PDT 24
Peak memory 215488 kb
Host smart-205f4885-5f13-48d8-9e26-ae1706d5221e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631601380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3631601380
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2226955325
Short name T207
Test name
Test status
Simulation time 569979068 ps
CPU time 1.46 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:05 PM PDT 24
Peak memory 196352 kb
Host smart-a431ba47-8148-4510-b5d5-d2d891140c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226955325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2226955325
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3083180852
Short name T267
Test name
Test status
Simulation time 12731686879 ps
CPU time 11.89 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:23 PM PDT 24
Peak memory 190720 kb
Host smart-369b709d-bf9a-491c-8cdc-97acb150856a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083180852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3083180852
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.4195694056
Short name T265
Test name
Test status
Simulation time 617261564 ps
CPU time 0.8 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:11 PM PDT 24
Peak memory 191468 kb
Host smart-3a1b3aa1-c797-4726-a812-1ebb2f08a1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195694056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.4195694056
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.432489017
Short name T251
Test name
Test status
Simulation time 24106464479 ps
CPU time 34.18 seconds
Started Jul 18 05:57:05 PM PDT 24
Finished Jul 18 05:57:46 PM PDT 24
Peak memory 191508 kb
Host smart-555b34e3-a0a6-49ba-94ce-d9eb8dfe69bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432489017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.432489017
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2992160073
Short name T222
Test name
Test status
Simulation time 557538596 ps
CPU time 1.45 seconds
Started Jul 18 05:57:04 PM PDT 24
Finished Jul 18 05:57:13 PM PDT 24
Peak memory 196316 kb
Host smart-64655b72-2239-4d66-adcf-af1defcf7196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992160073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2992160073
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1446934563
Short name T200
Test name
Test status
Simulation time 3846723245 ps
CPU time 3.49 seconds
Started Jul 18 05:57:08 PM PDT 24
Finished Jul 18 05:57:16 PM PDT 24
Peak memory 196148 kb
Host smart-2c5828d5-2aad-41a1-aa92-7d5c123eac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446934563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1446934563
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3917515208
Short name T255
Test name
Test status
Simulation time 413151717 ps
CPU time 0.73 seconds
Started Jul 18 05:57:06 PM PDT 24
Finished Jul 18 05:57:13 PM PDT 24
Peak memory 191456 kb
Host smart-e0e3c2e7-bee2-413b-bb20-a9ed96b2d295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917515208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3917515208
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1098006699
Short name T172
Test name
Test status
Simulation time 131803559157 ps
CPU time 193.2 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 06:00:24 PM PDT 24
Peak memory 192664 kb
Host smart-9332d750-53b9-4d05-85e0-cbd3564d399b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098006699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1098006699
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2086092266
Short name T242
Test name
Test status
Simulation time 23190138491 ps
CPU time 14.41 seconds
Started Jul 18 05:57:08 PM PDT 24
Finished Jul 18 05:57:28 PM PDT 24
Peak memory 196532 kb
Host smart-e5b78d6c-aab6-40d7-bba0-68c65ebc7e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086092266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2086092266
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2102696038
Short name T259
Test name
Test status
Simulation time 434112607 ps
CPU time 1.21 seconds
Started Jul 18 05:57:01 PM PDT 24
Finished Jul 18 05:57:10 PM PDT 24
Peak memory 196348 kb
Host smart-dd730589-f6eb-45f4-a438-10b80b8d87d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102696038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2102696038
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2758822469
Short name T16
Test name
Test status
Simulation time 6039146517 ps
CPU time 5.09 seconds
Started Jul 18 05:57:07 PM PDT 24
Finished Jul 18 05:57:18 PM PDT 24
Peak memory 196540 kb
Host smart-8191312e-c38a-4b56-8cb9-4f8e857a181f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758822469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2758822469
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1955635955
Short name T61
Test name
Test status
Simulation time 391804836 ps
CPU time 0.72 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:11 PM PDT 24
Peak memory 191476 kb
Host smart-773aaadb-d9ca-480d-b9d5-4dfa0c2b56b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955635955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1955635955
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1733983474
Short name T261
Test name
Test status
Simulation time 50749387904 ps
CPU time 11.73 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:22 PM PDT 24
Peak memory 191568 kb
Host smart-cd08edfc-a272-4936-93eb-8c77a6bed2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733983474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1733983474
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2787916100
Short name T241
Test name
Test status
Simulation time 456030387 ps
CPU time 0.98 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 05:57:08 PM PDT 24
Peak memory 196356 kb
Host smart-24258df4-0f26-45ed-b276-b2c955e96b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787916100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2787916100
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3302394460
Short name T63
Test name
Test status
Simulation time 9483206195 ps
CPU time 9.95 seconds
Started Jul 18 05:57:04 PM PDT 24
Finished Jul 18 05:57:21 PM PDT 24
Peak memory 191528 kb
Host smart-03a0de59-507e-45fc-b941-58f68ca8d594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302394460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3302394460
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3451032962
Short name T277
Test name
Test status
Simulation time 460638199 ps
CPU time 0.91 seconds
Started Jul 18 05:57:07 PM PDT 24
Finished Jul 18 05:57:13 PM PDT 24
Peak memory 196324 kb
Host smart-17a19457-8305-46c6-abcf-3d2dc1fc870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451032962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3451032962
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_jump.4181641445
Short name T51
Test name
Test status
Simulation time 564341617 ps
CPU time 0.79 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:05 PM PDT 24
Peak memory 196356 kb
Host smart-f65be23c-90bc-4584-bd36-bba887fdc3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181641445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.4181641445
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3538346463
Short name T252
Test name
Test status
Simulation time 31840209495 ps
CPU time 42.31 seconds
Started Jul 18 05:57:01 PM PDT 24
Finished Jul 18 05:57:51 PM PDT 24
Peak memory 196548 kb
Host smart-44b07aab-532a-4c90-a940-cc3250e2872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538346463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3538346463
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4023564824
Short name T263
Test name
Test status
Simulation time 617344057 ps
CPU time 1 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:05 PM PDT 24
Peak memory 191496 kb
Host smart-b32444b0-83e5-4d0e-b0eb-a485c76f3b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023564824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4023564824
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.385026975
Short name T199
Test name
Test status
Simulation time 2454259928 ps
CPU time 2.42 seconds
Started Jul 18 05:57:00 PM PDT 24
Finished Jul 18 05:57:10 PM PDT 24
Peak memory 191564 kb
Host smart-2c6d1428-7fb6-4bcf-835f-cfbded6b58e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385026975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.385026975
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3502696498
Short name T234
Test name
Test status
Simulation time 653666905 ps
CPU time 0.76 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 05:57:07 PM PDT 24
Peak memory 191504 kb
Host smart-aa8d78db-022d-4871-9810-5dba282bcdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502696498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3502696498
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.4165086784
Short name T238
Test name
Test status
Simulation time 13527969917 ps
CPU time 5.24 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:16 PM PDT 24
Peak memory 196552 kb
Host smart-2d223e02-e1c5-4694-bd9f-b83bd747646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165086784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4165086784
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2086587312
Short name T273
Test name
Test status
Simulation time 506069155 ps
CPU time 1.16 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:05 PM PDT 24
Peak memory 196304 kb
Host smart-147cc1bc-1022-40ed-b081-89e8db60882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086587312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2086587312
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3467482119
Short name T247
Test name
Test status
Simulation time 48610208656 ps
CPU time 25.35 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:29 PM PDT 24
Peak memory 196496 kb
Host smart-147bae11-5829-4687-8558-666976fe459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467482119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3467482119
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.104519591
Short name T26
Test name
Test status
Simulation time 4080072029 ps
CPU time 3.87 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:14 PM PDT 24
Peak memory 215184 kb
Host smart-d2ffc9b6-d484-4147-a1b2-28ef49069d79
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104519591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.104519591
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2788181315
Short name T210
Test name
Test status
Simulation time 611339275 ps
CPU time 0.64 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 05:57:06 PM PDT 24
Peak memory 191476 kb
Host smart-199dc8f8-ed9c-4725-9f03-d002928bc622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788181315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2788181315
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2291029816
Short name T65
Test name
Test status
Simulation time 1533437601 ps
CPU time 1.15 seconds
Started Jul 18 05:57:11 PM PDT 24
Finished Jul 18 05:57:16 PM PDT 24
Peak memory 191504 kb
Host smart-e045ef66-1ec6-4c56-8d3a-7e4909088bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291029816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2291029816
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3818231061
Short name T231
Test name
Test status
Simulation time 378077953 ps
CPU time 0.83 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 05:57:07 PM PDT 24
Peak memory 191452 kb
Host smart-3878b6a7-0b52-4670-894c-2025fa90f2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818231061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3818231061
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.311793579
Short name T175
Test name
Test status
Simulation time 409251964 ps
CPU time 0.71 seconds
Started Jul 18 05:57:13 PM PDT 24
Finished Jul 18 05:57:18 PM PDT 24
Peak memory 196376 kb
Host smart-962ea97a-e594-4a96-a3cb-51d503002753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311793579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.311793579
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2840876666
Short name T227
Test name
Test status
Simulation time 60007137161 ps
CPU time 95.56 seconds
Started Jul 18 05:57:15 PM PDT 24
Finished Jul 18 05:58:54 PM PDT 24
Peak memory 191540 kb
Host smart-6346011b-a5c7-4d1c-8a29-93e595711884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840876666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2840876666
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.926916556
Short name T212
Test name
Test status
Simulation time 598074983 ps
CPU time 0.79 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 05:57:23 PM PDT 24
Peak memory 196360 kb
Host smart-72fca093-6e8c-4bc2-9706-29ba7657cc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926916556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.926916556
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2540590354
Short name T8
Test name
Test status
Simulation time 7007286352 ps
CPU time 6.29 seconds
Started Jul 18 05:57:29 PM PDT 24
Finished Jul 18 05:57:38 PM PDT 24
Peak memory 191556 kb
Host smart-a0fd5bf8-5577-431a-891c-bd3d4ded1d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540590354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2540590354
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4255849289
Short name T18
Test name
Test status
Simulation time 482811259 ps
CPU time 1.27 seconds
Started Jul 18 05:57:31 PM PDT 24
Finished Jul 18 05:57:34 PM PDT 24
Peak memory 191524 kb
Host smart-223d0111-4fcb-4152-80e4-b3948b05928b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255849289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4255849289
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.41928036
Short name T239
Test name
Test status
Simulation time 10268120288 ps
CPU time 17.11 seconds
Started Jul 18 05:57:15 PM PDT 24
Finished Jul 18 05:57:36 PM PDT 24
Peak memory 196544 kb
Host smart-6d9208ec-12fe-482e-87e3-0653db886435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41928036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.41928036
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3564282471
Short name T270
Test name
Test status
Simulation time 374859205 ps
CPU time 1.12 seconds
Started Jul 18 05:57:31 PM PDT 24
Finished Jul 18 05:57:35 PM PDT 24
Peak memory 196308 kb
Host smart-25f307b8-2690-4593-85ca-6727fd1e9d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564282471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3564282471
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2731339199
Short name T228
Test name
Test status
Simulation time 29008350092 ps
CPU time 43.68 seconds
Started Jul 18 05:57:32 PM PDT 24
Finished Jul 18 05:58:18 PM PDT 24
Peak memory 191508 kb
Host smart-4d8fb0ab-7812-4c21-9bb5-d02f01597055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731339199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2731339199
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2105823050
Short name T232
Test name
Test status
Simulation time 582260260 ps
CPU time 1.47 seconds
Started Jul 18 05:57:30 PM PDT 24
Finished Jul 18 05:57:33 PM PDT 24
Peak memory 191548 kb
Host smart-3b91969b-a77b-427b-b2e5-105b17cbf103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105823050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2105823050
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3078105137
Short name T169
Test name
Test status
Simulation time 533185654 ps
CPU time 0.77 seconds
Started Jul 18 05:57:25 PM PDT 24
Finished Jul 18 05:57:27 PM PDT 24
Peak memory 196280 kb
Host smart-0fe3f338-da78-4431-8511-50f62494db5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078105137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3078105137
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1799343726
Short name T236
Test name
Test status
Simulation time 17788194713 ps
CPU time 5.49 seconds
Started Jul 18 05:57:16 PM PDT 24
Finished Jul 18 05:57:25 PM PDT 24
Peak memory 196540 kb
Host smart-5851e98a-150e-4281-bae7-82311f107ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799343726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1799343726
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3318808393
Short name T10
Test name
Test status
Simulation time 625817450 ps
CPU time 0.8 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 05:57:23 PM PDT 24
Peak memory 191484 kb
Host smart-4fd8e8e3-6a50-4390-a0c4-0ea8418c3368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318808393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3318808393
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.984178034
Short name T64
Test name
Test status
Simulation time 43642313310 ps
CPU time 15.21 seconds
Started Jul 18 05:57:24 PM PDT 24
Finished Jul 18 05:57:40 PM PDT 24
Peak memory 196572 kb
Host smart-5eaa01a6-2554-430e-9bd5-ff0e3a7e4ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984178034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.984178034
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.633598654
Short name T218
Test name
Test status
Simulation time 429406437 ps
CPU time 0.78 seconds
Started Jul 18 05:57:26 PM PDT 24
Finished Jul 18 05:57:28 PM PDT 24
Peak memory 191452 kb
Host smart-b460fcdd-2e91-4949-bea8-90ea41516479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633598654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.633598654
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.58964237
Short name T272
Test name
Test status
Simulation time 28947221852 ps
CPU time 10.44 seconds
Started Jul 18 05:57:29 PM PDT 24
Finished Jul 18 05:57:41 PM PDT 24
Peak memory 196528 kb
Host smart-03f686a8-b0de-4a05-9365-e7b6fb8754c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58964237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.58964237
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2416460947
Short name T48
Test name
Test status
Simulation time 516697116 ps
CPU time 0.92 seconds
Started Jul 18 05:57:12 PM PDT 24
Finished Jul 18 05:57:17 PM PDT 24
Peak memory 196356 kb
Host smart-720d0c27-3abd-4b2d-baad-08b33399a6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416460947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2416460947
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2901084246
Short name T220
Test name
Test status
Simulation time 1577598952 ps
CPU time 0.94 seconds
Started Jul 18 05:57:25 PM PDT 24
Finished Jul 18 05:57:27 PM PDT 24
Peak memory 191464 kb
Host smart-e9d1c7cd-d898-4403-98bb-ffc7deb69506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901084246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2901084246
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.996118502
Short name T205
Test name
Test status
Simulation time 480962463 ps
CPU time 1.32 seconds
Started Jul 18 05:57:29 PM PDT 24
Finished Jul 18 05:57:32 PM PDT 24
Peak memory 191536 kb
Host smart-2e4d7939-4097-4db7-a027-13f018b5731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996118502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.996118502
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1567237989
Short name T6
Test name
Test status
Simulation time 46493020013 ps
CPU time 61.63 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 191536 kb
Host smart-b50c3fbb-f3e1-4f65-8f9b-6f75f3d1e268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567237989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1567237989
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1044220776
Short name T235
Test name
Test status
Simulation time 379476897 ps
CPU time 0.85 seconds
Started Jul 18 05:57:22 PM PDT 24
Finished Jul 18 05:57:25 PM PDT 24
Peak memory 191696 kb
Host smart-2e475f30-4c6c-44bb-8c0c-edd9a0dbca72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044220776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1044220776
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2100732518
Short name T276
Test name
Test status
Simulation time 38277936000 ps
CPU time 310.97 seconds
Started Jul 18 05:57:18 PM PDT 24
Finished Jul 18 06:02:32 PM PDT 24
Peak memory 213892 kb
Host smart-e88f91d0-1e36-4006-8556-2cd6598e6be0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100732518 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2100732518
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3762535750
Short name T47
Test name
Test status
Simulation time 50521647147 ps
CPU time 63.4 seconds
Started Jul 18 05:57:02 PM PDT 24
Finished Jul 18 05:58:14 PM PDT 24
Peak memory 191528 kb
Host smart-50c48090-7959-4929-b0b2-bb96eb691bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762535750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3762535750
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.509560581
Short name T25
Test name
Test status
Simulation time 7461854996 ps
CPU time 3.68 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:08 PM PDT 24
Peak memory 215584 kb
Host smart-f2540eca-bf3a-435b-a4ae-e27b43d8b854
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509560581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.509560581
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2811782635
Short name T216
Test name
Test status
Simulation time 479880666 ps
CPU time 1.16 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:05 PM PDT 24
Peak memory 191496 kb
Host smart-785720e3-1d8c-4984-854b-603ce6c94c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811782635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2811782635
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.559215095
Short name T201
Test name
Test status
Simulation time 10665832950 ps
CPU time 4.95 seconds
Started Jul 18 05:57:26 PM PDT 24
Finished Jul 18 05:57:32 PM PDT 24
Peak memory 196544 kb
Host smart-0cc9de66-4e71-4c0a-861f-94cef18dcf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559215095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.559215095
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1063042486
Short name T257
Test name
Test status
Simulation time 432257058 ps
CPU time 0.73 seconds
Started Jul 18 05:57:14 PM PDT 24
Finished Jul 18 05:57:18 PM PDT 24
Peak memory 196348 kb
Host smart-71c78014-18e9-4c4e-96b5-a2fc53892e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063042486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1063042486
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1807272872
Short name T211
Test name
Test status
Simulation time 41240750722 ps
CPU time 23.96 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 05:57:46 PM PDT 24
Peak memory 191540 kb
Host smart-0268ab1f-3cf7-435b-aec2-fc8ad8e345b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807272872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1807272872
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4171681861
Short name T204
Test name
Test status
Simulation time 513957051 ps
CPU time 1.44 seconds
Started Jul 18 05:57:27 PM PDT 24
Finished Jul 18 05:57:29 PM PDT 24
Peak memory 191472 kb
Host smart-2f0c88d6-a50c-4994-9b06-e9953c0574ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171681861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4171681861
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1398773038
Short name T13
Test name
Test status
Simulation time 368893985 ps
CPU time 1.1 seconds
Started Jul 18 05:57:15 PM PDT 24
Finished Jul 18 05:57:20 PM PDT 24
Peak memory 196272 kb
Host smart-f6e080d4-14d1-4b8a-80c5-55fd02aaf5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398773038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1398773038
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2370741302
Short name T233
Test name
Test status
Simulation time 30209377095 ps
CPU time 20.65 seconds
Started Jul 18 05:57:31 PM PDT 24
Finished Jul 18 05:57:54 PM PDT 24
Peak memory 191556 kb
Host smart-8b27143c-1d35-4ba5-93e2-b337b0b18552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370741302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2370741302
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2909661120
Short name T244
Test name
Test status
Simulation time 391952344 ps
CPU time 0.71 seconds
Started Jul 18 05:57:30 PM PDT 24
Finished Jul 18 05:57:32 PM PDT 24
Peak memory 191452 kb
Host smart-65d26fa3-198b-4e6c-b4d0-0f8a192daafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909661120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2909661120
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.941643450
Short name T45
Test name
Test status
Simulation time 46245218870 ps
CPU time 25.16 seconds
Started Jul 18 05:57:17 PM PDT 24
Finished Jul 18 05:57:46 PM PDT 24
Peak memory 196584 kb
Host smart-02182439-bdf8-4f71-a57e-8acd8d36423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941643450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.941643450
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.4113458159
Short name T209
Test name
Test status
Simulation time 557703146 ps
CPU time 1.49 seconds
Started Jul 18 05:57:22 PM PDT 24
Finished Jul 18 05:57:25 PM PDT 24
Peak memory 191452 kb
Host smart-ef8ac433-3b00-4263-bad6-2c18e7450d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113458159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.4113458159
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.819359313
Short name T162
Test name
Test status
Simulation time 467503821 ps
CPU time 1.24 seconds
Started Jul 18 05:57:29 PM PDT 24
Finished Jul 18 05:57:33 PM PDT 24
Peak memory 196480 kb
Host smart-643d9f4c-93ed-4860-8dfc-81ee07b8f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819359313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.819359313
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.4278445208
Short name T224
Test name
Test status
Simulation time 7637027143 ps
CPU time 3.4 seconds
Started Jul 18 05:57:33 PM PDT 24
Finished Jul 18 05:57:39 PM PDT 24
Peak memory 191504 kb
Host smart-a7a88b9f-3a47-40af-a173-84615b8b8e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278445208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.4278445208
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3446734286
Short name T221
Test name
Test status
Simulation time 505805143 ps
CPU time 0.97 seconds
Started Jul 18 05:57:17 PM PDT 24
Finished Jul 18 05:57:22 PM PDT 24
Peak memory 196352 kb
Host smart-512b63a5-31a2-442e-b6a9-f64ad3af9c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446734286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3446734286
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2741223082
Short name T214
Test name
Test status
Simulation time 37009415754 ps
CPU time 20.15 seconds
Started Jul 18 05:57:19 PM PDT 24
Finished Jul 18 05:57:42 PM PDT 24
Peak memory 191552 kb
Host smart-afe0724c-3456-43c6-9e63-4f271776a42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741223082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2741223082
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3192024941
Short name T245
Test name
Test status
Simulation time 550268419 ps
CPU time 0.77 seconds
Started Jul 18 05:57:28 PM PDT 24
Finished Jul 18 05:57:31 PM PDT 24
Peak memory 191500 kb
Host smart-8c1cb56f-3cf8-4e6d-9515-3cb5aee3cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192024941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3192024941
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3203601668
Short name T278
Test name
Test status
Simulation time 54690802815 ps
CPU time 19.54 seconds
Started Jul 18 05:57:34 PM PDT 24
Finished Jul 18 05:57:55 PM PDT 24
Peak memory 191556 kb
Host smart-5a158748-8423-4fb1-8566-a2dec4e94481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203601668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3203601668
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1426297650
Short name T230
Test name
Test status
Simulation time 595040469 ps
CPU time 1.56 seconds
Started Jul 18 05:57:28 PM PDT 24
Finished Jul 18 05:57:31 PM PDT 24
Peak memory 196360 kb
Host smart-18af99d1-b053-4ab6-94aa-b3d4bae3bbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426297650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1426297650
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2761256349
Short name T17
Test name
Test status
Simulation time 52400979972 ps
CPU time 8.05 seconds
Started Jul 18 05:57:27 PM PDT 24
Finished Jul 18 05:57:36 PM PDT 24
Peak memory 196552 kb
Host smart-7601ced7-c820-44fc-9ec5-76235ecd45a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761256349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2761256349
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1574466030
Short name T208
Test name
Test status
Simulation time 611293406 ps
CPU time 1.01 seconds
Started Jul 18 05:57:16 PM PDT 24
Finished Jul 18 05:57:21 PM PDT 24
Peak memory 191416 kb
Host smart-ef36d493-f4d5-4573-9a7b-371fe7c11c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574466030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1574466030
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2535866805
Short name T165
Test name
Test status
Simulation time 630769089 ps
CPU time 1.55 seconds
Started Jul 18 05:57:36 PM PDT 24
Finished Jul 18 05:57:39 PM PDT 24
Peak memory 196364 kb
Host smart-7d2397d9-2016-4915-85b9-d094c102d9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535866805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2535866805
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.787224557
Short name T67
Test name
Test status
Simulation time 37930327556 ps
CPU time 55.34 seconds
Started Jul 18 05:57:33 PM PDT 24
Finished Jul 18 05:58:30 PM PDT 24
Peak memory 196572 kb
Host smart-baf09b8a-9b2c-4f09-99f6-d76c19c85e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787224557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.787224557
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3550878332
Short name T269
Test name
Test status
Simulation time 409982565 ps
CPU time 0.73 seconds
Started Jul 18 05:57:31 PM PDT 24
Finished Jul 18 05:57:35 PM PDT 24
Peak memory 191500 kb
Host smart-496d10a1-7103-48b3-965e-0e58343814f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550878332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3550878332
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.574630324
Short name T9
Test name
Test status
Simulation time 30223056422 ps
CPU time 41.79 seconds
Started Jul 18 05:57:36 PM PDT 24
Finished Jul 18 05:58:19 PM PDT 24
Peak memory 196592 kb
Host smart-e5e1f106-c5dd-406c-bcb4-e38a617522f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574630324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.574630324
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1990024870
Short name T248
Test name
Test status
Simulation time 402521479 ps
CPU time 0.73 seconds
Started Jul 18 05:57:34 PM PDT 24
Finished Jul 18 05:57:37 PM PDT 24
Peak memory 191504 kb
Host smart-c43237a6-5a14-4dfa-8d68-a4f91052df39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990024870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1990024870
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2224332209
Short name T215
Test name
Test status
Simulation time 17104819795 ps
CPU time 10.2 seconds
Started Jul 18 05:56:54 PM PDT 24
Finished Jul 18 05:57:11 PM PDT 24
Peak memory 191532 kb
Host smart-ac7eeac2-b2ac-4aed-a743-2ba2c5a508e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224332209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2224332209
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.971309925
Short name T21
Test name
Test status
Simulation time 7760230663 ps
CPU time 2.32 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:05 PM PDT 24
Peak memory 215492 kb
Host smart-9342b552-a91a-4e09-bfb7-79ccbe8a7567
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971309925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.971309925
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3135600076
Short name T266
Test name
Test status
Simulation time 373416283 ps
CPU time 1.17 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:04 PM PDT 24
Peak memory 196312 kb
Host smart-7438f8fc-e558-4359-adcc-6119feb80253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135600076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3135600076
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4100727675
Short name T168
Test name
Test status
Simulation time 582941438 ps
CPU time 1 seconds
Started Jul 18 05:57:34 PM PDT 24
Finished Jul 18 05:57:37 PM PDT 24
Peak memory 196280 kb
Host smart-31824f57-0525-44da-8307-18e952cf498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100727675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4100727675
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.485198026
Short name T258
Test name
Test status
Simulation time 27017117041 ps
CPU time 22.16 seconds
Started Jul 18 05:57:39 PM PDT 24
Finished Jul 18 05:58:03 PM PDT 24
Peak memory 191520 kb
Host smart-eed9b9aa-e891-40dd-bd48-b52cab43e6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485198026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.485198026
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1607171156
Short name T275
Test name
Test status
Simulation time 512119906 ps
CPU time 0.95 seconds
Started Jul 18 05:57:37 PM PDT 24
Finished Jul 18 05:57:39 PM PDT 24
Peak memory 191496 kb
Host smart-bc2a9ea2-75de-4428-aef3-bf7eacb31fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607171156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1607171156
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1246310033
Short name T181
Test name
Test status
Simulation time 396075930 ps
CPU time 0.87 seconds
Started Jul 18 05:57:40 PM PDT 24
Finished Jul 18 05:57:43 PM PDT 24
Peak memory 196308 kb
Host smart-7fdc23b3-b341-4b9d-bc32-5c36ed425c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246310033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1246310033
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2650535953
Short name T213
Test name
Test status
Simulation time 6797279798 ps
CPU time 9.94 seconds
Started Jul 18 05:57:39 PM PDT 24
Finished Jul 18 05:57:51 PM PDT 24
Peak memory 191560 kb
Host smart-91ca9f92-88ec-4f4c-a3b0-e7edce168756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650535953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2650535953
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1592083007
Short name T243
Test name
Test status
Simulation time 572995613 ps
CPU time 0.8 seconds
Started Jul 18 05:57:36 PM PDT 24
Finished Jul 18 05:57:39 PM PDT 24
Peak memory 196316 kb
Host smart-76171074-ac3a-4d51-98d9-33b362d4dabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592083007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1592083007
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_jump.608504345
Short name T190
Test name
Test status
Simulation time 585836562 ps
CPU time 1.52 seconds
Started Jul 18 05:57:37 PM PDT 24
Finished Jul 18 05:57:40 PM PDT 24
Peak memory 196224 kb
Host smart-ba5a2f8b-b620-405a-8d67-eed8ae15cc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608504345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.608504345
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2109349870
Short name T240
Test name
Test status
Simulation time 51046671390 ps
CPU time 32.68 seconds
Started Jul 18 05:57:44 PM PDT 24
Finished Jul 18 05:58:23 PM PDT 24
Peak memory 191512 kb
Host smart-e2e10b1c-2c35-44dd-a753-2ab98e7d82d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109349870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2109349870
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1850625480
Short name T229
Test name
Test status
Simulation time 452782317 ps
CPU time 0.94 seconds
Started Jul 18 05:57:41 PM PDT 24
Finished Jul 18 05:57:44 PM PDT 24
Peak memory 191492 kb
Host smart-47d7acbb-6b4c-44d0-b8c2-208ecf4787b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850625480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1850625480
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.635010564
Short name T260
Test name
Test status
Simulation time 3950898734 ps
CPU time 5.84 seconds
Started Jul 18 05:57:39 PM PDT 24
Finished Jul 18 05:57:47 PM PDT 24
Peak memory 196352 kb
Host smart-40ac86f9-8088-4cfe-b82f-add29cef3980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635010564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.635010564
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.683128807
Short name T237
Test name
Test status
Simulation time 411087810 ps
CPU time 0.72 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:48 PM PDT 24
Peak memory 191444 kb
Host smart-956f882d-71f3-42f0-9d74-e3216029456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683128807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.683128807
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.4240212083
Short name T271
Test name
Test status
Simulation time 15270774210 ps
CPU time 6.36 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:57:52 PM PDT 24
Peak memory 196560 kb
Host smart-7e3edd0b-2ae7-44a7-9f27-5a122f0ff599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240212083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.4240212083
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1010221912
Short name T27
Test name
Test status
Simulation time 416025890 ps
CPU time 1.25 seconds
Started Jul 18 05:57:40 PM PDT 24
Finished Jul 18 05:57:43 PM PDT 24
Peak memory 191464 kb
Host smart-79cf7b5d-0255-4471-9bed-0ae5f2a9dced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010221912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1010221912
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3114483427
Short name T202
Test name
Test status
Simulation time 13671118049 ps
CPU time 11.77 seconds
Started Jul 18 05:57:37 PM PDT 24
Finished Jul 18 05:57:50 PM PDT 24
Peak memory 191556 kb
Host smart-37c2d1f7-0f58-48a8-98f5-1ed0e2944926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114483427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3114483427
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2964389439
Short name T11
Test name
Test status
Simulation time 494822159 ps
CPU time 0.72 seconds
Started Jul 18 05:57:41 PM PDT 24
Finished Jul 18 05:57:44 PM PDT 24
Peak memory 196352 kb
Host smart-5c3a1122-1654-4ecf-96a4-30da6253311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964389439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2964389439
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_jump.457245443
Short name T87
Test name
Test status
Simulation time 539687466 ps
CPU time 1.34 seconds
Started Jul 18 05:57:43 PM PDT 24
Finished Jul 18 05:57:50 PM PDT 24
Peak memory 196284 kb
Host smart-8698ab82-c02c-48e3-9e03-c233fa673433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457245443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.457245443
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2226200990
Short name T225
Test name
Test status
Simulation time 12272159656 ps
CPU time 4.99 seconds
Started Jul 18 05:57:34 PM PDT 24
Finished Jul 18 05:57:41 PM PDT 24
Peak memory 191556 kb
Host smart-f0f003f2-da6b-4dbe-8c17-f82ce5a76f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226200990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2226200990
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.736895695
Short name T253
Test name
Test status
Simulation time 589044480 ps
CPU time 0.99 seconds
Started Jul 18 05:57:44 PM PDT 24
Finished Jul 18 05:57:51 PM PDT 24
Peak memory 195852 kb
Host smart-16091b62-2027-4a58-b340-41e724921a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736895695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.736895695
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1626479226
Short name T268
Test name
Test status
Simulation time 22304178876 ps
CPU time 5.63 seconds
Started Jul 18 05:57:34 PM PDT 24
Finished Jul 18 05:57:42 PM PDT 24
Peak memory 196644 kb
Host smart-52e19797-be83-442e-b6ff-9a330f0d6566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626479226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1626479226
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1045373277
Short name T217
Test name
Test status
Simulation time 650257830 ps
CPU time 0.6 seconds
Started Jul 18 05:57:35 PM PDT 24
Finished Jul 18 05:57:37 PM PDT 24
Peak memory 196256 kb
Host smart-0ede7e13-a2a3-4b71-acc4-d6d5c55c9daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045373277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1045373277
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2672767572
Short name T23
Test name
Test status
Simulation time 50109241123 ps
CPU time 82.01 seconds
Started Jul 18 05:57:42 PM PDT 24
Finished Jul 18 05:59:07 PM PDT 24
Peak memory 191596 kb
Host smart-e0af2f02-90e2-44f7-b1c0-59bf468ee9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672767572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2672767572
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.550391966
Short name T186
Test name
Test status
Simulation time 401427534 ps
CPU time 0.75 seconds
Started Jul 18 05:57:36 PM PDT 24
Finished Jul 18 05:57:39 PM PDT 24
Peak memory 196404 kb
Host smart-e959c304-d331-4024-a49b-90e574abd550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550391966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.550391966
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3915856824
Short name T66
Test name
Test status
Simulation time 35820838523 ps
CPU time 52.37 seconds
Started Jul 18 05:57:39 PM PDT 24
Finished Jul 18 05:58:33 PM PDT 24
Peak memory 191564 kb
Host smart-b8827124-e365-4194-889d-78671d7afa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915856824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3915856824
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3599820562
Short name T226
Test name
Test status
Simulation time 541349407 ps
CPU time 1.01 seconds
Started Jul 18 05:57:45 PM PDT 24
Finished Jul 18 05:57:51 PM PDT 24
Peak memory 191520 kb
Host smart-dece4589-52b6-48a7-8e37-4cad1dd5f98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599820562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3599820562
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1124760331
Short name T12
Test name
Test status
Simulation time 56798465679 ps
CPU time 89.53 seconds
Started Jul 18 05:57:44 PM PDT 24
Finished Jul 18 05:59:20 PM PDT 24
Peak memory 191104 kb
Host smart-e8a81c00-39c9-42aa-b877-719b7b1964d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124760331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1124760331
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1803758654
Short name T262
Test name
Test status
Simulation time 452753846 ps
CPU time 0.82 seconds
Started Jul 18 05:57:38 PM PDT 24
Finished Jul 18 05:57:40 PM PDT 24
Peak memory 191460 kb
Host smart-0604773a-d224-4ce1-9590-ae73dfcd8eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803758654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1803758654
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2467247854
Short name T264
Test name
Test status
Simulation time 9202431151 ps
CPU time 4.1 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:07 PM PDT 24
Peak memory 196584 kb
Host smart-ff898fc7-8d9e-4033-8faf-88090197a178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467247854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2467247854
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3354953099
Short name T254
Test name
Test status
Simulation time 565802796 ps
CPU time 0.83 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:05 PM PDT 24
Peak memory 191472 kb
Host smart-ad5da2ea-c5cf-46d9-ad81-aec902fc0ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354953099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3354953099
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3546943803
Short name T223
Test name
Test status
Simulation time 36350408710 ps
CPU time 47.83 seconds
Started Jul 18 05:56:56 PM PDT 24
Finished Jul 18 05:57:51 PM PDT 24
Peak memory 191516 kb
Host smart-fe763659-197d-4ba3-b08b-4dd4ebaa519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546943803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3546943803
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2300406979
Short name T50
Test name
Test status
Simulation time 503137470 ps
CPU time 1.22 seconds
Started Jul 18 05:56:57 PM PDT 24
Finished Jul 18 05:57:05 PM PDT 24
Peak memory 196312 kb
Host smart-b70cbeda-31e2-44c3-a9a6-009e88ea2f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300406979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2300406979
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2655174864
Short name T188
Test name
Test status
Simulation time 548869461 ps
CPU time 0.96 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 05:57:08 PM PDT 24
Peak memory 196296 kb
Host smart-101aa6d5-e459-40b9-9430-39fff0c20b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655174864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2655174864
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3046543941
Short name T249
Test name
Test status
Simulation time 28124131380 ps
CPU time 9.78 seconds
Started Jul 18 05:57:00 PM PDT 24
Finished Jul 18 05:57:18 PM PDT 24
Peak memory 191552 kb
Host smart-30dd4097-1bba-4aea-9faf-4e353f7dcf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046543941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3046543941
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3155170732
Short name T250
Test name
Test status
Simulation time 403749694 ps
CPU time 0.72 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 05:57:07 PM PDT 24
Peak memory 191496 kb
Host smart-391add25-49c4-406a-8a0b-04c505e7a658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155170732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3155170732
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_jump.456533948
Short name T161
Test name
Test status
Simulation time 559182852 ps
CPU time 0.81 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 05:57:06 PM PDT 24
Peak memory 196284 kb
Host smart-c8a2a201-f181-40c4-9375-6b875f0d790a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456533948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.456533948
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2085328817
Short name T256
Test name
Test status
Simulation time 16331822014 ps
CPU time 24.66 seconds
Started Jul 18 05:56:58 PM PDT 24
Finished Jul 18 05:57:30 PM PDT 24
Peak memory 191560 kb
Host smart-7148ea01-7ab3-4183-81da-0f59ef99b2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085328817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2085328817
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3264681861
Short name T198
Test name
Test status
Simulation time 596929875 ps
CPU time 0.71 seconds
Started Jul 18 05:56:59 PM PDT 24
Finished Jul 18 05:57:08 PM PDT 24
Peak memory 196332 kb
Host smart-40172367-7e55-4d77-a5e0-80154787efb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264681861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3264681861
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.4115270062
Short name T246
Test name
Test status
Simulation time 22085649153 ps
CPU time 18.4 seconds
Started Jul 18 05:57:03 PM PDT 24
Finished Jul 18 05:57:29 PM PDT 24
Peak memory 190780 kb
Host smart-03959dd0-60fb-4a65-9cd7-acb4defddbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115270062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.4115270062
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1656674246
Short name T219
Test name
Test status
Simulation time 508524356 ps
CPU time 1.32 seconds
Started Jul 18 05:57:02 PM PDT 24
Finished Jul 18 05:57:11 PM PDT 24
Peak memory 196308 kb
Host smart-462ddf8b-de0d-4dbf-a872-da774fa93230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656674246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1656674246
Directory /workspace/9.aon_timer_smoke/latest
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