Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	28377	1		T2	59		T3	10		T4	10
bark[1]	963	1		T28	21		T44	236		T46	21
bark[2]	336	1		T30	14		T94	21		T165	44
bark[3]	539	1		T11	90		T14	21		T80	218
bark[4]	393	1		T2	94		T16	21		T43	21
bark[5]	954	1		T11	21		T15	476		T43	39
bark[6]	646	1		T32	14		T14	76		T43	26
bark[7]	495	1		T8	19		T53	14		T129	35
bark[8]	713	1		T9	14		T31	14		T53	21
bark[9]	879	1		T43	134		T94	21		T101	14
bark[10]	857	1		T11	115		T43	68		T53	26
bark[11]	417	1		T8	38		T53	21		T185	14
bark[12]	666	1		T8	21		T15	21		T33	47
bark[13]	352	1		T8	21		T14	21		T50	82
bark[14]	661	1		T11	30		T14	21		T46	236
bark[15]	212	1		T50	21		T16	26		T122	14
bark[16]	515	1		T11	21		T16	47		T53	21
bark[17]	641	1		T43	154		T53	38		T47	47
bark[18]	875	1		T44	172		T48	21		T102	21
bark[19]	192	1		T11	21		T181	14		T149	136
bark[20]	299	1		T1	14		T33	21		T43	21
bark[21]	763	1		T14	21		T33	21		T28	30
bark[22]	672	1		T46	21		T47	14		T166	63
bark[23]	679	1		T9	21		T11	61		T15	21
bark[24]	325	1		T15	21		T43	26		T76	21
bark[25]	741	1		T7	14		T14	14		T44	275
bark[26]	473	1		T6	14		T14	21		T29	14
bark[27]	1090	1		T44	21		T53	21		T47	35
bark[28]	814	1		T2	26		T44	21		T119	21
bark[29]	503	1		T14	21		T28	30		T43	30
bark[30]	138	1		T2	14		T102	14		T54	47
bark[31]	890	1		T33	21		T143	40		T119	26
bark_0	4649	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	28276	1		T2	59		T3	9		T4	9
bite[1]	328	1		T8	18		T47	114		T94	21
bite[2]	681	1		T2	13		T14	42		T53	26
bite[3]	466	1		T14	13		T15	21		T43	93
bite[4]	652	1		T14	21		T46	235		T102	21
bite[5]	658	1		T44	30		T102	21		T129	35
bite[6]	582	1		T46	21		T76	209		T78	21
bite[7]	615	1		T166	40		T79	21		T81	96
bite[8]	811	1		T143	21		T76	21		T175	26
bite[9]	844	1		T11	21		T31	13		T16	46
bite[10]	537	1		T160	102		T157	195		T141	30
bite[11]	72	1		T43	21		T46	30		T55	21
bite[12]	311	1		T15	21		T28	21		T166	21
bite[13]	916	1		T8	21		T48	21		T119	47
bite[14]	440	1		T11	21		T14	76		T50	51
bite[15]	703	1		T9	13		T11	21		T43	21
bite[16]	1189	1		T15	475		T33	26		T43	153
bite[17]	390	1		T50	59		T152	31		T76	195
bite[18]	491	1		T29	13		T53	13		T102	21
bite[19]	914	1		T9	21		T32	13		T14	21
bite[20]	798	1		T1	13		T11	60		T28	30
bite[21]	372	1		T33	21		T53	21		T175	26
bite[22]	759	1		T6	13		T11	89		T14	21
bite[23]	218	1		T49	53		T80	21		T82	34
bite[24]	437	1		T14	21		T50	21		T49	25
bite[25]	590	1		T33	21		T43	56		T44	171
bite[26]	824	1		T11	114		T44	226		T125	13
bite[27]	688	1		T8	21		T50	30		T28	30
bite[28]	603	1		T2	26		T43	190		T53	38
bite[29]	595	1		T2	94		T16	21		T143	40
bite[30]	618	1		T7	13		T8	38		T43	39
bite[31]	245	1		T33	21		T53	21		T102	38
bite_0	5096	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	43349	1		T1	21		T2	87		T3	17
auto[1]	8370	1		T2	113		T9	60		T14	34

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	960	1		T2	59		T9	19		T11	19
prescale[1]	751	1		T11	19		T43	102		T47	19
prescale[2]	746	1		T11	19		T44	61		T166	40
prescale[3]	688	1		T47	19		T198	9		T140	74
prescale[4]	674	1		T11	19		T43	19		T46	101
prescale[5]	673	1		T12	9		T47	9		T165	49
prescale[6]	513	1		T8	66		T33	28		T24	9
prescale[7]	555	1		T11	19		T16	42		T43	54
prescale[8]	722	1		T11	19		T15	19		T16	2
prescale[9]	1214	1		T9	19		T15	53		T16	9
prescale[10]	1006	1		T8	19		T16	23		T28	24
prescale[11]	829	1		T44	23		T46	46		T47	2
prescale[12]	1245	1		T11	36		T44	68		T47	169
prescale[13]	559	1		T43	47		T44	47		T48	2
prescale[14]	767	1		T11	66		T15	40		T16	19
prescale[15]	966	1		T14	55		T15	107		T45	2
prescale[16]	601	1		T11	19		T15	53		T43	2
prescale[17]	580	1		T8	32		T11	19		T47	49
prescale[18]	978	1		T2	28		T14	23		T23	9
prescale[19]	1093	1		T13	9		T15	241		T33	28
prescale[20]	557	1		T11	19		T15	2		T43	64
prescale[21]	1251	1		T10	9		T11	77		T15	55
prescale[22]	898	1		T8	70		T11	76		T14	30
prescale[23]	864	1		T15	60		T16	19		T43	102
prescale[24]	700	1		T8	19		T11	14		T16	24
prescale[25]	529	1		T45	2		T140	64		T160	121
prescale[26]	759	1		T8	19		T11	73		T16	185
prescale[27]	797	1		T11	81		T44	81		T48	2
prescale[28]	483	1		T33	18		T16	19		T43	2
prescale[29]	424	1		T11	4		T16	2		T43	43
prescale[30]	661	1		T11	9		T16	2		T43	69
prescale[31]	1005	1		T9	28		T11	71		T15	19
prescale_0	26671	1		T1	21		T2	113		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38397	1		T1	9		T2	132		T3	17
auto[1]	13322	1		T1	12		T2	68		T5	9

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	51719	1		T1	21		T2	200		T3	17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30223	1		T1	1		T2	119		T3	12
wkup[1]	173	1		T166	21		T129	47		T143	21
wkup[2]	248	1		T44	21		T47	21		T152	21
wkup[3]	290	1		T31	15		T28	21		T129	15
wkup[4]	201	1		T11	21		T50	21		T152	63
wkup[5]	238	1		T183	15		T181	15		T76	71
wkup[6]	272	1		T44	21		T46	42		T80	42
wkup[7]	329	1		T9	26		T11	21		T14	21
wkup[8]	308	1		T32	15		T44	26		T143	21
wkup[9]	222	1		T14	21		T43	42		T44	21
wkup[10]	230	1		T15	21		T43	21		T48	15
wkup[11]	302	1		T44	30		T46	21		T47	21
wkup[12]	244	1		T11	26		T15	21		T152	26
wkup[13]	284	1		T11	63		T15	21		T94	21
wkup[14]	198	1		T43	21		T53	15		T78	42
wkup[15]	274	1		T16	16		T44	21		T125	26
wkup[16]	417	1		T50	26		T44	8		T45	26
wkup[17]	356	1		T50	21		T43	21		T45	21
wkup[18]	282	1		T50	21		T44	21		T160	21
wkup[19]	443	1		T43	30		T44	21		T47	21
wkup[20]	253	1		T47	21		T160	15		T77	30
wkup[21]	243	1		T8	26		T50	21		T16	21
wkup[22]	170	1		T7	15		T140	42		T79	21
wkup[23]	265	1		T16	30		T77	21		T157	21
wkup[24]	270	1		T15	21		T16	21		T47	21
wkup[25]	170	1		T47	26		T76	21		T159	31
wkup[26]	199	1		T11	30		T43	21		T125	26
wkup[27]	235	1		T8	21		T43	26		T102	21
wkup[28]	388	1		T28	30		T43	15		T47	21
wkup[29]	278	1		T15	21		T50	30		T125	30
wkup[30]	170	1		T16	21		T47	15		T49	8
wkup[31]	242	1		T94	26		T116	15		T128	30
wkup[32]	143	1		T9	36		T44	21		T46	30
wkup[33]	285	1		T11	26		T33	21		T43	60
wkup[34]	252	1		T2	26		T16	8		T182	21
wkup[35]	231	1		T43	8		T94	24		T143	21
wkup[36]	257	1		T15	21		T44	26		T47	21
wkup[37]	318	1		T16	42		T43	21		T45	21
wkup[38]	221	1		T2	15		T11	21		T94	21
wkup[39]	407	1		T15	21		T33	21		T16	21
wkup[40]	225	1		T14	36		T50	21		T16	21
wkup[41]	289	1		T6	15		T44	21		T53	21
wkup[42]	254	1		T1	15		T43	21		T46	21
wkup[43]	350	1		T33	26		T44	60		T166	21
wkup[44]	329	1		T8	21		T9	21		T43	26
wkup[45]	422	1		T43	39		T53	26		T47	21
wkup[46]	316	1		T14	21		T16	30		T29	15
wkup[47]	370	1		T11	30		T15	21		T43	42
wkup[48]	406	1		T11	21		T14	21		T15	15
wkup[49]	273	1		T15	15		T43	30		T129	35
wkup[50]	182	1		T8	21		T43	21		T82	21
wkup[51]	310	1		T11	47		T15	21		T43	21
wkup[52]	192	1		T11	21		T46	21		T159	21
wkup[53]	300	1		T15	21		T43	45		T77	42
wkup[54]	387	1		T8	50		T11	30		T16	42
wkup[55]	408	1		T11	21		T33	42		T125	35
wkup[56]	278	1		T14	21		T50	21		T28	30
wkup[57]	282	1		T16	21		T160	21		T79	21
wkup[58]	309	1		T33	21		T44	50		T102	21
wkup[59]	356	1		T43	77		T166	21		T77	51
wkup[60]	269	1		T15	21		T16	30		T53	21
wkup[61]	456	1		T2	35		T14	21		T33	21
wkup[62]	222	1		T30	15		T53	21		T102	44
wkup[63]	406	1		T14	21		T43	30		T44	57
wkup_0	3597	1		T1	5		T2	5		T3	5