Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
4039 |
1 |
|
T1 |
1 |
|
T2 |
27 |
|
T3 |
1 |
all_values[1] |
4039 |
1 |
|
T1 |
1 |
|
T2 |
27 |
|
T3 |
1 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6479 |
1 |
|
T2 |
45 |
|
T3 |
1 |
|
T4 |
1 |
auto[1] |
1599 |
1 |
|
T1 |
2 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4593 |
1 |
|
T1 |
2 |
|
T2 |
31 |
|
T3 |
1 |
auto[1] |
3485 |
1 |
|
T2 |
23 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
1634 |
1 |
|
T2 |
12 |
|
T8 |
3 |
|
T9 |
6 |
all_values[0] |
auto[0] |
auto[1] |
1108 |
1 |
|
T2 |
8 |
|
T8 |
9 |
|
T9 |
8 |
all_values[0] |
auto[1] |
auto[0] |
163 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
1 |
all_values[0] |
auto[1] |
auto[1] |
1134 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
1 |
all_values[1] |
auto[0] |
auto[0] |
2650 |
1 |
|
T2 |
17 |
|
T3 |
1 |
|
T4 |
1 |
all_values[1] |
auto[0] |
auto[1] |
1087 |
1 |
|
T2 |
8 |
|
T8 |
6 |
|
T9 |
7 |
all_values[1] |
auto[1] |
auto[0] |
146 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T6 |
1 |
all_values[1] |
auto[1] |
auto[1] |
156 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T11 |
1 |