Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.42 99.33 93.67 100.00 98.40 99.51 51.60


Total test records in report: 418
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T40 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3739684071 Jul 19 04:53:51 PM PDT 24 Jul 19 04:54:06 PM PDT 24 7293791465 ps
T41 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3648669594 Jul 19 04:53:45 PM PDT 24 Jul 19 04:53:48 PM PDT 24 526260646 ps
T288 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.816017102 Jul 19 04:54:08 PM PDT 24 Jul 19 04:54:10 PM PDT 24 406427231 ps
T289 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2814893819 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:28 PM PDT 24 444720546 ps
T42 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.595531385 Jul 19 04:53:45 PM PDT 24 Jul 19 04:53:58 PM PDT 24 13840142932 ps
T35 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.379582625 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:30 PM PDT 24 3301514572 ps
T36 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3923312160 Jul 19 04:54:00 PM PDT 24 Jul 19 04:54:03 PM PDT 24 494774183 ps
T290 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1307936898 Jul 19 04:54:29 PM PDT 24 Jul 19 04:54:34 PM PDT 24 366142240 ps
T37 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2711572154 Jul 19 04:53:47 PM PDT 24 Jul 19 04:53:58 PM PDT 24 4540842502 ps
T291 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2233793286 Jul 19 04:54:18 PM PDT 24 Jul 19 04:54:20 PM PDT 24 454528253 ps
T292 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.777378881 Jul 19 04:54:28 PM PDT 24 Jul 19 04:54:32 PM PDT 24 514371965 ps
T199 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2098627727 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:30 PM PDT 24 401122155 ps
T293 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3402010154 Jul 19 04:54:31 PM PDT 24 Jul 19 04:54:35 PM PDT 24 437136439 ps
T38 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3213621782 Jul 19 04:54:01 PM PDT 24 Jul 19 04:54:10 PM PDT 24 7858339338 ps
T294 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.670249491 Jul 19 04:54:30 PM PDT 24 Jul 19 04:54:35 PM PDT 24 349938822 ps
T56 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2752521924 Jul 19 04:53:53 PM PDT 24 Jul 19 04:53:58 PM PDT 24 543120534 ps
T295 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1787539383 Jul 19 04:54:18 PM PDT 24 Jul 19 04:54:20 PM PDT 24 527540386 ps
T57 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2042908966 Jul 19 04:53:54 PM PDT 24 Jul 19 04:54:00 PM PDT 24 1163296986 ps
T296 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3580252642 Jul 19 04:54:00 PM PDT 24 Jul 19 04:54:05 PM PDT 24 510636398 ps
T58 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3153646019 Jul 19 04:53:53 PM PDT 24 Jul 19 04:54:02 PM PDT 24 4008736004 ps
T297 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3503194930 Jul 19 04:54:03 PM PDT 24 Jul 19 04:54:05 PM PDT 24 458504645 ps
T59 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1286599023 Jul 19 04:54:12 PM PDT 24 Jul 19 04:54:15 PM PDT 24 326276447 ps
T298 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2041095771 Jul 19 04:54:12 PM PDT 24 Jul 19 04:54:16 PM PDT 24 354756101 ps
T299 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3669475218 Jul 19 04:54:13 PM PDT 24 Jul 19 04:54:17 PM PDT 24 299262035 ps
T300 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.703905314 Jul 19 04:54:47 PM PDT 24 Jul 19 04:54:51 PM PDT 24 450677357 ps
T301 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2009574365 Jul 19 04:54:28 PM PDT 24 Jul 19 04:54:33 PM PDT 24 269036808 ps
T302 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2511719823 Jul 19 04:53:59 PM PDT 24 Jul 19 04:54:02 PM PDT 24 418519931 ps
T70 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3296937278 Jul 19 04:54:11 PM PDT 24 Jul 19 04:54:13 PM PDT 24 987683607 ps
T303 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.840463540 Jul 19 04:54:19 PM PDT 24 Jul 19 04:54:23 PM PDT 24 515506461 ps
T304 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1265024717 Jul 19 04:54:29 PM PDT 24 Jul 19 04:54:33 PM PDT 24 369806775 ps
T200 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1159940667 Jul 19 04:54:21 PM PDT 24 Jul 19 04:54:24 PM PDT 24 752446301 ps
T305 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4258683061 Jul 19 04:54:19 PM PDT 24 Jul 19 04:54:22 PM PDT 24 404992073 ps
T71 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3133979154 Jul 19 04:53:46 PM PDT 24 Jul 19 04:53:50 PM PDT 24 343400371 ps
T60 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3172420332 Jul 19 04:54:18 PM PDT 24 Jul 19 04:54:20 PM PDT 24 568934256 ps
T306 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3191357514 Jul 19 04:53:53 PM PDT 24 Jul 19 04:53:59 PM PDT 24 601286725 ps
T307 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.247754750 Jul 19 04:54:25 PM PDT 24 Jul 19 04:54:28 PM PDT 24 472724206 ps
T308 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3728568836 Jul 19 04:53:44 PM PDT 24 Jul 19 04:53:47 PM PDT 24 505403053 ps
T309 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1877239347 Jul 19 04:53:52 PM PDT 24 Jul 19 04:53:57 PM PDT 24 370389519 ps
T310 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4291216342 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:29 PM PDT 24 464490354 ps
T311 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2310891654 Jul 19 04:53:45 PM PDT 24 Jul 19 04:53:48 PM PDT 24 441721788 ps
T312 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1722090303 Jul 19 04:54:00 PM PDT 24 Jul 19 04:54:04 PM PDT 24 512084240 ps
T313 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4139912372 Jul 19 04:54:12 PM PDT 24 Jul 19 04:54:16 PM PDT 24 803350691 ps
T39 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2210162980 Jul 19 04:53:46 PM PDT 24 Jul 19 04:53:56 PM PDT 24 8515661225 ps
T314 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3414738504 Jul 19 04:53:44 PM PDT 24 Jul 19 04:53:46 PM PDT 24 471892493 ps
T315 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.228206823 Jul 19 04:53:52 PM PDT 24 Jul 19 04:53:58 PM PDT 24 400597728 ps
T316 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.617229637 Jul 19 04:53:45 PM PDT 24 Jul 19 04:53:49 PM PDT 24 867639555 ps
T317 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1477377203 Jul 19 04:53:44 PM PDT 24 Jul 19 04:53:48 PM PDT 24 297529081 ps
T63 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1760953781 Jul 19 04:54:20 PM PDT 24 Jul 19 04:54:22 PM PDT 24 579703655 ps
T61 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4123433795 Jul 19 04:54:11 PM PDT 24 Jul 19 04:54:14 PM PDT 24 307925321 ps
T318 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3790074184 Jul 19 04:54:30 PM PDT 24 Jul 19 04:54:35 PM PDT 24 470006761 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1209308488 Jul 19 04:53:44 PM PDT 24 Jul 19 04:53:47 PM PDT 24 394243336 ps
T319 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.443608233 Jul 19 04:53:53 PM PDT 24 Jul 19 04:53:59 PM PDT 24 575890265 ps
T64 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.451353621 Jul 19 04:53:47 PM PDT 24 Jul 19 04:53:51 PM PDT 24 598498361 ps
T72 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4222475750 Jul 19 04:54:00 PM PDT 24 Jul 19 04:54:04 PM PDT 24 1924210011 ps
T73 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2914214291 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:12 PM PDT 24 1041754995 ps
T74 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3623940849 Jul 19 04:54:19 PM PDT 24 Jul 19 04:54:22 PM PDT 24 501562126 ps
T75 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2603845710 Jul 19 04:54:18 PM PDT 24 Jul 19 04:54:23 PM PDT 24 2231015381 ps
T320 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1940178734 Jul 19 04:54:20 PM PDT 24 Jul 19 04:54:22 PM PDT 24 264557727 ps
T321 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.372760175 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:28 PM PDT 24 378447001 ps
T322 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3352450067 Jul 19 04:54:02 PM PDT 24 Jul 19 04:54:05 PM PDT 24 482198611 ps
T191 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3224807000 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:15 PM PDT 24 4001756313 ps
T323 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1127710060 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:29 PM PDT 24 302980148 ps
T324 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3372373324 Jul 19 04:53:52 PM PDT 24 Jul 19 04:53:57 PM PDT 24 283305266 ps
T192 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.274568721 Jul 19 04:53:53 PM PDT 24 Jul 19 04:54:03 PM PDT 24 4666291387 ps
T325 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3821779365 Jul 19 04:53:57 PM PDT 24 Jul 19 04:54:02 PM PDT 24 329213732 ps
T326 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.477905212 Jul 19 04:54:11 PM PDT 24 Jul 19 04:54:14 PM PDT 24 340826594 ps
T327 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4175311854 Jul 19 04:53:52 PM PDT 24 Jul 19 04:53:57 PM PDT 24 407781494 ps
T328 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.928408904 Jul 19 04:53:45 PM PDT 24 Jul 19 04:53:49 PM PDT 24 1133099364 ps
T329 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.309439577 Jul 19 04:54:27 PM PDT 24 Jul 19 04:54:32 PM PDT 24 301738792 ps
T330 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2036381032 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:12 PM PDT 24 440929788 ps
T331 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1674992056 Jul 19 04:54:19 PM PDT 24 Jul 19 04:54:28 PM PDT 24 4611555300 ps
T332 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2503769784 Jul 19 04:54:29 PM PDT 24 Jul 19 04:54:33 PM PDT 24 357437572 ps
T333 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1101266893 Jul 19 04:54:00 PM PDT 24 Jul 19 04:54:04 PM PDT 24 1286842584 ps
T334 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3716012101 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:13 PM PDT 24 412000771 ps
T335 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.256204526 Jul 19 04:54:01 PM PDT 24 Jul 19 04:54:05 PM PDT 24 426303564 ps
T193 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2883110029 Jul 19 04:54:12 PM PDT 24 Jul 19 04:54:21 PM PDT 24 8288417076 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1843531039 Jul 19 04:53:55 PM PDT 24 Jul 19 04:54:01 PM PDT 24 376508343 ps
T336 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1703087365 Jul 19 04:53:49 PM PDT 24 Jul 19 04:53:55 PM PDT 24 712258391 ps
T337 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.752403282 Jul 19 04:54:27 PM PDT 24 Jul 19 04:54:31 PM PDT 24 381935244 ps
T338 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.286465615 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:17 PM PDT 24 2150193512 ps
T339 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2468889581 Jul 19 04:54:27 PM PDT 24 Jul 19 04:54:33 PM PDT 24 505307229 ps
T340 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1667052236 Jul 19 04:54:28 PM PDT 24 Jul 19 04:54:33 PM PDT 24 306459842 ps
T341 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1661377099 Jul 19 04:54:28 PM PDT 24 Jul 19 04:54:32 PM PDT 24 497827527 ps
T66 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1929288768 Jul 19 04:53:47 PM PDT 24 Jul 19 04:53:52 PM PDT 24 676589445 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2714507348 Jul 19 04:53:56 PM PDT 24 Jul 19 04:54:01 PM PDT 24 475470930 ps
T342 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3311522078 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:14 PM PDT 24 464355574 ps
T343 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2752323063 Jul 19 04:54:11 PM PDT 24 Jul 19 04:54:14 PM PDT 24 487298120 ps
T344 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2675372685 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:13 PM PDT 24 673453580 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1845987674 Jul 19 04:53:47 PM PDT 24 Jul 19 04:53:51 PM PDT 24 727430335 ps
T345 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2086872625 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:15 PM PDT 24 8506943124 ps
T346 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.962404326 Jul 19 04:53:46 PM PDT 24 Jul 19 04:53:51 PM PDT 24 1213960754 ps
T196 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3841860171 Jul 19 04:53:57 PM PDT 24 Jul 19 04:54:12 PM PDT 24 8471905243 ps
T347 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1825116897 Jul 19 04:54:00 PM PDT 24 Jul 19 04:54:03 PM PDT 24 466790344 ps
T348 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2226700357 Jul 19 04:54:20 PM PDT 24 Jul 19 04:54:24 PM PDT 24 602627264 ps
T349 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1765734565 Jul 19 04:54:28 PM PDT 24 Jul 19 04:54:33 PM PDT 24 438186852 ps
T350 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1073583196 Jul 19 04:54:11 PM PDT 24 Jul 19 04:54:14 PM PDT 24 272182798 ps
T351 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.696249485 Jul 19 04:53:57 PM PDT 24 Jul 19 04:54:03 PM PDT 24 493070855 ps
T352 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3381886594 Jul 19 04:54:12 PM PDT 24 Jul 19 04:54:16 PM PDT 24 1827906738 ps
T353 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.177363634 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:30 PM PDT 24 397612388 ps
T354 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4163610868 Jul 19 04:54:19 PM PDT 24 Jul 19 04:54:26 PM PDT 24 4020944863 ps
T355 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.675349161 Jul 19 04:53:53 PM PDT 24 Jul 19 04:53:59 PM PDT 24 624833718 ps
T356 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3958590272 Jul 19 04:54:01 PM PDT 24 Jul 19 04:54:05 PM PDT 24 323139844 ps
T357 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2617696172 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:29 PM PDT 24 462032273 ps
T358 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3758774993 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:29 PM PDT 24 365585383 ps
T194 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2395148188 Jul 19 04:53:47 PM PDT 24 Jul 19 04:53:53 PM PDT 24 8563260073 ps
T359 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2667071364 Jul 19 04:53:51 PM PDT 24 Jul 19 04:53:56 PM PDT 24 403901392 ps
T360 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4008784637 Jul 19 04:54:27 PM PDT 24 Jul 19 04:54:31 PM PDT 24 437022282 ps
T361 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.97851507 Jul 19 04:53:47 PM PDT 24 Jul 19 04:53:57 PM PDT 24 2523470985 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3015874792 Jul 19 04:53:52 PM PDT 24 Jul 19 04:53:58 PM PDT 24 409874468 ps
T363 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3741144614 Jul 19 04:53:48 PM PDT 24 Jul 19 04:53:51 PM PDT 24 355036410 ps
T364 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4068949794 Jul 19 04:54:20 PM PDT 24 Jul 19 04:54:22 PM PDT 24 265836507 ps
T365 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4125688621 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:12 PM PDT 24 315199977 ps
T366 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2384828913 Jul 19 04:54:21 PM PDT 24 Jul 19 04:54:25 PM PDT 24 494113139 ps
T367 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2180573914 Jul 19 04:53:53 PM PDT 24 Jul 19 04:53:59 PM PDT 24 632124840 ps
T368 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1777390279 Jul 19 04:54:11 PM PDT 24 Jul 19 04:54:14 PM PDT 24 667242139 ps
T369 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.854864578 Jul 19 04:53:53 PM PDT 24 Jul 19 04:53:58 PM PDT 24 343950255 ps
T370 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.285474504 Jul 19 04:54:12 PM PDT 24 Jul 19 04:54:15 PM PDT 24 506509401 ps
T371 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2363144936 Jul 19 04:54:25 PM PDT 24 Jul 19 04:54:28 PM PDT 24 474886129 ps
T372 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4137000084 Jul 19 04:54:11 PM PDT 24 Jul 19 04:54:19 PM PDT 24 1671059713 ps
T373 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2255865023 Jul 19 04:54:20 PM PDT 24 Jul 19 04:54:23 PM PDT 24 380236397 ps
T374 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3114208713 Jul 19 04:54:09 PM PDT 24 Jul 19 04:54:10 PM PDT 24 545278888 ps
T375 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4258907270 Jul 19 04:54:12 PM PDT 24 Jul 19 04:54:15 PM PDT 24 834012597 ps
T376 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4097623667 Jul 19 04:54:25 PM PDT 24 Jul 19 04:54:28 PM PDT 24 1051046055 ps
T377 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.92199877 Jul 19 04:54:03 PM PDT 24 Jul 19 04:54:06 PM PDT 24 518915103 ps
T378 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2727396535 Jul 19 04:54:06 PM PDT 24 Jul 19 04:54:10 PM PDT 24 1117021716 ps
T379 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1772167818 Jul 19 04:54:21 PM PDT 24 Jul 19 04:54:24 PM PDT 24 4128164622 ps
T68 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2884973043 Jul 19 04:53:52 PM PDT 24 Jul 19 04:53:58 PM PDT 24 775059008 ps
T380 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1616332325 Jul 19 04:53:53 PM PDT 24 Jul 19 04:53:59 PM PDT 24 934945720 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2658024266 Jul 19 04:53:56 PM PDT 24 Jul 19 04:54:02 PM PDT 24 683552339 ps
T382 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1645809810 Jul 19 04:54:29 PM PDT 24 Jul 19 04:54:33 PM PDT 24 469335149 ps
T383 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2014788993 Jul 19 04:54:12 PM PDT 24 Jul 19 04:54:16 PM PDT 24 4545387295 ps
T384 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3634536422 Jul 19 04:53:47 PM PDT 24 Jul 19 04:53:51 PM PDT 24 348142505 ps
T385 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.163667778 Jul 19 04:54:19 PM PDT 24 Jul 19 04:54:28 PM PDT 24 2777287965 ps
T386 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.499883382 Jul 19 04:54:28 PM PDT 24 Jul 19 04:54:33 PM PDT 24 403741695 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4015143793 Jul 19 04:53:56 PM PDT 24 Jul 19 04:54:04 PM PDT 24 8199962434 ps
T388 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2996893732 Jul 19 04:53:44 PM PDT 24 Jul 19 04:53:48 PM PDT 24 1672292935 ps
T389 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1798530131 Jul 19 04:53:47 PM PDT 24 Jul 19 04:53:51 PM PDT 24 488798409 ps
T390 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4183485560 Jul 19 04:53:52 PM PDT 24 Jul 19 04:54:01 PM PDT 24 2169998664 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1417920916 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:12 PM PDT 24 498202233 ps
T195 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.117304694 Jul 19 04:54:18 PM PDT 24 Jul 19 04:54:25 PM PDT 24 8693041466 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4089357275 Jul 19 04:53:54 PM PDT 24 Jul 19 04:54:00 PM PDT 24 536566281 ps
T393 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3393102778 Jul 19 04:54:01 PM PDT 24 Jul 19 04:54:10 PM PDT 24 4472170296 ps
T394 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2743462994 Jul 19 04:54:21 PM PDT 24 Jul 19 04:54:23 PM PDT 24 537755342 ps
T395 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1113253643 Jul 19 04:53:54 PM PDT 24 Jul 19 04:53:59 PM PDT 24 309380304 ps
T396 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3792645794 Jul 19 04:54:00 PM PDT 24 Jul 19 04:54:03 PM PDT 24 653694126 ps
T397 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1503115205 Jul 19 04:54:20 PM PDT 24 Jul 19 04:54:23 PM PDT 24 470568066 ps
T398 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2900885085 Jul 19 04:54:20 PM PDT 24 Jul 19 04:54:23 PM PDT 24 376002720 ps
T399 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.511974261 Jul 19 04:54:30 PM PDT 24 Jul 19 04:54:34 PM PDT 24 426724958 ps
T400 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.884679465 Jul 19 04:54:26 PM PDT 24 Jul 19 04:54:28 PM PDT 24 314232595 ps
T401 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.96851381 Jul 19 04:54:18 PM PDT 24 Jul 19 04:54:21 PM PDT 24 1288716006 ps
T402 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3048977799 Jul 19 04:54:27 PM PDT 24 Jul 19 04:54:30 PM PDT 24 382141168 ps
T197 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1384764955 Jul 19 04:54:28 PM PDT 24 Jul 19 04:54:42 PM PDT 24 7807647412 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1635146353 Jul 19 04:53:52 PM PDT 24 Jul 19 04:53:56 PM PDT 24 433416572 ps
T404 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1670305397 Jul 19 04:54:09 PM PDT 24 Jul 19 04:54:11 PM PDT 24 442220528 ps
T405 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3406460989 Jul 19 04:54:00 PM PDT 24 Jul 19 04:54:04 PM PDT 24 501419231 ps
T406 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1884426143 Jul 19 04:54:19 PM PDT 24 Jul 19 04:54:28 PM PDT 24 7756797448 ps
T407 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2965654902 Jul 19 04:53:56 PM PDT 24 Jul 19 04:54:04 PM PDT 24 2436506075 ps
T408 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2811164570 Jul 19 04:54:28 PM PDT 24 Jul 19 04:54:32 PM PDT 24 324762260 ps
T409 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3271143902 Jul 19 04:53:53 PM PDT 24 Jul 19 04:53:58 PM PDT 24 439373935 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2010079293 Jul 19 04:54:10 PM PDT 24 Jul 19 04:54:27 PM PDT 24 8916060448 ps
T411 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3076667809 Jul 19 04:53:53 PM PDT 24 Jul 19 04:53:59 PM PDT 24 864567824 ps
T412 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1401693139 Jul 19 04:53:52 PM PDT 24 Jul 19 04:53:58 PM PDT 24 358125496 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2467022825 Jul 19 04:54:00 PM PDT 24 Jul 19 04:54:04 PM PDT 24 395885969 ps
T414 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1739900739 Jul 19 04:54:01 PM PDT 24 Jul 19 04:54:05 PM PDT 24 4486524553 ps
T415 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1456119631 Jul 19 04:54:11 PM PDT 24 Jul 19 04:54:13 PM PDT 24 372895662 ps
T416 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.20793218 Jul 19 04:54:30 PM PDT 24 Jul 19 04:54:35 PM PDT 24 386484162 ps
T417 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3218837691 Jul 19 04:54:25 PM PDT 24 Jul 19 04:54:28 PM PDT 24 544865493 ps
T418 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3109314051 Jul 19 04:54:25 PM PDT 24 Jul 19 04:54:27 PM PDT 24 320899075 ps

Test location /workspace/coverage/default/30.aon_timer_jump.4234522763
Short name T7
Test name
Test status
Simulation time 586518101 ps
CPU time 0.66 seconds
Started Jul 19 04:38:54 PM PDT 24
Finished Jul 19 04:39:31 PM PDT 24
Peak memory 196308 kb
Host smart-06bbfaf5-eda5-4fab-8886-8dfe97224891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234522763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4234522763
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1909867518
Short name T11
Test name
Test status
Simulation time 121640222086 ps
CPU time 256.05 seconds
Started Jul 19 04:38:57 PM PDT 24
Finished Jul 19 04:43:53 PM PDT 24
Peak memory 208900 kb
Host smart-63fa0368-6739-477c-98a5-bf7e0ab43ef1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909867518 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1909867518
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.825154468
Short name T43
Test name
Test status
Simulation time 131155874305 ps
CPU time 564.39 seconds
Started Jul 19 04:39:09 PM PDT 24
Finished Jul 19 04:49:11 PM PDT 24
Peak memory 204404 kb
Host smart-f796781c-160f-443c-95a7-f605ae3d30fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825154468 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.825154468
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2480886822
Short name T17
Test name
Test status
Simulation time 4196535059 ps
CPU time 4.53 seconds
Started Jul 19 04:38:39 PM PDT 24
Finished Jul 19 04:38:56 PM PDT 24
Peak memory 215116 kb
Host smart-0195ef1d-cd5a-40da-91cd-da9c9dc29d2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480886822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2480886822
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.619954329
Short name T16
Test name
Test status
Simulation time 316859076282 ps
CPU time 525.7 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:47:39 PM PDT 24
Peak memory 211844 kb
Host smart-b4749e92-0bad-4209-9806-5540cdcab3b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619954329 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.619954329
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3288439697
Short name T53
Test name
Test status
Simulation time 16387414202 ps
CPU time 27.01 seconds
Started Jul 19 04:38:54 PM PDT 24
Finished Jul 19 04:39:59 PM PDT 24
Peak memory 197848 kb
Host smart-85723f7f-811b-4aa4-b825-353da45db27b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288439697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3288439697
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3160943970
Short name T44
Test name
Test status
Simulation time 985071807850 ps
CPU time 1018.54 seconds
Started Jul 19 04:38:41 PM PDT 24
Finished Jul 19 04:55:53 PM PDT 24
Peak memory 214480 kb
Host smart-28bc1d3c-c8a0-4c6d-b8e4-15919f647637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160943970 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3160943970
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3213621782
Short name T38
Test name
Test status
Simulation time 7858339338 ps
CPU time 6.53 seconds
Started Jul 19 04:54:01 PM PDT 24
Finished Jul 19 04:54:10 PM PDT 24
Peak memory 198740 kb
Host smart-ffb8462e-91b4-468c-8264-a578126d0813
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213621782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3213621782
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.271297054
Short name T93
Test name
Test status
Simulation time 332422268615 ps
CPU time 467.76 seconds
Started Jul 19 04:38:43 PM PDT 24
Finished Jul 19 04:46:44 PM PDT 24
Peak memory 203660 kb
Host smart-28493cf0-f083-4b29-b02b-f570df662a6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271297054 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.271297054
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1251594270
Short name T79
Test name
Test status
Simulation time 615075569299 ps
CPU time 292.13 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:44:27 PM PDT 24
Peak memory 209380 kb
Host smart-79a5ed37-08b4-47ac-b574-2e4dc1bd917e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251594270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1251594270
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.924517642
Short name T76
Test name
Test status
Simulation time 70216597077 ps
CPU time 315.61 seconds
Started Jul 19 04:38:55 PM PDT 24
Finished Jul 19 04:44:48 PM PDT 24
Peak memory 198240 kb
Host smart-9ef9127f-861e-4e83-b56a-0accc25dd9f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924517642 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.924517642
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1909445848
Short name T82
Test name
Test status
Simulation time 77045648384 ps
CPU time 291.59 seconds
Started Jul 19 04:39:03 PM PDT 24
Finished Jul 19 04:44:36 PM PDT 24
Peak memory 200400 kb
Host smart-5d63f10e-f1f1-403e-883f-2d084be2cd86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909445848 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1909445848
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3670590356
Short name T77
Test name
Test status
Simulation time 501549074263 ps
CPU time 934.48 seconds
Started Jul 19 04:39:19 PM PDT 24
Finished Jul 19 04:55:21 PM PDT 24
Peak memory 208920 kb
Host smart-8ebf6bb3-b6e8-4269-8f40-96d79e2d09cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670590356 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3670590356
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1591882153
Short name T14
Test name
Test status
Simulation time 246857672440 ps
CPU time 362.13 seconds
Started Jul 19 04:38:37 PM PDT 24
Finished Jul 19 04:44:50 PM PDT 24
Peak memory 197888 kb
Host smart-95651ad1-b054-4e7d-a048-d0059d77048b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591882153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1591882153
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.462741386
Short name T8
Test name
Test status
Simulation time 335098310194 ps
CPU time 497.06 seconds
Started Jul 19 04:39:09 PM PDT 24
Finished Jul 19 04:48:03 PM PDT 24
Peak memory 192632 kb
Host smart-04e8270c-0074-4e7f-8ce0-941c1d7b0dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462741386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.462741386
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3698793705
Short name T97
Test name
Test status
Simulation time 452848713580 ps
CPU time 147.93 seconds
Started Jul 19 04:38:46 PM PDT 24
Finished Jul 19 04:41:27 PM PDT 24
Peak memory 192560 kb
Host smart-29659a5e-5172-45fc-89b0-8bca429fe812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698793705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3698793705
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2393570674
Short name T94
Test name
Test status
Simulation time 487012064884 ps
CPU time 400.2 seconds
Started Jul 19 04:38:46 PM PDT 24
Finished Jul 19 04:45:40 PM PDT 24
Peak memory 197880 kb
Host smart-5d91ac15-9855-4abe-99cc-4ea9f5e4eaec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393570674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2393570674
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1583005475
Short name T86
Test name
Test status
Simulation time 106989094306 ps
CPU time 306.36 seconds
Started Jul 19 04:38:45 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 201096 kb
Host smart-a97fc865-2b99-45af-a6ce-36e0e09457f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583005475 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1583005475
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.546774279
Short name T159
Test name
Test status
Simulation time 27900194918 ps
CPU time 285.74 seconds
Started Jul 19 04:39:03 PM PDT 24
Finished Jul 19 04:44:31 PM PDT 24
Peak memory 213920 kb
Host smart-709ad2b5-baf2-4a66-af02-e8a8933336ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546774279 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.546774279
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.392221281
Short name T141
Test name
Test status
Simulation time 179410526812 ps
CPU time 284.41 seconds
Started Jul 19 04:39:13 PM PDT 24
Finished Jul 19 04:44:29 PM PDT 24
Peak memory 192648 kb
Host smart-c805a27b-3564-47c3-826a-0b0f046297f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392221281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.392221281
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3186276783
Short name T54
Test name
Test status
Simulation time 351793134232 ps
CPU time 639.77 seconds
Started Jul 19 04:38:45 PM PDT 24
Finished Jul 19 04:49:38 PM PDT 24
Peak memory 204844 kb
Host smart-abd5a2d4-0c72-40d2-9b7c-3df65a9e4620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186276783 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3186276783
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.958433565
Short name T98
Test name
Test status
Simulation time 204397794621 ps
CPU time 144.61 seconds
Started Jul 19 04:39:11 PM PDT 24
Finished Jul 19 04:42:09 PM PDT 24
Peak memory 192764 kb
Host smart-c839044b-593c-4504-839d-cac39380f188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958433565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.958433565
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1250076638
Short name T125
Test name
Test status
Simulation time 154251598408 ps
CPU time 444.98 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:47:00 PM PDT 24
Peak memory 202900 kb
Host smart-06f982f0-2cf7-4802-bd5b-501d8f1dc2b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250076638 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1250076638
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2133290884
Short name T80
Test name
Test status
Simulation time 539038642351 ps
CPU time 440.06 seconds
Started Jul 19 04:38:49 PM PDT 24
Finished Jul 19 04:46:43 PM PDT 24
Peak memory 211576 kb
Host smart-2cdf2e75-2aa7-49e9-a574-c6f41ceb1d00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133290884 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2133290884
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.529200256
Short name T111
Test name
Test status
Simulation time 168343319724 ps
CPU time 428.01 seconds
Started Jul 19 04:38:47 PM PDT 24
Finished Jul 19 04:46:10 PM PDT 24
Peak memory 211160 kb
Host smart-92c55c86-fd0c-4bfd-a539-9285299e7159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529200256 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.529200256
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.623184166
Short name T33
Test name
Test status
Simulation time 130961865796 ps
CPU time 49.41 seconds
Started Jul 19 04:39:07 PM PDT 24
Finished Jul 19 04:40:35 PM PDT 24
Peak memory 197876 kb
Host smart-783cb106-b621-4b82-9752-8d89eb9661f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623184166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.623184166
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1059796563
Short name T143
Test name
Test status
Simulation time 68965621835 ps
CPU time 23.9 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:39:59 PM PDT 24
Peak memory 191492 kb
Host smart-7ef4030b-a38a-41da-9186-979e39648d75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059796563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1059796563
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1248635372
Short name T47
Test name
Test status
Simulation time 173930725053 ps
CPU time 471.7 seconds
Started Jul 19 04:38:43 PM PDT 24
Finished Jul 19 04:46:48 PM PDT 24
Peak memory 213556 kb
Host smart-80658701-ae63-417a-bc13-2ac785021d9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248635372 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1248635372
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1272019240
Short name T110
Test name
Test status
Simulation time 439714431817 ps
CPU time 918.62 seconds
Started Jul 19 04:38:51 PM PDT 24
Finished Jul 19 04:54:41 PM PDT 24
Peak memory 214608 kb
Host smart-911da4bc-fff8-423f-ac00-fd1e7784df2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272019240 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1272019240
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2562427911
Short name T46
Test name
Test status
Simulation time 135808140596 ps
CPU time 350.59 seconds
Started Jul 19 04:39:08 PM PDT 24
Finished Jul 19 04:45:37 PM PDT 24
Peak memory 210276 kb
Host smart-07630015-5bbf-4b33-b941-2b5c0b790e76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562427911 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2562427911
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3261190304
Short name T102
Test name
Test status
Simulation time 297816347072 ps
CPU time 90.72 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:41:04 PM PDT 24
Peak memory 192800 kb
Host smart-d609f3f3-13d5-4b1e-aea6-38d75fdea3a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261190304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3261190304
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1681695483
Short name T55
Test name
Test status
Simulation time 514779678199 ps
CPU time 830.92 seconds
Started Jul 19 04:39:05 PM PDT 24
Finished Jul 19 04:53:37 PM PDT 24
Peak memory 214480 kb
Host smart-d36aa3b7-0ef7-4473-960c-d9465d8dd274
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681695483 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1681695483
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1008758655
Short name T149
Test name
Test status
Simulation time 58727289929 ps
CPU time 110.41 seconds
Started Jul 19 04:38:53 PM PDT 24
Finished Jul 19 04:41:23 PM PDT 24
Peak memory 198160 kb
Host smart-f94b8d3b-0b4f-4dac-b264-49a28e8860ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008758655 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1008758655
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1149468790
Short name T100
Test name
Test status
Simulation time 60275432095 ps
CPU time 103.4 seconds
Started Jul 19 04:38:52 PM PDT 24
Finished Jul 19 04:41:17 PM PDT 24
Peak memory 198280 kb
Host smart-28c88d78-77f9-48df-8b8a-e5f425f6b8fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149468790 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1149468790
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1070492370
Short name T15
Test name
Test status
Simulation time 30552164908 ps
CPU time 158.09 seconds
Started Jul 19 04:38:31 PM PDT 24
Finished Jul 19 04:41:18 PM PDT 24
Peak memory 206384 kb
Host smart-71139a28-c30c-4f7a-aec7-c0d8dd217dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070492370 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1070492370
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3800703650
Short name T124
Test name
Test status
Simulation time 183345082781 ps
CPU time 250.46 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:43:46 PM PDT 24
Peak memory 183944 kb
Host smart-e1827be0-cb45-41b3-b0de-479f80021be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800703650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3800703650
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.43931042
Short name T106
Test name
Test status
Simulation time 3800757667 ps
CPU time 3.99 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:50 PM PDT 24
Peak memory 197896 kb
Host smart-aa590fb3-f2db-4c14-89ab-e80a5c589639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43931042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_al
l.43931042
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3412865373
Short name T121
Test name
Test status
Simulation time 110539916978 ps
CPU time 147.67 seconds
Started Jul 19 04:39:03 PM PDT 24
Finished Jul 19 04:42:13 PM PDT 24
Peak memory 192448 kb
Host smart-ae92384d-20e4-4b31-96f1-279273845106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412865373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3412865373
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2454777596
Short name T133
Test name
Test status
Simulation time 141005490797 ps
CPU time 211.95 seconds
Started Jul 19 04:38:53 PM PDT 24
Finished Jul 19 04:43:05 PM PDT 24
Peak memory 192592 kb
Host smart-9c8332f9-91db-4ba5-8d1b-54799cfcc846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454777596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2454777596
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.496120572
Short name T99
Test name
Test status
Simulation time 15813908054 ps
CPU time 108.95 seconds
Started Jul 19 04:38:35 PM PDT 24
Finished Jul 19 04:40:35 PM PDT 24
Peak memory 206332 kb
Host smart-41640d65-24b5-4dd0-b67d-ad1875698d8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496120572 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.496120572
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1970954455
Short name T85
Test name
Test status
Simulation time 82169276716 ps
CPU time 310.63 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:44:57 PM PDT 24
Peak memory 209296 kb
Host smart-3e9e1b87-c654-4f45-a89e-06a4c912cbcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970954455 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1970954455
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1664744120
Short name T129
Test name
Test status
Simulation time 142574876341 ps
CPU time 201.68 seconds
Started Jul 19 04:38:38 PM PDT 24
Finished Jul 19 04:42:10 PM PDT 24
Peak memory 197892 kb
Host smart-6a826076-84af-4f72-b82a-5196261d88c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664744120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1664744120
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.848095327
Short name T170
Test name
Test status
Simulation time 135520386868 ps
CPU time 718.66 seconds
Started Jul 19 04:39:08 PM PDT 24
Finished Jul 19 04:51:45 PM PDT 24
Peak memory 214684 kb
Host smart-a4b7d475-6d05-4a04-990e-e8f12eb48482
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848095327 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.848095327
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3179244900
Short name T78
Test name
Test status
Simulation time 286586541067 ps
CPU time 424.76 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:46:51 PM PDT 24
Peak memory 210788 kb
Host smart-149a17de-41dc-460f-b45e-cd2d4ca404df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179244900 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3179244900
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1700683994
Short name T139
Test name
Test status
Simulation time 359496492192 ps
CPU time 272.56 seconds
Started Jul 19 04:38:54 PM PDT 24
Finished Jul 19 04:44:05 PM PDT 24
Peak memory 192528 kb
Host smart-af4fd689-bc39-4d3b-8bd7-2ecd914acdd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700683994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1700683994
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.4145411634
Short name T115
Test name
Test status
Simulation time 55661045008 ps
CPU time 430.59 seconds
Started Jul 19 04:39:06 PM PDT 24
Finished Jul 19 04:46:57 PM PDT 24
Peak memory 209500 kb
Host smart-671b865b-55e8-4278-9140-97e83b697b98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145411634 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.4145411634
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3921684589
Short name T81
Test name
Test status
Simulation time 217536721481 ps
CPU time 465.69 seconds
Started Jul 19 04:39:07 PM PDT 24
Finished Jul 19 04:47:32 PM PDT 24
Peak memory 211472 kb
Host smart-ad83174b-6e1c-4919-aac8-03e97a9a44ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921684589 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3921684589
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2014590177
Short name T112
Test name
Test status
Simulation time 292775538519 ps
CPU time 478.37 seconds
Started Jul 19 04:38:44 PM PDT 24
Finished Jul 19 04:46:55 PM PDT 24
Peak memory 191536 kb
Host smart-152c31a4-97de-4602-9c88-a878a1591f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014590177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2014590177
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.279810676
Short name T50
Test name
Test status
Simulation time 65351860695 ps
CPU time 32.18 seconds
Started Jul 19 04:38:48 PM PDT 24
Finished Jul 19 04:39:45 PM PDT 24
Peak memory 197904 kb
Host smart-e1f54447-ec6a-41bf-a029-4c4e6edbaf2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279810676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.279810676
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1191290666
Short name T9
Test name
Test status
Simulation time 84079667691 ps
CPU time 33.1 seconds
Started Jul 19 04:38:46 PM PDT 24
Finished Jul 19 04:39:33 PM PDT 24
Peak memory 192596 kb
Host smart-4b4c9408-1125-4c57-a4f0-28394921931a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191290666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1191290666
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1182239349
Short name T140
Test name
Test status
Simulation time 18966136480 ps
CPU time 79.08 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:41:05 PM PDT 24
Peak memory 206388 kb
Host smart-5414b35b-c010-4e83-a322-56aae5a5fb5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182239349 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1182239349
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1995836556
Short name T104
Test name
Test status
Simulation time 169218048873 ps
CPU time 352.1 seconds
Started Jul 19 04:38:42 PM PDT 24
Finished Jul 19 04:44:47 PM PDT 24
Peak memory 201548 kb
Host smart-2860d2da-5e92-4384-a3ad-1fc2f97676b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995836556 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1995836556
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2309612231
Short name T146
Test name
Test status
Simulation time 42419307602 ps
CPU time 54.72 seconds
Started Jul 19 04:38:44 PM PDT 24
Finished Jul 19 04:39:52 PM PDT 24
Peak memory 197872 kb
Host smart-f0e866e3-bb38-4924-ac86-527fdd51408b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309612231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2309612231
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4239005543
Short name T84
Test name
Test status
Simulation time 104179178948 ps
CPU time 208.27 seconds
Started Jul 19 04:38:52 PM PDT 24
Finished Jul 19 04:43:02 PM PDT 24
Peak memory 208200 kb
Host smart-53f76732-b85b-4154-b388-ad9bf5aed621
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239005543 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4239005543
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.4068173717
Short name T103
Test name
Test status
Simulation time 70803627801 ps
CPU time 93.54 seconds
Started Jul 19 04:38:54 PM PDT 24
Finished Jul 19 04:41:04 PM PDT 24
Peak memory 192604 kb
Host smart-7b8d1f7d-7ece-4c1f-b1ec-ca2b97bcd306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068173717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.4068173717
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.391397316
Short name T83
Test name
Test status
Simulation time 41655238353 ps
CPU time 145.89 seconds
Started Jul 19 04:38:47 PM PDT 24
Finished Jul 19 04:41:29 PM PDT 24
Peak memory 206384 kb
Host smart-4798e5c8-4c2c-4d03-8621-8b39c21cff8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391397316 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.391397316
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2012672295
Short name T108
Test name
Test status
Simulation time 15410783197 ps
CPU time 5.99 seconds
Started Jul 19 04:39:01 PM PDT 24
Finished Jul 19 04:39:51 PM PDT 24
Peak memory 197876 kb
Host smart-a40a0f8f-129e-4e00-817e-6ebb8c78859e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012672295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2012672295
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.879430923
Short name T105
Test name
Test status
Simulation time 200887279802 ps
CPU time 294.41 seconds
Started Jul 19 04:38:58 PM PDT 24
Finished Jul 19 04:44:39 PM PDT 24
Peak memory 197880 kb
Host smart-54ec00a3-744c-4915-b26f-08b8675ec2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879430923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.879430923
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2104181255
Short name T132
Test name
Test status
Simulation time 83547167261 ps
CPU time 8.18 seconds
Started Jul 19 04:38:42 PM PDT 24
Finished Jul 19 04:39:03 PM PDT 24
Peak memory 197880 kb
Host smart-8708cfc6-335d-4ea9-903c-049b406c5f03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104181255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2104181255
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3095967211
Short name T127
Test name
Test status
Simulation time 21739495108 ps
CPU time 25.01 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:39:18 PM PDT 24
Peak memory 192572 kb
Host smart-2c43a0a6-b110-41bb-a410-81dfc63aeaee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095967211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3095967211
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2564607124
Short name T130
Test name
Test status
Simulation time 91502640027 ps
CPU time 142.68 seconds
Started Jul 19 04:39:07 PM PDT 24
Finished Jul 19 04:42:09 PM PDT 24
Peak memory 191524 kb
Host smart-683dfe37-6a70-4aca-8aa1-e32a6e7adea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564607124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2564607124
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2646193223
Short name T128
Test name
Test status
Simulation time 107455712306 ps
CPU time 146.16 seconds
Started Jul 19 04:39:07 PM PDT 24
Finished Jul 19 04:42:12 PM PDT 24
Peak memory 197880 kb
Host smart-792103f9-6932-4de8-944c-c9f30c6d7102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646193223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2646193223
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.451353621
Short name T64
Test name
Test status
Simulation time 598498361 ps
CPU time 1.24 seconds
Started Jul 19 04:53:47 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 195136 kb
Host smart-f6c82a9c-1452-42a4-bb67-2d77410e857b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451353621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.451353621
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3133979154
Short name T71
Test name
Test status
Simulation time 343400371 ps
CPU time 0.72 seconds
Started Jul 19 04:53:46 PM PDT 24
Finished Jul 19 04:53:50 PM PDT 24
Peak memory 193692 kb
Host smart-935c971d-28ed-4f10-af80-1ed4989a8d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133979154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3133979154
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1729386688
Short name T166
Test name
Test status
Simulation time 161778180201 ps
CPU time 226.75 seconds
Started Jul 19 04:38:43 PM PDT 24
Finished Jul 19 04:42:42 PM PDT 24
Peak memory 197844 kb
Host smart-667dc97e-e18f-46db-9175-2aeaf37f61f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729386688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1729386688
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1137935563
Short name T114
Test name
Test status
Simulation time 80878039633 ps
CPU time 167.14 seconds
Started Jul 19 04:39:11 PM PDT 24
Finished Jul 19 04:42:32 PM PDT 24
Peak memory 199280 kb
Host smart-975e3729-44a9-4cea-9180-b4bd76eba560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137935563 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1137935563
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.887679056
Short name T174
Test name
Test status
Simulation time 141204494457 ps
CPU time 46.72 seconds
Started Jul 19 04:38:23 PM PDT 24
Finished Jul 19 04:39:14 PM PDT 24
Peak memory 198000 kb
Host smart-ac6fce6d-43d8-443d-a64f-2e450ee885f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887679056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.887679056
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2687851545
Short name T48
Test name
Test status
Simulation time 14322963778 ps
CPU time 102.17 seconds
Started Jul 19 04:38:31 PM PDT 24
Finished Jul 19 04:40:22 PM PDT 24
Peak memory 206424 kb
Host smart-8d76ef08-cf95-487a-9a32-d11d1ee054c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687851545 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2687851545
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.977674496
Short name T136
Test name
Test status
Simulation time 176036442637 ps
CPU time 59.14 seconds
Started Jul 19 04:38:38 PM PDT 24
Finished Jul 19 04:39:49 PM PDT 24
Peak memory 192072 kb
Host smart-a9c43cd5-005b-40dd-bc4e-de8403f47b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977674496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.977674496
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2512724702
Short name T2
Test name
Test status
Simulation time 40910863200 ps
CPU time 55.23 seconds
Started Jul 19 04:38:59 PM PDT 24
Finished Jul 19 04:40:34 PM PDT 24
Peak memory 191512 kb
Host smart-6ce3c689-474f-4d75-9a02-9e06825c8097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512724702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2512724702
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1941891277
Short name T96
Test name
Test status
Simulation time 51934893139 ps
CPU time 412.76 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:45:45 PM PDT 24
Peak memory 200284 kb
Host smart-59f1329c-d6c0-4a8b-96e1-4f368ce0cc7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941891277 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1941891277
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.287433841
Short name T160
Test name
Test status
Simulation time 432474335202 ps
CPU time 173.73 seconds
Started Jul 19 04:39:06 PM PDT 24
Finished Jul 19 04:42:40 PM PDT 24
Peak memory 197876 kb
Host smart-f8b9511a-e3d9-44ee-9336-186f3af0808d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287433841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.287433841
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1311410310
Short name T119
Test name
Test status
Simulation time 490765142110 ps
CPU time 681.31 seconds
Started Jul 19 04:38:44 PM PDT 24
Finished Jul 19 04:50:18 PM PDT 24
Peak memory 192640 kb
Host smart-7fce840c-10b0-4053-8bf6-181b0cf63d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311410310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1311410310
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.740461323
Short name T101
Test name
Test status
Simulation time 415374294 ps
CPU time 0.85 seconds
Started Jul 19 04:38:34 PM PDT 24
Finished Jul 19 04:38:45 PM PDT 24
Peak memory 196284 kb
Host smart-e694c8f3-b47b-4793-b975-430c7fa866dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740461323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.740461323
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3276369870
Short name T28
Test name
Test status
Simulation time 41737260497 ps
CPU time 16.1 seconds
Started Jul 19 04:38:29 PM PDT 24
Finished Jul 19 04:38:52 PM PDT 24
Peak memory 197840 kb
Host smart-a1173d68-82d6-480c-be78-7b337d53035e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276369870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3276369870
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.924111414
Short name T31
Test name
Test status
Simulation time 407918296 ps
CPU time 0.8 seconds
Started Jul 19 04:39:02 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 196368 kb
Host smart-b1ddade7-89c4-4b8c-a93d-c925ac3fec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924111414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.924111414
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.706567856
Short name T150
Test name
Test status
Simulation time 194522814639 ps
CPU time 287.58 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:44:34 PM PDT 24
Peak memory 192548 kb
Host smart-4049ec06-9e31-403a-96c4-0d2dde554079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706567856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.706567856
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1681593052
Short name T175
Test name
Test status
Simulation time 339418636041 ps
CPU time 533.03 seconds
Started Jul 19 04:39:13 PM PDT 24
Finished Jul 19 04:48:38 PM PDT 24
Peak memory 184064 kb
Host smart-75b00f3d-8786-4ab0-91d7-69fe10ff2f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681593052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1681593052
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1369524591
Short name T137
Test name
Test status
Simulation time 410692961 ps
CPU time 0.74 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:39:45 PM PDT 24
Peak memory 196268 kb
Host smart-bf4a7278-2d5f-4d3c-a647-63a338cfdb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369524591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1369524591
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2152066231
Short name T135
Test name
Test status
Simulation time 440046328 ps
CPU time 0.72 seconds
Started Jul 19 04:38:50 PM PDT 24
Finished Jul 19 04:39:22 PM PDT 24
Peak memory 196228 kb
Host smart-c5057538-c3cc-47c0-88a5-3eeccd2e9086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152066231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2152066231
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3255173282
Short name T118
Test name
Test status
Simulation time 173107438653 ps
CPU time 74.53 seconds
Started Jul 19 04:39:03 PM PDT 24
Finished Jul 19 04:40:59 PM PDT 24
Peak memory 191528 kb
Host smart-195bc433-fa32-471b-84b1-297fd801d8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255173282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3255173282
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3281987703
Short name T147
Test name
Test status
Simulation time 42638610078 ps
CPU time 437.75 seconds
Started Jul 19 04:38:55 PM PDT 24
Finished Jul 19 04:46:51 PM PDT 24
Peak memory 206368 kb
Host smart-fbe0043f-b6c1-4aa5-8a89-c6d775188d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281987703 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3281987703
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4087716313
Short name T144
Test name
Test status
Simulation time 489686954 ps
CPU time 0.78 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:38:54 PM PDT 24
Peak memory 196216 kb
Host smart-827a1cdb-32df-4cde-b44e-07af168f7631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087716313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4087716313
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.369775107
Short name T157
Test name
Test status
Simulation time 15390108638 ps
CPU time 83.27 seconds
Started Jul 19 04:38:44 PM PDT 24
Finished Jul 19 04:40:20 PM PDT 24
Peak memory 206440 kb
Host smart-66f8ba5a-fd90-4db9-938c-34c1394ea8e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369775107 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.369775107
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3733642234
Short name T122
Test name
Test status
Simulation time 517452158 ps
CPU time 1.32 seconds
Started Jul 19 04:39:06 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196264 kb
Host smart-7532ba38-e911-4326-9b18-6dafde450f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733642234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3733642234
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3895043492
Short name T154
Test name
Test status
Simulation time 64760391059 ps
CPU time 56.12 seconds
Started Jul 19 04:38:55 PM PDT 24
Finished Jul 19 04:40:29 PM PDT 24
Peak memory 191520 kb
Host smart-7a615496-4b07-40eb-8de2-e0d060b1ab0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895043492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3895043492
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1043586014
Short name T134
Test name
Test status
Simulation time 487576213 ps
CPU time 0.94 seconds
Started Jul 19 04:38:29 PM PDT 24
Finished Jul 19 04:38:37 PM PDT 24
Peak memory 196364 kb
Host smart-87ad0f7a-8059-4ba4-bde5-749d7018a80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043586014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1043586014
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2895099847
Short name T32
Test name
Test status
Simulation time 494743747 ps
CPU time 1.41 seconds
Started Jul 19 04:39:14 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 196472 kb
Host smart-2600aebd-c076-47df-879e-7166b77a5177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895099847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2895099847
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3415111094
Short name T107
Test name
Test status
Simulation time 449700775 ps
CPU time 1.22 seconds
Started Jul 19 04:38:45 PM PDT 24
Finished Jul 19 04:38:59 PM PDT 24
Peak memory 196328 kb
Host smart-1b31c0c9-56ce-44f3-ad1d-8fc03d4a601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415111094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3415111094
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2657133227
Short name T117
Test name
Test status
Simulation time 547872679 ps
CPU time 0.79 seconds
Started Jul 19 04:38:49 PM PDT 24
Finished Jul 19 04:39:21 PM PDT 24
Peak memory 196344 kb
Host smart-93501dc1-7d89-4c9d-b67e-0eb86dcd483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657133227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2657133227
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2246381123
Short name T142
Test name
Test status
Simulation time 399548705 ps
CPU time 0.72 seconds
Started Jul 19 04:38:35 PM PDT 24
Finished Jul 19 04:38:46 PM PDT 24
Peak memory 196352 kb
Host smart-1a016e48-b3ce-44f5-a65a-5365fefba5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246381123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2246381123
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.730869493
Short name T87
Test name
Test status
Simulation time 693912072909 ps
CPU time 688.93 seconds
Started Jul 19 04:38:49 PM PDT 24
Finished Jul 19 04:50:52 PM PDT 24
Peak memory 205196 kb
Host smart-458e0007-6f5c-4e87-a31f-d064da8d7d7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730869493 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.730869493
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.724517746
Short name T152
Test name
Test status
Simulation time 188802276716 ps
CPU time 239.13 seconds
Started Jul 19 04:38:45 PM PDT 24
Finished Jul 19 04:42:57 PM PDT 24
Peak memory 200384 kb
Host smart-47885e17-7f3b-4642-80a8-6771343e9f5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724517746 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.724517746
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.330019485
Short name T131
Test name
Test status
Simulation time 509939535 ps
CPU time 1.26 seconds
Started Jul 19 04:38:43 PM PDT 24
Finished Jul 19 04:38:58 PM PDT 24
Peak memory 196316 kb
Host smart-1d847b7f-0eee-4205-90ed-628c63b631e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330019485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.330019485
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.159207737
Short name T172
Test name
Test status
Simulation time 247069794344 ps
CPU time 203.92 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:42:16 PM PDT 24
Peak memory 191460 kb
Host smart-592df800-cb75-4809-80a8-82aa24f679d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159207737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.159207737
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.31303166
Short name T120
Test name
Test status
Simulation time 423329404 ps
CPU time 0.65 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196292 kb
Host smart-4043c7f5-4ee7-4a2b-a49e-4c60e515cad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31303166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.31303166
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3010461082
Short name T148
Test name
Test status
Simulation time 459525606 ps
CPU time 1.24 seconds
Started Jul 19 04:39:05 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196236 kb
Host smart-bc13b223-358e-4434-aaa2-1f1b4606335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010461082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3010461082
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1485577400
Short name T49
Test name
Test status
Simulation time 55227130958 ps
CPU time 156.81 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:42:23 PM PDT 24
Peak memory 214568 kb
Host smart-3214ea96-f1e4-460c-b407-c4978f101f4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485577400 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1485577400
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3704717265
Short name T113
Test name
Test status
Simulation time 455242797 ps
CPU time 0.96 seconds
Started Jul 19 04:38:29 PM PDT 24
Finished Jul 19 04:38:37 PM PDT 24
Peak memory 196288 kb
Host smart-770c70fb-be40-41b3-84b9-de8176d558ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704717265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3704717265
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.474712890
Short name T126
Test name
Test status
Simulation time 549272740 ps
CPU time 1.09 seconds
Started Jul 19 04:38:47 PM PDT 24
Finished Jul 19 04:39:01 PM PDT 24
Peak memory 196272 kb
Host smart-b655d15d-08e9-4e94-94c8-f1ffbcaeb628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474712890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.474712890
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1355228880
Short name T116
Test name
Test status
Simulation time 454268366 ps
CPU time 1.33 seconds
Started Jul 19 04:38:31 PM PDT 24
Finished Jul 19 04:38:41 PM PDT 24
Peak memory 196292 kb
Host smart-22ee6075-b77d-473f-9f80-94ae0fad3b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355228880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1355228880
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3258793030
Short name T173
Test name
Test status
Simulation time 306314715815 ps
CPU time 98.67 seconds
Started Jul 19 04:38:37 PM PDT 24
Finished Jul 19 04:40:26 PM PDT 24
Peak memory 192612 kb
Host smart-4663f946-a616-4339-969b-168b75b597e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258793030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3258793030
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1803354355
Short name T109
Test name
Test status
Simulation time 65945564877 ps
CPU time 13.31 seconds
Started Jul 19 04:38:46 PM PDT 24
Finished Jul 19 04:39:12 PM PDT 24
Peak memory 197864 kb
Host smart-a5b62243-d56a-430f-aa9a-e02e462f2fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803354355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1803354355
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.810793231
Short name T30
Test name
Test status
Simulation time 498587519 ps
CPU time 0.74 seconds
Started Jul 19 04:39:00 PM PDT 24
Finished Jul 19 04:39:40 PM PDT 24
Peak memory 196264 kb
Host smart-4322e739-78cb-41f9-8976-3f787c691c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810793231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.810793231
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4174644890
Short name T92
Test name
Test status
Simulation time 367248712 ps
CPU time 0.74 seconds
Started Jul 19 04:38:42 PM PDT 24
Finished Jul 19 04:38:55 PM PDT 24
Peak memory 196316 kb
Host smart-432c9653-d467-4697-a47d-4700a8006310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174644890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4174644890
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.190892828
Short name T182
Test name
Test status
Simulation time 172558288977 ps
CPU time 237.76 seconds
Started Jul 19 04:38:55 PM PDT 24
Finished Jul 19 04:43:30 PM PDT 24
Peak memory 197828 kb
Host smart-64a20418-0ba5-4f4e-8554-a5c0d016960b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190892828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.190892828
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2720836746
Short name T151
Test name
Test status
Simulation time 594102315 ps
CPU time 1.07 seconds
Started Jul 19 04:39:06 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196260 kb
Host smart-2977e70d-1961-43b3-ba62-37e482778a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720836746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2720836746
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.864135686
Short name T123
Test name
Test status
Simulation time 526544155 ps
CPU time 0.74 seconds
Started Jul 19 04:39:19 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196268 kb
Host smart-c89763b4-9198-4485-85ff-8362d98aebd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864135686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.864135686
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3512174627
Short name T163
Test name
Test status
Simulation time 257376949263 ps
CPU time 400.25 seconds
Started Jul 19 04:39:19 PM PDT 24
Finished Jul 19 04:46:26 PM PDT 24
Peak memory 191456 kb
Host smart-9a5734e3-f6f4-4584-b344-74b60b8e5904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512174627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3512174627
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1090652329
Short name T145
Test name
Test status
Simulation time 365509335 ps
CPU time 0.71 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:39:35 PM PDT 24
Peak memory 196276 kb
Host smart-826e3261-ab24-4017-a540-2cfd83994878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090652329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1090652329
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.654860584
Short name T167
Test name
Test status
Simulation time 372831213 ps
CPU time 0.91 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:38:54 PM PDT 24
Peak memory 196172 kb
Host smart-0b4f5e85-2394-4023-8ce8-085e053510bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654860584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.654860584
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3548769765
Short name T171
Test name
Test status
Simulation time 214137557882 ps
CPU time 133.04 seconds
Started Jul 19 04:38:43 PM PDT 24
Finished Jul 19 04:41:09 PM PDT 24
Peak memory 191464 kb
Host smart-f951a1e9-e184-4630-b3c3-ca7341c8d02a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548769765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3548769765
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.4284007777
Short name T1
Test name
Test status
Simulation time 559024541 ps
CPU time 0.62 seconds
Started Jul 19 04:39:00 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 196264 kb
Host smart-62a304d1-f3c2-4f82-a259-e60c5fd2ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284007777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.4284007777
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2821540975
Short name T138
Test name
Test status
Simulation time 464805432 ps
CPU time 0.94 seconds
Started Jul 19 04:38:46 PM PDT 24
Finished Jul 19 04:39:00 PM PDT 24
Peak memory 196372 kb
Host smart-c3a40475-acb9-41b4-9cec-287f85485270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821540975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2821540975
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3913095006
Short name T184
Test name
Test status
Simulation time 570582033 ps
CPU time 0.78 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:39:35 PM PDT 24
Peak memory 196196 kb
Host smart-45dbc7e1-9982-4cce-b8d5-28c9ec60451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913095006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3913095006
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.844028094
Short name T45
Test name
Test status
Simulation time 32731930089 ps
CPU time 167.66 seconds
Started Jul 19 04:38:57 PM PDT 24
Finished Jul 19 04:42:25 PM PDT 24
Peak memory 213600 kb
Host smart-42e6910f-4c48-4662-83fe-d2fbab3150e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844028094 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.844028094
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3714611656
Short name T158
Test name
Test status
Simulation time 431272720 ps
CPU time 1.2 seconds
Started Jul 19 04:39:11 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 196276 kb
Host smart-a45abe2a-1437-4924-a529-28b62ed13344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714611656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3714611656
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.341647649
Short name T189
Test name
Test status
Simulation time 610861122 ps
CPU time 1.52 seconds
Started Jul 19 04:39:11 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 196240 kb
Host smart-86930212-73c1-495f-be51-0f996230b91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341647649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.341647649
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2395148188
Short name T194
Test name
Test status
Simulation time 8563260073 ps
CPU time 3.08 seconds
Started Jul 19 04:53:47 PM PDT 24
Finished Jul 19 04:53:53 PM PDT 24
Peak memory 198568 kb
Host smart-d4e95e69-f7fb-49c2-bd83-5353e66b7061
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395148188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2395148188
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1083457208
Short name T186
Test name
Test status
Simulation time 479074770 ps
CPU time 0.79 seconds
Started Jul 19 04:38:54 PM PDT 24
Finished Jul 19 04:39:31 PM PDT 24
Peak memory 196348 kb
Host smart-364504a8-7ee7-4db3-847c-7db368fc7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083457208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1083457208
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3257371027
Short name T165
Test name
Test status
Simulation time 145998447670 ps
CPU time 12.71 seconds
Started Jul 19 04:38:36 PM PDT 24
Finished Jul 19 04:38:59 PM PDT 24
Peak memory 197888 kb
Host smart-1a5a190b-1097-4667-a0fc-cdaf4bb7de4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257371027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3257371027
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3006898494
Short name T178
Test name
Test status
Simulation time 348046862 ps
CPU time 1.03 seconds
Started Jul 19 04:38:30 PM PDT 24
Finished Jul 19 04:38:39 PM PDT 24
Peak memory 196336 kb
Host smart-7293664a-5c1c-4930-bb40-e33b0b4560cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006898494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3006898494
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.906767509
Short name T6
Test name
Test status
Simulation time 401784032 ps
CPU time 1.24 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 196364 kb
Host smart-c637cc9f-b0ec-49ed-8afd-016ddebbc9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906767509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.906767509
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.183097767
Short name T181
Test name
Test status
Simulation time 348538623 ps
CPU time 1.16 seconds
Started Jul 19 04:38:34 PM PDT 24
Finished Jul 19 04:38:46 PM PDT 24
Peak memory 196224 kb
Host smart-fd14e892-7f64-4323-8b95-f92a588b6cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183097767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.183097767
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1884426143
Short name T406
Test name
Test status
Simulation time 7756797448 ps
CPU time 7.48 seconds
Started Jul 19 04:54:19 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 198540 kb
Host smart-e6bba288-2ced-4ac0-97a9-651a3b120aaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884426143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1884426143
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2888024813
Short name T176
Test name
Test status
Simulation time 519568491 ps
CPU time 0.78 seconds
Started Jul 19 04:38:45 PM PDT 24
Finished Jul 19 04:38:59 PM PDT 24
Peak memory 196216 kb
Host smart-91ccc88e-626c-4b84-ab53-70c233a2d986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888024813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2888024813
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1500973995
Short name T179
Test name
Test status
Simulation time 583764767 ps
CPU time 0.84 seconds
Started Jul 19 04:38:43 PM PDT 24
Finished Jul 19 04:38:56 PM PDT 24
Peak memory 196204 kb
Host smart-faf2a839-a4c8-4a74-a4ba-0ab402f22c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500973995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1500973995
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.535313168
Short name T90
Test name
Test status
Simulation time 494621595 ps
CPU time 1.21 seconds
Started Jul 19 04:38:44 PM PDT 24
Finished Jul 19 04:38:58 PM PDT 24
Peak memory 196216 kb
Host smart-d875b139-493b-4679-a96d-e7e373ac02ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535313168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.535313168
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3948224863
Short name T164
Test name
Test status
Simulation time 523542005 ps
CPU time 0.8 seconds
Started Jul 19 04:38:39 PM PDT 24
Finished Jul 19 04:38:52 PM PDT 24
Peak memory 196196 kb
Host smart-e94661b0-3b32-4ad0-97be-b15991fb1aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948224863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3948224863
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1181596677
Short name T183
Test name
Test status
Simulation time 438253118 ps
CPU time 1.13 seconds
Started Jul 19 04:38:41 PM PDT 24
Finished Jul 19 04:38:54 PM PDT 24
Peak memory 196224 kb
Host smart-98bd2bd6-3f01-4b22-aa00-c1521d6faffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181596677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1181596677
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.99247990
Short name T95
Test name
Test status
Simulation time 390323050 ps
CPU time 1.21 seconds
Started Jul 19 04:38:59 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196544 kb
Host smart-d2ee0ce5-0c3f-4133-93c9-92590bb3fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99247990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.99247990
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.309306012
Short name T168
Test name
Test status
Simulation time 373132492 ps
CPU time 1.1 seconds
Started Jul 19 04:39:08 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196332 kb
Host smart-b676d3a4-73d9-4856-8a81-34f568ccae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309306012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.309306012
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.461248417
Short name T185
Test name
Test status
Simulation time 549113964 ps
CPU time 0.8 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196240 kb
Host smart-681d8613-8c7c-4155-8f5f-d5eecf4f1a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461248417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.461248417
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2871115472
Short name T190
Test name
Test status
Simulation time 436489878 ps
CPU time 1.25 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 196244 kb
Host smart-7034ad95-e4de-441a-8ffb-9ace8dd698fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871115472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2871115472
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4095908928
Short name T187
Test name
Test status
Simulation time 101534524191 ps
CPU time 71.49 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:40:57 PM PDT 24
Peak memory 192560 kb
Host smart-5429d366-3c35-4dfc-adc2-6ff43112658b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095908928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4095908928
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.466522437
Short name T162
Test name
Test status
Simulation time 562339965 ps
CPU time 1.38 seconds
Started Jul 19 04:39:16 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196228 kb
Host smart-d561f3a3-2c43-46f2-a4d5-f61e353d6274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466522437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.466522437
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.595531385
Short name T42
Test name
Test status
Simulation time 13840142932 ps
CPU time 9.65 seconds
Started Jul 19 04:53:45 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 192596 kb
Host smart-7ee38eed-dc03-4341-930e-46bfb8d9cdbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595531385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.595531385
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.962404326
Short name T346
Test name
Test status
Simulation time 1213960754 ps
CPU time 1.06 seconds
Started Jul 19 04:53:46 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 193840 kb
Host smart-712cc080-544b-4977-a57f-c760232e3693
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962404326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.962404326
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2180573914
Short name T367
Test name
Test status
Simulation time 632124840 ps
CPU time 1.21 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 198860 kb
Host smart-8d2ddc1e-f913-483f-9cb9-3353940e9b4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180573914 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2180573914
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1209308488
Short name T69
Test name
Test status
Simulation time 394243336 ps
CPU time 0.69 seconds
Started Jul 19 04:53:44 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 193404 kb
Host smart-66e942bc-d6da-4bc7-b957-bad6352300db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209308488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1209308488
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3372373324
Short name T324
Test name
Test status
Simulation time 283305266 ps
CPU time 0.87 seconds
Started Jul 19 04:53:52 PM PDT 24
Finished Jul 19 04:53:57 PM PDT 24
Peak memory 184212 kb
Host smart-cd2e3167-f05d-4da1-8053-94aa28b5b22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372373324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3372373324
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2310891654
Short name T311
Test name
Test status
Simulation time 441721788 ps
CPU time 0.79 seconds
Started Jul 19 04:53:45 PM PDT 24
Finished Jul 19 04:53:48 PM PDT 24
Peak memory 184076 kb
Host smart-64b2785d-c383-45ce-9492-a8b8e30be97b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310891654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2310891654
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1477377203
Short name T317
Test name
Test status
Simulation time 297529081 ps
CPU time 0.76 seconds
Started Jul 19 04:53:44 PM PDT 24
Finished Jul 19 04:53:48 PM PDT 24
Peak memory 184108 kb
Host smart-e1ba7f2d-3132-417a-a9fa-3adcca0195df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477377203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1477377203
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.97851507
Short name T361
Test name
Test status
Simulation time 2523470985 ps
CPU time 6.72 seconds
Started Jul 19 04:53:47 PM PDT 24
Finished Jul 19 04:53:57 PM PDT 24
Peak memory 195568 kb
Host smart-e0fd5276-f667-4443-9e8e-2c792eb2a781
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97851507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_same_csr_outstanding.97851507
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1703087365
Short name T336
Test name
Test status
Simulation time 712258391 ps
CPU time 2.52 seconds
Started Jul 19 04:53:49 PM PDT 24
Finished Jul 19 04:53:55 PM PDT 24
Peak memory 198980 kb
Host smart-8f5e4f5e-0570-493e-9748-2405fb69fe61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703087365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1703087365
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1929288768
Short name T66
Test name
Test status
Simulation time 676589445 ps
CPU time 1.01 seconds
Started Jul 19 04:53:47 PM PDT 24
Finished Jul 19 04:53:52 PM PDT 24
Peak memory 194624 kb
Host smart-c61ba23e-3af3-4c84-8e14-59b09c7b853a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929288768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1929288768
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1845987674
Short name T67
Test name
Test status
Simulation time 727430335 ps
CPU time 1.73 seconds
Started Jul 19 04:53:47 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 196640 kb
Host smart-f406ea35-6469-4037-ad80-a89c296585df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845987674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1845987674
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.617229637
Short name T316
Test name
Test status
Simulation time 867639555 ps
CPU time 0.88 seconds
Started Jul 19 04:53:45 PM PDT 24
Finished Jul 19 04:53:49 PM PDT 24
Peak memory 193376 kb
Host smart-97a2bbd3-6e07-4f18-90cd-b1a3830704c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617229637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.617229637
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3648669594
Short name T41
Test name
Test status
Simulation time 526260646 ps
CPU time 0.87 seconds
Started Jul 19 04:53:45 PM PDT 24
Finished Jul 19 04:53:48 PM PDT 24
Peak memory 196700 kb
Host smart-788ff864-41db-4d4f-8cf1-ccc581f65b2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648669594 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3648669594
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3271143902
Short name T409
Test name
Test status
Simulation time 439373935 ps
CPU time 0.76 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 184212 kb
Host smart-54aad3c0-016e-47d2-881a-5160bd20ce69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271143902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3271143902
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3728568836
Short name T308
Test name
Test status
Simulation time 505403053 ps
CPU time 1.39 seconds
Started Jul 19 04:53:44 PM PDT 24
Finished Jul 19 04:53:47 PM PDT 24
Peak memory 184060 kb
Host smart-3f1a73a5-4f2e-4dd8-9f14-e3fa7c30a482
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728568836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3728568836
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3741144614
Short name T363
Test name
Test status
Simulation time 355036410 ps
CPU time 0.63 seconds
Started Jul 19 04:53:48 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 184060 kb
Host smart-7dd02c7e-b495-4403-9d6c-3bcce62621ca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741144614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3741144614
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2996893732
Short name T388
Test name
Test status
Simulation time 1672292935 ps
CPU time 1.7 seconds
Started Jul 19 04:53:44 PM PDT 24
Finished Jul 19 04:53:48 PM PDT 24
Peak memory 194624 kb
Host smart-a64e7ca7-daaa-4a44-937d-8967b2dfab26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996893732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2996893732
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3015874792
Short name T362
Test name
Test status
Simulation time 409874468 ps
CPU time 1.7 seconds
Started Jul 19 04:53:52 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 199048 kb
Host smart-8c21dbca-d4e7-412c-88f2-5b7a726bf656
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015874792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3015874792
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2711572154
Short name T37
Test name
Test status
Simulation time 4540842502 ps
CPU time 7.61 seconds
Started Jul 19 04:53:47 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 198404 kb
Host smart-c80f419c-69b5-421a-ba4e-c2930c190b53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711572154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2711572154
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2752323063
Short name T343
Test name
Test status
Simulation time 487298120 ps
CPU time 1.01 seconds
Started Jul 19 04:54:11 PM PDT 24
Finished Jul 19 04:54:14 PM PDT 24
Peak memory 196008 kb
Host smart-16e3e78c-090d-494f-aa3f-2b866b7cc614
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752323063 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2752323063
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3114208713
Short name T374
Test name
Test status
Simulation time 545278888 ps
CPU time 0.69 seconds
Started Jul 19 04:54:09 PM PDT 24
Finished Jul 19 04:54:10 PM PDT 24
Peak memory 192448 kb
Host smart-858c2b73-65c0-4661-8bdd-0cb9b577dc7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114208713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3114208713
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.477905212
Short name T326
Test name
Test status
Simulation time 340826594 ps
CPU time 1.03 seconds
Started Jul 19 04:54:11 PM PDT 24
Finished Jul 19 04:54:14 PM PDT 24
Peak memory 193420 kb
Host smart-137489b9-0ea3-4f04-bf42-e3e0c57c972d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477905212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.477905212
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3296937278
Short name T70
Test name
Test status
Simulation time 987683607 ps
CPU time 0.98 seconds
Started Jul 19 04:54:11 PM PDT 24
Finished Jul 19 04:54:13 PM PDT 24
Peak memory 193832 kb
Host smart-220504e5-75f3-4123-9d05-655467c005e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296937278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3296937278
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3311522078
Short name T342
Test name
Test status
Simulation time 464355574 ps
CPU time 1.59 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:14 PM PDT 24
Peak memory 199012 kb
Host smart-c03d22ea-d94f-4a67-af65-e133811cdab2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311522078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3311522078
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3224807000
Short name T191
Test name
Test status
Simulation time 4001756313 ps
CPU time 2.48 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:15 PM PDT 24
Peak memory 198084 kb
Host smart-1c93a4b3-1488-4ef9-915a-adba075b3a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224807000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3224807000
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1417920916
Short name T391
Test name
Test status
Simulation time 498202233 ps
CPU time 1.02 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:12 PM PDT 24
Peak memory 196676 kb
Host smart-e621801a-c294-4e6e-8cc3-875256fb6285
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417920916 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1417920916
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1286599023
Short name T59
Test name
Test status
Simulation time 326276447 ps
CPU time 0.71 seconds
Started Jul 19 04:54:12 PM PDT 24
Finished Jul 19 04:54:15 PM PDT 24
Peak memory 193408 kb
Host smart-b7e499ef-a680-4e7c-8ded-f24544a683d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286599023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1286599023
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4125688621
Short name T365
Test name
Test status
Simulation time 315199977 ps
CPU time 0.78 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:12 PM PDT 24
Peak memory 184152 kb
Host smart-9fc8f198-1b21-47cb-9194-824e08679147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125688621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4125688621
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.4137000084
Short name T372
Test name
Test status
Simulation time 1671059713 ps
CPU time 5.74 seconds
Started Jul 19 04:54:11 PM PDT 24
Finished Jul 19 04:54:19 PM PDT 24
Peak memory 194448 kb
Host smart-5d88872b-6773-4305-8ec1-703afb69f13e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137000084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.4137000084
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.816017102
Short name T288
Test name
Test status
Simulation time 406427231 ps
CPU time 2.18 seconds
Started Jul 19 04:54:08 PM PDT 24
Finished Jul 19 04:54:10 PM PDT 24
Peak memory 198960 kb
Host smart-4ebdac04-2171-4815-852f-406a42f9544b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816017102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.816017102
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2010079293
Short name T410
Test name
Test status
Simulation time 8916060448 ps
CPU time 15.41 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:27 PM PDT 24
Peak memory 198580 kb
Host smart-7ce832c7-b9e7-46c2-b72e-205350f71de3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010079293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2010079293
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2036381032
Short name T330
Test name
Test status
Simulation time 440929788 ps
CPU time 1.21 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:12 PM PDT 24
Peak memory 196580 kb
Host smart-f47758b1-94da-430f-af6a-c268fe16f82e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036381032 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2036381032
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4123433795
Short name T61
Test name
Test status
Simulation time 307925321 ps
CPU time 0.83 seconds
Started Jul 19 04:54:11 PM PDT 24
Finished Jul 19 04:54:14 PM PDT 24
Peak memory 193408 kb
Host smart-b9295276-2d77-4201-a054-bd25805f92f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123433795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.4123433795
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1456119631
Short name T415
Test name
Test status
Simulation time 372895662 ps
CPU time 0.67 seconds
Started Jul 19 04:54:11 PM PDT 24
Finished Jul 19 04:54:13 PM PDT 24
Peak memory 184152 kb
Host smart-dfa392f7-0b58-43ef-8401-d0dda9761ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456119631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1456119631
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.286465615
Short name T338
Test name
Test status
Simulation time 2150193512 ps
CPU time 5.35 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:17 PM PDT 24
Peak memory 195320 kb
Host smart-6a534e0c-f41d-481f-9e1e-8b583349c8b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286465615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.286465615
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3669475218
Short name T299
Test name
Test status
Simulation time 299262035 ps
CPU time 2.02 seconds
Started Jul 19 04:54:13 PM PDT 24
Finished Jul 19 04:54:17 PM PDT 24
Peak memory 198904 kb
Host smart-027e0efb-d546-4cec-9044-fe72cad1e8ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669475218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3669475218
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2014788993
Short name T383
Test name
Test status
Simulation time 4545387295 ps
CPU time 2.35 seconds
Started Jul 19 04:54:12 PM PDT 24
Finished Jul 19 04:54:16 PM PDT 24
Peak memory 198236 kb
Host smart-809325ce-5572-46d1-b00f-b00026e32c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014788993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2014788993
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3716012101
Short name T334
Test name
Test status
Simulation time 412000771 ps
CPU time 1.04 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:13 PM PDT 24
Peak memory 196860 kb
Host smart-8a4de948-4096-4670-a467-401433183226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716012101 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3716012101
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1670305397
Short name T404
Test name
Test status
Simulation time 442220528 ps
CPU time 0.93 seconds
Started Jul 19 04:54:09 PM PDT 24
Finished Jul 19 04:54:11 PM PDT 24
Peak memory 193412 kb
Host smart-e34f9792-b0f5-4a0e-b7b0-ae0f6b4c6cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670305397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1670305397
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1777390279
Short name T368
Test name
Test status
Simulation time 667242139 ps
CPU time 0.61 seconds
Started Jul 19 04:54:11 PM PDT 24
Finished Jul 19 04:54:14 PM PDT 24
Peak memory 184196 kb
Host smart-78605333-7830-446d-a807-486025dde287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777390279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1777390279
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4258907270
Short name T375
Test name
Test status
Simulation time 834012597 ps
CPU time 1.19 seconds
Started Jul 19 04:54:12 PM PDT 24
Finished Jul 19 04:54:15 PM PDT 24
Peak memory 193380 kb
Host smart-95ba8f56-bfdf-4f6f-ad1e-09ac357dee8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258907270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.4258907270
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2041095771
Short name T298
Test name
Test status
Simulation time 354756101 ps
CPU time 1.7 seconds
Started Jul 19 04:54:12 PM PDT 24
Finished Jul 19 04:54:16 PM PDT 24
Peak memory 199000 kb
Host smart-8125f410-2dd2-4779-b187-968a075a833e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041095771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2041095771
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2086872625
Short name T345
Test name
Test status
Simulation time 8506943124 ps
CPU time 3.35 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:15 PM PDT 24
Peak memory 198520 kb
Host smart-38bbf736-d8ab-4c95-8130-38f3abfd069d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086872625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2086872625
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1787539383
Short name T295
Test name
Test status
Simulation time 527540386 ps
CPU time 1 seconds
Started Jul 19 04:54:18 PM PDT 24
Finished Jul 19 04:54:20 PM PDT 24
Peak memory 196424 kb
Host smart-ae205223-894d-44df-aebc-a2aae14bac56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787539383 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1787539383
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3623940849
Short name T74
Test name
Test status
Simulation time 501562126 ps
CPU time 1.34 seconds
Started Jul 19 04:54:19 PM PDT 24
Finished Jul 19 04:54:22 PM PDT 24
Peak memory 193652 kb
Host smart-09a77cd7-977b-49dc-a0a5-4d73241af1f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623940849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3623940849
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2233793286
Short name T291
Test name
Test status
Simulation time 454528253 ps
CPU time 0.64 seconds
Started Jul 19 04:54:18 PM PDT 24
Finished Jul 19 04:54:20 PM PDT 24
Peak memory 184160 kb
Host smart-6135a520-e459-40ed-afa4-845055cd727f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233793286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2233793286
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2258653962
Short name T34
Test name
Test status
Simulation time 2444669981 ps
CPU time 2.12 seconds
Started Jul 19 04:54:19 PM PDT 24
Finished Jul 19 04:54:23 PM PDT 24
Peak memory 194452 kb
Host smart-6760d151-bd45-4c3d-a5c0-d63e03700e1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258653962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2258653962
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.840463540
Short name T303
Test name
Test status
Simulation time 515506461 ps
CPU time 2.91 seconds
Started Jul 19 04:54:19 PM PDT 24
Finished Jul 19 04:54:23 PM PDT 24
Peak memory 198996 kb
Host smart-0013d1fc-1e8b-4cb1-9e18-40d9ff0d7047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840463540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.840463540
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1674992056
Short name T331
Test name
Test status
Simulation time 4611555300 ps
CPU time 7.58 seconds
Started Jul 19 04:54:19 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 198180 kb
Host smart-3690e9da-142d-47f2-9424-4ab4ed478586
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674992056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1674992056
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1503115205
Short name T397
Test name
Test status
Simulation time 470568066 ps
CPU time 1.3 seconds
Started Jul 19 04:54:20 PM PDT 24
Finished Jul 19 04:54:23 PM PDT 24
Peak memory 196580 kb
Host smart-b772cf89-ebb7-440a-8d92-1281dec7532c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503115205 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1503115205
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3172420332
Short name T60
Test name
Test status
Simulation time 568934256 ps
CPU time 0.68 seconds
Started Jul 19 04:54:18 PM PDT 24
Finished Jul 19 04:54:20 PM PDT 24
Peak memory 193684 kb
Host smart-da7a3ca0-473a-4c6b-95fc-5e8314cfc246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172420332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3172420332
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.247754750
Short name T307
Test name
Test status
Simulation time 472724206 ps
CPU time 1.33 seconds
Started Jul 19 04:54:25 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 193384 kb
Host smart-30a0d6d0-8c09-4cd0-81e5-ae9c3358a899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247754750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.247754750
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.96851381
Short name T401
Test name
Test status
Simulation time 1288716006 ps
CPU time 1.37 seconds
Started Jul 19 04:54:18 PM PDT 24
Finished Jul 19 04:54:21 PM PDT 24
Peak memory 193888 kb
Host smart-af7f997f-b8f5-4c0e-b0c0-1c760ea8236d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96851381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_
timer_same_csr_outstanding.96851381
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2363144936
Short name T371
Test name
Test status
Simulation time 474886129 ps
CPU time 2.07 seconds
Started Jul 19 04:54:25 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 198996 kb
Host smart-89aafbdd-65aa-487d-bac3-7db1b752ac68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363144936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2363144936
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.117304694
Short name T195
Test name
Test status
Simulation time 8693041466 ps
CPU time 5.19 seconds
Started Jul 19 04:54:18 PM PDT 24
Finished Jul 19 04:54:25 PM PDT 24
Peak memory 198528 kb
Host smart-6ae0034f-b6e2-47af-9656-a24e3becbf24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117304694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.117304694
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4258683061
Short name T305
Test name
Test status
Simulation time 404992073 ps
CPU time 1.16 seconds
Started Jul 19 04:54:19 PM PDT 24
Finished Jul 19 04:54:22 PM PDT 24
Peak memory 196472 kb
Host smart-9253a5c5-1866-41a6-9949-d3951fb164c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258683061 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4258683061
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2255865023
Short name T373
Test name
Test status
Simulation time 380236397 ps
CPU time 0.8 seconds
Started Jul 19 04:54:20 PM PDT 24
Finished Jul 19 04:54:23 PM PDT 24
Peak memory 193396 kb
Host smart-004a14df-1da9-42d3-a4c8-f0d6f6ef5e00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255865023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2255865023
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1940178734
Short name T320
Test name
Test status
Simulation time 264557727 ps
CPU time 0.88 seconds
Started Jul 19 04:54:20 PM PDT 24
Finished Jul 19 04:54:22 PM PDT 24
Peak memory 184188 kb
Host smart-f4337e5b-d05c-4104-8906-3a24359ed49a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940178734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1940178734
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2603845710
Short name T75
Test name
Test status
Simulation time 2231015381 ps
CPU time 3.67 seconds
Started Jul 19 04:54:18 PM PDT 24
Finished Jul 19 04:54:23 PM PDT 24
Peak memory 195528 kb
Host smart-02069e19-59ea-4d72-bec1-83680e0bca48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603845710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2603845710
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2384828913
Short name T366
Test name
Test status
Simulation time 494113139 ps
CPU time 1.53 seconds
Started Jul 19 04:54:21 PM PDT 24
Finished Jul 19 04:54:25 PM PDT 24
Peak memory 198972 kb
Host smart-45c56dca-756c-47d8-8797-5feb848704ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384828913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2384828913
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1159940667
Short name T200
Test name
Test status
Simulation time 752446301 ps
CPU time 0.78 seconds
Started Jul 19 04:54:21 PM PDT 24
Finished Jul 19 04:54:24 PM PDT 24
Peak memory 197072 kb
Host smart-181d939c-46f8-4508-97d4-9331863aa0fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159940667 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1159940667
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2743462994
Short name T394
Test name
Test status
Simulation time 537755342 ps
CPU time 0.79 seconds
Started Jul 19 04:54:21 PM PDT 24
Finished Jul 19 04:54:23 PM PDT 24
Peak memory 193416 kb
Host smart-cb80778a-a71a-49b2-b2ab-c88f8d1734ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743462994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2743462994
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4068949794
Short name T364
Test name
Test status
Simulation time 265836507 ps
CPU time 1.07 seconds
Started Jul 19 04:54:20 PM PDT 24
Finished Jul 19 04:54:22 PM PDT 24
Peak memory 184164 kb
Host smart-ec504d2c-6044-499b-8e26-ed5fed6fb9c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068949794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.4068949794
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.379582625
Short name T35
Test name
Test status
Simulation time 3301514572 ps
CPU time 1.36 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:30 PM PDT 24
Peak memory 192416 kb
Host smart-d1eb6286-8336-4218-a85e-52839aead937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379582625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.379582625
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2226700357
Short name T348
Test name
Test status
Simulation time 602627264 ps
CPU time 2.33 seconds
Started Jul 19 04:54:20 PM PDT 24
Finished Jul 19 04:54:24 PM PDT 24
Peak memory 199032 kb
Host smart-e0f72724-ac63-4a7c-896a-f9d3043210f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226700357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2226700357
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4163610868
Short name T354
Test name
Test status
Simulation time 4020944863 ps
CPU time 6.34 seconds
Started Jul 19 04:54:19 PM PDT 24
Finished Jul 19 04:54:26 PM PDT 24
Peak memory 198400 kb
Host smart-8ab99885-90c2-4127-8c66-97b36deb6a38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163610868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.4163610868
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2098627727
Short name T199
Test name
Test status
Simulation time 401122155 ps
CPU time 1.2 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:30 PM PDT 24
Peak memory 195816 kb
Host smart-3fd1c0d7-fcf2-4fad-ba35-9979a5850970
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098627727 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2098627727
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1760953781
Short name T63
Test name
Test status
Simulation time 579703655 ps
CPU time 0.84 seconds
Started Jul 19 04:54:20 PM PDT 24
Finished Jul 19 04:54:22 PM PDT 24
Peak memory 193732 kb
Host smart-a1c7078b-67f0-4759-8bc7-23fbdae81925
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760953781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1760953781
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2900885085
Short name T398
Test name
Test status
Simulation time 376002720 ps
CPU time 0.83 seconds
Started Jul 19 04:54:20 PM PDT 24
Finished Jul 19 04:54:23 PM PDT 24
Peak memory 193320 kb
Host smart-24684b6d-bd34-4b9a-89ad-de8faa15180e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900885085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2900885085
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.163667778
Short name T385
Test name
Test status
Simulation time 2777287965 ps
CPU time 7.48 seconds
Started Jul 19 04:54:19 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 195508 kb
Host smart-a44b66e6-bb24-4af1-a4c0-74e7d7f96dba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163667778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.163667778
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1098426750
Short name T285
Test name
Test status
Simulation time 501290574 ps
CPU time 2.55 seconds
Started Jul 19 04:54:19 PM PDT 24
Finished Jul 19 04:54:23 PM PDT 24
Peak memory 198996 kb
Host smart-23cd3ded-70bb-4153-9518-159dd99c2c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098426750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1098426750
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1772167818
Short name T379
Test name
Test status
Simulation time 4128164622 ps
CPU time 1.79 seconds
Started Jul 19 04:54:21 PM PDT 24
Finished Jul 19 04:54:24 PM PDT 24
Peak memory 198180 kb
Host smart-00c42448-e504-4856-9f58-2482d3b28ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772167818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1772167818
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.4291216342
Short name T310
Test name
Test status
Simulation time 464490354 ps
CPU time 1.33 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:29 PM PDT 24
Peak memory 196660 kb
Host smart-92e102e7-b169-4e71-9cee-326a331fc612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291216342 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.4291216342
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3048977799
Short name T402
Test name
Test status
Simulation time 382141168 ps
CPU time 0.7 seconds
Started Jul 19 04:54:27 PM PDT 24
Finished Jul 19 04:54:30 PM PDT 24
Peak memory 193408 kb
Host smart-076b4072-e85e-46c3-8629-d924a071aaff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048977799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3048977799
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.309439577
Short name T329
Test name
Test status
Simulation time 301738792 ps
CPU time 0.95 seconds
Started Jul 19 04:54:27 PM PDT 24
Finished Jul 19 04:54:32 PM PDT 24
Peak memory 193340 kb
Host smart-9b60a380-7cfb-4e2b-b976-ca1facdba6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309439577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.309439577
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4097623667
Short name T376
Test name
Test status
Simulation time 1051046055 ps
CPU time 2.02 seconds
Started Jul 19 04:54:25 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 184204 kb
Host smart-70ef5289-7e67-4c3e-a050-b71292cdaf88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097623667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.4097623667
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2468889581
Short name T339
Test name
Test status
Simulation time 505307229 ps
CPU time 2.3 seconds
Started Jul 19 04:54:27 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 199000 kb
Host smart-0bed5496-9344-417d-b9ca-bf4027af906f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468889581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2468889581
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1384764955
Short name T197
Test name
Test status
Simulation time 7807647412 ps
CPU time 10.62 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:42 PM PDT 24
Peak memory 198740 kb
Host smart-b1c0d579-536d-43db-8d46-aebcc5a04e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384764955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1384764955
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1843531039
Short name T65
Test name
Test status
Simulation time 376508343 ps
CPU time 0.98 seconds
Started Jul 19 04:53:55 PM PDT 24
Finished Jul 19 04:54:01 PM PDT 24
Peak memory 193516 kb
Host smart-73fc4237-6faa-4d65-8b0d-820727fa8385
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843531039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1843531039
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3739684071
Short name T40
Test name
Test status
Simulation time 7293791465 ps
CPU time 11.38 seconds
Started Jul 19 04:53:51 PM PDT 24
Finished Jul 19 04:54:06 PM PDT 24
Peak memory 196568 kb
Host smart-4f7f7d2b-c6f9-41e9-be70-74f3317978e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739684071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3739684071
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.928408904
Short name T328
Test name
Test status
Simulation time 1133099364 ps
CPU time 0.92 seconds
Started Jul 19 04:53:45 PM PDT 24
Finished Jul 19 04:53:49 PM PDT 24
Peak memory 193388 kb
Host smart-651f9316-57d9-497a-8268-bae171511966
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928408904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.928408904
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3191357514
Short name T306
Test name
Test status
Simulation time 601286725 ps
CPU time 0.96 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 198792 kb
Host smart-9471017d-0b15-4042-8a53-fddf1dd68c2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191357514 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3191357514
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2752521924
Short name T56
Test name
Test status
Simulation time 543120534 ps
CPU time 0.76 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 193572 kb
Host smart-1913679d-851f-4a84-889b-b0b7d9d21f13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752521924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2752521924
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3634536422
Short name T384
Test name
Test status
Simulation time 348142505 ps
CPU time 0.69 seconds
Started Jul 19 04:53:47 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 184192 kb
Host smart-524b3916-799b-4e45-85f1-9d412991b226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634536422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3634536422
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3414738504
Short name T314
Test name
Test status
Simulation time 471892493 ps
CPU time 0.58 seconds
Started Jul 19 04:53:44 PM PDT 24
Finished Jul 19 04:53:46 PM PDT 24
Peak memory 184080 kb
Host smart-f3619d41-1d5e-4ed5-b383-a9c9f96cb529
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414738504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3414738504
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1798530131
Short name T389
Test name
Test status
Simulation time 488798409 ps
CPU time 0.69 seconds
Started Jul 19 04:53:47 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 184024 kb
Host smart-0b463402-dcd9-41f8-ba24-1f4ff2d6d8f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798530131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1798530131
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4183485560
Short name T390
Test name
Test status
Simulation time 2169998664 ps
CPU time 4.25 seconds
Started Jul 19 04:53:52 PM PDT 24
Finished Jul 19 04:54:01 PM PDT 24
Peak memory 195404 kb
Host smart-decc98de-3531-4905-80a4-ba0b9d5fb351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183485560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4183485560
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2278154266
Short name T282
Test name
Test status
Simulation time 377248687 ps
CPU time 2.52 seconds
Started Jul 19 04:53:45 PM PDT 24
Finished Jul 19 04:53:51 PM PDT 24
Peak memory 199032 kb
Host smart-3cdeab8e-d199-4d68-8731-8edcec70c4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278154266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2278154266
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2210162980
Short name T39
Test name
Test status
Simulation time 8515661225 ps
CPU time 6.62 seconds
Started Jul 19 04:53:46 PM PDT 24
Finished Jul 19 04:53:56 PM PDT 24
Peak memory 198592 kb
Host smart-8df400b9-bfe7-48de-9c9c-48fc0db73859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210162980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2210162980
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.511974261
Short name T399
Test name
Test status
Simulation time 426724958 ps
CPU time 0.7 seconds
Started Jul 19 04:54:30 PM PDT 24
Finished Jul 19 04:54:34 PM PDT 24
Peak memory 184184 kb
Host smart-a721b2e1-ab44-4b33-b318-5fd45b3bbd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511974261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.511974261
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3758774993
Short name T358
Test name
Test status
Simulation time 365585383 ps
CPU time 1.01 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:29 PM PDT 24
Peak memory 193408 kb
Host smart-d1abd6c5-0a13-4d82-81c1-6962cd12624f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758774993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3758774993
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1307936898
Short name T290
Test name
Test status
Simulation time 366142240 ps
CPU time 0.84 seconds
Started Jul 19 04:54:29 PM PDT 24
Finished Jul 19 04:54:34 PM PDT 24
Peak memory 184156 kb
Host smart-f42c7943-3847-42ae-ad96-3b4bbc8ca39c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307936898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1307936898
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.703905314
Short name T300
Test name
Test status
Simulation time 450677357 ps
CPU time 0.85 seconds
Started Jul 19 04:54:47 PM PDT 24
Finished Jul 19 04:54:51 PM PDT 24
Peak memory 184156 kb
Host smart-7ac83843-c32b-4c72-90c6-3b28a93ff8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703905314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.703905314
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.177363634
Short name T353
Test name
Test status
Simulation time 397612388 ps
CPU time 1.05 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:30 PM PDT 24
Peak memory 184152 kb
Host smart-014001be-71cd-4baa-b4df-146d55abebc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177363634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.177363634
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3790074184
Short name T318
Test name
Test status
Simulation time 470006761 ps
CPU time 1.35 seconds
Started Jul 19 04:54:30 PM PDT 24
Finished Jul 19 04:54:35 PM PDT 24
Peak memory 193404 kb
Host smart-6bc122f1-2778-46ae-b8b7-5c10ab9eb622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790074184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3790074184
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1645809810
Short name T382
Test name
Test status
Simulation time 469335149 ps
CPU time 0.91 seconds
Started Jul 19 04:54:29 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 184120 kb
Host smart-f7b8028b-1030-49e8-b237-4c6268387c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645809810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1645809810
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3218837691
Short name T417
Test name
Test status
Simulation time 544865493 ps
CPU time 0.75 seconds
Started Jul 19 04:54:25 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 193352 kb
Host smart-364a9d2a-47cf-4c88-ad86-b73e045d7aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218837691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3218837691
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2814893819
Short name T289
Test name
Test status
Simulation time 444720546 ps
CPU time 0.71 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 184196 kb
Host smart-c9aa8927-fe7c-4331-a5e0-ab34e411dd14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814893819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2814893819
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4008784637
Short name T360
Test name
Test status
Simulation time 437022282 ps
CPU time 1.16 seconds
Started Jul 19 04:54:27 PM PDT 24
Finished Jul 19 04:54:31 PM PDT 24
Peak memory 184152 kb
Host smart-d5bcc457-57f8-43a7-96d6-cf5973b0c0eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008784637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4008784637
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2667071364
Short name T359
Test name
Test status
Simulation time 403901392 ps
CPU time 0.79 seconds
Started Jul 19 04:53:51 PM PDT 24
Finished Jul 19 04:53:56 PM PDT 24
Peak memory 184356 kb
Host smart-3b7cb4be-7026-4c3c-81ef-4c65fe64750f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667071364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2667071364
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3153646019
Short name T58
Test name
Test status
Simulation time 4008736004 ps
CPU time 4.95 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:54:02 PM PDT 24
Peak memory 192600 kb
Host smart-cd54e4c4-6277-4ba7-a78b-0d384508b81c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153646019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3153646019
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2042908966
Short name T57
Test name
Test status
Simulation time 1163296986 ps
CPU time 0.75 seconds
Started Jul 19 04:53:54 PM PDT 24
Finished Jul 19 04:54:00 PM PDT 24
Peak memory 193544 kb
Host smart-b2f15f7e-30cb-4f4e-9edf-9331299cd262
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042908966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2042908966
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.675349161
Short name T355
Test name
Test status
Simulation time 624833718 ps
CPU time 0.73 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 196640 kb
Host smart-1286251d-4053-4d8a-aaec-2b6c2ac009e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675349161 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.675349161
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.228206823
Short name T315
Test name
Test status
Simulation time 400597728 ps
CPU time 1.3 seconds
Started Jul 19 04:53:52 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 193352 kb
Host smart-19ee394e-aa3f-48f3-aa48-dbfb633af89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228206823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.228206823
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1635146353
Short name T403
Test name
Test status
Simulation time 433416572 ps
CPU time 0.6 seconds
Started Jul 19 04:53:52 PM PDT 24
Finished Jul 19 04:53:56 PM PDT 24
Peak memory 184192 kb
Host smart-6459c3ed-84b0-4695-8ecb-aa367c542017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635146353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1635146353
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3659835319
Short name T284
Test name
Test status
Simulation time 322481988 ps
CPU time 0.99 seconds
Started Jul 19 04:53:54 PM PDT 24
Finished Jul 19 04:54:00 PM PDT 24
Peak memory 184112 kb
Host smart-584a586a-8b53-455e-b480-ce641fb4dab0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659835319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3659835319
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1113253643
Short name T395
Test name
Test status
Simulation time 309380304 ps
CPU time 0.64 seconds
Started Jul 19 04:53:54 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 184088 kb
Host smart-78b325f4-31bc-419c-abdb-ad46d385fdea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113253643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1113253643
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3076667809
Short name T411
Test name
Test status
Simulation time 864567824 ps
CPU time 1.05 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 193668 kb
Host smart-9a1be4a1-b835-471f-98a0-12f9f2cb012d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076667809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3076667809
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2658024266
Short name T381
Test name
Test status
Simulation time 683552339 ps
CPU time 2.03 seconds
Started Jul 19 04:53:56 PM PDT 24
Finished Jul 19 04:54:02 PM PDT 24
Peak memory 198948 kb
Host smart-9faf7bc6-f2aa-481f-bddb-d5ff882bb93d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658024266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2658024266
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.4015143793
Short name T387
Test name
Test status
Simulation time 8199962434 ps
CPU time 3.93 seconds
Started Jul 19 04:53:56 PM PDT 24
Finished Jul 19 04:54:04 PM PDT 24
Peak memory 198748 kb
Host smart-20657c45-04b5-46a4-81d2-328de8b4401d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015143793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.4015143793
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3109314051
Short name T418
Test name
Test status
Simulation time 320899075 ps
CPU time 1 seconds
Started Jul 19 04:54:25 PM PDT 24
Finished Jul 19 04:54:27 PM PDT 24
Peak memory 184140 kb
Host smart-6e19aac1-e9ce-40fb-9c14-30d7df2cce8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109314051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3109314051
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2617696172
Short name T357
Test name
Test status
Simulation time 462032273 ps
CPU time 0.58 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:29 PM PDT 24
Peak memory 184196 kb
Host smart-88673a67-3072-46a2-ad5c-4fa7d5bd9923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617696172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2617696172
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.884679465
Short name T400
Test name
Test status
Simulation time 314232595 ps
CPU time 0.85 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 184164 kb
Host smart-c1e55d68-23d1-4d42-a406-c675394be4db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884679465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.884679465
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3907907902
Short name T287
Test name
Test status
Simulation time 438814711 ps
CPU time 1.18 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 193432 kb
Host smart-3566a325-5bf5-4464-9948-0392c64c2f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907907902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3907907902
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1870454815
Short name T283
Test name
Test status
Simulation time 454774226 ps
CPU time 1.13 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:32 PM PDT 24
Peak memory 184192 kb
Host smart-c518485e-1e12-40df-b46d-b52d8a45a938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870454815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1870454815
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1667052236
Short name T340
Test name
Test status
Simulation time 306459842 ps
CPU time 0.69 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 184196 kb
Host smart-c83f360d-afe8-47c6-ad52-fee25808fed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667052236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1667052236
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1765734565
Short name T349
Test name
Test status
Simulation time 438186852 ps
CPU time 1.2 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 184160 kb
Host smart-1f58b9e2-592f-4b5e-9162-da359fd77484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765734565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1765734565
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1265024717
Short name T304
Test name
Test status
Simulation time 369806775 ps
CPU time 0.69 seconds
Started Jul 19 04:54:29 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 184120 kb
Host smart-f54dd93c-2e70-4d24-8059-3b5044c31183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265024717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1265024717
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.20793218
Short name T416
Test name
Test status
Simulation time 386484162 ps
CPU time 1.13 seconds
Started Jul 19 04:54:30 PM PDT 24
Finished Jul 19 04:54:35 PM PDT 24
Peak memory 184104 kb
Host smart-610cb616-1563-4cfd-92cd-ce2aeae90816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20793218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.20793218
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1127710060
Short name T323
Test name
Test status
Simulation time 302980148 ps
CPU time 0.63 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:29 PM PDT 24
Peak memory 193320 kb
Host smart-60cfa10a-8baa-44c6-98db-c5a28c9202e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127710060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1127710060
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2714507348
Short name T62
Test name
Test status
Simulation time 475470930 ps
CPU time 1.42 seconds
Started Jul 19 04:53:56 PM PDT 24
Finished Jul 19 04:54:01 PM PDT 24
Peak memory 194444 kb
Host smart-ae9a920b-99b0-49a3-82cf-e4cb6c46be64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714507348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2714507348
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2884973043
Short name T68
Test name
Test status
Simulation time 775059008 ps
CPU time 2.46 seconds
Started Jul 19 04:53:52 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 184356 kb
Host smart-6e80cc35-5d99-4f2a-97a0-8e869f0c7747
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884973043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2884973043
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1616332325
Short name T380
Test name
Test status
Simulation time 934945720 ps
CPU time 0.92 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 193708 kb
Host smart-171d19c4-7b7b-41c1-94b9-be7f27b04ca3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616332325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1616332325
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.443608233
Short name T319
Test name
Test status
Simulation time 575890265 ps
CPU time 1.5 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:53:59 PM PDT 24
Peak memory 196576 kb
Host smart-40280146-c91d-4341-8701-f3380055358c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443608233 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.443608233
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4089357275
Short name T392
Test name
Test status
Simulation time 536566281 ps
CPU time 0.77 seconds
Started Jul 19 04:53:54 PM PDT 24
Finished Jul 19 04:54:00 PM PDT 24
Peak memory 193376 kb
Host smart-44eeacc7-f7d5-432d-b721-cebc3c9ccc1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089357275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4089357275
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4175311854
Short name T327
Test name
Test status
Simulation time 407781494 ps
CPU time 0.65 seconds
Started Jul 19 04:53:52 PM PDT 24
Finished Jul 19 04:53:57 PM PDT 24
Peak memory 184164 kb
Host smart-ed6fa1cc-ce49-42f0-8c6b-c6368847bcc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175311854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4175311854
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1877239347
Short name T309
Test name
Test status
Simulation time 370389519 ps
CPU time 0.99 seconds
Started Jul 19 04:53:52 PM PDT 24
Finished Jul 19 04:53:57 PM PDT 24
Peak memory 184112 kb
Host smart-568d2f82-5e2f-4296-8e8e-4f53b8606bb0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877239347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1877239347
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3821779365
Short name T325
Test name
Test status
Simulation time 329213732 ps
CPU time 1.04 seconds
Started Jul 19 04:53:57 PM PDT 24
Finished Jul 19 04:54:02 PM PDT 24
Peak memory 184020 kb
Host smart-cff9ad73-acbc-4a7e-9621-d72cf61d3702
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821779365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3821779365
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2965654902
Short name T407
Test name
Test status
Simulation time 2436506075 ps
CPU time 4.14 seconds
Started Jul 19 04:53:56 PM PDT 24
Finished Jul 19 04:54:04 PM PDT 24
Peak memory 195412 kb
Host smart-c8f7d2ae-be9d-42b2-9ee0-28d0a3e736fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965654902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2965654902
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.696249485
Short name T351
Test name
Test status
Simulation time 493070855 ps
CPU time 2.17 seconds
Started Jul 19 04:53:57 PM PDT 24
Finished Jul 19 04:54:03 PM PDT 24
Peak memory 198888 kb
Host smart-20c41748-b360-4910-829a-6eaf05ff2594
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696249485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.696249485
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.274568721
Short name T192
Test name
Test status
Simulation time 4666291387 ps
CPU time 6.77 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:54:03 PM PDT 24
Peak memory 198256 kb
Host smart-8dc84099-850d-4766-8cf8-c8bc31bfd88b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274568721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.274568721
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2503769784
Short name T332
Test name
Test status
Simulation time 357437572 ps
CPU time 0.67 seconds
Started Jul 19 04:54:29 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 193356 kb
Host smart-04121ca3-f944-42fa-b33d-b5b0e743fc96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503769784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2503769784
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3402010154
Short name T293
Test name
Test status
Simulation time 437136439 ps
CPU time 1.22 seconds
Started Jul 19 04:54:31 PM PDT 24
Finished Jul 19 04:54:35 PM PDT 24
Peak memory 193376 kb
Host smart-bae4f2c1-3758-4e51-9bc0-478189055123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402010154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3402010154
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.777378881
Short name T292
Test name
Test status
Simulation time 514371965 ps
CPU time 0.7 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:32 PM PDT 24
Peak memory 184192 kb
Host smart-8c5815bd-3f7d-439a-8992-f2e79894fc95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777378881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.777378881
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2009574365
Short name T301
Test name
Test status
Simulation time 269036808 ps
CPU time 0.94 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 184196 kb
Host smart-5a1e00b0-af60-4d4d-9d03-ee2a2fcd5672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009574365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2009574365
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.372760175
Short name T321
Test name
Test status
Simulation time 378447001 ps
CPU time 1.08 seconds
Started Jul 19 04:54:26 PM PDT 24
Finished Jul 19 04:54:28 PM PDT 24
Peak memory 193400 kb
Host smart-5e8b154e-3089-4b36-ab61-ed1e1bc2ebed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372760175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.372760175
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.670249491
Short name T294
Test name
Test status
Simulation time 349938822 ps
CPU time 0.66 seconds
Started Jul 19 04:54:30 PM PDT 24
Finished Jul 19 04:54:35 PM PDT 24
Peak memory 184084 kb
Host smart-b97c7233-11e4-4a0f-85ac-57205c432e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670249491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.670249491
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.499883382
Short name T386
Test name
Test status
Simulation time 403741695 ps
CPU time 1.07 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:33 PM PDT 24
Peak memory 184160 kb
Host smart-67e82836-dfaa-4169-8091-877652583f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499883382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.499883382
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.752403282
Short name T337
Test name
Test status
Simulation time 381935244 ps
CPU time 0.69 seconds
Started Jul 19 04:54:27 PM PDT 24
Finished Jul 19 04:54:31 PM PDT 24
Peak memory 184120 kb
Host smart-90f84375-e8f7-4574-a91d-9de788fa8931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752403282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.752403282
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2811164570
Short name T408
Test name
Test status
Simulation time 324762260 ps
CPU time 0.64 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:32 PM PDT 24
Peak memory 184192 kb
Host smart-c0277067-d86f-43ae-bf26-73d4c2bfd3d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811164570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2811164570
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1661377099
Short name T341
Test name
Test status
Simulation time 497827527 ps
CPU time 0.63 seconds
Started Jul 19 04:54:28 PM PDT 24
Finished Jul 19 04:54:32 PM PDT 24
Peak memory 193324 kb
Host smart-4429692a-0721-498a-a9e8-5439d834ecd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661377099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1661377099
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3503194930
Short name T297
Test name
Test status
Simulation time 458504645 ps
CPU time 0.84 seconds
Started Jul 19 04:54:03 PM PDT 24
Finished Jul 19 04:54:05 PM PDT 24
Peak memory 195732 kb
Host smart-65f8c257-5dee-48e9-aaa2-fe694a7993fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503194930 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3503194930
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3958590272
Short name T356
Test name
Test status
Simulation time 323139844 ps
CPU time 0.85 seconds
Started Jul 19 04:54:01 PM PDT 24
Finished Jul 19 04:54:05 PM PDT 24
Peak memory 193840 kb
Host smart-9c1c442b-f534-47fa-922c-89679e8833cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958590272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3958590272
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.854864578
Short name T369
Test name
Test status
Simulation time 343950255 ps
CPU time 0.97 seconds
Started Jul 19 04:53:53 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 193416 kb
Host smart-053c9bc0-ebbe-44bf-ab4c-8bcb34e68d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854864578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.854864578
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2727396535
Short name T378
Test name
Test status
Simulation time 1117021716 ps
CPU time 2.36 seconds
Started Jul 19 04:54:06 PM PDT 24
Finished Jul 19 04:54:10 PM PDT 24
Peak memory 194352 kb
Host smart-fb592fa7-3473-4edd-b202-0aee499aa72f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727396535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2727396535
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1401693139
Short name T412
Test name
Test status
Simulation time 358125496 ps
CPU time 2.53 seconds
Started Jul 19 04:53:52 PM PDT 24
Finished Jul 19 04:53:58 PM PDT 24
Peak memory 199040 kb
Host smart-9d966ecb-a389-4d5c-843f-072c416643bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401693139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1401693139
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3841860171
Short name T196
Test name
Test status
Simulation time 8471905243 ps
CPU time 12.03 seconds
Started Jul 19 04:53:57 PM PDT 24
Finished Jul 19 04:54:12 PM PDT 24
Peak memory 198536 kb
Host smart-a16a98c5-fe60-4b17-a952-03864ea81448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841860171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3841860171
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1825116897
Short name T347
Test name
Test status
Simulation time 466790344 ps
CPU time 0.79 seconds
Started Jul 19 04:54:00 PM PDT 24
Finished Jul 19 04:54:03 PM PDT 24
Peak memory 196560 kb
Host smart-a7a4e262-cf0d-4499-ad8b-58eb9865ba6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825116897 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1825116897
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3923312160
Short name T36
Test name
Test status
Simulation time 494774183 ps
CPU time 0.91 seconds
Started Jul 19 04:54:00 PM PDT 24
Finished Jul 19 04:54:03 PM PDT 24
Peak memory 192488 kb
Host smart-da63cdfd-efe8-4d87-8f40-1bd3a829540a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923312160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3923312160
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1073583196
Short name T350
Test name
Test status
Simulation time 272182798 ps
CPU time 0.73 seconds
Started Jul 19 04:54:11 PM PDT 24
Finished Jul 19 04:54:14 PM PDT 24
Peak memory 184068 kb
Host smart-4ea3a755-4683-45a3-8ad0-3e3d325d13d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073583196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1073583196
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1101266893
Short name T333
Test name
Test status
Simulation time 1286842584 ps
CPU time 1.08 seconds
Started Jul 19 04:54:00 PM PDT 24
Finished Jul 19 04:54:04 PM PDT 24
Peak memory 193628 kb
Host smart-efe5e159-3241-4a13-9899-8570ae3ed456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101266893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1101266893
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2467022825
Short name T413
Test name
Test status
Simulation time 395885969 ps
CPU time 1.37 seconds
Started Jul 19 04:54:00 PM PDT 24
Finished Jul 19 04:54:04 PM PDT 24
Peak memory 199052 kb
Host smart-40877595-1066-47a3-beb9-53876a9cbc7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467022825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2467022825
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3393102778
Short name T393
Test name
Test status
Simulation time 4472170296 ps
CPU time 6.83 seconds
Started Jul 19 04:54:01 PM PDT 24
Finished Jul 19 04:54:10 PM PDT 24
Peak memory 197036 kb
Host smart-8927fb16-8e56-4a46-8d19-9cbcf0ee9dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393102778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3393102778
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3792645794
Short name T396
Test name
Test status
Simulation time 653694126 ps
CPU time 1.01 seconds
Started Jul 19 04:54:00 PM PDT 24
Finished Jul 19 04:54:03 PM PDT 24
Peak memory 198784 kb
Host smart-75845fb1-4803-48ca-b9b5-b11f515a544e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792645794 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3792645794
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3406460989
Short name T405
Test name
Test status
Simulation time 501419231 ps
CPU time 0.98 seconds
Started Jul 19 04:54:00 PM PDT 24
Finished Jul 19 04:54:04 PM PDT 24
Peak memory 193348 kb
Host smart-78f70302-5637-4e99-81c8-28238709dfdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406460989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3406460989
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3352450067
Short name T322
Test name
Test status
Simulation time 482198611 ps
CPU time 0.76 seconds
Started Jul 19 04:54:02 PM PDT 24
Finished Jul 19 04:54:05 PM PDT 24
Peak memory 184168 kb
Host smart-4c1f3c89-e272-40d8-aab2-feb050833c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352450067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3352450067
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4222475750
Short name T72
Test name
Test status
Simulation time 1924210011 ps
CPU time 1.39 seconds
Started Jul 19 04:54:00 PM PDT 24
Finished Jul 19 04:54:04 PM PDT 24
Peak memory 194416 kb
Host smart-c2a9ed61-723a-4ac2-8897-26668f25baa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222475750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.4222475750
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3580252642
Short name T296
Test name
Test status
Simulation time 510636398 ps
CPU time 2.62 seconds
Started Jul 19 04:54:00 PM PDT 24
Finished Jul 19 04:54:05 PM PDT 24
Peak memory 199056 kb
Host smart-53c614db-3cf5-4a63-889d-1fd1e7bc5ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580252642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3580252642
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2883110029
Short name T193
Test name
Test status
Simulation time 8288417076 ps
CPU time 6.63 seconds
Started Jul 19 04:54:12 PM PDT 24
Finished Jul 19 04:54:21 PM PDT 24
Peak memory 198508 kb
Host smart-ee2513c1-1e50-4145-ae0d-9229c55ae3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883110029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2883110029
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.256204526
Short name T335
Test name
Test status
Simulation time 426303564 ps
CPU time 1.11 seconds
Started Jul 19 04:54:01 PM PDT 24
Finished Jul 19 04:54:05 PM PDT 24
Peak memory 196136 kb
Host smart-36a58833-cb51-41a2-85f2-2f3da603996d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256204526 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.256204526
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1722090303
Short name T312
Test name
Test status
Simulation time 512084240 ps
CPU time 1.47 seconds
Started Jul 19 04:54:00 PM PDT 24
Finished Jul 19 04:54:04 PM PDT 24
Peak memory 193336 kb
Host smart-9c82c020-8f4c-49c8-9311-51f4e273b5ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722090303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1722090303
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.92199877
Short name T377
Test name
Test status
Simulation time 518915103 ps
CPU time 1.38 seconds
Started Jul 19 04:54:03 PM PDT 24
Finished Jul 19 04:54:06 PM PDT 24
Peak memory 184204 kb
Host smart-cdce3bce-28f7-4c2a-a175-07c9e39e6c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92199877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.92199877
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3381886594
Short name T352
Test name
Test status
Simulation time 1827906738 ps
CPU time 1.91 seconds
Started Jul 19 04:54:12 PM PDT 24
Finished Jul 19 04:54:16 PM PDT 24
Peak memory 194264 kb
Host smart-6e7b38fd-3417-4cbe-966e-1ba1f1042806
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381886594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3381886594
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4139912372
Short name T313
Test name
Test status
Simulation time 803350691 ps
CPU time 2.04 seconds
Started Jul 19 04:54:12 PM PDT 24
Finished Jul 19 04:54:16 PM PDT 24
Peak memory 198888 kb
Host smart-42f58a9e-7e11-4fdf-b45d-3db37d64c67a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139912372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4139912372
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1739900739
Short name T414
Test name
Test status
Simulation time 4486524553 ps
CPU time 2.12 seconds
Started Jul 19 04:54:01 PM PDT 24
Finished Jul 19 04:54:05 PM PDT 24
Peak memory 198464 kb
Host smart-e1d0380c-ec7d-4d1d-9ce3-3ea976a4df5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739900739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1739900739
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2675372685
Short name T344
Test name
Test status
Simulation time 673453580 ps
CPU time 0.78 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:13 PM PDT 24
Peak memory 197680 kb
Host smart-b9c80eb9-e9e6-4e33-9491-2205a64e6786
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675372685 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2675372685
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2511719823
Short name T302
Test name
Test status
Simulation time 418519931 ps
CPU time 0.66 seconds
Started Jul 19 04:53:59 PM PDT 24
Finished Jul 19 04:54:02 PM PDT 24
Peak memory 193404 kb
Host smart-e9e72639-60c6-4001-9aab-66ee638f6034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511719823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2511719823
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.285474504
Short name T370
Test name
Test status
Simulation time 506509401 ps
CPU time 0.68 seconds
Started Jul 19 04:54:12 PM PDT 24
Finished Jul 19 04:54:15 PM PDT 24
Peak memory 193288 kb
Host smart-2f8f51bb-2be6-45f1-a443-47794278a87d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285474504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.285474504
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2914214291
Short name T73
Test name
Test status
Simulation time 1041754995 ps
CPU time 1.85 seconds
Started Jul 19 04:54:10 PM PDT 24
Finished Jul 19 04:54:12 PM PDT 24
Peak memory 194264 kb
Host smart-3c1aeb8b-1fff-4296-be17-b41c674729e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914214291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2914214291
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3925981304
Short name T286
Test name
Test status
Simulation time 470414779 ps
CPU time 1.58 seconds
Started Jul 19 04:54:01 PM PDT 24
Finished Jul 19 04:54:05 PM PDT 24
Peak memory 199064 kb
Host smart-7dbfef0c-89d2-4674-864d-66ae2125bd12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925981304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3925981304
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1524101253
Short name T24
Test name
Test status
Simulation time 12335244400 ps
CPU time 8.49 seconds
Started Jul 19 04:38:37 PM PDT 24
Finished Jul 19 04:38:56 PM PDT 24
Peak memory 191520 kb
Host smart-aabe2d19-f760-460b-b2ac-e49d0d86596e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524101253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1524101253
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2277661015
Short name T20
Test name
Test status
Simulation time 7297364408 ps
CPU time 12.17 seconds
Started Jul 19 04:38:31 PM PDT 24
Finished Jul 19 04:38:51 PM PDT 24
Peak memory 215508 kb
Host smart-3ae43505-be3b-4e47-b98a-33dec5c884e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277661015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2277661015
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.712547962
Short name T52
Test name
Test status
Simulation time 397674819 ps
CPU time 0.71 seconds
Started Jul 19 04:38:44 PM PDT 24
Finished Jul 19 04:38:57 PM PDT 24
Peak memory 196248 kb
Host smart-46e9a09a-efb9-418d-8b82-74a7f75eb3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712547962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.712547962
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2159059235
Short name T216
Test name
Test status
Simulation time 10231979310 ps
CPU time 14.84 seconds
Started Jul 19 04:38:42 PM PDT 24
Finished Jul 19 04:39:10 PM PDT 24
Peak memory 191548 kb
Host smart-228ae6dd-dc61-402f-8a07-9bcaaa7ac28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159059235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2159059235
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1973441216
Short name T18
Test name
Test status
Simulation time 4242613479 ps
CPU time 6.39 seconds
Started Jul 19 04:38:33 PM PDT 24
Finished Jul 19 04:38:49 PM PDT 24
Peak memory 215108 kb
Host smart-9f7bcab4-270c-4698-9e8e-c1b9de611615
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973441216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1973441216
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2047364902
Short name T245
Test name
Test status
Simulation time 509361809 ps
CPU time 0.86 seconds
Started Jul 19 04:38:38 PM PDT 24
Finished Jul 19 04:38:50 PM PDT 24
Peak memory 191464 kb
Host smart-94bd03fa-9195-4d1b-8795-73feacbdfd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047364902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2047364902
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1276961873
Short name T241
Test name
Test status
Simulation time 17878769450 ps
CPU time 6.64 seconds
Started Jul 19 04:38:55 PM PDT 24
Finished Jul 19 04:39:40 PM PDT 24
Peak memory 196516 kb
Host smart-e285deb2-a3c5-4e8a-833e-033003d405f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276961873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1276961873
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.219151029
Short name T230
Test name
Test status
Simulation time 470651145 ps
CPU time 0.9 seconds
Started Jul 19 04:38:57 PM PDT 24
Finished Jul 19 04:39:37 PM PDT 24
Peak memory 191424 kb
Host smart-87e8f247-d751-4923-ab92-c234257c5756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219151029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.219151029
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2885352501
Short name T218
Test name
Test status
Simulation time 661632163 ps
CPU time 0.68 seconds
Started Jul 19 04:38:39 PM PDT 24
Finished Jul 19 04:38:52 PM PDT 24
Peak memory 196172 kb
Host smart-c992cdd5-89cf-4a99-bb71-7b81a9c0b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885352501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2885352501
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1080267177
Short name T209
Test name
Test status
Simulation time 502742360 ps
CPU time 1.42 seconds
Started Jul 19 04:38:36 PM PDT 24
Finished Jul 19 04:38:48 PM PDT 24
Peak memory 196216 kb
Host smart-039a69c9-1429-4a8a-9436-4e731897ab47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080267177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1080267177
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_jump.4047868201
Short name T180
Test name
Test status
Simulation time 524084594 ps
CPU time 0.96 seconds
Started Jul 19 04:38:49 PM PDT 24
Finished Jul 19 04:39:23 PM PDT 24
Peak memory 196196 kb
Host smart-5e7e43c8-7aa6-4d0b-b398-c856becc9447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047868201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.4047868201
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4154572630
Short name T205
Test name
Test status
Simulation time 22247909119 ps
CPU time 8.12 seconds
Started Jul 19 04:38:43 PM PDT 24
Finished Jul 19 04:39:04 PM PDT 24
Peak memory 191516 kb
Host smart-cf88b168-9eb8-4338-930a-7339435c15c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154572630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4154572630
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2012709557
Short name T4
Test name
Test status
Simulation time 633782515 ps
CPU time 0.61 seconds
Started Jul 19 04:38:54 PM PDT 24
Finished Jul 19 04:39:34 PM PDT 24
Peak memory 191408 kb
Host smart-d3f26e3b-b05b-41fa-afb3-d70047081106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012709557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2012709557
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1617294744
Short name T12
Test name
Test status
Simulation time 10293500989 ps
CPU time 7.94 seconds
Started Jul 19 04:38:42 PM PDT 24
Finished Jul 19 04:39:02 PM PDT 24
Peak memory 191520 kb
Host smart-18b3e111-0c26-47dc-9803-b60a25c76e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617294744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1617294744
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1648441351
Short name T215
Test name
Test status
Simulation time 584951615 ps
CPU time 0.76 seconds
Started Jul 19 04:38:38 PM PDT 24
Finished Jul 19 04:38:50 PM PDT 24
Peak memory 191416 kb
Host smart-7b393797-fd2e-430a-afcd-a288aa4569d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648441351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1648441351
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2982494716
Short name T251
Test name
Test status
Simulation time 21436021420 ps
CPU time 15.47 seconds
Started Jul 19 04:38:39 PM PDT 24
Finished Jul 19 04:39:06 PM PDT 24
Peak memory 196516 kb
Host smart-cb7e83f7-8eee-4a31-9051-01a313970acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982494716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2982494716
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.96361648
Short name T212
Test name
Test status
Simulation time 508729829 ps
CPU time 0.98 seconds
Started Jul 19 04:38:38 PM PDT 24
Finished Jul 19 04:38:51 PM PDT 24
Peak memory 191440 kb
Host smart-d418daa6-686c-44a3-9db0-0e893cbcb2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96361648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.96361648
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3806395254
Short name T226
Test name
Test status
Simulation time 51233884647 ps
CPU time 81.83 seconds
Started Jul 19 04:38:54 PM PDT 24
Finished Jul 19 04:40:54 PM PDT 24
Peak memory 191504 kb
Host smart-656ec424-a4d5-4df6-9624-0d788ef95b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806395254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3806395254
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1552332219
Short name T3
Test name
Test status
Simulation time 396127988 ps
CPU time 1.06 seconds
Started Jul 19 04:38:41 PM PDT 24
Finished Jul 19 04:38:55 PM PDT 24
Peak memory 191440 kb
Host smart-24a339f7-2777-4739-b636-17ad22e2bd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552332219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1552332219
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2810531079
Short name T248
Test name
Test status
Simulation time 14778706999 ps
CPU time 11.59 seconds
Started Jul 19 04:38:53 PM PDT 24
Finished Jul 19 04:39:44 PM PDT 24
Peak memory 191500 kb
Host smart-dc03dc42-7d72-495c-ba34-0249a2f7230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810531079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2810531079
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2813015442
Short name T206
Test name
Test status
Simulation time 369463231 ps
CPU time 1.08 seconds
Started Jul 19 04:38:33 PM PDT 24
Finished Jul 19 04:38:44 PM PDT 24
Peak memory 191444 kb
Host smart-7cfa1d6e-7617-4bc5-90c4-7c84c2f51a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813015442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2813015442
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2102784577
Short name T169
Test name
Test status
Simulation time 494752965 ps
CPU time 0.98 seconds
Started Jul 19 04:38:48 PM PDT 24
Finished Jul 19 04:39:15 PM PDT 24
Peak memory 196208 kb
Host smart-9b555e44-69be-4668-977b-77d9cde409ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102784577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2102784577
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2194498332
Short name T237
Test name
Test status
Simulation time 1424970331 ps
CPU time 2.5 seconds
Started Jul 19 04:38:38 PM PDT 24
Finished Jul 19 04:38:52 PM PDT 24
Peak memory 191444 kb
Host smart-f46a938d-f630-4174-b465-d8d29df8866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194498332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2194498332
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3012698026
Short name T272
Test name
Test status
Simulation time 614831205 ps
CPU time 1.42 seconds
Started Jul 19 04:38:45 PM PDT 24
Finished Jul 19 04:39:00 PM PDT 24
Peak memory 191400 kb
Host smart-b2175863-7894-4a1c-b3ea-d7f1a4b148fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012698026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3012698026
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2037197462
Short name T10
Test name
Test status
Simulation time 27887088365 ps
CPU time 9.68 seconds
Started Jul 19 04:38:52 PM PDT 24
Finished Jul 19 04:39:42 PM PDT 24
Peak memory 191512 kb
Host smart-d5c49eca-5c36-4271-92de-33ec2919011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037197462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2037197462
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2260232016
Short name T240
Test name
Test status
Simulation time 378920815 ps
CPU time 0.89 seconds
Started Jul 19 04:38:46 PM PDT 24
Finished Jul 19 04:39:00 PM PDT 24
Peak memory 191456 kb
Host smart-d9b794d0-ba97-400f-8321-23aa25db21cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260232016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2260232016
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1520931721
Short name T268
Test name
Test status
Simulation time 44064173752 ps
CPU time 27.64 seconds
Started Jul 19 04:38:49 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 191472 kb
Host smart-69d2a8ff-d8f1-4ac3-b35b-9526b7bb8dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520931721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1520931721
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1551972410
Short name T27
Test name
Test status
Simulation time 558389080 ps
CPU time 0.95 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:38:54 PM PDT 24
Peak memory 191444 kb
Host smart-6e0bf281-d6a3-4aa6-8a3c-092a03c5963b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551972410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1551972410
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.955581503
Short name T243
Test name
Test status
Simulation time 12136865854 ps
CPU time 1.92 seconds
Started Jul 19 04:38:34 PM PDT 24
Finished Jul 19 04:38:46 PM PDT 24
Peak memory 196488 kb
Host smart-c5c1410f-dcc1-4180-8091-a1e10cdda101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955581503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.955581503
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1561703277
Short name T247
Test name
Test status
Simulation time 467576149 ps
CPU time 0.69 seconds
Started Jul 19 04:38:42 PM PDT 24
Finished Jul 19 04:38:56 PM PDT 24
Peak memory 191500 kb
Host smart-e50a9b26-91e0-40dc-8280-7a3441c1fdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561703277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1561703277
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.4225117445
Short name T207
Test name
Test status
Simulation time 61474236107 ps
CPU time 18.46 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:39:10 PM PDT 24
Peak memory 191512 kb
Host smart-8de5b933-555a-4a0d-8042-33263817df76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225117445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4225117445
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.562475191
Short name T235
Test name
Test status
Simulation time 492922671 ps
CPU time 0.66 seconds
Started Jul 19 04:38:44 PM PDT 24
Finished Jul 19 04:38:58 PM PDT 24
Peak memory 191448 kb
Host smart-44ea87e2-b31a-4f3d-be0c-43743316c8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562475191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.562475191
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2782299075
Short name T188
Test name
Test status
Simulation time 493959511 ps
CPU time 0.76 seconds
Started Jul 19 04:38:45 PM PDT 24
Finished Jul 19 04:39:00 PM PDT 24
Peak memory 196244 kb
Host smart-a5aa4bd3-8adb-47d3-857a-f333b45d8f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782299075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2782299075
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2925019951
Short name T278
Test name
Test status
Simulation time 14988344880 ps
CPU time 5.65 seconds
Started Jul 19 04:39:03 PM PDT 24
Finished Jul 19 04:39:50 PM PDT 24
Peak memory 196424 kb
Host smart-8ab1cb76-4ad3-41c8-a149-e615a0a5a548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925019951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2925019951
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1918876985
Short name T257
Test name
Test status
Simulation time 415650958 ps
CPU time 1.2 seconds
Started Jul 19 04:38:58 PM PDT 24
Finished Jul 19 04:39:39 PM PDT 24
Peak memory 191460 kb
Host smart-1ce6714d-6bec-4e60-b726-b3ea4a84ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918876985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1918876985
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3658288263
Short name T220
Test name
Test status
Simulation time 19625024009 ps
CPU time 33.16 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:39:26 PM PDT 24
Peak memory 191468 kb
Host smart-cd502e35-7615-4821-882d-ab7119d69f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658288263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3658288263
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1613900728
Short name T5
Test name
Test status
Simulation time 486520925 ps
CPU time 1.36 seconds
Started Jul 19 04:38:52 PM PDT 24
Finished Jul 19 04:39:35 PM PDT 24
Peak memory 191492 kb
Host smart-4fc6e429-b98d-4c91-b37d-d76a5ce6f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613900728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1613900728
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.536094029
Short name T211
Test name
Test status
Simulation time 23619473340 ps
CPU time 9.15 seconds
Started Jul 19 04:38:57 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 191520 kb
Host smart-4481a6f8-3862-4476-930f-1c4ebb60544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536094029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.536094029
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2137303871
Short name T256
Test name
Test status
Simulation time 406405318 ps
CPU time 1.05 seconds
Started Jul 19 04:38:46 PM PDT 24
Finished Jul 19 04:39:00 PM PDT 24
Peak memory 196288 kb
Host smart-ebb65dc6-f663-4ef8-bcf7-b29b259601e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137303871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2137303871
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1885920627
Short name T261
Test name
Test status
Simulation time 4384735740 ps
CPU time 3.85 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:39:38 PM PDT 24
Peak memory 191460 kb
Host smart-0e191093-63a4-4aa0-910b-3895c80e37bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885920627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1885920627
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3025740395
Short name T236
Test name
Test status
Simulation time 531845508 ps
CPU time 0.72 seconds
Started Jul 19 04:38:51 PM PDT 24
Finished Jul 19 04:39:23 PM PDT 24
Peak memory 191440 kb
Host smart-5db57f92-1cc0-4b1d-b866-9d9511b0f82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025740395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3025740395
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3702073059
Short name T253
Test name
Test status
Simulation time 13371317493 ps
CPU time 19.21 seconds
Started Jul 19 04:38:51 PM PDT 24
Finished Jul 19 04:39:42 PM PDT 24
Peak memory 191564 kb
Host smart-b61a658b-3f62-4222-9fd9-48ff3509458e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702073059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3702073059
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3290473698
Short name T231
Test name
Test status
Simulation time 427031177 ps
CPU time 0.73 seconds
Started Jul 19 04:38:51 PM PDT 24
Finished Jul 19 04:39:23 PM PDT 24
Peak memory 191484 kb
Host smart-95154b4e-a617-4ea1-abf8-4a296f62750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290473698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3290473698
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.515664205
Short name T259
Test name
Test status
Simulation time 41933748169 ps
CPU time 16.81 seconds
Started Jul 19 04:38:46 PM PDT 24
Finished Jul 19 04:39:16 PM PDT 24
Peak memory 191528 kb
Host smart-e434bbd9-66b8-476a-89e0-48184e2b4cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515664205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.515664205
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3250614672
Short name T217
Test name
Test status
Simulation time 614807398 ps
CPU time 0.82 seconds
Started Jul 19 04:38:39 PM PDT 24
Finished Jul 19 04:38:51 PM PDT 24
Peak memory 191488 kb
Host smart-374da80c-9e69-4811-89ea-63948c25b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250614672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3250614672
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.456605364
Short name T281
Test name
Test status
Simulation time 30994831467 ps
CPU time 23.37 seconds
Started Jul 19 04:38:49 PM PDT 24
Finished Jul 19 04:39:52 PM PDT 24
Peak memory 191572 kb
Host smart-25f65964-c888-4842-a199-f37318bfdd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456605364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.456605364
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1513753622
Short name T255
Test name
Test status
Simulation time 421053726 ps
CPU time 0.72 seconds
Started Jul 19 04:38:49 PM PDT 24
Finished Jul 19 04:39:22 PM PDT 24
Peak memory 191464 kb
Host smart-2a40e2b3-3d0e-47d6-9a0e-af4ccfe53acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513753622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1513753622
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1690164740
Short name T246
Test name
Test status
Simulation time 21632913785 ps
CPU time 8 seconds
Started Jul 19 04:39:02 PM PDT 24
Finished Jul 19 04:39:53 PM PDT 24
Peak memory 196476 kb
Host smart-2b1b33f1-4874-43fd-8e87-22d4b349c763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690164740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1690164740
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3433120658
Short name T229
Test name
Test status
Simulation time 382420202 ps
CPU time 0.86 seconds
Started Jul 19 04:38:54 PM PDT 24
Finished Jul 19 04:39:33 PM PDT 24
Peak memory 191416 kb
Host smart-95109fdb-6a37-42aa-b151-05f67a6ab94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433120658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3433120658
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2128662133
Short name T222
Test name
Test status
Simulation time 37471162927 ps
CPU time 48.47 seconds
Started Jul 19 04:39:02 PM PDT 24
Finished Jul 19 04:40:33 PM PDT 24
Peak memory 191524 kb
Host smart-fd8ad276-371b-4222-a2f5-260c41da0433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128662133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2128662133
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3016397192
Short name T153
Test name
Test status
Simulation time 463196962 ps
CPU time 1.17 seconds
Started Jul 19 04:38:47 PM PDT 24
Finished Jul 19 04:39:07 PM PDT 24
Peak memory 191472 kb
Host smart-5734fa72-eee5-412d-8e21-007de9bdb576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016397192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3016397192
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1239028042
Short name T242
Test name
Test status
Simulation time 31536691291 ps
CPU time 50.04 seconds
Started Jul 19 04:38:39 PM PDT 24
Finished Jul 19 04:39:42 PM PDT 24
Peak memory 196452 kb
Host smart-5f3669c7-9964-4f87-978e-19c005023e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239028042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1239028042
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2078697470
Short name T21
Test name
Test status
Simulation time 4086641695 ps
CPU time 6.34 seconds
Started Jul 19 04:38:42 PM PDT 24
Finished Jul 19 04:39:01 PM PDT 24
Peak memory 215148 kb
Host smart-addc9bf5-993a-40ea-a91c-37b02c3672d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078697470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2078697470
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.770205283
Short name T269
Test name
Test status
Simulation time 423557196 ps
CPU time 1.11 seconds
Started Jul 19 04:38:39 PM PDT 24
Finished Jul 19 04:38:53 PM PDT 24
Peak memory 196184 kb
Host smart-5037629c-6eb7-4b9b-8bf6-bddcbcccb1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770205283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.770205283
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2973103269
Short name T227
Test name
Test status
Simulation time 27985695881 ps
CPU time 43.17 seconds
Started Jul 19 04:38:57 PM PDT 24
Finished Jul 19 04:40:20 PM PDT 24
Peak memory 191512 kb
Host smart-0ae078b4-ba98-4538-b634-559d5f2490d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973103269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2973103269
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.912445681
Short name T201
Test name
Test status
Simulation time 437577638 ps
CPU time 0.85 seconds
Started Jul 19 04:38:47 PM PDT 24
Finished Jul 19 04:39:03 PM PDT 24
Peak memory 191432 kb
Host smart-e96702eb-5b7f-4eac-b43e-ee6b08cd3df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912445681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.912445681
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3523111056
Short name T234
Test name
Test status
Simulation time 2674606577 ps
CPU time 4.36 seconds
Started Jul 19 04:39:01 PM PDT 24
Finished Jul 19 04:39:49 PM PDT 24
Peak memory 191572 kb
Host smart-f7d2221a-e427-4a0c-af4f-b57b397406e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523111056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3523111056
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2981669498
Short name T280
Test name
Test status
Simulation time 401729914 ps
CPU time 1.19 seconds
Started Jul 19 04:38:53 PM PDT 24
Finished Jul 19 04:39:34 PM PDT 24
Peak memory 191428 kb
Host smart-588339b2-46a3-4599-bdbe-2b541318f284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981669498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2981669498
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2745420491
Short name T267
Test name
Test status
Simulation time 25522660266 ps
CPU time 9.31 seconds
Started Jul 19 04:39:04 PM PDT 24
Finished Jul 19 04:39:54 PM PDT 24
Peak memory 191528 kb
Host smart-f26cad67-7df4-4dd0-83f7-8107d40d7c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745420491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2745420491
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3711850183
Short name T279
Test name
Test status
Simulation time 447446274 ps
CPU time 0.89 seconds
Started Jul 19 04:39:00 PM PDT 24
Finished Jul 19 04:39:40 PM PDT 24
Peak memory 191416 kb
Host smart-da675da1-cd4e-4f6d-8082-f6d941f6e02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711850183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3711850183
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1757343211
Short name T203
Test name
Test status
Simulation time 36894902855 ps
CPU time 47.23 seconds
Started Jul 19 04:38:55 PM PDT 24
Finished Jul 19 04:40:20 PM PDT 24
Peak memory 191488 kb
Host smart-c43b92bc-abc1-4585-aa68-35c3d80bced5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757343211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1757343211
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2434984896
Short name T25
Test name
Test status
Simulation time 574071315 ps
CPU time 0.81 seconds
Started Jul 19 04:39:01 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 191460 kb
Host smart-2e1f9a5d-0d67-4da4-bb18-53048a7729cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434984896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2434984896
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3266330965
Short name T156
Test name
Test status
Simulation time 565695840 ps
CPU time 1.28 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 196208 kb
Host smart-8ba9fc9e-cc48-4467-b59e-e1651a41a635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266330965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3266330965
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3335903288
Short name T198
Test name
Test status
Simulation time 4409647291 ps
CPU time 7.83 seconds
Started Jul 19 04:39:05 PM PDT 24
Finished Jul 19 04:39:54 PM PDT 24
Peak memory 191524 kb
Host smart-8cf7759d-c1c4-4f07-b677-7e50285c4ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335903288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3335903288
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3282756307
Short name T213
Test name
Test status
Simulation time 527353438 ps
CPU time 0.96 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:39:34 PM PDT 24
Peak memory 191464 kb
Host smart-701e8ce1-2108-4ca2-a393-dee66a8a0231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282756307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3282756307
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.66004712
Short name T155
Test name
Test status
Simulation time 179802746778 ps
CPU time 129.72 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:41:56 PM PDT 24
Peak memory 191640 kb
Host smart-e782c73c-1cf6-4913-9359-76fa8b635f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66004712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_al
l.66004712
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.854867693
Short name T29
Test name
Test status
Simulation time 525945740 ps
CPU time 0.77 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:39:35 PM PDT 24
Peak memory 196232 kb
Host smart-ffa37231-6c7a-4678-bfee-2bab8afcd78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854867693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.854867693
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.992930984
Short name T23
Test name
Test status
Simulation time 36001441148 ps
CPU time 26.68 seconds
Started Jul 19 04:38:57 PM PDT 24
Finished Jul 19 04:40:04 PM PDT 24
Peak memory 196572 kb
Host smart-c8dbd037-5090-419e-9d9c-1508db6496a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992930984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.992930984
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.585223906
Short name T277
Test name
Test status
Simulation time 620739850 ps
CPU time 0.85 seconds
Started Jul 19 04:39:02 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 191464 kb
Host smart-79943ded-3d73-4a56-9a65-171e73add893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585223906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.585223906
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1756915446
Short name T177
Test name
Test status
Simulation time 355758773 ps
CPU time 1.27 seconds
Started Jul 19 04:38:58 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196236 kb
Host smart-edf360a0-0e12-4cbc-9cf4-6569aa6a2f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756915446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1756915446
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.14372627
Short name T254
Test name
Test status
Simulation time 30314161117 ps
CPU time 10.68 seconds
Started Jul 19 04:39:09 PM PDT 24
Finished Jul 19 04:39:57 PM PDT 24
Peak memory 191524 kb
Host smart-fb50cac9-be2b-4e80-a999-b54ba376d3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14372627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.14372627
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3624455654
Short name T233
Test name
Test status
Simulation time 409125013 ps
CPU time 1.14 seconds
Started Jul 19 04:39:07 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 191444 kb
Host smart-62263487-73c6-4bce-8411-5e5adadae994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624455654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3624455654
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2604001308
Short name T244
Test name
Test status
Simulation time 49512472348 ps
CPU time 72.39 seconds
Started Jul 19 04:39:07 PM PDT 24
Finished Jul 19 04:40:58 PM PDT 24
Peak memory 191484 kb
Host smart-646010a6-69d9-457b-afed-96ac414978f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604001308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2604001308
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2760675843
Short name T204
Test name
Test status
Simulation time 498698730 ps
CPU time 0.69 seconds
Started Jul 19 04:38:56 PM PDT 24
Finished Jul 19 04:39:34 PM PDT 24
Peak memory 196216 kb
Host smart-f2b60e18-a8a2-4729-a17f-03c40beec5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760675843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2760675843
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1835831569
Short name T249
Test name
Test status
Simulation time 1369345063 ps
CPU time 0.9 seconds
Started Jul 19 04:39:06 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196192 kb
Host smart-6da0ecac-e6bc-4924-b9cd-e89850e47db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835831569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1835831569
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2982286268
Short name T208
Test name
Test status
Simulation time 407962190 ps
CPU time 1.15 seconds
Started Jul 19 04:39:06 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 191424 kb
Host smart-9792f94a-7b86-49a5-a023-6640824e164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982286268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2982286268
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3959890953
Short name T228
Test name
Test status
Simulation time 44959529262 ps
CPU time 14.99 seconds
Started Jul 19 04:39:05 PM PDT 24
Finished Jul 19 04:40:01 PM PDT 24
Peak memory 191496 kb
Host smart-2b18f07b-9860-4d6b-b488-f7fc91b05da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959890953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3959890953
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2112418897
Short name T264
Test name
Test status
Simulation time 584650466 ps
CPU time 0.69 seconds
Started Jul 19 04:39:08 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 190664 kb
Host smart-7b8f8d64-6b92-4a93-a941-2aa1246dc73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112418897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2112418897
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1949637478
Short name T271
Test name
Test status
Simulation time 20723252476 ps
CPU time 8.76 seconds
Started Jul 19 04:38:46 PM PDT 24
Finished Jul 19 04:39:08 PM PDT 24
Peak memory 191536 kb
Host smart-4b313722-162b-4ce7-90c5-c65fb5139564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949637478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1949637478
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1566002702
Short name T19
Test name
Test status
Simulation time 7582484357 ps
CPU time 11.26 seconds
Started Jul 19 04:38:45 PM PDT 24
Finished Jul 19 04:39:09 PM PDT 24
Peak memory 215448 kb
Host smart-dda2f6ff-6749-495b-a8be-53928683b793
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566002702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1566002702
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3256746492
Short name T22
Test name
Test status
Simulation time 464994558 ps
CPU time 1.25 seconds
Started Jul 19 04:38:30 PM PDT 24
Finished Jul 19 04:38:38 PM PDT 24
Peak memory 196252 kb
Host smart-93c08506-fe93-4e86-b4ab-d052440f8e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256746492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3256746492
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2040455847
Short name T265
Test name
Test status
Simulation time 46359789632 ps
CPU time 56.3 seconds
Started Jul 19 04:39:13 PM PDT 24
Finished Jul 19 04:40:41 PM PDT 24
Peak memory 191480 kb
Host smart-b89f0f4c-00d4-48e3-944a-06a1c37e7276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040455847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2040455847
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2450551166
Short name T270
Test name
Test status
Simulation time 447384717 ps
CPU time 1.32 seconds
Started Jul 19 04:39:06 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196260 kb
Host smart-3ef4762f-0162-441b-b66c-7104c6b51e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450551166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2450551166
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3215151237
Short name T161
Test name
Test status
Simulation time 474932123 ps
CPU time 0.67 seconds
Started Jul 19 04:39:05 PM PDT 24
Finished Jul 19 04:39:46 PM PDT 24
Peak memory 196260 kb
Host smart-f62e7a25-be00-4f9f-8f05-b9c0a4017a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215151237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3215151237
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3886225535
Short name T224
Test name
Test status
Simulation time 16273399869 ps
CPU time 10.93 seconds
Started Jul 19 04:39:04 PM PDT 24
Finished Jul 19 04:39:56 PM PDT 24
Peak memory 191468 kb
Host smart-6092f529-ccc1-4e0b-8fa9-da7660b2a573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886225535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3886225535
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.403429304
Short name T26
Test name
Test status
Simulation time 597574212 ps
CPU time 1.02 seconds
Started Jul 19 04:39:18 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 191412 kb
Host smart-8e2c6c27-9cbc-4419-9889-8dada5e26239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403429304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.403429304
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.529786933
Short name T210
Test name
Test status
Simulation time 14737373390 ps
CPU time 2.18 seconds
Started Jul 19 04:39:11 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196504 kb
Host smart-ece719eb-8a84-4c02-ae08-a8be2ec196f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529786933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.529786933
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3158937976
Short name T262
Test name
Test status
Simulation time 472083797 ps
CPU time 1.19 seconds
Started Jul 19 04:39:04 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 191416 kb
Host smart-9e84ac49-7b26-4518-9265-6458a6d27a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158937976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3158937976
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1023702678
Short name T202
Test name
Test status
Simulation time 19117767199 ps
CPU time 6.82 seconds
Started Jul 19 04:39:07 PM PDT 24
Finished Jul 19 04:39:54 PM PDT 24
Peak memory 191568 kb
Host smart-f3dc40ad-c113-4ad7-b047-4b78ab0828e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023702678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1023702678
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4156021714
Short name T221
Test name
Test status
Simulation time 539720554 ps
CPU time 0.8 seconds
Started Jul 19 04:39:08 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 196364 kb
Host smart-67946b6e-0fd6-4cea-bc44-815e5cdebc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156021714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4156021714
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.303305647
Short name T232
Test name
Test status
Simulation time 51647236503 ps
CPU time 19.48 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:40:06 PM PDT 24
Peak memory 196536 kb
Host smart-6867fb82-030e-496a-b992-89bbf2537585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303305647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.303305647
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2751136429
Short name T263
Test name
Test status
Simulation time 457826199 ps
CPU time 1.31 seconds
Started Jul 19 04:39:07 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 191464 kb
Host smart-a6732290-4395-42d9-bc86-f02b8e26fb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751136429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2751136429
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.260922801
Short name T252
Test name
Test status
Simulation time 8045542777 ps
CPU time 2.87 seconds
Started Jul 19 04:39:09 PM PDT 24
Finished Jul 19 04:39:49 PM PDT 24
Peak memory 191496 kb
Host smart-979bef4a-d669-40d1-946b-ee0334b7649d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260922801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.260922801
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3490542965
Short name T273
Test name
Test status
Simulation time 338147333 ps
CPU time 1.01 seconds
Started Jul 19 04:39:10 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 191456 kb
Host smart-55b0475f-9804-4440-9c52-6850b061d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490542965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3490542965
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1609209614
Short name T13
Test name
Test status
Simulation time 38110753914 ps
CPU time 9.29 seconds
Started Jul 19 04:39:14 PM PDT 24
Finished Jul 19 04:39:55 PM PDT 24
Peak memory 191516 kb
Host smart-4efd894d-15aa-4d40-8a7c-0a292ff497f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609209614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1609209614
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.119820296
Short name T250
Test name
Test status
Simulation time 505684712 ps
CPU time 0.64 seconds
Started Jul 19 04:39:17 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 191460 kb
Host smart-ce131557-f83b-4329-906c-393838148990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119820296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.119820296
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2282419068
Short name T274
Test name
Test status
Simulation time 13727516528 ps
CPU time 20.21 seconds
Started Jul 19 04:39:08 PM PDT 24
Finished Jul 19 04:40:06 PM PDT 24
Peak memory 191516 kb
Host smart-fc196177-db1d-457f-80b5-780653ed7689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282419068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2282419068
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3916285055
Short name T223
Test name
Test status
Simulation time 572776490 ps
CPU time 1.48 seconds
Started Jul 19 04:39:08 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 190728 kb
Host smart-6558cf72-d952-4757-a622-6d017c0c79c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916285055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3916285055
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3702220897
Short name T89
Test name
Test status
Simulation time 39259123193 ps
CPU time 12.88 seconds
Started Jul 19 04:39:16 PM PDT 24
Finished Jul 19 04:39:59 PM PDT 24
Peak memory 191548 kb
Host smart-70a3a7a9-ed28-48b3-9b52-caba54a621b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702220897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3702220897
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.3564785561
Short name T260
Test name
Test status
Simulation time 494443861 ps
CPU time 0.72 seconds
Started Jul 19 04:39:16 PM PDT 24
Finished Jul 19 04:39:47 PM PDT 24
Peak memory 191456 kb
Host smart-e1f96ac7-37ba-4034-a0c5-07091663a523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564785561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.3564785561
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2789119963
Short name T258
Test name
Test status
Simulation time 11436556282 ps
CPU time 17.89 seconds
Started Jul 19 04:39:16 PM PDT 24
Finished Jul 19 04:40:04 PM PDT 24
Peak memory 191516 kb
Host smart-cfbe41c2-28df-448d-af20-339d6733fd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789119963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2789119963
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1827711358
Short name T51
Test name
Test status
Simulation time 435786874 ps
CPU time 0.92 seconds
Started Jul 19 04:39:21 PM PDT 24
Finished Jul 19 04:39:48 PM PDT 24
Peak memory 196340 kb
Host smart-add858d5-3d56-4cf2-8a4b-8776c76f1131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827711358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1827711358
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3215525510
Short name T88
Test name
Test status
Simulation time 26701606906 ps
CPU time 8.9 seconds
Started Jul 19 04:38:39 PM PDT 24
Finished Jul 19 04:39:00 PM PDT 24
Peak memory 191476 kb
Host smart-1f64c255-1ad7-405e-a150-108e2c3bc4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215525510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3215525510
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2706518219
Short name T219
Test name
Test status
Simulation time 560875695 ps
CPU time 0.98 seconds
Started Jul 19 04:38:35 PM PDT 24
Finished Jul 19 04:38:46 PM PDT 24
Peak memory 191412 kb
Host smart-35805b44-9bd1-4e9c-8e23-ee2272eed374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706518219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2706518219
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3244365814
Short name T276
Test name
Test status
Simulation time 37642684491 ps
CPU time 18.06 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:39:10 PM PDT 24
Peak memory 191528 kb
Host smart-7c539148-b8c3-433c-bdb1-5e8e77bbf66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244365814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3244365814
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2772837266
Short name T275
Test name
Test status
Simulation time 570732447 ps
CPU time 0.77 seconds
Started Jul 19 04:38:32 PM PDT 24
Finished Jul 19 04:38:41 PM PDT 24
Peak memory 191460 kb
Host smart-1e8d3d97-c30c-475c-b3aa-2dc29b1c8799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772837266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2772837266
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.329950548
Short name T266
Test name
Test status
Simulation time 7868062463 ps
CPU time 3.39 seconds
Started Jul 19 04:38:20 PM PDT 24
Finished Jul 19 04:38:28 PM PDT 24
Peak memory 191640 kb
Host smart-3c1fe927-8d9f-4a39-83c0-32bd2aa0e5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329950548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.329950548
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1876699036
Short name T91
Test name
Test status
Simulation time 427752186 ps
CPU time 0.72 seconds
Started Jul 19 04:38:31 PM PDT 24
Finished Jul 19 04:38:40 PM PDT 24
Peak memory 196284 kb
Host smart-c9606fb1-456e-4713-967f-d6f311b07924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876699036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1876699036
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3602647111
Short name T225
Test name
Test status
Simulation time 46944222095 ps
CPU time 10.31 seconds
Started Jul 19 04:38:36 PM PDT 24
Finished Jul 19 04:38:57 PM PDT 24
Peak memory 196516 kb
Host smart-292358fb-9938-4715-9942-e583f42462a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602647111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3602647111
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.162312098
Short name T238
Test name
Test status
Simulation time 390470099 ps
CPU time 0.81 seconds
Started Jul 19 04:38:40 PM PDT 24
Finished Jul 19 04:38:52 PM PDT 24
Peak memory 191460 kb
Host smart-18efb276-a36d-4bf4-a958-40383feecf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162312098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.162312098
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1872246185
Short name T214
Test name
Test status
Simulation time 16434526203 ps
CPU time 26.04 seconds
Started Jul 19 04:38:52 PM PDT 24
Finished Jul 19 04:39:59 PM PDT 24
Peak memory 196524 kb
Host smart-913ceae0-ea04-45fd-bc06-ec65e1c1d295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872246185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1872246185
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2408571215
Short name T239
Test name
Test status
Simulation time 542533932 ps
CPU time 0.85 seconds
Started Jul 19 04:38:45 PM PDT 24
Finished Jul 19 04:38:59 PM PDT 24
Peak memory 196236 kb
Host smart-5d5d75da-1a8b-4c86-905a-796ae713b31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408571215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2408571215
Directory /workspace/9.aon_timer_smoke/latest
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