Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 31933 1 T1 694 T2 497 T3 282
bark[1] 201 1 T43 68 T99 21 T175 21
bark[2] 1362 1 T80 122 T124 21 T137 47
bark[3] 103 1 T2 21 T42 14 T82 33
bark[4] 335 1 T43 21 T159 47 T137 21
bark[5] 196 1 T34 14 T18 21 T178 23
bark[6] 841 1 T1 225 T28 7 T36 208
bark[7] 355 1 T4 42 T43 26 T113 14
bark[8] 991 1 T1 26 T2 129 T43 146
bark[9] 566 1 T11 85 T192 14 T99 26
bark[10] 857 1 T36 226 T21 14 T51 14
bark[11] 794 1 T1 7 T4 21 T27 254
bark[12] 434 1 T49 21 T82 21 T155 35
bark[13] 492 1 T28 66 T18 21 T147 14
bark[14] 729 1 T8 26 T28 24 T80 227
bark[15] 310 1 T26 21 T38 14 T36 21
bark[16] 731 1 T43 155 T46 14 T126 21
bark[17] 558 1 T5 49 T126 21 T166 71
bark[18] 416 1 T4 56 T28 26 T35 229
bark[19] 411 1 T10 14 T35 47 T80 26
bark[20] 376 1 T49 21 T83 73 T122 14
bark[21] 803 1 T28 147 T194 14 T82 41
bark[22] 750 1 T1 119 T17 57 T82 142
bark[23] 632 1 T80 21 T43 21 T98 132
bark[24] 463 1 T98 212 T175 52 T104 5
bark[25] 690 1 T11 50 T80 21 T43 104
bark[26] 242 1 T5 39 T144 14 T99 49
bark[27] 725 1 T2 40 T36 21 T19 21
bark[28] 753 1 T1 255 T35 48 T36 247
bark[29] 349 1 T1 42 T3 31 T5 26
bark[30] 586 1 T102 64 T157 47 T111 21
bark[31] 291 1 T2 73 T11 26 T26 21
bark_0 4630 1 T1 84 T2 75 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 31970 1 T1 656 T2 541 T3 281
bite[1] 778 1 T43 154 T98 21 T175 52
bite[2] 675 1 T20 21 T191 13 T166 71
bite[3] 860 1 T3 31 T102 21 T123 30
bite[4] 848 1 T1 172 T4 21 T137 21
bite[5] 742 1 T1 26 T34 13 T36 251
bite[6] 305 1 T107 13 T108 13 T164 71
bite[7] 441 1 T80 26 T20 51 T43 26
bite[8] 138 1 T4 35 T21 13 T45 13
bite[9] 932 1 T5 39 T194 13 T80 121
bite[10] 477 1 T2 149 T10 13 T18 21
bite[11] 213 1 T165 13 T126 21 T159 46
bite[12] 905 1 T27 253 T80 21 T117 21
bite[13] 416 1 T36 204 T162 21 T157 55
bite[14] 582 1 T28 25 T43 42 T49 21
bite[15] 667 1 T1 117 T26 21 T28 6
bite[16] 994 1 T2 39 T4 21 T43 21
bite[17] 711 1 T28 146 T43 248 T82 33
bite[18] 334 1 T42 13 T98 21 T162 42
bite[19] 564 1 T1 136 T4 21 T5 26
bite[20] 297 1 T1 21 T43 67 T150 21
bite[21] 243 1 T80 21 T43 21 T136 13
bite[22] 489 1 T11 84 T38 13 T102 6
bite[23] 189 1 T35 47 T99 21 T96 21
bite[24] 382 1 T4 21 T28 23 T39 13
bite[25] 551 1 T1 6 T46 13 T123 21
bite[26] 1146 1 T2 21 T5 49 T28 65
bite[27] 164 1 T11 25 T36 21 T43 21
bite[28] 373 1 T26 21 T147 13 T182 13
bite[29] 723 1 T1 224 T82 21 T188 13
bite[30] 314 1 T11 49 T36 21 T17 32
bite[31] 376 1 T19 21 T155 34 T98 254
bite_0 5106 1 T1 94 T2 85 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 46666 1 T1 1236 T2 632 T3 320
auto[1] 7239 1 T1 216 T2 203 T8 19


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 594 1 T1 133 T3 9 T11 9
prescale[1] 1046 1 T2 37 T11 163 T27 49
prescale[2] 1125 1 T1 93 T27 64 T49 37
prescale[3] 967 1 T3 40 T11 24 T35 24
prescale[4] 723 1 T2 55 T3 19 T4 19
prescale[5] 1256 1 T1 9 T4 59 T27 80
prescale[6] 966 1 T5 77 T7 9 T11 2
prescale[7] 836 1 T1 19 T4 19 T35 19
prescale[8] 1066 1 T4 84 T11 21 T26 55
prescale[9] 877 1 T3 28 T4 2 T26 19
prescale[10] 794 1 T2 2 T3 24 T4 151
prescale[11] 1445 1 T8 28 T11 9 T27 106
prescale[12] 869 1 T2 19 T8 19 T11 88
prescale[13] 778 1 T8 29 T11 40 T27 138
prescale[14] 943 1 T2 2 T11 2 T26 122
prescale[15] 873 1 T2 29 T80 2 T17 19
prescale[16] 968 1 T2 203 T3 23 T4 129
prescale[17] 860 1 T1 250 T2 2 T3 28
prescale[18] 964 1 T1 2 T2 19 T5 23
prescale[19] 447 1 T1 19 T3 19 T80 28
prescale[20] 1563 1 T1 2 T2 23 T4 59
prescale[21] 1116 1 T1 55 T2 68 T4 79
prescale[22] 1008 1 T2 23 T3 19 T4 9
prescale[23] 1306 1 T1 80 T4 97 T26 18
prescale[24] 1157 1 T1 108 T4 67 T11 105
prescale[25] 456 1 T1 67 T27 2 T36 52
prescale[26] 315 1 T19 19 T150 42 T158 37
prescale[27] 1042 1 T1 107 T2 2 T4 19
prescale[28] 940 1 T3 19 T8 28 T27 172
prescale[29] 641 1 T11 2 T35 2 T49 36
prescale[30] 782 1 T1 38 T28 2 T41 9
prescale[31] 728 1 T1 73 T2 2 T27 2
prescale_0 24454 1 T1 397 T2 349 T3 92


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 40590 1 T1 1161 T2 642 T3 189
auto[1] 13315 1 T1 291 T2 193 T3 131


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 53905 1 T1 1452 T2 835 T3 320


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 31659 1 T1 833 T2 450 T3 242
wkup[1] 351 1 T1 72 T5 49 T35 30
wkup[2] 390 1 T11 21 T27 15 T35 30
wkup[3] 271 1 T27 21 T191 15 T83 21
wkup[4] 400 1 T1 21 T2 8 T4 21
wkup[5] 273 1 T4 30 T11 21 T36 30
wkup[6] 275 1 T2 21 T4 21 T80 30
wkup[7] 325 1 T4 21 T27 21 T28 21
wkup[8] 331 1 T2 56 T27 21 T165 15
wkup[9] 451 1 T1 21 T36 42 T49 21
wkup[10] 317 1 T3 31 T11 21 T28 8
wkup[11] 358 1 T1 21 T2 56 T27 21
wkup[12] 383 1 T4 21 T28 42 T36 15
wkup[13] 291 1 T27 21 T80 21 T82 8
wkup[14] 294 1 T27 21 T43 21 T102 21
wkup[15] 241 1 T10 15 T28 21 T80 69
wkup[16] 471 1 T2 26 T4 21 T36 47
wkup[17] 402 1 T11 21 T26 21 T35 26
wkup[18] 334 1 T27 21 T36 21 T19 21
wkup[19] 318 1 T11 21 T27 21 T80 42
wkup[20] 146 1 T80 21 T43 21 T159 26
wkup[21] 267 1 T8 30 T27 21 T18 21
wkup[22] 141 1 T80 21 T163 21 T94 21
wkup[23] 365 1 T4 21 T11 42 T28 21
wkup[24] 266 1 T82 21 T83 21 T116 26
wkup[25] 224 1 T2 21 T35 26 T80 42
wkup[26] 186 1 T1 42 T159 21 T174 30
wkup[27] 249 1 T1 21 T36 21 T82 21
wkup[28] 303 1 T11 21 T27 30 T99 30
wkup[29] 358 1 T1 29 T36 21 T80 15
wkup[30] 344 1 T2 15 T5 39 T11 26
wkup[31] 227 1 T1 42 T43 51 T82 21
wkup[32] 468 1 T2 21 T3 21 T28 21
wkup[33] 241 1 T43 21 T137 21 T150 21
wkup[34] 233 1 T1 42 T28 21 T102 21
wkup[35] 393 1 T2 21 T11 21 T26 26
wkup[36] 282 1 T11 21 T27 21 T80 21
wkup[37] 306 1 T2 21 T4 35 T36 62
wkup[38] 290 1 T11 21 T27 21 T28 21
wkup[39] 234 1 T1 21 T27 21 T35 15
wkup[40] 191 1 T1 42 T28 21 T194 15
wkup[41] 179 1 T4 26 T26 21 T157 30
wkup[42] 170 1 T158 21 T173 15 T116 21
wkup[43] 221 1 T11 21 T102 21 T159 21
wkup[44] 459 1 T27 21 T35 21 T80 21
wkup[45] 186 1 T1 26 T4 21 T35 21
wkup[46] 345 1 T1 21 T2 35 T4 35
wkup[47] 348 1 T11 21 T26 21 T27 21
wkup[48] 210 1 T80 21 T102 26 T82 21
wkup[49] 229 1 T159 21 T150 26 T84 21
wkup[50] 133 1 T11 21 T28 21 T98 8
wkup[51] 353 1 T2 21 T27 15 T28 21
wkup[52] 207 1 T1 30 T102 8 T150 21
wkup[53] 345 1 T5 26 T11 21 T43 21
wkup[54] 226 1 T1 15 T36 21 T82 26
wkup[55] 279 1 T35 21 T43 21 T82 8
wkup[56] 246 1 T1 21 T3 21 T4 21
wkup[57] 546 1 T1 26 T28 21 T80 21
wkup[58] 202 1 T1 21 T27 26 T160 30
wkup[59] 307 1 T11 21 T80 60 T43 8
wkup[60] 365 1 T8 26 T20 30 T45 15
wkup[61] 322 1 T1 21 T4 42 T34 15
wkup[62] 296 1 T18 21 T98 36 T166 21
wkup[63] 341 1 T2 8 T28 26 T36 21
wkup_0 3541 1 T1 64 T2 55 T3 5

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