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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.01 99.33 93.67 100.00 98.40 99.51 49.15


Total test records in report: 419
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T70 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2087016930 Jul 20 05:55:38 PM PDT 24 Jul 20 05:55:49 PM PDT 24 2894668298 ps
T283 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1999213659 Jul 20 05:55:55 PM PDT 24 Jul 20 05:55:57 PM PDT 24 397398618 ps
T284 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2029317374 Jul 20 05:55:38 PM PDT 24 Jul 20 05:55:41 PM PDT 24 338756280 ps
T285 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3165506266 Jul 20 05:55:57 PM PDT 24 Jul 20 05:55:59 PM PDT 24 310669657 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1633766193 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:37 PM PDT 24 453786441 ps
T71 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2341854735 Jul 20 05:55:40 PM PDT 24 Jul 20 05:55:44 PM PDT 24 1434512532 ps
T286 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1400486206 Jul 20 05:55:58 PM PDT 24 Jul 20 05:56:00 PM PDT 24 341208830 ps
T72 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4258844515 Jul 20 05:55:42 PM PDT 24 Jul 20 05:55:47 PM PDT 24 474285524 ps
T32 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2852013322 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:58 PM PDT 24 7698829786 ps
T287 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2397779811 Jul 20 05:55:33 PM PDT 24 Jul 20 05:55:38 PM PDT 24 420108612 ps
T33 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4154695185 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:55 PM PDT 24 7729231829 ps
T288 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2847521555 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:49 PM PDT 24 367252246 ps
T289 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3076682671 Jul 20 05:55:33 PM PDT 24 Jul 20 05:55:37 PM PDT 24 295712929 ps
T73 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2352098410 Jul 20 05:55:42 PM PDT 24 Jul 20 05:55:47 PM PDT 24 1155720984 ps
T195 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1375207715 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:56 PM PDT 24 4493529838 ps
T290 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.292398230 Jul 20 05:55:33 PM PDT 24 Jul 20 05:55:39 PM PDT 24 2045555775 ps
T291 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1001454000 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:34 PM PDT 24 559696279 ps
T53 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1782985187 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:50 PM PDT 24 318561515 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.216371513 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:43 PM PDT 24 7570756191 ps
T74 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2484348775 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:48 PM PDT 24 1293576729 ps
T75 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.9616269 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:51 PM PDT 24 1237498291 ps
T292 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3523765030 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:35 PM PDT 24 315518409 ps
T293 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1119063994 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:37 PM PDT 24 377899544 ps
T294 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.239412047 Jul 20 05:55:55 PM PDT 24 Jul 20 05:55:58 PM PDT 24 432250175 ps
T295 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1549362981 Jul 20 05:55:54 PM PDT 24 Jul 20 05:55:56 PM PDT 24 339657884 ps
T198 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1905726292 Jul 20 05:55:52 PM PDT 24 Jul 20 05:56:00 PM PDT 24 4382178785 ps
T296 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1396318599 Jul 20 05:55:55 PM PDT 24 Jul 20 05:55:57 PM PDT 24 388595050 ps
T297 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.340741792 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:35 PM PDT 24 295267114 ps
T298 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1141133384 Jul 20 05:55:30 PM PDT 24 Jul 20 05:55:35 PM PDT 24 889536641 ps
T299 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2584134380 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:36 PM PDT 24 777272508 ps
T300 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3210580855 Jul 20 05:56:00 PM PDT 24 Jul 20 05:56:01 PM PDT 24 332463278 ps
T55 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4084411589 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:42 PM PDT 24 7542645219 ps
T196 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1000973838 Jul 20 05:55:46 PM PDT 24 Jul 20 05:55:57 PM PDT 24 8594710295 ps
T301 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3002475903 Jul 20 05:55:29 PM PDT 24 Jul 20 05:55:32 PM PDT 24 384446250 ps
T302 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.895976474 Jul 20 05:55:55 PM PDT 24 Jul 20 05:55:56 PM PDT 24 436689518 ps
T76 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3095789708 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:48 PM PDT 24 1213985143 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.841723525 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:45 PM PDT 24 387004921 ps
T56 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3658503694 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:36 PM PDT 24 348384641 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3541358358 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:35 PM PDT 24 474861405 ps
T304 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1896696077 Jul 20 05:55:56 PM PDT 24 Jul 20 05:55:58 PM PDT 24 399239404 ps
T305 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1991556580 Jul 20 05:55:48 PM PDT 24 Jul 20 05:55:52 PM PDT 24 403781615 ps
T306 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2112959428 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:36 PM PDT 24 509391711 ps
T307 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4016902114 Jul 20 05:55:49 PM PDT 24 Jul 20 05:55:54 PM PDT 24 586255480 ps
T308 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2999153971 Jul 20 05:55:54 PM PDT 24 Jul 20 05:55:57 PM PDT 24 500321481 ps
T197 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2197750247 Jul 20 05:55:36 PM PDT 24 Jul 20 05:55:41 PM PDT 24 4221020589 ps
T309 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2361557522 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:42 PM PDT 24 264837532 ps
T310 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3866611250 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:36 PM PDT 24 456807199 ps
T77 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.188610215 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:45 PM PDT 24 1351686620 ps
T311 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.455557291 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:37 PM PDT 24 492692064 ps
T312 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2743209933 Jul 20 05:55:47 PM PDT 24 Jul 20 05:55:53 PM PDT 24 2394622578 ps
T313 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.526870770 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:46 PM PDT 24 513687000 ps
T314 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2990963735 Jul 20 05:55:56 PM PDT 24 Jul 20 05:55:58 PM PDT 24 488493952 ps
T315 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1249946095 Jul 20 05:55:52 PM PDT 24 Jul 20 05:55:55 PM PDT 24 455053550 ps
T316 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.430995343 Jul 20 05:55:56 PM PDT 24 Jul 20 05:55:58 PM PDT 24 396388012 ps
T58 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3179147388 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:48 PM PDT 24 351513548 ps
T317 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3011426998 Jul 20 05:55:55 PM PDT 24 Jul 20 05:55:58 PM PDT 24 495491170 ps
T318 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1940583181 Jul 20 05:55:40 PM PDT 24 Jul 20 05:55:44 PM PDT 24 422492151 ps
T59 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.317330590 Jul 20 05:55:47 PM PDT 24 Jul 20 05:55:52 PM PDT 24 406316136 ps
T60 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3922019540 Jul 20 05:55:44 PM PDT 24 Jul 20 05:55:49 PM PDT 24 543782217 ps
T319 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3183165290 Jul 20 05:55:46 PM PDT 24 Jul 20 05:55:54 PM PDT 24 2504337669 ps
T320 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1455506932 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:47 PM PDT 24 4509714514 ps
T321 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2597876962 Jul 20 05:55:50 PM PDT 24 Jul 20 05:55:54 PM PDT 24 1551976221 ps
T322 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2700104666 Jul 20 05:55:36 PM PDT 24 Jul 20 05:55:53 PM PDT 24 8949968195 ps
T323 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2835707908 Jul 20 05:55:30 PM PDT 24 Jul 20 05:55:35 PM PDT 24 7318755092 ps
T324 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.167399127 Jul 20 05:55:44 PM PDT 24 Jul 20 05:56:01 PM PDT 24 8343638444 ps
T325 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1219557337 Jul 20 05:55:40 PM PDT 24 Jul 20 05:55:44 PM PDT 24 883865946 ps
T326 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.88897829 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:52 PM PDT 24 4418667726 ps
T327 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3186553944 Jul 20 05:55:46 PM PDT 24 Jul 20 05:55:52 PM PDT 24 4323337084 ps
T328 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.901906181 Jul 20 05:55:58 PM PDT 24 Jul 20 05:56:00 PM PDT 24 415930917 ps
T329 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2944931872 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:45 PM PDT 24 435132261 ps
T330 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3698790739 Jul 20 05:55:55 PM PDT 24 Jul 20 05:55:57 PM PDT 24 378653547 ps
T331 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1256525964 Jul 20 05:55:58 PM PDT 24 Jul 20 05:56:00 PM PDT 24 415995774 ps
T332 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.644765623 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:50 PM PDT 24 471803940 ps
T333 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.179187404 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:43 PM PDT 24 557775476 ps
T334 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.299929838 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:51 PM PDT 24 411641967 ps
T335 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4002479982 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:51 PM PDT 24 439083042 ps
T336 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.323854772 Jul 20 05:55:27 PM PDT 24 Jul 20 05:55:30 PM PDT 24 315653245 ps
T337 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.312343601 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:44 PM PDT 24 8477001570 ps
T338 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3492180533 Jul 20 05:55:42 PM PDT 24 Jul 20 05:55:48 PM PDT 24 521466426 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2211088254 Jul 20 05:55:44 PM PDT 24 Jul 20 05:55:49 PM PDT 24 436847315 ps
T339 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3103040035 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:48 PM PDT 24 580660072 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2409067543 Jul 20 05:55:40 PM PDT 24 Jul 20 05:55:44 PM PDT 24 344263171 ps
T340 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.197961762 Jul 20 05:55:40 PM PDT 24 Jul 20 05:55:43 PM PDT 24 437346926 ps
T341 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2583462691 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:46 PM PDT 24 4281939018 ps
T65 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2352471289 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:49 PM PDT 24 597729716 ps
T342 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2066435185 Jul 20 05:56:01 PM PDT 24 Jul 20 05:56:02 PM PDT 24 349695014 ps
T343 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1573316391 Jul 20 05:55:30 PM PDT 24 Jul 20 05:55:34 PM PDT 24 312845125 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3226416266 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:37 PM PDT 24 297128392 ps
T345 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2217754353 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:46 PM PDT 24 383143888 ps
T346 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4049583768 Jul 20 05:55:42 PM PDT 24 Jul 20 05:55:49 PM PDT 24 584597309 ps
T347 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2579123836 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:50 PM PDT 24 454283293 ps
T348 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2981746439 Jul 20 05:55:44 PM PDT 24 Jul 20 05:55:49 PM PDT 24 347075739 ps
T349 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.102544930 Jul 20 05:55:44 PM PDT 24 Jul 20 05:55:50 PM PDT 24 393264570 ps
T350 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.162521118 Jul 20 05:55:48 PM PDT 24 Jul 20 05:55:53 PM PDT 24 427389354 ps
T66 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3483039420 Jul 20 05:55:54 PM PDT 24 Jul 20 05:55:55 PM PDT 24 476540806 ps
T351 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3439087564 Jul 20 05:55:46 PM PDT 24 Jul 20 05:55:57 PM PDT 24 4483463879 ps
T352 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2137907955 Jul 20 05:55:48 PM PDT 24 Jul 20 05:55:52 PM PDT 24 342031768 ps
T353 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2822642611 Jul 20 05:55:56 PM PDT 24 Jul 20 05:55:58 PM PDT 24 445919810 ps
T354 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.412791596 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:49 PM PDT 24 7901210690 ps
T355 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1726326506 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:48 PM PDT 24 1258224048 ps
T356 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3464431276 Jul 20 05:55:47 PM PDT 24 Jul 20 05:55:53 PM PDT 24 765044016 ps
T357 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4050014130 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:47 PM PDT 24 396111060 ps
T358 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1817336215 Jul 20 05:55:57 PM PDT 24 Jul 20 05:55:59 PM PDT 24 337524508 ps
T61 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.61386455 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:48 PM PDT 24 459981218 ps
T359 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1121978996 Jul 20 05:55:48 PM PDT 24 Jul 20 05:55:53 PM PDT 24 1186091106 ps
T360 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3948292826 Jul 20 05:55:49 PM PDT 24 Jul 20 05:55:54 PM PDT 24 2018129107 ps
T68 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.143359669 Jul 20 05:55:49 PM PDT 24 Jul 20 05:55:53 PM PDT 24 377768516 ps
T361 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3428108839 Jul 20 05:55:58 PM PDT 24 Jul 20 05:56:00 PM PDT 24 464516864 ps
T362 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2300499828 Jul 20 05:55:38 PM PDT 24 Jul 20 05:55:41 PM PDT 24 541425722 ps
T363 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2507664778 Jul 20 05:55:49 PM PDT 24 Jul 20 05:55:53 PM PDT 24 643088718 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2728717631 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:47 PM PDT 24 292034428 ps
T364 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.936719285 Jul 20 05:55:44 PM PDT 24 Jul 20 05:55:50 PM PDT 24 4346238776 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2633262718 Jul 20 05:55:32 PM PDT 24 Jul 20 05:55:40 PM PDT 24 8585993227 ps
T366 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1739369544 Jul 20 05:56:01 PM PDT 24 Jul 20 05:56:03 PM PDT 24 453648788 ps
T367 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2089376128 Jul 20 05:55:54 PM PDT 24 Jul 20 05:55:55 PM PDT 24 498603161 ps
T368 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2718980084 Jul 20 05:55:44 PM PDT 24 Jul 20 05:55:49 PM PDT 24 374822220 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.594119015 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:50 PM PDT 24 472188355 ps
T370 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1729341622 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:43 PM PDT 24 555674359 ps
T371 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.948227073 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:49 PM PDT 24 742922562 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3907995500 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:43 PM PDT 24 13299562693 ps
T372 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1351114085 Jul 20 05:55:47 PM PDT 24 Jul 20 05:55:53 PM PDT 24 2366259391 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1693528648 Jul 20 05:55:34 PM PDT 24 Jul 20 05:55:39 PM PDT 24 491592807 ps
T374 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2323596389 Jul 20 05:55:50 PM PDT 24 Jul 20 05:55:53 PM PDT 24 419003845 ps
T375 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3633575768 Jul 20 05:55:30 PM PDT 24 Jul 20 05:55:34 PM PDT 24 706718368 ps
T376 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3590651109 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:48 PM PDT 24 429805642 ps
T62 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.799139750 Jul 20 05:55:46 PM PDT 24 Jul 20 05:55:51 PM PDT 24 440817280 ps
T377 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.174364923 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:50 PM PDT 24 421798031 ps
T378 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2799441305 Jul 20 05:55:46 PM PDT 24 Jul 20 05:55:51 PM PDT 24 522436525 ps
T379 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1308169628 Jul 20 05:55:45 PM PDT 24 Jul 20 05:55:53 PM PDT 24 8046444494 ps
T380 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2115112699 Jul 20 05:55:38 PM PDT 24 Jul 20 05:55:42 PM PDT 24 282689405 ps
T381 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2725588505 Jul 20 05:55:36 PM PDT 24 Jul 20 05:55:41 PM PDT 24 324738687 ps
T382 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2580900975 Jul 20 05:55:44 PM PDT 24 Jul 20 05:55:51 PM PDT 24 1072951701 ps
T383 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.856818031 Jul 20 05:55:46 PM PDT 24 Jul 20 05:55:51 PM PDT 24 2430768545 ps
T384 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2007926690 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:47 PM PDT 24 466219411 ps
T385 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3256147402 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:46 PM PDT 24 503763547 ps
T386 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4029047166 Jul 20 05:55:51 PM PDT 24 Jul 20 05:55:53 PM PDT 24 596635232 ps
T387 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3668086038 Jul 20 05:55:48 PM PDT 24 Jul 20 05:55:53 PM PDT 24 406485204 ps
T388 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3288500176 Jul 20 05:55:59 PM PDT 24 Jul 20 05:56:01 PM PDT 24 549400671 ps
T389 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.125601681 Jul 20 05:55:28 PM PDT 24 Jul 20 05:55:31 PM PDT 24 640691783 ps
T390 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1259357372 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:41 PM PDT 24 562228334 ps
T391 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.539154422 Jul 20 05:55:55 PM PDT 24 Jul 20 05:55:57 PM PDT 24 596368197 ps
T392 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2170140995 Jul 20 05:55:48 PM PDT 24 Jul 20 05:55:53 PM PDT 24 582867463 ps
T393 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1060056128 Jul 20 05:55:53 PM PDT 24 Jul 20 05:55:55 PM PDT 24 424380578 ps
T394 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2728714004 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:43 PM PDT 24 311926394 ps
T395 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3344327450 Jul 20 05:55:41 PM PDT 24 Jul 20 05:55:46 PM PDT 24 1307151719 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2524344367 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:42 PM PDT 24 415043784 ps
T397 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1963338592 Jul 20 05:55:40 PM PDT 24 Jul 20 05:55:44 PM PDT 24 712642093 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1625198338 Jul 20 05:55:46 PM PDT 24 Jul 20 05:55:51 PM PDT 24 467427972 ps
T399 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2932501632 Jul 20 05:55:42 PM PDT 24 Jul 20 05:55:47 PM PDT 24 421526875 ps
T400 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3328352461 Jul 20 05:55:54 PM PDT 24 Jul 20 05:55:55 PM PDT 24 312290517 ps
T401 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2683685863 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:42 PM PDT 24 1331857022 ps
T402 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.881555819 Jul 20 05:55:55 PM PDT 24 Jul 20 05:55:57 PM PDT 24 503079318 ps
T403 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2892794964 Jul 20 05:55:43 PM PDT 24 Jul 20 05:55:49 PM PDT 24 699066231 ps
T404 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3750642879 Jul 20 05:55:58 PM PDT 24 Jul 20 05:56:00 PM PDT 24 347730273 ps
T405 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3111455658 Jul 20 05:55:35 PM PDT 24 Jul 20 05:55:40 PM PDT 24 2699918931 ps
T406 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2081544615 Jul 20 05:55:42 PM PDT 24 Jul 20 05:55:47 PM PDT 24 668271316 ps
T407 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2290093038 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:45 PM PDT 24 7396441234 ps
T408 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1755191777 Jul 20 05:55:40 PM PDT 24 Jul 20 05:55:45 PM PDT 24 474543356 ps
T409 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1008661954 Jul 20 05:55:39 PM PDT 24 Jul 20 05:55:42 PM PDT 24 508192792 ps
T410 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2032776682 Jul 20 05:55:58 PM PDT 24 Jul 20 05:56:00 PM PDT 24 273304848 ps
T411 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3177847597 Jul 20 05:55:55 PM PDT 24 Jul 20 05:55:57 PM PDT 24 436829820 ps
T412 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.391744420 Jul 20 05:55:58 PM PDT 24 Jul 20 05:55:59 PM PDT 24 435993485 ps
T413 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3148221625 Jul 20 05:55:49 PM PDT 24 Jul 20 05:55:53 PM PDT 24 278132422 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1992849003 Jul 20 05:55:37 PM PDT 24 Jul 20 05:55:40 PM PDT 24 275224709 ps
T415 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3082507037 Jul 20 05:56:00 PM PDT 24 Jul 20 05:56:02 PM PDT 24 335977022 ps
T416 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2784629979 Jul 20 05:55:46 PM PDT 24 Jul 20 05:55:57 PM PDT 24 4251072400 ps
T417 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1737952623 Jul 20 05:55:40 PM PDT 24 Jul 20 05:55:44 PM PDT 24 759688364 ps
T418 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2864976971 Jul 20 05:55:31 PM PDT 24 Jul 20 05:55:36 PM PDT 24 2628278934 ps
T419 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3139750645 Jul 20 05:55:42 PM PDT 24 Jul 20 05:55:47 PM PDT 24 1341543177 ps

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.217174089
Short name T2
Test name
Test status
Simulation time 269282478949 ps
CPU time 740.37 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:58:31 PM PDT 24
Peak memory 214620 kb
Host smart-62826a62-490c-4035-bfd9-75cbee9cabf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217174089 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.217174089
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3079803767
Short name T30
Test name
Test status
Simulation time 8467185742 ps
CPU time 4.58 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:55 PM PDT 24
Peak memory 198540 kb
Host smart-df3ebffb-1224-4a72-ac73-08d275be9d9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079803767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3079803767
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3382901144
Short name T43
Test name
Test status
Simulation time 68919707405 ps
CPU time 419.27 seconds
Started Jul 20 05:46:23 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 200364 kb
Host smart-52325539-0f06-46e8-8e4c-c48109fe6106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382901144 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3382901144
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.387842549
Short name T8
Test name
Test status
Simulation time 201547970802 ps
CPU time 277.06 seconds
Started Jul 20 05:46:24 PM PDT 24
Finished Jul 20 05:51:02 PM PDT 24
Peak memory 192600 kb
Host smart-bef939bb-7c29-451a-b6a9-307fa330743d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387842549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.387842549
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.4078315001
Short name T95
Test name
Test status
Simulation time 167455083825 ps
CPU time 717.88 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:58:08 PM PDT 24
Peak memory 206080 kb
Host smart-a21807a9-2e1a-445d-9ad9-33e44e6cee0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078315001 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.4078315001
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2642306026
Short name T80
Test name
Test status
Simulation time 424181723515 ps
CPU time 900.57 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 06:01:13 PM PDT 24
Peak memory 208844 kb
Host smart-feaf867c-61b4-47f9-b1d5-3d9221e61a13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642306026 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2642306026
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2786546194
Short name T86
Test name
Test status
Simulation time 245809018636 ps
CPU time 483.71 seconds
Started Jul 20 05:46:29 PM PDT 24
Finished Jul 20 05:54:35 PM PDT 24
Peak memory 203228 kb
Host smart-5e28d58e-bf13-4440-ab99-64d6b6bee396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786546194 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2786546194
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1140120853
Short name T98
Test name
Test status
Simulation time 469158024825 ps
CPU time 1273.77 seconds
Started Jul 20 05:46:19 PM PDT 24
Finished Jul 20 06:07:33 PM PDT 24
Peak memory 214252 kb
Host smart-d0d92522-33a1-4778-855b-28b84bbe1954
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140120853 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1140120853
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2141752013
Short name T96
Test name
Test status
Simulation time 26730839650 ps
CPU time 201.49 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:49:28 PM PDT 24
Peak memory 206392 kb
Host smart-e1798200-6023-4c90-9c9f-0fe5ee3ec0fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141752013 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2141752013
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.4082142524
Short name T36
Test name
Test status
Simulation time 20209473014 ps
CPU time 168.69 seconds
Started Jul 20 05:46:06 PM PDT 24
Finished Jul 20 05:49:02 PM PDT 24
Peak memory 198128 kb
Host smart-3cb6745d-c1a2-475f-917c-a92644911b5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082142524 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.4082142524
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.4165353544
Short name T1
Test name
Test status
Simulation time 626643150093 ps
CPU time 436.27 seconds
Started Jul 20 05:46:28 PM PDT 24
Finished Jul 20 05:53:47 PM PDT 24
Peak memory 206616 kb
Host smart-6627957b-95e4-4b9f-b772-303e27b89887
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165353544 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.4165353544
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4291122727
Short name T16
Test name
Test status
Simulation time 4450034351 ps
CPU time 6.69 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:58 PM PDT 24
Peak memory 215528 kb
Host smart-4929d21a-5a9f-417c-9d74-361a0662d988
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291122727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4291122727
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.245189518
Short name T97
Test name
Test status
Simulation time 89887621721 ps
CPU time 968.99 seconds
Started Jul 20 05:46:18 PM PDT 24
Finished Jul 20 06:02:28 PM PDT 24
Peak memory 209868 kb
Host smart-fa86ace6-ce3f-4758-a492-6fe72d5de65e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245189518 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.245189518
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3839439654
Short name T105
Test name
Test status
Simulation time 163989270764 ps
CPU time 340.63 seconds
Started Jul 20 05:46:31 PM PDT 24
Finished Jul 20 05:52:13 PM PDT 24
Peak memory 201780 kb
Host smart-d7b0d1e0-483e-4840-9f4c-f94e8493224a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839439654 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3839439654
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.552394992
Short name T4
Test name
Test status
Simulation time 68609143700 ps
CPU time 276.55 seconds
Started Jul 20 05:46:27 PM PDT 24
Finished Jul 20 05:51:05 PM PDT 24
Peak memory 199564 kb
Host smart-464e4557-a8df-41ed-8af3-3d5b2c5bf5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552394992 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.552394992
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1572646318
Short name T11
Test name
Test status
Simulation time 38382503293 ps
CPU time 297.07 seconds
Started Jul 20 05:46:37 PM PDT 24
Finished Jul 20 05:51:36 PM PDT 24
Peak memory 206428 kb
Host smart-e7b24f87-7442-4d21-ac34-ffc6fd6f17f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572646318 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1572646318
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.284598637
Short name T91
Test name
Test status
Simulation time 112443779176 ps
CPU time 219.59 seconds
Started Jul 20 05:46:05 PM PDT 24
Finished Jul 20 05:49:52 PM PDT 24
Peak memory 208256 kb
Host smart-02d63cf2-d1c8-449d-95b4-97a9c18153c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284598637 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.284598637
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2933774783
Short name T85
Test name
Test status
Simulation time 263967145684 ps
CPU time 1049.07 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 06:03:37 PM PDT 24
Peak memory 211288 kb
Host smart-2fd97109-d310-4e07-89c8-17263de2149e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933774783 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2933774783
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.782674084
Short name T35
Test name
Test status
Simulation time 87080746942 ps
CPU time 295.2 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:51:03 PM PDT 24
Peak memory 207952 kb
Host smart-c191fd09-a815-48c4-9200-66515dddbca4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782674084 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.782674084
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2096061111
Short name T90
Test name
Test status
Simulation time 398708256483 ps
CPU time 612.05 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:56:13 PM PDT 24
Peak memory 213048 kb
Host smart-fb1cb57f-a8c4-48d8-91d9-aa0b8ca74077
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096061111 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2096061111
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.523453872
Short name T99
Test name
Test status
Simulation time 122157077853 ps
CPU time 30.04 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:46:23 PM PDT 24
Peak memory 192672 kb
Host smart-4944421b-3cee-48af-8426-94e76db5f4d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523453872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.523453872
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2747275994
Short name T116
Test name
Test status
Simulation time 43886746619 ps
CPU time 174.83 seconds
Started Jul 20 05:46:26 PM PDT 24
Finished Jul 20 05:49:23 PM PDT 24
Peak memory 213576 kb
Host smart-22c52abb-beaf-473a-8095-6c3e3585ab7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747275994 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2747275994
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4039578717
Short name T112
Test name
Test status
Simulation time 160213759513 ps
CPU time 56.06 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:47:03 PM PDT 24
Peak memory 197912 kb
Host smart-06a3e724-9035-4143-84fc-ade3cd71cb4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039578717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4039578717
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3687047701
Short name T102
Test name
Test status
Simulation time 189157061242 ps
CPU time 190.09 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:49:16 PM PDT 24
Peak memory 208004 kb
Host smart-fcf89dc8-7ca1-489c-8cf1-ddbf89540cf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687047701 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3687047701
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.589516359
Short name T101
Test name
Test status
Simulation time 81700303194 ps
CPU time 15.92 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:26 PM PDT 24
Peak memory 197796 kb
Host smart-37599187-8382-42d0-bdf8-f95bb57a0c00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589516359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.589516359
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.957620597
Short name T115
Test name
Test status
Simulation time 17424832044 ps
CPU time 123.5 seconds
Started Jul 20 05:46:19 PM PDT 24
Finished Jul 20 05:48:23 PM PDT 24
Peak memory 213544 kb
Host smart-88d957ed-6548-4bd6-b3d6-57f3f9197cfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957620597 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.957620597
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2399742376
Short name T120
Test name
Test status
Simulation time 86230355986 ps
CPU time 128.31 seconds
Started Jul 20 05:46:11 PM PDT 24
Finished Jul 20 05:48:23 PM PDT 24
Peak memory 192620 kb
Host smart-7210bb9b-8d86-4b9a-ba45-ac4d19e25be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399742376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2399742376
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2992100420
Short name T135
Test name
Test status
Simulation time 156630928876 ps
CPU time 151.94 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:48:42 PM PDT 24
Peak memory 197900 kb
Host smart-1541444f-d850-4ea1-a62e-f01fb840f9a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992100420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2992100420
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2503172601
Short name T94
Test name
Test status
Simulation time 117643452531 ps
CPU time 180.18 seconds
Started Jul 20 05:46:31 PM PDT 24
Finished Jul 20 05:49:33 PM PDT 24
Peak memory 192660 kb
Host smart-ee8faace-a3d6-497f-86de-064f5bb3b9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503172601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2503172601
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2352937269
Short name T157
Test name
Test status
Simulation time 24447658768 ps
CPU time 247.73 seconds
Started Jul 20 05:46:08 PM PDT 24
Finished Jul 20 05:50:21 PM PDT 24
Peak memory 206516 kb
Host smart-dec3165f-7937-479e-b6e6-b5d67cf0eda9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352937269 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2352937269
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3541358358
Short name T57
Test name
Test status
Simulation time 474861405 ps
CPU time 1.3 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 194420 kb
Host smart-f5693d0f-c50a-4e03-afb5-1bbe475b5082
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541358358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3541358358
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3180779017
Short name T82
Test name
Test status
Simulation time 350313575402 ps
CPU time 323.58 seconds
Started Jul 20 05:46:16 PM PDT 24
Finished Jul 20 05:51:41 PM PDT 24
Peak memory 201840 kb
Host smart-d9d689c9-3564-43c6-afb2-ab90d8c43faf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180779017 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3180779017
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3578849524
Short name T83
Test name
Test status
Simulation time 198988378126 ps
CPU time 826.78 seconds
Started Jul 20 05:46:20 PM PDT 24
Finished Jul 20 06:00:07 PM PDT 24
Peak memory 214652 kb
Host smart-36713448-5450-49fa-9f2f-57b18445717b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578849524 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3578849524
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1302579970
Short name T109
Test name
Test status
Simulation time 148182574773 ps
CPU time 818.17 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:59:29 PM PDT 24
Peak memory 207824 kb
Host smart-a6597f69-ea04-4e88-9ae0-70054a645ad2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302579970 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1302579970
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.691579867
Short name T111
Test name
Test status
Simulation time 148558689475 ps
CPU time 42.16 seconds
Started Jul 20 05:45:52 PM PDT 24
Finished Jul 20 05:46:38 PM PDT 24
Peak memory 197860 kb
Host smart-8585b57a-8361-4fb4-abcc-78a4f7feff65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691579867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.691579867
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.602809664
Short name T123
Test name
Test status
Simulation time 203775149447 ps
CPU time 25.78 seconds
Started Jul 20 05:46:29 PM PDT 24
Finished Jul 20 05:46:58 PM PDT 24
Peak memory 197936 kb
Host smart-08eee3a6-bc4b-453f-b404-ddec8631b243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602809664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.602809664
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3481289036
Short name T150
Test name
Test status
Simulation time 65233329654 ps
CPU time 667.5 seconds
Started Jul 20 05:46:30 PM PDT 24
Finished Jul 20 05:57:40 PM PDT 24
Peak memory 206468 kb
Host smart-a11cfceb-5ee5-4a77-9f64-0fe4de5c1af6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481289036 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3481289036
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2368117753
Short name T28
Test name
Test status
Simulation time 455864073967 ps
CPU time 648.88 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:56:55 PM PDT 24
Peak memory 213416 kb
Host smart-5a9197f0-633b-4078-96fc-d5b109e0e284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368117753 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2368117753
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3151741551
Short name T110
Test name
Test status
Simulation time 163546537045 ps
CPU time 25.94 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:35 PM PDT 24
Peak memory 183784 kb
Host smart-42bdcd54-7ca6-44fd-9c45-7c8b2419ecee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151741551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3151741551
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3985833886
Short name T87
Test name
Test status
Simulation time 150479716102 ps
CPU time 449.97 seconds
Started Jul 20 05:46:35 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 210156 kb
Host smart-a01e21cc-bd74-40e3-bca0-2c91a11f9f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985833886 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3985833886
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1742082873
Short name T118
Test name
Test status
Simulation time 81734777654 ps
CPU time 25.74 seconds
Started Jul 20 05:46:16 PM PDT 24
Finished Jul 20 05:46:43 PM PDT 24
Peak memory 183832 kb
Host smart-13c25e94-7f46-4579-b64f-f21faef2517c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742082873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1742082873
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2191980375
Short name T117
Test name
Test status
Simulation time 200827426388 ps
CPU time 72.87 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:47:08 PM PDT 24
Peak memory 198060 kb
Host smart-ff5434c3-d85c-4e36-8507-78bdd83409e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191980375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2191980375
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3641443178
Short name T92
Test name
Test status
Simulation time 159508882467 ps
CPU time 334.3 seconds
Started Jul 20 05:46:20 PM PDT 24
Finished Jul 20 05:51:55 PM PDT 24
Peak memory 209608 kb
Host smart-c68a5ad1-dccc-4332-9672-b78f02b00edc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641443178 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3641443178
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.779665109
Short name T138
Test name
Test status
Simulation time 331385131766 ps
CPU time 242 seconds
Started Jul 20 05:46:26 PM PDT 24
Finished Jul 20 05:50:29 PM PDT 24
Peak memory 192604 kb
Host smart-762653fb-b930-4439-8ebb-00ca6a7d0939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779665109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.779665109
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.153842382
Short name T131
Test name
Test status
Simulation time 115738577670 ps
CPU time 153.9 seconds
Started Jul 20 05:46:29 PM PDT 24
Finished Jul 20 05:49:06 PM PDT 24
Peak memory 197912 kb
Host smart-1932820d-619a-4547-a65d-8af696a1734b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153842382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.153842382
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3162299653
Short name T103
Test name
Test status
Simulation time 228154460922 ps
CPU time 167.8 seconds
Started Jul 20 05:46:11 PM PDT 24
Finished Jul 20 05:49:03 PM PDT 24
Peak memory 191704 kb
Host smart-c9ca2c26-910f-45a7-ae20-5c10a8e25bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162299653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3162299653
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1278771503
Short name T146
Test name
Test status
Simulation time 5858526367 ps
CPU time 49.15 seconds
Started Jul 20 05:46:17 PM PDT 24
Finished Jul 20 05:47:07 PM PDT 24
Peak memory 198200 kb
Host smart-02ac61e3-c08b-4317-8366-cd7b63b2c021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278771503 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1278771503
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.427347690
Short name T139
Test name
Test status
Simulation time 169795364597 ps
CPU time 268.14 seconds
Started Jul 20 05:46:41 PM PDT 24
Finished Jul 20 05:51:10 PM PDT 24
Peak memory 197924 kb
Host smart-1dd3132a-06f1-494b-b577-f1ac3610d074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427347690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.427347690
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1739502049
Short name T126
Test name
Test status
Simulation time 465448176622 ps
CPU time 626.85 seconds
Started Jul 20 05:46:28 PM PDT 24
Finished Jul 20 05:56:57 PM PDT 24
Peak memory 192648 kb
Host smart-f0498d89-001e-46dc-9645-84f7ac5f0a79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739502049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1739502049
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.369195300
Short name T134
Test name
Test status
Simulation time 307010823218 ps
CPU time 121.67 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:48:11 PM PDT 24
Peak memory 198068 kb
Host smart-82d2545f-42ec-467d-8556-f0821197933a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369195300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.369195300
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.188610215
Short name T77
Test name
Test status
Simulation time 1351686620 ps
CPU time 2.63 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:45 PM PDT 24
Peak memory 194536 kb
Host smart-5cff1216-da42-48f2-b3d3-1e544f3bbc65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188610215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.188610215
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.218833301
Short name T127
Test name
Test status
Simulation time 265487459873 ps
CPU time 81.53 seconds
Started Jul 20 05:46:13 PM PDT 24
Finished Jul 20 05:47:38 PM PDT 24
Peak memory 191528 kb
Host smart-c3b15170-3925-4183-b47c-7a6360690db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218833301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.218833301
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3247863870
Short name T143
Test name
Test status
Simulation time 137744886027 ps
CPU time 97.93 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:47:48 PM PDT 24
Peak memory 191564 kb
Host smart-5ff24cb3-4eea-435d-b881-df6de9fca10e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247863870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3247863870
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1213555459
Short name T93
Test name
Test status
Simulation time 67652697597 ps
CPU time 278.2 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:50:46 PM PDT 24
Peak memory 207708 kb
Host smart-c549569a-6772-4770-8d70-22e9919684dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213555459 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1213555459
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4028783915
Short name T159
Test name
Test status
Simulation time 77135009311 ps
CPU time 221.62 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:49:41 PM PDT 24
Peak memory 207960 kb
Host smart-23eb4443-3c6e-46bf-a3f3-b0f27274ca7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028783915 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4028783915
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1959881547
Short name T154
Test name
Test status
Simulation time 4836292692 ps
CPU time 7.21 seconds
Started Jul 20 05:46:22 PM PDT 24
Finished Jul 20 05:46:30 PM PDT 24
Peak memory 192664 kb
Host smart-80409223-cb4f-419f-b83b-2957cdeeb0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959881547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1959881547
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2329848209
Short name T49
Test name
Test status
Simulation time 431075569337 ps
CPU time 475.03 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 192656 kb
Host smart-58fb4850-c4a6-4b7c-85f0-1e2a75e21a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329848209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2329848209
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2917134770
Short name T142
Test name
Test status
Simulation time 268349313806 ps
CPU time 102.13 seconds
Started Jul 20 05:46:34 PM PDT 24
Finished Jul 20 05:48:18 PM PDT 24
Peak memory 191516 kb
Host smart-0ba24e85-4769-4fb5-99ae-f02e280b0738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917134770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2917134770
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3639870730
Short name T26
Test name
Test status
Simulation time 19887524063 ps
CPU time 52.13 seconds
Started Jul 20 05:46:27 PM PDT 24
Finished Jul 20 05:47:21 PM PDT 24
Peak memory 206384 kb
Host smart-b8e373f0-5441-417d-9a3d-3c31cb0ab971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639870730 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3639870730
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.390354672
Short name T3
Test name
Test status
Simulation time 215007088393 ps
CPU time 27.44 seconds
Started Jul 20 05:46:08 PM PDT 24
Finished Jul 20 05:46:41 PM PDT 24
Peak memory 192596 kb
Host smart-50093470-6292-4d7e-9c75-de8e2ef6df50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390354672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.390354672
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2964540672
Short name T20
Test name
Test status
Simulation time 38667035437 ps
CPU time 54.22 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:46:55 PM PDT 24
Peak memory 197880 kb
Host smart-0a98b6b9-74db-4a64-97a1-5353680d4ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964540672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2964540672
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2875587279
Short name T18
Test name
Test status
Simulation time 11282750349 ps
CPU time 8.1 seconds
Started Jul 20 05:46:17 PM PDT 24
Finished Jul 20 05:46:26 PM PDT 24
Peak memory 191564 kb
Host smart-1f593ed2-f492-4b0c-a693-875389bcaee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875587279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2875587279
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1088541988
Short name T84
Test name
Test status
Simulation time 17733979928 ps
CPU time 176.67 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:49:07 PM PDT 24
Peak memory 206428 kb
Host smart-19da694a-f4d3-4869-980c-781815b19b51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088541988 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1088541988
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.21315082
Short name T137
Test name
Test status
Simulation time 274764659505 ps
CPU time 83.7 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:47:16 PM PDT 24
Peak memory 197928 kb
Host smart-30ebb850-6e65-43be-8d7a-33be8bcd2753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21315082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all
.21315082
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2468342532
Short name T100
Test name
Test status
Simulation time 551315898 ps
CPU time 0.64 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:46:12 PM PDT 24
Peak memory 196340 kb
Host smart-d78e7c66-5b4f-438d-b095-b65ea568c01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468342532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2468342532
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3136501993
Short name T160
Test name
Test status
Simulation time 109106288723 ps
CPU time 212.16 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:49:43 PM PDT 24
Peak memory 208416 kb
Host smart-ec951cf0-dde9-49fd-b3e4-cb555d0a997f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136501993 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3136501993
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2475944089
Short name T151
Test name
Test status
Simulation time 258758116892 ps
CPU time 59.14 seconds
Started Jul 20 05:46:18 PM PDT 24
Finished Jul 20 05:47:18 PM PDT 24
Peak memory 184360 kb
Host smart-77e03a64-dcef-4547-b492-23f82971d54c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475944089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2475944089
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4145494703
Short name T114
Test name
Test status
Simulation time 571187620 ps
CPU time 1.47 seconds
Started Jul 20 05:46:29 PM PDT 24
Finished Jul 20 05:46:33 PM PDT 24
Peak memory 196392 kb
Host smart-ac9b9e74-9cd2-48e7-a702-e16d5e2a1889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145494703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4145494703
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.451210477
Short name T108
Test name
Test status
Simulation time 439069317 ps
CPU time 0.94 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 196244 kb
Host smart-e920ac3c-5e8e-4e73-af6e-003fc2b96940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451210477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.451210477
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2688404839
Short name T169
Test name
Test status
Simulation time 234539852229 ps
CPU time 344.81 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:51:55 PM PDT 24
Peak memory 213876 kb
Host smart-c6541ccb-3a0d-4188-9a01-17fd07f5d8e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688404839 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2688404839
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4050417778
Short name T136
Test name
Test status
Simulation time 465922886 ps
CPU time 0.77 seconds
Started Jul 20 05:45:56 PM PDT 24
Finished Jul 20 05:46:00 PM PDT 24
Peak memory 196380 kb
Host smart-a0a3c21b-5a00-4a16-a512-3475c4c239a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050417778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4050417778
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1138507294
Short name T119
Test name
Test status
Simulation time 371157724 ps
CPU time 0.73 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:07 PM PDT 24
Peak memory 196304 kb
Host smart-fb56772d-8075-4d7f-a5ca-0da33664a3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138507294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1138507294
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1168929162
Short name T153
Test name
Test status
Simulation time 386927640 ps
CPU time 1.23 seconds
Started Jul 20 05:46:09 PM PDT 24
Finished Jul 20 05:46:16 PM PDT 24
Peak memory 196324 kb
Host smart-28c1e3e9-a8ec-41f5-9941-b3e133055b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168929162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1168929162
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2929922385
Short name T27
Test name
Test status
Simulation time 47637881044 ps
CPU time 400.28 seconds
Started Jul 20 05:45:57 PM PDT 24
Finished Jul 20 05:52:40 PM PDT 24
Peak memory 206540 kb
Host smart-6f051663-bf97-4076-820a-d1e25248d898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929922385 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2929922385
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.883827873
Short name T167
Test name
Test status
Simulation time 25989044688 ps
CPU time 197.41 seconds
Started Jul 20 05:46:12 PM PDT 24
Finished Jul 20 05:49:33 PM PDT 24
Peak memory 198240 kb
Host smart-fc5e1119-0c56-4311-9743-4c0049d050e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883827873 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.883827873
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.621000424
Short name T130
Test name
Test status
Simulation time 504554941 ps
CPU time 1.31 seconds
Started Jul 20 05:46:09 PM PDT 24
Finished Jul 20 05:46:16 PM PDT 24
Peak memory 196400 kb
Host smart-f42521b7-1cb1-4ac3-bf28-d61207c7c6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621000424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.621000424
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2568774902
Short name T121
Test name
Test status
Simulation time 156603999855 ps
CPU time 123.3 seconds
Started Jul 20 05:45:52 PM PDT 24
Finished Jul 20 05:48:00 PM PDT 24
Peak memory 192644 kb
Host smart-305ddcad-bccd-4f85-b78c-960505ca221f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568774902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2568774902
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1592600361
Short name T147
Test name
Test status
Simulation time 535483053 ps
CPU time 1.45 seconds
Started Jul 20 05:46:18 PM PDT 24
Finished Jul 20 05:46:20 PM PDT 24
Peak memory 196364 kb
Host smart-5ef0ead9-3bd3-4e8a-b7ad-5020fc5509e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592600361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1592600361
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1057227165
Short name T21
Test name
Test status
Simulation time 376957408 ps
CPU time 0.73 seconds
Started Jul 20 05:46:06 PM PDT 24
Finished Jul 20 05:46:14 PM PDT 24
Peak memory 196392 kb
Host smart-a50df5d1-f361-4340-9d85-bbcd52f70d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057227165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1057227165
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1757746204
Short name T155
Test name
Test status
Simulation time 232433186181 ps
CPU time 41.9 seconds
Started Jul 20 05:46:34 PM PDT 24
Finished Jul 20 05:47:17 PM PDT 24
Peak memory 193204 kb
Host smart-b342aff6-b091-4264-a325-e85611805778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757746204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1757746204
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3502741239
Short name T149
Test name
Test status
Simulation time 512390422 ps
CPU time 1 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:46:01 PM PDT 24
Peak memory 196340 kb
Host smart-fd738863-0a13-47ba-9bc2-fb27e251d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502741239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3502741239
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3045022196
Short name T122
Test name
Test status
Simulation time 101659635979 ps
CPU time 105.41 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:47:55 PM PDT 24
Peak memory 197896 kb
Host smart-734f65e7-455e-48cc-9580-a1655f963e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045022196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3045022196
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3058582515
Short name T128
Test name
Test status
Simulation time 481458169 ps
CPU time 1.34 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 196388 kb
Host smart-74ad7011-6886-4626-8e6c-b6817f44596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058582515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3058582515
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.29966217
Short name T113
Test name
Test status
Simulation time 421464855 ps
CPU time 0.7 seconds
Started Jul 20 05:46:18 PM PDT 24
Finished Jul 20 05:46:20 PM PDT 24
Peak memory 196288 kb
Host smart-eb96b3b3-2c3b-4493-9014-80a6e68aa528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29966217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.29966217
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3740467675
Short name T133
Test name
Test status
Simulation time 591506564 ps
CPU time 1.06 seconds
Started Jul 20 05:46:32 PM PDT 24
Finished Jul 20 05:46:35 PM PDT 24
Peak memory 196420 kb
Host smart-74ca03c6-b845-4dbd-8c1d-80de7c15755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740467675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3740467675
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2649846460
Short name T104
Test name
Test status
Simulation time 69376991121 ps
CPU time 746.75 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:58:28 PM PDT 24
Peak memory 206220 kb
Host smart-3e769bf6-3d0c-4534-908b-177cfd144cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649846460 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2649846460
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1455739776
Short name T144
Test name
Test status
Simulation time 398159021 ps
CPU time 0.88 seconds
Started Jul 20 05:46:20 PM PDT 24
Finished Jul 20 05:46:22 PM PDT 24
Peak memory 196372 kb
Host smart-58ad51fd-106a-4149-91cf-393a7377920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455739776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1455739776
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3860218956
Short name T129
Test name
Test status
Simulation time 104542379966 ps
CPU time 71.26 seconds
Started Jul 20 05:46:13 PM PDT 24
Finished Jul 20 05:47:28 PM PDT 24
Peak memory 197896 kb
Host smart-5c8a3a2d-8cd6-4f03-976d-c87b9fda8754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860218956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3860218956
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2331286092
Short name T145
Test name
Test status
Simulation time 62987689447 ps
CPU time 16.82 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:21 PM PDT 24
Peak memory 191552 kb
Host smart-7bd34975-70e5-447b-96ae-cb9a53361727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331286092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2331286092
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.263345664
Short name T162
Test name
Test status
Simulation time 110207470755 ps
CPU time 116.36 seconds
Started Jul 20 05:46:28 PM PDT 24
Finished Jul 20 05:48:27 PM PDT 24
Peak memory 192588 kb
Host smart-3eb36136-3202-4870-a425-82941d96948f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263345664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.263345664
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3231990465
Short name T124
Test name
Test status
Simulation time 203288289240 ps
CPU time 228.05 seconds
Started Jul 20 05:46:38 PM PDT 24
Finished Jul 20 05:50:27 PM PDT 24
Peak memory 191532 kb
Host smart-58e1a72c-0afb-4092-98a5-76bd48b4d95b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231990465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3231990465
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3107481643
Short name T140
Test name
Test status
Simulation time 10804689190 ps
CPU time 105.82 seconds
Started Jul 20 05:46:33 PM PDT 24
Finished Jul 20 05:48:21 PM PDT 24
Peak memory 214560 kb
Host smart-1cbd684e-2265-4666-b9eb-49e3233ecc3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107481643 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3107481643
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2534915993
Short name T178
Test name
Test status
Simulation time 84463012380 ps
CPU time 29.27 seconds
Started Jul 20 05:45:59 PM PDT 24
Finished Jul 20 05:46:31 PM PDT 24
Peak memory 197912 kb
Host smart-94a7f1de-c910-4c5e-90d3-2911a8297264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534915993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2534915993
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2490176311
Short name T174
Test name
Test status
Simulation time 40400398417 ps
CPU time 14.34 seconds
Started Jul 20 05:45:51 PM PDT 24
Finished Jul 20 05:46:10 PM PDT 24
Peak memory 191568 kb
Host smart-be7abfd4-de23-4056-9603-4bd4448ffb94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490176311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2490176311
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1318438442
Short name T42
Test name
Test status
Simulation time 520715631 ps
CPU time 0.78 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 196356 kb
Host smart-9e4f6944-275f-45f4-9ab6-7521298d259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318438442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1318438442
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.904448529
Short name T132
Test name
Test status
Simulation time 486674848 ps
CPU time 1.25 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:07 PM PDT 24
Peak memory 196232 kb
Host smart-d99aff84-90c4-49df-af51-efea4681bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904448529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.904448529
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3258308674
Short name T106
Test name
Test status
Simulation time 357306707 ps
CPU time 1.14 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:07 PM PDT 24
Peak memory 196344 kb
Host smart-71f28bc6-9ec8-4792-816b-0a0e378a6b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258308674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3258308674
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3527266467
Short name T163
Test name
Test status
Simulation time 58254414351 ps
CPU time 85.22 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:47:17 PM PDT 24
Peak memory 197864 kb
Host smart-ea48896f-5ccc-422c-8a43-2d8e5c36ba79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527266467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3527266467
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1654441500
Short name T125
Test name
Test status
Simulation time 101835877540 ps
CPU time 43.95 seconds
Started Jul 20 05:46:35 PM PDT 24
Finished Jul 20 05:47:20 PM PDT 24
Peak memory 191564 kb
Host smart-79d37f86-7127-4342-8066-c75fd8a79bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654441500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1654441500
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2152504003
Short name T141
Test name
Test status
Simulation time 405985844 ps
CPU time 1.11 seconds
Started Jul 20 05:46:25 PM PDT 24
Finished Jul 20 05:46:27 PM PDT 24
Peak memory 196316 kb
Host smart-d4a75569-134f-4cc2-965a-9945fa61b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152504003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2152504003
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3791188364
Short name T170
Test name
Test status
Simulation time 428375617 ps
CPU time 0.74 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:08 PM PDT 24
Peak memory 196272 kb
Host smart-8237dee9-163a-4d8a-a05b-343298d1606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791188364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3791188364
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3348120922
Short name T5
Test name
Test status
Simulation time 236106862805 ps
CPU time 93.91 seconds
Started Jul 20 05:46:14 PM PDT 24
Finished Jul 20 05:47:50 PM PDT 24
Peak memory 197916 kb
Host smart-7e073b6c-2551-4b72-9c84-10f9001f84bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348120922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3348120922
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.616257794
Short name T180
Test name
Test status
Simulation time 393950098 ps
CPU time 0.88 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:10 PM PDT 24
Peak memory 196276 kb
Host smart-191108a0-59d3-4057-87a0-b78e1949d08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616257794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.616257794
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3089239532
Short name T185
Test name
Test status
Simulation time 554128535 ps
CPU time 1.46 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 196268 kb
Host smart-1766e699-58e7-4030-8278-7b661167351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089239532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3089239532
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3596117423
Short name T164
Test name
Test status
Simulation time 290154653251 ps
CPU time 267 seconds
Started Jul 20 05:46:13 PM PDT 24
Finished Jul 20 05:50:43 PM PDT 24
Peak memory 192656 kb
Host smart-aea9bb29-a695-4255-9677-bf73a3e5dcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596117423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3596117423
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.548223642
Short name T194
Test name
Test status
Simulation time 368573357 ps
CPU time 0.73 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:46:13 PM PDT 24
Peak memory 196284 kb
Host smart-022d60e2-14f2-43ba-9955-6c85194086ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548223642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.548223642
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3764535619
Short name T177
Test name
Test status
Simulation time 566679514 ps
CPU time 0.79 seconds
Started Jul 20 05:46:32 PM PDT 24
Finished Jul 20 05:46:35 PM PDT 24
Peak memory 196372 kb
Host smart-37c641e2-5105-4312-a95a-707bff46a900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764535619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3764535619
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3074371598
Short name T10
Test name
Test status
Simulation time 573139303 ps
CPU time 0.79 seconds
Started Jul 20 05:45:55 PM PDT 24
Finished Jul 20 05:45:58 PM PDT 24
Peak memory 196260 kb
Host smart-75c71b94-b5fa-4454-a2ea-b4e133a57872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074371598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3074371598
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1000973838
Short name T196
Test name
Test status
Simulation time 8594710295 ps
CPU time 6.95 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 198760 kb
Host smart-78b25c19-93ab-4930-abf0-b523ee944fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000973838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1000973838
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1139661166
Short name T182
Test name
Test status
Simulation time 511244885 ps
CPU time 1.03 seconds
Started Jul 20 05:45:51 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 196272 kb
Host smart-39101546-acc5-4ac6-b7ba-57aa71261335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139661166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1139661166
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1839681513
Short name T107
Test name
Test status
Simulation time 575866854 ps
CPU time 0.89 seconds
Started Jul 20 05:45:53 PM PDT 24
Finished Jul 20 05:45:58 PM PDT 24
Peak memory 196424 kb
Host smart-9cf3ee21-ee74-4418-99c9-2b6a63efed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839681513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1839681513
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2209084259
Short name T38
Test name
Test status
Simulation time 546917369 ps
CPU time 0.85 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 196212 kb
Host smart-96d539e9-66c1-40c4-8e3b-167786bbe423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209084259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2209084259
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1371299638
Short name T176
Test name
Test status
Simulation time 427719063 ps
CPU time 0.65 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 196256 kb
Host smart-123432ad-c2d2-4fa2-a1df-3f0cb9ab2e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371299638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1371299638
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2274414814
Short name T193
Test name
Test status
Simulation time 412781534 ps
CPU time 1.21 seconds
Started Jul 20 05:46:06 PM PDT 24
Finished Jul 20 05:46:14 PM PDT 24
Peak memory 196200 kb
Host smart-ba87191b-6fe8-4e6c-a359-9156348c8fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274414814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2274414814
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2652458806
Short name T19
Test name
Test status
Simulation time 150038657110 ps
CPU time 13.11 seconds
Started Jul 20 05:46:11 PM PDT 24
Finished Jul 20 05:46:29 PM PDT 24
Peak memory 197908 kb
Host smart-0b2d35c0-cbf2-4b07-97c0-92abff8f1e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652458806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2652458806
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2648477515
Short name T190
Test name
Test status
Simulation time 14747308704 ps
CPU time 148.83 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:48:41 PM PDT 24
Peak memory 198188 kb
Host smart-252a045a-ea21-4783-935c-8ba3e3f234b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648477515 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2648477515
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3469722656
Short name T165
Test name
Test status
Simulation time 410307400 ps
CPU time 0.75 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 196292 kb
Host smart-52a31cfd-85ec-4cb2-a918-5d2e152b2516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469722656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3469722656
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3487882821
Short name T158
Test name
Test status
Simulation time 72968033702 ps
CPU time 214.84 seconds
Started Jul 20 05:46:06 PM PDT 24
Finished Jul 20 05:49:48 PM PDT 24
Peak memory 206444 kb
Host smart-df936a57-d078-4086-aec5-5b03fd036352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487882821 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3487882821
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3016079374
Short name T45
Test name
Test status
Simulation time 395427491 ps
CPU time 1.35 seconds
Started Jul 20 05:46:35 PM PDT 24
Finished Jul 20 05:46:38 PM PDT 24
Peak memory 196304 kb
Host smart-fd4809d6-3c3b-4646-a62b-5cef2e6fe47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016079374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3016079374
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.661634171
Short name T172
Test name
Test status
Simulation time 541072708 ps
CPU time 0.8 seconds
Started Jul 20 05:46:23 PM PDT 24
Finished Jul 20 05:46:25 PM PDT 24
Peak memory 196276 kb
Host smart-29200d37-d6ac-4d5f-b0c7-7f1b0e300f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661634171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.661634171
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1014841693
Short name T186
Test name
Test status
Simulation time 430021159 ps
CPU time 1.26 seconds
Started Jul 20 05:46:28 PM PDT 24
Finished Jul 20 05:46:32 PM PDT 24
Peak memory 196256 kb
Host smart-731fe5af-43de-417e-8b08-73ac86f78dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014841693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1014841693
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.279027195
Short name T39
Test name
Test status
Simulation time 558361079 ps
CPU time 0.74 seconds
Started Jul 20 05:46:35 PM PDT 24
Finished Jul 20 05:46:38 PM PDT 24
Peak memory 196216 kb
Host smart-3cdf69e2-e3cf-46e9-aa18-ce02f65557b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279027195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.279027195
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.347002189
Short name T191
Test name
Test status
Simulation time 538846691 ps
CPU time 0.96 seconds
Started Jul 20 05:46:35 PM PDT 24
Finished Jul 20 05:46:37 PM PDT 24
Peak memory 196368 kb
Host smart-b8bf88ba-0b52-44e4-ba1a-f32bc654fdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347002189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.347002189
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3672046086
Short name T51
Test name
Test status
Simulation time 520154877 ps
CPU time 0.98 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:07 PM PDT 24
Peak memory 196320 kb
Host smart-c86e43af-004f-46f7-a9bc-96f2d8cfe3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672046086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3672046086
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1386014662
Short name T161
Test name
Test status
Simulation time 349627419 ps
CPU time 1.09 seconds
Started Jul 20 05:45:53 PM PDT 24
Finished Jul 20 05:45:58 PM PDT 24
Peak memory 196232 kb
Host smart-59db7ecd-d769-4634-8c0c-7792287979ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386014662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1386014662
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3970602200
Short name T179
Test name
Test status
Simulation time 432620531 ps
CPU time 0.87 seconds
Started Jul 20 05:46:11 PM PDT 24
Finished Jul 20 05:46:16 PM PDT 24
Peak memory 196396 kb
Host smart-6a3604d7-a3d3-4b28-a30a-166b68d13566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970602200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3970602200
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2712682914
Short name T188
Test name
Test status
Simulation time 602782358 ps
CPU time 1.05 seconds
Started Jul 20 05:46:16 PM PDT 24
Finished Jul 20 05:46:18 PM PDT 24
Peak memory 196396 kb
Host smart-334200b3-6eb1-438e-9e5b-c048a4dbe789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712682914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2712682914
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3476421247
Short name T184
Test name
Test status
Simulation time 535825011 ps
CPU time 0.93 seconds
Started Jul 20 05:46:18 PM PDT 24
Finished Jul 20 05:46:20 PM PDT 24
Peak memory 196292 kb
Host smart-5e860de2-2b60-4e4d-9b0d-a66ba8b4b62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476421247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3476421247
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1088956903
Short name T187
Test name
Test status
Simulation time 416206094 ps
CPU time 0.68 seconds
Started Jul 20 05:45:47 PM PDT 24
Finished Jul 20 05:45:51 PM PDT 24
Peak memory 196436 kb
Host smart-2e997548-573a-4f29-9a93-f6d39a515baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088956903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1088956903
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1366933914
Short name T17
Test name
Test status
Simulation time 92858712978 ps
CPU time 31.54 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:40 PM PDT 24
Peak memory 197904 kb
Host smart-d1d7517e-2bff-4604-bcfa-ea27a000783a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366933914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1366933914
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3995904022
Short name T183
Test name
Test status
Simulation time 507799383 ps
CPU time 0.75 seconds
Started Jul 20 05:46:06 PM PDT 24
Finished Jul 20 05:46:14 PM PDT 24
Peak memory 196036 kb
Host smart-7a4404a9-1f6d-42a6-9932-7146e0438a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995904022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3995904022
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3480556013
Short name T152
Test name
Test status
Simulation time 358389283 ps
CPU time 0.75 seconds
Started Jul 20 05:46:29 PM PDT 24
Finished Jul 20 05:46:33 PM PDT 24
Peak memory 196360 kb
Host smart-268c8471-c1d0-41cc-b7ed-20288cb5f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480556013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3480556013
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1876588492
Short name T46
Test name
Test status
Simulation time 469566619 ps
CPU time 1.32 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:12 PM PDT 24
Peak memory 196280 kb
Host smart-17228923-54f9-46de-a23e-1b66e0f4ae11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876588492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1876588492
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.129926041
Short name T171
Test name
Test status
Simulation time 145404286387 ps
CPU time 211.56 seconds
Started Jul 20 05:46:37 PM PDT 24
Finished Jul 20 05:50:10 PM PDT 24
Peak memory 192576 kb
Host smart-9050fbb9-8215-4194-ba7a-63e2a01373ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129926041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.129926041
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.11605146
Short name T175
Test name
Test status
Simulation time 235837741017 ps
CPU time 240.69 seconds
Started Jul 20 05:46:11 PM PDT 24
Finished Jul 20 05:50:16 PM PDT 24
Peak memory 192328 kb
Host smart-42b6f216-9faa-41f9-a9c4-9e7fee86a759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11605146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all
.11605146
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1891621356
Short name T173
Test name
Test status
Simulation time 535181949 ps
CPU time 1.04 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 196076 kb
Host smart-ca8ecda2-ebcb-4d19-9e9b-0370f3331f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891621356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1891621356
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1755191777
Short name T408
Test name
Test status
Simulation time 474543356 ps
CPU time 1.32 seconds
Started Jul 20 05:55:40 PM PDT 24
Finished Jul 20 05:55:45 PM PDT 24
Peak memory 193636 kb
Host smart-a2a3bb7b-3841-4128-821e-4a817b6b1f58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755191777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1755191777
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3907995500
Short name T67
Test name
Test status
Simulation time 13299562693 ps
CPU time 9.02 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:43 PM PDT 24
Peak memory 196924 kb
Host smart-376d0011-c6b4-4d3c-910d-c68e61367d59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907995500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3907995500
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.948227073
Short name T371
Test name
Test status
Simulation time 742922562 ps
CPU time 1.11 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 193404 kb
Host smart-fe4d67a2-0229-4fa6-b4cc-b6cbc224eaa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948227073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.948227073
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1693528648
Short name T373
Test name
Test status
Simulation time 491592807 ps
CPU time 0.84 seconds
Started Jul 20 05:55:34 PM PDT 24
Finished Jul 20 05:55:39 PM PDT 24
Peak memory 196000 kb
Host smart-454c3077-fcda-40db-8dcb-cfc3a0f18974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693528648 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1693528648
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1573316391
Short name T343
Test name
Test status
Simulation time 312845125 ps
CPU time 0.67 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 193420 kb
Host smart-0c4b1aa4-484f-4982-a82c-8e787da91583
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573316391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1573316391
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1008661954
Short name T409
Test name
Test status
Simulation time 508192792 ps
CPU time 0.89 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 184192 kb
Host smart-83cc6c2b-d9eb-49d0-9e5a-f44e7da541c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008661954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1008661954
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.455557291
Short name T311
Test name
Test status
Simulation time 492692064 ps
CPU time 0.69 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:37 PM PDT 24
Peak memory 184132 kb
Host smart-3a0817e4-df30-4c15-acc8-c7f52bff618c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455557291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.455557291
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.323854772
Short name T336
Test name
Test status
Simulation time 315653245 ps
CPU time 0.96 seconds
Started Jul 20 05:55:27 PM PDT 24
Finished Jul 20 05:55:30 PM PDT 24
Peak memory 184104 kb
Host smart-14d0faa7-fb29-4785-a2c3-6261f3b5e0b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323854772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.323854772
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2864976971
Short name T418
Test name
Test status
Simulation time 2628278934 ps
CPU time 1.64 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:36 PM PDT 24
Peak memory 195424 kb
Host smart-1d5e32a2-bdc4-4804-954f-81a657911bb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864976971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2864976971
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.125601681
Short name T389
Test name
Test status
Simulation time 640691783 ps
CPU time 1.51 seconds
Started Jul 20 05:55:28 PM PDT 24
Finished Jul 20 05:55:31 PM PDT 24
Peak memory 198768 kb
Host smart-6d25256a-9aea-4c10-99e0-c2868a1b6903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125601681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.125601681
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2700104666
Short name T322
Test name
Test status
Simulation time 8949968195 ps
CPU time 13.58 seconds
Started Jul 20 05:55:36 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 198396 kb
Host smart-a8369b1b-f959-4830-ae36-1d7b8a313163
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700104666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2700104666
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.216371513
Short name T54
Test name
Test status
Simulation time 7570756191 ps
CPU time 8.3 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:43 PM PDT 24
Peak memory 192580 kb
Host smart-39ea13c1-725a-4052-8ad2-3a62d3da3327
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216371513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.216371513
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1737952623
Short name T417
Test name
Test status
Simulation time 759688364 ps
CPU time 1.52 seconds
Started Jul 20 05:55:40 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 184132 kb
Host smart-c9f1f567-8e0a-4615-a89a-79cfdaad785a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737952623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1737952623
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2397779811
Short name T287
Test name
Test status
Simulation time 420108612 ps
CPU time 1.23 seconds
Started Jul 20 05:55:33 PM PDT 24
Finished Jul 20 05:55:38 PM PDT 24
Peak memory 196108 kb
Host smart-bbde9e84-7036-479d-9c15-e07e22d4e900
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397779811 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2397779811
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2728717631
Short name T69
Test name
Test status
Simulation time 292034428 ps
CPU time 1 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 193908 kb
Host smart-025d347a-105b-4258-a8f5-5bfefd0ad303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728717631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2728717631
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1001454000
Short name T291
Test name
Test status
Simulation time 559696279 ps
CPU time 0.57 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 193404 kb
Host smart-91c8f063-6e3b-45b1-b294-7fb55e0f53c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001454000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1001454000
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3226416266
Short name T344
Test name
Test status
Simulation time 297128392 ps
CPU time 0.94 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:37 PM PDT 24
Peak memory 184084 kb
Host smart-399bb9c2-091e-4ea4-bc83-f3d7b4fefb2c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226416266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3226416266
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2799441305
Short name T378
Test name
Test status
Simulation time 522436525 ps
CPU time 0.58 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 184104 kb
Host smart-1ac50fc6-7c53-4498-a463-13a9dcb0ac7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799441305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2799441305
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3111455658
Short name T405
Test name
Test status
Simulation time 2699918931 ps
CPU time 2.19 seconds
Started Jul 20 05:55:35 PM PDT 24
Finished Jul 20 05:55:40 PM PDT 24
Peak memory 195428 kb
Host smart-e3c165a4-ecd6-4bfb-bec4-e41467bd8bf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111455658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3111455658
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4050014130
Short name T357
Test name
Test status
Simulation time 396111060 ps
CPU time 1.82 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 199024 kb
Host smart-72bc629c-7536-4940-bbd1-e80a7685f2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050014130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4050014130
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2583462691
Short name T341
Test name
Test status
Simulation time 4281939018 ps
CPU time 6.83 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:46 PM PDT 24
Peak memory 198140 kb
Host smart-d49685fc-2050-4482-97ce-842508bc7bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583462691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2583462691
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1060056128
Short name T393
Test name
Test status
Simulation time 424380578 ps
CPU time 1.15 seconds
Started Jul 20 05:55:53 PM PDT 24
Finished Jul 20 05:55:55 PM PDT 24
Peak memory 196556 kb
Host smart-3a5a3eeb-4ee4-4f32-8053-831667567cc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060056128 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1060056128
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3922019540
Short name T60
Test name
Test status
Simulation time 543782217 ps
CPU time 0.98 seconds
Started Jul 20 05:55:44 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 193516 kb
Host smart-9b771a45-d993-4c23-8a4c-848d9606974d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922019540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3922019540
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3256147402
Short name T385
Test name
Test status
Simulation time 503763547 ps
CPU time 0.75 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:46 PM PDT 24
Peak memory 184192 kb
Host smart-7df9eb60-7c9c-40a0-9161-3adef1d22ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256147402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3256147402
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.809728856
Short name T281
Test name
Test status
Simulation time 437327011 ps
CPU time 2.04 seconds
Started Jul 20 05:55:44 PM PDT 24
Finished Jul 20 05:55:50 PM PDT 24
Peak memory 199040 kb
Host smart-6a0e1a03-4609-48e5-8427-0665e2047c09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809728856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.809728856
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.88897829
Short name T326
Test name
Test status
Simulation time 4418667726 ps
CPU time 6.76 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:52 PM PDT 24
Peak memory 198420 kb
Host smart-5925460d-f0dd-4c9c-8587-68d7b47d7c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88897829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_
intg_err.88897829
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2300499828
Short name T362
Test name
Test status
Simulation time 541425722 ps
CPU time 1.08 seconds
Started Jul 20 05:55:38 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 196520 kb
Host smart-40ba1b35-009b-467e-9c51-dc711f95e081
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300499828 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2300499828
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2981746439
Short name T348
Test name
Test status
Simulation time 347075739 ps
CPU time 1.03 seconds
Started Jul 20 05:55:44 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 193404 kb
Host smart-80645521-d4a4-4ae2-843d-812947949e72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981746439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2981746439
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.526870770
Short name T313
Test name
Test status
Simulation time 513687000 ps
CPU time 1.13 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:46 PM PDT 24
Peak memory 184188 kb
Host smart-1ad1bc2f-8b5d-46e2-8c0a-7e8b00514d93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526870770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.526870770
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2683685863
Short name T401
Test name
Test status
Simulation time 1331857022 ps
CPU time 0.75 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 184180 kb
Host smart-5728481d-f3cc-45ad-bf86-a808eee86ba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683685863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2683685863
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4049583768
Short name T346
Test name
Test status
Simulation time 584597309 ps
CPU time 2.43 seconds
Started Jul 20 05:55:42 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 198972 kb
Host smart-61497810-7f49-47fb-9632-df14a0eedc1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049583768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4049583768
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3439087564
Short name T351
Test name
Test status
Simulation time 4483463879 ps
CPU time 6.9 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 198380 kb
Host smart-9ddecce2-b834-4377-80d2-c2d264847bba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439087564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3439087564
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2081544615
Short name T406
Test name
Test status
Simulation time 668271316 ps
CPU time 0.93 seconds
Started Jul 20 05:55:42 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 197588 kb
Host smart-5d178ee9-05f8-48d6-a44c-27172e646b9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081544615 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2081544615
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2352471289
Short name T65
Test name
Test status
Simulation time 597729716 ps
CPU time 0.64 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 193580 kb
Host smart-b736dc05-6a02-49a8-9751-fb731e292eeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352471289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2352471289
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2718980084
Short name T368
Test name
Test status
Simulation time 374822220 ps
CPU time 1.14 seconds
Started Jul 20 05:55:44 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 193424 kb
Host smart-31c67257-7a22-4005-a4a6-d4198618c999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718980084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2718980084
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.9616269
Short name T75
Test name
Test status
Simulation time 1237498291 ps
CPU time 2.12 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 194052 kb
Host smart-e1b1a910-c8f5-427e-801c-2c5ddb7cd2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9616269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_t
imer_same_csr_outstanding.9616269
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2892794964
Short name T403
Test name
Test status
Simulation time 699066231 ps
CPU time 2.44 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 199012 kb
Host smart-0218d239-fb86-40d5-b69b-47f883731a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892794964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2892794964
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2197750247
Short name T197
Test name
Test status
Simulation time 4221020589 ps
CPU time 1.95 seconds
Started Jul 20 05:55:36 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 198216 kb
Host smart-cf779589-e450-46cd-a725-60335285634f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197750247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2197750247
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2847521555
Short name T288
Test name
Test status
Simulation time 367252246 ps
CPU time 0.92 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 196264 kb
Host smart-8d469a6c-ef5a-4d2e-a30b-7a5c3b3d738c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847521555 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2847521555
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1782985187
Short name T53
Test name
Test status
Simulation time 318561515 ps
CPU time 0.67 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:50 PM PDT 24
Peak memory 193444 kb
Host smart-a7694351-ad47-4a30-a108-d46b4303d9ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782985187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1782985187
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1991556580
Short name T305
Test name
Test status
Simulation time 403781615 ps
CPU time 1.14 seconds
Started Jul 20 05:55:48 PM PDT 24
Finished Jul 20 05:55:52 PM PDT 24
Peak memory 184188 kb
Host smart-b96b613b-13b3-4bdb-9196-2fe8e81e6379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991556580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1991556580
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3139750645
Short name T419
Test name
Test status
Simulation time 1341543177 ps
CPU time 1.54 seconds
Started Jul 20 05:55:42 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 193396 kb
Host smart-14cc2a11-e5d9-445c-9e2a-0269192f4c78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139750645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3139750645
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1729341622
Short name T370
Test name
Test status
Simulation time 555674359 ps
CPU time 2.12 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:43 PM PDT 24
Peak memory 198992 kb
Host smart-84a80127-5d76-46ed-a702-bb7642098eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729341622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1729341622
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.936719285
Short name T364
Test name
Test status
Simulation time 4346238776 ps
CPU time 2.28 seconds
Started Jul 20 05:55:44 PM PDT 24
Finished Jul 20 05:55:50 PM PDT 24
Peak memory 198388 kb
Host smart-329ee4e4-a8d0-4e53-88c7-892ae24b503b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936719285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.936719285
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2137907955
Short name T352
Test name
Test status
Simulation time 342031768 ps
CPU time 0.97 seconds
Started Jul 20 05:55:48 PM PDT 24
Finished Jul 20 05:55:52 PM PDT 24
Peak memory 197400 kb
Host smart-73f4001a-ccc1-4683-b396-bda8a7355fb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137907955 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2137907955
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.61386455
Short name T61
Test name
Test status
Simulation time 459981218 ps
CPU time 0.67 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:48 PM PDT 24
Peak memory 193488 kb
Host smart-9f263f24-20bb-4276-bf9b-453699cdf890
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61386455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.61386455
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2115112699
Short name T380
Test name
Test status
Simulation time 282689405 ps
CPU time 0.95 seconds
Started Jul 20 05:55:38 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 193408 kb
Host smart-f4290c1b-ce8a-4465-b3f2-d75122edb8c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115112699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2115112699
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3948292826
Short name T360
Test name
Test status
Simulation time 2018129107 ps
CPU time 1.83 seconds
Started Jul 20 05:55:49 PM PDT 24
Finished Jul 20 05:55:54 PM PDT 24
Peak memory 195396 kb
Host smart-eca9ae65-6ae9-4473-817d-07df050c29bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948292826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3948292826
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3590651109
Short name T376
Test name
Test status
Simulation time 429805642 ps
CPU time 2.64 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:48 PM PDT 24
Peak memory 199068 kb
Host smart-6379162f-fb99-4a36-bb3e-8acc39d99905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590651109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3590651109
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2852013322
Short name T32
Test name
Test status
Simulation time 7698829786 ps
CPU time 11.47 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:58 PM PDT 24
Peak memory 198692 kb
Host smart-6b1c90e0-aa03-4b38-be5c-a1d81233d67d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852013322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2852013322
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2999153971
Short name T308
Test name
Test status
Simulation time 500321481 ps
CPU time 1.32 seconds
Started Jul 20 05:55:54 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 196820 kb
Host smart-2444bbb6-97c0-4b37-b338-d78152a378b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999153971 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2999153971
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.799139750
Short name T62
Test name
Test status
Simulation time 440817280 ps
CPU time 0.81 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 192528 kb
Host smart-88938490-e223-424c-a673-3eac98e3f97a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799139750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.799139750
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2579123836
Short name T347
Test name
Test status
Simulation time 454283293 ps
CPU time 0.6 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:50 PM PDT 24
Peak memory 184324 kb
Host smart-d66f837e-c496-41f3-b055-3fed201e5ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579123836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2579123836
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1351114085
Short name T372
Test name
Test status
Simulation time 2366259391 ps
CPU time 2.42 seconds
Started Jul 20 05:55:47 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 195452 kb
Host smart-153257a6-1b62-41fc-b101-d9b7dbb2cce3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351114085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1351114085
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1121978996
Short name T359
Test name
Test status
Simulation time 1186091106 ps
CPU time 1.32 seconds
Started Jul 20 05:55:48 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 198968 kb
Host smart-8382b3c5-f34c-4e82-8fce-05a971646289
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121978996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1121978996
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.167399127
Short name T324
Test name
Test status
Simulation time 8343638444 ps
CPU time 12.94 seconds
Started Jul 20 05:55:44 PM PDT 24
Finished Jul 20 05:56:01 PM PDT 24
Peak memory 198612 kb
Host smart-6335049a-4919-4505-8d24-92fa61a1d749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167399127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.167399127
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4029047166
Short name T386
Test name
Test status
Simulation time 596635232 ps
CPU time 0.71 seconds
Started Jul 20 05:55:51 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 195996 kb
Host smart-80481c3f-674e-47d2-8c1d-a4cb3b3e4145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029047166 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4029047166
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.317330590
Short name T59
Test name
Test status
Simulation time 406316136 ps
CPU time 1.14 seconds
Started Jul 20 05:55:47 PM PDT 24
Finished Jul 20 05:55:52 PM PDT 24
Peak memory 192460 kb
Host smart-b1a4b401-0fbd-4440-bed3-e9ba6c37c02c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317330590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.317330590
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2323596389
Short name T374
Test name
Test status
Simulation time 419003845 ps
CPU time 1.11 seconds
Started Jul 20 05:55:50 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 193400 kb
Host smart-0987e1ee-a112-41ec-aa6f-6cc78cae9bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323596389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2323596389
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.856818031
Short name T383
Test name
Test status
Simulation time 2430768545 ps
CPU time 1.25 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 194256 kb
Host smart-cf46ade9-a0cf-4031-8022-ee7aeb361cc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856818031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.856818031
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.102544930
Short name T349
Test name
Test status
Simulation time 393264570 ps
CPU time 2.18 seconds
Started Jul 20 05:55:44 PM PDT 24
Finished Jul 20 05:55:50 PM PDT 24
Peak memory 198988 kb
Host smart-d55a7f64-c87b-4293-9640-4e3dcb3dd462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102544930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.102544930
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1375207715
Short name T195
Test name
Test status
Simulation time 4493529838 ps
CPU time 6.47 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:56 PM PDT 24
Peak memory 198348 kb
Host smart-f2442506-3011-484b-aee9-6a2435d26072
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375207715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1375207715
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3668086038
Short name T387
Test name
Test status
Simulation time 406485204 ps
CPU time 1.12 seconds
Started Jul 20 05:55:48 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 196236 kb
Host smart-3be9e0b8-290b-454f-b0d7-b8a616062b25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668086038 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3668086038
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.143359669
Short name T68
Test name
Test status
Simulation time 377768516 ps
CPU time 1.2 seconds
Started Jul 20 05:55:49 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 193820 kb
Host smart-2cf5826f-53c4-4c75-ab09-3157556ae542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143359669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.143359669
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.162521118
Short name T350
Test name
Test status
Simulation time 427389354 ps
CPU time 1.13 seconds
Started Jul 20 05:55:48 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 184196 kb
Host smart-99b166ff-c8d3-4d4a-b52f-ed2f15c40145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162521118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.162521118
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3183165290
Short name T319
Test name
Test status
Simulation time 2504337669 ps
CPU time 3.86 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:54 PM PDT 24
Peak memory 194772 kb
Host smart-8afa6a3a-a93c-4788-909c-8e9739ecafae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183165290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3183165290
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.299929838
Short name T334
Test name
Test status
Simulation time 411641967 ps
CPU time 2.27 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 199040 kb
Host smart-f8fef32d-b14d-470d-be5b-77ea279c04de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299929838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.299929838
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3011426998
Short name T317
Test name
Test status
Simulation time 495491170 ps
CPU time 1.39 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:58 PM PDT 24
Peak memory 196884 kb
Host smart-3e5c3006-0722-438e-a7c1-32619f94e200
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011426998 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3011426998
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1396318599
Short name T296
Test name
Test status
Simulation time 388595050 ps
CPU time 1.16 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 193404 kb
Host smart-f3b9d8fd-bab3-4ef7-a38c-188e9ad45360
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396318599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1396318599
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3148221625
Short name T413
Test name
Test status
Simulation time 278132422 ps
CPU time 0.99 seconds
Started Jul 20 05:55:49 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 193408 kb
Host smart-c05c25bb-b34e-4db0-9f69-33625b46b008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148221625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3148221625
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2743209933
Short name T312
Test name
Test status
Simulation time 2394622578 ps
CPU time 1.73 seconds
Started Jul 20 05:55:47 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 193492 kb
Host smart-b4315a65-7ced-4e0e-929f-20843ef36ede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743209933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2743209933
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2170140995
Short name T392
Test name
Test status
Simulation time 582867463 ps
CPU time 1.27 seconds
Started Jul 20 05:55:48 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 198984 kb
Host smart-6c601bb3-7424-452c-811d-0c26fd257651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170140995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2170140995
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1905726292
Short name T198
Test name
Test status
Simulation time 4382178785 ps
CPU time 6.72 seconds
Started Jul 20 05:55:52 PM PDT 24
Finished Jul 20 05:56:00 PM PDT 24
Peak memory 198244 kb
Host smart-b7eef508-d6fd-4cde-adfa-6278132c3c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905726292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1905726292
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2507664778
Short name T363
Test name
Test status
Simulation time 643088718 ps
CPU time 1.04 seconds
Started Jul 20 05:55:49 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 197820 kb
Host smart-9d9d71b8-f174-4d0c-b5dd-792cf0d5b96d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507664778 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2507664778
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3483039420
Short name T66
Test name
Test status
Simulation time 476540806 ps
CPU time 0.97 seconds
Started Jul 20 05:55:54 PM PDT 24
Finished Jul 20 05:55:55 PM PDT 24
Peak memory 194428 kb
Host smart-edd95847-5d6b-4fa4-ae6d-f9b498e29a0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483039420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3483039420
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3177847597
Short name T411
Test name
Test status
Simulation time 436829820 ps
CPU time 0.62 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 193412 kb
Host smart-4a0d459b-fdbf-4d8e-b48d-6df6aabe810a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177847597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3177847597
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2597876962
Short name T321
Test name
Test status
Simulation time 1551976221 ps
CPU time 1.71 seconds
Started Jul 20 05:55:50 PM PDT 24
Finished Jul 20 05:55:54 PM PDT 24
Peak memory 195428 kb
Host smart-c342e79c-861f-410c-977c-f02e1b9e4b52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597876962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2597876962
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3464431276
Short name T356
Test name
Test status
Simulation time 765044016 ps
CPU time 2.24 seconds
Started Jul 20 05:55:47 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 199068 kb
Host smart-f3a7f7aa-1499-4d0c-899c-3ae46f9e3eac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464431276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3464431276
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1308169628
Short name T379
Test name
Test status
Simulation time 8046444494 ps
CPU time 3.58 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:53 PM PDT 24
Peak memory 198612 kb
Host smart-f1b859bb-384e-4238-bc54-90d5b839bbc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308169628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1308169628
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2211088254
Short name T64
Test name
Test status
Simulation time 436847315 ps
CPU time 1.09 seconds
Started Jul 20 05:55:44 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 184184 kb
Host smart-29dd25fd-ea00-4a6d-827f-1c31b9484add
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211088254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2211088254
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4084411589
Short name T55
Test name
Test status
Simulation time 7542645219 ps
CPU time 6.45 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 192648 kb
Host smart-346f4eee-bb9c-432b-87c4-79bcb3df269a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084411589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4084411589
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1219557337
Short name T325
Test name
Test status
Simulation time 883865946 ps
CPU time 0.75 seconds
Started Jul 20 05:55:40 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 184188 kb
Host smart-5ec7ea1e-7b1e-4d58-93a6-8dc9feb83613
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219557337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1219557337
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.841723525
Short name T303
Test name
Test status
Simulation time 387004921 ps
CPU time 0.76 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:45 PM PDT 24
Peak memory 196016 kb
Host smart-c99f5733-3616-48b0-ba4e-2d1cbde598c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841723525 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.841723525
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3658503694
Short name T56
Test name
Test status
Simulation time 348384641 ps
CPU time 0.72 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:36 PM PDT 24
Peak memory 193508 kb
Host smart-c3a0b61e-64a8-454f-b5d4-506b42bfcee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658503694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3658503694
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2217754353
Short name T345
Test name
Test status
Simulation time 383143888 ps
CPU time 0.68 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:46 PM PDT 24
Peak memory 193432 kb
Host smart-699c0358-98b4-43a4-94d3-385428ac142a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217754353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2217754353
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3866611250
Short name T310
Test name
Test status
Simulation time 456807199 ps
CPU time 0.62 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:36 PM PDT 24
Peak memory 184116 kb
Host smart-ea61dfd6-f8e8-47b7-a1f3-7700e6de07e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866611250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3866611250
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2524344367
Short name T396
Test name
Test status
Simulation time 415043784 ps
CPU time 0.68 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 184060 kb
Host smart-46ebe8a6-4fa2-4638-b6ff-8100d7632090
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524344367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2524344367
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2352098410
Short name T73
Test name
Test status
Simulation time 1155720984 ps
CPU time 0.93 seconds
Started Jul 20 05:55:42 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 193380 kb
Host smart-172e0fbb-c30d-406a-8a48-8cbe79b0f927
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352098410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2352098410
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.292398230
Short name T290
Test name
Test status
Simulation time 2045555775 ps
CPU time 2.17 seconds
Started Jul 20 05:55:33 PM PDT 24
Finished Jul 20 05:55:39 PM PDT 24
Peak memory 199052 kb
Host smart-af8cb16b-8df4-4b86-b677-50f47da78e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292398230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.292398230
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1455506932
Short name T320
Test name
Test status
Simulation time 4509714514 ps
CPU time 2.54 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 197072 kb
Host smart-9689629d-2d43-44ed-b66a-3f74acf349cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455506932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1455506932
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.881555819
Short name T402
Test name
Test status
Simulation time 503079318 ps
CPU time 0.95 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 193416 kb
Host smart-4849936e-6357-4ce9-b3fb-8772a7fda569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881555819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.881555819
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3165506266
Short name T285
Test name
Test status
Simulation time 310669657 ps
CPU time 1 seconds
Started Jul 20 05:55:57 PM PDT 24
Finished Jul 20 05:55:59 PM PDT 24
Peak memory 184156 kb
Host smart-d732bbc8-471b-44f6-9eb8-4d4b721120bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165506266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3165506266
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3288500176
Short name T388
Test name
Test status
Simulation time 549400671 ps
CPU time 0.68 seconds
Started Jul 20 05:55:59 PM PDT 24
Finished Jul 20 05:56:01 PM PDT 24
Peak memory 184184 kb
Host smart-704ad09f-13f6-4d94-8f2e-b45ec4ccbc25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288500176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3288500176
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1896696077
Short name T304
Test name
Test status
Simulation time 399239404 ps
CPU time 1.17 seconds
Started Jul 20 05:55:56 PM PDT 24
Finished Jul 20 05:55:58 PM PDT 24
Peak memory 184188 kb
Host smart-aeb42942-7b32-4139-95d6-ba487c03100c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896696077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1896696077
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.391744420
Short name T412
Test name
Test status
Simulation time 435993485 ps
CPU time 0.57 seconds
Started Jul 20 05:55:58 PM PDT 24
Finished Jul 20 05:55:59 PM PDT 24
Peak memory 184196 kb
Host smart-3c0e459b-9aff-454e-93b4-cae24d959a8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391744420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.391744420
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.430995343
Short name T316
Test name
Test status
Simulation time 396388012 ps
CPU time 0.82 seconds
Started Jul 20 05:55:56 PM PDT 24
Finished Jul 20 05:55:58 PM PDT 24
Peak memory 184120 kb
Host smart-f2db349b-d9c4-4a6d-b1ab-623f8b3836ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430995343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.430995343
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.239412047
Short name T294
Test name
Test status
Simulation time 432250175 ps
CPU time 1.18 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:58 PM PDT 24
Peak memory 193432 kb
Host smart-86e0e63e-4ecf-41ec-920e-4492537b38f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239412047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.239412047
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1400486206
Short name T286
Test name
Test status
Simulation time 341208830 ps
CPU time 1.04 seconds
Started Jul 20 05:55:58 PM PDT 24
Finished Jul 20 05:56:00 PM PDT 24
Peak memory 184192 kb
Host smart-8041f50f-4c96-4241-b73b-dbe07ce91af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400486206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1400486206
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2822642611
Short name T353
Test name
Test status
Simulation time 445919810 ps
CPU time 0.69 seconds
Started Jul 20 05:55:56 PM PDT 24
Finished Jul 20 05:55:58 PM PDT 24
Peak memory 193372 kb
Host smart-0e3a61e9-d4dd-47fc-899b-edab3c6de49a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822642611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2822642611
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3210580855
Short name T300
Test name
Test status
Simulation time 332463278 ps
CPU time 0.69 seconds
Started Jul 20 05:56:00 PM PDT 24
Finished Jul 20 05:56:01 PM PDT 24
Peak memory 193408 kb
Host smart-e8dc0453-ce9e-437c-aec8-a6bec2cd8f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210580855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3210580855
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1633766193
Short name T52
Test name
Test status
Simulation time 453786441 ps
CPU time 0.81 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:37 PM PDT 24
Peak memory 184172 kb
Host smart-f5ca5072-6ae8-485a-8ae6-ec998254b814
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633766193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1633766193
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2835707908
Short name T323
Test name
Test status
Simulation time 7318755092 ps
CPU time 2.11 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 192616 kb
Host smart-92294305-1494-4e0a-bb62-7775f5eef705
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835707908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2835707908
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3344327450
Short name T395
Test name
Test status
Simulation time 1307151719 ps
CPU time 1.58 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:46 PM PDT 24
Peak memory 184176 kb
Host smart-6ebe7645-6c3a-41d9-aadf-7f679c87c2b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344327450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3344327450
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1625198338
Short name T398
Test name
Test status
Simulation time 467427972 ps
CPU time 1.36 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 197128 kb
Host smart-db6a162c-b914-47b6-a4ba-d8369472c2eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625198338 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1625198338
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2409067543
Short name T63
Test name
Test status
Simulation time 344263171 ps
CPU time 0.74 seconds
Started Jul 20 05:55:40 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 193884 kb
Host smart-efdf786b-f550-4400-891c-c55f6e3d2b94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409067543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2409067543
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.594119015
Short name T369
Test name
Test status
Simulation time 472188355 ps
CPU time 0.77 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:50 PM PDT 24
Peak memory 193416 kb
Host smart-404f573f-4839-46e6-8f20-be776d6c5437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594119015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.594119015
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3523765030
Short name T292
Test name
Test status
Simulation time 315518409 ps
CPU time 1.04 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 184128 kb
Host smart-cb1b6f2e-bcb2-4d89-baa8-916a2673f156
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523765030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3523765030
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.340741792
Short name T297
Test name
Test status
Simulation time 295267114 ps
CPU time 0.68 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 184132 kb
Host smart-83211d32-0259-4ee3-9c11-f05a43b201e2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340741792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.340741792
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1726326506
Short name T355
Test name
Test status
Simulation time 1258224048 ps
CPU time 2.23 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:48 PM PDT 24
Peak memory 193420 kb
Host smart-d889a06a-6d68-474f-8630-5be2956dbfc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726326506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1726326506
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3002475903
Short name T301
Test name
Test status
Simulation time 384446250 ps
CPU time 2.18 seconds
Started Jul 20 05:55:29 PM PDT 24
Finished Jul 20 05:55:32 PM PDT 24
Peak memory 199144 kb
Host smart-2080d86a-306e-4cfb-a3fa-0032a87b9b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002475903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3002475903
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3186553944
Short name T327
Test name
Test status
Simulation time 4323337084 ps
CPU time 1.56 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:52 PM PDT 24
Peak memory 198280 kb
Host smart-0a8b71f9-e23f-4bf7-867a-c20c16e7343b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186553944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3186553944
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1256525964
Short name T331
Test name
Test status
Simulation time 415995774 ps
CPU time 1.13 seconds
Started Jul 20 05:55:58 PM PDT 24
Finished Jul 20 05:56:00 PM PDT 24
Peak memory 184196 kb
Host smart-b8dcb210-f642-4bc8-8fcd-a24538ada898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256525964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1256525964
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.900992327
Short name T282
Test name
Test status
Simulation time 479309817 ps
CPU time 0.72 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 193380 kb
Host smart-aeb34426-3765-44d4-9ad7-3d18bf30ba2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900992327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.900992327
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2066435185
Short name T342
Test name
Test status
Simulation time 349695014 ps
CPU time 1.01 seconds
Started Jul 20 05:56:01 PM PDT 24
Finished Jul 20 05:56:02 PM PDT 24
Peak memory 184192 kb
Host smart-562476cb-eb14-4525-9681-2ae18a56f3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066435185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2066435185
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1549362981
Short name T295
Test name
Test status
Simulation time 339657884 ps
CPU time 1.04 seconds
Started Jul 20 05:55:54 PM PDT 24
Finished Jul 20 05:55:56 PM PDT 24
Peak memory 184160 kb
Host smart-ef47eeb6-86e0-4795-acfa-f4f298ad8375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549362981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1549362981
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2990963735
Short name T314
Test name
Test status
Simulation time 488493952 ps
CPU time 1.25 seconds
Started Jul 20 05:55:56 PM PDT 24
Finished Jul 20 05:55:58 PM PDT 24
Peak memory 184192 kb
Host smart-94686239-f51e-4070-8d70-f7ed37e7ba4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990963735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2990963735
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.81831670
Short name T280
Test name
Test status
Simulation time 429697889 ps
CPU time 1.18 seconds
Started Jul 20 05:55:59 PM PDT 24
Finished Jul 20 05:56:01 PM PDT 24
Peak memory 184192 kb
Host smart-2d7ac810-4abe-4c95-ba2e-8382399507a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81831670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.81831670
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3750642879
Short name T404
Test name
Test status
Simulation time 347730273 ps
CPU time 0.63 seconds
Started Jul 20 05:55:58 PM PDT 24
Finished Jul 20 05:56:00 PM PDT 24
Peak memory 184124 kb
Host smart-6bde6a95-d385-4ec3-bd3c-c84da97d5c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750642879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3750642879
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.901906181
Short name T328
Test name
Test status
Simulation time 415930917 ps
CPU time 1.05 seconds
Started Jul 20 05:55:58 PM PDT 24
Finished Jul 20 05:56:00 PM PDT 24
Peak memory 193336 kb
Host smart-119365c7-718b-4545-a54c-ca4de2fbd35e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901906181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.901906181
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3082507037
Short name T415
Test name
Test status
Simulation time 335977022 ps
CPU time 1.11 seconds
Started Jul 20 05:56:00 PM PDT 24
Finished Jul 20 05:56:02 PM PDT 24
Peak memory 184188 kb
Host smart-2f67ad91-66d1-4788-a16f-f518e7c6170b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082507037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3082507037
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3428108839
Short name T361
Test name
Test status
Simulation time 464516864 ps
CPU time 1.24 seconds
Started Jul 20 05:55:58 PM PDT 24
Finished Jul 20 05:56:00 PM PDT 24
Peak memory 184192 kb
Host smart-e2086941-2689-4685-b4f0-aba84a4a129d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428108839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3428108839
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3633575768
Short name T375
Test name
Test status
Simulation time 706718368 ps
CPU time 1.03 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:55:34 PM PDT 24
Peak memory 194268 kb
Host smart-db8df228-c871-4eb6-8ca4-cb15e9b96d0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633575768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3633575768
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2290093038
Short name T407
Test name
Test status
Simulation time 7396441234 ps
CPU time 4.81 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:45 PM PDT 24
Peak memory 196444 kb
Host smart-c29330fa-e1d4-43b2-90bb-f3d48576b873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290093038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2290093038
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2584134380
Short name T299
Test name
Test status
Simulation time 777272508 ps
CPU time 0.84 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:36 PM PDT 24
Peak memory 192556 kb
Host smart-7f46c64b-86a7-4d73-ba38-7cd5bce5fc42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584134380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2584134380
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2112959428
Short name T306
Test name
Test status
Simulation time 509391711 ps
CPU time 1.31 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:36 PM PDT 24
Peak memory 196208 kb
Host smart-83fda156-37ec-481d-8938-f4173ff4a33e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112959428 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2112959428
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2007926690
Short name T384
Test name
Test status
Simulation time 466219411 ps
CPU time 1.18 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 193404 kb
Host smart-ab464be5-6fc9-4a36-9586-495cfe1e6f5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007926690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2007926690
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1992849003
Short name T414
Test name
Test status
Simulation time 275224709 ps
CPU time 0.89 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:40 PM PDT 24
Peak memory 184252 kb
Host smart-5f35ef3a-662c-4499-a09e-191e0e4c2164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992849003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1992849003
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.197961762
Short name T340
Test name
Test status
Simulation time 437346926 ps
CPU time 0.67 seconds
Started Jul 20 05:55:40 PM PDT 24
Finished Jul 20 05:55:43 PM PDT 24
Peak memory 184112 kb
Host smart-4ced595b-98e6-4dd8-a8a9-e1cd2df8fcef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197961762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.197961762
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3076682671
Short name T289
Test name
Test status
Simulation time 295712929 ps
CPU time 0.91 seconds
Started Jul 20 05:55:33 PM PDT 24
Finished Jul 20 05:55:37 PM PDT 24
Peak memory 184032 kb
Host smart-c4e4c9d7-ef85-4002-8100-c3854534428b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076682671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3076682671
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2087016930
Short name T70
Test name
Test status
Simulation time 2894668298 ps
CPU time 8.74 seconds
Started Jul 20 05:55:38 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 195532 kb
Host smart-43ac666d-0d66-47ed-be40-44ad4388686b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087016930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2087016930
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1141133384
Short name T298
Test name
Test status
Simulation time 889536641 ps
CPU time 2.39 seconds
Started Jul 20 05:55:30 PM PDT 24
Finished Jul 20 05:55:35 PM PDT 24
Peak memory 198952 kb
Host smart-ef5f3b1a-0eaa-459a-b368-7e281ea39e1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141133384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1141133384
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2633262718
Short name T365
Test name
Test status
Simulation time 8585993227 ps
CPU time 4.14 seconds
Started Jul 20 05:55:32 PM PDT 24
Finished Jul 20 05:55:40 PM PDT 24
Peak memory 198700 kb
Host smart-2fe1f985-cb85-473a-b297-857226e23264
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633262718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2633262718
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2032776682
Short name T410
Test name
Test status
Simulation time 273304848 ps
CPU time 0.76 seconds
Started Jul 20 05:55:58 PM PDT 24
Finished Jul 20 05:56:00 PM PDT 24
Peak memory 193416 kb
Host smart-d70d151d-4597-4b4d-95d1-3b764a73b6d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032776682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2032776682
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1999213659
Short name T283
Test name
Test status
Simulation time 397398618 ps
CPU time 1.06 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 184164 kb
Host smart-329169e4-62da-4287-aeab-1bbf21707b6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999213659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1999213659
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.895976474
Short name T302
Test name
Test status
Simulation time 436689518 ps
CPU time 0.72 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:56 PM PDT 24
Peak memory 184208 kb
Host smart-b33084e0-0a51-4833-960f-a71e34d5e7a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895976474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.895976474
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1739369544
Short name T366
Test name
Test status
Simulation time 453648788 ps
CPU time 0.7 seconds
Started Jul 20 05:56:01 PM PDT 24
Finished Jul 20 05:56:03 PM PDT 24
Peak memory 193408 kb
Host smart-9d2815dd-1b0a-476e-9a1a-148851c2f474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739369544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1739369544
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2089376128
Short name T367
Test name
Test status
Simulation time 498603161 ps
CPU time 0.79 seconds
Started Jul 20 05:55:54 PM PDT 24
Finished Jul 20 05:55:55 PM PDT 24
Peak memory 184180 kb
Host smart-0819ea89-010a-46fc-aecb-b146c360d48e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089376128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2089376128
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1249946095
Short name T315
Test name
Test status
Simulation time 455053550 ps
CPU time 1.25 seconds
Started Jul 20 05:55:52 PM PDT 24
Finished Jul 20 05:55:55 PM PDT 24
Peak memory 184200 kb
Host smart-0e998794-ac4f-4541-857c-ff8f1890edeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249946095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1249946095
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1817336215
Short name T358
Test name
Test status
Simulation time 337524508 ps
CPU time 1.04 seconds
Started Jul 20 05:55:57 PM PDT 24
Finished Jul 20 05:55:59 PM PDT 24
Peak memory 184184 kb
Host smart-0b2d8129-ca25-4bb8-8b4d-682ca5a9fcc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817336215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1817336215
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.539154422
Short name T391
Test name
Test status
Simulation time 596368197 ps
CPU time 0.6 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 184244 kb
Host smart-219edf7c-ad04-4c9d-8f9d-e03472c2f63e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539154422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.539154422
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3698790739
Short name T330
Test name
Test status
Simulation time 378653547 ps
CPU time 0.79 seconds
Started Jul 20 05:55:55 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 184248 kb
Host smart-1a728e41-997d-4418-979f-35dacb5f0804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698790739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3698790739
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3328352461
Short name T400
Test name
Test status
Simulation time 312290517 ps
CPU time 0.71 seconds
Started Jul 20 05:55:54 PM PDT 24
Finished Jul 20 05:55:55 PM PDT 24
Peak memory 193416 kb
Host smart-f4e66177-1c05-4cca-8de6-4b9212e2cc0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328352461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3328352461
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1940583181
Short name T318
Test name
Test status
Simulation time 422492151 ps
CPU time 0.76 seconds
Started Jul 20 05:55:40 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 196172 kb
Host smart-be9900b0-5553-4e30-aba1-7eb0e0f11372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940583181 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1940583181
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2728714004
Short name T394
Test name
Test status
Simulation time 311926394 ps
CPU time 0.94 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:43 PM PDT 24
Peak memory 193384 kb
Host smart-09eafbc4-9a28-4434-8fd5-541977fe6978
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728714004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2728714004
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2361557522
Short name T309
Test name
Test status
Simulation time 264837532 ps
CPU time 0.96 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:42 PM PDT 24
Peak memory 193336 kb
Host smart-c8d12c28-aa87-4a9c-abc6-1089473a6be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361557522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2361557522
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2341854735
Short name T71
Test name
Test status
Simulation time 1434512532 ps
CPU time 1.13 seconds
Started Jul 20 05:55:40 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 193404 kb
Host smart-05ee2b39-c390-4cd4-baaa-68cc9c0c2dd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341854735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2341854735
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1119063994
Short name T293
Test name
Test status
Simulation time 377899544 ps
CPU time 1.91 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:37 PM PDT 24
Peak memory 198972 kb
Host smart-7736219e-592c-4992-a58b-2e3cb8c8fefe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119063994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1119063994
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.412791596
Short name T354
Test name
Test status
Simulation time 7901210690 ps
CPU time 13.6 seconds
Started Jul 20 05:55:31 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 198592 kb
Host smart-ee6063c8-3537-4782-a0a0-c7736f761e4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412791596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.412791596
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3103040035
Short name T339
Test name
Test status
Simulation time 580660072 ps
CPU time 1.17 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:48 PM PDT 24
Peak memory 198864 kb
Host smart-f011d937-4d91-485f-a007-4097a21a22c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103040035 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3103040035
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4258844515
Short name T72
Test name
Test status
Simulation time 474285524 ps
CPU time 0.88 seconds
Started Jul 20 05:55:42 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 193404 kb
Host smart-7c3f5428-3dea-444d-8a90-f8473961e2cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258844515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4258844515
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.644765623
Short name T332
Test name
Test status
Simulation time 471803940 ps
CPU time 0.59 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:50 PM PDT 24
Peak memory 193472 kb
Host smart-cf703d3e-7b4a-4d12-92cc-57191866eef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644765623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.644765623
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2580900975
Short name T382
Test name
Test status
Simulation time 1072951701 ps
CPU time 2.85 seconds
Started Jul 20 05:55:44 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 184364 kb
Host smart-f0c88c3d-c8a4-4ac0-8741-b5010180e5de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580900975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2580900975
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4002479982
Short name T335
Test name
Test status
Simulation time 439083042 ps
CPU time 1.91 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:51 PM PDT 24
Peak memory 198904 kb
Host smart-43bb63f4-343b-48be-8c45-e810367ff3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002479982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4002479982
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1259357372
Short name T390
Test name
Test status
Simulation time 562228334 ps
CPU time 1.31 seconds
Started Jul 20 05:55:37 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 195828 kb
Host smart-91d08e7c-78d3-450a-9d48-7e01ff0673d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259357372 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1259357372
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3179147388
Short name T58
Test name
Test status
Simulation time 351513548 ps
CPU time 0.72 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:48 PM PDT 24
Peak memory 194372 kb
Host smart-cacf3649-eec4-47e5-8897-a2fd0f26effe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179147388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3179147388
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2932501632
Short name T399
Test name
Test status
Simulation time 421526875 ps
CPU time 0.69 seconds
Started Jul 20 05:55:42 PM PDT 24
Finished Jul 20 05:55:47 PM PDT 24
Peak memory 184160 kb
Host smart-8e8d84dc-2d69-4712-9366-3e18b719924c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932501632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2932501632
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.778640770
Short name T29
Test name
Test status
Simulation time 1374329318 ps
CPU time 2.32 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 193952 kb
Host smart-43612135-21a0-4a46-bc0b-69f54f8cebcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778640770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.778640770
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.4016902114
Short name T307
Test name
Test status
Simulation time 586255480 ps
CPU time 2.6 seconds
Started Jul 20 05:55:49 PM PDT 24
Finished Jul 20 05:55:54 PM PDT 24
Peak memory 199028 kb
Host smart-ae413f05-2669-428d-894c-77f80ab6cdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016902114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.4016902114
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2784629979
Short name T416
Test name
Test status
Simulation time 4251072400 ps
CPU time 7.09 seconds
Started Jul 20 05:55:46 PM PDT 24
Finished Jul 20 05:55:57 PM PDT 24
Peak memory 198084 kb
Host smart-76a4eb5e-c7aa-4904-a932-50a1723deaa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784629979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2784629979
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.179187404
Short name T333
Test name
Test status
Simulation time 557775476 ps
CPU time 0.83 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:43 PM PDT 24
Peak memory 196312 kb
Host smart-182fbb5d-e4dd-4350-a346-9f24c83dd4ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179187404 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.179187404
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.276733065
Short name T31
Test name
Test status
Simulation time 323428161 ps
CPU time 1.08 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:50 PM PDT 24
Peak memory 193404 kb
Host smart-4d7cdfa6-1e8f-44e8-979d-177cf7c15d3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276733065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.276733065
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2029317374
Short name T284
Test name
Test status
Simulation time 338756280 ps
CPU time 0.8 seconds
Started Jul 20 05:55:38 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 193408 kb
Host smart-76cecd21-6c4a-411b-8187-d146f88efbac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029317374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2029317374
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2484348775
Short name T74
Test name
Test status
Simulation time 1293576729 ps
CPU time 1.1 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:48 PM PDT 24
Peak memory 192372 kb
Host smart-f50e2396-e689-4c3b-a994-ef2777aeaab5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484348775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2484348775
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2725588505
Short name T381
Test name
Test status
Simulation time 324738687 ps
CPU time 1.62 seconds
Started Jul 20 05:55:36 PM PDT 24
Finished Jul 20 05:55:41 PM PDT 24
Peak memory 198920 kb
Host smart-5ffe4566-fbac-416d-b45b-c26320354ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725588505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2725588505
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4154695185
Short name T33
Test name
Test status
Simulation time 7729231829 ps
CPU time 7.84 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:55 PM PDT 24
Peak memory 198900 kb
Host smart-703b9419-a247-4829-9a46-82adbc1990bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154695185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.4154695185
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2944931872
Short name T329
Test name
Test status
Simulation time 435132261 ps
CPU time 0.82 seconds
Started Jul 20 05:55:41 PM PDT 24
Finished Jul 20 05:55:45 PM PDT 24
Peak memory 196576 kb
Host smart-042a1f66-7d06-42e2-b304-76b07c5894cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944931872 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2944931872
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3492180533
Short name T338
Test name
Test status
Simulation time 521466426 ps
CPU time 1 seconds
Started Jul 20 05:55:42 PM PDT 24
Finished Jul 20 05:55:48 PM PDT 24
Peak memory 193568 kb
Host smart-3d0ebffd-6c9e-4974-a259-7b06f745d509
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492180533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3492180533
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.174364923
Short name T377
Test name
Test status
Simulation time 421798031 ps
CPU time 0.81 seconds
Started Jul 20 05:55:45 PM PDT 24
Finished Jul 20 05:55:50 PM PDT 24
Peak memory 184120 kb
Host smart-8a9e6f73-c3de-406e-aaee-8b607baa7824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174364923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.174364923
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3095789708
Short name T76
Test name
Test status
Simulation time 1213985143 ps
CPU time 1.15 seconds
Started Jul 20 05:55:43 PM PDT 24
Finished Jul 20 05:55:48 PM PDT 24
Peak memory 194104 kb
Host smart-13dcb40b-67d5-4c25-87ba-3e867b065973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095789708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3095789708
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1963338592
Short name T397
Test name
Test status
Simulation time 712642093 ps
CPU time 1.48 seconds
Started Jul 20 05:55:40 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 198996 kb
Host smart-2fdac0cf-53d4-4816-b6f7-355219156a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963338592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1963338592
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.312343601
Short name T337
Test name
Test status
Simulation time 8477001570 ps
CPU time 2.98 seconds
Started Jul 20 05:55:39 PM PDT 24
Finished Jul 20 05:55:44 PM PDT 24
Peak memory 198724 kb
Host smart-757b26e3-ac77-4179-ac79-e3cf2dfc2091
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312343601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.312343601
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.709768663
Short name T228
Test name
Test status
Simulation time 4444095119 ps
CPU time 2.16 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 191556 kb
Host smart-070e0c5e-1e4a-4a61-aa19-5e3eff835369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709768663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.709768663
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.298067496
Short name T201
Test name
Test status
Simulation time 382706733 ps
CPU time 1.12 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:45:54 PM PDT 24
Peak memory 191504 kb
Host smart-5d8e94a5-c7f3-41f6-bc6a-76332fb6c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298067496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.298067496
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.772668742
Short name T230
Test name
Test status
Simulation time 17208242763 ps
CPU time 26.82 seconds
Started Jul 20 05:46:05 PM PDT 24
Finished Jul 20 05:46:39 PM PDT 24
Peak memory 196448 kb
Host smart-f6ec7d30-c83b-4c07-bdce-eafc5c87866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772668742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.772668742
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.659398565
Short name T15
Test name
Test status
Simulation time 4390424916 ps
CPU time 2.67 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:45:56 PM PDT 24
Peak memory 215440 kb
Host smart-c0eb5eaf-ebf8-4e0b-9801-bd8b3215d00a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659398565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.659398565
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2181997336
Short name T207
Test name
Test status
Simulation time 548512594 ps
CPU time 1.37 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 191500 kb
Host smart-b1fb57b1-7c4c-4823-8ef2-57250827c0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181997336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2181997336
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.810567596
Short name T250
Test name
Test status
Simulation time 31475056341 ps
CPU time 48.41 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:47:00 PM PDT 24
Peak memory 191544 kb
Host smart-9ebdd3bb-b634-4160-b8b9-2563d1a77db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810567596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.810567596
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3581107935
Short name T242
Test name
Test status
Simulation time 491228202 ps
CPU time 0.72 seconds
Started Jul 20 05:45:53 PM PDT 24
Finished Jul 20 05:45:57 PM PDT 24
Peak memory 191444 kb
Host smart-8ab28a75-94f6-4f94-832d-c62288e50d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581107935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3581107935
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3459669248
Short name T263
Test name
Test status
Simulation time 32823100748 ps
CPU time 49.68 seconds
Started Jul 20 05:46:09 PM PDT 24
Finished Jul 20 05:47:04 PM PDT 24
Peak memory 196520 kb
Host smart-71c8a879-cca3-41ed-b6bf-5d917996e053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459669248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3459669248
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1686538606
Short name T249
Test name
Test status
Simulation time 478007593 ps
CPU time 0.68 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 191456 kb
Host smart-de22fb18-db1f-449d-8f50-b75e7b79c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686538606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1686538606
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1727618577
Short name T41
Test name
Test status
Simulation time 38627649137 ps
CPU time 27.62 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:34 PM PDT 24
Peak memory 191508 kb
Host smart-22a39766-ad6d-44d0-9534-7ae7b9593541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727618577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1727618577
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3059834233
Short name T44
Test name
Test status
Simulation time 573930117 ps
CPU time 0.79 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:12 PM PDT 24
Peak memory 191452 kb
Host smart-101786a0-c2ba-41cc-b643-a3f5bb74ea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059834233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3059834233
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.4244648309
Short name T34
Test name
Test status
Simulation time 50775754194 ps
CPU time 285.06 seconds
Started Jul 20 05:45:57 PM PDT 24
Finished Jul 20 05:50:45 PM PDT 24
Peak memory 207336 kb
Host smart-b1f05d88-579b-4f3c-a6bb-e90f29fd0b0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244648309 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.4244648309
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.299240557
Short name T254
Test name
Test status
Simulation time 12136040456 ps
CPU time 8.65 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:19 PM PDT 24
Peak memory 191524 kb
Host smart-9f949be2-26e2-4560-979c-e8011b661ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299240557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.299240557
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.611402001
Short name T265
Test name
Test status
Simulation time 602605242 ps
CPU time 0.67 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:10 PM PDT 24
Peak memory 191436 kb
Host smart-95beebe1-8c32-4903-a2b4-d9895fc27709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611402001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.611402001
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3135192397
Short name T229
Test name
Test status
Simulation time 26248198982 ps
CPU time 41.1 seconds
Started Jul 20 05:45:49 PM PDT 24
Finished Jul 20 05:46:35 PM PDT 24
Peak memory 196564 kb
Host smart-db93051b-e813-4478-8cf3-95634cfeab91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135192397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3135192397
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2725498200
Short name T272
Test name
Test status
Simulation time 370160254 ps
CPU time 1.05 seconds
Started Jul 20 05:46:12 PM PDT 24
Finished Jul 20 05:46:17 PM PDT 24
Peak memory 191488 kb
Host smart-a48dea93-ebc2-448c-b7f3-9b88db2a0b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725498200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2725498200
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.4184513584
Short name T234
Test name
Test status
Simulation time 2314221517 ps
CPU time 3.65 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:46:16 PM PDT 24
Peak memory 196276 kb
Host smart-2971159e-1367-4a44-8304-d2c0cf1b7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184513584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.4184513584
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.712300850
Short name T215
Test name
Test status
Simulation time 502508610 ps
CPU time 0.86 seconds
Started Jul 20 05:46:22 PM PDT 24
Finished Jul 20 05:46:24 PM PDT 24
Peak memory 196288 kb
Host smart-16175344-05c0-4df6-b01b-eb44500a1cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712300850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.712300850
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3899467601
Short name T50
Test name
Test status
Simulation time 20604816945 ps
CPU time 2.38 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:08 PM PDT 24
Peak memory 191576 kb
Host smart-ec70c234-0873-4f20-98cc-67f8595be94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899467601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3899467601
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2324761408
Short name T219
Test name
Test status
Simulation time 464192402 ps
CPU time 0.65 seconds
Started Jul 20 05:46:17 PM PDT 24
Finished Jul 20 05:46:19 PM PDT 24
Peak memory 196352 kb
Host smart-b183393f-fc82-4498-a3a6-7e6cb9b2f0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324761408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2324761408
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2021608309
Short name T211
Test name
Test status
Simulation time 25601314436 ps
CPU time 7.99 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:18 PM PDT 24
Peak memory 191560 kb
Host smart-135ca2c8-e1cc-466f-981a-c46ecaf503fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021608309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2021608309
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3763329598
Short name T24
Test name
Test status
Simulation time 624233986 ps
CPU time 0.86 seconds
Started Jul 20 05:46:14 PM PDT 24
Finished Jul 20 05:46:18 PM PDT 24
Peak memory 191488 kb
Host smart-1bc9ead8-08b4-4ce5-b1dd-928cce739603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763329598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3763329598
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2740523995
Short name T270
Test name
Test status
Simulation time 38874194402 ps
CPU time 30.12 seconds
Started Jul 20 05:46:13 PM PDT 24
Finished Jul 20 05:46:47 PM PDT 24
Peak memory 191556 kb
Host smart-29bbfdeb-ddce-4e62-950e-34e93b5df85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740523995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2740523995
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1459376829
Short name T276
Test name
Test status
Simulation time 450592714 ps
CPU time 1 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 191524 kb
Host smart-350d4468-d121-4fc0-a864-3a79b8b41fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459376829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1459376829
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.36307550
Short name T261
Test name
Test status
Simulation time 6131376946 ps
CPU time 8.9 seconds
Started Jul 20 05:46:05 PM PDT 24
Finished Jul 20 05:46:22 PM PDT 24
Peak memory 191572 kb
Host smart-4a7d411f-394c-41b7-be16-aada2bc8e79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36307550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.36307550
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.548770892
Short name T233
Test name
Test status
Simulation time 456137756 ps
CPU time 0.97 seconds
Started Jul 20 05:46:19 PM PDT 24
Finished Jul 20 05:46:20 PM PDT 24
Peak memory 191500 kb
Host smart-d01db545-247d-4232-9880-35ec3c330921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548770892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.548770892
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.585877662
Short name T222
Test name
Test status
Simulation time 7165796500 ps
CPU time 5.06 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 191516 kb
Host smart-5c642458-f50b-4e87-b151-c685228155a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585877662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.585877662
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1591825943
Short name T14
Test name
Test status
Simulation time 3819950255 ps
CPU time 5.82 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:16 PM PDT 24
Peak memory 215444 kb
Host smart-c9c72b79-a548-4026-85bf-118b0eda9e21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591825943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1591825943
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3463991203
Short name T257
Test name
Test status
Simulation time 354415696 ps
CPU time 0.78 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:46:13 PM PDT 24
Peak memory 191420 kb
Host smart-1f367093-c92f-4cc3-8f73-52ac98f06880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463991203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3463991203
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1388312542
Short name T253
Test name
Test status
Simulation time 8459725638 ps
CPU time 11.84 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:17 PM PDT 24
Peak memory 191556 kb
Host smart-ffdbe9bd-66c5-41bf-b6a9-8f06a587d950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388312542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1388312542
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2763817521
Short name T277
Test name
Test status
Simulation time 543178911 ps
CPU time 1.46 seconds
Started Jul 20 05:46:08 PM PDT 24
Finished Jul 20 05:46:15 PM PDT 24
Peak memory 191504 kb
Host smart-8f54b1eb-4be8-4663-8ca5-237ccdeda3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763817521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2763817521
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2737381044
Short name T22
Test name
Test status
Simulation time 23518817537 ps
CPU time 4.47 seconds
Started Jul 20 05:46:10 PM PDT 24
Finished Jul 20 05:46:19 PM PDT 24
Peak memory 191524 kb
Host smart-24c43a4a-3c16-4b2a-9bf6-0862938d9209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737381044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2737381044
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2439542605
Short name T226
Test name
Test status
Simulation time 498191262 ps
CPU time 0.75 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:07 PM PDT 24
Peak memory 196352 kb
Host smart-4f62523b-b710-4887-a2b0-11698797f2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439542605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2439542605
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3353076201
Short name T232
Test name
Test status
Simulation time 12796696345 ps
CPU time 11.54 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:46:23 PM PDT 24
Peak memory 196560 kb
Host smart-03ca77e0-6c51-4fe9-8558-02be99f1cbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353076201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3353076201
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3661488534
Short name T245
Test name
Test status
Simulation time 495443899 ps
CPU time 0.7 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:08 PM PDT 24
Peak memory 190880 kb
Host smart-51ae777b-85cb-47b1-9ae3-6c381793d490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661488534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3661488534
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1827182144
Short name T246
Test name
Test status
Simulation time 13335579370 ps
CPU time 2.4 seconds
Started Jul 20 05:46:16 PM PDT 24
Finished Jul 20 05:46:20 PM PDT 24
Peak memory 191544 kb
Host smart-40d8211c-1833-44f2-9c8b-ce5a47d5eedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827182144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1827182144
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1257792106
Short name T247
Test name
Test status
Simulation time 514201904 ps
CPU time 0.81 seconds
Started Jul 20 05:46:22 PM PDT 24
Finished Jul 20 05:46:23 PM PDT 24
Peak memory 196312 kb
Host smart-b2ce2a64-700f-4333-9d52-9347b2083929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257792106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1257792106
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.4270480298
Short name T181
Test name
Test status
Simulation time 464713023 ps
CPU time 0.76 seconds
Started Jul 20 05:45:54 PM PDT 24
Finished Jul 20 05:45:58 PM PDT 24
Peak memory 196276 kb
Host smart-6a95f062-ec20-4f6e-a660-fb86d56a0fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270480298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.4270480298
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2153741714
Short name T224
Test name
Test status
Simulation time 2736797734 ps
CPU time 4.09 seconds
Started Jul 20 05:45:57 PM PDT 24
Finished Jul 20 05:46:03 PM PDT 24
Peak memory 191520 kb
Host smart-e18af596-2bc9-4af1-a8d9-e86485ff5794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153741714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2153741714
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.375676313
Short name T244
Test name
Test status
Simulation time 520115864 ps
CPU time 0.73 seconds
Started Jul 20 05:46:09 PM PDT 24
Finished Jul 20 05:46:15 PM PDT 24
Peak memory 196368 kb
Host smart-6db164af-62f3-4860-aa13-cd19d4ce636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375676313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.375676313
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1573591650
Short name T217
Test name
Test status
Simulation time 29432886866 ps
CPU time 46.77 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:57 PM PDT 24
Peak memory 191556 kb
Host smart-a4e81288-7693-40c7-8675-6f25ef0a6f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573591650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1573591650
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1488968189
Short name T200
Test name
Test status
Simulation time 455024752 ps
CPU time 0.66 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:06 PM PDT 24
Peak memory 191496 kb
Host smart-b4d1bb7f-d0bb-443a-9a55-d18dbaac0b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488968189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1488968189
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2403240806
Short name T88
Test name
Test status
Simulation time 1437890932 ps
CPU time 1.55 seconds
Started Jul 20 05:46:05 PM PDT 24
Finished Jul 20 05:46:14 PM PDT 24
Peak memory 196176 kb
Host smart-72ecc7ab-560c-4540-a4f4-0701dbe6f2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403240806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2403240806
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2658368543
Short name T78
Test name
Test status
Simulation time 564603533 ps
CPU time 0.96 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:08 PM PDT 24
Peak memory 190700 kb
Host smart-88fcb67c-690d-4841-9031-68aa0a675c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658368543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2658368543
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.380685521
Short name T279
Test name
Test status
Simulation time 18295585194 ps
CPU time 7.49 seconds
Started Jul 20 05:46:09 PM PDT 24
Finished Jul 20 05:46:22 PM PDT 24
Peak memory 191544 kb
Host smart-fb89272f-c5f4-4421-b0c2-a55b788d122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380685521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.380685521
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1177389176
Short name T220
Test name
Test status
Simulation time 479616092 ps
CPU time 1.32 seconds
Started Jul 20 05:46:15 PM PDT 24
Finished Jul 20 05:46:18 PM PDT 24
Peak memory 191456 kb
Host smart-929e14d4-a913-4347-a631-0ad6aef1c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177389176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1177389176
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2411228207
Short name T267
Test name
Test status
Simulation time 49074083013 ps
CPU time 11.4 seconds
Started Jul 20 05:46:12 PM PDT 24
Finished Jul 20 05:46:27 PM PDT 24
Peak memory 191572 kb
Host smart-6b89a6ca-72d8-47eb-8718-e6b72466924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411228207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2411228207
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.928488278
Short name T47
Test name
Test status
Simulation time 525241242 ps
CPU time 1.3 seconds
Started Jul 20 05:46:00 PM PDT 24
Finished Jul 20 05:46:07 PM PDT 24
Peak memory 191328 kb
Host smart-afdfa2c6-a1db-45ee-bbe6-31dc088f963c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928488278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.928488278
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_jump.49989781
Short name T189
Test name
Test status
Simulation time 451968462 ps
CPU time 1.29 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:46:13 PM PDT 24
Peak memory 196216 kb
Host smart-a91b603e-e1e7-4509-8956-eb8cdb4b52fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49989781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.49989781
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3583675453
Short name T210
Test name
Test status
Simulation time 10852144056 ps
CPU time 7.55 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:14 PM PDT 24
Peak memory 191524 kb
Host smart-b8091903-1762-4284-889e-9b57b08855b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583675453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3583675453
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.232697738
Short name T6
Test name
Test status
Simulation time 363399697 ps
CPU time 0.71 seconds
Started Jul 20 05:46:10 PM PDT 24
Finished Jul 20 05:46:15 PM PDT 24
Peak memory 191504 kb
Host smart-a521eb4a-0a16-4288-af73-47f577e1a3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232697738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.232697738
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1036999804
Short name T166
Test name
Test status
Simulation time 54887985346 ps
CPU time 21.29 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:27 PM PDT 24
Peak memory 191556 kb
Host smart-a658902f-6078-40b1-88ee-dab466aecf5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036999804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1036999804
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3976059389
Short name T213
Test name
Test status
Simulation time 53479827136 ps
CPU time 83.52 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:47:23 PM PDT 24
Peak memory 196536 kb
Host smart-b28939fb-b6af-4d81-8590-15d9d96e57ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976059389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3976059389
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1425756156
Short name T12
Test name
Test status
Simulation time 4540334727 ps
CPU time 7.19 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:18 PM PDT 24
Peak memory 215456 kb
Host smart-2f931d29-ff3d-4f53-97fa-16e82f9dd7d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425756156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1425756156
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.933105193
Short name T237
Test name
Test status
Simulation time 524633875 ps
CPU time 0.87 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:46:01 PM PDT 24
Peak memory 196340 kb
Host smart-2b5008ec-a867-421d-9d26-58ed7ef5468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933105193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.933105193
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4100810774
Short name T168
Test name
Test status
Simulation time 412743960 ps
CPU time 0.74 seconds
Started Jul 20 05:46:23 PM PDT 24
Finished Jul 20 05:46:24 PM PDT 24
Peak memory 196292 kb
Host smart-2698d791-b5bd-436a-93f0-44cc85e64afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100810774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4100810774
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1588115847
Short name T9
Test name
Test status
Simulation time 28953300403 ps
CPU time 11.28 seconds
Started Jul 20 05:46:05 PM PDT 24
Finished Jul 20 05:46:24 PM PDT 24
Peak memory 191560 kb
Host smart-7b1f5c21-2f6e-4513-aea6-6a396c190eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588115847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1588115847
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3509765584
Short name T23
Test name
Test status
Simulation time 472917914 ps
CPU time 0.77 seconds
Started Jul 20 05:46:03 PM PDT 24
Finished Jul 20 05:46:11 PM PDT 24
Peak memory 196340 kb
Host smart-b9ed740f-c51a-4981-a6b6-8d161f1d2589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509765584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3509765584
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3237016523
Short name T221
Test name
Test status
Simulation time 34212579382 ps
CPU time 12.45 seconds
Started Jul 20 05:46:11 PM PDT 24
Finished Jul 20 05:46:27 PM PDT 24
Peak memory 196584 kb
Host smart-5fdb7ed4-7d2b-4141-ab9d-777c368d11e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237016523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3237016523
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4174305552
Short name T256
Test name
Test status
Simulation time 416509638 ps
CPU time 1.22 seconds
Started Jul 20 05:45:59 PM PDT 24
Finished Jul 20 05:46:05 PM PDT 24
Peak memory 196332 kb
Host smart-ec7f47ce-c7af-495f-9326-317f2d8971e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174305552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4174305552
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2635825575
Short name T206
Test name
Test status
Simulation time 15488433594 ps
CPU time 11.1 seconds
Started Jul 20 05:46:15 PM PDT 24
Finished Jul 20 05:46:28 PM PDT 24
Peak memory 191512 kb
Host smart-1041ea59-c222-4802-a6e5-e84bc5d137a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635825575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2635825575
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1077018657
Short name T268
Test name
Test status
Simulation time 409110056 ps
CPU time 0.74 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:46:13 PM PDT 24
Peak memory 191512 kb
Host smart-5c4ccd1a-4628-4b5b-9064-ac78c5320287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077018657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1077018657
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1991329886
Short name T252
Test name
Test status
Simulation time 44551569639 ps
CPU time 70.37 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:47:18 PM PDT 24
Peak memory 191560 kb
Host smart-76d488c4-b43a-448a-8359-0aff9c818247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991329886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1991329886
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2178414458
Short name T37
Test name
Test status
Simulation time 522484875 ps
CPU time 0.9 seconds
Started Jul 20 05:46:02 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 191444 kb
Host smart-266e03c6-787f-479c-8fc8-b635db0d3710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178414458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2178414458
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2221881569
Short name T40
Test name
Test status
Simulation time 28219968444 ps
CPU time 4.3 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:12 PM PDT 24
Peak memory 191484 kb
Host smart-dc526d79-9bc3-40ef-8811-90ca1b13c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221881569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2221881569
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1347891860
Short name T236
Test name
Test status
Simulation time 430316293 ps
CPU time 0.91 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:09 PM PDT 24
Peak memory 191544 kb
Host smart-fc09ceb3-7276-47cc-8519-ffda4b36e203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347891860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1347891860
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2630824036
Short name T251
Test name
Test status
Simulation time 2334779492 ps
CPU time 2.23 seconds
Started Jul 20 05:46:17 PM PDT 24
Finished Jul 20 05:46:20 PM PDT 24
Peak memory 191524 kb
Host smart-2de62f98-1c7a-4637-ae46-fe0403a56478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630824036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2630824036
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.113701407
Short name T238
Test name
Test status
Simulation time 561654706 ps
CPU time 1.02 seconds
Started Jul 20 05:46:07 PM PDT 24
Finished Jul 20 05:46:14 PM PDT 24
Peak memory 191448 kb
Host smart-7358f614-205e-4a8f-93d1-d8faaa2dfdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113701407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.113701407
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3933765276
Short name T241
Test name
Test status
Simulation time 42508221299 ps
CPU time 13.99 seconds
Started Jul 20 05:46:09 PM PDT 24
Finished Jul 20 05:46:28 PM PDT 24
Peak memory 191560 kb
Host smart-1726ccb0-1c8f-47fc-bbb9-8f1f84847a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933765276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3933765276
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2540033402
Short name T235
Test name
Test status
Simulation time 520085564 ps
CPU time 0.97 seconds
Started Jul 20 05:46:10 PM PDT 24
Finished Jul 20 05:46:16 PM PDT 24
Peak memory 191440 kb
Host smart-bf2e5e23-df2c-4240-8e58-b77c82cada25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540033402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2540033402
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.7172202
Short name T223
Test name
Test status
Simulation time 35054888132 ps
CPU time 24.38 seconds
Started Jul 20 05:46:21 PM PDT 24
Finished Jul 20 05:46:46 PM PDT 24
Peak memory 196568 kb
Host smart-e34230af-45cf-4c50-b154-8d2932850b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7172202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.7172202
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2150019566
Short name T156
Test name
Test status
Simulation time 493883106 ps
CPU time 1.39 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:46:16 PM PDT 24
Peak memory 191500 kb
Host smart-82dff85b-f5da-44c8-aa2c-c7c9231e44af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150019566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2150019566
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2353814500
Short name T248
Test name
Test status
Simulation time 1687854750 ps
CPU time 1.74 seconds
Started Jul 20 05:46:24 PM PDT 24
Finished Jul 20 05:46:26 PM PDT 24
Peak memory 196216 kb
Host smart-97632cb7-7470-4ae2-b3df-cc107db65879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353814500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2353814500
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.905343005
Short name T264
Test name
Test status
Simulation time 466130020 ps
CPU time 0.76 seconds
Started Jul 20 05:46:19 PM PDT 24
Finished Jul 20 05:46:21 PM PDT 24
Peak memory 196308 kb
Host smart-92227f3a-b670-4b0c-a51f-33b93069eef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905343005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.905343005
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3881561447
Short name T199
Test name
Test status
Simulation time 40134788020 ps
CPU time 7.84 seconds
Started Jul 20 05:46:24 PM PDT 24
Finished Jul 20 05:46:33 PM PDT 24
Peak memory 191576 kb
Host smart-10721b28-0232-47d4-97a2-f6d16bc7309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881561447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3881561447
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1724070082
Short name T266
Test name
Test status
Simulation time 471443380 ps
CPU time 1.3 seconds
Started Jul 20 05:46:24 PM PDT 24
Finished Jul 20 05:46:26 PM PDT 24
Peak memory 191540 kb
Host smart-49c9d5ff-d449-4111-ab15-f8e65ed47d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724070082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1724070082
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3219132371
Short name T278
Test name
Test status
Simulation time 16492920479 ps
CPU time 21.45 seconds
Started Jul 20 05:46:04 PM PDT 24
Finished Jul 20 05:46:34 PM PDT 24
Peak memory 191508 kb
Host smart-b60b669a-c922-4b6c-8d27-fca854501ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219132371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3219132371
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1683948083
Short name T13
Test name
Test status
Simulation time 8268948214 ps
CPU time 3.54 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:50 PM PDT 24
Peak memory 215540 kb
Host smart-ad7d2cc6-327f-4dd5-8c24-380562b20006
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683948083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1683948083
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2142598103
Short name T243
Test name
Test status
Simulation time 511730585 ps
CPU time 0.67 seconds
Started Jul 20 05:46:05 PM PDT 24
Finished Jul 20 05:46:13 PM PDT 24
Peak memory 191368 kb
Host smart-5a26db49-5e05-458d-b1eb-1bf488461504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142598103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2142598103
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2492722587
Short name T204
Test name
Test status
Simulation time 55295839548 ps
CPU time 36.58 seconds
Started Jul 20 05:46:20 PM PDT 24
Finished Jul 20 05:46:57 PM PDT 24
Peak memory 191544 kb
Host smart-5745360f-51f5-4afe-b7ac-bd5cbd7768b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492722587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2492722587
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.188363238
Short name T271
Test name
Test status
Simulation time 378408865 ps
CPU time 0.75 seconds
Started Jul 20 05:46:22 PM PDT 24
Finished Jul 20 05:46:23 PM PDT 24
Peak memory 191504 kb
Host smart-28fb40e9-ba07-49cb-93a8-07bdf9dbd917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188363238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.188363238
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.4040417815
Short name T227
Test name
Test status
Simulation time 11870081658 ps
CPU time 8.41 seconds
Started Jul 20 05:46:28 PM PDT 24
Finished Jul 20 05:46:39 PM PDT 24
Peak memory 191560 kb
Host smart-17765ab5-fabc-482a-bcbc-76a4a3922193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040417815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.4040417815
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2744600208
Short name T255
Test name
Test status
Simulation time 381992238 ps
CPU time 0.7 seconds
Started Jul 20 05:46:33 PM PDT 24
Finished Jul 20 05:46:35 PM PDT 24
Peak memory 191488 kb
Host smart-071deba3-3581-4499-be9b-c08343e6f976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744600208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2744600208
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2809655607
Short name T192
Test name
Test status
Simulation time 512133360 ps
CPU time 0.66 seconds
Started Jul 20 05:46:27 PM PDT 24
Finished Jul 20 05:46:30 PM PDT 24
Peak memory 196356 kb
Host smart-4673eddd-1bcb-4bcf-8c39-b9c51a4c673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809655607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2809655607
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1213320570
Short name T25
Test name
Test status
Simulation time 25289632645 ps
CPU time 9.56 seconds
Started Jul 20 05:46:26 PM PDT 24
Finished Jul 20 05:46:37 PM PDT 24
Peak memory 191564 kb
Host smart-e5771689-a314-44c5-9e34-fe315bb4acd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213320570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1213320570
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2543177679
Short name T225
Test name
Test status
Simulation time 531509088 ps
CPU time 1.01 seconds
Started Jul 20 05:46:35 PM PDT 24
Finished Jul 20 05:46:38 PM PDT 24
Peak memory 191452 kb
Host smart-032817db-7772-4170-9c7d-48c4b0b1b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543177679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2543177679
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1309245282
Short name T148
Test name
Test status
Simulation time 418524430 ps
CPU time 1.12 seconds
Started Jul 20 05:46:29 PM PDT 24
Finished Jul 20 05:46:33 PM PDT 24
Peak memory 196360 kb
Host smart-69540604-c0c0-4d45-960b-e456477b2038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309245282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1309245282
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2063266515
Short name T205
Test name
Test status
Simulation time 37290469246 ps
CPU time 13.39 seconds
Started Jul 20 05:46:32 PM PDT 24
Finished Jul 20 05:46:47 PM PDT 24
Peak memory 191564 kb
Host smart-e5f0c308-1c66-41a0-b264-aa8bc229fb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063266515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2063266515
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1500522895
Short name T208
Test name
Test status
Simulation time 482798594 ps
CPU time 0.92 seconds
Started Jul 20 05:46:26 PM PDT 24
Finished Jul 20 05:46:29 PM PDT 24
Peak memory 191628 kb
Host smart-604454fc-f50d-4156-be59-01d015d33b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500522895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1500522895
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1325277655
Short name T212
Test name
Test status
Simulation time 5603619150 ps
CPU time 1.64 seconds
Started Jul 20 05:46:29 PM PDT 24
Finished Jul 20 05:46:33 PM PDT 24
Peak memory 191564 kb
Host smart-4f2b4627-9307-4ad2-b427-1301743ce80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325277655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1325277655
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3090744206
Short name T240
Test name
Test status
Simulation time 557631187 ps
CPU time 1.39 seconds
Started Jul 20 05:46:26 PM PDT 24
Finished Jul 20 05:46:29 PM PDT 24
Peak memory 196324 kb
Host smart-baf98b26-d901-4f76-9aee-9e242b53a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090744206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3090744206
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3671438790
Short name T48
Test name
Test status
Simulation time 35530004443 ps
CPU time 22.92 seconds
Started Jul 20 05:46:36 PM PDT 24
Finished Jul 20 05:47:01 PM PDT 24
Peak memory 196572 kb
Host smart-2d51a139-a040-4d6e-9cd7-3b3d0f22f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671438790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3671438790
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.360652966
Short name T203
Test name
Test status
Simulation time 350026525 ps
CPU time 0.83 seconds
Started Jul 20 05:46:30 PM PDT 24
Finished Jul 20 05:46:33 PM PDT 24
Peak memory 191452 kb
Host smart-8842ad35-13e5-4b07-98cd-04d56b90921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360652966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.360652966
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1098040537
Short name T274
Test name
Test status
Simulation time 51041496613 ps
CPU time 75.19 seconds
Started Jul 20 05:46:27 PM PDT 24
Finished Jul 20 05:47:45 PM PDT 24
Peak memory 196576 kb
Host smart-05d87b93-bf5a-46fa-a61f-cffd8f6f436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098040537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1098040537
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3355842558
Short name T79
Test name
Test status
Simulation time 542288382 ps
CPU time 1.38 seconds
Started Jul 20 05:46:36 PM PDT 24
Finished Jul 20 05:46:39 PM PDT 24
Peak memory 191504 kb
Host smart-91d18173-186a-4510-84a6-aaed2ff92445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355842558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3355842558
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1143394457
Short name T7
Test name
Test status
Simulation time 8343832783 ps
CPU time 10.89 seconds
Started Jul 20 05:46:33 PM PDT 24
Finished Jul 20 05:46:45 PM PDT 24
Peak memory 191560 kb
Host smart-dc03be07-31f1-487d-a5e5-6e79dbfcded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143394457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1143394457
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2191379886
Short name T218
Test name
Test status
Simulation time 570998570 ps
CPU time 1.01 seconds
Started Jul 20 05:46:24 PM PDT 24
Finished Jul 20 05:46:26 PM PDT 24
Peak memory 191492 kb
Host smart-25f7d9f9-85b2-4198-a84a-9dc81229e8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191379886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2191379886
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2402507186
Short name T89
Test name
Test status
Simulation time 459743351377 ps
CPU time 228.12 seconds
Started Jul 20 05:46:29 PM PDT 24
Finished Jul 20 05:50:19 PM PDT 24
Peak memory 208492 kb
Host smart-14d4c1a8-6a9d-4cbe-9b6c-f6d5d0a40342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402507186 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2402507186
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3888420728
Short name T216
Test name
Test status
Simulation time 38278652027 ps
CPU time 5.32 seconds
Started Jul 20 05:46:26 PM PDT 24
Finished Jul 20 05:46:33 PM PDT 24
Peak memory 196516 kb
Host smart-cd5d5964-7e3d-4469-b87a-7e0c6ecaecb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888420728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3888420728
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1886662346
Short name T202
Test name
Test status
Simulation time 368083235 ps
CPU time 1.12 seconds
Started Jul 20 05:46:27 PM PDT 24
Finished Jul 20 05:46:30 PM PDT 24
Peak memory 191504 kb
Host smart-09555cb1-09fa-4069-be1f-9cd9c964498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886662346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1886662346
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2693674002
Short name T239
Test name
Test status
Simulation time 55631877576 ps
CPU time 46.91 seconds
Started Jul 20 05:46:34 PM PDT 24
Finished Jul 20 05:47:22 PM PDT 24
Peak memory 191552 kb
Host smart-f0932567-edfd-4d4d-8518-e8b44a1d6f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693674002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2693674002
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4204458443
Short name T275
Test name
Test status
Simulation time 350688893 ps
CPU time 0.82 seconds
Started Jul 20 05:46:31 PM PDT 24
Finished Jul 20 05:46:34 PM PDT 24
Peak memory 191492 kb
Host smart-c30a1c6b-9e7a-48d9-94c2-133478116fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204458443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4204458443
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3289835755
Short name T258
Test name
Test status
Simulation time 47577910820 ps
CPU time 30.24 seconds
Started Jul 20 05:45:48 PM PDT 24
Finished Jul 20 05:46:23 PM PDT 24
Peak memory 196560 kb
Host smart-0eef40fa-df36-4557-a346-b1483a196f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289835755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3289835755
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2327931667
Short name T231
Test name
Test status
Simulation time 523432186 ps
CPU time 0.86 seconds
Started Jul 20 05:45:58 PM PDT 24
Finished Jul 20 05:46:01 PM PDT 24
Peak memory 191492 kb
Host smart-751e04cd-372a-4ca5-a7d0-f3d2c2658157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327931667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2327931667
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.263561877
Short name T273
Test name
Test status
Simulation time 46154994435 ps
CPU time 59.65 seconds
Started Jul 20 05:46:07 PM PDT 24
Finished Jul 20 05:47:13 PM PDT 24
Peak memory 196512 kb
Host smart-7e1f5b88-2f73-42f7-9e4a-59e9fe46f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263561877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.263561877
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2079736700
Short name T269
Test name
Test status
Simulation time 489648069 ps
CPU time 0.66 seconds
Started Jul 20 05:45:52 PM PDT 24
Finished Jul 20 05:45:57 PM PDT 24
Peak memory 191512 kb
Host smart-dd896fd5-f1aa-424d-92e9-4e3a1c501cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079736700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2079736700
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3435372218
Short name T259
Test name
Test status
Simulation time 20649678169 ps
CPU time 14.72 seconds
Started Jul 20 05:46:01 PM PDT 24
Finished Jul 20 05:46:23 PM PDT 24
Peak memory 191504 kb
Host smart-ed2f4d10-eb27-419e-b413-0246a3ac52bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435372218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3435372218
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2380362876
Short name T81
Test name
Test status
Simulation time 489170528 ps
CPU time 0.93 seconds
Started Jul 20 05:46:07 PM PDT 24
Finished Jul 20 05:46:15 PM PDT 24
Peak memory 196352 kb
Host smart-06cf40c7-dd38-4b42-adde-c964beca0632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380362876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2380362876
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1381512932
Short name T209
Test name
Test status
Simulation time 22786459394 ps
CPU time 2.1 seconds
Started Jul 20 05:46:15 PM PDT 24
Finished Jul 20 05:46:19 PM PDT 24
Peak memory 191544 kb
Host smart-27ff7f2e-aefc-4d07-81ee-aad8da1aebcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381512932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1381512932
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.625794659
Short name T260
Test name
Test status
Simulation time 475232681 ps
CPU time 1.3 seconds
Started Jul 20 05:46:07 PM PDT 24
Finished Jul 20 05:46:15 PM PDT 24
Peak memory 191432 kb
Host smart-6c9c5723-db66-4fba-a704-bed7ac26acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625794659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.625794659
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.961248719
Short name T262
Test name
Test status
Simulation time 18234349113 ps
CPU time 14.89 seconds
Started Jul 20 05:45:54 PM PDT 24
Finished Jul 20 05:46:13 PM PDT 24
Peak memory 196568 kb
Host smart-e6ffa2e5-f09a-4a55-b2a2-4bd2d04a6279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961248719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.961248719
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2729626971
Short name T214
Test name
Test status
Simulation time 470729974 ps
CPU time 1.3 seconds
Started Jul 20 05:46:17 PM PDT 24
Finished Jul 20 05:46:19 PM PDT 24
Peak memory 191476 kb
Host smart-6ce8b624-7d5a-4619-ab6e-6fa4f893da99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729626971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2729626971
Directory /workspace/9.aon_timer_smoke/latest
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