Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 28751 1 T1 10 T2 11 T3 304
bark[1] 356 1 T40 14 T95 21 T25 69
bark[2] 84 1 T3 21 T178 14 T148 14
bark[3] 336 1 T7 165 T33 68 T20 21
bark[4] 399 1 T5 21 T95 21 T26 21
bark[5] 1002 1 T3 179 T45 14 T78 21
bark[6] 570 1 T6 14 T8 21 T143 28
bark[7] 131 1 T7 5 T89 21 T141 21
bark[8] 387 1 T12 21 T39 39 T33 21
bark[9] 864 1 T7 21 T44 35 T143 112
bark[10] 1003 1 T3 103 T12 35 T18 21
bark[11] 227 1 T22 14 T172 14 T131 21
bark[12] 364 1 T8 59 T25 40 T99 21
bark[13] 886 1 T34 69 T36 21 T37 5
bark[14] 777 1 T8 21 T39 21 T33 21
bark[15] 151 1 T151 26 T112 26 T86 85
bark[16] 328 1 T5 21 T7 30 T34 21
bark[17] 634 1 T3 83 T8 14 T39 35
bark[18] 221 1 T5 21 T10 26 T95 21
bark[19] 249 1 T39 21 T153 14 T26 21
bark[20] 507 1 T12 163 T43 14 T19 26
bark[21] 290 1 T41 21 T131 51 T81 21
bark[22] 437 1 T7 39 T134 30 T20 21
bark[23] 600 1 T4 26 T8 21 T10 26
bark[24] 455 1 T7 64 T145 55 T180 14
bark[25] 1054 1 T134 26 T184 14 T77 42
bark[26] 778 1 T12 43 T34 278 T143 26
bark[27] 468 1 T6 42 T33 44 T95 30
bark[28] 825 1 T83 232 T26 21 T84 21
bark[29] 185 1 T4 60 T134 19 T136 44
bark[30] 974 1 T3 534 T4 21 T37 77
bark[31] 387 1 T145 21 T26 56 T84 21
bark_0 4586 1 T1 7 T2 7 T3 84


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 28388 1 T1 9 T2 10 T3 300
bite[1] 376 1 T8 13 T95 21 T88 153
bite[2] 484 1 T4 59 T5 21 T20 21
bite[3] 693 1 T39 35 T33 21 T37 4
bite[4] 316 1 T3 102 T8 21 T39 21
bite[5] 1161 1 T3 533 T7 39 T36 48
bite[6] 588 1 T7 30 T8 21 T39 21
bite[7] 514 1 T3 21 T43 13 T18 21
bite[8] 314 1 T12 21 T45 13 T36 21
bite[9] 500 1 T4 21 T95 21 T38 21
bite[10] 604 1 T7 21 T8 21 T10 26
bite[11] 1094 1 T84 21 T78 288 T118 21
bite[12] 1872 1 T6 13 T7 164 T33 43
bite[13] 159 1 T84 21 T110 35 T90 21
bite[14] 215 1 T40 13 T20 21 T26 21
bite[15] 320 1 T95 30 T134 30 T22 13
bite[16] 970 1 T3 82 T18 300 T114 21
bite[17] 548 1 T5 21 T6 21 T145 21
bite[18] 162 1 T19 26 T26 21 T166 13
bite[19] 349 1 T12 162 T153 13 T35 13
bite[20] 387 1 T134 18 T18 21 T24 13
bite[21] 233 1 T126 42 T118 62 T133 21
bite[22] 199 1 T41 21 T20 21 T25 68
bite[23] 810 1 T4 25 T10 69 T151 21
bite[24] 438 1 T8 80 T131 21 T147 145
bite[25] 707 1 T3 178 T5 21 T83 293
bite[26] 361 1 T7 42 T36 21 T83 179
bite[27] 301 1 T12 42 T143 27 T18 21
bite[28] 235 1 T6 21 T10 26 T37 76
bite[29] 492 1 T7 4 T44 35 T33 67
bite[30] 235 1 T143 26 T123 13 T131 21
bite[31] 165 1 T7 21 T25 40 T131 61
bite_0 5076 1 T1 8 T2 8 T3 92


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 41022 1 T1 17 T2 18 T3 760
auto[1] 8244 1 T3 548 T4 303 T5 157


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1176 1 T7 120 T12 19 T143 23
prescale[1] 871 1 T3 94 T4 131 T7 19
prescale[2] 941 1 T3 19 T7 26 T12 19
prescale[3] 739 1 T3 19 T34 98 T36 19
prescale[4] 673 1 T3 53 T7 46 T10 45
prescale[5] 816 1 T3 36 T4 97 T5 19
prescale[6] 781 1 T10 24 T44 28 T36 9
prescale[7] 783 1 T12 19 T36 2 T37 19
prescale[8] 419 1 T3 2 T4 28 T7 40
prescale[9] 874 1 T3 97 T7 78 T10 23
prescale[10] 1170 1 T4 2 T7 70 T34 41
prescale[11] 567 1 T3 2 T44 51 T36 19
prescale[12] 703 1 T6 19 T7 19 T33 38
prescale[13] 717 1 T3 66 T6 19 T7 132
prescale[14] 1012 1 T7 121 T33 167 T34 2
prescale[15] 480 1 T3 2 T44 19 T38 19
prescale[16] 596 1 T34 23 T36 19 T95 19
prescale[17] 1269 1 T7 28 T41 45 T36 36
prescale[18] 894 1 T6 57 T7 9 T12 19
prescale[19] 559 1 T4 9 T5 40 T8 23
prescale[20] 703 1 T3 21 T6 40 T7 19
prescale[21] 498 1 T3 19 T7 19 T39 46
prescale[22] 685 1 T3 59 T7 2 T12 17
prescale[23] 683 1 T7 19 T12 42 T47 9
prescale[24] 896 1 T3 62 T41 9 T145 57
prescale[25] 588 1 T4 2 T7 4 T12 2
prescale[26] 660 1 T4 2 T7 38 T12 36
prescale[27] 545 1 T4 2 T6 45 T11 9
prescale[28] 700 1 T3 41 T12 2 T35 2
prescale[29] 619 1 T3 177 T5 19 T34 2
prescale[30] 1068 1 T5 93 T7 19 T41 19
prescale[31] 581 1 T3 2 T7 147 T12 2
prescale_0 25000 1 T1 17 T2 18 T3 537


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 37044 1 T1 17 T2 9 T3 1172
auto[1] 12222 1 T2 9 T3 136 T4 90


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 49266 1 T1 17 T2 18 T3 1308


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 28822 1 T1 12 T2 13 T3 695
wkup[1] 178 1 T7 6 T8 21 T33 21
wkup[2] 228 1 T36 21 T145 21 T20 21
wkup[3] 222 1 T7 21 T84 21 T85 21
wkup[4] 305 1 T3 21 T7 21 T33 21
wkup[5] 270 1 T3 34 T33 30 T38 21
wkup[6] 291 1 T3 21 T7 21 T39 21
wkup[7] 367 1 T3 21 T34 30 T36 26
wkup[8] 273 1 T3 21 T18 21 T19 21
wkup[9] 268 1 T3 21 T34 26 T83 26
wkup[10] 227 1 T7 21 T34 21 T121 30
wkup[11] 396 1 T4 31 T7 39 T83 21
wkup[12] 331 1 T5 21 T45 15 T134 30
wkup[13] 254 1 T7 21 T38 21 T18 30
wkup[14] 330 1 T4 21 T36 26 T134 21
wkup[15] 255 1 T7 21 T12 21 T141 21
wkup[16] 180 1 T34 31 T25 6 T26 21
wkup[17] 294 1 T3 60 T7 42 T37 21
wkup[18] 217 1 T8 15 T41 26 T33 21
wkup[19] 291 1 T8 21 T39 21 T40 15
wkup[20] 225 1 T10 26 T12 21 T83 21
wkup[21] 231 1 T7 21 T8 21 T26 21
wkup[22] 202 1 T3 21 T134 21 T170 15
wkup[23] 322 1 T8 21 T95 21 T85 21
wkup[24] 194 1 T8 21 T83 21 T18 42
wkup[25] 145 1 T84 21 T80 21 T81 56
wkup[26] 153 1 T4 21 T7 21 T12 30
wkup[27] 277 1 T12 21 T145 21 T83 42
wkup[28] 242 1 T43 15 T20 21 T126 21
wkup[29] 248 1 T7 21 T44 35 T33 21
wkup[30] 383 1 T3 21 T7 51 T10 30
wkup[31] 314 1 T7 21 T143 21 T36 21
wkup[32] 243 1 T3 42 T7 21 T39 35
wkup[33] 261 1 T18 42 T85 42 T112 21
wkup[34] 697 1 T5 21 T7 26 T10 26
wkup[35] 185 1 T3 30 T7 21 T34 21
wkup[36] 127 1 T10 26 T84 24 T147 21
wkup[37] 395 1 T3 26 T7 21 T44 35
wkup[38] 222 1 T35 15 T93 15 T112 21
wkup[39] 359 1 T6 21 T34 21 T36 69
wkup[40] 280 1 T4 21 T7 21 T10 26
wkup[41] 355 1 T7 21 T33 26 T36 21
wkup[42] 341 1 T7 30 T33 21 T38 15
wkup[43] 253 1 T3 63 T7 21 T18 15
wkup[44] 296 1 T34 21 T121 21 T169 21
wkup[45] 367 1 T3 21 T6 21 T7 15
wkup[46] 84 1 T3 21 T83 21 T84 21
wkup[47] 191 1 T37 30 T134 21 T22 15
wkup[48] 316 1 T4 21 T7 29 T39 39
wkup[49] 214 1 T4 21 T5 21 T8 21
wkup[50] 317 1 T153 15 T143 26 T83 21
wkup[51] 262 1 T6 21 T7 21 T83 21
wkup[52] 313 1 T36 21 T95 21 T131 21
wkup[53] 224 1 T7 21 T36 21 T78 21
wkup[54] 273 1 T12 21 T83 21 T77 21
wkup[55] 211 1 T7 21 T34 15 T25 21
wkup[56] 230 1 T3 38 T5 21 T34 21
wkup[57] 237 1 T8 21 T34 21 T36 26
wkup[58] 304 1 T12 21 T44 21 T38 43
wkup[59] 269 1 T3 21 T6 15 T12 21
wkup[60] 157 1 T36 21 T20 21 T78 21
wkup[61] 253 1 T4 21 T44 15 T83 21
wkup[62] 214 1 T3 21 T34 8 T95 30
wkup[63] 272 1 T3 21 T5 21 T78 21
wkup_0 3609 1 T1 5 T2 5 T3 68

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