Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 2 0 2 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 8 0 8 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 3519 1 T1 3 T2 3 T3 46
all_pins[1] 3519 1 T1 3 T2 3 T3 46



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 4997 1 T1 5 T2 3 T3 64
values[0x1] 2041 1 T1 1 T2 3 T3 28
transitions[0x0=>0x1] 1655 1 T1 1 T2 1 T3 24
transitions[0x1=>0x0] 1606 1 T1 1 T3 24 T4 6



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 2960 1 T1 3 T2 1 T3 40
all_pins[0] values[0x1] 559 1 T2 2 T3 6 T4 3
all_pins[0] transitions[0x0=>0x1] 304 1 T2 1 T3 3 T4 2
all_pins[0] transitions[0x1=>0x0] 1227 1 T1 1 T3 19 T4 4
all_pins[1] values[0x0] 2037 1 T1 2 T2 2 T3 24
all_pins[1] values[0x1] 1482 1 T1 1 T2 1 T3 22
all_pins[1] transitions[0x0=>0x1] 1351 1 T1 1 T3 21 T4 4
all_pins[1] transitions[0x1=>0x0] 379 1 T3 5 T4 2 T5 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%