Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.03 99.33 93.67 100.00 98.40 99.51 49.28


Total test records in report: 422
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T32 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.700271728 Jul 21 05:35:33 PM PDT 24 Jul 21 05:35:39 PM PDT 24 7315194557 ps
T285 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.111411059 Jul 21 05:36:09 PM PDT 24 Jul 21 05:36:10 PM PDT 24 268051351 ps
T286 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3246216359 Jul 21 05:36:08 PM PDT 24 Jul 21 05:36:10 PM PDT 24 319843184 ps
T287 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3421226173 Jul 21 05:35:27 PM PDT 24 Jul 21 05:35:29 PM PDT 24 397418313 ps
T288 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3297986908 Jul 21 05:36:17 PM PDT 24 Jul 21 05:36:18 PM PDT 24 397914575 ps
T289 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1907086180 Jul 21 05:36:07 PM PDT 24 Jul 21 05:36:08 PM PDT 24 397519736 ps
T51 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3977147122 Jul 21 05:35:50 PM PDT 24 Jul 21 05:35:52 PM PDT 24 451349158 ps
T28 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1029644650 Jul 21 05:35:59 PM PDT 24 Jul 21 05:36:00 PM PDT 24 841066575 ps
T290 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2406178466 Jul 21 05:35:35 PM PDT 24 Jul 21 05:35:36 PM PDT 24 525884900 ps
T194 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.428802839 Jul 21 05:35:37 PM PDT 24 Jul 21 05:36:11 PM PDT 24 13747785692 ps
T291 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.206614216 Jul 21 05:35:45 PM PDT 24 Jul 21 05:35:46 PM PDT 24 351708061 ps
T29 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.484485234 Jul 21 05:35:59 PM PDT 24 Jul 21 05:36:07 PM PDT 24 4498628877 ps
T292 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1081804637 Jul 21 05:36:05 PM PDT 24 Jul 21 05:36:07 PM PDT 24 315610255 ps
T293 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3070345000 Jul 21 05:36:02 PM PDT 24 Jul 21 05:36:03 PM PDT 24 270287362 ps
T52 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1237363271 Jul 21 05:35:34 PM PDT 24 Jul 21 05:35:36 PM PDT 24 480594349 ps
T294 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.955952005 Jul 21 05:35:56 PM PDT 24 Jul 21 05:35:57 PM PDT 24 329234954 ps
T295 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2053332437 Jul 21 05:36:06 PM PDT 24 Jul 21 05:36:08 PM PDT 24 266263656 ps
T30 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.175739061 Jul 21 05:35:54 PM PDT 24 Jul 21 05:35:58 PM PDT 24 7907188033 ps
T191 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2734035603 Jul 21 05:35:47 PM PDT 24 Jul 21 05:35:52 PM PDT 24 8802218205 ps
T296 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3614025701 Jul 21 05:36:09 PM PDT 24 Jul 21 05:36:10 PM PDT 24 361506591 ps
T297 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.126684989 Jul 21 05:36:00 PM PDT 24 Jul 21 05:36:01 PM PDT 24 481146638 ps
T298 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1111448217 Jul 21 05:35:51 PM PDT 24 Jul 21 05:35:53 PM PDT 24 475686568 ps
T299 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.495166285 Jul 21 05:36:10 PM PDT 24 Jul 21 05:36:11 PM PDT 24 489474668 ps
T53 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2757373843 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:03 PM PDT 24 556903629 ps
T300 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.575112271 Jul 21 05:35:41 PM PDT 24 Jul 21 05:35:54 PM PDT 24 7880913143 ps
T68 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2437057645 Jul 21 05:35:35 PM PDT 24 Jul 21 05:35:37 PM PDT 24 1013488955 ps
T301 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2055985610 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:02 PM PDT 24 559160200 ps
T302 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1653920071 Jul 21 05:35:49 PM PDT 24 Jul 21 05:35:52 PM PDT 24 308717227 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2359166943 Jul 21 05:35:36 PM PDT 24 Jul 21 05:35:37 PM PDT 24 798227954 ps
T304 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.750762898 Jul 21 05:35:33 PM PDT 24 Jul 21 05:35:36 PM PDT 24 581235364 ps
T305 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1702861415 Jul 21 05:36:15 PM PDT 24 Jul 21 05:36:17 PM PDT 24 294819961 ps
T306 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.556366237 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:15 PM PDT 24 8317743790 ps
T307 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1917987383 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:05 PM PDT 24 4228574220 ps
T308 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.678454023 Jul 21 05:35:49 PM PDT 24 Jul 21 05:35:51 PM PDT 24 409205476 ps
T309 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.963106215 Jul 21 05:35:48 PM PDT 24 Jul 21 05:35:50 PM PDT 24 381502302 ps
T310 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1289366831 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:03 PM PDT 24 470560340 ps
T311 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3126210444 Jul 21 05:35:55 PM PDT 24 Jul 21 05:35:57 PM PDT 24 370275238 ps
T312 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.20671996 Jul 21 05:35:28 PM PDT 24 Jul 21 05:35:29 PM PDT 24 396883275 ps
T313 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1629460249 Jul 21 05:35:41 PM PDT 24 Jul 21 05:35:42 PM PDT 24 518639198 ps
T314 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3314151202 Jul 21 05:36:08 PM PDT 24 Jul 21 05:36:09 PM PDT 24 476496347 ps
T315 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4061566976 Jul 21 05:35:29 PM PDT 24 Jul 21 05:35:32 PM PDT 24 996816903 ps
T316 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4031976763 Jul 21 05:35:58 PM PDT 24 Jul 21 05:35:59 PM PDT 24 541389301 ps
T54 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2720239979 Jul 21 05:36:02 PM PDT 24 Jul 21 05:36:04 PM PDT 24 375165455 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2219418132 Jul 21 05:35:38 PM PDT 24 Jul 21 05:35:40 PM PDT 24 397042499 ps
T318 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1078394408 Jul 21 05:36:14 PM PDT 24 Jul 21 05:36:16 PM PDT 24 500803517 ps
T69 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.828113511 Jul 21 05:35:53 PM PDT 24 Jul 21 05:35:56 PM PDT 24 1508206036 ps
T70 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.448924000 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:03 PM PDT 24 1571206063 ps
T319 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.184159720 Jul 21 05:35:58 PM PDT 24 Jul 21 05:36:01 PM PDT 24 633704649 ps
T320 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2390943755 Jul 21 05:35:33 PM PDT 24 Jul 21 05:35:35 PM PDT 24 971786299 ps
T321 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2033874601 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:04 PM PDT 24 441895007 ps
T322 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2107452086 Jul 21 05:35:48 PM PDT 24 Jul 21 05:35:50 PM PDT 24 528474157 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.404522790 Jul 21 05:35:51 PM PDT 24 Jul 21 05:35:52 PM PDT 24 1530503829 ps
T323 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2955547234 Jul 21 05:35:34 PM PDT 24 Jul 21 05:35:37 PM PDT 24 4516137839 ps
T72 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1098620099 Jul 21 05:35:54 PM PDT 24 Jul 21 05:35:56 PM PDT 24 1239523590 ps
T324 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1782935867 Jul 21 05:36:13 PM PDT 24 Jul 21 05:36:15 PM PDT 24 397446435 ps
T325 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4033632760 Jul 21 05:35:41 PM PDT 24 Jul 21 05:35:43 PM PDT 24 350458770 ps
T73 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.159084852 Jul 21 05:35:56 PM PDT 24 Jul 21 05:36:00 PM PDT 24 2011033144 ps
T55 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3441956206 Jul 21 05:35:51 PM PDT 24 Jul 21 05:35:52 PM PDT 24 428432780 ps
T56 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.779320979 Jul 21 05:35:54 PM PDT 24 Jul 21 05:35:56 PM PDT 24 442849813 ps
T74 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2904647117 Jul 21 05:35:31 PM PDT 24 Jul 21 05:35:32 PM PDT 24 345859353 ps
T326 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2384459642 Jul 21 05:35:57 PM PDT 24 Jul 21 05:35:58 PM PDT 24 4938538922 ps
T327 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2848898711 Jul 21 05:35:47 PM PDT 24 Jul 21 05:35:52 PM PDT 24 8248868560 ps
T328 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2954046836 Jul 21 05:35:53 PM PDT 24 Jul 21 05:35:54 PM PDT 24 524017218 ps
T75 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1979761855 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:06 PM PDT 24 2833556315 ps
T329 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.507933156 Jul 21 05:36:09 PM PDT 24 Jul 21 05:36:10 PM PDT 24 315465442 ps
T76 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.947075820 Jul 21 05:35:34 PM PDT 24 Jul 21 05:35:37 PM PDT 24 2726633338 ps
T330 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.4142252053 Jul 21 05:35:50 PM PDT 24 Jul 21 05:36:05 PM PDT 24 8423651403 ps
T331 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1718479970 Jul 21 05:35:41 PM PDT 24 Jul 21 05:35:42 PM PDT 24 457432131 ps
T332 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3490895036 Jul 21 05:36:09 PM PDT 24 Jul 21 05:36:10 PM PDT 24 448629779 ps
T333 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2104662800 Jul 21 05:36:00 PM PDT 24 Jul 21 05:36:04 PM PDT 24 8675563701 ps
T334 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3854742948 Jul 21 05:35:40 PM PDT 24 Jul 21 05:35:41 PM PDT 24 298068932 ps
T335 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.423828016 Jul 21 05:35:54 PM PDT 24 Jul 21 05:35:56 PM PDT 24 355514394 ps
T336 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2309148161 Jul 21 05:35:39 PM PDT 24 Jul 21 05:35:40 PM PDT 24 486651557 ps
T337 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2590945471 Jul 21 05:35:47 PM PDT 24 Jul 21 05:35:50 PM PDT 24 441377811 ps
T338 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.66294494 Jul 21 05:36:11 PM PDT 24 Jul 21 05:36:13 PM PDT 24 472695174 ps
T339 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2482873488 Jul 21 05:35:34 PM PDT 24 Jul 21 05:35:41 PM PDT 24 3807041679 ps
T340 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3653946066 Jul 21 05:36:08 PM PDT 24 Jul 21 05:36:10 PM PDT 24 426320868 ps
T341 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.394326885 Jul 21 05:35:34 PM PDT 24 Jul 21 05:35:35 PM PDT 24 486929031 ps
T57 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2423622372 Jul 21 05:35:48 PM PDT 24 Jul 21 05:35:50 PM PDT 24 520324987 ps
T342 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2188597548 Jul 21 05:35:26 PM PDT 24 Jul 21 05:35:28 PM PDT 24 581141201 ps
T343 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1594186034 Jul 21 05:36:10 PM PDT 24 Jul 21 05:36:11 PM PDT 24 347226655 ps
T344 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4144718276 Jul 21 05:35:49 PM PDT 24 Jul 21 05:35:50 PM PDT 24 830038208 ps
T345 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.312777874 Jul 21 05:35:54 PM PDT 24 Jul 21 05:35:56 PM PDT 24 276428999 ps
T58 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.415369240 Jul 21 05:35:28 PM PDT 24 Jul 21 05:35:30 PM PDT 24 759231829 ps
T346 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.260784510 Jul 21 05:36:07 PM PDT 24 Jul 21 05:36:08 PM PDT 24 391997767 ps
T347 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1127491320 Jul 21 05:35:50 PM PDT 24 Jul 21 05:35:56 PM PDT 24 4222216889 ps
T59 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1025532040 Jul 21 05:35:52 PM PDT 24 Jul 21 05:35:54 PM PDT 24 493329952 ps
T348 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.336646777 Jul 21 05:35:32 PM PDT 24 Jul 21 05:35:33 PM PDT 24 391192799 ps
T349 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3659609428 Jul 21 05:36:11 PM PDT 24 Jul 21 05:36:13 PM PDT 24 415827410 ps
T350 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3983023879 Jul 21 05:35:29 PM PDT 24 Jul 21 05:35:31 PM PDT 24 301379791 ps
T351 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.151083616 Jul 21 05:36:07 PM PDT 24 Jul 21 05:36:08 PM PDT 24 408505355 ps
T352 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1350394677 Jul 21 05:35:55 PM PDT 24 Jul 21 05:35:57 PM PDT 24 480191453 ps
T353 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.473401861 Jul 21 05:35:37 PM PDT 24 Jul 21 05:35:39 PM PDT 24 515445253 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2210131071 Jul 21 05:35:41 PM PDT 24 Jul 21 05:35:43 PM PDT 24 457989707 ps
T355 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1507659368 Jul 21 05:35:46 PM PDT 24 Jul 21 05:35:48 PM PDT 24 1525360629 ps
T356 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2902550089 Jul 21 05:35:47 PM PDT 24 Jul 21 05:35:48 PM PDT 24 309628868 ps
T357 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3849994970 Jul 21 05:36:02 PM PDT 24 Jul 21 05:36:04 PM PDT 24 543149725 ps
T358 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1672761020 Jul 21 05:35:30 PM PDT 24 Jul 21 05:35:37 PM PDT 24 4418895151 ps
T359 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2121947571 Jul 21 05:35:34 PM PDT 24 Jul 21 05:35:35 PM PDT 24 502461792 ps
T360 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2020768454 Jul 21 05:36:00 PM PDT 24 Jul 21 05:36:01 PM PDT 24 331145786 ps
T361 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2417113667 Jul 21 05:36:02 PM PDT 24 Jul 21 05:36:04 PM PDT 24 1173870028 ps
T362 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1333984697 Jul 21 05:35:48 PM PDT 24 Jul 21 05:35:50 PM PDT 24 1557430790 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3029357022 Jul 21 05:35:48 PM PDT 24 Jul 21 05:35:50 PM PDT 24 387086140 ps
T363 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3821904784 Jul 21 05:35:53 PM PDT 24 Jul 21 05:35:54 PM PDT 24 516643783 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1179029878 Jul 21 05:35:35 PM PDT 24 Jul 21 05:35:37 PM PDT 24 575985969 ps
T364 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2159162491 Jul 21 05:35:49 PM PDT 24 Jul 21 05:35:51 PM PDT 24 530710587 ps
T365 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.260070467 Jul 21 05:35:48 PM PDT 24 Jul 21 05:35:50 PM PDT 24 422918758 ps
T366 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1615464257 Jul 21 05:35:49 PM PDT 24 Jul 21 05:35:51 PM PDT 24 459716234 ps
T367 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2892532769 Jul 21 05:35:46 PM PDT 24 Jul 21 05:35:49 PM PDT 24 508848003 ps
T368 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3576857037 Jul 21 05:35:26 PM PDT 24 Jul 21 05:35:29 PM PDT 24 732961681 ps
T369 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3095941681 Jul 21 05:35:53 PM PDT 24 Jul 21 05:35:55 PM PDT 24 411728171 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3698017990 Jul 21 05:35:50 PM PDT 24 Jul 21 05:35:52 PM PDT 24 338384540 ps
T370 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.688793356 Jul 21 05:35:53 PM PDT 24 Jul 21 05:35:56 PM PDT 24 441777584 ps
T371 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1686002493 Jul 21 05:35:58 PM PDT 24 Jul 21 05:35:59 PM PDT 24 307440244 ps
T372 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2374122200 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:03 PM PDT 24 445713963 ps
T373 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2727465122 Jul 21 05:36:15 PM PDT 24 Jul 21 05:36:16 PM PDT 24 443406867 ps
T374 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1081316862 Jul 21 05:35:59 PM PDT 24 Jul 21 05:36:01 PM PDT 24 1520174283 ps
T375 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2491698145 Jul 21 05:35:47 PM PDT 24 Jul 21 05:35:49 PM PDT 24 481486963 ps
T376 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2788930560 Jul 21 05:36:07 PM PDT 24 Jul 21 05:36:08 PM PDT 24 359803462 ps
T377 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.452395926 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:03 PM PDT 24 299210063 ps
T378 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2473476978 Jul 21 05:35:50 PM PDT 24 Jul 21 05:35:52 PM PDT 24 418503903 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1596025321 Jul 21 05:35:37 PM PDT 24 Jul 21 05:35:40 PM PDT 24 580017824 ps
T379 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4271051576 Jul 21 05:35:47 PM PDT 24 Jul 21 05:35:50 PM PDT 24 2853254011 ps
T380 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3477883135 Jul 21 05:35:46 PM PDT 24 Jul 21 05:35:50 PM PDT 24 1279211271 ps
T381 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1127681183 Jul 21 05:35:53 PM PDT 24 Jul 21 05:35:54 PM PDT 24 416476959 ps
T382 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3421954010 Jul 21 05:35:41 PM PDT 24 Jul 21 05:35:43 PM PDT 24 1083450382 ps
T383 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3303415228 Jul 21 05:36:02 PM PDT 24 Jul 21 05:36:04 PM PDT 24 569281544 ps
T65 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1720994149 Jul 21 05:35:35 PM PDT 24 Jul 21 05:35:37 PM PDT 24 409835623 ps
T384 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2651753118 Jul 21 05:35:45 PM PDT 24 Jul 21 05:35:48 PM PDT 24 1069817548 ps
T385 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1492729478 Jul 21 05:35:48 PM PDT 24 Jul 21 05:35:51 PM PDT 24 698387630 ps
T386 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.916539900 Jul 21 05:35:39 PM PDT 24 Jul 21 05:35:41 PM PDT 24 487788777 ps
T387 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3703445203 Jul 21 05:36:14 PM PDT 24 Jul 21 05:36:16 PM PDT 24 418342230 ps
T388 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1172220378 Jul 21 05:35:56 PM PDT 24 Jul 21 05:36:00 PM PDT 24 1096538248 ps
T389 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1271250123 Jul 21 05:35:59 PM PDT 24 Jul 21 05:36:06 PM PDT 24 4081640873 ps
T390 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.659384252 Jul 21 05:36:08 PM PDT 24 Jul 21 05:36:10 PM PDT 24 319339947 ps
T391 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2791615628 Jul 21 05:35:26 PM PDT 24 Jul 21 05:35:32 PM PDT 24 4509449486 ps
T62 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2541061476 Jul 21 05:35:37 PM PDT 24 Jul 21 05:35:38 PM PDT 24 399803860 ps
T392 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3880057224 Jul 21 05:36:09 PM PDT 24 Jul 21 05:36:11 PM PDT 24 407420007 ps
T393 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4146100876 Jul 21 05:35:49 PM PDT 24 Jul 21 05:35:51 PM PDT 24 298369439 ps
T394 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1599126958 Jul 21 05:35:46 PM PDT 24 Jul 21 05:35:48 PM PDT 24 653270966 ps
T395 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2968424860 Jul 21 05:35:56 PM PDT 24 Jul 21 05:35:58 PM PDT 24 299613117 ps
T396 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.623334506 Jul 21 05:35:49 PM PDT 24 Jul 21 05:35:50 PM PDT 24 388265651 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3355389944 Jul 21 05:35:35 PM PDT 24 Jul 21 05:35:36 PM PDT 24 639055062 ps
T66 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.880491406 Jul 21 05:35:33 PM PDT 24 Jul 21 05:35:34 PM PDT 24 640217201 ps
T398 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3357403848 Jul 21 05:36:02 PM PDT 24 Jul 21 05:36:05 PM PDT 24 1351209638 ps
T399 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1574756957 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:03 PM PDT 24 572845600 ps
T400 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.831797420 Jul 21 05:35:49 PM PDT 24 Jul 21 05:35:54 PM PDT 24 4397240344 ps
T401 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3613970115 Jul 21 05:35:34 PM PDT 24 Jul 21 05:35:36 PM PDT 24 540352644 ps
T402 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4286560561 Jul 21 05:35:59 PM PDT 24 Jul 21 05:36:00 PM PDT 24 367432522 ps
T403 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1858672472 Jul 21 05:36:01 PM PDT 24 Jul 21 05:36:03 PM PDT 24 467509045 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4284843251 Jul 21 05:35:39 PM PDT 24 Jul 21 05:35:42 PM PDT 24 1545571101 ps
T405 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2641872154 Jul 21 05:35:38 PM PDT 24 Jul 21 05:35:40 PM PDT 24 524030041 ps
T406 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.628240413 Jul 21 05:35:27 PM PDT 24 Jul 21 05:35:28 PM PDT 24 389476515 ps
T407 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1111748056 Jul 21 05:36:17 PM PDT 24 Jul 21 05:36:19 PM PDT 24 284701666 ps
T63 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1560063831 Jul 21 05:35:49 PM PDT 24 Jul 21 05:35:59 PM PDT 24 5541572156 ps
T408 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3126258321 Jul 21 05:35:29 PM PDT 24 Jul 21 05:35:30 PM PDT 24 1527313554 ps
T409 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.627730821 Jul 21 05:36:02 PM PDT 24 Jul 21 05:36:03 PM PDT 24 359569229 ps
T410 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1138122992 Jul 21 05:36:12 PM PDT 24 Jul 21 05:36:14 PM PDT 24 333708780 ps
T411 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3971249182 Jul 21 05:35:59 PM PDT 24 Jul 21 05:36:00 PM PDT 24 439766497 ps
T192 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.377486546 Jul 21 05:35:53 PM PDT 24 Jul 21 05:36:08 PM PDT 24 8208006727 ps
T412 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1092335771 Jul 21 05:35:52 PM PDT 24 Jul 21 05:35:54 PM PDT 24 591782377 ps
T413 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1809412478 Jul 21 05:35:54 PM PDT 24 Jul 21 05:35:56 PM PDT 24 491400099 ps
T414 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.964238626 Jul 21 05:36:10 PM PDT 24 Jul 21 05:36:11 PM PDT 24 446168192 ps
T415 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2237485512 Jul 21 05:35:48 PM PDT 24 Jul 21 05:35:54 PM PDT 24 2355487369 ps
T416 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.361361043 Jul 21 05:36:05 PM PDT 24 Jul 21 05:36:06 PM PDT 24 377185675 ps
T417 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1568830745 Jul 21 05:36:08 PM PDT 24 Jul 21 05:36:09 PM PDT 24 352035372 ps
T418 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2677344046 Jul 21 05:36:07 PM PDT 24 Jul 21 05:36:08 PM PDT 24 488291581 ps
T419 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2850178286 Jul 21 05:35:39 PM PDT 24 Jul 21 05:35:43 PM PDT 24 622688887 ps
T420 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1155506336 Jul 21 05:35:40 PM PDT 24 Jul 21 05:35:41 PM PDT 24 291978414 ps
T421 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1219762791 Jul 21 05:35:37 PM PDT 24 Jul 21 05:35:39 PM PDT 24 463057067 ps
T193 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1336118243 Jul 21 05:35:54 PM PDT 24 Jul 21 05:36:06 PM PDT 24 7721774340 ps
T422 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.165940128 Jul 21 05:35:39 PM PDT 24 Jul 21 05:35:41 PM PDT 24 729730054 ps

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3333326950
Short name T7
Test name
Test status
Simulation time 267186344445 ps
CPU time 563.4 seconds
Started Jul 21 05:35:04 PM PDT 24
Finished Jul 21 05:44:28 PM PDT 24
Peak memory 204064 kb
Host smart-0fa742ad-b510-4443-81b3-eabeea64624c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333326950 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3333326950
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1872831588
Short name T12
Test name
Test status
Simulation time 97056246174 ps
CPU time 633.16 seconds
Started Jul 21 05:34:50 PM PDT 24
Finished Jul 21 05:45:24 PM PDT 24
Peak memory 214516 kb
Host smart-be52fd27-ff00-4a98-888c-3e79c2f37e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872831588 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1872831588
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.202917428
Short name T27
Test name
Test status
Simulation time 4403810100 ps
CPU time 2.24 seconds
Started Jul 21 05:35:46 PM PDT 24
Finished Jul 21 05:35:48 PM PDT 24
Peak memory 198244 kb
Host smart-9dc148bf-16c6-4773-8251-46b984d05d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202917428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.202917428
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.4120393760
Short name T8
Test name
Test status
Simulation time 5875185480 ps
CPU time 3.18 seconds
Started Jul 21 05:35:08 PM PDT 24
Finished Jul 21 05:35:12 PM PDT 24
Peak memory 192516 kb
Host smart-c440d5c3-34ef-411a-9651-4cabc7fdbc89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120393760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.4120393760
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1347673830
Short name T80
Test name
Test status
Simulation time 435810268309 ps
CPU time 959.73 seconds
Started Jul 21 05:35:21 PM PDT 24
Finished Jul 21 05:51:22 PM PDT 24
Peak memory 209328 kb
Host smart-433151da-aa75-4da8-9adb-0ba6a088b9e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347673830 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1347673830
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3395491762
Short name T3
Test name
Test status
Simulation time 303256104537 ps
CPU time 635.74 seconds
Started Jul 21 05:35:21 PM PDT 24
Finished Jul 21 05:45:58 PM PDT 24
Peak memory 212912 kb
Host smart-34a19d67-86a7-4599-9e26-efd71a8a8a0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395491762 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3395491762
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1726998775
Short name T105
Test name
Test status
Simulation time 303333554520 ps
CPU time 524.13 seconds
Started Jul 21 05:35:22 PM PDT 24
Finished Jul 21 05:44:07 PM PDT 24
Peak memory 212388 kb
Host smart-7a708152-a219-4340-ac10-c2db24578d7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726998775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1726998775
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1434155546
Short name T18
Test name
Test status
Simulation time 73266993254 ps
CPU time 132.14 seconds
Started Jul 21 05:35:08 PM PDT 24
Finished Jul 21 05:37:21 PM PDT 24
Peak memory 206340 kb
Host smart-36213e22-166c-4046-870b-7c2cb5f6c89b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434155546 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1434155546
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.102162222
Short name T84
Test name
Test status
Simulation time 233246386584 ps
CPU time 456.88 seconds
Started Jul 21 05:34:44 PM PDT 24
Finished Jul 21 05:42:21 PM PDT 24
Peak memory 211352 kb
Host smart-aca7e676-3a09-41ed-beac-72f2aa957fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102162222 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.102162222
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.399634730
Short name T14
Test name
Test status
Simulation time 7624540459 ps
CPU time 3.77 seconds
Started Jul 21 05:34:41 PM PDT 24
Finished Jul 21 05:34:46 PM PDT 24
Peak memory 215484 kb
Host smart-4c168f61-4925-4a4e-b7f3-d03231d3c19a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399634730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.399634730
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3665632287
Short name T116
Test name
Test status
Simulation time 40775641108 ps
CPU time 33.06 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:35:44 PM PDT 24
Peak memory 198000 kb
Host smart-e66d958c-9245-407e-a090-366f89351975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665632287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3665632287
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.562452231
Short name T134
Test name
Test status
Simulation time 163838496388 ps
CPU time 58.48 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:36:16 PM PDT 24
Peak memory 192520 kb
Host smart-2c9649bc-b9ba-4ac8-9546-10e845b5da76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562452231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.562452231
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1792895130
Short name T108
Test name
Test status
Simulation time 681740298497 ps
CPU time 555.29 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:44:34 PM PDT 24
Peak memory 204652 kb
Host smart-3b8ad807-c2a6-41eb-b80b-49b5a2a57399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792895130 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1792895130
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2422712804
Short name T81
Test name
Test status
Simulation time 177788429010 ps
CPU time 289.43 seconds
Started Jul 21 05:35:27 PM PDT 24
Finished Jul 21 05:40:17 PM PDT 24
Peak memory 208376 kb
Host smart-a3d6e983-27be-4d34-92c3-7caaa7b60ca8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422712804 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2422712804
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3275794768
Short name T78
Test name
Test status
Simulation time 58970154584 ps
CPU time 312.36 seconds
Started Jul 21 05:35:11 PM PDT 24
Finished Jul 21 05:40:24 PM PDT 24
Peak memory 198100 kb
Host smart-5778b442-2a17-4076-9ea9-a7e751c8a809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275794768 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3275794768
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3997029789
Short name T87
Test name
Test status
Simulation time 664108108626 ps
CPU time 508.77 seconds
Started Jul 21 05:35:09 PM PDT 24
Finished Jul 21 05:43:39 PM PDT 24
Peak memory 203448 kb
Host smart-a735491e-05b4-4189-ab74-a732734418a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997029789 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3997029789
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.5949340
Short name T5
Test name
Test status
Simulation time 705750505630 ps
CPU time 555.24 seconds
Started Jul 21 05:35:04 PM PDT 24
Finished Jul 21 05:44:20 PM PDT 24
Peak memory 192500 kb
Host smart-8764bd2e-e74a-42dd-86ee-a19885cea640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5949340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.5949340
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3685147270
Short name T83
Test name
Test status
Simulation time 70943397877 ps
CPU time 301.19 seconds
Started Jul 21 05:34:50 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 206460 kb
Host smart-e8105b87-a92a-49c0-9342-2265be6bb287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685147270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3685147270
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.518603047
Short name T36
Test name
Test status
Simulation time 1251298100924 ps
CPU time 416.1 seconds
Started Jul 21 05:35:25 PM PDT 24
Finished Jul 21 05:42:21 PM PDT 24
Peak memory 206432 kb
Host smart-dbb086f5-b8f7-4c72-a1c1-037b4f4780f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518603047 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.518603047
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.4048949341
Short name T112
Test name
Test status
Simulation time 201337070076 ps
CPU time 557.52 seconds
Started Jul 21 05:34:43 PM PDT 24
Finished Jul 21 05:44:01 PM PDT 24
Peak memory 204512 kb
Host smart-48e52903-978b-4a09-ae8f-cc3bd11af524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048949341 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.4048949341
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3450439965
Short name T129
Test name
Test status
Simulation time 153531973686 ps
CPU time 239.02 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:38:56 PM PDT 24
Peak memory 192236 kb
Host smart-10877c1d-ed29-4459-8b7d-55b4f1a1a6ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450439965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3450439965
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3531762012
Short name T26
Test name
Test status
Simulation time 80590834224 ps
CPU time 29.66 seconds
Started Jul 21 05:34:44 PM PDT 24
Finished Jul 21 05:35:14 PM PDT 24
Peak memory 192144 kb
Host smart-f42b5f97-0d4f-48dc-ae88-e21f205f17af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531762012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3531762012
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2385324164
Short name T97
Test name
Test status
Simulation time 55366378634 ps
CPU time 470.01 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:42:47 PM PDT 24
Peak memory 214136 kb
Host smart-0b4fdd78-1789-48e2-9382-7054e4987c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385324164 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2385324164
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2077643149
Short name T125
Test name
Test status
Simulation time 81343185241 ps
CPU time 33.79 seconds
Started Jul 21 05:35:02 PM PDT 24
Finished Jul 21 05:35:36 PM PDT 24
Peak memory 191496 kb
Host smart-970b149a-b9f7-4279-9fa7-0e4dbea0b8c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077643149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2077643149
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.985681990
Short name T121
Test name
Test status
Simulation time 152076785124 ps
CPU time 112.51 seconds
Started Jul 21 05:35:12 PM PDT 24
Finished Jul 21 05:37:05 PM PDT 24
Peak memory 192552 kb
Host smart-bb830ab1-d1b7-4c76-8254-75b69e7ea865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985681990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.985681990
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.285777370
Short name T95
Test name
Test status
Simulation time 148751144835 ps
CPU time 231.42 seconds
Started Jul 21 05:35:27 PM PDT 24
Finished Jul 21 05:39:19 PM PDT 24
Peak memory 192468 kb
Host smart-273a4786-b6e4-4d80-bc6f-138ca0167351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285777370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.285777370
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1133661134
Short name T127
Test name
Test status
Simulation time 70427653144 ps
CPU time 306.03 seconds
Started Jul 21 05:35:23 PM PDT 24
Finished Jul 21 05:40:30 PM PDT 24
Peak memory 214472 kb
Host smart-87fc6df3-725c-4094-92d0-0a371441360e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133661134 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1133661134
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.922488291
Short name T107
Test name
Test status
Simulation time 264788266813 ps
CPU time 117.45 seconds
Started Jul 21 05:35:08 PM PDT 24
Finished Jul 21 05:37:07 PM PDT 24
Peak memory 197800 kb
Host smart-947886ff-d610-48e7-822a-b585985a059a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922488291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.922488291
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4086868626
Short name T85
Test name
Test status
Simulation time 204869955634 ps
CPU time 413.46 seconds
Started Jul 21 05:34:51 PM PDT 24
Finished Jul 21 05:41:46 PM PDT 24
Peak memory 210436 kb
Host smart-c9897def-a517-4fff-8b97-0006ff1f1e2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086868626 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4086868626
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1646726250
Short name T124
Test name
Test status
Simulation time 648539478097 ps
CPU time 233.26 seconds
Started Jul 21 05:35:26 PM PDT 24
Finished Jul 21 05:39:20 PM PDT 24
Peak memory 197844 kb
Host smart-44d78666-6624-4af9-b051-831a38b6c538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646726250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1646726250
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2720239979
Short name T54
Test name
Test status
Simulation time 375165455 ps
CPU time 0.95 seconds
Started Jul 21 05:36:02 PM PDT 24
Finished Jul 21 05:36:04 PM PDT 24
Peak memory 193364 kb
Host smart-a157a3a9-5cea-4f36-855c-62a2ef60cc4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720239979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2720239979
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.4289396226
Short name T110
Test name
Test status
Simulation time 260153012041 ps
CPU time 389.8 seconds
Started Jul 21 05:35:19 PM PDT 24
Finished Jul 21 05:41:50 PM PDT 24
Peak memory 192612 kb
Host smart-ad2cc74b-528e-44c1-91f2-4274f04467af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289396226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.4289396226
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1359505360
Short name T77
Test name
Test status
Simulation time 19471364819 ps
CPU time 210.8 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:38:42 PM PDT 24
Peak memory 206336 kb
Host smart-a7a27307-cb52-4987-8b01-c9b98c04b5fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359505360 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1359505360
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1055664462
Short name T25
Test name
Test status
Simulation time 36304440553 ps
CPU time 274.6 seconds
Started Jul 21 05:35:11 PM PDT 24
Finished Jul 21 05:39:46 PM PDT 24
Peak memory 206368 kb
Host smart-68439140-219c-4c6e-b353-ab88983b09fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055664462 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1055664462
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2197108508
Short name T86
Test name
Test status
Simulation time 24985340967 ps
CPU time 194.8 seconds
Started Jul 21 05:35:18 PM PDT 24
Finished Jul 21 05:38:33 PM PDT 24
Peak memory 213820 kb
Host smart-da1d8635-e0f5-4e72-98d1-af045c8145de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197108508 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2197108508
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.844843040
Short name T113
Test name
Test status
Simulation time 79461201044 ps
CPU time 429.28 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:42:27 PM PDT 24
Peak memory 202336 kb
Host smart-0a236f20-eb1d-4dad-98ae-33da5b3107e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844843040 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.844843040
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2944505957
Short name T96
Test name
Test status
Simulation time 399246923048 ps
CPU time 322.21 seconds
Started Jul 21 05:34:51 PM PDT 24
Finished Jul 21 05:40:14 PM PDT 24
Peak memory 197848 kb
Host smart-b77960c4-da39-4eed-bed4-0d776c92ab04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944505957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2944505957
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3414325474
Short name T118
Test name
Test status
Simulation time 71158538025 ps
CPU time 106 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:36:43 PM PDT 24
Peak memory 183804 kb
Host smart-dcc57a2e-6911-4deb-bfcb-267d93f2e4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414325474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3414325474
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.560568209
Short name T131
Test name
Test status
Simulation time 57663355560 ps
CPU time 86.19 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:36:37 PM PDT 24
Peak memory 197804 kb
Host smart-dcac1194-8853-4765-985a-9d2835ec8a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560568209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.560568209
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1970636810
Short name T126
Test name
Test status
Simulation time 160295240995 ps
CPU time 210.24 seconds
Started Jul 21 05:35:19 PM PDT 24
Finished Jul 21 05:38:50 PM PDT 24
Peak memory 192504 kb
Host smart-940f10a2-62ee-4761-b4df-23b70fc36da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970636810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1970636810
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3996279792
Short name T19
Test name
Test status
Simulation time 241437079503 ps
CPU time 381.04 seconds
Started Jul 21 05:35:12 PM PDT 24
Finished Jul 21 05:41:33 PM PDT 24
Peak memory 197808 kb
Host smart-1f9868b1-4461-4b7a-afbd-8a784c285cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996279792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3996279792
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.787502939
Short name T20
Test name
Test status
Simulation time 254726694441 ps
CPU time 363.04 seconds
Started Jul 21 05:34:48 PM PDT 24
Finished Jul 21 05:40:52 PM PDT 24
Peak memory 192624 kb
Host smart-180ac7f0-9144-41f6-9b4b-e27fb280c5a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787502939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.787502939
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.170451719
Short name T34
Test name
Test status
Simulation time 188122337656 ps
CPU time 502.03 seconds
Started Jul 21 05:34:57 PM PDT 24
Finished Jul 21 05:43:21 PM PDT 24
Peak memory 204016 kb
Host smart-b3264ff0-778e-42ce-b40d-4b3913d693b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170451719 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.170451719
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3672465389
Short name T50
Test name
Test status
Simulation time 83903705868 ps
CPU time 505.76 seconds
Started Jul 21 05:35:19 PM PDT 24
Finished Jul 21 05:43:45 PM PDT 24
Peak memory 203572 kb
Host smart-d83e6e19-9370-4d06-aea1-48e296658d51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672465389 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3672465389
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2421290842
Short name T39
Test name
Test status
Simulation time 27597344523 ps
CPU time 11.42 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:35:22 PM PDT 24
Peak memory 191468 kb
Host smart-e5b55824-127d-4f83-aca4-3fd1c2127372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421290842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2421290842
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.4003129477
Short name T106
Test name
Test status
Simulation time 156941694214 ps
CPU time 58.26 seconds
Started Jul 21 05:34:57 PM PDT 24
Finished Jul 21 05:35:57 PM PDT 24
Peak memory 191568 kb
Host smart-a4d08420-22d7-46ad-a4c8-be12076746a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003129477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.4003129477
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3154565569
Short name T102
Test name
Test status
Simulation time 80149375390 ps
CPU time 114.74 seconds
Started Jul 21 05:35:16 PM PDT 24
Finished Jul 21 05:37:11 PM PDT 24
Peak memory 192520 kb
Host smart-2f45d878-cadb-498d-b500-ea95a5d671e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154565569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3154565569
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1622981335
Short name T109
Test name
Test status
Simulation time 230981458544 ps
CPU time 76.36 seconds
Started Jul 21 05:35:29 PM PDT 24
Finished Jul 21 05:36:46 PM PDT 24
Peak memory 192544 kb
Host smart-b1466069-26c4-4bcc-b992-a285c3251346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622981335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1622981335
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3774884392
Short name T33
Test name
Test status
Simulation time 88097992555 ps
CPU time 475.09 seconds
Started Jul 21 05:34:49 PM PDT 24
Finished Jul 21 05:42:45 PM PDT 24
Peak memory 203348 kb
Host smart-d49c0aa7-2ce3-4a6e-8527-d80a23b0a543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774884392 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3774884392
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3755904992
Short name T92
Test name
Test status
Simulation time 78109439286 ps
CPU time 242.88 seconds
Started Jul 21 05:34:45 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 213680 kb
Host smart-65086746-28ed-45a2-91a9-51dd299fd7ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755904992 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3755904992
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1216103149
Short name T136
Test name
Test status
Simulation time 38748580667 ps
CPU time 306.19 seconds
Started Jul 21 05:35:04 PM PDT 24
Finished Jul 21 05:40:11 PM PDT 24
Peak memory 206332 kb
Host smart-a8404d9b-a3ac-4e9c-8bf4-55009a1b627c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216103149 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1216103149
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.758261488
Short name T147
Test name
Test status
Simulation time 221711202689 ps
CPU time 306.96 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:40:04 PM PDT 24
Peak memory 192620 kb
Host smart-f99e12bd-c1d3-4a62-a4ee-8e05bf7e7351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758261488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.758261488
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2632511609
Short name T159
Test name
Test status
Simulation time 417418233988 ps
CPU time 151.05 seconds
Started Jul 21 05:35:16 PM PDT 24
Finished Jul 21 05:37:48 PM PDT 24
Peak memory 197872 kb
Host smart-8619d3d6-2e84-4d57-83d3-06c638ac2db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632511609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2632511609
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1712028001
Short name T99
Test name
Test status
Simulation time 80627867609 ps
CPU time 112.28 seconds
Started Jul 21 05:35:21 PM PDT 24
Finished Jul 21 05:37:14 PM PDT 24
Peak memory 206296 kb
Host smart-e4de4031-ca46-445f-8170-32ca4c5f88ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712028001 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1712028001
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3960294771
Short name T89
Test name
Test status
Simulation time 136502831964 ps
CPU time 45.62 seconds
Started Jul 21 05:35:22 PM PDT 24
Finished Jul 21 05:36:08 PM PDT 24
Peak memory 192456 kb
Host smart-9d10bd4e-1e5d-45d0-8f5f-06872ea1284d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960294771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3960294771
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.215886818
Short name T135
Test name
Test status
Simulation time 253506265715 ps
CPU time 161.01 seconds
Started Jul 21 05:35:01 PM PDT 24
Finished Jul 21 05:37:43 PM PDT 24
Peak memory 197872 kb
Host smart-0d13b7da-b8ca-42e7-a889-aff4d531c4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215886818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.215886818
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.793808961
Short name T141
Test name
Test status
Simulation time 77879219863 ps
CPU time 17.45 seconds
Started Jul 21 05:35:09 PM PDT 24
Finished Jul 21 05:35:27 PM PDT 24
Peak memory 197844 kb
Host smart-0d444638-d69d-4a13-9ee5-f3fe084cdcd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793808961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.793808961
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1223145320
Short name T143
Test name
Test status
Simulation time 47555263755 ps
CPU time 21.13 seconds
Started Jul 21 05:35:22 PM PDT 24
Finished Jul 21 05:35:43 PM PDT 24
Peak memory 191464 kb
Host smart-6169aecd-af38-4160-8721-b06edf61a805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223145320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1223145320
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3646677489
Short name T6
Test name
Test status
Simulation time 394821489027 ps
CPU time 634.51 seconds
Started Jul 21 05:35:21 PM PDT 24
Finished Jul 21 05:45:56 PM PDT 24
Peak memory 183744 kb
Host smart-ece7df39-b036-4716-bf62-b70318fc9fed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646677489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3646677489
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4135170746
Short name T140
Test name
Test status
Simulation time 352048245647 ps
CPU time 146.7 seconds
Started Jul 21 05:34:55 PM PDT 24
Finished Jul 21 05:37:22 PM PDT 24
Peak memory 192524 kb
Host smart-560f5da6-3507-4bc7-9287-3478fd9ca40f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135170746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4135170746
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3344094913
Short name T88
Test name
Test status
Simulation time 9560590104 ps
CPU time 42.95 seconds
Started Jul 21 05:35:02 PM PDT 24
Finished Jul 21 05:35:45 PM PDT 24
Peak memory 206324 kb
Host smart-39c7e855-abb3-4750-b23b-b3da8d2954f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344094913 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3344094913
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.210530016
Short name T111
Test name
Test status
Simulation time 55502924821 ps
CPU time 86.28 seconds
Started Jul 21 05:34:51 PM PDT 24
Finished Jul 21 05:36:18 PM PDT 24
Peak memory 192584 kb
Host smart-2c9c4502-dec6-4cf2-83e5-4729e6204905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210530016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.210530016
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2163848115
Short name T133
Test name
Test status
Simulation time 303754335982 ps
CPU time 233.77 seconds
Started Jul 21 05:35:15 PM PDT 24
Finished Jul 21 05:39:09 PM PDT 24
Peak memory 192464 kb
Host smart-388efae8-622e-4786-8074-d4ef900532e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163848115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2163848115
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.833930975
Short name T90
Test name
Test status
Simulation time 215798233275 ps
CPU time 39.87 seconds
Started Jul 21 05:35:16 PM PDT 24
Finished Jul 21 05:35:56 PM PDT 24
Peak memory 191488 kb
Host smart-a41ca75e-f8ca-4c2c-beea-8a7a1dcf124b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833930975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.833930975
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1803720123
Short name T114
Test name
Test status
Simulation time 85258722225 ps
CPU time 219.82 seconds
Started Jul 21 05:34:57 PM PDT 24
Finished Jul 21 05:38:38 PM PDT 24
Peak memory 208360 kb
Host smart-e5f9e1bc-38ed-4fe3-aef3-6a520b2a32dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803720123 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1803720123
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2233236582
Short name T82
Test name
Test status
Simulation time 165204816647 ps
CPU time 431.22 seconds
Started Jul 21 05:35:03 PM PDT 24
Finished Jul 21 05:42:15 PM PDT 24
Peak memory 206292 kb
Host smart-6dd8877d-afc9-47fd-81e9-2eb16bafabc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233236582 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2233236582
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3506020179
Short name T44
Test name
Test status
Simulation time 158262843836 ps
CPU time 61.66 seconds
Started Jul 21 05:35:05 PM PDT 24
Finished Jul 21 05:36:07 PM PDT 24
Peak memory 197856 kb
Host smart-6960143d-a3ab-4839-a385-c436090b16e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506020179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3506020179
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.331576890
Short name T79
Test name
Test status
Simulation time 72987574300 ps
CPU time 301.26 seconds
Started Jul 21 05:35:07 PM PDT 24
Finished Jul 21 05:40:10 PM PDT 24
Peak memory 206380 kb
Host smart-6228dbb2-8fcf-49a7-8632-593d628bc1d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331576890 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.331576890
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1311298028
Short name T91
Test name
Test status
Simulation time 519829055 ps
CPU time 1.39 seconds
Started Jul 21 05:34:55 PM PDT 24
Finished Jul 21 05:34:57 PM PDT 24
Peak memory 196172 kb
Host smart-b2fa3e41-70cf-4e2b-acfc-8a86ff315c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311298028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1311298028
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1375681813
Short name T130
Test name
Test status
Simulation time 471378396 ps
CPU time 1.52 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:34:58 PM PDT 24
Peak memory 196128 kb
Host smart-b0757e98-bfc0-44b6-b2cf-6fa9baa598e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375681813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1375681813
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1374446750
Short name T120
Test name
Test status
Simulation time 571137698 ps
CPU time 1.45 seconds
Started Jul 21 05:35:00 PM PDT 24
Finished Jul 21 05:35:02 PM PDT 24
Peak memory 196400 kb
Host smart-9f906885-fbc8-4116-ac88-a40a5c01131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374446750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1374446750
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3325062602
Short name T10
Test name
Test status
Simulation time 124714362887 ps
CPU time 165.85 seconds
Started Jul 21 05:35:02 PM PDT 24
Finished Jul 21 05:37:49 PM PDT 24
Peak memory 197808 kb
Host smart-bbd300ad-0888-4bf1-9570-bc9b90e8c5e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325062602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3325062602
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1220065996
Short name T145
Test name
Test status
Simulation time 302798049095 ps
CPU time 226.82 seconds
Started Jul 21 05:35:04 PM PDT 24
Finished Jul 21 05:38:51 PM PDT 24
Peak memory 191512 kb
Host smart-2ba81b50-0fd6-4db2-8557-4f6593371349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220065996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1220065996
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2830092050
Short name T101
Test name
Test status
Simulation time 158571067239 ps
CPU time 143.29 seconds
Started Jul 21 05:34:45 PM PDT 24
Finished Jul 21 05:37:09 PM PDT 24
Peak memory 207396 kb
Host smart-6a39db30-b52f-474f-a741-9275961cec0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830092050 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2830092050
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2315445777
Short name T4
Test name
Test status
Simulation time 32689632113 ps
CPU time 282.21 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:40:03 PM PDT 24
Peak memory 206316 kb
Host smart-37df0557-9e90-47d0-a5e5-b136b10a8037
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315445777 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2315445777
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1941240288
Short name T115
Test name
Test status
Simulation time 451151329 ps
CPU time 1.17 seconds
Started Jul 21 05:35:24 PM PDT 24
Finished Jul 21 05:35:25 PM PDT 24
Peak memory 196384 kb
Host smart-a1db3f16-ee4d-4689-b589-f45783df6e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941240288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1941240288
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3400264283
Short name T142
Test name
Test status
Simulation time 364920255 ps
CPU time 0.9 seconds
Started Jul 21 05:34:52 PM PDT 24
Finished Jul 21 05:34:53 PM PDT 24
Peak memory 196292 kb
Host smart-8f97c497-0295-4d40-b1f2-7692f0aaad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400264283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3400264283
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1233572392
Short name T144
Test name
Test status
Simulation time 413836231 ps
CPU time 0.88 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:35:12 PM PDT 24
Peak memory 196244 kb
Host smart-9b1ff8c1-1c92-4d36-b2e2-538d04bab69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233572392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1233572392
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.384046278
Short name T117
Test name
Test status
Simulation time 392749944 ps
CPU time 0.83 seconds
Started Jul 21 05:35:07 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 196384 kb
Host smart-1e829a79-0a58-4586-b0f2-2d24b875f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384046278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.384046278
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.923537126
Short name T94
Test name
Test status
Simulation time 639725252 ps
CPU time 0.69 seconds
Started Jul 21 05:35:18 PM PDT 24
Finished Jul 21 05:35:19 PM PDT 24
Peak memory 196236 kb
Host smart-3bfe655d-f8a7-434e-bb39-5419a7df85c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923537126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.923537126
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1075679957
Short name T137
Test name
Test status
Simulation time 530446035 ps
CPU time 1.47 seconds
Started Jul 21 05:35:23 PM PDT 24
Finished Jul 21 05:35:25 PM PDT 24
Peak memory 196280 kb
Host smart-92622ad0-4af5-4bce-82d0-97f05dc8fb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075679957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1075679957
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2155350183
Short name T122
Test name
Test status
Simulation time 441464149106 ps
CPU time 700.15 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:47:00 PM PDT 24
Peak memory 192028 kb
Host smart-0a00e8fe-1b5e-43dd-94a1-3d447e6a7c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155350183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2155350183
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2951424509
Short name T123
Test name
Test status
Simulation time 494972958 ps
CPU time 0.77 seconds
Started Jul 21 05:35:03 PM PDT 24
Finished Jul 21 05:35:05 PM PDT 24
Peak memory 196168 kb
Host smart-cef6eb3a-2a6a-4a2d-97ba-eaa56b506caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951424509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2951424509
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1530687572
Short name T38
Test name
Test status
Simulation time 121421615772 ps
CPU time 396.15 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:41:47 PM PDT 24
Peak memory 209116 kb
Host smart-25d98931-a1bf-4169-83e2-a34f08df039b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530687572 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1530687572
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.179882616
Short name T45
Test name
Test status
Simulation time 373509129 ps
CPU time 1.13 seconds
Started Jul 21 05:35:07 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 196268 kb
Host smart-99af361a-cb0f-474b-9191-d8a1422b4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179882616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.179882616
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1227837327
Short name T167
Test name
Test status
Simulation time 127045517370 ps
CPU time 331.71 seconds
Started Jul 21 05:35:08 PM PDT 24
Finished Jul 21 05:40:41 PM PDT 24
Peak memory 209532 kb
Host smart-dce0f33b-7f16-4ec8-830b-ce9c7259060a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227837327 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1227837327
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3031163167
Short name T103
Test name
Test status
Simulation time 402031137 ps
CPU time 0.76 seconds
Started Jul 21 05:35:08 PM PDT 24
Finished Jul 21 05:35:10 PM PDT 24
Peak memory 196264 kb
Host smart-6ec3e8a9-a50d-4a8b-b941-970aa668211c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031163167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3031163167
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2660978071
Short name T156
Test name
Test status
Simulation time 158691507582 ps
CPU time 245.69 seconds
Started Jul 21 05:34:43 PM PDT 24
Finished Jul 21 05:38:49 PM PDT 24
Peak memory 191496 kb
Host smart-9df85c66-f5aa-464f-bf11-f08d06c6cb51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660978071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2660978071
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2905033484
Short name T154
Test name
Test status
Simulation time 405768355103 ps
CPU time 513.55 seconds
Started Jul 21 05:35:15 PM PDT 24
Finished Jul 21 05:43:49 PM PDT 24
Peak memory 197848 kb
Host smart-aa54884d-dd2e-483c-abfe-7a674f40e62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905033484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2905033484
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.744581307
Short name T22
Test name
Test status
Simulation time 567409482 ps
CPU time 1.03 seconds
Started Jul 21 05:35:28 PM PDT 24
Finished Jul 21 05:35:30 PM PDT 24
Peak memory 196240 kb
Host smart-5bd50b17-cc16-4d86-99a1-7d7e3f43c44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744581307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.744581307
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1079468076
Short name T165
Test name
Test status
Simulation time 49033055058 ps
CPU time 15.66 seconds
Started Jul 21 05:34:52 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 192532 kb
Host smart-ef879592-f40e-47c9-9853-0e7c0e31bad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079468076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1079468076
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1408791775
Short name T93
Test name
Test status
Simulation time 373357377 ps
CPU time 0.74 seconds
Started Jul 21 05:34:55 PM PDT 24
Finished Jul 21 05:34:57 PM PDT 24
Peak memory 196308 kb
Host smart-244fd7cc-3709-4978-ab97-26145fc287c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408791775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1408791775
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2459176709
Short name T179
Test name
Test status
Simulation time 25160869754 ps
CPU time 193.04 seconds
Started Jul 21 05:34:58 PM PDT 24
Finished Jul 21 05:38:13 PM PDT 24
Peak memory 198196 kb
Host smart-f22efa31-db26-4156-b9cd-865d9371b471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459176709 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2459176709
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3834206308
Short name T150
Test name
Test status
Simulation time 113438158237 ps
CPU time 447.32 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:42:39 PM PDT 24
Peak memory 202492 kb
Host smart-b09efc7c-8dc5-45f8-9d85-f2c965205a41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834206308 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3834206308
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3129999266
Short name T119
Test name
Test status
Simulation time 532251516 ps
CPU time 1.44 seconds
Started Jul 21 05:35:13 PM PDT 24
Finished Jul 21 05:35:15 PM PDT 24
Peak memory 196280 kb
Host smart-0a0c391f-3788-4839-b86a-3ad462198ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129999266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3129999266
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1731463426
Short name T128
Test name
Test status
Simulation time 490022784 ps
CPU time 0.89 seconds
Started Jul 21 05:35:06 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 196244 kb
Host smart-1de64a52-b65b-4170-909b-5acb9df5e0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731463426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1731463426
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1463410691
Short name T40
Test name
Test status
Simulation time 534825012 ps
CPU time 0.67 seconds
Started Jul 21 05:35:22 PM PDT 24
Finished Jul 21 05:35:23 PM PDT 24
Peak memory 196216 kb
Host smart-5ecb0b6e-f738-4790-b4ac-5f3ba95886a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463410691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1463410691
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1907808967
Short name T146
Test name
Test status
Simulation time 69165238339 ps
CPU time 151.21 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:37:28 PM PDT 24
Peak memory 206300 kb
Host smart-98f1118b-a619-487c-b732-625aedf2a072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907808967 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1907808967
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3508676696
Short name T171
Test name
Test status
Simulation time 149121740120 ps
CPU time 372.06 seconds
Started Jul 21 05:34:54 PM PDT 24
Finished Jul 21 05:41:06 PM PDT 24
Peak memory 202196 kb
Host smart-67107691-126d-444e-9012-a3ab7245a353
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508676696 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3508676696
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1481539563
Short name T155
Test name
Test status
Simulation time 45396320857 ps
CPU time 175.88 seconds
Started Jul 21 05:35:03 PM PDT 24
Finished Jul 21 05:38:00 PM PDT 24
Peak memory 213656 kb
Host smart-15059d55-1f6d-40a4-883b-1ea1353b9f55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481539563 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1481539563
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2344056976
Short name T98
Test name
Test status
Simulation time 545917921 ps
CPU time 1.23 seconds
Started Jul 21 05:35:15 PM PDT 24
Finished Jul 21 05:35:17 PM PDT 24
Peak memory 196308 kb
Host smart-a24d46b6-5e55-4271-aee4-f1d0755a89c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344056976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2344056976
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2739599268
Short name T132
Test name
Test status
Simulation time 202770463354 ps
CPU time 67.59 seconds
Started Jul 21 05:35:21 PM PDT 24
Finished Jul 21 05:36:29 PM PDT 24
Peak memory 191488 kb
Host smart-c8256b74-0f41-498d-902e-bb7fe879e28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739599268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2739599268
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2959019418
Short name T163
Test name
Test status
Simulation time 80290952771 ps
CPU time 27.09 seconds
Started Jul 21 05:34:49 PM PDT 24
Finished Jul 21 05:35:17 PM PDT 24
Peak memory 191464 kb
Host smart-cee8fa23-f96f-4b88-a8a6-db94c9bd4ed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959019418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2959019418
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1115200563
Short name T148
Test name
Test status
Simulation time 499303935 ps
CPU time 1.42 seconds
Started Jul 21 05:34:43 PM PDT 24
Finished Jul 21 05:34:45 PM PDT 24
Peak memory 196208 kb
Host smart-6fb7eaf9-d2ba-41ae-8c7d-3699588fbd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115200563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1115200563
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1123398493
Short name T41
Test name
Test status
Simulation time 185268599452 ps
CPU time 70.01 seconds
Started Jul 21 05:34:58 PM PDT 24
Finished Jul 21 05:36:09 PM PDT 24
Peak memory 192536 kb
Host smart-2a85bb59-19d6-4143-a088-c0bf56f4aaa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123398493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1123398493
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1193570667
Short name T158
Test name
Test status
Simulation time 44554927362 ps
CPU time 16.09 seconds
Started Jul 21 05:34:42 PM PDT 24
Finished Jul 21 05:34:59 PM PDT 24
Peak memory 192084 kb
Host smart-e3cf3818-1b1f-4641-9eb1-b4c56335ce88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193570667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1193570667
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2473828650
Short name T161
Test name
Test status
Simulation time 545261878 ps
CPU time 1.35 seconds
Started Jul 21 05:35:02 PM PDT 24
Finished Jul 21 05:35:04 PM PDT 24
Peak memory 196156 kb
Host smart-851a4cbd-9f6f-4f85-a0ff-5ccee2b45e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473828650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2473828650
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3102236166
Short name T104
Test name
Test status
Simulation time 421375656 ps
CPU time 1.2 seconds
Started Jul 21 05:35:07 PM PDT 24
Finished Jul 21 05:35:09 PM PDT 24
Peak memory 196280 kb
Host smart-76c2818d-2a3a-492e-9675-aaf71b3288c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102236166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3102236166
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2810487591
Short name T160
Test name
Test status
Simulation time 376975469 ps
CPU time 0.84 seconds
Started Jul 21 05:35:19 PM PDT 24
Finished Jul 21 05:35:21 PM PDT 24
Peak memory 196236 kb
Host smart-b30efe4c-0fc4-43cf-bf31-233a0cd7ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810487591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2810487591
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2837773156
Short name T138
Test name
Test status
Simulation time 432777306 ps
CPU time 0.65 seconds
Started Jul 21 05:35:23 PM PDT 24
Finished Jul 21 05:35:24 PM PDT 24
Peak memory 196280 kb
Host smart-3c768d04-fcf0-45c0-bb66-6b52fbc5ea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837773156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2837773156
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.201638198
Short name T169
Test name
Test status
Simulation time 34793572066 ps
CPU time 204.53 seconds
Started Jul 21 05:35:29 PM PDT 24
Finished Jul 21 05:38:54 PM PDT 24
Peak memory 206320 kb
Host smart-d4007b54-8003-4e53-a8ad-7a4becce81ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201638198 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.201638198
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1538764527
Short name T35
Test name
Test status
Simulation time 30421376260 ps
CPU time 295.08 seconds
Started Jul 21 05:35:29 PM PDT 24
Finished Jul 21 05:40:24 PM PDT 24
Peak memory 214512 kb
Host smart-297ed5cb-6e2c-49fd-a291-1a1a1fac3c42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538764527 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1538764527
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.440323773
Short name T173
Test name
Test status
Simulation time 552555580 ps
CPU time 0.75 seconds
Started Jul 21 05:34:44 PM PDT 24
Finished Jul 21 05:34:46 PM PDT 24
Peak memory 196172 kb
Host smart-aa2d8148-86a6-478d-9073-af4cf532b158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440323773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.440323773
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3338681003
Short name T176
Test name
Test status
Simulation time 480717413 ps
CPU time 0.95 seconds
Started Jul 21 05:34:57 PM PDT 24
Finished Jul 21 05:35:00 PM PDT 24
Peak memory 196232 kb
Host smart-1ed91b82-24c8-419d-ba71-bf28715f257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338681003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3338681003
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.216207501
Short name T183
Test name
Test status
Simulation time 203571107618 ps
CPU time 134.69 seconds
Started Jul 21 05:34:58 PM PDT 24
Finished Jul 21 05:37:15 PM PDT 24
Peak memory 192108 kb
Host smart-5c3477bc-7995-4fa5-8c38-d134a1f6e6df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216207501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.216207501
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1308170349
Short name T185
Test name
Test status
Simulation time 523169703 ps
CPU time 0.84 seconds
Started Jul 21 05:35:08 PM PDT 24
Finished Jul 21 05:35:10 PM PDT 24
Peak memory 196220 kb
Host smart-6ad03a33-214c-462d-80e1-2a0b8c79f1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308170349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1308170349
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1845659838
Short name T181
Test name
Test status
Simulation time 378803638 ps
CPU time 0.71 seconds
Started Jul 21 05:35:07 PM PDT 24
Finished Jul 21 05:35:09 PM PDT 24
Peak memory 196224 kb
Host smart-8ee566af-a257-44c3-b2d1-d3fe1f74a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845659838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1845659838
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3725310210
Short name T100
Test name
Test status
Simulation time 589235863 ps
CPU time 0.67 seconds
Started Jul 21 05:35:18 PM PDT 24
Finished Jul 21 05:35:19 PM PDT 24
Peak memory 196244 kb
Host smart-734cff1c-cf39-4dd7-b21f-b364c6ef5f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725310210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3725310210
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2823693205
Short name T188
Test name
Test status
Simulation time 450129822 ps
CPU time 0.75 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:35:19 PM PDT 24
Peak memory 196216 kb
Host smart-4e42552c-b4c5-4e95-8735-e2b3d108d8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823693205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2823693205
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1708658261
Short name T139
Test name
Test status
Simulation time 448314254 ps
CPU time 1.31 seconds
Started Jul 21 05:34:43 PM PDT 24
Finished Jul 21 05:34:45 PM PDT 24
Peak memory 196180 kb
Host smart-6cf098ce-95cf-48d0-a990-10189b02a43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708658261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1708658261
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4184562759
Short name T174
Test name
Test status
Simulation time 634653387 ps
CPU time 0.68 seconds
Started Jul 21 05:35:25 PM PDT 24
Finished Jul 21 05:35:26 PM PDT 24
Peak memory 196168 kb
Host smart-7bdc4da1-f99b-4db6-a725-4f34f9a0803d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184562759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4184562759
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3626165275
Short name T162
Test name
Test status
Simulation time 426491932 ps
CPU time 0.89 seconds
Started Jul 21 05:35:24 PM PDT 24
Finished Jul 21 05:35:25 PM PDT 24
Peak memory 196176 kb
Host smart-1d6f67e4-e466-42ba-8104-0934f33cf617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626165275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3626165275
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2278797078
Short name T182
Test name
Test status
Simulation time 545903130 ps
CPU time 1.4 seconds
Started Jul 21 05:35:25 PM PDT 24
Finished Jul 21 05:35:26 PM PDT 24
Peak memory 196344 kb
Host smart-1add709c-ae65-44e4-97cc-19905c5aa834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278797078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2278797078
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1601548142
Short name T164
Test name
Test status
Simulation time 302490274666 ps
CPU time 62.56 seconds
Started Jul 21 05:34:49 PM PDT 24
Finished Jul 21 05:35:51 PM PDT 24
Peak memory 191452 kb
Host smart-9a7dab06-bf22-4878-8667-ac870778dd5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601548142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1601548142
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3121539812
Short name T170
Test name
Test status
Simulation time 474897222 ps
CPU time 1.35 seconds
Started Jul 21 05:34:50 PM PDT 24
Finished Jul 21 05:34:52 PM PDT 24
Peak memory 196244 kb
Host smart-ff2123c9-17c5-47fd-b305-62dafbb72a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121539812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3121539812
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4256130804
Short name T190
Test name
Test status
Simulation time 604456915 ps
CPU time 1.17 seconds
Started Jul 21 05:34:50 PM PDT 24
Finished Jul 21 05:34:52 PM PDT 24
Peak memory 196156 kb
Host smart-4e45f840-5d6f-48d3-886c-fa45d21c7bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256130804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4256130804
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1336118243
Short name T193
Test name
Test status
Simulation time 7721774340 ps
CPU time 10.82 seconds
Started Jul 21 05:35:54 PM PDT 24
Finished Jul 21 05:36:06 PM PDT 24
Peak memory 198644 kb
Host smart-ec028cc8-3401-4382-80ac-9b721bab7046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336118243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1336118243
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1559546927
Short name T178
Test name
Test status
Simulation time 401615561 ps
CPU time 0.88 seconds
Started Jul 21 05:34:55 PM PDT 24
Finished Jul 21 05:34:56 PM PDT 24
Peak memory 196160 kb
Host smart-610e8172-665f-4566-8b54-211e097c78bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559546927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1559546927
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.266430882
Short name T172
Test name
Test status
Simulation time 546076145 ps
CPU time 0.81 seconds
Started Jul 21 05:34:55 PM PDT 24
Finished Jul 21 05:34:57 PM PDT 24
Peak memory 196192 kb
Host smart-388f04be-719c-42d7-802f-3a0a77f79767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266430882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.266430882
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1273395733
Short name T189
Test name
Test status
Simulation time 469683660 ps
CPU time 1.32 seconds
Started Jul 21 05:35:21 PM PDT 24
Finished Jul 21 05:35:23 PM PDT 24
Peak memory 196308 kb
Host smart-2bc2a57c-1a78-41c2-bae6-ed2e96ea217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273395733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1273395733
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3580292115
Short name T187
Test name
Test status
Simulation time 527370458 ps
CPU time 0.73 seconds
Started Jul 21 05:34:45 PM PDT 24
Finished Jul 21 05:34:47 PM PDT 24
Peak memory 196256 kb
Host smart-d0e92415-503a-4fef-86d8-a2bcb4d73d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580292115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3580292115
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.501354293
Short name T184
Test name
Test status
Simulation time 545338575 ps
CPU time 1.39 seconds
Started Jul 21 05:35:09 PM PDT 24
Finished Jul 21 05:35:11 PM PDT 24
Peak memory 196328 kb
Host smart-30b647e6-907d-4a0b-ab86-dd92123f1c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501354293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.501354293
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3040065890
Short name T153
Test name
Test status
Simulation time 387339365 ps
CPU time 0.71 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:35:18 PM PDT 24
Peak memory 196260 kb
Host smart-bb0f2be7-7b95-4554-b5f7-8c7e5db081a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040065890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3040065890
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2322051033
Short name T180
Test name
Test status
Simulation time 389409675 ps
CPU time 0.98 seconds
Started Jul 21 05:35:15 PM PDT 24
Finished Jul 21 05:35:17 PM PDT 24
Peak memory 196344 kb
Host smart-c2303cf9-cc0e-4a2a-8cd6-42fc4023a608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322051033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2322051033
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.145501443
Short name T175
Test name
Test status
Simulation time 189508770208 ps
CPU time 218.61 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:38:57 PM PDT 24
Peak memory 191480 kb
Host smart-741f35e8-c6ce-40ec-8c97-3e02ff50639a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145501443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.145501443
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1839881617
Short name T43
Test name
Test status
Simulation time 574353801 ps
CPU time 1 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:35:22 PM PDT 24
Peak memory 196308 kb
Host smart-4c5e7df9-a85b-499e-83d2-e4b8a79955c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839881617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1839881617
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1543540204
Short name T157
Test name
Test status
Simulation time 546673251 ps
CPU time 1.3 seconds
Started Jul 21 05:35:24 PM PDT 24
Finished Jul 21 05:35:26 PM PDT 24
Peak memory 196216 kb
Host smart-dec9f662-1f13-4402-b104-dad7aad78884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543540204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1543540204
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3013355258
Short name T168
Test name
Test status
Simulation time 509332877 ps
CPU time 0.98 seconds
Started Jul 21 05:34:59 PM PDT 24
Finished Jul 21 05:35:01 PM PDT 24
Peak memory 196324 kb
Host smart-42b869c3-b529-4c09-aaf6-d1b2757ae14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013355258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3013355258
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.880491406
Short name T66
Test name
Test status
Simulation time 640217201 ps
CPU time 1.1 seconds
Started Jul 21 05:35:33 PM PDT 24
Finished Jul 21 05:35:34 PM PDT 24
Peak memory 184264 kb
Host smart-448155f3-8fe3-4306-ab44-38e3677ab756
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880491406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.880491406
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.415369240
Short name T58
Test name
Test status
Simulation time 759231829 ps
CPU time 1.73 seconds
Started Jul 21 05:35:28 PM PDT 24
Finished Jul 21 05:35:30 PM PDT 24
Peak memory 192572 kb
Host smart-67f91c56-8d56-4655-8f0e-28cda8a6a4aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415369240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.415369240
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4061566976
Short name T315
Test name
Test status
Simulation time 996816903 ps
CPU time 2.09 seconds
Started Jul 21 05:35:29 PM PDT 24
Finished Jul 21 05:35:32 PM PDT 24
Peak memory 184060 kb
Host smart-68e6e0ed-e98a-48c6-a44b-3a756bf8e03e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061566976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4061566976
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2188597548
Short name T342
Test name
Test status
Simulation time 581141201 ps
CPU time 1 seconds
Started Jul 21 05:35:26 PM PDT 24
Finished Jul 21 05:35:28 PM PDT 24
Peak memory 195964 kb
Host smart-727b2b13-f2a8-4ed2-a9e2-3f6879852d4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188597548 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2188597548
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2904647117
Short name T74
Test name
Test status
Simulation time 345859353 ps
CPU time 0.65 seconds
Started Jul 21 05:35:31 PM PDT 24
Finished Jul 21 05:35:32 PM PDT 24
Peak memory 193692 kb
Host smart-dbd115fa-c23d-4af7-8ebc-e4ce4966646c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904647117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2904647117
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.628240413
Short name T406
Test name
Test status
Simulation time 389476515 ps
CPU time 0.65 seconds
Started Jul 21 05:35:27 PM PDT 24
Finished Jul 21 05:35:28 PM PDT 24
Peak memory 193364 kb
Host smart-4e9f4437-5d7d-49ca-8eff-691b3c16b054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628240413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.628240413
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.20671996
Short name T312
Test name
Test status
Simulation time 396883275 ps
CPU time 0.56 seconds
Started Jul 21 05:35:28 PM PDT 24
Finished Jul 21 05:35:29 PM PDT 24
Peak memory 184036 kb
Host smart-fb8aee08-7e07-43f9-97ee-316120957c01
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20671996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_mem_partial_access.20671996
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3421226173
Short name T287
Test name
Test status
Simulation time 397418313 ps
CPU time 0.66 seconds
Started Jul 21 05:35:27 PM PDT 24
Finished Jul 21 05:35:29 PM PDT 24
Peak memory 184068 kb
Host smart-78b6388f-3b28-4cb6-8c91-b1ea68cd9760
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421226173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3421226173
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3126258321
Short name T408
Test name
Test status
Simulation time 1527313554 ps
CPU time 1.1 seconds
Started Jul 21 05:35:29 PM PDT 24
Finished Jul 21 05:35:30 PM PDT 24
Peak memory 193764 kb
Host smart-6603e46d-8d1c-483e-bb16-5d5c52a8beff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126258321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3126258321
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3576857037
Short name T368
Test name
Test status
Simulation time 732961681 ps
CPU time 2.05 seconds
Started Jul 21 05:35:26 PM PDT 24
Finished Jul 21 05:35:29 PM PDT 24
Peak memory 198948 kb
Host smart-aaed6d95-caae-4a7b-ab76-0497f58788b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576857037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3576857037
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2791615628
Short name T391
Test name
Test status
Simulation time 4509449486 ps
CPU time 5.41 seconds
Started Jul 21 05:35:26 PM PDT 24
Finished Jul 21 05:35:32 PM PDT 24
Peak memory 198144 kb
Host smart-5987823b-f5c4-44f3-af7f-d85e089f405b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791615628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2791615628
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1720994149
Short name T65
Test name
Test status
Simulation time 409835623 ps
CPU time 1.21 seconds
Started Jul 21 05:35:35 PM PDT 24
Finished Jul 21 05:35:37 PM PDT 24
Peak memory 193592 kb
Host smart-5d9559cb-838a-4424-a47f-7bf519494c3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720994149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1720994149
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1596025321
Short name T61
Test name
Test status
Simulation time 580017824 ps
CPU time 1.98 seconds
Started Jul 21 05:35:37 PM PDT 24
Finished Jul 21 05:35:40 PM PDT 24
Peak memory 192440 kb
Host smart-1965ec10-6afb-4529-beb7-6afcc347e4bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596025321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1596025321
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2390943755
Short name T320
Test name
Test status
Simulation time 971786299 ps
CPU time 1.82 seconds
Started Jul 21 05:35:33 PM PDT 24
Finished Jul 21 05:35:35 PM PDT 24
Peak memory 184044 kb
Host smart-1ca92ac3-cfb5-474d-b7ef-0d5f3257acc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390943755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2390943755
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3613970115
Short name T401
Test name
Test status
Simulation time 540352644 ps
CPU time 1.03 seconds
Started Jul 21 05:35:34 PM PDT 24
Finished Jul 21 05:35:36 PM PDT 24
Peak memory 197708 kb
Host smart-1c487d48-7f35-4eb7-a0da-67cc88d8ceda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613970115 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3613970115
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2541061476
Short name T62
Test name
Test status
Simulation time 399803860 ps
CPU time 0.72 seconds
Started Jul 21 05:35:37 PM PDT 24
Finished Jul 21 05:35:38 PM PDT 24
Peak memory 193712 kb
Host smart-6bd79910-847e-44b9-815b-6b5784883fff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541061476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2541061476
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3355389944
Short name T397
Test name
Test status
Simulation time 639055062 ps
CPU time 0.57 seconds
Started Jul 21 05:35:35 PM PDT 24
Finished Jul 21 05:35:36 PM PDT 24
Peak memory 184168 kb
Host smart-c2cf0cb6-a514-4d39-ad06-0c4cefca4751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355389944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3355389944
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.394326885
Short name T341
Test name
Test status
Simulation time 486929031 ps
CPU time 1.15 seconds
Started Jul 21 05:35:34 PM PDT 24
Finished Jul 21 05:35:35 PM PDT 24
Peak memory 184000 kb
Host smart-3b05854e-546e-4d52-bd95-fdcbfa62bf30
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394326885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.394326885
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.336646777
Short name T348
Test name
Test status
Simulation time 391192799 ps
CPU time 0.62 seconds
Started Jul 21 05:35:32 PM PDT 24
Finished Jul 21 05:35:33 PM PDT 24
Peak memory 184068 kb
Host smart-c8d5f9c9-675d-4b44-94c0-30926adfb74c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336646777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.336646777
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.947075820
Short name T76
Test name
Test status
Simulation time 2726633338 ps
CPU time 2.41 seconds
Started Jul 21 05:35:34 PM PDT 24
Finished Jul 21 05:35:37 PM PDT 24
Peak memory 194280 kb
Host smart-73e9003b-b659-4e2b-80ce-f5c30c3d3e24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947075820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.947075820
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3983023879
Short name T350
Test name
Test status
Simulation time 301379791 ps
CPU time 1.95 seconds
Started Jul 21 05:35:29 PM PDT 24
Finished Jul 21 05:35:31 PM PDT 24
Peak memory 199000 kb
Host smart-41a2e951-9212-4fc1-9542-b186cf4c5635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983023879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3983023879
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1672761020
Short name T358
Test name
Test status
Simulation time 4418895151 ps
CPU time 7.2 seconds
Started Jul 21 05:35:30 PM PDT 24
Finished Jul 21 05:35:37 PM PDT 24
Peak memory 198340 kb
Host smart-33175688-ce80-44dc-8318-ff9fd7fed1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672761020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1672761020
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2954046836
Short name T328
Test name
Test status
Simulation time 524017218 ps
CPU time 0.98 seconds
Started Jul 21 05:35:53 PM PDT 24
Finished Jul 21 05:35:54 PM PDT 24
Peak memory 198452 kb
Host smart-6dc13356-3a13-4cb5-9521-d742d811655a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954046836 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2954046836
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2423622372
Short name T57
Test name
Test status
Simulation time 520324987 ps
CPU time 0.75 seconds
Started Jul 21 05:35:48 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 193612 kb
Host smart-aa439b4d-8d29-4641-9046-808c6a722748
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423622372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2423622372
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.678454023
Short name T308
Test name
Test status
Simulation time 409205476 ps
CPU time 0.69 seconds
Started Jul 21 05:35:49 PM PDT 24
Finished Jul 21 05:35:51 PM PDT 24
Peak memory 183988 kb
Host smart-ef8b5fe7-da2d-4989-aa9f-d467b01094ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678454023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.678454023
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3477883135
Short name T380
Test name
Test status
Simulation time 1279211271 ps
CPU time 2.86 seconds
Started Jul 21 05:35:46 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 184160 kb
Host smart-75174a20-4422-41dd-89d4-0f8981f37ef3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477883135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3477883135
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.963106215
Short name T309
Test name
Test status
Simulation time 381502302 ps
CPU time 1.89 seconds
Started Jul 21 05:35:48 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 199060 kb
Host smart-f8f8c589-cf04-4e53-bc75-ea75a526c1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963106215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.963106215
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4286560561
Short name T402
Test name
Test status
Simulation time 367432522 ps
CPU time 0.77 seconds
Started Jul 21 05:35:59 PM PDT 24
Finished Jul 21 05:36:00 PM PDT 24
Peak memory 196408 kb
Host smart-72badc5b-9332-4f89-98f7-264a7e2d2f84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286560561 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4286560561
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.779320979
Short name T56
Test name
Test status
Simulation time 442849813 ps
CPU time 1.21 seconds
Started Jul 21 05:35:54 PM PDT 24
Finished Jul 21 05:35:56 PM PDT 24
Peak memory 192436 kb
Host smart-270ef505-1b66-4d8b-91ac-e531e5dc2463
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779320979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.779320979
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1239141885
Short name T284
Test name
Test status
Simulation time 516405410 ps
CPU time 0.91 seconds
Started Jul 21 05:35:56 PM PDT 24
Finished Jul 21 05:35:58 PM PDT 24
Peak memory 184084 kb
Host smart-4e26563f-5bd2-4281-8d3e-c991c2a7f02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239141885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1239141885
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.159084852
Short name T73
Test name
Test status
Simulation time 2011033144 ps
CPU time 4.34 seconds
Started Jul 21 05:35:56 PM PDT 24
Finished Jul 21 05:36:00 PM PDT 24
Peak memory 194384 kb
Host smart-e21acc89-7ec4-41c2-839b-8c383076d50a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159084852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.159084852
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.688793356
Short name T370
Test name
Test status
Simulation time 441777584 ps
CPU time 2.67 seconds
Started Jul 21 05:35:53 PM PDT 24
Finished Jul 21 05:35:56 PM PDT 24
Peak memory 198912 kb
Host smart-a2e6e37e-7086-42e6-bf3c-60cf9c5a6a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688793356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.688793356
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2384459642
Short name T326
Test name
Test status
Simulation time 4938538922 ps
CPU time 1.56 seconds
Started Jul 21 05:35:57 PM PDT 24
Finished Jul 21 05:35:58 PM PDT 24
Peak memory 198084 kb
Host smart-a5fb2755-bc71-4b3a-b76d-390ff94f410b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384459642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2384459642
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3821904784
Short name T363
Test name
Test status
Simulation time 516643783 ps
CPU time 0.7 seconds
Started Jul 21 05:35:53 PM PDT 24
Finished Jul 21 05:35:54 PM PDT 24
Peak memory 196424 kb
Host smart-65f0a6a3-fa62-4f9e-a3f4-f2ea82e76f7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821904784 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3821904784
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3095941681
Short name T369
Test name
Test status
Simulation time 411728171 ps
CPU time 0.86 seconds
Started Jul 21 05:35:53 PM PDT 24
Finished Jul 21 05:35:55 PM PDT 24
Peak memory 193296 kb
Host smart-ab3f6f5a-0ac5-4fa8-bb86-ab1c7d43085a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095941681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3095941681
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.312777874
Short name T345
Test name
Test status
Simulation time 276428999 ps
CPU time 0.91 seconds
Started Jul 21 05:35:54 PM PDT 24
Finished Jul 21 05:35:56 PM PDT 24
Peak memory 184136 kb
Host smart-11074b71-eed3-40c2-ac55-a526ef63958f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312777874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.312777874
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1098620099
Short name T72
Test name
Test status
Simulation time 1239523590 ps
CPU time 1 seconds
Started Jul 21 05:35:54 PM PDT 24
Finished Jul 21 05:35:56 PM PDT 24
Peak memory 193672 kb
Host smart-4e60c05d-604f-4893-9374-f61a488bd73e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098620099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1098620099
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1350394677
Short name T352
Test name
Test status
Simulation time 480191453 ps
CPU time 2 seconds
Started Jul 21 05:35:55 PM PDT 24
Finished Jul 21 05:35:57 PM PDT 24
Peak memory 198924 kb
Host smart-84c34613-6d11-4a01-9446-05ef45a63230
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350394677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1350394677
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1127681183
Short name T381
Test name
Test status
Simulation time 416476959 ps
CPU time 0.99 seconds
Started Jul 21 05:35:53 PM PDT 24
Finished Jul 21 05:35:54 PM PDT 24
Peak memory 198788 kb
Host smart-ac3bd249-2396-4b40-98f3-fae87e8fd9a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127681183 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1127681183
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.955952005
Short name T294
Test name
Test status
Simulation time 329234954 ps
CPU time 0.67 seconds
Started Jul 21 05:35:56 PM PDT 24
Finished Jul 21 05:35:57 PM PDT 24
Peak memory 192444 kb
Host smart-671a457f-9a55-44fb-8a1d-6fad3aa2f701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955952005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.955952005
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.423828016
Short name T335
Test name
Test status
Simulation time 355514394 ps
CPU time 1.04 seconds
Started Jul 21 05:35:54 PM PDT 24
Finished Jul 21 05:35:56 PM PDT 24
Peak memory 184112 kb
Host smart-ada63f59-5d30-44fc-bc34-2f124b79be5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423828016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.423828016
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.828113511
Short name T69
Test name
Test status
Simulation time 1508206036 ps
CPU time 2.58 seconds
Started Jul 21 05:35:53 PM PDT 24
Finished Jul 21 05:35:56 PM PDT 24
Peak memory 194520 kb
Host smart-67ce12c3-fdf4-4406-8079-ca1918927598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828113511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.828113511
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3126210444
Short name T311
Test name
Test status
Simulation time 370275238 ps
CPU time 1.82 seconds
Started Jul 21 05:35:55 PM PDT 24
Finished Jul 21 05:35:57 PM PDT 24
Peak memory 198860 kb
Host smart-ee2075cb-811e-47b8-83ee-81316dc4b3fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126210444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3126210444
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.175739061
Short name T30
Test name
Test status
Simulation time 7907188033 ps
CPU time 4.31 seconds
Started Jul 21 05:35:54 PM PDT 24
Finished Jul 21 05:35:58 PM PDT 24
Peak memory 198556 kb
Host smart-8bcbfa29-89cc-44ae-ae1b-a11af2e99ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175739061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.175739061
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1809412478
Short name T413
Test name
Test status
Simulation time 491400099 ps
CPU time 1.04 seconds
Started Jul 21 05:35:54 PM PDT 24
Finished Jul 21 05:35:56 PM PDT 24
Peak memory 197952 kb
Host smart-4f60bae3-31f0-4adf-ac9c-6437b394397a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809412478 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1809412478
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1025532040
Short name T59
Test name
Test status
Simulation time 493329952 ps
CPU time 1.25 seconds
Started Jul 21 05:35:52 PM PDT 24
Finished Jul 21 05:35:54 PM PDT 24
Peak memory 193312 kb
Host smart-8187dd57-abe3-4671-bed7-bdc328744e39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025532040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1025532040
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1686002493
Short name T371
Test name
Test status
Simulation time 307440244 ps
CPU time 0.73 seconds
Started Jul 21 05:35:58 PM PDT 24
Finished Jul 21 05:35:59 PM PDT 24
Peak memory 193284 kb
Host smart-b7303dd7-e3f2-4d05-9304-bdbc9f7d57a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686002493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1686002493
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1172220378
Short name T388
Test name
Test status
Simulation time 1096538248 ps
CPU time 3.66 seconds
Started Jul 21 05:35:56 PM PDT 24
Finished Jul 21 05:36:00 PM PDT 24
Peak memory 194616 kb
Host smart-44d778cd-55ba-41a0-852f-1f5a980e4e1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172220378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1172220378
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.184159720
Short name T319
Test name
Test status
Simulation time 633704649 ps
CPU time 2.95 seconds
Started Jul 21 05:35:58 PM PDT 24
Finished Jul 21 05:36:01 PM PDT 24
Peak memory 198900 kb
Host smart-408d777d-cfd9-495e-8de0-249aa24e72c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184159720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.184159720
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.377486546
Short name T192
Test name
Test status
Simulation time 8208006727 ps
CPU time 14.35 seconds
Started Jul 21 05:35:53 PM PDT 24
Finished Jul 21 05:36:08 PM PDT 24
Peak memory 198744 kb
Host smart-8edc67da-6d94-4a70-86c0-59ae13a7a15c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377486546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.377486546
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1858672472
Short name T403
Test name
Test status
Simulation time 467509045 ps
CPU time 1.41 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:03 PM PDT 24
Peak memory 196420 kb
Host smart-cf6ed6af-1ffa-4974-8ce3-2e63be430be7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858672472 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1858672472
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.627730821
Short name T409
Test name
Test status
Simulation time 359569229 ps
CPU time 0.83 seconds
Started Jul 21 05:36:02 PM PDT 24
Finished Jul 21 05:36:03 PM PDT 24
Peak memory 193304 kb
Host smart-67a995fe-3cfd-4ebb-ae04-aa56fa6c02e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627730821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.627730821
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.452395926
Short name T377
Test name
Test status
Simulation time 299210063 ps
CPU time 1.03 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:03 PM PDT 24
Peak memory 193384 kb
Host smart-65483298-73ce-4564-8803-1a4e817a0b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452395926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.452395926
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1081316862
Short name T374
Test name
Test status
Simulation time 1520174283 ps
CPU time 1.06 seconds
Started Jul 21 05:35:59 PM PDT 24
Finished Jul 21 05:36:01 PM PDT 24
Peak memory 193384 kb
Host smart-f839ad0d-cbd9-4b7c-9c67-e38a872949fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081316862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1081316862
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2968424860
Short name T395
Test name
Test status
Simulation time 299613117 ps
CPU time 1.52 seconds
Started Jul 21 05:35:56 PM PDT 24
Finished Jul 21 05:35:58 PM PDT 24
Peak memory 199152 kb
Host smart-c3422eae-a701-4616-be17-02d189a55efa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968424860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2968424860
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1271250123
Short name T389
Test name
Test status
Simulation time 4081640873 ps
CPU time 6.17 seconds
Started Jul 21 05:35:59 PM PDT 24
Finished Jul 21 05:36:06 PM PDT 24
Peak memory 198356 kb
Host smart-5a04c24d-c898-476d-83c5-364c2eab05b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271250123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1271250123
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1029644650
Short name T28
Test name
Test status
Simulation time 841066575 ps
CPU time 0.95 seconds
Started Jul 21 05:35:59 PM PDT 24
Finished Jul 21 05:36:00 PM PDT 24
Peak memory 198792 kb
Host smart-4d8d8326-0018-4855-9e09-93dee9ef24a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029644650 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1029644650
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2757373843
Short name T53
Test name
Test status
Simulation time 556903629 ps
CPU time 0.82 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:03 PM PDT 24
Peak memory 193844 kb
Host smart-05a5d11d-4195-46a1-a999-8cb9bc8684e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757373843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2757373843
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2374122200
Short name T372
Test name
Test status
Simulation time 445713963 ps
CPU time 1.19 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:03 PM PDT 24
Peak memory 184152 kb
Host smart-a6328c13-3c49-473c-b41a-493977e66c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374122200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2374122200
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.448924000
Short name T70
Test name
Test status
Simulation time 1571206063 ps
CPU time 1.19 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:03 PM PDT 24
Peak memory 194356 kb
Host smart-cb3d1a3e-d06b-4cd6-a636-1759142e69eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448924000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.448924000
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3303415228
Short name T383
Test name
Test status
Simulation time 569281544 ps
CPU time 1.28 seconds
Started Jul 21 05:36:02 PM PDT 24
Finished Jul 21 05:36:04 PM PDT 24
Peak memory 198764 kb
Host smart-92b6634b-78d4-44c5-90bc-c8518ce30239
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303415228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3303415228
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.556366237
Short name T306
Test name
Test status
Simulation time 8317743790 ps
CPU time 13.8 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:15 PM PDT 24
Peak memory 198576 kb
Host smart-46535256-1ac8-49f4-918c-fac7b0dbbe59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556366237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.556366237
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4031976763
Short name T316
Test name
Test status
Simulation time 541389301 ps
CPU time 1.01 seconds
Started Jul 21 05:35:58 PM PDT 24
Finished Jul 21 05:35:59 PM PDT 24
Peak memory 198620 kb
Host smart-d44e71ab-8d35-4229-9ed0-aab2249ffad3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031976763 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4031976763
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1289366831
Short name T310
Test name
Test status
Simulation time 470560340 ps
CPU time 1.26 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:03 PM PDT 24
Peak memory 184128 kb
Host smart-4d81723b-572e-4cfa-b9f7-e5fa4bedca9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289366831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1289366831
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2417113667
Short name T361
Test name
Test status
Simulation time 1173870028 ps
CPU time 1.34 seconds
Started Jul 21 05:36:02 PM PDT 24
Finished Jul 21 05:36:04 PM PDT 24
Peak memory 193664 kb
Host smart-b3932c4a-ccf8-42b8-859d-c720c89160df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417113667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2417113667
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3849994970
Short name T357
Test name
Test status
Simulation time 543149725 ps
CPU time 1.64 seconds
Started Jul 21 05:36:02 PM PDT 24
Finished Jul 21 05:36:04 PM PDT 24
Peak memory 199076 kb
Host smart-0c9e4b1c-b7e2-41f4-a4d2-47cfd3d6fa65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849994970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3849994970
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2104662800
Short name T333
Test name
Test status
Simulation time 8675563701 ps
CPU time 3.89 seconds
Started Jul 21 05:36:00 PM PDT 24
Finished Jul 21 05:36:04 PM PDT 24
Peak memory 198496 kb
Host smart-5e58c2da-d461-4f5a-a822-b97c7b9aaf75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104662800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2104662800
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1574756957
Short name T399
Test name
Test status
Simulation time 572845600 ps
CPU time 0.99 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:03 PM PDT 24
Peak memory 195948 kb
Host smart-480b30a1-6352-43fc-9b0c-3d563ccb71b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574756957 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1574756957
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3971249182
Short name T411
Test name
Test status
Simulation time 439766497 ps
CPU time 0.7 seconds
Started Jul 21 05:35:59 PM PDT 24
Finished Jul 21 05:36:00 PM PDT 24
Peak memory 193300 kb
Host smart-4d861a63-afc5-46dc-aaec-e98301960da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971249182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3971249182
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3070345000
Short name T293
Test name
Test status
Simulation time 270287362 ps
CPU time 0.93 seconds
Started Jul 21 05:36:02 PM PDT 24
Finished Jul 21 05:36:03 PM PDT 24
Peak memory 193336 kb
Host smart-9299bb91-60f9-410e-9053-420d4b655dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070345000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3070345000
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1979761855
Short name T75
Test name
Test status
Simulation time 2833556315 ps
CPU time 3.61 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:06 PM PDT 24
Peak memory 195400 kb
Host smart-4e8dd485-bbd0-450a-8a48-69faae7f3d79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979761855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1979761855
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2055985610
Short name T301
Test name
Test status
Simulation time 559160200 ps
CPU time 1.32 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:02 PM PDT 24
Peak memory 198808 kb
Host smart-b7be427a-2236-40d2-9682-a28153851758
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055985610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2055985610
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.484485234
Short name T29
Test name
Test status
Simulation time 4498628877 ps
CPU time 7.68 seconds
Started Jul 21 05:35:59 PM PDT 24
Finished Jul 21 05:36:07 PM PDT 24
Peak memory 197000 kb
Host smart-3ca00236-e6e8-4605-938b-1fd331912e97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484485234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.484485234
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3880057224
Short name T392
Test name
Test status
Simulation time 407420007 ps
CPU time 0.73 seconds
Started Jul 21 05:36:09 PM PDT 24
Finished Jul 21 05:36:11 PM PDT 24
Peak memory 196320 kb
Host smart-fd59e333-9743-433a-b306-fa4386852434
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880057224 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3880057224
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2020768454
Short name T360
Test name
Test status
Simulation time 331145786 ps
CPU time 1.04 seconds
Started Jul 21 05:36:00 PM PDT 24
Finished Jul 21 05:36:01 PM PDT 24
Peak memory 192412 kb
Host smart-cb6796ef-e531-4056-81ba-4263c2b4f457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020768454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2020768454
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.126684989
Short name T297
Test name
Test status
Simulation time 481146638 ps
CPU time 0.74 seconds
Started Jul 21 05:36:00 PM PDT 24
Finished Jul 21 05:36:01 PM PDT 24
Peak memory 184104 kb
Host smart-69d0929d-389d-46a3-9d14-332db50b56fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126684989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.126684989
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3357403848
Short name T398
Test name
Test status
Simulation time 1351209638 ps
CPU time 2.3 seconds
Started Jul 21 05:36:02 PM PDT 24
Finished Jul 21 05:36:05 PM PDT 24
Peak memory 192308 kb
Host smart-be5ddf89-55b9-411e-ba60-8948516ca2b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357403848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3357403848
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2033874601
Short name T321
Test name
Test status
Simulation time 441895007 ps
CPU time 1.61 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:04 PM PDT 24
Peak memory 199056 kb
Host smart-4f0cf5d6-68e9-443a-9e24-59fd1fdcb3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033874601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2033874601
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1917987383
Short name T307
Test name
Test status
Simulation time 4228574220 ps
CPU time 2.51 seconds
Started Jul 21 05:36:01 PM PDT 24
Finished Jul 21 05:36:05 PM PDT 24
Peak memory 198208 kb
Host smart-b23d3f0d-d474-41b3-94d9-8be789dd389a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917987383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1917987383
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1179029878
Short name T64
Test name
Test status
Simulation time 575985969 ps
CPU time 1.6 seconds
Started Jul 21 05:35:35 PM PDT 24
Finished Jul 21 05:35:37 PM PDT 24
Peak memory 194680 kb
Host smart-cf4971e6-fee8-4cd2-b1e6-30a9635a99a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179029878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1179029878
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.700271728
Short name T32
Test name
Test status
Simulation time 7315194557 ps
CPU time 5.46 seconds
Started Jul 21 05:35:33 PM PDT 24
Finished Jul 21 05:35:39 PM PDT 24
Peak memory 192668 kb
Host smart-87188b67-81ed-45c7-aafc-ec5f4fc72c37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700271728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.700271728
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2359166943
Short name T303
Test name
Test status
Simulation time 798227954 ps
CPU time 0.85 seconds
Started Jul 21 05:35:36 PM PDT 24
Finished Jul 21 05:35:37 PM PDT 24
Peak memory 184156 kb
Host smart-04a41cc2-1bcf-41ed-b0ac-bd3ad308fa68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359166943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2359166943
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2219418132
Short name T317
Test name
Test status
Simulation time 397042499 ps
CPU time 1.32 seconds
Started Jul 21 05:35:38 PM PDT 24
Finished Jul 21 05:35:40 PM PDT 24
Peak memory 196604 kb
Host smart-dbca9555-d550-4195-9ea4-394249ab2271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219418132 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2219418132
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1237363271
Short name T52
Test name
Test status
Simulation time 480594349 ps
CPU time 1.25 seconds
Started Jul 21 05:35:34 PM PDT 24
Finished Jul 21 05:35:36 PM PDT 24
Peak memory 194308 kb
Host smart-ebe548be-3e1b-4f22-976c-e373d65cdcf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237363271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1237363271
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2406178466
Short name T290
Test name
Test status
Simulation time 525884900 ps
CPU time 0.92 seconds
Started Jul 21 05:35:35 PM PDT 24
Finished Jul 21 05:35:36 PM PDT 24
Peak memory 184148 kb
Host smart-6967faba-7e45-4201-aeaf-9d0336401153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406178466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2406178466
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2121947571
Short name T359
Test name
Test status
Simulation time 502461792 ps
CPU time 0.65 seconds
Started Jul 21 05:35:34 PM PDT 24
Finished Jul 21 05:35:35 PM PDT 24
Peak memory 184148 kb
Host smart-b0fe98a6-cf79-4b54-8935-e9a284f57699
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121947571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2121947571
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.473401861
Short name T353
Test name
Test status
Simulation time 515445253 ps
CPU time 0.68 seconds
Started Jul 21 05:35:37 PM PDT 24
Finished Jul 21 05:35:39 PM PDT 24
Peak memory 184100 kb
Host smart-24ca2ec2-e47e-4d92-a584-ce0da973cf1a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473401861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.473401861
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2437057645
Short name T68
Test name
Test status
Simulation time 1013488955 ps
CPU time 1.85 seconds
Started Jul 21 05:35:35 PM PDT 24
Finished Jul 21 05:35:37 PM PDT 24
Peak memory 193380 kb
Host smart-5599cd9e-02d7-49a9-bbde-dc611d49fe11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437057645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2437057645
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1219762791
Short name T421
Test name
Test status
Simulation time 463057067 ps
CPU time 1.56 seconds
Started Jul 21 05:35:37 PM PDT 24
Finished Jul 21 05:35:39 PM PDT 24
Peak memory 198944 kb
Host smart-60c310de-9228-40a7-b6e6-15b0e592c77b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219762791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1219762791
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2482873488
Short name T339
Test name
Test status
Simulation time 3807041679 ps
CPU time 6.21 seconds
Started Jul 21 05:35:34 PM PDT 24
Finished Jul 21 05:35:41 PM PDT 24
Peak memory 198268 kb
Host smart-0e68e7fe-4c80-4278-a4bc-565d1c4312fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482873488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2482873488
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.495166285
Short name T299
Test name
Test status
Simulation time 489474668 ps
CPU time 1.22 seconds
Started Jul 21 05:36:10 PM PDT 24
Finished Jul 21 05:36:11 PM PDT 24
Peak memory 184112 kb
Host smart-64d51b14-bc56-438e-af5f-7f8a65033aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495166285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.495166285
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1568830745
Short name T417
Test name
Test status
Simulation time 352035372 ps
CPU time 0.77 seconds
Started Jul 21 05:36:08 PM PDT 24
Finished Jul 21 05:36:09 PM PDT 24
Peak memory 193356 kb
Host smart-96e015c9-b3f7-48c0-8ca1-c8217c6accc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568830745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1568830745
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2788930560
Short name T376
Test name
Test status
Simulation time 359803462 ps
CPU time 0.86 seconds
Started Jul 21 05:36:07 PM PDT 24
Finished Jul 21 05:36:08 PM PDT 24
Peak memory 184148 kb
Host smart-1d177af8-dc51-45bd-a128-c861fb8bdae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788930560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2788930560
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.111411059
Short name T285
Test name
Test status
Simulation time 268051351 ps
CPU time 0.95 seconds
Started Jul 21 05:36:09 PM PDT 24
Finished Jul 21 05:36:10 PM PDT 24
Peak memory 184156 kb
Host smart-1a6b86f8-9c99-4eef-a330-5a8d64bbe24d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111411059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.111411059
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2677344046
Short name T418
Test name
Test status
Simulation time 488291581 ps
CPU time 0.7 seconds
Started Jul 21 05:36:07 PM PDT 24
Finished Jul 21 05:36:08 PM PDT 24
Peak memory 193360 kb
Host smart-e28c9814-2fb1-4eab-8874-7b522c5a24c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677344046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2677344046
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1907086180
Short name T289
Test name
Test status
Simulation time 397519736 ps
CPU time 0.89 seconds
Started Jul 21 05:36:07 PM PDT 24
Finished Jul 21 05:36:08 PM PDT 24
Peak memory 184140 kb
Host smart-91298b65-f673-4da2-8a97-49d3998b26d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907086180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1907086180
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3314151202
Short name T314
Test name
Test status
Simulation time 476496347 ps
CPU time 0.72 seconds
Started Jul 21 05:36:08 PM PDT 24
Finished Jul 21 05:36:09 PM PDT 24
Peak memory 184160 kb
Host smart-266c16de-eef1-446f-bb80-be6c501ca5f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314151202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3314151202
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.507933156
Short name T329
Test name
Test status
Simulation time 315465442 ps
CPU time 0.63 seconds
Started Jul 21 05:36:09 PM PDT 24
Finished Jul 21 05:36:10 PM PDT 24
Peak memory 184148 kb
Host smart-1f3eafd8-e726-4948-aa38-aa2e36d4bf03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507933156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.507933156
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3246216359
Short name T286
Test name
Test status
Simulation time 319843184 ps
CPU time 0.98 seconds
Started Jul 21 05:36:08 PM PDT 24
Finished Jul 21 05:36:10 PM PDT 24
Peak memory 184084 kb
Host smart-791ab8cd-7566-4add-ade3-f14d2167aa08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246216359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3246216359
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.66294494
Short name T338
Test name
Test status
Simulation time 472695174 ps
CPU time 1.28 seconds
Started Jul 21 05:36:11 PM PDT 24
Finished Jul 21 05:36:13 PM PDT 24
Peak memory 184168 kb
Host smart-874e489e-49d4-4300-b262-303ff075aa7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66294494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.66294494
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.916539900
Short name T386
Test name
Test status
Simulation time 487788777 ps
CPU time 1.4 seconds
Started Jul 21 05:35:39 PM PDT 24
Finished Jul 21 05:35:41 PM PDT 24
Peak memory 184112 kb
Host smart-3b35ef13-dd61-4a21-837a-1bf49b0c085b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916539900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.916539900
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.428802839
Short name T194
Test name
Test status
Simulation time 13747785692 ps
CPU time 33.67 seconds
Started Jul 21 05:35:37 PM PDT 24
Finished Jul 21 05:36:11 PM PDT 24
Peak memory 196900 kb
Host smart-e27d9667-b6f2-4f2f-ad12-64f9a4754330
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428802839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.428802839
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3421954010
Short name T382
Test name
Test status
Simulation time 1083450382 ps
CPU time 1.31 seconds
Started Jul 21 05:35:41 PM PDT 24
Finished Jul 21 05:35:43 PM PDT 24
Peak memory 193772 kb
Host smart-440bd9b5-df17-4aa8-a3c2-9598e5fd56b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421954010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3421954010
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2210131071
Short name T354
Test name
Test status
Simulation time 457989707 ps
CPU time 1.22 seconds
Started Jul 21 05:35:41 PM PDT 24
Finished Jul 21 05:35:43 PM PDT 24
Peak memory 196484 kb
Host smart-8b91d82b-b280-4e62-8160-7b501aea6b34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210131071 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2210131071
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2641872154
Short name T405
Test name
Test status
Simulation time 524030041 ps
CPU time 1.21 seconds
Started Jul 21 05:35:38 PM PDT 24
Finished Jul 21 05:35:40 PM PDT 24
Peak memory 193356 kb
Host smart-d856ae1a-47d3-4c38-89b0-c8e5f2b5098e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641872154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2641872154
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4033632760
Short name T325
Test name
Test status
Simulation time 350458770 ps
CPU time 0.69 seconds
Started Jul 21 05:35:41 PM PDT 24
Finished Jul 21 05:35:43 PM PDT 24
Peak memory 184088 kb
Host smart-8c9984ba-b4c0-465a-9544-7fb0d7edc9bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033632760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4033632760
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3854742948
Short name T334
Test name
Test status
Simulation time 298068932 ps
CPU time 0.71 seconds
Started Jul 21 05:35:40 PM PDT 24
Finished Jul 21 05:35:41 PM PDT 24
Peak memory 184012 kb
Host smart-731cf0cb-ea9a-4a71-bc10-764b72e22d39
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854742948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3854742948
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1718479970
Short name T331
Test name
Test status
Simulation time 457432131 ps
CPU time 0.57 seconds
Started Jul 21 05:35:41 PM PDT 24
Finished Jul 21 05:35:42 PM PDT 24
Peak memory 184088 kb
Host smart-1f116f5d-5256-42c8-8207-a74c0df9e178
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718479970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1718479970
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4284843251
Short name T404
Test name
Test status
Simulation time 1545571101 ps
CPU time 2.47 seconds
Started Jul 21 05:35:39 PM PDT 24
Finished Jul 21 05:35:42 PM PDT 24
Peak memory 184124 kb
Host smart-d98bc65a-9b78-4c54-aaa9-7a263b774cb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284843251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.4284843251
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.750762898
Short name T304
Test name
Test status
Simulation time 581235364 ps
CPU time 2.76 seconds
Started Jul 21 05:35:33 PM PDT 24
Finished Jul 21 05:35:36 PM PDT 24
Peak memory 198976 kb
Host smart-a865b51b-932b-4cce-8656-1d64e534a870
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750762898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.750762898
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2955547234
Short name T323
Test name
Test status
Simulation time 4516137839 ps
CPU time 2.74 seconds
Started Jul 21 05:35:34 PM PDT 24
Finished Jul 21 05:35:37 PM PDT 24
Peak memory 198264 kb
Host smart-1597abdb-b0d7-4864-abab-52a513e5dc58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955547234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2955547234
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3653946066
Short name T340
Test name
Test status
Simulation time 426320868 ps
CPU time 1.14 seconds
Started Jul 21 05:36:08 PM PDT 24
Finished Jul 21 05:36:10 PM PDT 24
Peak memory 184140 kb
Host smart-a149227c-a0f3-4083-93cc-7a01e03dc31f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653946066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3653946066
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3659609428
Short name T349
Test name
Test status
Simulation time 415827410 ps
CPU time 0.72 seconds
Started Jul 21 05:36:11 PM PDT 24
Finished Jul 21 05:36:13 PM PDT 24
Peak memory 193384 kb
Host smart-308754cc-f9c2-47f9-8830-21a79c0f2867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659609428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3659609428
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1594186034
Short name T343
Test name
Test status
Simulation time 347226655 ps
CPU time 0.63 seconds
Started Jul 21 05:36:10 PM PDT 24
Finished Jul 21 05:36:11 PM PDT 24
Peak memory 184196 kb
Host smart-1d8ec2a0-5c9d-4fec-98ac-d1b49679fd11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594186034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1594186034
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.361361043
Short name T416
Test name
Test status
Simulation time 377185675 ps
CPU time 0.73 seconds
Started Jul 21 05:36:05 PM PDT 24
Finished Jul 21 05:36:06 PM PDT 24
Peak memory 184112 kb
Host smart-d01a4dc7-ccdb-44d4-8766-691d871df704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361361043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.361361043
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2053332437
Short name T295
Test name
Test status
Simulation time 266263656 ps
CPU time 0.96 seconds
Started Jul 21 05:36:06 PM PDT 24
Finished Jul 21 05:36:08 PM PDT 24
Peak memory 184064 kb
Host smart-a8dc48b5-9eeb-4a49-a53e-fbacac9ec308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053332437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2053332437
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3614025701
Short name T296
Test name
Test status
Simulation time 361506591 ps
CPU time 1 seconds
Started Jul 21 05:36:09 PM PDT 24
Finished Jul 21 05:36:10 PM PDT 24
Peak memory 184220 kb
Host smart-d18076e4-9fc4-457f-87a9-61f665f8db9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614025701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3614025701
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.151083616
Short name T351
Test name
Test status
Simulation time 408505355 ps
CPU time 0.69 seconds
Started Jul 21 05:36:07 PM PDT 24
Finished Jul 21 05:36:08 PM PDT 24
Peak memory 184168 kb
Host smart-04a298ef-e3a6-4737-9ffc-3972608002df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151083616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.151083616
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.260784510
Short name T346
Test name
Test status
Simulation time 391997767 ps
CPU time 0.68 seconds
Started Jul 21 05:36:07 PM PDT 24
Finished Jul 21 05:36:08 PM PDT 24
Peak memory 184144 kb
Host smart-f0549f71-d78f-45d6-a21a-48ed35d9e25a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260784510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.260784510
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.659384252
Short name T390
Test name
Test status
Simulation time 319339947 ps
CPU time 0.66 seconds
Started Jul 21 05:36:08 PM PDT 24
Finished Jul 21 05:36:10 PM PDT 24
Peak memory 184048 kb
Host smart-6d66a8b0-f03f-4c1b-8e12-e53675552144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659384252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.659384252
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1081804637
Short name T292
Test name
Test status
Simulation time 315610255 ps
CPU time 0.89 seconds
Started Jul 21 05:36:05 PM PDT 24
Finished Jul 21 05:36:07 PM PDT 24
Peak memory 184116 kb
Host smart-f1975740-0a04-4102-abe6-1cd6f96b7812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081804637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1081804637
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3698017990
Short name T60
Test name
Test status
Simulation time 338384540 ps
CPU time 0.9 seconds
Started Jul 21 05:35:50 PM PDT 24
Finished Jul 21 05:35:52 PM PDT 24
Peak memory 193692 kb
Host smart-f598a771-581a-42e7-ab4d-ede40d5a3223
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698017990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3698017990
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1560063831
Short name T63
Test name
Test status
Simulation time 5541572156 ps
CPU time 8.34 seconds
Started Jul 21 05:35:49 PM PDT 24
Finished Jul 21 05:35:59 PM PDT 24
Peak memory 192580 kb
Host smart-02ad64a9-4916-4470-ac21-6918d1a4912e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560063831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1560063831
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.165940128
Short name T422
Test name
Test status
Simulation time 729730054 ps
CPU time 1.03 seconds
Started Jul 21 05:35:39 PM PDT 24
Finished Jul 21 05:35:41 PM PDT 24
Peak memory 192408 kb
Host smart-069909d5-9a87-47bd-8045-4f88022f1469
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165940128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.165940128
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.623334506
Short name T396
Test name
Test status
Simulation time 388265651 ps
CPU time 0.77 seconds
Started Jul 21 05:35:49 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 196304 kb
Host smart-d23e49d6-4d79-4d9c-a51c-3315817ffc85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623334506 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.623334506
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3029357022
Short name T67
Test name
Test status
Simulation time 387086140 ps
CPU time 1.08 seconds
Started Jul 21 05:35:48 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 194304 kb
Host smart-dd96d3d5-6342-45d3-a45f-c13de72f46d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029357022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3029357022
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1629460249
Short name T313
Test name
Test status
Simulation time 518639198 ps
CPU time 0.68 seconds
Started Jul 21 05:35:41 PM PDT 24
Finished Jul 21 05:35:42 PM PDT 24
Peak memory 184168 kb
Host smart-ef7fea15-f202-4fb3-91cd-48ce7e43f806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629460249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1629460249
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2309148161
Short name T336
Test name
Test status
Simulation time 486651557 ps
CPU time 0.71 seconds
Started Jul 21 05:35:39 PM PDT 24
Finished Jul 21 05:35:40 PM PDT 24
Peak memory 184096 kb
Host smart-b0d82aa8-5917-4626-b2df-881d121cd79d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309148161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2309148161
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1155506336
Short name T420
Test name
Test status
Simulation time 291978414 ps
CPU time 0.84 seconds
Started Jul 21 05:35:40 PM PDT 24
Finished Jul 21 05:35:41 PM PDT 24
Peak memory 183988 kb
Host smart-19abc422-a30e-4d28-b395-a80304449da6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155506336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1155506336
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.404522790
Short name T71
Test name
Test status
Simulation time 1530503829 ps
CPU time 1.01 seconds
Started Jul 21 05:35:51 PM PDT 24
Finished Jul 21 05:35:52 PM PDT 24
Peak memory 192248 kb
Host smart-21745913-5ded-4016-b09c-ac39269f05b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404522790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.404522790
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2850178286
Short name T419
Test name
Test status
Simulation time 622688887 ps
CPU time 3.16 seconds
Started Jul 21 05:35:39 PM PDT 24
Finished Jul 21 05:35:43 PM PDT 24
Peak memory 198984 kb
Host smart-87b8c22b-9fd1-4a0f-b846-bf54612f4624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850178286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2850178286
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.575112271
Short name T300
Test name
Test status
Simulation time 7880913143 ps
CPU time 12.43 seconds
Started Jul 21 05:35:41 PM PDT 24
Finished Jul 21 05:35:54 PM PDT 24
Peak memory 198632 kb
Host smart-126326a1-00a9-43ba-a16c-99823ab09f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575112271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.575112271
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3490895036
Short name T332
Test name
Test status
Simulation time 448629779 ps
CPU time 0.89 seconds
Started Jul 21 05:36:09 PM PDT 24
Finished Jul 21 05:36:10 PM PDT 24
Peak memory 184064 kb
Host smart-4e3138e6-35dc-4d5f-a162-529556091dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490895036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3490895036
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.964238626
Short name T414
Test name
Test status
Simulation time 446168192 ps
CPU time 0.68 seconds
Started Jul 21 05:36:10 PM PDT 24
Finished Jul 21 05:36:11 PM PDT 24
Peak memory 184084 kb
Host smart-fc9e3b5a-e3fa-4bac-8d46-e7c03863ea37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964238626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.964238626
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2727465122
Short name T373
Test name
Test status
Simulation time 443406867 ps
CPU time 0.63 seconds
Started Jul 21 05:36:15 PM PDT 24
Finished Jul 21 05:36:16 PM PDT 24
Peak memory 184156 kb
Host smart-586db7e3-7123-44ee-a3c8-a4175295c5c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727465122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2727465122
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1138122992
Short name T410
Test name
Test status
Simulation time 333708780 ps
CPU time 1.09 seconds
Started Jul 21 05:36:12 PM PDT 24
Finished Jul 21 05:36:14 PM PDT 24
Peak memory 184052 kb
Host smart-be07bc14-309f-490b-b9df-da1dda48a45b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138122992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1138122992
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1782935867
Short name T324
Test name
Test status
Simulation time 397446435 ps
CPU time 0.68 seconds
Started Jul 21 05:36:13 PM PDT 24
Finished Jul 21 05:36:15 PM PDT 24
Peak memory 184160 kb
Host smart-7a302f7f-4ea2-4ce4-a452-1c6378d25613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782935867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1782935867
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3297986908
Short name T288
Test name
Test status
Simulation time 397914575 ps
CPU time 0.61 seconds
Started Jul 21 05:36:17 PM PDT 24
Finished Jul 21 05:36:18 PM PDT 24
Peak memory 184068 kb
Host smart-50e7cfa2-0109-454b-904e-7a19a80f50f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297986908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3297986908
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1078394408
Short name T318
Test name
Test status
Simulation time 500803517 ps
CPU time 0.99 seconds
Started Jul 21 05:36:14 PM PDT 24
Finished Jul 21 05:36:16 PM PDT 24
Peak memory 184160 kb
Host smart-f113eb58-5379-461d-b8aa-dd22f9a84c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078394408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1078394408
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1702861415
Short name T305
Test name
Test status
Simulation time 294819961 ps
CPU time 0.93 seconds
Started Jul 21 05:36:15 PM PDT 24
Finished Jul 21 05:36:17 PM PDT 24
Peak memory 184156 kb
Host smart-4ac798e5-1d0e-40e9-b4a2-27ad2a860ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702861415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1702861415
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3703445203
Short name T387
Test name
Test status
Simulation time 418342230 ps
CPU time 0.63 seconds
Started Jul 21 05:36:14 PM PDT 24
Finished Jul 21 05:36:16 PM PDT 24
Peak memory 193364 kb
Host smart-67287278-2d06-4f16-9d50-97b2aa5737b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703445203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3703445203
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1111748056
Short name T407
Test name
Test status
Simulation time 284701666 ps
CPU time 0.97 seconds
Started Jul 21 05:36:17 PM PDT 24
Finished Jul 21 05:36:19 PM PDT 24
Peak memory 184068 kb
Host smart-398444a9-bd9c-4b47-91b0-82b141730148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111748056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1111748056
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.4144718276
Short name T344
Test name
Test status
Simulation time 830038208 ps
CPU time 0.88 seconds
Started Jul 21 05:35:49 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 198048 kb
Host smart-30583bcb-bfd0-4be1-8504-8bea382bb3d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144718276 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.4144718276
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3977147122
Short name T51
Test name
Test status
Simulation time 451349158 ps
CPU time 0.71 seconds
Started Jul 21 05:35:50 PM PDT 24
Finished Jul 21 05:35:52 PM PDT 24
Peak memory 192268 kb
Host smart-c2894876-2286-457e-888f-8a7139f65d92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977147122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3977147122
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2107452086
Short name T322
Test name
Test status
Simulation time 528474157 ps
CPU time 0.72 seconds
Started Jul 21 05:35:48 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 184068 kb
Host smart-6f5a8cfa-2b94-47e5-bfd5-3ab6622fbed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107452086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2107452086
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1333984697
Short name T362
Test name
Test status
Simulation time 1557430790 ps
CPU time 0.93 seconds
Started Jul 21 05:35:48 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 194064 kb
Host smart-dfdc735e-b401-478f-b320-5fbbb3a4820d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333984697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1333984697
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2892532769
Short name T367
Test name
Test status
Simulation time 508848003 ps
CPU time 1.79 seconds
Started Jul 21 05:35:46 PM PDT 24
Finished Jul 21 05:35:49 PM PDT 24
Peak memory 198792 kb
Host smart-89b39442-79ff-4e2b-af5e-7f7887c9ee48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892532769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2892532769
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.4142252053
Short name T330
Test name
Test status
Simulation time 8423651403 ps
CPU time 13.84 seconds
Started Jul 21 05:35:50 PM PDT 24
Finished Jul 21 05:36:05 PM PDT 24
Peak memory 198608 kb
Host smart-3bda0227-3f26-4b07-bf7d-d344ecd610d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142252053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.4142252053
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1092335771
Short name T412
Test name
Test status
Simulation time 591782377 ps
CPU time 1.47 seconds
Started Jul 21 05:35:52 PM PDT 24
Finished Jul 21 05:35:54 PM PDT 24
Peak memory 196364 kb
Host smart-3d8aa93d-1bfa-4d37-b1fb-eb0adebd17f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092335771 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1092335771
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.260070467
Short name T365
Test name
Test status
Simulation time 422918758 ps
CPU time 0.71 seconds
Started Jul 21 05:35:48 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 193344 kb
Host smart-ccd7d042-21fd-4b0f-88d0-a459667cd88c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260070467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.260070467
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2902550089
Short name T356
Test name
Test status
Simulation time 309628868 ps
CPU time 0.75 seconds
Started Jul 21 05:35:47 PM PDT 24
Finished Jul 21 05:35:48 PM PDT 24
Peak memory 184152 kb
Host smart-7be5f5fc-60d7-4851-9ff0-0c00f6a813e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902550089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2902550089
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2651753118
Short name T384
Test name
Test status
Simulation time 1069817548 ps
CPU time 1.82 seconds
Started Jul 21 05:35:45 PM PDT 24
Finished Jul 21 05:35:48 PM PDT 24
Peak memory 193380 kb
Host smart-a30665f3-d711-4e95-b34d-5ae4a0fa9f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651753118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2651753118
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1599126958
Short name T394
Test name
Test status
Simulation time 653270966 ps
CPU time 1.62 seconds
Started Jul 21 05:35:46 PM PDT 24
Finished Jul 21 05:35:48 PM PDT 24
Peak memory 198960 kb
Host smart-01cc8f7f-a062-4c8a-87a2-9d1ed8c2ba04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599126958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1599126958
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.831797420
Short name T400
Test name
Test status
Simulation time 4397240344 ps
CPU time 4.02 seconds
Started Jul 21 05:35:49 PM PDT 24
Finished Jul 21 05:35:54 PM PDT 24
Peak memory 196732 kb
Host smart-51046d56-f62d-4c47-997a-6dfbca1d2332
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831797420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.831797420
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2491698145
Short name T375
Test name
Test status
Simulation time 481486963 ps
CPU time 1.38 seconds
Started Jul 21 05:35:47 PM PDT 24
Finished Jul 21 05:35:49 PM PDT 24
Peak memory 195692 kb
Host smart-b7805d32-2928-41e0-971b-a3c81015ead3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491698145 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2491698145
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2590945471
Short name T337
Test name
Test status
Simulation time 441377811 ps
CPU time 1.25 seconds
Started Jul 21 05:35:47 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 193268 kb
Host smart-3bbdb580-f744-463f-ba0c-cc7281554c39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590945471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2590945471
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1615464257
Short name T366
Test name
Test status
Simulation time 459716234 ps
CPU time 1.13 seconds
Started Jul 21 05:35:49 PM PDT 24
Finished Jul 21 05:35:51 PM PDT 24
Peak memory 193348 kb
Host smart-16f7b23f-ae76-4e8b-9d17-22b9abb9974b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615464257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1615464257
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4271051576
Short name T379
Test name
Test status
Simulation time 2853254011 ps
CPU time 1.57 seconds
Started Jul 21 05:35:47 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 194296 kb
Host smart-275f2675-83f2-4b3e-9b7b-bd54f48eaf1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271051576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.4271051576
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1653920071
Short name T302
Test name
Test status
Simulation time 308717227 ps
CPU time 2.34 seconds
Started Jul 21 05:35:49 PM PDT 24
Finished Jul 21 05:35:52 PM PDT 24
Peak memory 198900 kb
Host smart-ea864992-dec0-4775-bf44-061cafdd55bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653920071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1653920071
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1127491320
Short name T347
Test name
Test status
Simulation time 4222216889 ps
CPU time 6.04 seconds
Started Jul 21 05:35:50 PM PDT 24
Finished Jul 21 05:35:56 PM PDT 24
Peak memory 198236 kb
Host smart-61eff401-1a0a-4238-9f8d-22f626e758fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127491320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1127491320
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2473476978
Short name T378
Test name
Test status
Simulation time 418503903 ps
CPU time 0.88 seconds
Started Jul 21 05:35:50 PM PDT 24
Finished Jul 21 05:35:52 PM PDT 24
Peak memory 197960 kb
Host smart-af9e7e83-465c-46a8-9806-1fcef7153c5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473476978 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2473476978
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2159162491
Short name T364
Test name
Test status
Simulation time 530710587 ps
CPU time 0.73 seconds
Started Jul 21 05:35:49 PM PDT 24
Finished Jul 21 05:35:51 PM PDT 24
Peak memory 192428 kb
Host smart-d3477011-0f09-482f-81b0-f46bb6adfe88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159162491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2159162491
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4146100876
Short name T393
Test name
Test status
Simulation time 298369439 ps
CPU time 0.91 seconds
Started Jul 21 05:35:49 PM PDT 24
Finished Jul 21 05:35:51 PM PDT 24
Peak memory 184168 kb
Host smart-f6011938-eb83-4e9c-8fdb-7391ffab5d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146100876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.4146100876
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2237485512
Short name T415
Test name
Test status
Simulation time 2355487369 ps
CPU time 5.93 seconds
Started Jul 21 05:35:48 PM PDT 24
Finished Jul 21 05:35:54 PM PDT 24
Peak memory 194452 kb
Host smart-1659ec4a-f9df-42fa-ae55-a4f0935b5ddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237485512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2237485512
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1492729478
Short name T385
Test name
Test status
Simulation time 698387630 ps
CPU time 1.78 seconds
Started Jul 21 05:35:48 PM PDT 24
Finished Jul 21 05:35:51 PM PDT 24
Peak memory 198964 kb
Host smart-a2f3f68d-c69c-4c02-b34b-ccd1dab4a6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492729478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1492729478
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2848898711
Short name T327
Test name
Test status
Simulation time 8248868560 ps
CPU time 3.95 seconds
Started Jul 21 05:35:47 PM PDT 24
Finished Jul 21 05:35:52 PM PDT 24
Peak memory 198608 kb
Host smart-4ee7df92-f158-4895-bc54-39c7d606d380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848898711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2848898711
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3142083055
Short name T31
Test name
Test status
Simulation time 538616741 ps
CPU time 0.96 seconds
Started Jul 21 05:35:46 PM PDT 24
Finished Jul 21 05:35:48 PM PDT 24
Peak memory 195764 kb
Host smart-0077ede6-773a-4c22-b8ee-401f3ce9ab52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142083055 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3142083055
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3441956206
Short name T55
Test name
Test status
Simulation time 428432780 ps
CPU time 1.19 seconds
Started Jul 21 05:35:51 PM PDT 24
Finished Jul 21 05:35:52 PM PDT 24
Peak memory 193208 kb
Host smart-e7485c82-0859-4c16-88b3-9dc73b01d4f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441956206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3441956206
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.206614216
Short name T291
Test name
Test status
Simulation time 351708061 ps
CPU time 0.64 seconds
Started Jul 21 05:35:45 PM PDT 24
Finished Jul 21 05:35:46 PM PDT 24
Peak memory 193336 kb
Host smart-3c55d989-5cf7-4a0c-95da-f289c45dfbd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206614216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.206614216
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1507659368
Short name T355
Test name
Test status
Simulation time 1525360629 ps
CPU time 1.03 seconds
Started Jul 21 05:35:46 PM PDT 24
Finished Jul 21 05:35:48 PM PDT 24
Peak memory 193300 kb
Host smart-3256c80d-ee2a-4617-8359-8598fdda39da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507659368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1507659368
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1111448217
Short name T298
Test name
Test status
Simulation time 475686568 ps
CPU time 2.03 seconds
Started Jul 21 05:35:51 PM PDT 24
Finished Jul 21 05:35:53 PM PDT 24
Peak memory 198856 kb
Host smart-fdf761d0-f57a-4cd1-a67d-81e2b414d32c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111448217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1111448217
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2734035603
Short name T191
Test name
Test status
Simulation time 8802218205 ps
CPU time 4.09 seconds
Started Jul 21 05:35:47 PM PDT 24
Finished Jul 21 05:35:52 PM PDT 24
Peak memory 198668 kb
Host smart-ddd51a09-4790-4f7b-8415-92fe81bc05d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734035603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2734035603
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1906741635
Short name T248
Test name
Test status
Simulation time 20927794952 ps
CPU time 27.82 seconds
Started Jul 21 05:34:43 PM PDT 24
Finished Jul 21 05:35:11 PM PDT 24
Peak memory 191432 kb
Host smart-97dd33eb-a80e-49be-b9df-38e4f77b2ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906741635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1906741635
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.4036435740
Short name T203
Test name
Test status
Simulation time 555084246 ps
CPU time 0.79 seconds
Started Jul 21 05:34:42 PM PDT 24
Finished Jul 21 05:34:43 PM PDT 24
Peak memory 196136 kb
Host smart-36a7a35d-df6f-4a2a-8c48-83f4fb764b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036435740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.4036435740
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3480588615
Short name T47
Test name
Test status
Simulation time 30425104874 ps
CPU time 20.71 seconds
Started Jul 21 05:34:45 PM PDT 24
Finished Jul 21 05:35:06 PM PDT 24
Peak memory 196484 kb
Host smart-3cde5449-5b5f-4b37-90b7-45ee2eb36b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480588615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3480588615
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1904177212
Short name T16
Test name
Test status
Simulation time 4460236675 ps
CPU time 4.18 seconds
Started Jul 21 05:34:44 PM PDT 24
Finished Jul 21 05:34:49 PM PDT 24
Peak memory 215384 kb
Host smart-8fdf5065-a3c1-46d1-bb64-b068f8026ba3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904177212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1904177212
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.4073762458
Short name T252
Test name
Test status
Simulation time 612120643 ps
CPU time 0.81 seconds
Started Jul 21 05:34:43 PM PDT 24
Finished Jul 21 05:34:44 PM PDT 24
Peak memory 191396 kb
Host smart-2667057e-d28e-4e32-9eb1-023692413087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073762458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.4073762458
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2967267306
Short name T177
Test name
Test status
Simulation time 582463368 ps
CPU time 1.37 seconds
Started Jul 21 05:34:59 PM PDT 24
Finished Jul 21 05:35:01 PM PDT 24
Peak memory 196200 kb
Host smart-522a0949-7522-4ff6-9674-86e0c586873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967267306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2967267306
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1145072012
Short name T211
Test name
Test status
Simulation time 51150683080 ps
CPU time 10.84 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 191512 kb
Host smart-cdf2cf16-2bad-47c5-87e6-6d936334b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145072012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1145072012
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.702935855
Short name T227
Test name
Test status
Simulation time 514704062 ps
CPU time 1.23 seconds
Started Jul 21 05:34:57 PM PDT 24
Finished Jul 21 05:35:00 PM PDT 24
Peak memory 191448 kb
Host smart-13e6e1b5-53d6-49b8-afc6-2d05dad40518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702935855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.702935855
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.942745794
Short name T208
Test name
Test status
Simulation time 56040073206 ps
CPU time 5.62 seconds
Started Jul 21 05:34:59 PM PDT 24
Finished Jul 21 05:35:06 PM PDT 24
Peak memory 196440 kb
Host smart-0a7950da-c019-4a21-b93d-4a34b55e6fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942745794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.942745794
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2842222059
Short name T222
Test name
Test status
Simulation time 416193138 ps
CPU time 0.61 seconds
Started Jul 21 05:35:02 PM PDT 24
Finished Jul 21 05:35:04 PM PDT 24
Peak memory 191436 kb
Host smart-aa82c690-e978-4dff-a302-bf2e24f8fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842222059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2842222059
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3664610055
Short name T253
Test name
Test status
Simulation time 13955353554 ps
CPU time 3.14 seconds
Started Jul 21 05:34:58 PM PDT 24
Finished Jul 21 05:35:03 PM PDT 24
Peak memory 191516 kb
Host smart-ae261fee-909e-49e0-b252-600ff25b5340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664610055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3664610055
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.609536829
Short name T9
Test name
Test status
Simulation time 721887192 ps
CPU time 0.67 seconds
Started Jul 21 05:34:59 PM PDT 24
Finished Jul 21 05:35:01 PM PDT 24
Peak memory 196144 kb
Host smart-728e1a9c-8b50-4dfc-94e4-1eeba564fa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609536829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.609536829
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.4014299869
Short name T262
Test name
Test status
Simulation time 32658309897 ps
CPU time 46.51 seconds
Started Jul 21 05:34:58 PM PDT 24
Finished Jul 21 05:35:46 PM PDT 24
Peak memory 191532 kb
Host smart-10a6aed5-400c-445b-92dc-08c7aa9dbdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014299869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4014299869
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.427962152
Short name T195
Test name
Test status
Simulation time 433065362 ps
CPU time 0.77 seconds
Started Jul 21 05:34:57 PM PDT 24
Finished Jul 21 05:34:59 PM PDT 24
Peak memory 191412 kb
Host smart-3c995497-1246-4695-990b-2be374169d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427962152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.427962152
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1467919978
Short name T261
Test name
Test status
Simulation time 19698489068 ps
CPU time 27.37 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:35:24 PM PDT 24
Peak memory 196532 kb
Host smart-4694d456-d87c-4047-a1fe-8b3f76077b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467919978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1467919978
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2654823239
Short name T269
Test name
Test status
Simulation time 602670540 ps
CPU time 0.81 seconds
Started Jul 21 05:34:58 PM PDT 24
Finished Jul 21 05:35:00 PM PDT 24
Peak memory 191440 kb
Host smart-e3239b0c-cefa-4c17-93d5-e8ff3ac2c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654823239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2654823239
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.216196907
Short name T281
Test name
Test status
Simulation time 10004063928 ps
CPU time 3.88 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:35:01 PM PDT 24
Peak memory 196520 kb
Host smart-75d5e119-edf9-4210-8d21-6504694bd85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216196907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.216196907
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2108181039
Short name T244
Test name
Test status
Simulation time 594865607 ps
CPU time 1.03 seconds
Started Jul 21 05:34:55 PM PDT 24
Finished Jul 21 05:34:56 PM PDT 24
Peak memory 196176 kb
Host smart-345c970d-d3fc-45bf-918b-a6c19ea72137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108181039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2108181039
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.4184226063
Short name T206
Test name
Test status
Simulation time 45281483694 ps
CPU time 69.28 seconds
Started Jul 21 05:34:58 PM PDT 24
Finished Jul 21 05:36:09 PM PDT 24
Peak memory 191516 kb
Host smart-509ca287-d737-4457-8331-aa749e1f9a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184226063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.4184226063
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3907932768
Short name T201
Test name
Test status
Simulation time 347539498 ps
CPU time 0.71 seconds
Started Jul 21 05:34:56 PM PDT 24
Finished Jul 21 05:34:57 PM PDT 24
Peak memory 191420 kb
Host smart-16489ea3-0daa-44b9-8d91-d6eeba39f4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907932768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3907932768
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.118244198
Short name T242
Test name
Test status
Simulation time 39272423610 ps
CPU time 56.17 seconds
Started Jul 21 05:35:02 PM PDT 24
Finished Jul 21 05:35:59 PM PDT 24
Peak memory 191516 kb
Host smart-ad4345bb-75c0-44bd-9273-9150ed6cdce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118244198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.118244198
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1320609638
Short name T198
Test name
Test status
Simulation time 420466836 ps
CPU time 1.13 seconds
Started Jul 21 05:35:01 PM PDT 24
Finished Jul 21 05:35:03 PM PDT 24
Peak memory 191396 kb
Host smart-a8913005-1425-4420-ac8c-5ce8aeb05b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320609638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1320609638
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2003198696
Short name T265
Test name
Test status
Simulation time 24211935426 ps
CPU time 32.47 seconds
Started Jul 21 05:35:02 PM PDT 24
Finished Jul 21 05:35:35 PM PDT 24
Peak memory 191512 kb
Host smart-d0694a6c-4893-4241-a716-ba6314f3c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003198696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2003198696
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3513038518
Short name T247
Test name
Test status
Simulation time 573496614 ps
CPU time 0.79 seconds
Started Jul 21 05:35:05 PM PDT 24
Finished Jul 21 05:35:06 PM PDT 24
Peak memory 191420 kb
Host smart-e3e61d87-0f87-4847-a116-f732d897485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513038518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3513038518
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1563321110
Short name T166
Test name
Test status
Simulation time 536317471 ps
CPU time 0.63 seconds
Started Jul 21 05:35:07 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 196204 kb
Host smart-5e51457e-3ebc-41b8-b2b6-a725c126d7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563321110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1563321110
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3984318540
Short name T223
Test name
Test status
Simulation time 20192943524 ps
CPU time 15.24 seconds
Started Jul 21 05:35:04 PM PDT 24
Finished Jul 21 05:35:19 PM PDT 24
Peak memory 191492 kb
Host smart-dbe1f461-46f2-4416-bdfb-1a38d37ca304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984318540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3984318540
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1455780870
Short name T2
Test name
Test status
Simulation time 404275990 ps
CPU time 1.2 seconds
Started Jul 21 05:35:02 PM PDT 24
Finished Jul 21 05:35:04 PM PDT 24
Peak memory 191376 kb
Host smart-f6712b5f-a00b-454f-8a69-20bb946b46d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455780870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1455780870
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2317215154
Short name T226
Test name
Test status
Simulation time 57021755247 ps
CPU time 20.63 seconds
Started Jul 21 05:34:51 PM PDT 24
Finished Jul 21 05:35:12 PM PDT 24
Peak memory 196520 kb
Host smart-fd923b66-b478-474e-afdb-3baac7ddfff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317215154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2317215154
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.608999521
Short name T13
Test name
Test status
Simulation time 4227047567 ps
CPU time 7.72 seconds
Started Jul 21 05:34:44 PM PDT 24
Finished Jul 21 05:34:53 PM PDT 24
Peak memory 215380 kb
Host smart-01a8942d-1813-4b32-99bc-b429cf567885
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608999521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.608999521
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.649883102
Short name T218
Test name
Test status
Simulation time 631276439 ps
CPU time 0.82 seconds
Started Jul 21 05:34:51 PM PDT 24
Finished Jul 21 05:34:53 PM PDT 24
Peak memory 191412 kb
Host smart-c9046dc5-fc1b-46b7-b355-7aac58e0a640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649883102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.649883102
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.4009331575
Short name T258
Test name
Test status
Simulation time 21381671048 ps
CPU time 24.11 seconds
Started Jul 21 05:35:04 PM PDT 24
Finished Jul 21 05:35:29 PM PDT 24
Peak memory 191424 kb
Host smart-74f236a1-9c20-4445-956a-cef8c3fe6698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009331575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4009331575
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2979104666
Short name T197
Test name
Test status
Simulation time 506912742 ps
CPU time 1.1 seconds
Started Jul 21 05:35:06 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 191308 kb
Host smart-83200ccc-5537-4935-a568-cb13a86f82f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979104666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2979104666
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1173092014
Short name T234
Test name
Test status
Simulation time 11443106863 ps
CPU time 7.4 seconds
Started Jul 21 05:35:04 PM PDT 24
Finished Jul 21 05:35:12 PM PDT 24
Peak memory 196432 kb
Host smart-f78d3d27-c5a4-4894-9920-6568f5e7aa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173092014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1173092014
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3065280038
Short name T255
Test name
Test status
Simulation time 521380258 ps
CPU time 0.67 seconds
Started Jul 21 05:35:05 PM PDT 24
Finished Jul 21 05:35:06 PM PDT 24
Peak memory 191460 kb
Host smart-1f5786eb-080f-4c98-9f3b-9ff977c897c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065280038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3065280038
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3619139434
Short name T259
Test name
Test status
Simulation time 6539887855 ps
CPU time 3.28 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:35:14 PM PDT 24
Peak memory 191508 kb
Host smart-a5f9fa16-1820-4c1e-b7e7-f42ac41423e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619139434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3619139434
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3944800754
Short name T275
Test name
Test status
Simulation time 444983976 ps
CPU time 1.17 seconds
Started Jul 21 05:35:06 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 191384 kb
Host smart-f5f2010f-6b41-4301-b582-3cf43e615fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944800754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3944800754
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.84940771
Short name T42
Test name
Test status
Simulation time 17778767571 ps
CPU time 6.43 seconds
Started Jul 21 05:35:14 PM PDT 24
Finished Jul 21 05:35:21 PM PDT 24
Peak memory 196468 kb
Host smart-6b21cd31-2c2a-4858-a583-cf1a7cca6aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84940771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.84940771
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3567735750
Short name T216
Test name
Test status
Simulation time 531193893 ps
CPU time 0.99 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:35:12 PM PDT 24
Peak memory 191436 kb
Host smart-8830319c-f368-4028-b4fd-0b570a42d640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567735750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3567735750
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.901988046
Short name T205
Test name
Test status
Simulation time 737700297 ps
CPU time 1.7 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:35:13 PM PDT 24
Peak memory 191440 kb
Host smart-b4ce8c67-313b-46bc-bb4d-9fe822e21fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901988046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.901988046
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3688870213
Short name T277
Test name
Test status
Simulation time 437013102 ps
CPU time 1.22 seconds
Started Jul 21 05:35:06 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 196312 kb
Host smart-a34c71cf-5b0e-4596-a34a-916bb042c9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688870213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3688870213
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.512199183
Short name T251
Test name
Test status
Simulation time 50847567113 ps
CPU time 76.37 seconds
Started Jul 21 05:35:07 PM PDT 24
Finished Jul 21 05:36:24 PM PDT 24
Peak memory 196516 kb
Host smart-cd55b014-8a94-45fd-8a5e-a1992cc01a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512199183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.512199183
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3882268704
Short name T233
Test name
Test status
Simulation time 479871390 ps
CPU time 0.63 seconds
Started Jul 21 05:35:12 PM PDT 24
Finished Jul 21 05:35:13 PM PDT 24
Peak memory 196300 kb
Host smart-ae82dce0-ff09-47c9-beb2-e98e18dcec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882268704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3882268704
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1054859743
Short name T236
Test name
Test status
Simulation time 34037996857 ps
CPU time 12.03 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:35:22 PM PDT 24
Peak memory 191464 kb
Host smart-30ffb3f9-0294-4623-b2bf-05a7f71fa464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054859743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1054859743
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1244762663
Short name T254
Test name
Test status
Simulation time 354525363 ps
CPU time 1.1 seconds
Started Jul 21 05:35:12 PM PDT 24
Finished Jul 21 05:35:14 PM PDT 24
Peak memory 191384 kb
Host smart-f5ac417f-1aa1-45b3-8dff-7c664a3dbf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244762663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1244762663
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3450801622
Short name T49
Test name
Test status
Simulation time 49332158672 ps
CPU time 73.38 seconds
Started Jul 21 05:35:13 PM PDT 24
Finished Jul 21 05:36:27 PM PDT 24
Peak memory 191504 kb
Host smart-ea33a351-b3c2-4807-931b-1633733a0118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450801622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3450801622
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2782007749
Short name T220
Test name
Test status
Simulation time 540945644 ps
CPU time 0.84 seconds
Started Jul 21 05:35:08 PM PDT 24
Finished Jul 21 05:35:10 PM PDT 24
Peak memory 196132 kb
Host smart-cccbbd2a-8823-48dc-94d4-8d06cca6f2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782007749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2782007749
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2925680143
Short name T276
Test name
Test status
Simulation time 23626118600 ps
CPU time 17.32 seconds
Started Jul 21 05:35:09 PM PDT 24
Finished Jul 21 05:35:27 PM PDT 24
Peak memory 191496 kb
Host smart-8cb4faeb-4f31-4990-a1ad-db3c151c3479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925680143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2925680143
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.288026997
Short name T283
Test name
Test status
Simulation time 485693028 ps
CPU time 0.74 seconds
Started Jul 21 05:35:13 PM PDT 24
Finished Jul 21 05:35:14 PM PDT 24
Peak memory 191416 kb
Host smart-960fe520-101a-4ea2-93a2-bd415abdf1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288026997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.288026997
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3108933476
Short name T243
Test name
Test status
Simulation time 8325979552 ps
CPU time 2.83 seconds
Started Jul 21 05:35:11 PM PDT 24
Finished Jul 21 05:35:14 PM PDT 24
Peak memory 196508 kb
Host smart-8fac640e-e403-41cf-b055-eafd1caa18f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108933476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3108933476
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1347436358
Short name T213
Test name
Test status
Simulation time 422982412 ps
CPU time 0.84 seconds
Started Jul 21 05:35:09 PM PDT 24
Finished Jul 21 05:35:11 PM PDT 24
Peak memory 191432 kb
Host smart-90321f02-d330-402e-b9f2-7ac9129cd015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347436358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1347436358
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_jump.719950169
Short name T24
Test name
Test status
Simulation time 510148750 ps
CPU time 1.28 seconds
Started Jul 21 05:34:45 PM PDT 24
Finished Jul 21 05:34:47 PM PDT 24
Peak memory 196336 kb
Host smart-970af2b6-387c-4ecf-b8f0-00d1288680fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719950169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.719950169
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1619722070
Short name T238
Test name
Test status
Simulation time 38216505857 ps
CPU time 25.09 seconds
Started Jul 21 05:34:41 PM PDT 24
Finished Jul 21 05:35:07 PM PDT 24
Peak memory 191500 kb
Host smart-1938ec6c-9d4d-4248-bcc0-a8d41802722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619722070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1619722070
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2456354433
Short name T17
Test name
Test status
Simulation time 4335453340 ps
CPU time 2.57 seconds
Started Jul 21 05:34:44 PM PDT 24
Finished Jul 21 05:34:47 PM PDT 24
Peak memory 215392 kb
Host smart-c85511e8-a3b3-42fa-b4db-2e4ee8a9a438
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456354433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2456354433
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2581731539
Short name T240
Test name
Test status
Simulation time 563206704 ps
CPU time 1.44 seconds
Started Jul 21 05:34:45 PM PDT 24
Finished Jul 21 05:34:47 PM PDT 24
Peak memory 191408 kb
Host smart-7bbba74b-eb14-45e4-8109-761353302e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581731539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2581731539
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.674577119
Short name T46
Test name
Test status
Simulation time 26760835716 ps
CPU time 38.43 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 191452 kb
Host smart-f2a780a5-7492-4941-b6d3-1811ff9233a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674577119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.674577119
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1489630990
Short name T257
Test name
Test status
Simulation time 670686901 ps
CPU time 0.67 seconds
Started Jul 21 05:35:08 PM PDT 24
Finished Jul 21 05:35:10 PM PDT 24
Peak memory 191448 kb
Host smart-8f74e09b-bb8b-4af8-8166-77ceb60b5b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489630990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1489630990
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.798722589
Short name T151
Test name
Test status
Simulation time 81845036383 ps
CPU time 33.15 seconds
Started Jul 21 05:35:07 PM PDT 24
Finished Jul 21 05:35:42 PM PDT 24
Peak memory 197736 kb
Host smart-6479bb40-bb87-457c-8444-d09a9e746af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798722589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.798722589
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2609832790
Short name T11
Test name
Test status
Simulation time 52553684211 ps
CPU time 79.22 seconds
Started Jul 21 05:35:13 PM PDT 24
Finished Jul 21 05:36:33 PM PDT 24
Peak memory 191500 kb
Host smart-92a8edb8-cd25-4b71-bb81-bf490264d37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609832790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2609832790
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.555464203
Short name T282
Test name
Test status
Simulation time 580130025 ps
CPU time 1.46 seconds
Started Jul 21 05:35:10 PM PDT 24
Finished Jul 21 05:35:12 PM PDT 24
Peak memory 191448 kb
Host smart-9cc51e88-0003-4c73-9782-8d8f36916258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555464203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.555464203
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3308806587
Short name T228
Test name
Test status
Simulation time 42630343607 ps
CPU time 7.99 seconds
Started Jul 21 05:35:13 PM PDT 24
Finished Jul 21 05:35:22 PM PDT 24
Peak memory 196508 kb
Host smart-eb90ff87-5194-4412-87a3-59c8bb1e8be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308806587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3308806587
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2851916113
Short name T225
Test name
Test status
Simulation time 608685332 ps
CPU time 1.49 seconds
Started Jul 21 05:35:07 PM PDT 24
Finished Jul 21 05:35:10 PM PDT 24
Peak memory 191308 kb
Host smart-8dfad329-b499-448e-a3db-ba4c238a0af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851916113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2851916113
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1239431803
Short name T207
Test name
Test status
Simulation time 22595730313 ps
CPU time 4.66 seconds
Started Jul 21 05:35:16 PM PDT 24
Finished Jul 21 05:35:22 PM PDT 24
Peak memory 191536 kb
Host smart-50ea38c8-8f63-4249-97ba-e3135bf9cda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239431803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1239431803
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1594421250
Short name T1
Test name
Test status
Simulation time 639509680 ps
CPU time 0.78 seconds
Started Jul 21 05:35:15 PM PDT 24
Finished Jul 21 05:35:16 PM PDT 24
Peak memory 191456 kb
Host smart-02f16267-4606-4563-a152-191b25461167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594421250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1594421250
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.14632957
Short name T239
Test name
Test status
Simulation time 39945335972 ps
CPU time 59.93 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:36:17 PM PDT 24
Peak memory 191508 kb
Host smart-45c513d2-fe51-4cce-85f8-6345244777b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14632957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.14632957
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2353342418
Short name T241
Test name
Test status
Simulation time 387421440 ps
CPU time 0.72 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:35:19 PM PDT 24
Peak memory 191372 kb
Host smart-f58b3614-1cff-4660-a810-ceeb4af1bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353342418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2353342418
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1376929630
Short name T202
Test name
Test status
Simulation time 49281347319 ps
CPU time 71.49 seconds
Started Jul 21 05:35:19 PM PDT 24
Finished Jul 21 05:36:31 PM PDT 24
Peak memory 191452 kb
Host smart-1cbfc0bb-b2f1-4708-a36f-1fe89e0b5e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376929630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1376929630
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1148669413
Short name T246
Test name
Test status
Simulation time 541767978 ps
CPU time 0.83 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:35:18 PM PDT 24
Peak memory 196244 kb
Host smart-08442a82-164f-416e-9a40-24a6413ae9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148669413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1148669413
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.4201804471
Short name T152
Test name
Test status
Simulation time 216019445615 ps
CPU time 29.48 seconds
Started Jul 21 05:35:15 PM PDT 24
Finished Jul 21 05:35:45 PM PDT 24
Peak memory 191496 kb
Host smart-1aa52d69-90d8-4b69-aac2-3e886b70b687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201804471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.4201804471
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3652259134
Short name T235
Test name
Test status
Simulation time 703499077 ps
CPU time 0.64 seconds
Started Jul 21 05:35:16 PM PDT 24
Finished Jul 21 05:35:18 PM PDT 24
Peak memory 191452 kb
Host smart-316f9874-138b-416f-96df-42f71abf3295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652259134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3652259134
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2722221170
Short name T221
Test name
Test status
Simulation time 373624986 ps
CPU time 0.84 seconds
Started Jul 21 05:35:16 PM PDT 24
Finished Jul 21 05:35:18 PM PDT 24
Peak memory 191444 kb
Host smart-1b71153e-6af3-4a47-9162-6c7da65316ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722221170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2722221170
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.739490016
Short name T266
Test name
Test status
Simulation time 15967335378 ps
CPU time 6.92 seconds
Started Jul 21 05:35:19 PM PDT 24
Finished Jul 21 05:35:27 PM PDT 24
Peak memory 196496 kb
Host smart-feb207a5-4ae9-4579-92f5-5b2519601c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739490016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.739490016
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3091296332
Short name T264
Test name
Test status
Simulation time 516211790 ps
CPU time 0.89 seconds
Started Jul 21 05:35:18 PM PDT 24
Finished Jul 21 05:35:20 PM PDT 24
Peak memory 191432 kb
Host smart-44b361b6-6215-442e-846d-e57b3c86446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091296332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3091296332
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2422301761
Short name T212
Test name
Test status
Simulation time 2035844741 ps
CPU time 0.83 seconds
Started Jul 21 05:35:17 PM PDT 24
Finished Jul 21 05:35:18 PM PDT 24
Peak memory 191384 kb
Host smart-07b44efe-40d9-4e52-9fc4-ab18311b98ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422301761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2422301761
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3009832229
Short name T271
Test name
Test status
Simulation time 548716126 ps
CPU time 1.34 seconds
Started Jul 21 05:35:19 PM PDT 24
Finished Jul 21 05:35:21 PM PDT 24
Peak memory 191404 kb
Host smart-5db608ca-ae81-456a-869f-f1b1ae8bc13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009832229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3009832229
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1926975055
Short name T210
Test name
Test status
Simulation time 55245322667 ps
CPU time 5.99 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:35:27 PM PDT 24
Peak memory 191496 kb
Host smart-2a78d84d-d118-4a5d-a138-58bb181879df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926975055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1926975055
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.83930376
Short name T230
Test name
Test status
Simulation time 393783235 ps
CPU time 0.7 seconds
Started Jul 21 05:35:15 PM PDT 24
Finished Jul 21 05:35:16 PM PDT 24
Peak memory 191432 kb
Host smart-eb912ed7-9095-46b1-be48-27a3caa4b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83930376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.83930376
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3976554822
Short name T273
Test name
Test status
Simulation time 39997907367 ps
CPU time 13.32 seconds
Started Jul 21 05:34:45 PM PDT 24
Finished Jul 21 05:34:59 PM PDT 24
Peak memory 191428 kb
Host smart-4802a316-e5e0-46b0-b89b-08885df41ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976554822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3976554822
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2143798666
Short name T15
Test name
Test status
Simulation time 4232254285 ps
CPU time 7.25 seconds
Started Jul 21 05:34:51 PM PDT 24
Finished Jul 21 05:34:59 PM PDT 24
Peak memory 215152 kb
Host smart-a67d6836-1285-488f-819f-c80efa34a0ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143798666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2143798666
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1919234977
Short name T250
Test name
Test status
Simulation time 452818607 ps
CPU time 0.88 seconds
Started Jul 21 05:34:45 PM PDT 24
Finished Jul 21 05:34:47 PM PDT 24
Peak memory 191404 kb
Host smart-18b2569c-8072-474e-a0d3-0b5c0992cb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919234977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1919234977
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.268203145
Short name T214
Test name
Test status
Simulation time 51393015531 ps
CPU time 26.55 seconds
Started Jul 21 05:35:21 PM PDT 24
Finished Jul 21 05:35:49 PM PDT 24
Peak memory 191468 kb
Host smart-4d4022d1-2a3e-45f5-b2ae-e230b6c20c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268203145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.268203145
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3982514397
Short name T274
Test name
Test status
Simulation time 462382026 ps
CPU time 0.96 seconds
Started Jul 21 05:35:18 PM PDT 24
Finished Jul 21 05:35:20 PM PDT 24
Peak memory 191448 kb
Host smart-035a3d76-f18d-4f35-9a48-b1da85f86f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982514397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3982514397
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.396718686
Short name T196
Test name
Test status
Simulation time 42286514407 ps
CPU time 61.58 seconds
Started Jul 21 05:35:19 PM PDT 24
Finished Jul 21 05:36:21 PM PDT 24
Peak memory 196544 kb
Host smart-2fac89af-46cc-42cf-8583-0e21912fb08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396718686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.396718686
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2894704334
Short name T199
Test name
Test status
Simulation time 515833622 ps
CPU time 1.4 seconds
Started Jul 21 05:35:18 PM PDT 24
Finished Jul 21 05:35:20 PM PDT 24
Peak memory 191440 kb
Host smart-6d5c3a33-fc73-476c-bb9c-dba15b0028f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894704334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2894704334
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2061098953
Short name T186
Test name
Test status
Simulation time 429896695 ps
CPU time 0.69 seconds
Started Jul 21 05:35:27 PM PDT 24
Finished Jul 21 05:35:28 PM PDT 24
Peak memory 196276 kb
Host smart-503efcd7-2276-4673-a58b-719e73b9bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061098953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2061098953
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1859784180
Short name T270
Test name
Test status
Simulation time 39668371088 ps
CPU time 59.47 seconds
Started Jul 21 05:35:21 PM PDT 24
Finished Jul 21 05:36:21 PM PDT 24
Peak memory 191436 kb
Host smart-2301a20c-20c4-40bf-af6c-e831d7871ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859784180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1859784180
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3803580001
Short name T204
Test name
Test status
Simulation time 557586364 ps
CPU time 1.5 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:35:23 PM PDT 24
Peak memory 196224 kb
Host smart-e6a4d0b4-b329-4f45-bcab-ce0ac04f31c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803580001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3803580001
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1968522812
Short name T237
Test name
Test status
Simulation time 21806076101 ps
CPU time 16.96 seconds
Started Jul 21 05:35:24 PM PDT 24
Finished Jul 21 05:35:42 PM PDT 24
Peak memory 191460 kb
Host smart-5e102b7a-efec-42ab-908d-cd2f966ac9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968522812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1968522812
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4187535561
Short name T280
Test name
Test status
Simulation time 502446125 ps
CPU time 1.35 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:35:22 PM PDT 24
Peak memory 191424 kb
Host smart-b44c76ca-e600-4aed-95be-8a145ae18723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187535561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4187535561
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.792321439
Short name T245
Test name
Test status
Simulation time 12196682496 ps
CPU time 2.2 seconds
Started Jul 21 05:35:22 PM PDT 24
Finished Jul 21 05:35:25 PM PDT 24
Peak memory 191440 kb
Host smart-44de55a4-50b3-489a-b483-03d0e86566aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792321439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.792321439
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.4253035062
Short name T279
Test name
Test status
Simulation time 474815570 ps
CPU time 1.27 seconds
Started Jul 21 05:35:29 PM PDT 24
Finished Jul 21 05:35:31 PM PDT 24
Peak memory 191380 kb
Host smart-b278fe3b-6923-4a00-a645-e1dfdecaf5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253035062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.4253035062
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2540277537
Short name T249
Test name
Test status
Simulation time 20887182697 ps
CPU time 16.49 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:35:38 PM PDT 24
Peak memory 191504 kb
Host smart-7a5e3c50-6d8a-4174-8314-1314caf36347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540277537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2540277537
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1866775476
Short name T232
Test name
Test status
Simulation time 527727356 ps
CPU time 1.33 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:35:22 PM PDT 24
Peak memory 196256 kb
Host smart-d38ccc93-ee37-45ed-a4ca-1b203af6c8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866775476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1866775476
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3689999657
Short name T231
Test name
Test status
Simulation time 40924640193 ps
CPU time 10.38 seconds
Started Jul 21 05:35:22 PM PDT 24
Finished Jul 21 05:35:33 PM PDT 24
Peak memory 191492 kb
Host smart-721e8d2a-c9b5-44bd-897d-7f2bae8397af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689999657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3689999657
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2095222952
Short name T267
Test name
Test status
Simulation time 494466767 ps
CPU time 1.28 seconds
Started Jul 21 05:35:27 PM PDT 24
Finished Jul 21 05:35:28 PM PDT 24
Peak memory 191412 kb
Host smart-d4958afb-019e-4106-b54b-9350cca08665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095222952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2095222952
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1825753007
Short name T23
Test name
Test status
Simulation time 35628256210 ps
CPU time 12.14 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:35:33 PM PDT 24
Peak memory 196424 kb
Host smart-be9ce7b7-fb6a-4c69-84fc-99de26a01272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825753007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1825753007
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3388356730
Short name T260
Test name
Test status
Simulation time 491948440 ps
CPU time 1.22 seconds
Started Jul 21 05:35:25 PM PDT 24
Finished Jul 21 05:35:27 PM PDT 24
Peak memory 196184 kb
Host smart-4b197b70-432d-4678-9792-cfde459bd512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388356730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3388356730
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.418372358
Short name T272
Test name
Test status
Simulation time 2662199178 ps
CPU time 4.34 seconds
Started Jul 21 05:35:22 PM PDT 24
Finished Jul 21 05:35:27 PM PDT 24
Peak memory 191336 kb
Host smart-fbd8c44d-aa9e-4a6c-a14c-522e286b7e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418372358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.418372358
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.4160864170
Short name T224
Test name
Test status
Simulation time 610115960 ps
CPU time 0.8 seconds
Started Jul 21 05:35:24 PM PDT 24
Finished Jul 21 05:35:25 PM PDT 24
Peak memory 196264 kb
Host smart-5288e42b-1ef9-4ff6-87a3-dd54d6febae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160864170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.4160864170
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1970539611
Short name T229
Test name
Test status
Simulation time 39058168460 ps
CPU time 13.45 seconds
Started Jul 21 05:35:24 PM PDT 24
Finished Jul 21 05:35:37 PM PDT 24
Peak memory 191536 kb
Host smart-5f6a094d-b5af-4e0f-8479-c6cc318563b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970539611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1970539611
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1795695155
Short name T263
Test name
Test status
Simulation time 390656809 ps
CPU time 1.12 seconds
Started Jul 21 05:35:20 PM PDT 24
Finished Jul 21 05:35:22 PM PDT 24
Peak memory 196288 kb
Host smart-c6e81c7b-963d-4ee8-87eb-85554508d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795695155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1795695155
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2735055969
Short name T149
Test name
Test status
Simulation time 355435836 ps
CPU time 0.85 seconds
Started Jul 21 05:34:48 PM PDT 24
Finished Jul 21 05:34:49 PM PDT 24
Peak memory 196228 kb
Host smart-51fee630-9d4f-42a0-a779-5a3debb354bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735055969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2735055969
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2101308792
Short name T256
Test name
Test status
Simulation time 15218603708 ps
CPU time 9.79 seconds
Started Jul 21 05:34:52 PM PDT 24
Finished Jul 21 05:35:02 PM PDT 24
Peak memory 191500 kb
Host smart-1c6a5ffa-a8fe-44ff-a7bd-c6f67c885223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101308792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2101308792
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3146392580
Short name T217
Test name
Test status
Simulation time 451423313 ps
CPU time 0.97 seconds
Started Jul 21 05:34:52 PM PDT 24
Finished Jul 21 05:34:54 PM PDT 24
Peak memory 191412 kb
Host smart-ee216ed6-a495-4054-9d31-71945c16096e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146392580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3146392580
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.77946644
Short name T215
Test name
Test status
Simulation time 2112732021 ps
CPU time 3.38 seconds
Started Jul 21 05:34:53 PM PDT 24
Finished Jul 21 05:34:57 PM PDT 24
Peak memory 191464 kb
Host smart-43d6153d-bafa-47a6-993d-165928c8584b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77946644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.77946644
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2894847942
Short name T48
Test name
Test status
Simulation time 497711267 ps
CPU time 0.82 seconds
Started Jul 21 05:34:53 PM PDT 24
Finished Jul 21 05:34:54 PM PDT 24
Peak memory 191452 kb
Host smart-636a3203-2041-44f5-9445-a95314062b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894847942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2894847942
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2698878298
Short name T219
Test name
Test status
Simulation time 41278191595 ps
CPU time 62.66 seconds
Started Jul 21 05:34:49 PM PDT 24
Finished Jul 21 05:35:52 PM PDT 24
Peak memory 196500 kb
Host smart-0eb4a823-7703-4966-8c2c-138c583f1fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698878298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2698878298
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2468532066
Short name T278
Test name
Test status
Simulation time 454567151 ps
CPU time 1.35 seconds
Started Jul 21 05:34:50 PM PDT 24
Finished Jul 21 05:34:51 PM PDT 24
Peak memory 191440 kb
Host smart-795d1e01-b3d2-4f0e-9392-69c45de58534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468532066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2468532066
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4019122344
Short name T209
Test name
Test status
Simulation time 59012480242 ps
CPU time 82.51 seconds
Started Jul 21 05:34:51 PM PDT 24
Finished Jul 21 05:36:14 PM PDT 24
Peak memory 191432 kb
Host smart-04943de1-c934-4b39-856c-16a21f99d66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019122344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4019122344
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3377533628
Short name T21
Test name
Test status
Simulation time 607334224 ps
CPU time 1.41 seconds
Started Jul 21 05:34:50 PM PDT 24
Finished Jul 21 05:34:52 PM PDT 24
Peak memory 191348 kb
Host smart-c97d84b8-1f18-4120-a331-cf81515ac02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377533628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3377533628
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1239695244
Short name T200
Test name
Test status
Simulation time 36992199862 ps
CPU time 7.5 seconds
Started Jul 21 05:34:57 PM PDT 24
Finished Jul 21 05:35:06 PM PDT 24
Peak memory 191500 kb
Host smart-e089d002-c24e-43f5-8bea-f1afc83c2ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239695244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1239695244
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1110582301
Short name T268
Test name
Test status
Simulation time 576108093 ps
CPU time 0.81 seconds
Started Jul 21 05:34:50 PM PDT 24
Finished Jul 21 05:34:51 PM PDT 24
Peak memory 191364 kb
Host smart-09960567-9e8d-4296-9549-908ba5e2f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110582301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1110582301
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.158856214
Short name T37
Test name
Test status
Simulation time 22079427177 ps
CPU time 191.63 seconds
Started Jul 21 05:34:55 PM PDT 24
Finished Jul 21 05:38:07 PM PDT 24
Peak memory 206312 kb
Host smart-372eb860-c3c3-446c-b1ca-59b4806f1365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158856214 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.158856214
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%