Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.27	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	3	170	98.27

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	33175	1		T1	11		T3	108		T5	12
bark[1]	936	1		T12	21		T19	21		T27	47
bark[2]	953	1		T12	21		T29	156		T76	42
bark[3]	392	1		T6	14		T140	21		T143	14
bark[4]	269	1		T183	14		T108	14		T83	21
bark[5]	253	1		T3	21		T92	111		T171	14
bark[6]	265	1		T10	21		T19	21		T194	14
bark[7]	554	1		T31	224		T120	159		T119	33
bark[8]	482	1		T19	21		T27	68		T28	43
bark[9]	526	1		T7	40		T117	14		T142	14
bark[10]	396	1		T3	30		T27	275		T88	7
bark[11]	585	1		T13	26		T146	21		T123	14
bark[12]	998	1		T12	39		T88	287		T83	83
bark[13]	790	1		T10	30		T19	30		T33	21
bark[14]	556	1		T10	21		T181	14		T87	21
bark[15]	1683	1		T27	177		T29	26		T32	30
bark[16]	993	1		T7	43		T18	14		T27	21
bark[17]	356	1		T19	26		T76	21		T32	21
bark[18]	246	1		T7	21		T31	26		T78	14
bark[19]	232	1		T2	14		T12	42		T146	21
bark[20]	763	1		T3	26		T29	21		T146	277
bark[21]	729	1		T8	5		T29	185		T39	30
bark[22]	185	1		T19	21		T29	21		T82	35
bark[23]	565	1		T3	61		T28	21		T32	26
bark[24]	752	1		T13	26		T76	21		T31	21
bark[25]	910	1		T32	35		T88	222		T83	225
bark[26]	303	1		T8	7		T87	21		T82	81
bark[27]	924	1		T27	155		T90	21		T163	47
bark[28]	218	1		T7	14		T13	5		T27	21
bark[29]	492	1		T10	40		T29	136		T156	14
bark[30]	190	1		T31	82		T87	21		T151	26
bark[31]	610	1		T27	26		T28	176		T31	111
bark_0	4593	1		T1	7		T2	7		T3	21

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	32432	1		T1	10		T3	107		T5	11
bite[1]	644	1		T12	42		T145	13		T90	42
bite[2]	328	1		T3	30		T7	43		T29	21
bite[3]	848	1		T32	309		T38	13		T118	35
bite[4]	449	1		T7	40		T8	4		T29	199
bite[5]	245	1		T3	61		T13	26		T19	21
bite[6]	377	1		T10	21		T12	39		T13	33
bite[7]	523	1		T29	155		T76	21		T115	21
bite[8]	1530	1		T29	135		T33	519		T115	21
bite[9]	352	1		T6	13		T31	110		T37	13
bite[10]	746	1		T27	184		T28	21		T31	223
bite[11]	453	1		T28	175		T87	21		T123	21
bite[12]	787	1		T19	51		T29	25		T32	106
bite[13]	941	1		T7	13		T27	46		T82	236
bite[14]	246	1		T2	13		T10	40		T32	21
bite[15]	1176	1		T19	26		T29	184		T76	21
bite[16]	897	1		T10	30		T29	21		T33	21
bite[17]	358	1		T12	21		T27	175		T170	13
bite[18]	743	1		T31	21		T189	13		T142	13
bite[19]	521	1		T183	13		T92	6		T124	218
bite[20]	522	1		T3	21		T27	21		T76	42
bite[21]	609	1		T12	21		T27	21		T32	30
bite[22]	609	1		T185	13		T108	13		T89	83
bite[23]	550	1		T3	26		T27	279		T88	21
bite[24]	428	1		T10	21		T28	42		T32	21
bite[25]	462	1		T13	4		T31	81		T128	283
bite[26]	536	1		T146	276		T120	158		T140	21
bite[27]	585	1		T8	6		T27	25		T153	21
bite[28]	560	1		T30	21		T194	13		T123	21
bite[29]	281	1		T83	61		T166	13		T167	13
bite[30]	427	1		T7	21		T18	13		T19	42
bite[31]	572	1		T30	23		T31	227		T87	39
bite_0	5137	1		T1	8		T2	8		T3	22

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	47153	1		T1	18		T2	21		T3	267
auto[1]	8721	1		T8	233		T12	38		T19	88

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	2	1		T92	2		-	-		-	-
prescale[0]	1072	1		T8	19		T11	57		T27	19
prescale[1]	1570	1		T29	74		T30	40		T31	19
prescale[2]	768	1		T11	48		T27	2		T32	54
prescale[3]	1539	1		T11	95		T31	19		T81	9
prescale[4]	984	1		T8	66		T10	49		T11	2
prescale[5]	1136	1		T11	41		T27	96		T32	79
prescale[6]	1056	1		T10	23		T12	23		T27	2
prescale[7]	466	1		T27	19		T29	55		T30	2
prescale[8]	1003	1		T7	70		T13	75		T27	108
prescale[9]	1150	1		T7	19		T8	44		T27	19
prescale[10]	726	1		T12	9		T27	9		T29	39
prescale[11]	647	1		T29	2		T32	46		T88	57
prescale[12]	650	1		T8	59		T11	18		T27	58
prescale[13]	1199	1		T8	88		T19	49		T27	102
prescale[14]	1039	1		T3	23		T13	2		T27	23
prescale[15]	1084	1		T11	19		T19	35		T32	68
prescale[16]	1035	1		T3	19		T10	56		T12	19
prescale[17]	1137	1		T3	9		T11	64		T29	68
prescale[18]	1249	1		T11	19		T13	92		T27	57
prescale[19]	1336	1		T3	23		T31	2		T87	230
prescale[20]	769	1		T7	19		T28	11		T29	24
prescale[21]	806	1		T3	36		T27	72		T29	19
prescale[22]	744	1		T11	4		T13	2		T27	50
prescale[23]	803	1		T27	23		T28	125		T29	79
prescale[24]	1067	1		T27	94		T28	19		T93	9
prescale[25]	297	1		T12	36		T13	19		T35	9
prescale[26]	781	1		T7	40		T32	96		T33	2
prescale[27]	1063	1		T5	9		T8	2		T10	40
prescale[28]	704	1		T28	19		T29	21		T31	52
prescale[29]	869	1		T13	23		T27	61		T80	9
prescale[30]	584	1		T31	19		T36	9		T32	19
prescale[31]	800	1		T12	40		T29	115		T32	76
prescale_0	25741	1		T1	18		T2	21		T3	157

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	41734	1		T1	9		T2	9		T3	227
auto[1]	14140	1		T1	9		T2	12		T3	40

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	55874	1		T1	18		T2	21		T3	267

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	33398	1		T1	13		T2	1		T3	129
wkup[1]	216	1		T185	15		T82	21		T123	30
wkup[2]	276	1		T89	21		T116	21		T166	21
wkup[3]	306	1		T76	21		T32	21		T88	42
wkup[4]	185	1		T3	21		T27	21		T29	21
wkup[5]	447	1		T13	21		T29	21		T32	30
wkup[6]	459	1		T12	21		T32	21		T82	21
wkup[7]	422	1		T10	30		T13	21		T32	26
wkup[8]	485	1		T8	21		T31	30		T146	30
wkup[9]	209	1		T8	26		T31	21		T33	21
wkup[10]	260	1		T7	15		T8	21		T29	56
wkup[11]	327	1		T27	47		T28	21		T29	68
wkup[12]	362	1		T8	21		T31	21		T33	21
wkup[13]	203	1		T10	21		T27	20		T32	21
wkup[14]	316	1		T8	30		T19	30		T27	21
wkup[15]	284	1		T8	15		T19	21		T27	21
wkup[16]	327	1		T2	15		T13	21		T31	21
wkup[17]	292	1		T10	21		T27	30		T29	21
wkup[18]	284	1		T32	21		T87	21		T88	21
wkup[19]	503	1		T19	26		T29	21		T31	21
wkup[20]	404	1		T10	21		T27	8		T29	21
wkup[21]	273	1		T83	21		T140	15		T111	15
wkup[22]	212	1		T29	21		T31	30		T87	39
wkup[23]	264	1		T31	21		T33	21		T87	21
wkup[24]	234	1		T7	21		T11	21		T27	21
wkup[25]	282	1		T10	21		T18	15		T12	42
wkup[26]	296	1		T82	29		T145	15		T83	52
wkup[27]	285	1		T33	21		T82	21		T88	21
wkup[28]	187	1		T29	21		T31	26		T88	42
wkup[29]	344	1		T13	21		T29	15		T31	47
wkup[30]	262	1		T13	26		T76	21		T32	21
wkup[31]	258	1		T8	6		T30	42		T32	39
wkup[32]	199	1		T29	21		T124	21		T84	21
wkup[33]	270	1		T7	21		T29	21		T31	51
wkup[34]	277	1		T31	21		T32	30		T82	21
wkup[35]	407	1		T3	21		T27	29		T29	21
wkup[36]	350	1		T29	15		T31	56		T88	21
wkup[37]	339	1		T12	21		T19	15		T89	45
wkup[38]	386	1		T27	21		T28	21		T30	30
wkup[39]	350	1		T27	21		T28	21		T31	21
wkup[40]	412	1		T3	21		T28	26		T29	21
wkup[41]	163	1		T12	39		T13	6		T32	21
wkup[42]	544	1		T7	30		T19	21		T27	21
wkup[43]	336	1		T104	15		T92	51		T163	21
wkup[44]	177	1		T29	21		T39	30		T92	21
wkup[45]	202	1		T92	21		T166	15		T96	21
wkup[46]	248	1		T19	21		T37	15		T33	21
wkup[47]	235	1		T29	21		T32	42		T183	15
wkup[48]	62	1		T31	21		T146	26		T131	15
wkup[49]	298	1		T7	21		T8	8		T31	21
wkup[50]	346	1		T27	26		T31	26		T78	15
wkup[51]	277	1		T6	15		T13	26		T32	15
wkup[52]	366	1		T27	77		T87	21		T146	21
wkup[53]	278	1		T3	30		T27	26		T29	26
wkup[54]	278	1		T10	21		T19	21		T181	15
wkup[55]	480	1		T29	21		T190	26		T87	21
wkup[56]	230	1		T27	21		T31	21		T189	15
wkup[57]	198	1		T11	21		T140	21		T157	21
wkup[58]	378	1		T27	60		T30	21		T82	21
wkup[59]	285	1		T11	24		T31	21		T87	21
wkup[60]	156	1		T32	42		T89	21		T124	21
wkup[61]	357	1		T3	26		T7	21		T19	21
wkup[62]	225	1		T31	21		T32	21		T87	42
wkup[63]	329	1		T27	42		T28	21		T76	21
wkup_0	3574	1		T1	5		T2	5		T3	19