Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.41 99.33 93.67 100.00 98.40 99.51 51.54


Total test records in report: 424
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T20 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1391881436 Jul 22 07:13:11 PM PDT 24 Jul 22 07:14:02 PM PDT 24 1249076511 ps
T290 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2462721131 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:00 PM PDT 24 350055663 ps
T26 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3897629025 Jul 22 07:12:37 PM PDT 24 Jul 22 07:13:23 PM PDT 24 467473981 ps
T21 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.759784912 Jul 22 07:12:03 PM PDT 24 Jul 22 07:12:39 PM PDT 24 1466686007 ps
T22 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2549695745 Jul 22 07:11:33 PM PDT 24 Jul 22 07:11:58 PM PDT 24 561540562 ps
T291 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.931846231 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:02 PM PDT 24 472065745 ps
T68 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1095275209 Jul 22 07:13:06 PM PDT 24 Jul 22 07:13:57 PM PDT 24 1307243908 ps
T69 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3746195137 Jul 22 07:14:14 PM PDT 24 Jul 22 07:14:58 PM PDT 24 540032737 ps
T203 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4244953546 Jul 22 07:12:37 PM PDT 24 Jul 22 07:13:23 PM PDT 24 487715885 ps
T70 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3795554926 Jul 22 07:12:15 PM PDT 24 Jul 22 07:13:01 PM PDT 24 2974322157 ps
T71 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.306065342 Jul 22 07:11:35 PM PDT 24 Jul 22 07:12:01 PM PDT 24 2255449708 ps
T292 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2794497478 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:36 PM PDT 24 439943200 ps
T204 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1657164867 Jul 22 07:13:06 PM PDT 24 Jul 22 07:13:55 PM PDT 24 561381539 ps
T72 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2954731338 Jul 22 07:12:08 PM PDT 24 Jul 22 07:12:48 PM PDT 24 1095704261 ps
T293 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1446095606 Jul 22 07:12:37 PM PDT 24 Jul 22 07:13:23 PM PDT 24 505465764 ps
T294 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1821440750 Jul 22 07:12:14 PM PDT 24 Jul 22 07:12:55 PM PDT 24 418429137 ps
T73 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3325775491 Jul 22 07:11:59 PM PDT 24 Jul 22 07:12:31 PM PDT 24 1364446870 ps
T202 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1126600850 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:00 PM PDT 24 449363269 ps
T74 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.493090557 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:37 PM PDT 24 1340414530 ps
T201 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2176463791 Jul 22 07:12:49 PM PDT 24 Jul 22 07:13:37 PM PDT 24 703223025 ps
T295 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1063799108 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:36 PM PDT 24 448479530 ps
T75 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.272002574 Jul 22 07:12:37 PM PDT 24 Jul 22 07:13:23 PM PDT 24 1742765508 ps
T296 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2545492859 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:58 PM PDT 24 312789247 ps
T297 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1112295099 Jul 22 07:13:07 PM PDT 24 Jul 22 07:13:57 PM PDT 24 312597324 ps
T298 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4143928808 Jul 22 07:12:07 PM PDT 24 Jul 22 07:12:45 PM PDT 24 491544871 ps
T23 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1746673225 Jul 22 07:12:37 PM PDT 24 Jul 22 07:13:34 PM PDT 24 8378368427 ps
T299 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3161491742 Jul 22 07:11:55 PM PDT 24 Jul 22 07:12:23 PM PDT 24 919298442 ps
T300 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.865952415 Jul 22 07:11:53 PM PDT 24 Jul 22 07:12:21 PM PDT 24 741112426 ps
T301 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2630892963 Jul 22 07:11:54 PM PDT 24 Jul 22 07:12:22 PM PDT 24 2360535876 ps
T24 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3293603377 Jul 22 07:11:40 PM PDT 24 Jul 22 07:12:07 PM PDT 24 4471393360 ps
T51 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1556800043 Jul 22 07:11:58 PM PDT 24 Jul 22 07:12:47 PM PDT 24 13754428565 ps
T302 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3714178550 Jul 22 07:12:06 PM PDT 24 Jul 22 07:12:43 PM PDT 24 377058298 ps
T303 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.913685324 Jul 22 07:11:58 PM PDT 24 Jul 22 07:12:29 PM PDT 24 523394500 ps
T304 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3692202320 Jul 22 07:12:02 PM PDT 24 Jul 22 07:12:38 PM PDT 24 346347099 ps
T305 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2202558160 Jul 22 07:12:05 PM PDT 24 Jul 22 07:12:42 PM PDT 24 411944491 ps
T306 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1373088151 Jul 22 07:12:16 PM PDT 24 Jul 22 07:12:58 PM PDT 24 521184095 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2837814212 Jul 22 07:11:56 PM PDT 24 Jul 22 07:12:24 PM PDT 24 381463642 ps
T25 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2386836368 Jul 22 07:12:03 PM PDT 24 Jul 22 07:12:50 PM PDT 24 8502395942 ps
T307 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2773303768 Jul 22 07:12:03 PM PDT 24 Jul 22 07:12:41 PM PDT 24 369633062 ps
T308 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3560288686 Jul 22 07:12:04 PM PDT 24 Jul 22 07:12:41 PM PDT 24 433338668 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2372667226 Jul 22 07:11:58 PM PDT 24 Jul 22 07:12:26 PM PDT 24 502147349 ps
T309 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3988207311 Jul 22 07:12:28 PM PDT 24 Jul 22 07:13:12 PM PDT 24 321260434 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2775541667 Jul 22 07:11:59 PM PDT 24 Jul 22 07:12:29 PM PDT 24 301543512 ps
T196 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1894982170 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:40 PM PDT 24 8431986694 ps
T310 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3383206539 Jul 22 07:13:13 PM PDT 24 Jul 22 07:14:01 PM PDT 24 323304292 ps
T55 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3391053880 Jul 22 07:12:16 PM PDT 24 Jul 22 07:12:59 PM PDT 24 499715909 ps
T311 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1038285499 Jul 22 07:12:00 PM PDT 24 Jul 22 07:12:39 PM PDT 24 4761779368 ps
T312 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1045489885 Jul 22 07:12:00 PM PDT 24 Jul 22 07:12:34 PM PDT 24 265956588 ps
T313 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1518640335 Jul 22 07:11:52 PM PDT 24 Jul 22 07:12:28 PM PDT 24 7080832586 ps
T314 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3655454347 Jul 22 07:11:43 PM PDT 24 Jul 22 07:12:09 PM PDT 24 4407560194 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1531229019 Jul 22 07:11:54 PM PDT 24 Jul 22 07:12:22 PM PDT 24 522265227 ps
T315 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3572255926 Jul 22 07:11:56 PM PDT 24 Jul 22 07:12:26 PM PDT 24 1326037605 ps
T316 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4271403764 Jul 22 07:11:57 PM PDT 24 Jul 22 07:12:27 PM PDT 24 366632591 ps
T317 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3026165700 Jul 22 07:13:06 PM PDT 24 Jul 22 07:13:55 PM PDT 24 501793972 ps
T318 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2186231560 Jul 22 07:12:02 PM PDT 24 Jul 22 07:12:38 PM PDT 24 401245800 ps
T319 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1954994803 Jul 22 07:13:09 PM PDT 24 Jul 22 07:14:02 PM PDT 24 1624163263 ps
T320 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3553575449 Jul 22 07:12:16 PM PDT 24 Jul 22 07:12:59 PM PDT 24 323421832 ps
T321 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2211418956 Jul 22 07:12:08 PM PDT 24 Jul 22 07:12:46 PM PDT 24 327456785 ps
T322 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.847612599 Jul 22 07:11:57 PM PDT 24 Jul 22 07:12:29 PM PDT 24 14761262276 ps
T323 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.617811043 Jul 22 07:11:58 PM PDT 24 Jul 22 07:12:28 PM PDT 24 2285525821 ps
T324 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3777219782 Jul 22 07:11:40 PM PDT 24 Jul 22 07:12:07 PM PDT 24 1241631134 ps
T199 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.584562580 Jul 22 07:12:16 PM PDT 24 Jul 22 07:13:05 PM PDT 24 4285898123 ps
T57 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2898138959 Jul 22 07:11:40 PM PDT 24 Jul 22 07:12:06 PM PDT 24 506774594 ps
T60 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2184131886 Jul 22 07:11:56 PM PDT 24 Jul 22 07:12:25 PM PDT 24 327007589 ps
T325 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2944113477 Jul 22 07:12:31 PM PDT 24 Jul 22 07:13:17 PM PDT 24 505265215 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2487173060 Jul 22 07:11:58 PM PDT 24 Jul 22 07:12:28 PM PDT 24 1110814770 ps
T327 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3008724359 Jul 22 07:12:02 PM PDT 24 Jul 22 07:12:40 PM PDT 24 488548565 ps
T197 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.98422213 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:04 PM PDT 24 4473929978 ps
T198 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2810838685 Jul 22 07:12:02 PM PDT 24 Jul 22 07:12:43 PM PDT 24 3952452295 ps
T328 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3106952967 Jul 22 07:11:54 PM PDT 24 Jul 22 07:12:21 PM PDT 24 359498751 ps
T329 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1097173548 Jul 22 07:11:55 PM PDT 24 Jul 22 07:12:23 PM PDT 24 468967027 ps
T330 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.407023637 Jul 22 07:13:10 PM PDT 24 Jul 22 07:14:01 PM PDT 24 663114711 ps
T331 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3352894849 Jul 22 07:12:37 PM PDT 24 Jul 22 07:13:28 PM PDT 24 3997650761 ps
T61 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3855905261 Jul 22 07:12:04 PM PDT 24 Jul 22 07:12:39 PM PDT 24 342028965 ps
T332 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.463204909 Jul 22 07:11:55 PM PDT 24 Jul 22 07:12:23 PM PDT 24 366080574 ps
T333 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3241716322 Jul 22 07:14:29 PM PDT 24 Jul 22 07:15:05 PM PDT 24 559869775 ps
T334 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1944421580 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:58 PM PDT 24 2477170790 ps
T335 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3334853707 Jul 22 07:12:06 PM PDT 24 Jul 22 07:12:43 PM PDT 24 556115083 ps
T336 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2189626523 Jul 22 07:12:13 PM PDT 24 Jul 22 07:12:52 PM PDT 24 316176624 ps
T337 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3995151564 Jul 22 07:11:59 PM PDT 24 Jul 22 07:12:44 PM PDT 24 8412257794 ps
T338 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2738966522 Jul 22 07:11:56 PM PDT 24 Jul 22 07:12:28 PM PDT 24 1425584468 ps
T339 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2284568224 Jul 22 07:12:16 PM PDT 24 Jul 22 07:12:59 PM PDT 24 330223807 ps
T62 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4058952402 Jul 22 07:12:10 PM PDT 24 Jul 22 07:12:49 PM PDT 24 398230310 ps
T340 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.69051007 Jul 22 07:12:07 PM PDT 24 Jul 22 07:12:45 PM PDT 24 559158151 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2021029093 Jul 22 07:11:56 PM PDT 24 Jul 22 07:12:25 PM PDT 24 419566191 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3733175110 Jul 22 07:11:59 PM PDT 24 Jul 22 07:12:32 PM PDT 24 1454297834 ps
T343 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3742373817 Jul 22 07:12:07 PM PDT 24 Jul 22 07:12:46 PM PDT 24 588651197 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4269396768 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:36 PM PDT 24 402808096 ps
T345 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3308938623 Jul 22 07:11:55 PM PDT 24 Jul 22 07:12:23 PM PDT 24 541554505 ps
T346 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2267163300 Jul 22 07:12:28 PM PDT 24 Jul 22 07:13:14 PM PDT 24 444632656 ps
T63 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3133048475 Jul 22 07:12:10 PM PDT 24 Jul 22 07:12:49 PM PDT 24 578393025 ps
T347 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2680277778 Jul 22 07:11:59 PM PDT 24 Jul 22 07:12:42 PM PDT 24 7862454601 ps
T348 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3531889403 Jul 22 07:11:55 PM PDT 24 Jul 22 07:12:23 PM PDT 24 450657817 ps
T349 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3905352080 Jul 22 07:12:02 PM PDT 24 Jul 22 07:12:38 PM PDT 24 528653612 ps
T350 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1703581370 Jul 22 07:12:08 PM PDT 24 Jul 22 07:12:51 PM PDT 24 8365985825 ps
T351 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4192729071 Jul 22 07:11:58 PM PDT 24 Jul 22 07:12:28 PM PDT 24 380802264 ps
T352 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2744094830 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:58 PM PDT 24 310335559 ps
T353 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2082238114 Jul 22 07:11:54 PM PDT 24 Jul 22 07:12:23 PM PDT 24 513290388 ps
T354 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1971633308 Jul 22 07:12:55 PM PDT 24 Jul 22 07:13:43 PM PDT 24 272108561 ps
T355 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2154493831 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:57 PM PDT 24 344782721 ps
T356 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2187105419 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:58 PM PDT 24 598486501 ps
T357 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1677469606 Jul 22 07:11:56 PM PDT 24 Jul 22 07:12:25 PM PDT 24 326234585 ps
T358 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1968773235 Jul 22 07:12:08 PM PDT 24 Jul 22 07:12:47 PM PDT 24 4447346967 ps
T359 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1245902644 Jul 22 07:12:16 PM PDT 24 Jul 22 07:12:59 PM PDT 24 509170089 ps
T360 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4038679033 Jul 22 07:12:14 PM PDT 24 Jul 22 07:12:54 PM PDT 24 479909964 ps
T361 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3876387156 Jul 22 07:12:29 PM PDT 24 Jul 22 07:13:15 PM PDT 24 418334440 ps
T362 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1833529075 Jul 22 07:12:37 PM PDT 24 Jul 22 07:13:23 PM PDT 24 466376374 ps
T363 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.186464106 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:01 PM PDT 24 8934128646 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.448853611 Jul 22 07:11:43 PM PDT 24 Jul 22 07:12:08 PM PDT 24 440603627 ps
T365 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2195290360 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:00 PM PDT 24 320063533 ps
T366 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4055690781 Jul 22 07:12:03 PM PDT 24 Jul 22 07:12:40 PM PDT 24 300209934 ps
T367 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.564017524 Jul 22 07:11:43 PM PDT 24 Jul 22 07:12:08 PM PDT 24 517399325 ps
T368 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1343948565 Jul 22 07:11:56 PM PDT 24 Jul 22 07:12:25 PM PDT 24 460741380 ps
T58 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2365278897 Jul 22 07:11:57 PM PDT 24 Jul 22 07:12:27 PM PDT 24 469559443 ps
T369 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.756421375 Jul 22 07:12:08 PM PDT 24 Jul 22 07:12:47 PM PDT 24 502247648 ps
T370 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.345102247 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:56 PM PDT 24 423851904 ps
T371 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3366194909 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:57 PM PDT 24 464450187 ps
T372 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1465687783 Jul 22 07:12:10 PM PDT 24 Jul 22 07:12:51 PM PDT 24 4659152564 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4208853420 Jul 22 07:12:00 PM PDT 24 Jul 22 07:12:34 PM PDT 24 569058087 ps
T374 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1926403672 Jul 22 07:12:16 PM PDT 24 Jul 22 07:12:58 PM PDT 24 486534807 ps
T375 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2759996625 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:00 PM PDT 24 476003486 ps
T376 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2002369215 Jul 22 07:11:59 PM PDT 24 Jul 22 07:12:31 PM PDT 24 360570432 ps
T377 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2915520349 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:36 PM PDT 24 398685684 ps
T378 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3025514550 Jul 22 07:12:08 PM PDT 24 Jul 22 07:12:46 PM PDT 24 423896832 ps
T379 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2663729153 Jul 22 07:12:07 PM PDT 24 Jul 22 07:12:45 PM PDT 24 309436159 ps
T380 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1679525608 Jul 22 07:12:16 PM PDT 24 Jul 22 07:12:59 PM PDT 24 416703237 ps
T381 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.247345250 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:35 PM PDT 24 489638166 ps
T382 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2442192670 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:01 PM PDT 24 536623722 ps
T383 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1652667763 Jul 22 07:12:18 PM PDT 24 Jul 22 07:13:03 PM PDT 24 480769943 ps
T67 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1129024563 Jul 22 07:11:55 PM PDT 24 Jul 22 07:12:25 PM PDT 24 1356822251 ps
T384 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1173589746 Jul 22 07:12:03 PM PDT 24 Jul 22 07:12:41 PM PDT 24 2277514546 ps
T385 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3915616805 Jul 22 07:11:40 PM PDT 24 Jul 22 07:12:06 PM PDT 24 669255919 ps
T64 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1307551624 Jul 22 07:14:14 PM PDT 24 Jul 22 07:15:20 PM PDT 24 10394536218 ps
T386 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1121933017 Jul 22 07:12:03 PM PDT 24 Jul 22 07:12:40 PM PDT 24 450103265 ps
T387 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3938621113 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:56 PM PDT 24 433508781 ps
T388 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1434335172 Jul 22 07:12:28 PM PDT 24 Jul 22 07:13:13 PM PDT 24 303046290 ps
T389 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2853059256 Jul 22 07:12:05 PM PDT 24 Jul 22 07:12:43 PM PDT 24 985638978 ps
T390 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3583163347 Jul 22 07:11:55 PM PDT 24 Jul 22 07:12:25 PM PDT 24 566730379 ps
T391 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.121227559 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:59 PM PDT 24 4772736376 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4172724956 Jul 22 07:11:40 PM PDT 24 Jul 22 07:12:05 PM PDT 24 532045408 ps
T393 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3403365689 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:01 PM PDT 24 370056892 ps
T394 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3797323371 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:57 PM PDT 24 517539504 ps
T395 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1028228182 Jul 22 07:11:57 PM PDT 24 Jul 22 07:12:27 PM PDT 24 534730100 ps
T396 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3885340149 Jul 22 07:12:16 PM PDT 24 Jul 22 07:12:58 PM PDT 24 373493033 ps
T397 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3723776081 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:36 PM PDT 24 513090641 ps
T398 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3485367986 Jul 22 07:14:15 PM PDT 24 Jul 22 07:14:59 PM PDT 24 2260223598 ps
T399 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3042768507 Jul 22 07:12:04 PM PDT 24 Jul 22 07:12:41 PM PDT 24 413699036 ps
T400 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.48795982 Jul 22 07:12:17 PM PDT 24 Jul 22 07:12:59 PM PDT 24 459424105 ps
T401 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2412693789 Jul 22 07:12:15 PM PDT 24 Jul 22 07:12:57 PM PDT 24 369623627 ps
T402 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3716307184 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:35 PM PDT 24 382359283 ps
T403 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.163327516 Jul 22 07:12:10 PM PDT 24 Jul 22 07:12:49 PM PDT 24 437269337 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.998164596 Jul 22 07:11:57 PM PDT 24 Jul 22 07:12:25 PM PDT 24 472894974 ps
T405 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.143413954 Jul 22 07:11:56 PM PDT 24 Jul 22 07:12:38 PM PDT 24 6961013852 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2311515450 Jul 22 07:14:14 PM PDT 24 Jul 22 07:14:59 PM PDT 24 625782282 ps
T406 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3159204456 Jul 22 07:12:14 PM PDT 24 Jul 22 07:12:54 PM PDT 24 375525753 ps
T407 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3780978440 Jul 22 07:11:57 PM PDT 24 Jul 22 07:12:26 PM PDT 24 365524826 ps
T408 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2579040353 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:00 PM PDT 24 451727337 ps
T409 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3834130509 Jul 22 07:11:56 PM PDT 24 Jul 22 07:12:26 PM PDT 24 530394525 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2989142323 Jul 22 07:13:09 PM PDT 24 Jul 22 07:14:01 PM PDT 24 1138104472 ps
T200 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3007400171 Jul 22 07:12:10 PM PDT 24 Jul 22 07:12:52 PM PDT 24 8732436864 ps
T411 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.973798603 Jul 22 07:11:57 PM PDT 24 Jul 22 07:12:26 PM PDT 24 342886715 ps
T412 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.576131788 Jul 22 07:12:37 PM PDT 24 Jul 22 07:13:23 PM PDT 24 1087752833 ps
T413 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3221400676 Jul 22 07:12:16 PM PDT 24 Jul 22 07:12:59 PM PDT 24 493500857 ps
T414 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2183112985 Jul 22 07:12:17 PM PDT 24 Jul 22 07:13:01 PM PDT 24 347354224 ps
T415 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3435838734 Jul 22 07:11:57 PM PDT 24 Jul 22 07:12:27 PM PDT 24 508243211 ps
T416 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2329043056 Jul 22 07:12:14 PM PDT 24 Jul 22 07:12:54 PM PDT 24 2330226851 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4190076609 Jul 22 07:11:59 PM PDT 24 Jul 22 07:12:30 PM PDT 24 299919930 ps
T418 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1849278548 Jul 22 07:12:01 PM PDT 24 Jul 22 07:12:37 PM PDT 24 4664833017 ps
T419 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1024961007 Jul 22 07:11:55 PM PDT 24 Jul 22 07:12:33 PM PDT 24 7412043521 ps
T420 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3104638604 Jul 22 07:12:28 PM PDT 24 Jul 22 07:13:14 PM PDT 24 281842368 ps
T421 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1882655510 Jul 22 07:12:28 PM PDT 24 Jul 22 07:13:14 PM PDT 24 383684620 ps
T422 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.563013967 Jul 22 07:11:59 PM PDT 24 Jul 22 07:12:29 PM PDT 24 386178405 ps
T423 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2362986574 Jul 22 07:12:02 PM PDT 24 Jul 22 07:12:39 PM PDT 24 498301080 ps
T424 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1740670721 Jul 22 07:13:06 PM PDT 24 Jul 22 07:13:55 PM PDT 24 407554846 ps

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2044694218
Short name T8
Test name
Test status
Simulation time 44874430041 ps
CPU time 118.29 seconds
Started Jul 22 05:17:02 PM PDT 24
Finished Jul 22 05:19:01 PM PDT 24
Peak memory 214156 kb
Host smart-d5557fa6-0ac2-44db-97f3-168db94878ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044694218 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2044694218
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2666975157
Short name T3
Test name
Test status
Simulation time 224139480056 ps
CPU time 88.74 seconds
Started Jul 22 05:19:00 PM PDT 24
Finished Jul 22 05:20:30 PM PDT 24
Peak memory 198192 kb
Host smart-2b37c33f-d82e-4d86-ba8b-cf8331afedda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666975157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2666975157
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2488042423
Short name T32
Test name
Test status
Simulation time 261972065814 ps
CPU time 478.65 seconds
Started Jul 22 05:17:36 PM PDT 24
Finished Jul 22 05:25:36 PM PDT 24
Peak memory 211704 kb
Host smart-9c31e36d-e29b-41ff-aa6a-1f1e17baea70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488042423 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2488042423
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1103163601
Short name T40
Test name
Test status
Simulation time 129341112973 ps
CPU time 695.6 seconds
Started Jul 22 05:17:55 PM PDT 24
Finished Jul 22 05:29:31 PM PDT 24
Peak memory 206756 kb
Host smart-f60adc55-5e4a-4fe1-bb7c-d04e9415b858
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103163601 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1103163601
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1557781350
Short name T16
Test name
Test status
Simulation time 3813882541 ps
CPU time 5.26 seconds
Started Jul 22 05:16:41 PM PDT 24
Finished Jul 22 05:16:47 PM PDT 24
Peak memory 215392 kb
Host smart-9374439f-a82b-439d-b609-1867fa2b4e47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557781350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1557781350
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3113125904
Short name T27
Test name
Test status
Simulation time 344914320166 ps
CPU time 643.41 seconds
Started Jul 22 05:19:40 PM PDT 24
Finished Jul 22 05:30:23 PM PDT 24
Peak memory 205444 kb
Host smart-bc4cd3e5-b4e1-4ffd-b14f-3a9c98e1286e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113125904 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3113125904
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2784479991
Short name T124
Test name
Test status
Simulation time 462917451752 ps
CPU time 562.64 seconds
Started Jul 22 05:18:32 PM PDT 24
Finished Jul 22 05:27:56 PM PDT 24
Peak memory 204628 kb
Host smart-0539dee4-a850-4b59-b9c2-511a8bc140f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784479991 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2784479991
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3248697634
Short name T49
Test name
Test status
Simulation time 271725967566 ps
CPU time 525.88 seconds
Started Jul 22 05:19:22 PM PDT 24
Finished Jul 22 05:28:09 PM PDT 24
Peak memory 204264 kb
Host smart-84c7ad26-a919-4853-98a9-0bd45151dcb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248697634 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3248697634
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1101713573
Short name T84
Test name
Test status
Simulation time 105783198446 ps
CPU time 1051.58 seconds
Started Jul 22 05:18:12 PM PDT 24
Finished Jul 22 05:35:44 PM PDT 24
Peak memory 210560 kb
Host smart-2f2fa659-4e48-40aa-ba43-400113d5ce58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101713573 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1101713573
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2526917671
Short name T101
Test name
Test status
Simulation time 23907865947 ps
CPU time 171.02 seconds
Started Jul 22 05:18:23 PM PDT 24
Finished Jul 22 05:21:15 PM PDT 24
Peak memory 198452 kb
Host smart-579d1026-d3cd-4990-bc20-1e8c38a240b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526917671 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2526917671
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.306065342
Short name T71
Test name
Test status
Simulation time 2255449708 ps
CPU time 3.43 seconds
Started Jul 22 07:11:35 PM PDT 24
Finished Jul 22 07:12:01 PM PDT 24
Peak memory 192568 kb
Host smart-fc8ee3d6-303e-4c68-a0c8-64d84fbb6a0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306065342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.306065342
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3645224693
Short name T31
Test name
Test status
Simulation time 53826645903 ps
CPU time 486.3 seconds
Started Jul 22 05:20:46 PM PDT 24
Finished Jul 22 05:28:53 PM PDT 24
Peak memory 213912 kb
Host smart-7f46c248-4890-44ed-9ee8-7f010188e8f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645224693 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3645224693
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3453099084
Short name T135
Test name
Test status
Simulation time 935166573923 ps
CPU time 719.49 seconds
Started Jul 22 05:19:01 PM PDT 24
Finished Jul 22 05:31:01 PM PDT 24
Peak memory 214772 kb
Host smart-5f493bdb-660b-49b5-9532-8981afb45655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453099084 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3453099084
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2480594226
Short name T82
Test name
Test status
Simulation time 377363888988 ps
CPU time 920.11 seconds
Started Jul 22 05:18:58 PM PDT 24
Finished Jul 22 05:34:19 PM PDT 24
Peak memory 208864 kb
Host smart-89a9de9d-1680-4e66-b09f-3f1f4948e2a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480594226 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2480594226
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1308269065
Short name T88
Test name
Test status
Simulation time 1230725278817 ps
CPU time 584.94 seconds
Started Jul 22 05:17:29 PM PDT 24
Finished Jul 22 05:27:14 PM PDT 24
Peak memory 206688 kb
Host smart-966a395f-d7d1-45f6-b70a-f83493870714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308269065 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1308269065
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3563717914
Short name T131
Test name
Test status
Simulation time 428660598906 ps
CPU time 1162.17 seconds
Started Jul 22 05:17:39 PM PDT 24
Finished Jul 22 05:37:02 PM PDT 24
Peak memory 212312 kb
Host smart-f779d5d8-a9eb-443c-8cf6-f01e89a53ccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563717914 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3563717914
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1655433000
Short name T10
Test name
Test status
Simulation time 130394288617 ps
CPU time 201.38 seconds
Started Jul 22 05:19:11 PM PDT 24
Finished Jul 22 05:22:33 PM PDT 24
Peak memory 192764 kb
Host smart-cb6dd72a-951f-4d56-868a-8d4f6b7ce43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655433000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1655433000
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.691556502
Short name T100
Test name
Test status
Simulation time 66475119820 ps
CPU time 641.15 seconds
Started Jul 22 05:17:12 PM PDT 24
Finished Jul 22 05:27:54 PM PDT 24
Peak memory 212928 kb
Host smart-fd4b5691-6214-4cfd-8fe5-46ce62b9c3c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691556502 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.691556502
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3603123555
Short name T29
Test name
Test status
Simulation time 72729423244 ps
CPU time 610.7 seconds
Started Jul 22 05:18:00 PM PDT 24
Finished Jul 22 05:28:12 PM PDT 24
Peak memory 206644 kb
Host smart-2fb73f4c-b62e-4496-8025-b70804e3e8a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603123555 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3603123555
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3860649343
Short name T89
Test name
Test status
Simulation time 46848551767 ps
CPU time 350.89 seconds
Started Jul 22 05:18:43 PM PDT 24
Finished Jul 22 05:24:35 PM PDT 24
Peak memory 207368 kb
Host smart-f73a1cfd-3b7e-4fbc-8991-e93508ef364f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860649343 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3860649343
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1081447973
Short name T102
Test name
Test status
Simulation time 74093226459 ps
CPU time 108.65 seconds
Started Jul 22 05:17:39 PM PDT 24
Finished Jul 22 05:19:28 PM PDT 24
Peak memory 192928 kb
Host smart-bab212ec-fe05-4f76-ad1a-e3ede0fa2f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081447973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1081447973
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1746673225
Short name T23
Test name
Test status
Simulation time 8378368427 ps
CPU time 12.56 seconds
Started Jul 22 07:12:37 PM PDT 24
Finished Jul 22 07:13:34 PM PDT 24
Peak memory 198324 kb
Host smart-6032ffd9-8227-4b46-ba2a-a05a727ea923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746673225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1746673225
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2455035693
Short name T123
Test name
Test status
Simulation time 358800870488 ps
CPU time 35.02 seconds
Started Jul 22 05:17:22 PM PDT 24
Finished Jul 22 05:17:57 PM PDT 24
Peak memory 198144 kb
Host smart-0369aefd-9d05-4bdc-9fc8-f18f3edcdb5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455035693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2455035693
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2627118808
Short name T99
Test name
Test status
Simulation time 125424877027 ps
CPU time 186.18 seconds
Started Jul 22 05:17:48 PM PDT 24
Finished Jul 22 05:20:55 PM PDT 24
Peak memory 192940 kb
Host smart-760c4fae-ea54-4627-963b-bac877184d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627118808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2627118808
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2573994391
Short name T106
Test name
Test status
Simulation time 305455834318 ps
CPU time 113.91 seconds
Started Jul 22 05:18:48 PM PDT 24
Finished Jul 22 05:20:43 PM PDT 24
Peak memory 192908 kb
Host smart-1dc739be-5663-45c6-8c2a-af58099a97c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573994391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2573994391
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.682311655
Short name T19
Test name
Test status
Simulation time 86833442775 ps
CPU time 32.29 seconds
Started Jul 22 05:17:54 PM PDT 24
Finished Jul 22 05:18:27 PM PDT 24
Peak memory 192832 kb
Host smart-bd28925e-dc8d-4284-9e4f-7eb895894a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682311655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.682311655
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.132795892
Short name T94
Test name
Test status
Simulation time 345842199483 ps
CPU time 391.8 seconds
Started Jul 22 05:17:02 PM PDT 24
Finished Jul 22 05:23:35 PM PDT 24
Peak memory 202952 kb
Host smart-484f14e8-64ef-45ce-935e-16cb50fbf3a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132795892 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.132795892
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2887419309
Short name T163
Test name
Test status
Simulation time 32264528063 ps
CPU time 115.57 seconds
Started Jul 22 05:17:58 PM PDT 24
Finished Jul 22 05:19:54 PM PDT 24
Peak memory 206552 kb
Host smart-ae1662f2-5d78-4aa7-8942-cc2e34840907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887419309 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2887419309
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.636550757
Short name T114
Test name
Test status
Simulation time 201619698703 ps
CPU time 970.05 seconds
Started Jul 22 05:16:40 PM PDT 24
Finished Jul 22 05:32:51 PM PDT 24
Peak memory 209252 kb
Host smart-f09a5459-71bb-4fd5-b2cd-209e9942f595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636550757 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.636550757
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2798417932
Short name T43
Test name
Test status
Simulation time 116143746223 ps
CPU time 176.17 seconds
Started Jul 22 05:17:29 PM PDT 24
Finished Jul 22 05:20:25 PM PDT 24
Peak memory 192412 kb
Host smart-75b0b154-e33f-454c-b8a3-0dccda37e078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798417932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2798417932
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1633464553
Short name T92
Test name
Test status
Simulation time 167376222601 ps
CPU time 309.39 seconds
Started Jul 22 05:18:04 PM PDT 24
Finished Jul 22 05:23:13 PM PDT 24
Peak memory 201292 kb
Host smart-e88be476-3ac7-4338-8220-f1589df460dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633464553 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1633464553
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1307551624
Short name T64
Test name
Test status
Simulation time 10394536218 ps
CPU time 22.77 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:15:20 PM PDT 24
Peak memory 192712 kb
Host smart-0b614304-81e4-492d-b4fc-74b1a7739f63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307551624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1307551624
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.523722956
Short name T140
Test name
Test status
Simulation time 63219136626 ps
CPU time 70.8 seconds
Started Jul 22 05:17:47 PM PDT 24
Finished Jul 22 05:18:58 PM PDT 24
Peak memory 191812 kb
Host smart-0f927bfe-c1ec-41fa-9d5c-ac3e60fa5374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523722956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.523722956
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3709660585
Short name T139
Test name
Test status
Simulation time 148019732397 ps
CPU time 34.88 seconds
Started Jul 22 05:19:01 PM PDT 24
Finished Jul 22 05:19:36 PM PDT 24
Peak memory 191784 kb
Host smart-606c8a0d-33b0-4d19-8bba-987174e7c494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709660585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3709660585
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2313527399
Short name T96
Test name
Test status
Simulation time 251585244614 ps
CPU time 395.04 seconds
Started Jul 22 05:18:15 PM PDT 24
Finished Jul 22 05:24:51 PM PDT 24
Peak memory 192892 kb
Host smart-3e050aeb-7268-44fe-9517-9755307c4f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313527399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2313527399
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1255118865
Short name T33
Test name
Test status
Simulation time 60591614780 ps
CPU time 467.89 seconds
Started Jul 22 05:16:53 PM PDT 24
Finished Jul 22 05:24:41 PM PDT 24
Peak memory 214868 kb
Host smart-1e197d4a-d6ad-4d2f-a30a-fb170234d01b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255118865 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1255118865
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2299401068
Short name T168
Test name
Test status
Simulation time 786045101515 ps
CPU time 902.59 seconds
Started Jul 22 05:17:20 PM PDT 24
Finished Jul 22 05:32:24 PM PDT 24
Peak memory 214848 kb
Host smart-596bf8c6-a605-47fe-9e0c-ef0229210b48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299401068 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2299401068
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3315259748
Short name T120
Test name
Test status
Simulation time 296600975868 ps
CPU time 559.59 seconds
Started Jul 22 05:17:29 PM PDT 24
Finished Jul 22 05:26:50 PM PDT 24
Peak memory 204348 kb
Host smart-1b5baec3-555d-4bc9-9b30-1284b47b420b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315259748 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3315259748
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2159490889
Short name T107
Test name
Test status
Simulation time 262300099749 ps
CPU time 204.07 seconds
Started Jul 22 05:17:20 PM PDT 24
Finished Jul 22 05:20:45 PM PDT 24
Peak memory 192428 kb
Host smart-ec8a5a7d-138c-4a0a-86ce-c59b645b6c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159490889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2159490889
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.861953597
Short name T116
Test name
Test status
Simulation time 325082678275 ps
CPU time 69.04 seconds
Started Jul 22 05:20:46 PM PDT 24
Finished Jul 22 05:21:56 PM PDT 24
Peak memory 198188 kb
Host smart-304f9971-a3e1-4af0-95ba-9ee5b13438c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861953597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.861953597
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.611236533
Short name T41
Test name
Test status
Simulation time 53717471232 ps
CPU time 225.37 seconds
Started Jul 22 05:18:50 PM PDT 24
Finished Jul 22 05:22:36 PM PDT 24
Peak memory 198452 kb
Host smart-cd667ac0-6b3b-4b89-ae94-064a9b324287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611236533 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.611236533
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2221778252
Short name T86
Test name
Test status
Simulation time 17796390081 ps
CPU time 168.07 seconds
Started Jul 22 05:17:15 PM PDT 24
Finished Jul 22 05:20:03 PM PDT 24
Peak memory 198440 kb
Host smart-362d8466-0df5-47b3-bee9-d673199efa07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221778252 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2221778252
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3759149435
Short name T133
Test name
Test status
Simulation time 227394511109 ps
CPU time 73.33 seconds
Started Jul 22 05:16:40 PM PDT 24
Finished Jul 22 05:17:54 PM PDT 24
Peak memory 192916 kb
Host smart-4ccec8cd-3793-4241-b3cd-d288407a0565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759149435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3759149435
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3662213943
Short name T127
Test name
Test status
Simulation time 93619683809 ps
CPU time 129.51 seconds
Started Jul 22 05:17:25 PM PDT 24
Finished Jul 22 05:19:35 PM PDT 24
Peak memory 198108 kb
Host smart-6330e41a-fd2b-4f16-8b59-9284d5423e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662213943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3662213943
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3658595617
Short name T90
Test name
Test status
Simulation time 18520828947 ps
CPU time 139.85 seconds
Started Jul 22 05:19:06 PM PDT 24
Finished Jul 22 05:21:27 PM PDT 24
Peak memory 198352 kb
Host smart-3e9c9873-5df1-4c89-8beb-3a72166f0a3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658595617 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3658595617
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.673286665
Short name T128
Test name
Test status
Simulation time 77203563706 ps
CPU time 457.15 seconds
Started Jul 22 05:18:10 PM PDT 24
Finished Jul 22 05:25:48 PM PDT 24
Peak memory 211128 kb
Host smart-6ee2ec11-8e71-4aa9-9b9a-b635ce8f3bc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673286665 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.673286665
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.297674873
Short name T122
Test name
Test status
Simulation time 19826021199 ps
CPU time 216.03 seconds
Started Jul 22 05:18:13 PM PDT 24
Finished Jul 22 05:21:50 PM PDT 24
Peak memory 213916 kb
Host smart-8019687e-dbc4-4044-b618-f57e2e2718e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297674873 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.297674873
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1594503941
Short name T98
Test name
Test status
Simulation time 11329095292 ps
CPU time 82.87 seconds
Started Jul 22 05:18:24 PM PDT 24
Finished Jul 22 05:19:47 PM PDT 24
Peak memory 213916 kb
Host smart-0edac2d9-d0a6-4983-8724-ecc1d3af1b34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594503941 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1594503941
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1026078358
Short name T115
Test name
Test status
Simulation time 75625626557 ps
CPU time 25.95 seconds
Started Jul 22 05:17:02 PM PDT 24
Finished Jul 22 05:17:28 PM PDT 24
Peak memory 198160 kb
Host smart-71027aca-734f-485f-a93f-2b7c30252e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026078358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1026078358
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1262756462
Short name T83
Test name
Test status
Simulation time 258352026735 ps
CPU time 529.62 seconds
Started Jul 22 05:17:03 PM PDT 24
Finished Jul 22 05:25:54 PM PDT 24
Peak memory 212168 kb
Host smart-04acd709-19bc-4aad-823b-4abef17eb61e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262756462 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1262756462
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1632767868
Short name T66
Test name
Test status
Simulation time 59572543518 ps
CPU time 504.24 seconds
Started Jul 22 05:17:26 PM PDT 24
Finished Jul 22 05:25:51 PM PDT 24
Peak memory 214860 kb
Host smart-376f5edc-43fd-468a-8086-beb4127aa497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632767868 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1632767868
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.914067425
Short name T76
Test name
Test status
Simulation time 67895248410 ps
CPU time 91.43 seconds
Started Jul 22 05:16:50 PM PDT 24
Finished Jul 22 05:18:22 PM PDT 24
Peak memory 198184 kb
Host smart-3ddc8959-be3e-4544-8cdf-d9e124e3e772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914067425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.914067425
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1656809325
Short name T105
Test name
Test status
Simulation time 214544550340 ps
CPU time 50.98 seconds
Started Jul 22 05:18:10 PM PDT 24
Finished Jul 22 05:19:02 PM PDT 24
Peak memory 191832 kb
Host smart-042ca6bf-698e-485b-ae87-ad24654a76ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656809325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1656809325
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2262109753
Short name T138
Test name
Test status
Simulation time 186705275062 ps
CPU time 266.8 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:22:52 PM PDT 24
Peak memory 191700 kb
Host smart-835391e5-b84a-402a-9b32-837372c3e23f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262109753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2262109753
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.4259560825
Short name T154
Test name
Test status
Simulation time 163487922784 ps
CPU time 171.38 seconds
Started Jul 22 05:18:34 PM PDT 24
Finished Jul 22 05:21:26 PM PDT 24
Peak memory 191820 kb
Host smart-b9097b43-fb08-46cb-88ec-ff67913e7a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259560825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.4259560825
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.805767776
Short name T112
Test name
Test status
Simulation time 224065278361 ps
CPU time 342.12 seconds
Started Jul 22 05:18:59 PM PDT 24
Finished Jul 22 05:24:42 PM PDT 24
Peak memory 198172 kb
Host smart-c69e12d0-089a-43aa-b7f6-7b3868dd69db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805767776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.805767776
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1081742522
Short name T137
Test name
Test status
Simulation time 241424825971 ps
CPU time 71.71 seconds
Started Jul 22 05:18:38 PM PDT 24
Finished Jul 22 05:19:50 PM PDT 24
Peak memory 192904 kb
Host smart-b95ffe46-b7b2-4552-9819-72e9a99ee9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081742522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1081742522
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3602931884
Short name T30
Test name
Test status
Simulation time 59000297587 ps
CPU time 529.35 seconds
Started Jul 22 05:18:04 PM PDT 24
Finished Jul 22 05:26:54 PM PDT 24
Peak memory 214016 kb
Host smart-63f18fd5-267f-4796-8ff5-5f9bae2fb982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602931884 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3602931884
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2468808509
Short name T151
Test name
Test status
Simulation time 53487793737 ps
CPU time 36.67 seconds
Started Jul 22 05:17:04 PM PDT 24
Finished Jul 22 05:17:41 PM PDT 24
Peak memory 191780 kb
Host smart-6abb4b61-733d-481b-99fd-a77e905be823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468808509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2468808509
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3978658350
Short name T147
Test name
Test status
Simulation time 29451340647 ps
CPU time 20.25 seconds
Started Jul 22 05:18:32 PM PDT 24
Finished Jul 22 05:18:53 PM PDT 24
Peak memory 198124 kb
Host smart-29dbfbc3-df95-4263-bce7-c5651f519ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978658350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3978658350
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1100117988
Short name T87
Test name
Test status
Simulation time 117356951018 ps
CPU time 233.99 seconds
Started Jul 22 05:17:36 PM PDT 24
Finished Jul 22 05:21:31 PM PDT 24
Peak memory 206648 kb
Host smart-1cb2a77a-c410-460c-8d65-0db15d8ad01a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100117988 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1100117988
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3071525720
Short name T148
Test name
Test status
Simulation time 437712390160 ps
CPU time 373.9 seconds
Started Jul 22 05:17:02 PM PDT 24
Finished Jul 22 05:23:16 PM PDT 24
Peak memory 192940 kb
Host smart-da66504c-0a28-4c0b-8be2-3e2f8683af28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071525720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3071525720
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1695277104
Short name T13
Test name
Test status
Simulation time 119708034054 ps
CPU time 243.77 seconds
Started Jul 22 05:19:15 PM PDT 24
Finished Jul 22 05:23:20 PM PDT 24
Peak memory 208604 kb
Host smart-7d302800-c43e-4588-881f-d2f108cd1a33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695277104 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1695277104
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.4265815727
Short name T132
Test name
Test status
Simulation time 57111565274 ps
CPU time 22.12 seconds
Started Jul 22 05:18:23 PM PDT 24
Finished Jul 22 05:18:46 PM PDT 24
Peak memory 191856 kb
Host smart-cf877c4e-2e09-48af-af94-8199193f6422
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265815727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.4265815727
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1680806993
Short name T160
Test name
Test status
Simulation time 94142391976 ps
CPU time 253.89 seconds
Started Jul 22 05:17:26 PM PDT 24
Finished Jul 22 05:21:40 PM PDT 24
Peak memory 209012 kb
Host smart-02b24f6f-8c7b-403c-80f6-117216001810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680806993 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1680806993
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3456070671
Short name T146
Test name
Test status
Simulation time 56151476373 ps
CPU time 244.02 seconds
Started Jul 22 05:17:47 PM PDT 24
Finished Jul 22 05:21:52 PM PDT 24
Peak memory 198696 kb
Host smart-bd19d9f9-7372-42a9-83f3-ebb398756cf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456070671 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3456070671
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3729584320
Short name T141
Test name
Test status
Simulation time 143718806933 ps
CPU time 94.51 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:20:00 PM PDT 24
Peak memory 192884 kb
Host smart-50d50206-c928-4c91-926a-5aae98cbc6f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729584320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3729584320
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3405051794
Short name T136
Test name
Test status
Simulation time 561091129577 ps
CPU time 360.12 seconds
Started Jul 22 05:18:31 PM PDT 24
Finished Jul 22 05:24:31 PM PDT 24
Peak memory 192088 kb
Host smart-1ba806e7-e43d-4ead-b445-e0a507e4e4fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405051794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3405051794
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2911328233
Short name T118
Test name
Test status
Simulation time 45031649713 ps
CPU time 25.05 seconds
Started Jul 22 05:18:42 PM PDT 24
Finished Jul 22 05:19:07 PM PDT 24
Peak memory 191844 kb
Host smart-9f220059-72d0-41e0-bf15-4d10861f90a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911328233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2911328233
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.646261033
Short name T113
Test name
Test status
Simulation time 538602307 ps
CPU time 1.05 seconds
Started Jul 22 05:17:11 PM PDT 24
Finished Jul 22 05:17:13 PM PDT 24
Peak memory 196524 kb
Host smart-61b388fd-037d-4237-a6fd-585fd524fb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646261033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.646261033
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3584477820
Short name T12
Test name
Test status
Simulation time 308051368441 ps
CPU time 455.43 seconds
Started Jul 22 05:17:20 PM PDT 24
Finished Jul 22 05:24:57 PM PDT 24
Peak memory 198164 kb
Host smart-5fec4cb3-5543-4132-a6d5-87c74849057c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584477820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3584477820
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3498134879
Short name T143
Test name
Test status
Simulation time 452651791 ps
CPU time 0.95 seconds
Started Jul 22 05:17:30 PM PDT 24
Finished Jul 22 05:17:32 PM PDT 24
Peak memory 196500 kb
Host smart-c089dd85-b795-48d8-ab17-9dfaa425269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498134879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3498134879
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1084214637
Short name T7
Test name
Test status
Simulation time 165969273443 ps
CPU time 43.82 seconds
Started Jul 22 05:18:53 PM PDT 24
Finished Jul 22 05:19:37 PM PDT 24
Peak memory 198204 kb
Host smart-45c45e15-a290-403b-b6bf-b5f05af48dee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084214637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1084214637
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4027462581
Short name T108
Test name
Test status
Simulation time 550354333 ps
CPU time 0.74 seconds
Started Jul 22 05:17:13 PM PDT 24
Finished Jul 22 05:17:14 PM PDT 24
Peak memory 196608 kb
Host smart-62f306d3-3e58-4647-b33d-6c6d174bedfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027462581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4027462581
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3397976185
Short name T125
Test name
Test status
Simulation time 390203462 ps
CPU time 0.77 seconds
Started Jul 22 05:17:13 PM PDT 24
Finished Jul 22 05:17:15 PM PDT 24
Peak memory 196564 kb
Host smart-e74ef556-aaca-4dde-b202-ada85cf436bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397976185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3397976185
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.863955715
Short name T126
Test name
Test status
Simulation time 383987599 ps
CPU time 0.74 seconds
Started Jul 22 05:17:20 PM PDT 24
Finished Jul 22 05:17:21 PM PDT 24
Peak memory 196660 kb
Host smart-6f63d32e-16dd-4a79-8533-69c4f77497f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863955715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.863955715
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.340432339
Short name T166
Test name
Test status
Simulation time 15568298148 ps
CPU time 34.01 seconds
Started Jul 22 05:17:29 PM PDT 24
Finished Jul 22 05:18:03 PM PDT 24
Peak memory 213824 kb
Host smart-88bf6a00-c4b6-4213-93a8-f54901be756c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340432339 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.340432339
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1686883357
Short name T149
Test name
Test status
Simulation time 591362881 ps
CPU time 0.72 seconds
Started Jul 22 05:16:50 PM PDT 24
Finished Jul 22 05:16:51 PM PDT 24
Peak memory 196392 kb
Host smart-c6c270c1-f722-47a8-94a1-0a75d2c06fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686883357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1686883357
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.204121032
Short name T2
Test name
Test status
Simulation time 489391810 ps
CPU time 0.78 seconds
Started Jul 22 05:18:16 PM PDT 24
Finished Jul 22 05:18:18 PM PDT 24
Peak memory 196524 kb
Host smart-b787df48-fd2e-4076-ba20-3e6394226e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204121032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.204121032
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.278142774
Short name T144
Test name
Test status
Simulation time 132788037068 ps
CPU time 42.81 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:19:09 PM PDT 24
Peak memory 191744 kb
Host smart-a58e8888-ca21-4ff3-a65d-a9341279e5da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278142774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.278142774
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.4272359971
Short name T175
Test name
Test status
Simulation time 5578551091 ps
CPU time 2.98 seconds
Started Jul 22 05:19:01 PM PDT 24
Finished Jul 22 05:19:04 PM PDT 24
Peak memory 192860 kb
Host smart-dfd4693e-2f06-4c7f-b7c2-09db431010d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272359971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.4272359971
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.787958212
Short name T110
Test name
Test status
Simulation time 322886952617 ps
CPU time 472.3 seconds
Started Jul 22 05:17:40 PM PDT 24
Finished Jul 22 05:25:33 PM PDT 24
Peak memory 192800 kb
Host smart-050e3fe2-237a-4110-b1fc-c198470453ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787958212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.787958212
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3016705752
Short name T145
Test name
Test status
Simulation time 457818325 ps
CPU time 0.78 seconds
Started Jul 22 05:17:46 PM PDT 24
Finished Jul 22 05:17:47 PM PDT 24
Peak memory 196528 kb
Host smart-1bc30898-0655-40fe-9bc1-84fd767fcba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016705752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3016705752
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3918640975
Short name T130
Test name
Test status
Simulation time 617818595 ps
CPU time 1.14 seconds
Started Jul 22 05:17:56 PM PDT 24
Finished Jul 22 05:17:58 PM PDT 24
Peak memory 196524 kb
Host smart-b9cced79-d68a-48f1-b8ff-4fc0309562a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918640975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3918640975
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.953763268
Short name T109
Test name
Test status
Simulation time 463117719 ps
CPU time 0.73 seconds
Started Jul 22 05:17:56 PM PDT 24
Finished Jul 22 05:17:57 PM PDT 24
Peak memory 196500 kb
Host smart-c9e8e4d9-d81a-40f1-8459-10f5d6095b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953763268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.953763268
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3798227397
Short name T28
Test name
Test status
Simulation time 17915913849 ps
CPU time 195.95 seconds
Started Jul 22 05:18:15 PM PDT 24
Finished Jul 22 05:21:32 PM PDT 24
Peak memory 198960 kb
Host smart-6e3a0af2-4ba0-4a6d-8c5d-5de5d5aa46ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798227397 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3798227397
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.470493690
Short name T97
Test name
Test status
Simulation time 89949139494 ps
CPU time 144.97 seconds
Started Jul 22 05:18:14 PM PDT 24
Finished Jul 22 05:20:40 PM PDT 24
Peak memory 184144 kb
Host smart-af9e1a6a-49a6-49c3-8bf0-87e0a582585a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470493690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.470493690
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1935245444
Short name T104
Test name
Test status
Simulation time 509378364 ps
CPU time 0.65 seconds
Started Jul 22 05:18:41 PM PDT 24
Finished Jul 22 05:18:42 PM PDT 24
Peak memory 196396 kb
Host smart-268ee4ee-6fdc-4f09-9a8c-2c93b97cf40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935245444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1935245444
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2170445504
Short name T95
Test name
Test status
Simulation time 446537951 ps
CPU time 1.26 seconds
Started Jul 22 05:18:59 PM PDT 24
Finished Jul 22 05:19:00 PM PDT 24
Peak memory 196552 kb
Host smart-c37ef2f1-d828-42e3-9c10-a14b75cef01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170445504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2170445504
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3785031971
Short name T119
Test name
Test status
Simulation time 35919122158 ps
CPU time 10.44 seconds
Started Jul 22 05:17:23 PM PDT 24
Finished Jul 22 05:17:34 PM PDT 24
Peak memory 191832 kb
Host smart-890e4b5b-f103-48a8-8666-ee8cbeded24f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785031971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3785031971
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1469815695
Short name T85
Test name
Test status
Simulation time 106178266958 ps
CPU time 442.94 seconds
Started Jul 22 05:17:36 PM PDT 24
Finished Jul 22 05:25:00 PM PDT 24
Peak memory 214356 kb
Host smart-7011af5b-d231-41e0-aa6a-92c00aaefec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469815695 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1469815695
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2568779765
Short name T142
Test name
Test status
Simulation time 521756690 ps
CPU time 0.67 seconds
Started Jul 22 05:17:57 PM PDT 24
Finished Jul 22 05:17:59 PM PDT 24
Peak memory 196524 kb
Host smart-d841b7ad-a7de-44e6-954d-3dc5c18c1a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568779765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2568779765
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3964668906
Short name T103
Test name
Test status
Simulation time 591515547 ps
CPU time 0.78 seconds
Started Jul 22 05:18:11 PM PDT 24
Finished Jul 22 05:18:13 PM PDT 24
Peak memory 196484 kb
Host smart-5a31945c-e327-4de6-94cb-07f949b6b02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964668906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3964668906
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2227135080
Short name T111
Test name
Test status
Simulation time 385730818 ps
CPU time 1.18 seconds
Started Jul 22 05:16:40 PM PDT 24
Finished Jul 22 05:16:42 PM PDT 24
Peak memory 196604 kb
Host smart-64f86d58-54ea-4fc7-9e79-4bdddbcd129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227135080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2227135080
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1223865119
Short name T150
Test name
Test status
Simulation time 27421690691 ps
CPU time 59.69 seconds
Started Jul 22 05:17:31 PM PDT 24
Finished Jul 22 05:18:32 PM PDT 24
Peak memory 206692 kb
Host smart-573cd533-1f7e-4ce8-96e2-8ec72c8feb93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223865119 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1223865119
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3160980022
Short name T159
Test name
Test status
Simulation time 224917030849 ps
CPU time 182.07 seconds
Started Jul 22 05:16:52 PM PDT 24
Finished Jul 22 05:19:54 PM PDT 24
Peak memory 192800 kb
Host smart-34f7e610-cfee-4b21-bf65-f2e619ca7634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160980022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3160980022
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2177318639
Short name T178
Test name
Test status
Simulation time 186952436428 ps
CPU time 276.06 seconds
Started Jul 22 05:18:19 PM PDT 24
Finished Jul 22 05:22:56 PM PDT 24
Peak memory 208708 kb
Host smart-9eefabfe-7b4e-4197-a467-1c1202cdec67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177318639 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2177318639
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1085557491
Short name T6
Test name
Test status
Simulation time 357396652 ps
CPU time 1.28 seconds
Started Jul 22 05:18:11 PM PDT 24
Finished Jul 22 05:18:13 PM PDT 24
Peak memory 196520 kb
Host smart-8f95acfd-573e-464b-bd11-74b5da9829bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085557491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1085557491
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.190167396
Short name T117
Test name
Test status
Simulation time 519193240 ps
CPU time 0.66 seconds
Started Jul 22 05:18:32 PM PDT 24
Finished Jul 22 05:18:33 PM PDT 24
Peak memory 196540 kb
Host smart-d1a9ca55-7e73-43f2-a272-cc87a3b99f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190167396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.190167396
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1286592260
Short name T50
Test name
Test status
Simulation time 67898109859 ps
CPU time 271.21 seconds
Started Jul 22 05:18:34 PM PDT 24
Finished Jul 22 05:23:05 PM PDT 24
Peak memory 206596 kb
Host smart-e9c02276-9e4f-4e11-a96d-ef6945d06de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286592260 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1286592260
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.23574900
Short name T155
Test name
Test status
Simulation time 178613944218 ps
CPU time 56.45 seconds
Started Jul 22 05:18:44 PM PDT 24
Finished Jul 22 05:19:41 PM PDT 24
Peak memory 191776 kb
Host smart-af2dd979-8310-4298-b388-095fc124905f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23574900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_al
l.23574900
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.557250406
Short name T157
Test name
Test status
Simulation time 222615473676 ps
CPU time 301.67 seconds
Started Jul 22 05:18:49 PM PDT 24
Finished Jul 22 05:23:51 PM PDT 24
Peak memory 192760 kb
Host smart-845caf0f-3e67-421d-9cd0-e3ec0cb7c1b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557250406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.557250406
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.849841710
Short name T161
Test name
Test status
Simulation time 38602714652 ps
CPU time 136.72 seconds
Started Jul 22 05:19:11 PM PDT 24
Finished Jul 22 05:21:28 PM PDT 24
Peak memory 213876 kb
Host smart-bb47a3bb-7e0c-47d4-8c41-ab9656a7f3c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849841710 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.849841710
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.943455069
Short name T180
Test name
Test status
Simulation time 203187205439 ps
CPU time 137.25 seconds
Started Jul 22 05:17:12 PM PDT 24
Finished Jul 22 05:19:30 PM PDT 24
Peak memory 191768 kb
Host smart-408b8a0b-eb4f-483d-8d7d-aa98817c43bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943455069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.943455069
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3734568067
Short name T37
Test name
Test status
Simulation time 531776921 ps
CPU time 0.8 seconds
Started Jul 22 05:17:26 PM PDT 24
Finished Jul 22 05:17:27 PM PDT 24
Peak memory 196476 kb
Host smart-e133066f-4049-47c0-b6ba-ebbfedd35b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734568067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3734568067
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1305667911
Short name T48
Test name
Test status
Simulation time 55944238189 ps
CPU time 26.22 seconds
Started Jul 22 05:17:31 PM PDT 24
Finished Jul 22 05:17:57 PM PDT 24
Peak memory 198208 kb
Host smart-9d7c460f-85db-411a-8aad-a64caea6fc0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305667911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1305667911
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.4060413775
Short name T184
Test name
Test status
Simulation time 361982952 ps
CPU time 0.97 seconds
Started Jul 22 05:17:41 PM PDT 24
Finished Jul 22 05:17:44 PM PDT 24
Peak memory 196588 kb
Host smart-8c7c05c5-ee3a-42ef-bfea-c4dd7e476596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060413775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.4060413775
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1023406777
Short name T158
Test name
Test status
Simulation time 58902023277 ps
CPU time 87.8 seconds
Started Jul 22 05:17:29 PM PDT 24
Finished Jul 22 05:18:58 PM PDT 24
Peak memory 191828 kb
Host smart-f7cde4d2-b819-439b-92b9-2fdaa6878819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023406777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1023406777
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1130340423
Short name T192
Test name
Test status
Simulation time 598329264 ps
CPU time 0.67 seconds
Started Jul 22 05:17:27 PM PDT 24
Finished Jul 22 05:17:28 PM PDT 24
Peak memory 196476 kb
Host smart-86261ab0-45b0-47d3-ad2d-bcdb53ed946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130340423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1130340423
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2186611511
Short name T164
Test name
Test status
Simulation time 23198412419 ps
CPU time 111.3 seconds
Started Jul 22 05:16:51 PM PDT 24
Finished Jul 22 05:18:43 PM PDT 24
Peak memory 206596 kb
Host smart-4897b542-449f-44cc-84a5-c88d6f60de8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186611511 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2186611511
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.552281924
Short name T185
Test name
Test status
Simulation time 498214680 ps
CPU time 0.74 seconds
Started Jul 22 05:19:15 PM PDT 24
Finished Jul 22 05:19:16 PM PDT 24
Peak memory 196508 kb
Host smart-3a1009ee-cef1-4210-98a9-d1ab549582ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552281924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.552281924
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3069032321
Short name T170
Test name
Test status
Simulation time 587037063 ps
CPU time 1.43 seconds
Started Jul 22 05:17:41 PM PDT 24
Finished Jul 22 05:17:44 PM PDT 24
Peak memory 196404 kb
Host smart-ae4b9f7f-fde3-4ddf-8921-19fa47b7c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069032321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3069032321
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1257061079
Short name T11
Test name
Test status
Simulation time 73684955621 ps
CPU time 144.27 seconds
Started Jul 22 05:19:00 PM PDT 24
Finished Jul 22 05:21:24 PM PDT 24
Peak memory 214172 kb
Host smart-4e272494-61ea-4897-9594-bcc58dbb64f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257061079 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1257061079
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2293330096
Short name T153
Test name
Test status
Simulation time 287356243987 ps
CPU time 39.21 seconds
Started Jul 22 05:17:03 PM PDT 24
Finished Jul 22 05:17:43 PM PDT 24
Peak memory 198208 kb
Host smart-38a61996-a681-4546-8b86-e835ae72d601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293330096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2293330096
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3305966288
Short name T172
Test name
Test status
Simulation time 22648789812 ps
CPU time 82.42 seconds
Started Jul 22 05:17:13 PM PDT 24
Finished Jul 22 05:18:36 PM PDT 24
Peak memory 198452 kb
Host smart-9840485b-0dab-418b-9d53-4c30ba37ad52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305966288 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3305966288
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3007400171
Short name T200
Test name
Test status
Simulation time 8732436864 ps
CPU time 4.06 seconds
Started Jul 22 07:12:10 PM PDT 24
Finished Jul 22 07:12:52 PM PDT 24
Peak memory 198612 kb
Host smart-52097f82-0ac7-4a78-a048-ca65776bf543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007400171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3007400171
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4182379809
Short name T156
Test name
Test status
Simulation time 555879470 ps
CPU time 1.39 seconds
Started Jul 22 05:17:18 PM PDT 24
Finished Jul 22 05:17:20 PM PDT 24
Peak memory 196592 kb
Host smart-90bbd824-eab3-4e34-9d48-07a53d0ab75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182379809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4182379809
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4240584469
Short name T134
Test name
Test status
Simulation time 423799688925 ps
CPU time 658.04 seconds
Started Jul 22 05:17:39 PM PDT 24
Finished Jul 22 05:28:37 PM PDT 24
Peak memory 198132 kb
Host smart-8deb4601-e4fa-4176-bd22-90200f82892a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240584469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4240584469
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.848457879
Short name T191
Test name
Test status
Simulation time 530076252 ps
CPU time 0.9 seconds
Started Jul 22 05:17:48 PM PDT 24
Finished Jul 22 05:17:49 PM PDT 24
Peak memory 196468 kb
Host smart-d2bed590-c996-40b2-860d-3d863404d775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848457879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.848457879
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.762936791
Short name T152
Test name
Test status
Simulation time 497609827 ps
CPU time 0.65 seconds
Started Jul 22 05:18:15 PM PDT 24
Finished Jul 22 05:18:17 PM PDT 24
Peak memory 196632 kb
Host smart-d0facd36-22f4-45da-a13b-f8f8564e552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762936791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.762936791
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.368419967
Short name T179
Test name
Test status
Simulation time 477313566 ps
CPU time 1.18 seconds
Started Jul 22 05:18:23 PM PDT 24
Finished Jul 22 05:18:25 PM PDT 24
Peak memory 196544 kb
Host smart-aea79c5c-bc01-40dc-9e8b-035bc8b7d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368419967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.368419967
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3279146525
Short name T18
Test name
Test status
Simulation time 428949032 ps
CPU time 0.8 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:18:27 PM PDT 24
Peak memory 196640 kb
Host smart-5bb38351-fb12-4304-a287-dde771d26c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279146525 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3279146525
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3437927632
Short name T121
Test name
Test status
Simulation time 451674630 ps
CPU time 1.25 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:18:27 PM PDT 24
Peak memory 196560 kb
Host smart-62c20e86-e24e-49f1-8aeb-6406deb67f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437927632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3437927632
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3688069325
Short name T177
Test name
Test status
Simulation time 505907156 ps
CPU time 1.28 seconds
Started Jul 22 05:16:50 PM PDT 24
Finished Jul 22 05:16:52 PM PDT 24
Peak memory 196480 kb
Host smart-b3791844-83ee-4e67-a0bb-eafe6794f39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688069325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3688069325
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4046622505
Short name T186
Test name
Test status
Simulation time 426637500 ps
CPU time 0.73 seconds
Started Jul 22 05:18:31 PM PDT 24
Finished Jul 22 05:18:33 PM PDT 24
Peak memory 196508 kb
Host smart-2b845c35-cda4-40fb-8b01-aea3bb741388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046622505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4046622505
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.535258657
Short name T181
Test name
Test status
Simulation time 531591438 ps
CPU time 0.62 seconds
Started Jul 22 05:18:41 PM PDT 24
Finished Jul 22 05:18:42 PM PDT 24
Peak memory 196492 kb
Host smart-bccbe144-5bb7-4ea4-9ba2-759d663fd8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535258657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.535258657
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.4094526762
Short name T183
Test name
Test status
Simulation time 585240765 ps
CPU time 0.82 seconds
Started Jul 22 05:19:09 PM PDT 24
Finished Jul 22 05:19:10 PM PDT 24
Peak memory 196508 kb
Host smart-79d44096-96ed-4785-bf5b-5462aba0dc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094526762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.4094526762
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2847696896
Short name T174
Test name
Test status
Simulation time 490626071 ps
CPU time 0.69 seconds
Started Jul 22 05:18:59 PM PDT 24
Finished Jul 22 05:19:01 PM PDT 24
Peak memory 196404 kb
Host smart-dc2fe4e5-02cd-4e1d-9800-7d9f81aa635d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847696896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2847696896
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3943459470
Short name T78
Test name
Test status
Simulation time 587699211 ps
CPU time 1.47 seconds
Started Jul 22 05:17:02 PM PDT 24
Finished Jul 22 05:17:05 PM PDT 24
Peak memory 196436 kb
Host smart-167db3d6-3a29-4a2b-ae8c-cf7919662d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943459470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3943459470
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1686346863
Short name T165
Test name
Test status
Simulation time 573691359 ps
CPU time 1.41 seconds
Started Jul 22 05:16:39 PM PDT 24
Finished Jul 22 05:16:41 PM PDT 24
Peak memory 196576 kb
Host smart-7ba194bc-1dd4-4300-85e1-4c01d92dfbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686346863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1686346863
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1139969009
Short name T193
Test name
Test status
Simulation time 474429655 ps
CPU time 1.22 seconds
Started Jul 22 05:17:12 PM PDT 24
Finished Jul 22 05:17:13 PM PDT 24
Peak memory 196392 kb
Host smart-402a8ce2-8e22-4e9a-8f06-b2b769be5fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139969009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1139969009
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2946069794
Short name T39
Test name
Test status
Simulation time 123795665510 ps
CPU time 89.75 seconds
Started Jul 22 05:17:15 PM PDT 24
Finished Jul 22 05:18:45 PM PDT 24
Peak memory 192208 kb
Host smart-27582da7-c236-4cfd-b44d-9feb20da6cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946069794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2946069794
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3475815811
Short name T176
Test name
Test status
Simulation time 505707497 ps
CPU time 0.77 seconds
Started Jul 22 05:17:13 PM PDT 24
Finished Jul 22 05:17:15 PM PDT 24
Peak memory 196432 kb
Host smart-3b0d8a07-1e54-4712-bb50-2e72cd35718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475815811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3475815811
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3227537928
Short name T129
Test name
Test status
Simulation time 583157061 ps
CPU time 0.75 seconds
Started Jul 22 05:19:08 PM PDT 24
Finished Jul 22 05:19:09 PM PDT 24
Peak memory 196520 kb
Host smart-5d35c43f-c70d-4d52-89f4-177c9421d333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227537928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3227537928
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2613977050
Short name T162
Test name
Test status
Simulation time 537418461 ps
CPU time 0.69 seconds
Started Jul 22 05:17:38 PM PDT 24
Finished Jul 22 05:17:40 PM PDT 24
Peak memory 196428 kb
Host smart-bbc1c483-e393-4adc-8a1e-88550c422798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613977050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2613977050
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1120918744
Short name T169
Test name
Test status
Simulation time 540154252 ps
CPU time 0.81 seconds
Started Jul 22 05:19:15 PM PDT 24
Finished Jul 22 05:19:17 PM PDT 24
Peak memory 196496 kb
Host smart-ec44a562-a591-44a1-9a44-ee7b9d2ba164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120918744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1120918744
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2528576647
Short name T189
Test name
Test status
Simulation time 629197988 ps
CPU time 0.83 seconds
Started Jul 22 05:16:50 PM PDT 24
Finished Jul 22 05:16:51 PM PDT 24
Peak memory 196428 kb
Host smart-7ddde809-3393-4106-86e7-d9683140335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528576647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2528576647
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1406247895
Short name T173
Test name
Test status
Simulation time 526402593 ps
CPU time 0.9 seconds
Started Jul 22 05:18:16 PM PDT 24
Finished Jul 22 05:18:18 PM PDT 24
Peak memory 196348 kb
Host smart-e41ce86c-93e3-430d-b558-f7640349ac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406247895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1406247895
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4212733179
Short name T187
Test name
Test status
Simulation time 431805925 ps
CPU time 0.75 seconds
Started Jul 22 05:19:31 PM PDT 24
Finished Jul 22 05:19:32 PM PDT 24
Peak memory 196568 kb
Host smart-5be9cfa7-4145-4c4a-8eb4-771def94fd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212733179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4212733179
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_jump.817028867
Short name T38
Test name
Test status
Simulation time 517821855 ps
CPU time 1.43 seconds
Started Jul 22 05:17:03 PM PDT 24
Finished Jul 22 05:17:05 PM PDT 24
Peak memory 196508 kb
Host smart-a07476f4-1993-4b1f-a6bd-63b7b08f6264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817028867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.817028867
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3276968449
Short name T188
Test name
Test status
Simulation time 400450266 ps
CPU time 1.11 seconds
Started Jul 22 05:17:02 PM PDT 24
Finished Jul 22 05:17:04 PM PDT 24
Peak memory 196484 kb
Host smart-378393e8-cf21-4979-9ff5-190789cf6da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276968449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3276968449
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.943037930
Short name T190
Test name
Test status
Simulation time 158125059761 ps
CPU time 53.82 seconds
Started Jul 22 05:17:14 PM PDT 24
Finished Jul 22 05:18:08 PM PDT 24
Peak memory 192500 kb
Host smart-e75b321d-c2b1-4f8d-a05c-defddc27a6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943037930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.943037930
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2311515450
Short name T59
Test name
Test status
Simulation time 625782282 ps
CPU time 1.87 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 184408 kb
Host smart-60d22135-bdb0-4fb9-a4b6-854c826a2761
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311515450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2311515450
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3777219782
Short name T324
Test name
Test status
Simulation time 1241631134 ps
CPU time 2.49 seconds
Started Jul 22 07:11:40 PM PDT 24
Finished Jul 22 07:12:07 PM PDT 24
Peak memory 193848 kb
Host smart-ebc829b0-6d1b-4fda-af7d-18de0737f85a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777219782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3777219782
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2549695745
Short name T22
Test name
Test status
Simulation time 561540562 ps
CPU time 0.88 seconds
Started Jul 22 07:11:33 PM PDT 24
Finished Jul 22 07:11:58 PM PDT 24
Peak memory 197244 kb
Host smart-2de8d5b6-fb86-437a-bbc8-ce7aafeaf896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549695745 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2549695745
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2898138959
Short name T57
Test name
Test status
Simulation time 506774594 ps
CPU time 1.22 seconds
Started Jul 22 07:11:40 PM PDT 24
Finished Jul 22 07:12:06 PM PDT 24
Peak memory 194180 kb
Host smart-0d3c9285-fca9-41b8-a614-e51332097871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898138959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2898138959
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.564017524
Short name T367
Test name
Test status
Simulation time 517399325 ps
CPU time 1.22 seconds
Started Jul 22 07:11:43 PM PDT 24
Finished Jul 22 07:12:08 PM PDT 24
Peak memory 184232 kb
Host smart-8b25148e-59f1-4cbc-97c2-f6288a635f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564017524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.564017524
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4172724956
Short name T392
Test name
Test status
Simulation time 532045408 ps
CPU time 0.7 seconds
Started Jul 22 07:11:40 PM PDT 24
Finished Jul 22 07:12:05 PM PDT 24
Peak memory 184372 kb
Host smart-b83f2ebd-9c34-4092-8653-53eab2632cb6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172724956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.4172724956
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.448853611
Short name T364
Test name
Test status
Simulation time 440603627 ps
CPU time 1.15 seconds
Started Jul 22 07:11:43 PM PDT 24
Finished Jul 22 07:12:08 PM PDT 24
Peak memory 184144 kb
Host smart-bd5670de-48d6-444e-8389-acff7dcba7aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448853611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.448853611
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.865952415
Short name T300
Test name
Test status
Simulation time 741112426 ps
CPU time 2.12 seconds
Started Jul 22 07:11:53 PM PDT 24
Finished Jul 22 07:12:21 PM PDT 24
Peak memory 199072 kb
Host smart-b81659c4-e5e8-47c3-a71d-ada5a5e30473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865952415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.865952415
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3655454347
Short name T314
Test name
Test status
Simulation time 4407560194 ps
CPU time 2.48 seconds
Started Jul 22 07:11:43 PM PDT 24
Finished Jul 22 07:12:09 PM PDT 24
Peak memory 198280 kb
Host smart-093be563-310c-410f-aa7d-50545addd5dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655454347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3655454347
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2176463791
Short name T201
Test name
Test status
Simulation time 703223025 ps
CPU time 1.34 seconds
Started Jul 22 07:12:49 PM PDT 24
Finished Jul 22 07:13:37 PM PDT 24
Peak memory 192436 kb
Host smart-d46ce51d-ed05-462e-be6a-ea421c25a0be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176463791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2176463791
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.143413954
Short name T405
Test name
Test status
Simulation time 6961013852 ps
CPU time 13.76 seconds
Started Jul 22 07:11:56 PM PDT 24
Finished Jul 22 07:12:38 PM PDT 24
Peak memory 184460 kb
Host smart-c7bc77dc-bdf3-4ca0-b9d4-45341108f54f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143413954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.143413954
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3161491742
Short name T299
Test name
Test status
Simulation time 919298442 ps
CPU time 1.81 seconds
Started Jul 22 07:11:55 PM PDT 24
Finished Jul 22 07:12:23 PM PDT 24
Peak memory 184248 kb
Host smart-48031578-bdda-49bd-87ea-c4c537389152
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161491742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3161491742
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4269396768
Short name T344
Test name
Test status
Simulation time 402808096 ps
CPU time 0.87 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:36 PM PDT 24
Peak memory 196776 kb
Host smart-eebe7a7a-5d40-476b-8ecf-19fd1cd49db5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269396768 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.4269396768
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2775541667
Short name T54
Test name
Test status
Simulation time 301543512 ps
CPU time 0.66 seconds
Started Jul 22 07:11:59 PM PDT 24
Finished Jul 22 07:12:29 PM PDT 24
Peak memory 194488 kb
Host smart-2719aac4-2cd3-4d75-8845-42cadb80d7de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775541667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2775541667
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.563013967
Short name T422
Test name
Test status
Simulation time 386178405 ps
CPU time 0.67 seconds
Started Jul 22 07:11:59 PM PDT 24
Finished Jul 22 07:12:29 PM PDT 24
Peak memory 184308 kb
Host smart-9f02df85-ecab-483a-9fa7-04570e046024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563013967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.563013967
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3780978440
Short name T407
Test name
Test status
Simulation time 365524826 ps
CPU time 1.03 seconds
Started Jul 22 07:11:57 PM PDT 24
Finished Jul 22 07:12:26 PM PDT 24
Peak memory 184148 kb
Host smart-d5ebeddd-c347-461b-a1ff-d52efd9a73a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780978440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3780978440
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1677469606
Short name T357
Test name
Test status
Simulation time 326234585 ps
CPU time 0.93 seconds
Started Jul 22 07:11:56 PM PDT 24
Finished Jul 22 07:12:25 PM PDT 24
Peak memory 184076 kb
Host smart-f10a68d0-9ccd-4b8e-b55e-224518ea6dd7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677469606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1677469606
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2630892963
Short name T301
Test name
Test status
Simulation time 2360535876 ps
CPU time 0.92 seconds
Started Jul 22 07:11:54 PM PDT 24
Finished Jul 22 07:12:22 PM PDT 24
Peak memory 195564 kb
Host smart-95e05ac7-ddbd-4c12-99b7-a9bd4f556a46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630892963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2630892963
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3915616805
Short name T385
Test name
Test status
Simulation time 669255919 ps
CPU time 1.97 seconds
Started Jul 22 07:11:40 PM PDT 24
Finished Jul 22 07:12:06 PM PDT 24
Peak memory 199304 kb
Host smart-7661e01e-62b5-4611-b2aa-864039b61277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915616805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3915616805
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3293603377
Short name T24
Test name
Test status
Simulation time 4471393360 ps
CPU time 2.44 seconds
Started Jul 22 07:11:40 PM PDT 24
Finished Jul 22 07:12:07 PM PDT 24
Peak memory 198580 kb
Host smart-c46a5f9c-556f-4816-a413-2f3323a0bbd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293603377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3293603377
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4244953546
Short name T203
Test name
Test status
Simulation time 487715885 ps
CPU time 1.48 seconds
Started Jul 22 07:12:37 PM PDT 24
Finished Jul 22 07:13:23 PM PDT 24
Peak memory 196800 kb
Host smart-91ee2f5c-efbf-4b83-bef7-09ce7931699a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244953546 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4244953546
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3746195137
Short name T69
Test name
Test status
Simulation time 540032737 ps
CPU time 0.63 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:14:58 PM PDT 24
Peak memory 193440 kb
Host smart-5d57fc09-f533-4c40-89bd-9f0f5350277f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746195137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3746195137
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2211418956
Short name T321
Test name
Test status
Simulation time 327456785 ps
CPU time 0.64 seconds
Started Jul 22 07:12:08 PM PDT 24
Finished Jul 22 07:12:46 PM PDT 24
Peak memory 184216 kb
Host smart-c4a426f2-2fd0-4965-8a86-556842093df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211418956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2211418956
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1391881436
Short name T20
Test name
Test status
Simulation time 1249076511 ps
CPU time 1.4 seconds
Started Jul 22 07:13:11 PM PDT 24
Finished Jul 22 07:14:02 PM PDT 24
Peak memory 193540 kb
Host smart-9fec1be3-9a32-4268-9c4c-4fdf3bf8fd61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391881436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1391881436
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3008724359
Short name T327
Test name
Test status
Simulation time 488548565 ps
CPU time 3.19 seconds
Started Jul 22 07:12:02 PM PDT 24
Finished Jul 22 07:12:40 PM PDT 24
Peak memory 199140 kb
Host smart-45ce3915-ef71-4f5a-917b-a6187be78da3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008724359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3008724359
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3742373817
Short name T343
Test name
Test status
Simulation time 588651197 ps
CPU time 0.92 seconds
Started Jul 22 07:12:07 PM PDT 24
Finished Jul 22 07:12:46 PM PDT 24
Peak memory 198868 kb
Host smart-d89ee710-14e1-44c7-b41c-f047f865db5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742373817 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3742373817
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2663729153
Short name T379
Test name
Test status
Simulation time 309436159 ps
CPU time 0.77 seconds
Started Jul 22 07:12:07 PM PDT 24
Finished Jul 22 07:12:45 PM PDT 24
Peak memory 193432 kb
Host smart-14d9c35a-d872-4f5c-b069-81b660e44add
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663729153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2663729153
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1112295099
Short name T297
Test name
Test status
Simulation time 312597324 ps
CPU time 0.95 seconds
Started Jul 22 07:13:07 PM PDT 24
Finished Jul 22 07:13:57 PM PDT 24
Peak memory 184320 kb
Host smart-9dec98d4-02b4-4750-9936-007d9dac13d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112295099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1112295099
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2989142323
Short name T410
Test name
Test status
Simulation time 1138104472 ps
CPU time 1.33 seconds
Started Jul 22 07:13:09 PM PDT 24
Finished Jul 22 07:14:01 PM PDT 24
Peak memory 194176 kb
Host smart-6536c497-f920-4a62-a912-4bf95cf35e9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989142323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2989142323
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4143928808
Short name T298
Test name
Test status
Simulation time 491544871 ps
CPU time 1.24 seconds
Started Jul 22 07:12:07 PM PDT 24
Finished Jul 22 07:12:45 PM PDT 24
Peak memory 198864 kb
Host smart-022349a4-7027-4914-abe8-211400802365
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143928808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4143928808
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1465687783
Short name T372
Test name
Test status
Simulation time 4659152564 ps
CPU time 2.51 seconds
Started Jul 22 07:12:10 PM PDT 24
Finished Jul 22 07:12:51 PM PDT 24
Peak memory 198464 kb
Host smart-4e1cee5a-9b89-4921-b4fc-cf0aba1fb7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465687783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1465687783
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.69051007
Short name T340
Test name
Test status
Simulation time 559158151 ps
CPU time 0.93 seconds
Started Jul 22 07:12:07 PM PDT 24
Finished Jul 22 07:12:45 PM PDT 24
Peak memory 196664 kb
Host smart-90450fc2-f169-4d79-92b8-5a682d1f4fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69051007 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.69051007
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3855905261
Short name T61
Test name
Test status
Simulation time 342028965 ps
CPU time 0.68 seconds
Started Jul 22 07:12:04 PM PDT 24
Finished Jul 22 07:12:39 PM PDT 24
Peak memory 193448 kb
Host smart-93099da1-5f9c-42c6-887c-a20de2ce8e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855905261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3855905261
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2915520349
Short name T377
Test name
Test status
Simulation time 398685684 ps
CPU time 1.12 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:36 PM PDT 24
Peak memory 193448 kb
Host smart-6dab09e4-f29c-4baa-9cfa-081d07016c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915520349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2915520349
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1954994803
Short name T319
Test name
Test status
Simulation time 1624163263 ps
CPU time 2.69 seconds
Started Jul 22 07:13:09 PM PDT 24
Finished Jul 22 07:14:02 PM PDT 24
Peak memory 194564 kb
Host smart-2cadc872-132d-4ce7-b346-23f294296861
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954994803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1954994803
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2202558160
Short name T305
Test name
Test status
Simulation time 411944491 ps
CPU time 2.34 seconds
Started Jul 22 07:12:05 PM PDT 24
Finished Jul 22 07:12:42 PM PDT 24
Peak memory 199116 kb
Host smart-75a18c44-64b9-471e-a599-13df2a6d5b69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202558160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2202558160
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2810838685
Short name T198
Test name
Test status
Simulation time 3952452295 ps
CPU time 5.8 seconds
Started Jul 22 07:12:02 PM PDT 24
Finished Jul 22 07:12:43 PM PDT 24
Peak memory 197988 kb
Host smart-9b00a1e0-f50a-41a6-aba0-292dc6bf3472
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810838685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2810838685
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1446095606
Short name T293
Test name
Test status
Simulation time 505465764 ps
CPU time 1.34 seconds
Started Jul 22 07:12:37 PM PDT 24
Finished Jul 22 07:13:23 PM PDT 24
Peak memory 196996 kb
Host smart-2a29f8aa-c775-4ec6-b2cf-a153a9248747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446095606 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1446095606
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3897629025
Short name T26
Test name
Test status
Simulation time 467473981 ps
CPU time 1.19 seconds
Started Jul 22 07:12:37 PM PDT 24
Finished Jul 22 07:13:23 PM PDT 24
Peak memory 193220 kb
Host smart-14f2fb25-4b74-49c9-b8d6-cc9a92f457bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897629025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3897629025
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3241716322
Short name T333
Test name
Test status
Simulation time 559869775 ps
CPU time 0.59 seconds
Started Jul 22 07:14:29 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 193444 kb
Host smart-2328e8ad-7fe1-4ec3-9bb4-4ca48a92a421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241716322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3241716322
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.576131788
Short name T412
Test name
Test status
Simulation time 1087752833 ps
CPU time 0.95 seconds
Started Jul 22 07:12:37 PM PDT 24
Finished Jul 22 07:13:23 PM PDT 24
Peak memory 184208 kb
Host smart-faca4e1a-5a36-440e-81a2-2bd4d9b648a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576131788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.576131788
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.407023637
Short name T330
Test name
Test status
Simulation time 663114711 ps
CPU time 1.33 seconds
Started Jul 22 07:13:10 PM PDT 24
Finished Jul 22 07:14:01 PM PDT 24
Peak memory 199148 kb
Host smart-659dfc52-6fe5-4446-bfe4-fdd5aa6b685c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407023637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.407023637
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.98422213
Short name T197
Test name
Test status
Simulation time 4473929978 ps
CPU time 4.04 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:04 PM PDT 24
Peak memory 198168 kb
Host smart-f1297c01-d194-45d5-816f-f415d7f07a65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98422213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_
intg_err.98422213
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3692202320
Short name T304
Test name
Test status
Simulation time 346347099 ps
CPU time 1.09 seconds
Started Jul 22 07:12:02 PM PDT 24
Finished Jul 22 07:12:38 PM PDT 24
Peak memory 196024 kb
Host smart-5a8ce83b-1e8d-46b7-94b2-464b99c6839f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692202320 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3692202320
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4058952402
Short name T62
Test name
Test status
Simulation time 398230310 ps
CPU time 1.18 seconds
Started Jul 22 07:12:10 PM PDT 24
Finished Jul 22 07:12:49 PM PDT 24
Peak memory 193468 kb
Host smart-5118febb-3449-4145-a89f-03b2c90f6d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058952402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4058952402
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3025514550
Short name T378
Test name
Test status
Simulation time 423896832 ps
CPU time 0.65 seconds
Started Jul 22 07:12:08 PM PDT 24
Finished Jul 22 07:12:46 PM PDT 24
Peak memory 184208 kb
Host smart-f8e0918d-4143-414a-b290-406211e24626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025514550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3025514550
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.272002574
Short name T75
Test name
Test status
Simulation time 1742765508 ps
CPU time 0.92 seconds
Started Jul 22 07:12:37 PM PDT 24
Finished Jul 22 07:13:23 PM PDT 24
Peak memory 195332 kb
Host smart-e3d333a5-3a0a-430f-bbf3-df703d89d955
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272002574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon
_timer_same_csr_outstanding.272002574
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2773303768
Short name T307
Test name
Test status
Simulation time 369633062 ps
CPU time 1.99 seconds
Started Jul 22 07:12:03 PM PDT 24
Finished Jul 22 07:12:41 PM PDT 24
Peak memory 199096 kb
Host smart-66d59f2c-5688-4ce2-9db7-0dd8171fa84c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773303768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2773303768
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.186464106
Short name T363
Test name
Test status
Simulation time 8934128646 ps
CPU time 2.85 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:01 PM PDT 24
Peak memory 198832 kb
Host smart-6580055b-d227-446f-838c-81e9ffeb7adb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186464106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.186464106
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.48795982
Short name T400
Test name
Test status
Simulation time 459424105 ps
CPU time 0.78 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:12:59 PM PDT 24
Peak memory 197820 kb
Host smart-c71aaf2b-b51d-4c34-9740-6229de2347a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48795982 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.48795982
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3133048475
Short name T63
Test name
Test status
Simulation time 578393025 ps
CPU time 0.81 seconds
Started Jul 22 07:12:10 PM PDT 24
Finished Jul 22 07:12:49 PM PDT 24
Peak memory 194240 kb
Host smart-5995d84c-a0e5-4307-b1a1-1b809002d972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133048475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3133048475
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2759996625
Short name T375
Test name
Test status
Simulation time 476003486 ps
CPU time 1.25 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:00 PM PDT 24
Peak memory 184064 kb
Host smart-8c171738-8ef5-48c2-a5ce-8391770cfe02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759996625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2759996625
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3485367986
Short name T398
Test name
Test status
Simulation time 2260223598 ps
CPU time 1.39 seconds
Started Jul 22 07:14:15 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 194528 kb
Host smart-07ecfde1-44a2-45aa-b1e0-3021508341e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485367986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3485367986
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.756421375
Short name T369
Test name
Test status
Simulation time 502247648 ps
CPU time 2.45 seconds
Started Jul 22 07:12:08 PM PDT 24
Finished Jul 22 07:12:47 PM PDT 24
Peak memory 199048 kb
Host smart-c75ec668-3a8d-4acb-a263-3ac80cd5fe13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756421375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.756421375
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1703581370
Short name T350
Test name
Test status
Simulation time 8365985825 ps
CPU time 4.4 seconds
Started Jul 22 07:12:08 PM PDT 24
Finished Jul 22 07:12:51 PM PDT 24
Peak memory 198876 kb
Host smart-7d3d3bc0-63cf-4582-8519-d152539d822f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703581370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1703581370
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3334853707
Short name T335
Test name
Test status
Simulation time 556115083 ps
CPU time 0.81 seconds
Started Jul 22 07:12:06 PM PDT 24
Finished Jul 22 07:12:43 PM PDT 24
Peak memory 196308 kb
Host smart-4f014d5e-f81c-4857-906e-e8b2698adc0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334853707 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3334853707
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4055690781
Short name T366
Test name
Test status
Simulation time 300209934 ps
CPU time 1 seconds
Started Jul 22 07:12:03 PM PDT 24
Finished Jul 22 07:12:40 PM PDT 24
Peak memory 193408 kb
Host smart-de10af58-71b5-4ca7-ae71-66f5107ba958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055690781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4055690781
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3042768507
Short name T399
Test name
Test status
Simulation time 413699036 ps
CPU time 1.11 seconds
Started Jul 22 07:12:04 PM PDT 24
Finished Jul 22 07:12:41 PM PDT 24
Peak memory 184196 kb
Host smart-55e7d0b1-3e38-4e2a-a6c5-924b5920662e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042768507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3042768507
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3795554926
Short name T70
Test name
Test status
Simulation time 2974322157 ps
CPU time 4.75 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:13:01 PM PDT 24
Peak memory 195892 kb
Host smart-25530fcc-e4b0-40b5-9882-7ce779ee6069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795554926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3795554926
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2853059256
Short name T389
Test name
Test status
Simulation time 985638978 ps
CPU time 2.92 seconds
Started Jul 22 07:12:05 PM PDT 24
Finished Jul 22 07:12:43 PM PDT 24
Peak memory 199108 kb
Host smart-55f44aaa-bd91-47b6-9c8a-20aa3144db68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853059256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2853059256
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1968773235
Short name T358
Test name
Test status
Simulation time 4447346967 ps
CPU time 1.66 seconds
Started Jul 22 07:12:08 PM PDT 24
Finished Jul 22 07:12:47 PM PDT 24
Peak memory 197276 kb
Host smart-aeecfe71-5afe-4ed9-95e9-cdb5955a9170
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968773235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1968773235
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3714178550
Short name T302
Test name
Test status
Simulation time 377058298 ps
CPU time 1.01 seconds
Started Jul 22 07:12:06 PM PDT 24
Finished Jul 22 07:12:43 PM PDT 24
Peak memory 196728 kb
Host smart-de820dd2-cfd9-417b-b0fc-eb05e9fe510e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714178550 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3714178550
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1652667763
Short name T383
Test name
Test status
Simulation time 480769943 ps
CPU time 1.41 seconds
Started Jul 22 07:12:18 PM PDT 24
Finished Jul 22 07:13:03 PM PDT 24
Peak memory 193852 kb
Host smart-4a309e82-4e86-4288-8907-4fc403a90aed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652667763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1652667763
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1833529075
Short name T362
Test name
Test status
Simulation time 466376374 ps
CPU time 1.17 seconds
Started Jul 22 07:12:37 PM PDT 24
Finished Jul 22 07:13:23 PM PDT 24
Peak memory 184108 kb
Host smart-2b96c85d-d24d-4f33-9712-7ac94f1a8af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833529075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1833529075
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2954731338
Short name T72
Test name
Test status
Simulation time 1095704261 ps
CPU time 1.46 seconds
Started Jul 22 07:12:08 PM PDT 24
Finished Jul 22 07:12:48 PM PDT 24
Peak memory 193436 kb
Host smart-f920d961-eb83-4557-9705-caa5b22ea202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954731338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2954731338
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2442192670
Short name T382
Test name
Test status
Simulation time 536623722 ps
CPU time 1.86 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:01 PM PDT 24
Peak memory 198928 kb
Host smart-cf3544af-acb0-4c0d-b364-e1e63572b1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442192670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2442192670
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3352894849
Short name T331
Test name
Test status
Simulation time 3997650761 ps
CPU time 6.46 seconds
Started Jul 22 07:12:37 PM PDT 24
Finished Jul 22 07:13:28 PM PDT 24
Peak memory 198112 kb
Host smart-166846bd-1a15-4513-a494-282738302930
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352894849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3352894849
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2412693789
Short name T401
Test name
Test status
Simulation time 369623627 ps
CPU time 0.82 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:57 PM PDT 24
Peak memory 197248 kb
Host smart-8e50a57d-94c3-4eeb-bbd2-949fabbfa18f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412693789 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2412693789
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1126600850
Short name T202
Test name
Test status
Simulation time 449363269 ps
CPU time 0.83 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:00 PM PDT 24
Peak memory 193432 kb
Host smart-63eed106-f713-4515-9a99-ade2a6f415f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126600850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1126600850
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3723776081
Short name T397
Test name
Test status
Simulation time 513090641 ps
CPU time 1.17 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:36 PM PDT 24
Peak memory 184176 kb
Host smart-cb58e791-36ce-4e6d-bb50-92c4787d966c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723776081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3723776081
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1944421580
Short name T334
Test name
Test status
Simulation time 2477170790 ps
CPU time 1.4 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:58 PM PDT 24
Peak memory 194632 kb
Host smart-9903dd89-46a4-4606-b9db-b6d53e8af583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944421580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1944421580
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.931846231
Short name T291
Test name
Test status
Simulation time 472065745 ps
CPU time 2.18 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:02 PM PDT 24
Peak memory 199092 kb
Host smart-04b574d2-ea4d-44be-9668-0b93d01f184d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931846231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.931846231
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1679525608
Short name T380
Test name
Test status
Simulation time 416703237 ps
CPU time 1.22 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:12:59 PM PDT 24
Peak memory 197948 kb
Host smart-4cf2a510-6c90-4a06-b5ff-39074179be8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679525608 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1679525608
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3391053880
Short name T55
Test name
Test status
Simulation time 499715909 ps
CPU time 1.02 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:12:59 PM PDT 24
Peak memory 193520 kb
Host smart-ed237fd0-1e11-42f1-a728-d7caa837fdb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391053880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3391053880
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3159204456
Short name T406
Test name
Test status
Simulation time 375525753 ps
CPU time 0.68 seconds
Started Jul 22 07:12:14 PM PDT 24
Finished Jul 22 07:12:54 PM PDT 24
Peak memory 184264 kb
Host smart-b350e08e-c296-4d96-ab01-ee2667d14888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159204456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3159204456
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2329043056
Short name T416
Test name
Test status
Simulation time 2330226851 ps
CPU time 1.17 seconds
Started Jul 22 07:12:14 PM PDT 24
Finished Jul 22 07:12:54 PM PDT 24
Peak memory 184596 kb
Host smart-ccc8b2e7-d6a6-401f-8e7e-67829cfbc380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329043056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2329043056
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2187105419
Short name T356
Test name
Test status
Simulation time 598486501 ps
CPU time 1.32 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:58 PM PDT 24
Peak memory 198764 kb
Host smart-2d91c41a-2d69-4a63-b9eb-b1b8245a0a3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187105419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2187105419
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.121227559
Short name T391
Test name
Test status
Simulation time 4772736376 ps
CPU time 3.95 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:59 PM PDT 24
Peak memory 197252 kb
Host smart-5f413e60-244e-4f76-9095-44202eafe3da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121227559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.121227559
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3308938623
Short name T345
Test name
Test status
Simulation time 541554505 ps
CPU time 1.01 seconds
Started Jul 22 07:11:55 PM PDT 24
Finished Jul 22 07:12:23 PM PDT 24
Peak memory 184232 kb
Host smart-ec05c9c1-d402-4c4b-97e6-f988a7fcef1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308938623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3308938623
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1518640335
Short name T313
Test name
Test status
Simulation time 7080832586 ps
CPU time 9.93 seconds
Started Jul 22 07:11:52 PM PDT 24
Finished Jul 22 07:12:28 PM PDT 24
Peak memory 197000 kb
Host smart-c47ac70f-6c6f-434a-86de-14e352d011ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518640335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1518640335
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3733175110
Short name T342
Test name
Test status
Simulation time 1454297834 ps
CPU time 1.15 seconds
Started Jul 22 07:11:59 PM PDT 24
Finished Jul 22 07:12:32 PM PDT 24
Peak memory 193448 kb
Host smart-b23b0500-483b-4a96-bbc0-edc60a57b2c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733175110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3733175110
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3531889403
Short name T348
Test name
Test status
Simulation time 450657817 ps
CPU time 0.87 seconds
Started Jul 22 07:11:55 PM PDT 24
Finished Jul 22 07:12:23 PM PDT 24
Peak memory 197760 kb
Host smart-3f48e09d-2e1b-4744-af04-11454de6e029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531889403 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3531889403
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2365278897
Short name T58
Test name
Test status
Simulation time 469559443 ps
CPU time 1.22 seconds
Started Jul 22 07:11:57 PM PDT 24
Finished Jul 22 07:12:27 PM PDT 24
Peak memory 192480 kb
Host smart-e7f2dfbf-e92e-475d-9479-6b8919e352a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365278897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2365278897
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2002369215
Short name T376
Test name
Test status
Simulation time 360570432 ps
CPU time 1.04 seconds
Started Jul 22 07:11:59 PM PDT 24
Finished Jul 22 07:12:31 PM PDT 24
Peak memory 184148 kb
Host smart-b26d64f9-d311-4e2f-bc45-9af672619bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002369215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2002369215
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.4192729071
Short name T351
Test name
Test status
Simulation time 380802264 ps
CPU time 0.65 seconds
Started Jul 22 07:11:58 PM PDT 24
Finished Jul 22 07:12:28 PM PDT 24
Peak memory 184152 kb
Host smart-3e2f42f8-0d8f-4cfc-b508-9908bc9878c5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192729071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.4192729071
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3106952967
Short name T328
Test name
Test status
Simulation time 359498751 ps
CPU time 0.97 seconds
Started Jul 22 07:11:54 PM PDT 24
Finished Jul 22 07:12:21 PM PDT 24
Peak memory 184200 kb
Host smart-d02aaf52-82d4-47d9-b75e-99a46a8e1201
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106952967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3106952967
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.759784912
Short name T21
Test name
Test status
Simulation time 1466686007 ps
CPU time 1.11 seconds
Started Jul 22 07:12:03 PM PDT 24
Finished Jul 22 07:12:39 PM PDT 24
Peak memory 193432 kb
Host smart-da044410-7270-4187-9c73-e7d9615aef50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759784912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.759784912
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4271403764
Short name T316
Test name
Test status
Simulation time 366632591 ps
CPU time 1.78 seconds
Started Jul 22 07:11:57 PM PDT 24
Finished Jul 22 07:12:27 PM PDT 24
Peak memory 199032 kb
Host smart-85ee1c8f-900f-4b49-aabc-ea7222e8e6a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271403764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4271403764
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2680277778
Short name T347
Test name
Test status
Simulation time 7862454601 ps
CPU time 12.85 seconds
Started Jul 22 07:11:59 PM PDT 24
Finished Jul 22 07:12:42 PM PDT 24
Peak memory 198912 kb
Host smart-50f978ac-f343-4bb4-aaa1-0e58047ca481
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680277778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2680277778
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.345102247
Short name T370
Test name
Test status
Simulation time 423851904 ps
CPU time 1.06 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:56 PM PDT 24
Peak memory 184260 kb
Host smart-6f340ed1-ee1c-4276-9e62-781a6abba8b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345102247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.345102247
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3938621113
Short name T387
Test name
Test status
Simulation time 433508781 ps
CPU time 1.21 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:56 PM PDT 24
Peak memory 184284 kb
Host smart-ff9823e3-5794-481a-b5e5-403132356219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938621113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3938621113
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3797323371
Short name T394
Test name
Test status
Simulation time 517539504 ps
CPU time 1.3 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:57 PM PDT 24
Peak memory 184232 kb
Host smart-e3cfefa6-f8a0-4007-a0c2-08131d9a3752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797323371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3797323371
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1926403672
Short name T374
Test name
Test status
Simulation time 486534807 ps
CPU time 0.65 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:12:58 PM PDT 24
Peak memory 184240 kb
Host smart-bd4217eb-d22f-4e82-8f4f-08c13cfd1462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926403672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1926403672
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3383206539
Short name T310
Test name
Test status
Simulation time 323304292 ps
CPU time 0.8 seconds
Started Jul 22 07:13:13 PM PDT 24
Finished Jul 22 07:14:01 PM PDT 24
Peak memory 184320 kb
Host smart-6c8a45f2-e41f-4622-a3d7-b1d6fb6515fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383206539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3383206539
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1373088151
Short name T306
Test name
Test status
Simulation time 521184095 ps
CPU time 0.68 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:12:58 PM PDT 24
Peak memory 184164 kb
Host smart-eeae2f7c-0ee7-49b7-ac40-7774df387fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373088151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1373088151
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3403365689
Short name T393
Test name
Test status
Simulation time 370056892 ps
CPU time 1.11 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:01 PM PDT 24
Peak memory 193448 kb
Host smart-509cbb87-f8dc-498a-8e0c-611246320f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403365689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3403365689
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3553575449
Short name T320
Test name
Test status
Simulation time 323421832 ps
CPU time 0.78 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:12:59 PM PDT 24
Peak memory 193508 kb
Host smart-6be28ae5-d0e3-4de9-8ef9-81460db4dbeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553575449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3553575449
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3366194909
Short name T371
Test name
Test status
Simulation time 464450187 ps
CPU time 0.78 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:57 PM PDT 24
Peak memory 184232 kb
Host smart-93cdf69d-e53d-4eb5-8a1c-c672edae37d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366194909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3366194909
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1821440750
Short name T294
Test name
Test status
Simulation time 418429137 ps
CPU time 1.21 seconds
Started Jul 22 07:12:14 PM PDT 24
Finished Jul 22 07:12:55 PM PDT 24
Peak memory 184148 kb
Host smart-e74832de-fa26-4351-900f-5dc8104f7555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821440750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1821440750
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2837814212
Short name T52
Test name
Test status
Simulation time 381463642 ps
CPU time 0.92 seconds
Started Jul 22 07:11:56 PM PDT 24
Finished Jul 22 07:12:24 PM PDT 24
Peak memory 184196 kb
Host smart-c9f2345e-7122-47d8-a8c0-184b6d9f8847
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837814212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2837814212
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.847612599
Short name T322
Test name
Test status
Simulation time 14761262276 ps
CPU time 4.32 seconds
Started Jul 22 07:11:57 PM PDT 24
Finished Jul 22 07:12:29 PM PDT 24
Peak memory 192784 kb
Host smart-43014fbb-13b0-4080-98b8-4af58513ea14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847612599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.847612599
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1129024563
Short name T67
Test name
Test status
Simulation time 1356822251 ps
CPU time 2.26 seconds
Started Jul 22 07:11:55 PM PDT 24
Finished Jul 22 07:12:25 PM PDT 24
Peak memory 184224 kb
Host smart-acb769b4-59ae-4f84-ac9c-9946487282b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129024563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1129024563
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.973798603
Short name T411
Test name
Test status
Simulation time 342886715 ps
CPU time 1.15 seconds
Started Jul 22 07:11:57 PM PDT 24
Finished Jul 22 07:12:26 PM PDT 24
Peak memory 196368 kb
Host smart-ebef687b-aab6-4fe0-a277-01f1b050fffe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973798603 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.973798603
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.463204909
Short name T332
Test name
Test status
Simulation time 366080574 ps
CPU time 0.73 seconds
Started Jul 22 07:11:55 PM PDT 24
Finished Jul 22 07:12:23 PM PDT 24
Peak memory 193368 kb
Host smart-90a25fd2-8267-4e5a-95b7-b4f1dab18141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463204909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.463204909
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.998164596
Short name T404
Test name
Test status
Simulation time 472894974 ps
CPU time 0.74 seconds
Started Jul 22 07:11:57 PM PDT 24
Finished Jul 22 07:12:25 PM PDT 24
Peak memory 193532 kb
Host smart-a2d4816f-5937-4849-8f48-9ae43008b7a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998164596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.998164596
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1045489885
Short name T312
Test name
Test status
Simulation time 265956588 ps
CPU time 0.91 seconds
Started Jul 22 07:12:00 PM PDT 24
Finished Jul 22 07:12:34 PM PDT 24
Peak memory 184076 kb
Host smart-8c4865e5-5196-4642-821f-23fd7afe12c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045489885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1045489885
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2021029093
Short name T341
Test name
Test status
Simulation time 419566191 ps
CPU time 0.74 seconds
Started Jul 22 07:11:56 PM PDT 24
Finished Jul 22 07:12:25 PM PDT 24
Peak memory 184148 kb
Host smart-1bf32034-cb49-4bb6-9899-497bfb3c45f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021029093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2021029093
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1173589746
Short name T384
Test name
Test status
Simulation time 2277514546 ps
CPU time 2.71 seconds
Started Jul 22 07:12:03 PM PDT 24
Finished Jul 22 07:12:41 PM PDT 24
Peak memory 194380 kb
Host smart-045eb1a5-4ed9-43aa-b3b8-c528f937ade4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173589746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1173589746
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2082238114
Short name T353
Test name
Test status
Simulation time 513290388 ps
CPU time 2.39 seconds
Started Jul 22 07:11:54 PM PDT 24
Finished Jul 22 07:12:23 PM PDT 24
Peak memory 199048 kb
Host smart-3a08fe41-47b0-4a48-9e07-6aa160dedf3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082238114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2082238114
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1024961007
Short name T419
Test name
Test status
Simulation time 7412043521 ps
CPU time 11.72 seconds
Started Jul 22 07:11:55 PM PDT 24
Finished Jul 22 07:12:33 PM PDT 24
Peak memory 198788 kb
Host smart-7e4725e3-6258-49de-9d8b-a9a0db19484a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024961007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1024961007
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2545492859
Short name T296
Test name
Test status
Simulation time 312789247 ps
CPU time 0.76 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:58 PM PDT 24
Peak memory 184148 kb
Host smart-f43fb0bd-8650-4581-83c8-8e7d0e521797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545492859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2545492859
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2284568224
Short name T339
Test name
Test status
Simulation time 330223807 ps
CPU time 0.6 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:12:59 PM PDT 24
Peak memory 184140 kb
Host smart-79ee221b-c062-4dde-930c-57676bf4b70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284568224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2284568224
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2462721131
Short name T290
Test name
Test status
Simulation time 350055663 ps
CPU time 1.08 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:00 PM PDT 24
Peak memory 184216 kb
Host smart-a8b14155-6dea-4c39-ad5a-ce3f2095b3fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462721131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2462721131
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2154493831
Short name T355
Test name
Test status
Simulation time 344782721 ps
CPU time 0.66 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:57 PM PDT 24
Peak memory 184216 kb
Host smart-162c664b-7d6a-484e-a4e0-f2a8c8d7740b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154493831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2154493831
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2579040353
Short name T408
Test name
Test status
Simulation time 451727337 ps
CPU time 0.67 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:00 PM PDT 24
Peak memory 184228 kb
Host smart-c7c7a6bf-3c91-455e-95b3-1c6772761a73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579040353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2579040353
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2183112985
Short name T414
Test name
Test status
Simulation time 347354224 ps
CPU time 1.04 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:01 PM PDT 24
Peak memory 184228 kb
Host smart-5f91f682-a790-4a9f-9bb7-9e679df6dd34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183112985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2183112985
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2744094830
Short name T352
Test name
Test status
Simulation time 310335559 ps
CPU time 0.95 seconds
Started Jul 22 07:12:15 PM PDT 24
Finished Jul 22 07:12:58 PM PDT 24
Peak memory 184200 kb
Host smart-7ac46205-ecc3-4a5b-a049-a38040f22e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744094830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2744094830
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2189626523
Short name T336
Test name
Test status
Simulation time 316176624 ps
CPU time 0.75 seconds
Started Jul 22 07:12:13 PM PDT 24
Finished Jul 22 07:12:52 PM PDT 24
Peak memory 193436 kb
Host smart-cdb3e5e4-cb6d-4249-8d14-ef665daccdf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189626523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2189626523
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1245902644
Short name T359
Test name
Test status
Simulation time 509170089 ps
CPU time 0.81 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:12:59 PM PDT 24
Peak memory 184212 kb
Host smart-504787da-2898-4a9c-9853-4c8422fd5a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245902644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1245902644
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4038679033
Short name T360
Test name
Test status
Simulation time 479909964 ps
CPU time 0.62 seconds
Started Jul 22 07:12:14 PM PDT 24
Finished Jul 22 07:12:54 PM PDT 24
Peak memory 184340 kb
Host smart-cc4a9caf-1970-45df-b301-6dc850209a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038679033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4038679033
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1531229019
Short name T56
Test name
Test status
Simulation time 522265227 ps
CPU time 1.39 seconds
Started Jul 22 07:11:54 PM PDT 24
Finished Jul 22 07:12:22 PM PDT 24
Peak memory 192412 kb
Host smart-434cf911-2864-4de0-8d18-9e18daacb15a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531229019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1531229019
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1556800043
Short name T51
Test name
Test status
Simulation time 13754428565 ps
CPU time 18.48 seconds
Started Jul 22 07:11:58 PM PDT 24
Finished Jul 22 07:12:47 PM PDT 24
Peak memory 184564 kb
Host smart-27b84573-62b5-4c13-a140-dfdb6efd4c80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556800043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1556800043
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2487173060
Short name T326
Test name
Test status
Simulation time 1110814770 ps
CPU time 0.88 seconds
Started Jul 22 07:11:58 PM PDT 24
Finished Jul 22 07:12:28 PM PDT 24
Peak memory 184152 kb
Host smart-0c6619f9-35ca-4b07-bd8e-5aa7729722b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487173060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2487173060
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.4208853420
Short name T373
Test name
Test status
Simulation time 569058087 ps
CPU time 1.56 seconds
Started Jul 22 07:12:00 PM PDT 24
Finished Jul 22 07:12:34 PM PDT 24
Peak memory 196408 kb
Host smart-32ccac23-3202-4a17-a482-7bbba9242659
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208853420 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.4208853420
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2372667226
Short name T53
Test name
Test status
Simulation time 502147349 ps
CPU time 0.76 seconds
Started Jul 22 07:11:58 PM PDT 24
Finished Jul 22 07:12:26 PM PDT 24
Peak memory 193596 kb
Host smart-48275017-cb10-4d13-a708-3f7490651165
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372667226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2372667226
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.913685324
Short name T303
Test name
Test status
Simulation time 523394500 ps
CPU time 0.69 seconds
Started Jul 22 07:11:58 PM PDT 24
Finished Jul 22 07:12:29 PM PDT 24
Peak memory 193476 kb
Host smart-c2fa28b4-5bc5-4015-9646-f5347fe8d597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913685324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.913685324
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3026165700
Short name T317
Test name
Test status
Simulation time 501793972 ps
CPU time 1.23 seconds
Started Jul 22 07:13:06 PM PDT 24
Finished Jul 22 07:13:55 PM PDT 24
Peak memory 184132 kb
Host smart-dd7bd759-1a0d-4e91-94bc-38c7e9c5268c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026165700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3026165700
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4190076609
Short name T417
Test name
Test status
Simulation time 299919930 ps
CPU time 0.91 seconds
Started Jul 22 07:11:59 PM PDT 24
Finished Jul 22 07:12:30 PM PDT 24
Peak memory 184168 kb
Host smart-cff3724a-b994-4028-b9a8-e77836cda86b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190076609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.4190076609
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2738966522
Short name T338
Test name
Test status
Simulation time 1425584468 ps
CPU time 3.78 seconds
Started Jul 22 07:11:56 PM PDT 24
Finished Jul 22 07:12:28 PM PDT 24
Peak memory 193480 kb
Host smart-308e533c-cb6e-48c4-8484-2db1de1011d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738966522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2738966522
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1028228182
Short name T395
Test name
Test status
Simulation time 534730100 ps
CPU time 2.44 seconds
Started Jul 22 07:11:57 PM PDT 24
Finished Jul 22 07:12:27 PM PDT 24
Peak memory 199068 kb
Host smart-105e9140-2f48-4a9d-b5a0-329b6a8a0ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028228182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1028228182
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2386836368
Short name T25
Test name
Test status
Simulation time 8502395942 ps
CPU time 11.62 seconds
Started Jul 22 07:12:03 PM PDT 24
Finished Jul 22 07:12:50 PM PDT 24
Peak memory 198600 kb
Host smart-92a8b493-3607-4e2d-bc3f-f798b30a0ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386836368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2386836368
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1971633308
Short name T354
Test name
Test status
Simulation time 272108561 ps
CPU time 0.83 seconds
Started Jul 22 07:12:55 PM PDT 24
Finished Jul 22 07:13:43 PM PDT 24
Peak memory 184196 kb
Host smart-6de0216c-79aa-4faa-a8d1-260f0339fe74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971633308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1971633308
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3885340149
Short name T396
Test name
Test status
Simulation time 373493033 ps
CPU time 0.59 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:12:58 PM PDT 24
Peak memory 193408 kb
Host smart-44802f5c-3798-4d2a-8f4e-31c68f4cbca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885340149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3885340149
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2195290360
Short name T365
Test name
Test status
Simulation time 320063533 ps
CPU time 0.63 seconds
Started Jul 22 07:12:17 PM PDT 24
Finished Jul 22 07:13:00 PM PDT 24
Peak memory 184216 kb
Host smart-4cfa125b-4e61-4e8c-9f6f-4e46428dc289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195290360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2195290360
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1434335172
Short name T388
Test name
Test status
Simulation time 303046290 ps
CPU time 0.95 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:13 PM PDT 24
Peak memory 184232 kb
Host smart-e66d75ab-7f0b-41a4-bf28-72a96823cadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434335172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1434335172
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3988207311
Short name T309
Test name
Test status
Simulation time 321260434 ps
CPU time 0.64 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:12 PM PDT 24
Peak memory 184212 kb
Host smart-c89449c8-4538-4ebb-aaaf-8da0d24af4cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988207311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3988207311
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2944113477
Short name T325
Test name
Test status
Simulation time 505265215 ps
CPU time 1.09 seconds
Started Jul 22 07:12:31 PM PDT 24
Finished Jul 22 07:13:17 PM PDT 24
Peak memory 193448 kb
Host smart-dd33ce88-408a-40ef-b94b-8a7081be6afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944113477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2944113477
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2267163300
Short name T346
Test name
Test status
Simulation time 444632656 ps
CPU time 0.8 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:14 PM PDT 24
Peak memory 193484 kb
Host smart-7140ded5-addd-4183-b95a-3cf79ccb3585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267163300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2267163300
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3876387156
Short name T361
Test name
Test status
Simulation time 418334440 ps
CPU time 0.87 seconds
Started Jul 22 07:12:29 PM PDT 24
Finished Jul 22 07:13:15 PM PDT 24
Peak memory 184296 kb
Host smart-1db6960f-bedc-453b-bb0b-bdcda21ab2a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876387156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3876387156
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3104638604
Short name T420
Test name
Test status
Simulation time 281842368 ps
CPU time 0.9 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:14 PM PDT 24
Peak memory 184284 kb
Host smart-71f8e701-5485-4228-9f59-68eaee59241c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104638604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3104638604
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1882655510
Short name T421
Test name
Test status
Simulation time 383684620 ps
CPU time 0.81 seconds
Started Jul 22 07:12:28 PM PDT 24
Finished Jul 22 07:13:14 PM PDT 24
Peak memory 184208 kb
Host smart-9b1f0776-9d74-4c7b-9a30-f5b5127967f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882655510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1882655510
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3834130509
Short name T409
Test name
Test status
Simulation time 530394525 ps
CPU time 1.43 seconds
Started Jul 22 07:11:56 PM PDT 24
Finished Jul 22 07:12:26 PM PDT 24
Peak memory 196904 kb
Host smart-80abb312-3f8c-4547-b8d6-b90bffbf7ed5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834130509 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3834130509
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3435838734
Short name T415
Test name
Test status
Simulation time 508243211 ps
CPU time 1.2 seconds
Started Jul 22 07:11:57 PM PDT 24
Finished Jul 22 07:12:27 PM PDT 24
Peak memory 192488 kb
Host smart-3f4482ff-b308-400b-9ed8-d0720717fcf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435838734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3435838734
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1343948565
Short name T368
Test name
Test status
Simulation time 460741380 ps
CPU time 0.68 seconds
Started Jul 22 07:11:56 PM PDT 24
Finished Jul 22 07:12:25 PM PDT 24
Peak memory 184216 kb
Host smart-e523b662-0dcc-404e-9d90-8402e7d4b882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343948565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1343948565
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3572255926
Short name T315
Test name
Test status
Simulation time 1326037605 ps
CPU time 2.77 seconds
Started Jul 22 07:11:56 PM PDT 24
Finished Jul 22 07:12:26 PM PDT 24
Peak memory 194084 kb
Host smart-7306c2cd-5796-4aca-89e0-c3aafa2a0ba6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572255926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3572255926
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2362986574
Short name T423
Test name
Test status
Simulation time 498301080 ps
CPU time 1.74 seconds
Started Jul 22 07:12:02 PM PDT 24
Finished Jul 22 07:12:39 PM PDT 24
Peak memory 199032 kb
Host smart-9b7ae6b4-c818-4162-92ef-6a43dca87c02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362986574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2362986574
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1849278548
Short name T418
Test name
Test status
Simulation time 4664833017 ps
CPU time 2.15 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:37 PM PDT 24
Peak memory 198160 kb
Host smart-2415aa7b-3f46-402e-9e6a-e578209deaeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849278548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1849278548
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3905352080
Short name T349
Test name
Test status
Simulation time 528653612 ps
CPU time 1.27 seconds
Started Jul 22 07:12:02 PM PDT 24
Finished Jul 22 07:12:38 PM PDT 24
Peak memory 196548 kb
Host smart-8d3f1686-654b-448b-af7c-d60e886e3c1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905352080 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3905352080
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2184131886
Short name T60
Test name
Test status
Simulation time 327007589 ps
CPU time 1.03 seconds
Started Jul 22 07:11:56 PM PDT 24
Finished Jul 22 07:12:25 PM PDT 24
Peak memory 193632 kb
Host smart-196ec07a-92d7-451f-9a33-a48e3dd89453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184131886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2184131886
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1097173548
Short name T329
Test name
Test status
Simulation time 468967027 ps
CPU time 0.67 seconds
Started Jul 22 07:11:55 PM PDT 24
Finished Jul 22 07:12:23 PM PDT 24
Peak memory 184292 kb
Host smart-0edbbb57-16ef-4c4d-86c5-2eeab4df99a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097173548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1097173548
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1095275209
Short name T68
Test name
Test status
Simulation time 1307243908 ps
CPU time 2.57 seconds
Started Jul 22 07:13:06 PM PDT 24
Finished Jul 22 07:13:57 PM PDT 24
Peak memory 194044 kb
Host smart-35d6eafc-a492-4022-9dec-fb905b136c04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095275209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1095275209
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3583163347
Short name T390
Test name
Test status
Simulation time 566730379 ps
CPU time 2.56 seconds
Started Jul 22 07:11:55 PM PDT 24
Finished Jul 22 07:12:25 PM PDT 24
Peak memory 199088 kb
Host smart-004cfa2a-90df-4d0c-aa88-5cd73e62e80a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583163347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3583163347
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3995151564
Short name T337
Test name
Test status
Simulation time 8412257794 ps
CPU time 14.3 seconds
Started Jul 22 07:11:59 PM PDT 24
Finished Jul 22 07:12:44 PM PDT 24
Peak memory 198860 kb
Host smart-6a24028e-37fa-485a-ba96-b62b22579eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995151564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3995151564
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1657164867
Short name T204
Test name
Test status
Simulation time 561381539 ps
CPU time 0.9 seconds
Started Jul 22 07:13:06 PM PDT 24
Finished Jul 22 07:13:55 PM PDT 24
Peak memory 197680 kb
Host smart-5660595f-d71d-45d1-a657-daded966bdfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657164867 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1657164867
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1740670721
Short name T424
Test name
Test status
Simulation time 407554846 ps
CPU time 0.68 seconds
Started Jul 22 07:13:06 PM PDT 24
Finished Jul 22 07:13:55 PM PDT 24
Peak memory 193420 kb
Host smart-663f5f10-96f5-4189-9ef0-52a282e55b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740670721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1740670721
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1063799108
Short name T295
Test name
Test status
Simulation time 448479530 ps
CPU time 1.09 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:36 PM PDT 24
Peak memory 184020 kb
Host smart-0143e6dc-172a-40ab-bcf0-630e6d694296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063799108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1063799108
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.617811043
Short name T323
Test name
Test status
Simulation time 2285525821 ps
CPU time 0.85 seconds
Started Jul 22 07:11:58 PM PDT 24
Finished Jul 22 07:12:28 PM PDT 24
Peak memory 194232 kb
Host smart-1c39ff20-7c76-4d71-b77c-bdff86644d0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617811043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.617811043
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.247345250
Short name T381
Test name
Test status
Simulation time 489638166 ps
CPU time 0.97 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:35 PM PDT 24
Peak memory 197764 kb
Host smart-a73e9545-1c9b-4f41-86a8-572d50f7e528
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247345250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.247345250
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1894982170
Short name T196
Test name
Test status
Simulation time 8431986694 ps
CPU time 3.93 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:40 PM PDT 24
Peak memory 198588 kb
Host smart-4c3324a4-0325-41f7-9080-1d9ea7564891
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894982170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1894982170
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2186231560
Short name T318
Test name
Test status
Simulation time 401245800 ps
CPU time 1.28 seconds
Started Jul 22 07:12:02 PM PDT 24
Finished Jul 22 07:12:38 PM PDT 24
Peak memory 196452 kb
Host smart-2c1c1407-a48c-44e6-bbcb-7f921b87965d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186231560 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2186231560
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3716307184
Short name T402
Test name
Test status
Simulation time 382359283 ps
CPU time 0.84 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:35 PM PDT 24
Peak memory 194468 kb
Host smart-fc97450f-8ece-4daa-8560-d9f4c645ce52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716307184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3716307184
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1121933017
Short name T386
Test name
Test status
Simulation time 450103265 ps
CPU time 0.94 seconds
Started Jul 22 07:12:03 PM PDT 24
Finished Jul 22 07:12:40 PM PDT 24
Peak memory 184200 kb
Host smart-2c9c1b6f-f25a-4a8d-a0ac-5760dcca6302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121933017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1121933017
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3325775491
Short name T73
Test name
Test status
Simulation time 1364446870 ps
CPU time 1.06 seconds
Started Jul 22 07:11:59 PM PDT 24
Finished Jul 22 07:12:31 PM PDT 24
Peak memory 184244 kb
Host smart-c91ffe36-8b39-4dec-a9ca-d83a260ca323
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325775491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3325775491
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2794497478
Short name T292
Test name
Test status
Simulation time 439943200 ps
CPU time 1.7 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:36 PM PDT 24
Peak memory 199044 kb
Host smart-cc9fc4a2-5960-41e2-9589-44acff353aa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794497478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2794497478
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1038285499
Short name T311
Test name
Test status
Simulation time 4761779368 ps
CPU time 6.99 seconds
Started Jul 22 07:12:00 PM PDT 24
Finished Jul 22 07:12:39 PM PDT 24
Peak memory 198372 kb
Host smart-9fa36260-41bd-46b0-9ec6-e7a1e7132719
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038285499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1038285499
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.163327516
Short name T403
Test name
Test status
Simulation time 437269337 ps
CPU time 0.8 seconds
Started Jul 22 07:12:10 PM PDT 24
Finished Jul 22 07:12:49 PM PDT 24
Peak memory 197520 kb
Host smart-eb23c0d1-1975-42e1-9fb8-2c1a03b8e708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163327516 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.163327516
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3560288686
Short name T308
Test name
Test status
Simulation time 433338668 ps
CPU time 0.84 seconds
Started Jul 22 07:12:04 PM PDT 24
Finished Jul 22 07:12:41 PM PDT 24
Peak memory 194432 kb
Host smart-e7db5d52-e61d-4f8a-ac25-33d499ffb3e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560288686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3560288686
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3221400676
Short name T413
Test name
Test status
Simulation time 493500857 ps
CPU time 1.28 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:12:59 PM PDT 24
Peak memory 184232 kb
Host smart-a026cbcc-60c3-40c4-bc87-90f65602fc9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221400676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3221400676
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.493090557
Short name T74
Test name
Test status
Simulation time 1340414530 ps
CPU time 0.89 seconds
Started Jul 22 07:12:01 PM PDT 24
Finished Jul 22 07:12:37 PM PDT 24
Peak memory 193508 kb
Host smart-45aa529a-c7eb-4219-b08a-ab45b09962b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493090557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.493090557
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.796910044
Short name T289
Test name
Test status
Simulation time 581389484 ps
CPU time 1.6 seconds
Started Jul 22 07:14:14 PM PDT 24
Finished Jul 22 07:14:59 PM PDT 24
Peak memory 199072 kb
Host smart-fb5bf104-8fa7-4c0a-8449-08b2cf6396bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796910044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.796910044
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.584562580
Short name T199
Test name
Test status
Simulation time 4285898123 ps
CPU time 7.29 seconds
Started Jul 22 07:12:16 PM PDT 24
Finished Jul 22 07:13:05 PM PDT 24
Peak memory 198592 kb
Host smart-f2b97448-be02-485d-aa0d-8f000d690a65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584562580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.584562580
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.385772971
Short name T42
Test name
Test status
Simulation time 51337329291 ps
CPU time 21.17 seconds
Started Jul 22 05:16:57 PM PDT 24
Finished Jul 22 05:17:19 PM PDT 24
Peak memory 191848 kb
Host smart-0ce7f8c9-7dda-4dd2-a8c3-fe8fa83fd12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385772971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.385772971
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.318794104
Short name T34
Test name
Test status
Simulation time 587824843 ps
CPU time 0.76 seconds
Started Jul 22 05:16:42 PM PDT 24
Finished Jul 22 05:16:43 PM PDT 24
Peak memory 191640 kb
Host smart-e7dacf8f-4d4a-424a-ac8c-cbefd60c8a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318794104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.318794104
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1461160227
Short name T282
Test name
Test status
Simulation time 26109903735 ps
CPU time 5.58 seconds
Started Jul 22 05:16:40 PM PDT 24
Finished Jul 22 05:16:47 PM PDT 24
Peak memory 191796 kb
Host smart-c6aae71e-0ded-4589-a9dc-71dad390b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461160227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1461160227
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1907184374
Short name T4
Test name
Test status
Simulation time 4026406891 ps
CPU time 2.14 seconds
Started Jul 22 05:17:48 PM PDT 24
Finished Jul 22 05:17:51 PM PDT 24
Peak memory 215300 kb
Host smart-be3d5b2c-29e6-4481-8afd-3fbf7d0c13ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907184374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1907184374
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1009145281
Short name T215
Test name
Test status
Simulation time 480302942 ps
CPU time 0.73 seconds
Started Jul 22 05:16:39 PM PDT 24
Finished Jul 22 05:16:40 PM PDT 24
Peak memory 191704 kb
Host smart-495fe315-496e-4608-a0f7-9355ed44241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009145281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1009145281
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3044051414
Short name T44
Test name
Test status
Simulation time 44599281715 ps
CPU time 17.25 seconds
Started Jul 22 05:17:14 PM PDT 24
Finished Jul 22 05:17:32 PM PDT 24
Peak memory 191712 kb
Host smart-5585cb12-bd5b-47d9-9695-2307893ed408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044051414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3044051414
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.251337866
Short name T262
Test name
Test status
Simulation time 562749003 ps
CPU time 0.95 seconds
Started Jul 22 05:17:13 PM PDT 24
Finished Jul 22 05:17:15 PM PDT 24
Peak memory 191632 kb
Host smart-d2a86f45-ed75-4b0c-923d-7d5794a241ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251337866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.251337866
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4211260989
Short name T258
Test name
Test status
Simulation time 8705430251 ps
CPU time 12.04 seconds
Started Jul 22 05:17:11 PM PDT 24
Finished Jul 22 05:17:24 PM PDT 24
Peak memory 191848 kb
Host smart-de68b777-c3de-497d-b210-e7fb3c7dce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211260989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4211260989
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.157656610
Short name T9
Test name
Test status
Simulation time 469169149 ps
CPU time 0.86 seconds
Started Jul 22 05:17:13 PM PDT 24
Finished Jul 22 05:17:14 PM PDT 24
Peak memory 191712 kb
Host smart-60b352e3-0121-493b-a207-e67a883c8e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157656610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.157656610
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1550501321
Short name T212
Test name
Test status
Simulation time 40917103444 ps
CPU time 10.36 seconds
Started Jul 22 05:17:14 PM PDT 24
Finished Jul 22 05:17:25 PM PDT 24
Peak memory 191708 kb
Host smart-e457d7ad-fd7f-4c66-a1bf-63973ab39153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550501321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1550501321
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3629198434
Short name T274
Test name
Test status
Simulation time 362852531 ps
CPU time 0.86 seconds
Started Jul 22 05:17:11 PM PDT 24
Finished Jul 22 05:17:12 PM PDT 24
Peak memory 191676 kb
Host smart-6538ea83-09c0-46c8-a239-999f9dca153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629198434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3629198434
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.396585760
Short name T5
Test name
Test status
Simulation time 52600759333 ps
CPU time 16.22 seconds
Started Jul 22 05:19:07 PM PDT 24
Finished Jul 22 05:19:24 PM PDT 24
Peak memory 196760 kb
Host smart-382594f2-ec33-40d1-888b-b7bf661f1a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396585760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.396585760
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2259599982
Short name T205
Test name
Test status
Simulation time 336193375 ps
CPU time 1.05 seconds
Started Jul 22 05:17:22 PM PDT 24
Finished Jul 22 05:17:23 PM PDT 24
Peak memory 196576 kb
Host smart-9e78d51c-749e-431e-8379-74668c88a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259599982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2259599982
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1106469846
Short name T80
Test name
Test status
Simulation time 38070780585 ps
CPU time 41.71 seconds
Started Jul 22 05:17:26 PM PDT 24
Finished Jul 22 05:18:08 PM PDT 24
Peak memory 191748 kb
Host smart-b74a637e-5bd0-49fd-9dd2-8bcf01817df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106469846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1106469846
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2541571918
Short name T235
Test name
Test status
Simulation time 609969446 ps
CPU time 0.98 seconds
Started Jul 22 05:17:20 PM PDT 24
Finished Jul 22 05:17:22 PM PDT 24
Peak memory 191620 kb
Host smart-534c5172-2f61-4665-816b-4cfe2e4b0c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541571918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2541571918
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3792575905
Short name T264
Test name
Test status
Simulation time 36915950942 ps
CPU time 4.45 seconds
Started Jul 22 05:17:20 PM PDT 24
Finished Jul 22 05:17:25 PM PDT 24
Peak memory 196764 kb
Host smart-832b85d4-f06c-41b6-b26e-3745e8473e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792575905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3792575905
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3609008739
Short name T276
Test name
Test status
Simulation time 569184945 ps
CPU time 1.39 seconds
Started Jul 22 05:17:19 PM PDT 24
Finished Jul 22 05:17:21 PM PDT 24
Peak memory 191700 kb
Host smart-8501baaa-3e80-41ac-b14e-0e49cb29d16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609008739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3609008739
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2693000404
Short name T217
Test name
Test status
Simulation time 36411844896 ps
CPU time 14.44 seconds
Started Jul 22 05:17:24 PM PDT 24
Finished Jul 22 05:17:39 PM PDT 24
Peak memory 191748 kb
Host smart-56495910-c47e-4886-9d76-82ea02b8ce0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693000404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2693000404
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.924389722
Short name T226
Test name
Test status
Simulation time 506014028 ps
CPU time 1.35 seconds
Started Jul 22 05:17:20 PM PDT 24
Finished Jul 22 05:17:22 PM PDT 24
Peak memory 191684 kb
Host smart-d4ccc88c-2aa5-47d6-b829-1ebd5d8f0b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924389722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.924389722
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2879556987
Short name T246
Test name
Test status
Simulation time 23093616289 ps
CPU time 17.9 seconds
Started Jul 22 05:17:30 PM PDT 24
Finished Jul 22 05:17:48 PM PDT 24
Peak memory 196848 kb
Host smart-a973280e-2247-4c47-b0da-c5c0454f9367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879556987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2879556987
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1018659161
Short name T261
Test name
Test status
Simulation time 593283652 ps
CPU time 0.95 seconds
Started Jul 22 05:17:27 PM PDT 24
Finished Jul 22 05:17:28 PM PDT 24
Peak memory 191716 kb
Host smart-4001bfb6-06af-4519-a4c8-45249ba420a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018659161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1018659161
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1607940402
Short name T206
Test name
Test status
Simulation time 53048870150 ps
CPU time 84.34 seconds
Started Jul 22 05:17:30 PM PDT 24
Finished Jul 22 05:18:55 PM PDT 24
Peak memory 191800 kb
Host smart-09d4c212-e87f-4b29-b0a8-9f8b426d916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607940402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1607940402
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2587770878
Short name T216
Test name
Test status
Simulation time 577014023 ps
CPU time 0.93 seconds
Started Jul 22 05:17:32 PM PDT 24
Finished Jul 22 05:17:33 PM PDT 24
Peak memory 191716 kb
Host smart-a90d0748-55d7-4ad7-af8e-3f6f90a0c563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587770878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2587770878
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2908924016
Short name T254
Test name
Test status
Simulation time 18113357915 ps
CPU time 12.56 seconds
Started Jul 22 05:17:30 PM PDT 24
Finished Jul 22 05:17:43 PM PDT 24
Peak memory 191820 kb
Host smart-724f911e-e6b9-4661-8add-74f70dd64f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908924016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2908924016
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2726981801
Short name T248
Test name
Test status
Simulation time 375935071 ps
CPU time 1.07 seconds
Started Jul 22 05:17:29 PM PDT 24
Finished Jul 22 05:17:31 PM PDT 24
Peak memory 191644 kb
Host smart-eb90ff72-3f59-42db-a799-82720af290ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726981801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2726981801
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3765656490
Short name T250
Test name
Test status
Simulation time 6393515480 ps
CPU time 4.85 seconds
Started Jul 22 05:16:41 PM PDT 24
Finished Jul 22 05:16:46 PM PDT 24
Peak memory 191788 kb
Host smart-e73ff551-bbd4-4e8a-8bd2-190cfa57ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765656490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3765656490
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1343658847
Short name T17
Test name
Test status
Simulation time 8023075445 ps
CPU time 3.53 seconds
Started Jul 22 05:16:50 PM PDT 24
Finished Jul 22 05:16:55 PM PDT 24
Peak memory 215772 kb
Host smart-8af3d151-5666-4e4a-b877-3678380aef32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343658847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1343658847
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3168238460
Short name T249
Test name
Test status
Simulation time 401320948 ps
CPU time 0.69 seconds
Started Jul 22 05:16:40 PM PDT 24
Finished Jul 22 05:16:41 PM PDT 24
Peak memory 196508 kb
Host smart-addab62a-7850-44bf-ab99-69c417b12fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168238460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3168238460
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.4190099632
Short name T255
Test name
Test status
Simulation time 27916201945 ps
CPU time 4.16 seconds
Started Jul 22 05:17:40 PM PDT 24
Finished Jul 22 05:17:46 PM PDT 24
Peak memory 191768 kb
Host smart-3cce03ea-c1de-42d3-94e0-891aabc2d023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190099632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4190099632
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.4072972107
Short name T238
Test name
Test status
Simulation time 493139710 ps
CPU time 0.71 seconds
Started Jul 22 05:17:29 PM PDT 24
Finished Jul 22 05:17:30 PM PDT 24
Peak memory 191648 kb
Host smart-638a7abe-a80b-4fdd-aa5e-06ef9595c49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072972107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.4072972107
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.359010699
Short name T284
Test name
Test status
Simulation time 37944375971 ps
CPU time 12.96 seconds
Started Jul 22 05:20:46 PM PDT 24
Finished Jul 22 05:21:00 PM PDT 24
Peak memory 191724 kb
Host smart-ed604249-0ffb-499a-ac4d-97b6f65db77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359010699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.359010699
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.283633100
Short name T233
Test name
Test status
Simulation time 376017185 ps
CPU time 0.92 seconds
Started Jul 22 05:17:41 PM PDT 24
Finished Jul 22 05:17:44 PM PDT 24
Peak memory 191584 kb
Host smart-0ba18efb-a41f-4619-9b9c-57cac7b8436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283633100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.283633100
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2152772623
Short name T267
Test name
Test status
Simulation time 14327712552 ps
CPU time 22.55 seconds
Started Jul 22 05:17:37 PM PDT 24
Finished Jul 22 05:18:00 PM PDT 24
Peak memory 191828 kb
Host smart-a7467076-af97-442b-be05-c07436447bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152772623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2152772623
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3005531103
Short name T220
Test name
Test status
Simulation time 422157419 ps
CPU time 1.15 seconds
Started Jul 22 05:17:40 PM PDT 24
Finished Jul 22 05:17:42 PM PDT 24
Peak memory 191692 kb
Host smart-41b26146-7b19-419d-bfaf-4b8f9d290891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005531103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3005531103
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1150561858
Short name T47
Test name
Test status
Simulation time 22262134333 ps
CPU time 5.47 seconds
Started Jul 22 05:17:41 PM PDT 24
Finished Jul 22 05:17:48 PM PDT 24
Peak memory 196700 kb
Host smart-1e74921c-1ccf-4659-8a2e-43d34c965a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150561858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1150561858
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1762882811
Short name T45
Test name
Test status
Simulation time 599450910 ps
CPU time 1.03 seconds
Started Jul 22 05:20:46 PM PDT 24
Finished Jul 22 05:20:48 PM PDT 24
Peak memory 191692 kb
Host smart-c62acdb8-e3a1-4c9f-90c1-8e1708e083c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762882811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1762882811
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1022419040
Short name T252
Test name
Test status
Simulation time 4858766113 ps
CPU time 1.84 seconds
Started Jul 22 05:17:48 PM PDT 24
Finished Jul 22 05:17:50 PM PDT 24
Peak memory 191784 kb
Host smart-6d9e02ea-21ef-477b-a623-55b51d1037a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022419040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1022419040
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4232446879
Short name T259
Test name
Test status
Simulation time 598288767 ps
CPU time 1.39 seconds
Started Jul 22 05:20:46 PM PDT 24
Finished Jul 22 05:20:48 PM PDT 24
Peak memory 191644 kb
Host smart-6759134b-4c51-49fb-b392-195eab6d40d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232446879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4232446879
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1000049563
Short name T287
Test name
Test status
Simulation time 9717876505 ps
CPU time 4.2 seconds
Started Jul 22 05:20:46 PM PDT 24
Finished Jul 22 05:20:51 PM PDT 24
Peak memory 191844 kb
Host smart-dd6d7a19-248a-42d5-9fb0-a0b1ef74e57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000049563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1000049563
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.485476120
Short name T207
Test name
Test status
Simulation time 463278622 ps
CPU time 1.22 seconds
Started Jul 22 05:17:46 PM PDT 24
Finished Jul 22 05:17:48 PM PDT 24
Peak memory 191716 kb
Host smart-cabe0005-1df1-4440-9e29-3d12f2cc703c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485476120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.485476120
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.4247255921
Short name T81
Test name
Test status
Simulation time 5142555322 ps
CPU time 1.64 seconds
Started Jul 22 05:17:57 PM PDT 24
Finished Jul 22 05:17:59 PM PDT 24
Peak memory 191780 kb
Host smart-81410992-a4e0-420c-bb4d-e1b67b60c05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247255921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.4247255921
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.237786472
Short name T77
Test name
Test status
Simulation time 574060025 ps
CPU time 0.75 seconds
Started Jul 22 05:17:51 PM PDT 24
Finished Jul 22 05:17:53 PM PDT 24
Peak memory 196496 kb
Host smart-2f88f29a-5158-4cd8-81d1-507f6241f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237786472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.237786472
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1065723347
Short name T218
Test name
Test status
Simulation time 36525264399 ps
CPU time 6.18 seconds
Started Jul 22 05:17:54 PM PDT 24
Finished Jul 22 05:18:01 PM PDT 24
Peak memory 191828 kb
Host smart-c3be0a61-d595-4e1f-8cae-3cc5aeaeed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065723347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1065723347
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3641349723
Short name T210
Test name
Test status
Simulation time 476693587 ps
CPU time 0.71 seconds
Started Jul 22 05:17:56 PM PDT 24
Finished Jul 22 05:17:58 PM PDT 24
Peak memory 191648 kb
Host smart-f572abc2-b285-4050-9b0b-b53ec4875558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641349723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3641349723
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3881843523
Short name T271
Test name
Test status
Simulation time 56258286250 ps
CPU time 20.65 seconds
Started Jul 22 05:17:57 PM PDT 24
Finished Jul 22 05:18:19 PM PDT 24
Peak memory 196796 kb
Host smart-0b932731-f79f-4018-8c46-b703432505b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881843523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3881843523
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1451050653
Short name T229
Test name
Test status
Simulation time 526706456 ps
CPU time 0.63 seconds
Started Jul 22 05:17:55 PM PDT 24
Finished Jul 22 05:17:56 PM PDT 24
Peak memory 196572 kb
Host smart-cde9117d-90ca-4579-9d31-976c5693ed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451050653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1451050653
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.630536479
Short name T239
Test name
Test status
Simulation time 1666226201 ps
CPU time 2.88 seconds
Started Jul 22 05:18:12 PM PDT 24
Finished Jul 22 05:18:16 PM PDT 24
Peak memory 191724 kb
Host smart-013eb8c2-ef68-4b42-bc68-9bbc4f0a5c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630536479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.630536479
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3670087346
Short name T273
Test name
Test status
Simulation time 487995376 ps
CPU time 1.24 seconds
Started Jul 22 05:18:12 PM PDT 24
Finished Jul 22 05:18:15 PM PDT 24
Peak memory 191628 kb
Host smart-c960b32e-977a-4fe2-9fbe-54c18ad17f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670087346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3670087346
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2064369499
Short name T228
Test name
Test status
Simulation time 329743221461 ps
CPU time 179.23 seconds
Started Jul 22 05:18:11 PM PDT 24
Finished Jul 22 05:21:11 PM PDT 24
Peak memory 192536 kb
Host smart-e858e7d2-048b-4681-b335-590bb1a8ac50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064369499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2064369499
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1887584359
Short name T280
Test name
Test status
Simulation time 50017708302 ps
CPU time 28.51 seconds
Started Jul 22 05:16:52 PM PDT 24
Finished Jul 22 05:17:20 PM PDT 24
Peak memory 191832 kb
Host smart-8347abed-f506-4b2f-82c3-30c0453b2aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887584359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1887584359
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2676206011
Short name T14
Test name
Test status
Simulation time 4024955287 ps
CPU time 2.87 seconds
Started Jul 22 05:16:51 PM PDT 24
Finished Jul 22 05:16:54 PM PDT 24
Peak memory 215388 kb
Host smart-44c211e4-6d33-4e06-9185-fdf886bd9b09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676206011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2676206011
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1148719809
Short name T242
Test name
Test status
Simulation time 506661269 ps
CPU time 1.26 seconds
Started Jul 22 05:16:50 PM PDT 24
Finished Jul 22 05:16:51 PM PDT 24
Peak memory 191608 kb
Host smart-eb159703-5d39-40a5-9f0c-bc9c6df5e4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148719809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1148719809
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2524562251
Short name T167
Test name
Test status
Simulation time 622122330 ps
CPU time 0.98 seconds
Started Jul 22 05:18:05 PM PDT 24
Finished Jul 22 05:18:07 PM PDT 24
Peak memory 196472 kb
Host smart-697a303c-7708-4534-b49b-c7eb9c7820c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524562251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2524562251
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1194327583
Short name T223
Test name
Test status
Simulation time 9820092731 ps
CPU time 4.29 seconds
Started Jul 22 05:18:39 PM PDT 24
Finished Jul 22 05:18:44 PM PDT 24
Peak memory 191812 kb
Host smart-d9a103a0-c5db-4f7d-bd7a-cecccc504909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194327583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1194327583
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3658278036
Short name T257
Test name
Test status
Simulation time 433204571 ps
CPU time 0.74 seconds
Started Jul 22 05:18:14 PM PDT 24
Finished Jul 22 05:18:16 PM PDT 24
Peak memory 191712 kb
Host smart-1cef7055-1ff3-49b7-b480-045d1c14d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658278036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3658278036
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2373475665
Short name T227
Test name
Test status
Simulation time 32097151359 ps
CPU time 20.35 seconds
Started Jul 22 05:18:11 PM PDT 24
Finished Jul 22 05:18:33 PM PDT 24
Peak memory 196804 kb
Host smart-e07ef232-481a-4917-a9c8-0890077de65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373475665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2373475665
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3942994013
Short name T247
Test name
Test status
Simulation time 497093104 ps
CPU time 1.3 seconds
Started Jul 22 05:18:07 PM PDT 24
Finished Jul 22 05:18:09 PM PDT 24
Peak memory 191592 kb
Host smart-2dd02ecb-cb3f-4253-9966-c9a29afb15c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942994013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3942994013
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3322789702
Short name T182
Test name
Test status
Simulation time 389877790 ps
CPU time 1.24 seconds
Started Jul 22 05:18:06 PM PDT 24
Finished Jul 22 05:18:07 PM PDT 24
Peak memory 196544 kb
Host smart-8e2f9986-b592-41da-8be4-f6663b753f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322789702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3322789702
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.21128380
Short name T266
Test name
Test status
Simulation time 32239890944 ps
CPU time 3 seconds
Started Jul 22 05:18:11 PM PDT 24
Finished Jul 22 05:18:15 PM PDT 24
Peak memory 196772 kb
Host smart-dd3705f9-fe16-4af8-89e9-599a0188ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21128380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.21128380
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3009844097
Short name T277
Test name
Test status
Simulation time 517685516 ps
CPU time 1.21 seconds
Started Jul 22 05:18:11 PM PDT 24
Finished Jul 22 05:18:13 PM PDT 24
Peak memory 191744 kb
Host smart-ced03d3b-1982-433b-a9f2-08b5bb862377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009844097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3009844097
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3174953466
Short name T283
Test name
Test status
Simulation time 32730986889 ps
CPU time 12.74 seconds
Started Jul 22 05:18:17 PM PDT 24
Finished Jul 22 05:18:30 PM PDT 24
Peak memory 191872 kb
Host smart-a2cda68c-d8f3-443c-ad82-5f8f8c16aa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174953466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3174953466
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.989400672
Short name T243
Test name
Test status
Simulation time 525377163 ps
CPU time 0.74 seconds
Started Jul 22 05:18:18 PM PDT 24
Finished Jul 22 05:18:19 PM PDT 24
Peak memory 196476 kb
Host smart-3ef23c5f-4d34-4951-a619-58375c929114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989400672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.989400672
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.140756667
Short name T36
Test name
Test status
Simulation time 59407840813 ps
CPU time 24.47 seconds
Started Jul 22 05:18:16 PM PDT 24
Finished Jul 22 05:18:41 PM PDT 24
Peak memory 191848 kb
Host smart-46cdf917-560c-49d0-bc11-d875eb8433fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140756667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.140756667
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.122888819
Short name T219
Test name
Test status
Simulation time 391715358 ps
CPU time 0.85 seconds
Started Jul 22 05:18:15 PM PDT 24
Finished Jul 22 05:18:17 PM PDT 24
Peak memory 196512 kb
Host smart-70978b3d-85ac-42f4-873d-fe4a03242062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122888819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.122888819
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1520727323
Short name T234
Test name
Test status
Simulation time 34192945580 ps
CPU time 44.37 seconds
Started Jul 22 05:18:14 PM PDT 24
Finished Jul 22 05:19:00 PM PDT 24
Peak memory 191748 kb
Host smart-d55a0b54-d013-4707-a3a8-32717339300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520727323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1520727323
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.4179822953
Short name T214
Test name
Test status
Simulation time 434006695 ps
CPU time 1.27 seconds
Started Jul 22 05:18:15 PM PDT 24
Finished Jul 22 05:18:18 PM PDT 24
Peak memory 196544 kb
Host smart-2ab50ce6-2fcd-433c-a05d-6b7dd325aabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179822953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.4179822953
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2348090003
Short name T91
Test name
Test status
Simulation time 17290285799 ps
CPU time 121.43 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:20:27 PM PDT 24
Peak memory 198508 kb
Host smart-e4f3eb2e-48bf-4fdc-8de3-ea936071c21b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348090003 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2348090003
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2640680970
Short name T237
Test name
Test status
Simulation time 16836094671 ps
CPU time 23.15 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:18:49 PM PDT 24
Peak memory 196844 kb
Host smart-87f845c0-3e22-4908-b235-dbad0dba9dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640680970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2640680970
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1637527620
Short name T46
Test name
Test status
Simulation time 543158914 ps
CPU time 0.76 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:18:27 PM PDT 24
Peak memory 191692 kb
Host smart-bd68ff09-385d-4056-9959-c47a055838ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637527620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1637527620
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1442779697
Short name T208
Test name
Test status
Simulation time 29267348106 ps
CPU time 41.32 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:19:07 PM PDT 24
Peak memory 196784 kb
Host smart-625dd004-d3dc-40a0-9c99-6a4e5e18406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442779697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1442779697
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3750480429
Short name T260
Test name
Test status
Simulation time 558367981 ps
CPU time 0.99 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:18:27 PM PDT 24
Peak memory 191732 kb
Host smart-d6c5bef0-6cbb-46a8-ac07-a56b5fe4c8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750480429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3750480429
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2305636675
Short name T288
Test name
Test status
Simulation time 8246282193 ps
CPU time 11.63 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:18:38 PM PDT 24
Peak memory 191708 kb
Host smart-4a867dc4-30be-4c37-ae94-13ce5b2191dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305636675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2305636675
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4019681544
Short name T240
Test name
Test status
Simulation time 559113266 ps
CPU time 1.4 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:18:27 PM PDT 24
Peak memory 191680 kb
Host smart-3c2ecae5-d8d4-45d6-b56d-4d22dac4d4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019681544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4019681544
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1289512924
Short name T222
Test name
Test status
Simulation time 3545900428 ps
CPU time 2.19 seconds
Started Jul 22 05:19:07 PM PDT 24
Finished Jul 22 05:19:09 PM PDT 24
Peak memory 191784 kb
Host smart-54b176ff-f583-4913-b6bf-bad7270f1448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289512924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1289512924
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1680676173
Short name T285
Test name
Test status
Simulation time 456287708 ps
CPU time 0.66 seconds
Started Jul 22 05:18:25 PM PDT 24
Finished Jul 22 05:18:26 PM PDT 24
Peak memory 191648 kb
Host smart-1549598a-f122-4bc1-bb2b-9749fdee8c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680676173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1680676173
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1056644308
Short name T209
Test name
Test status
Simulation time 39454095185 ps
CPU time 14.69 seconds
Started Jul 22 05:17:10 PM PDT 24
Finished Jul 22 05:17:25 PM PDT 24
Peak memory 191832 kb
Host smart-26b1f8e6-27b4-420a-a50c-a0753bc5e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056644308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1056644308
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2796886803
Short name T15
Test name
Test status
Simulation time 4151676059 ps
CPU time 5.94 seconds
Started Jul 22 05:16:49 PM PDT 24
Finished Jul 22 05:16:56 PM PDT 24
Peak memory 215496 kb
Host smart-2b0ce30a-e8d4-4b65-aa73-d3242648015c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796886803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2796886803
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1610904155
Short name T244
Test name
Test status
Simulation time 378011091 ps
CPU time 0.85 seconds
Started Jul 22 05:16:49 PM PDT 24
Finished Jul 22 05:16:50 PM PDT 24
Peak memory 191708 kb
Host smart-e114adde-f46a-4450-9db8-2ee8fbd3a995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610904155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1610904155
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3398334878
Short name T263
Test name
Test status
Simulation time 5330220197 ps
CPU time 7.94 seconds
Started Jul 22 05:19:01 PM PDT 24
Finished Jul 22 05:19:09 PM PDT 24
Peak memory 191808 kb
Host smart-c87da9f2-eaac-4a01-9919-1394afaf13bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398334878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3398334878
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1787476168
Short name T275
Test name
Test status
Simulation time 524393573 ps
CPU time 1.24 seconds
Started Jul 22 05:18:32 PM PDT 24
Finished Jul 22 05:18:33 PM PDT 24
Peak memory 191652 kb
Host smart-ee5eb130-0e90-403b-99fd-410ff66286c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787476168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1787476168
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1259357652
Short name T241
Test name
Test status
Simulation time 23543783166 ps
CPU time 3.73 seconds
Started Jul 22 05:18:40 PM PDT 24
Finished Jul 22 05:18:44 PM PDT 24
Peak memory 191840 kb
Host smart-dde5c58a-de81-4a2a-8b06-d2abc3557976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259357652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1259357652
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2431878750
Short name T269
Test name
Test status
Simulation time 513928299 ps
CPU time 1.3 seconds
Started Jul 22 05:18:43 PM PDT 24
Finished Jul 22 05:18:45 PM PDT 24
Peak memory 191688 kb
Host smart-49e929d0-58ae-4823-b825-47bc348f8468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431878750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2431878750
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.689138071
Short name T253
Test name
Test status
Simulation time 5662425927 ps
CPU time 1.33 seconds
Started Jul 22 05:18:42 PM PDT 24
Finished Jul 22 05:18:44 PM PDT 24
Peak memory 191840 kb
Host smart-ecabb61b-1866-45e0-bbdb-ea6646a14377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689138071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.689138071
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3942923519
Short name T270
Test name
Test status
Simulation time 508107517 ps
CPU time 1.23 seconds
Started Jul 22 05:18:39 PM PDT 24
Finished Jul 22 05:18:41 PM PDT 24
Peak memory 191716 kb
Host smart-b3f70610-42e8-43f0-ac41-f1bf235f1219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942923519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3942923519
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1926525857
Short name T195
Test name
Test status
Simulation time 560577227 ps
CPU time 0.76 seconds
Started Jul 22 05:19:14 PM PDT 24
Finished Jul 22 05:19:15 PM PDT 24
Peak memory 196436 kb
Host smart-acad0951-1b8d-4724-8f8b-115319029292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926525857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1926525857
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.410395470
Short name T221
Test name
Test status
Simulation time 2129996542 ps
CPU time 0.78 seconds
Started Jul 22 05:18:40 PM PDT 24
Finished Jul 22 05:18:41 PM PDT 24
Peak memory 191704 kb
Host smart-d0990ca5-64a8-4525-8908-20ca8903aaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410395470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.410395470
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1066849941
Short name T279
Test name
Test status
Simulation time 424907008 ps
CPU time 1.21 seconds
Started Jul 22 05:18:40 PM PDT 24
Finished Jul 22 05:18:41 PM PDT 24
Peak memory 191720 kb
Host smart-e068b72a-f08b-4b97-94f5-8c4fc18c2c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066849941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1066849941
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3728605095
Short name T194
Test name
Test status
Simulation time 440757118 ps
CPU time 0.75 seconds
Started Jul 22 05:18:48 PM PDT 24
Finished Jul 22 05:18:49 PM PDT 24
Peak memory 196496 kb
Host smart-5f29828c-0f1b-4ff6-9c07-560d08772982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728605095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3728605095
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2364224682
Short name T213
Test name
Test status
Simulation time 29957377383 ps
CPU time 15.07 seconds
Started Jul 22 05:18:41 PM PDT 24
Finished Jul 22 05:18:56 PM PDT 24
Peak memory 196824 kb
Host smart-dafbb6c0-09db-43c6-9842-f6762bbdb599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364224682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2364224682
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3738996535
Short name T286
Test name
Test status
Simulation time 399588505 ps
CPU time 1.17 seconds
Started Jul 22 05:18:44 PM PDT 24
Finished Jul 22 05:18:46 PM PDT 24
Peak memory 191688 kb
Host smart-72a2d13a-8c73-49b8-9452-bf857273e3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738996535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3738996535
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_jump.4175511897
Short name T171
Test name
Test status
Simulation time 361767437 ps
CPU time 0.68 seconds
Started Jul 22 05:18:49 PM PDT 24
Finished Jul 22 05:18:51 PM PDT 24
Peak memory 196536 kb
Host smart-775abfe4-db53-4fce-bfeb-011e0a5fd578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175511897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.4175511897
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1331094658
Short name T231
Test name
Test status
Simulation time 27234118476 ps
CPU time 18.41 seconds
Started Jul 22 05:18:49 PM PDT 24
Finished Jul 22 05:19:08 PM PDT 24
Peak memory 191708 kb
Host smart-f6d497dd-fbba-42b2-9dbd-2682f1ac699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331094658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1331094658
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.456168306
Short name T79
Test name
Test status
Simulation time 553695730 ps
CPU time 0.98 seconds
Started Jul 22 05:18:50 PM PDT 24
Finished Jul 22 05:18:52 PM PDT 24
Peak memory 191720 kb
Host smart-5bd1e28b-8008-46da-98ed-209232abfa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456168306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.456168306
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2676002084
Short name T35
Test name
Test status
Simulation time 33512880809 ps
CPU time 11.78 seconds
Started Jul 22 05:19:00 PM PDT 24
Finished Jul 22 05:19:12 PM PDT 24
Peak memory 191808 kb
Host smart-12fc963b-923a-483e-b054-bf4d1a9458ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676002084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2676002084
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3545289325
Short name T225
Test name
Test status
Simulation time 326592871 ps
CPU time 1.07 seconds
Started Jul 22 05:19:09 PM PDT 24
Finished Jul 22 05:19:10 PM PDT 24
Peak memory 196552 kb
Host smart-5d2e1d87-fc08-4a2d-99a3-edab5ee29d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545289325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3545289325
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1686263064
Short name T265
Test name
Test status
Simulation time 52208734659 ps
CPU time 81.6 seconds
Started Jul 22 05:19:01 PM PDT 24
Finished Jul 22 05:20:23 PM PDT 24
Peak memory 191800 kb
Host smart-b01b5826-47db-4423-a369-e3792dab4dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686263064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1686263064
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.991740653
Short name T278
Test name
Test status
Simulation time 386897699 ps
CPU time 1.3 seconds
Started Jul 22 05:19:01 PM PDT 24
Finished Jul 22 05:19:03 PM PDT 24
Peak memory 191720 kb
Host smart-26559674-6b56-43d0-ae2f-88ba571d1ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991740653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.991740653
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.76229035
Short name T251
Test name
Test status
Simulation time 20932849203 ps
CPU time 9.05 seconds
Started Jul 22 05:18:59 PM PDT 24
Finished Jul 22 05:19:09 PM PDT 24
Peak memory 191764 kb
Host smart-8fa7521d-9dc6-43e9-a821-a33510ac445c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76229035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.76229035
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2510357771
Short name T65
Test name
Test status
Simulation time 617608535 ps
CPU time 0.8 seconds
Started Jul 22 05:19:01 PM PDT 24
Finished Jul 22 05:19:03 PM PDT 24
Peak memory 191712 kb
Host smart-01b59c4f-17ea-4f69-8b1c-69aae1b92f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510357771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2510357771
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3854739245
Short name T281
Test name
Test status
Simulation time 54117324342 ps
CPU time 22.08 seconds
Started Jul 22 05:19:06 PM PDT 24
Finished Jul 22 05:19:28 PM PDT 24
Peak memory 191844 kb
Host smart-da21abd0-6656-422a-89ea-78b8da2a9382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854739245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3854739245
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3189851657
Short name T245
Test name
Test status
Simulation time 529424461 ps
CPU time 1.45 seconds
Started Jul 22 05:18:59 PM PDT 24
Finished Jul 22 05:19:01 PM PDT 24
Peak memory 196580 kb
Host smart-9ee2cef8-3c79-4639-bab5-71cf4164600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189851657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3189851657
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4059842831
Short name T93
Test name
Test status
Simulation time 46626471339 ps
CPU time 17.92 seconds
Started Jul 22 05:17:01 PM PDT 24
Finished Jul 22 05:17:20 PM PDT 24
Peak memory 191832 kb
Host smart-c8546235-8d64-4c6b-b2cf-e96af55e1745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059842831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4059842831
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2221972178
Short name T1
Test name
Test status
Simulation time 497339515 ps
CPU time 0.97 seconds
Started Jul 22 05:16:50 PM PDT 24
Finished Jul 22 05:16:52 PM PDT 24
Peak memory 191712 kb
Host smart-f3370f6c-eabe-479e-968b-bb68599f410b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221972178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2221972178
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4139093905
Short name T211
Test name
Test status
Simulation time 56315173309 ps
CPU time 42.42 seconds
Started Jul 22 05:17:44 PM PDT 24
Finished Jul 22 05:18:27 PM PDT 24
Peak memory 191800 kb
Host smart-2301dfcd-2163-4db1-9963-4203c6bab9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139093905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4139093905
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.615944046
Short name T272
Test name
Test status
Simulation time 433107571 ps
CPU time 0.82 seconds
Started Jul 22 05:17:04 PM PDT 24
Finished Jul 22 05:17:06 PM PDT 24
Peak memory 191696 kb
Host smart-6d0fc010-a493-4efc-b7c4-feb0ccdb78e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615944046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.615944046
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.327084404
Short name T224
Test name
Test status
Simulation time 9704773431 ps
CPU time 13.92 seconds
Started Jul 22 05:17:01 PM PDT 24
Finished Jul 22 05:17:16 PM PDT 24
Peak memory 196764 kb
Host smart-84db8f7d-0e99-46a0-9ce9-bcaca0b4b8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327084404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.327084404
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2472605849
Short name T230
Test name
Test status
Simulation time 467710247 ps
CPU time 1.19 seconds
Started Jul 22 05:17:03 PM PDT 24
Finished Jul 22 05:17:05 PM PDT 24
Peak memory 191664 kb
Host smart-96a6aafb-232b-4552-93a5-e7390914864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472605849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2472605849
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1426482033
Short name T268
Test name
Test status
Simulation time 55766462729 ps
CPU time 19.07 seconds
Started Jul 22 05:17:11 PM PDT 24
Finished Jul 22 05:17:31 PM PDT 24
Peak memory 196860 kb
Host smart-f3f09315-411a-4569-a07a-fa4f69947029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426482033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1426482033
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3871149716
Short name T232
Test name
Test status
Simulation time 380565935 ps
CPU time 1.13 seconds
Started Jul 22 05:17:00 PM PDT 24
Finished Jul 22 05:17:02 PM PDT 24
Peak memory 191716 kb
Host smart-e2c08b80-8d91-4a14-a206-b9d9b6b5c021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871149716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3871149716
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3860192447
Short name T256
Test name
Test status
Simulation time 8945773274 ps
CPU time 7.24 seconds
Started Jul 22 05:17:13 PM PDT 24
Finished Jul 22 05:17:20 PM PDT 24
Peak memory 191876 kb
Host smart-35cadc32-9fdd-4e0a-a799-b3cee9463ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860192447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3860192447
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.175752987
Short name T236
Test name
Test status
Simulation time 413089597 ps
CPU time 0.65 seconds
Started Jul 22 05:17:16 PM PDT 24
Finished Jul 22 05:17:17 PM PDT 24
Peak memory 191692 kb
Host smart-53a4bd59-13d1-4ae8-a821-ae75ea88d966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175752987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.175752987
Directory /workspace/9.aon_timer_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%