Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.69 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 173 4 169 97.69


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 0 2 100.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 66 1 65 98.48 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 29397 1 T1 14 T2 12 T4 11
bark[1] 1082 1 T11 21 T14 415 T51 35
bark[2] 339 1 T40 45 T116 14 T99 26
bark[3] 486 1 T46 14 T109 47 T100 21
bark[4] 531 1 T9 45 T38 155 T125 21
bark[5] 272 1 T30 21 T172 14 T189 14
bark[6] 1118 1 T11 21 T30 21 T14 259
bark[7] 386 1 T15 76 T37 7 T125 21
bark[8] 255 1 T15 49 T50 21 T135 21
bark[9] 556 1 T7 57 T38 7 T51 21
bark[10] 265 1 T11 21 T57 21 T43 21
bark[11] 600 1 T135 21 T136 21 T137 14
bark[12] 499 1 T9 35 T30 35 T51 21
bark[13] 664 1 T3 14 T147 21 T58 226
bark[14] 168 1 T8 26 T130 21 T100 21
bark[15] 273 1 T14 51 T50 49 T148 35
bark[16] 608 1 T14 21 T110 21 T145 56
bark[17] 184 1 T131 76 T176 80 T171 14
bark[18] 536 1 T56 14 T39 7 T42 7
bark[19] 409 1 T8 21 T9 21 T154 14
bark[20] 505 1 T57 59 T147 76 T100 177
bark[21] 245 1 T8 26 T50 57 T57 14
bark[22] 315 1 T184 14 T14 85 T175 14
bark[23] 295 1 T9 26 T14 21 T161 14
bark[24] 396 1 T7 122 T38 21 T135 21
bark[25] 574 1 T30 26 T45 14 T38 226
bark[26] 348 1 T7 21 T9 47 T14 113
bark[27] 285 1 T57 21 T26 30 T166 14
bark[28] 486 1 T42 30 T130 21 T167 14
bark[29] 657 1 T11 21 T47 14 T14 21
bark[30] 413 1 T50 14 T39 60 T42 26
bark[31] 367 1 T5 14 T162 21 T128 21
bark_0 4626 1 T1 7 T2 7 T3 7


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 29057 1 T2 11 T4 10 T6 11
bite[1] 649 1 T14 112 T41 30 T107 63
bite[2] 530 1 T30 21 T42 6 T109 21
bite[3] 556 1 T15 75 T51 35 T39 21
bite[4] 386 1 T8 21 T40 30 T135 21
bite[5] 509 1 T9 44 T124 13 T130 21
bite[6] 353 1 T7 21 T8 26 T9 46
bite[7] 399 1 T30 21 T135 21 T131 76
bite[8] 371 1 T45 13 T14 21 T50 13
bite[9] 265 1 T30 26 T50 57 T131 21
bite[10] 530 1 T8 26 T50 47 T40 44
bite[11] 521 1 T38 21 T39 6 T41 67
bite[12] 584 1 T11 42 T14 21 T51 21
bite[13] 398 1 T9 21 T11 21 T14 258
bite[14] 1018 1 T1 13 T38 154 T131 35
bite[15] 251 1 T95 21 T23 13 T121 13
bite[16] 552 1 T50 49 T57 21 T40 256
bite[17] 202 1 T174 46 T110 21 T176 80
bite[18] 161 1 T139 21 T177 101 T156 26
bite[19] 440 1 T30 35 T184 13 T15 49
bite[20] 239 1 T11 21 T123 21 T131 21
bite[21] 470 1 T125 21 T39 59 T154 13
bite[22] 742 1 T38 6 T50 21 T57 59
bite[23] 288 1 T3 13 T14 84 T51 21
bite[24] 222 1 T14 21 T189 13 T147 21
bite[25] 229 1 T5 13 T7 122 T182 13
bite[26] 420 1 T11 21 T56 13 T175 13
bite[27] 573 1 T14 21 T172 13 T50 21
bite[28] 140 1 T9 26 T123 21 T128 47
bite[29] 675 1 T47 13 T43 278 T137 13
bite[30] 913 1 T7 78 T11 21 T37 44
bite[31] 329 1 T15 21 T37 6 T125 21
bite_0 5168 1 T1 8 T2 8 T3 8


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for pause_in_sleep_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 39520 1 T1 21 T2 19 T3 21
auto[1] 8620 1 T4 7 T7 18 T13 7


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 640 1 T38 127 T57 23 T43 40
prescale[1] 1257 1 T9 54 T14 162 T15 19
prescale[2] 367 1 T37 57 T38 18 T40 19
prescale[3] 577 1 T8 19 T9 90 T38 19
prescale[4] 673 1 T8 89 T14 28 T42 57
prescale[5] 1086 1 T14 19 T15 2 T37 19
prescale[6] 1107 1 T8 9 T9 9 T12 9
prescale[7] 724 1 T14 53 T38 60 T40 24
prescale[8] 704 1 T7 19 T14 167 T50 28
prescale[9] 830 1 T7 40 T9 34 T14 175
prescale[10] 753 1 T57 40 T39 28 T42 19
prescale[11] 821 1 T7 23 T14 19 T38 77
prescale[12] 926 1 T9 19 T11 19 T30 40
prescale[13] 669 1 T14 19 T38 59 T125 44
prescale[14] 919 1 T14 2 T37 143 T38 80
prescale[15] 479 1 T7 19 T14 69 T37 19
prescale[16] 622 1 T10 9 T37 75 T38 105
prescale[17] 456 1 T30 19 T37 2 T125 19
prescale[18] 616 1 T30 28 T14 51 T15 2
prescale[19] 792 1 T9 23 T11 40 T15 2
prescale[20] 575 1 T9 2 T14 45 T41 2
prescale[21] 616 1 T14 169 T57 47 T40 92
prescale[22] 836 1 T6 9 T9 202 T11 33
prescale[23] 646 1 T11 23 T30 58 T14 57
prescale[24] 585 1 T14 9 T37 2 T38 109
prescale[25] 476 1 T39 120 T40 56 T135 33
prescale[26] 589 1 T9 2 T11 41 T38 52
prescale[27] 621 1 T9 2 T30 9 T14 19
prescale[28] 520 1 T2 9 T48 9 T37 42
prescale[29] 539 1 T37 2 T40 30 T42 111
prescale[30] 429 1 T14 37 T37 2 T38 2
prescale[31] 949 1 T7 19 T44 9 T14 11
prescale_0 25741 1 T1 21 T2 10 T3 21


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34734 1 T1 9 T2 9 T3 21
auto[1] 13406 1 T1 12 T2 10 T4 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 48140 1 T1 21 T2 19 T3 21


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 66 1 65 98.48


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 28214 1 T1 1 T2 14 T3 1
wkup[1] 260 1 T7 21 T9 30 T43 21
wkup[2] 295 1 T50 49 T51 21 T100 21
wkup[3] 278 1 T14 42 T37 26 T109 8
wkup[4] 215 1 T109 21 T58 15 T198 21
wkup[5] 152 1 T30 26 T14 42 T39 21
wkup[6] 238 1 T45 15 T14 63 T50 21
wkup[7] 271 1 T14 21 T37 21 T38 35
wkup[8] 135 1 T1 15 T14 21 T111 21
wkup[9] 168 1 T38 21 T100 21 T95 42
wkup[10] 372 1 T38 54 T125 21 T110 21
wkup[11] 141 1 T130 21 T153 21 T127 21
wkup[12] 362 1 T9 21 T11 21 T14 21
wkup[13] 180 1 T40 21 T147 21 T100 8
wkup[14] 183 1 T8 21 T9 21 T123 21
wkup[15] 203 1 T9 21 T14 21 T38 21
wkup[16] 188 1 T9 21 T153 21 T155 15
wkup[17] 179 1 T11 21 T40 15 T58 15
wkup[18] 212 1 T14 21 T38 21 T50 15
wkup[19] 367 1 T9 47 T51 21 T39 21
wkup[20] 477 1 T5 15 T47 15 T14 58
wkup[21] 202 1 T38 26 T39 21 T42 21
wkup[22] 269 1 T11 21 T50 21 T39 21
wkup[23] 298 1 T14 21 T38 21 T57 21
wkup[24] 498 1 T38 21 T54 15 T39 21
wkup[25] 326 1 T14 91 T172 15 T41 21
wkup[26] 435 1 T3 15 T11 21 T14 21
wkup[27] 212 1 T9 21 T14 21 T38 21
wkup[28] 219 1 T15 49 T51 35 T174 30
wkup[29] 315 1 T7 21 T9 8 T37 21
wkup[30] 235 1 T37 51 T42 21 T95 21
wkup[31] 353 1 T7 21 T30 21 T38 21
wkup[32] 243 1 T38 42 T99 21 T58 8
wkup[33] 336 1 T7 21 T57 21 T40 42
wkup[34] 305 1 T7 21 T9 21 T39 19
wkup[35] 252 1 T174 21 T58 21 T153 21
wkup[36] 328 1 T50 21 T174 8 T153 93
wkup[37] 197 1 T147 21 T43 21 T99 26
wkup[38] 368 1 T14 21 T37 21 T38 21
wkup[39] 222 1 T9 15 T37 51 T38 30
wkup[40] 99 1 T109 21 T153 21 T145 21
wkup[41] 318 1 T11 21 T124 15 T43 21
wkup[42] 140 1 T40 21 T42 30 T59 26
wkup[43] 247 1 T15 26 T41 26 T42 21
wkup[44] 255 1 T38 26 T39 26 T135 21
wkup[45] 298 1 T8 26 T37 8 T125 21
wkup[46] 192 1 T9 21 T39 21 T40 21
wkup[47] 257 1 T14 21 T38 35 T39 21
wkup[48] 270 1 T9 21 T14 47 T43 30
wkup[49] 248 1 T30 21 T14 21 T40 21
wkup[50] 212 1 T108 15 T103 50 T177 42
wkup[51] 218 1 T9 26 T11 21 T38 42
wkup[52] 181 1 T7 21 T8 26 T41 21
wkup[53] 420 1 T9 21 T184 15 T38 29
wkup[54] 277 1 T9 8 T37 30 T125 42
wkup[55] 222 1 T189 15 T116 15 T123 15
wkup[56] 208 1 T42 8 T43 21 T26 30
wkup[57] 194 1 T7 21 T40 21 T107 26
wkup[58] 213 1 T109 21 T94 21 T101 21
wkup[59] 262 1 T9 35 T11 21 T38 26
wkup[60] 290 1 T9 26 T14 21 T38 21
wkup[61] 184 1 T30 35 T46 15 T15 21
wkup[62] 399 1 T14 26 T38 21 T56 15
wkup[63] 148 1 T14 51 T123 21 T58 21
wkup_0 3685 1 T1 5 T2 5 T3 5

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