Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.01 99.33 93.67 100.00 98.40 99.51 49.17


Total test records in report: 425
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T283 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.50951443 Jul 23 06:30:52 PM PDT 24 Jul 23 06:31:00 PM PDT 24 473391658 ps
T31 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.863415523 Jul 23 06:30:45 PM PDT 24 Jul 23 06:30:50 PM PDT 24 2601645731 ps
T36 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1388554821 Jul 23 06:30:55 PM PDT 24 Jul 23 06:31:03 PM PDT 24 863062915 ps
T32 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.163255395 Jul 23 06:30:43 PM PDT 24 Jul 23 06:30:45 PM PDT 24 351075029 ps
T33 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.374794867 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:11 PM PDT 24 8036651453 ps
T64 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.372851134 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:01 PM PDT 24 466921343 ps
T284 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3602316723 Jul 23 06:30:56 PM PDT 24 Jul 23 06:31:03 PM PDT 24 466798807 ps
T285 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1916370780 Jul 23 06:30:51 PM PDT 24 Jul 23 06:30:57 PM PDT 24 279345027 ps
T199 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3248739848 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:10 PM PDT 24 363698653 ps
T286 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1062182277 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:14 PM PDT 24 366783912 ps
T88 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2695353972 Jul 23 06:30:48 PM PDT 24 Jul 23 06:30:57 PM PDT 24 1425695510 ps
T34 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.103912452 Jul 23 06:30:33 PM PDT 24 Jul 23 06:30:41 PM PDT 24 4687488513 ps
T287 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3206031029 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:07 PM PDT 24 473251578 ps
T35 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2339553267 Jul 23 06:30:50 PM PDT 24 Jul 23 06:31:04 PM PDT 24 4465822050 ps
T288 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.188629497 Jul 23 06:30:49 PM PDT 24 Jul 23 06:30:56 PM PDT 24 410758372 ps
T89 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.615392195 Jul 23 06:30:45 PM PDT 24 Jul 23 06:30:50 PM PDT 24 2307256749 ps
T194 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1530632857 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:04 PM PDT 24 8212227402 ps
T289 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2503553519 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:01 PM PDT 24 384857174 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3904458163 Jul 23 06:30:40 PM PDT 24 Jul 23 06:30:45 PM PDT 24 776840877 ps
T90 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2780754552 Jul 23 06:30:40 PM PDT 24 Jul 23 06:30:44 PM PDT 24 1208868609 ps
T290 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1424741090 Jul 23 06:30:53 PM PDT 24 Jul 23 06:30:59 PM PDT 24 409663535 ps
T291 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2744738895 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:00 PM PDT 24 285347675 ps
T292 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2823850340 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:06 PM PDT 24 318932667 ps
T293 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2228848339 Jul 23 06:30:36 PM PDT 24 Jul 23 06:30:39 PM PDT 24 425309578 ps
T91 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.802538640 Jul 23 06:30:50 PM PDT 24 Jul 23 06:30:58 PM PDT 24 1122619683 ps
T294 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.234932093 Jul 23 06:30:31 PM PDT 24 Jul 23 06:30:37 PM PDT 24 399715794 ps
T195 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4229412004 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:22 PM PDT 24 8275744397 ps
T295 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3706695674 Jul 23 06:30:39 PM PDT 24 Jul 23 06:30:40 PM PDT 24 451481930 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2588219416 Jul 23 06:30:27 PM PDT 24 Jul 23 06:30:38 PM PDT 24 4496761728 ps
T297 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3959734032 Jul 23 06:30:29 PM PDT 24 Jul 23 06:30:55 PM PDT 24 7091379937 ps
T298 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2937568637 Jul 23 06:30:45 PM PDT 24 Jul 23 06:30:56 PM PDT 24 4545431528 ps
T299 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1615337376 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:06 PM PDT 24 345919489 ps
T66 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.844367728 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:05 PM PDT 24 339063745 ps
T300 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2454615147 Jul 23 06:30:40 PM PDT 24 Jul 23 06:30:58 PM PDT 24 7134982213 ps
T301 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4197633437 Jul 23 06:30:35 PM PDT 24 Jul 23 06:30:39 PM PDT 24 371472894 ps
T302 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2540822189 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:10 PM PDT 24 328800176 ps
T303 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1175678941 Jul 23 06:30:56 PM PDT 24 Jul 23 06:31:04 PM PDT 24 296425473 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3576146351 Jul 23 06:30:38 PM PDT 24 Jul 23 06:30:40 PM PDT 24 508723043 ps
T92 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2516952492 Jul 23 06:30:31 PM PDT 24 Jul 23 06:30:38 PM PDT 24 2786394051 ps
T304 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4189377501 Jul 23 06:30:28 PM PDT 24 Jul 23 06:30:36 PM PDT 24 404376245 ps
T72 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3446795395 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:05 PM PDT 24 418556828 ps
T305 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3864315876 Jul 23 06:30:30 PM PDT 24 Jul 23 06:30:36 PM PDT 24 359281803 ps
T306 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4078251968 Jul 23 06:31:00 PM PDT 24 Jul 23 06:31:07 PM PDT 24 473126089 ps
T93 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.200716710 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:06 PM PDT 24 1276118604 ps
T307 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.403728834 Jul 23 06:30:27 PM PDT 24 Jul 23 06:30:36 PM PDT 24 697599057 ps
T308 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2286961625 Jul 23 06:30:51 PM PDT 24 Jul 23 06:31:00 PM PDT 24 4438508964 ps
T309 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2067979583 Jul 23 06:30:28 PM PDT 24 Jul 23 06:30:35 PM PDT 24 448212713 ps
T73 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3373335014 Jul 23 06:30:23 PM PDT 24 Jul 23 06:30:33 PM PDT 24 410480016 ps
T310 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2971354152 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:13 PM PDT 24 411696253 ps
T311 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1762322102 Jul 23 06:30:52 PM PDT 24 Jul 23 06:31:00 PM PDT 24 1021355320 ps
T312 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2175478808 Jul 23 06:30:50 PM PDT 24 Jul 23 06:30:57 PM PDT 24 467658707 ps
T313 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3606250328 Jul 23 06:30:35 PM PDT 24 Jul 23 06:30:39 PM PDT 24 713346792 ps
T314 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2332068645 Jul 23 06:31:07 PM PDT 24 Jul 23 06:31:15 PM PDT 24 321525071 ps
T315 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3570723947 Jul 23 06:30:27 PM PDT 24 Jul 23 06:30:36 PM PDT 24 1862264806 ps
T316 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.242487919 Jul 23 06:30:45 PM PDT 24 Jul 23 06:30:49 PM PDT 24 496207984 ps
T317 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1114937975 Jul 23 06:30:52 PM PDT 24 Jul 23 06:30:58 PM PDT 24 376320165 ps
T318 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.313227259 Jul 23 06:30:51 PM PDT 24 Jul 23 06:30:58 PM PDT 24 359962332 ps
T319 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3384321372 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:05 PM PDT 24 414175650 ps
T320 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3890347858 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:12 PM PDT 24 407459088 ps
T321 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1139371409 Jul 23 06:30:45 PM PDT 24 Jul 23 06:30:51 PM PDT 24 4651361945 ps
T322 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1539074198 Jul 23 06:30:43 PM PDT 24 Jul 23 06:30:45 PM PDT 24 350100500 ps
T323 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4190678014 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:10 PM PDT 24 333504418 ps
T324 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.407331081 Jul 23 06:30:59 PM PDT 24 Jul 23 06:31:07 PM PDT 24 478721649 ps
T325 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4140385764 Jul 23 06:30:28 PM PDT 24 Jul 23 06:30:36 PM PDT 24 465976061 ps
T326 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.119378255 Jul 23 06:30:31 PM PDT 24 Jul 23 06:30:37 PM PDT 24 278498831 ps
T327 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1525888970 Jul 23 06:30:28 PM PDT 24 Jul 23 06:30:35 PM PDT 24 338242190 ps
T328 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1084997193 Jul 23 06:30:55 PM PDT 24 Jul 23 06:31:10 PM PDT 24 2554121679 ps
T329 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3780074974 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:09 PM PDT 24 340454318 ps
T330 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2264153739 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:18 PM PDT 24 8366715250 ps
T331 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2320147367 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:10 PM PDT 24 385190710 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2539449508 Jul 23 06:30:27 PM PDT 24 Jul 23 06:30:35 PM PDT 24 322546386 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.64860004 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:12 PM PDT 24 8353188185 ps
T334 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3244216481 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:11 PM PDT 24 1236571437 ps
T335 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3356913914 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:14 PM PDT 24 468692135 ps
T336 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.811364118 Jul 23 06:31:00 PM PDT 24 Jul 23 06:31:07 PM PDT 24 419573713 ps
T337 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3567228680 Jul 23 06:31:02 PM PDT 24 Jul 23 06:31:09 PM PDT 24 460715497 ps
T87 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1159709119 Jul 23 06:30:55 PM PDT 24 Jul 23 06:31:02 PM PDT 24 440027595 ps
T338 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2668162838 Jul 23 06:31:00 PM PDT 24 Jul 23 06:31:08 PM PDT 24 580109277 ps
T339 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1332348394 Jul 23 06:30:59 PM PDT 24 Jul 23 06:31:07 PM PDT 24 410667774 ps
T340 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.600827531 Jul 23 06:30:59 PM PDT 24 Jul 23 06:31:08 PM PDT 24 2601750378 ps
T341 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4178430391 Jul 23 06:30:25 PM PDT 24 Jul 23 06:30:35 PM PDT 24 472886247 ps
T342 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4120854031 Jul 23 06:30:23 PM PDT 24 Jul 23 06:30:33 PM PDT 24 352292741 ps
T343 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.537370108 Jul 23 06:30:46 PM PDT 24 Jul 23 06:30:50 PM PDT 24 364099056 ps
T344 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.900174268 Jul 23 06:30:50 PM PDT 24 Jul 23 06:30:59 PM PDT 24 1194228336 ps
T345 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2352772825 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:01 PM PDT 24 389902134 ps
T346 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.502574135 Jul 23 06:31:02 PM PDT 24 Jul 23 06:31:09 PM PDT 24 455848918 ps
T67 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3091735984 Jul 23 06:30:49 PM PDT 24 Jul 23 06:30:56 PM PDT 24 502426164 ps
T347 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1395396095 Jul 23 06:30:57 PM PDT 24 Jul 23 06:31:04 PM PDT 24 348717584 ps
T348 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3803350338 Jul 23 06:31:10 PM PDT 24 Jul 23 06:31:21 PM PDT 24 405929508 ps
T349 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1635271481 Jul 23 06:30:46 PM PDT 24 Jul 23 06:30:51 PM PDT 24 386582693 ps
T350 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2889251701 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:14 PM PDT 24 517574227 ps
T351 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3814200201 Jul 23 06:30:57 PM PDT 24 Jul 23 06:31:04 PM PDT 24 405364407 ps
T352 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2836008776 Jul 23 06:31:01 PM PDT 24 Jul 23 06:31:08 PM PDT 24 307873192 ps
T353 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2684612823 Jul 23 06:30:56 PM PDT 24 Jul 23 06:31:03 PM PDT 24 523604036 ps
T354 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.434801216 Jul 23 06:30:46 PM PDT 24 Jul 23 06:30:53 PM PDT 24 588095011 ps
T355 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1784531295 Jul 23 06:30:59 PM PDT 24 Jul 23 06:31:07 PM PDT 24 460174274 ps
T356 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3984861928 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:02 PM PDT 24 2232986799 ps
T357 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4229589051 Jul 23 06:30:50 PM PDT 24 Jul 23 06:30:58 PM PDT 24 928204156 ps
T358 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1496198970 Jul 23 06:30:24 PM PDT 24 Jul 23 06:30:33 PM PDT 24 432573662 ps
T68 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2943847799 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:06 PM PDT 24 472753875 ps
T359 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1121906159 Jul 23 06:30:40 PM PDT 24 Jul 23 06:30:45 PM PDT 24 577629085 ps
T360 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.226282930 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:07 PM PDT 24 1562248957 ps
T361 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.99854755 Jul 23 06:30:39 PM PDT 24 Jul 23 06:30:42 PM PDT 24 628904439 ps
T197 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2984209916 Jul 23 06:30:44 PM PDT 24 Jul 23 06:30:57 PM PDT 24 8447623533 ps
T362 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1357949605 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:05 PM PDT 24 581267093 ps
T363 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3088093258 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:01 PM PDT 24 472761881 ps
T364 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3068668556 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:04 PM PDT 24 1927256238 ps
T365 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3390771130 Jul 23 06:30:56 PM PDT 24 Jul 23 06:31:03 PM PDT 24 322558182 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.955408285 Jul 23 06:30:49 PM PDT 24 Jul 23 06:30:56 PM PDT 24 364545015 ps
T74 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2398526130 Jul 23 06:30:40 PM PDT 24 Jul 23 06:30:43 PM PDT 24 475694588 ps
T367 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.590418542 Jul 23 06:30:50 PM PDT 24 Jul 23 06:30:57 PM PDT 24 460253277 ps
T368 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1968011098 Jul 23 06:31:02 PM PDT 24 Jul 23 06:31:09 PM PDT 24 496254003 ps
T369 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1155823794 Jul 23 06:30:39 PM PDT 24 Jul 23 06:30:41 PM PDT 24 502137987 ps
T370 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2216322402 Jul 23 06:30:40 PM PDT 24 Jul 23 06:30:42 PM PDT 24 414595922 ps
T371 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.699589265 Jul 23 06:30:57 PM PDT 24 Jul 23 06:31:04 PM PDT 24 615294796 ps
T372 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.147950531 Jul 23 06:30:40 PM PDT 24 Jul 23 06:30:43 PM PDT 24 320386326 ps
T373 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.859159228 Jul 23 06:30:29 PM PDT 24 Jul 23 06:30:36 PM PDT 24 603095724 ps
T374 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.445677149 Jul 23 06:30:39 PM PDT 24 Jul 23 06:30:45 PM PDT 24 1223461815 ps
T375 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2244025160 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:10 PM PDT 24 497696477 ps
T376 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1701164517 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:13 PM PDT 24 505216779 ps
T377 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3974988828 Jul 23 06:31:02 PM PDT 24 Jul 23 06:31:09 PM PDT 24 493602012 ps
T378 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1445167617 Jul 23 06:30:51 PM PDT 24 Jul 23 06:30:58 PM PDT 24 527012633 ps
T379 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2810741739 Jul 23 06:30:52 PM PDT 24 Jul 23 06:30:58 PM PDT 24 605591863 ps
T380 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3068684505 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:07 PM PDT 24 9954215658 ps
T69 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.600640437 Jul 23 06:30:59 PM PDT 24 Jul 23 06:31:07 PM PDT 24 412153758 ps
T75 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1445487377 Jul 23 06:30:44 PM PDT 24 Jul 23 06:30:47 PM PDT 24 704967717 ps
T381 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3615352815 Jul 23 06:31:00 PM PDT 24 Jul 23 06:31:13 PM PDT 24 4391091135 ps
T382 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4241430496 Jul 23 06:30:41 PM PDT 24 Jul 23 06:30:44 PM PDT 24 370445928 ps
T76 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3388425135 Jul 23 06:30:31 PM PDT 24 Jul 23 06:30:38 PM PDT 24 484025687 ps
T383 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.493449224 Jul 23 06:30:52 PM PDT 24 Jul 23 06:31:00 PM PDT 24 1267196602 ps
T384 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.94120251 Jul 23 06:31:01 PM PDT 24 Jul 23 06:31:08 PM PDT 24 288523695 ps
T385 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4042476592 Jul 23 06:31:03 PM PDT 24 Jul 23 06:31:09 PM PDT 24 515096036 ps
T386 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2762186676 Jul 23 06:30:46 PM PDT 24 Jul 23 06:30:51 PM PDT 24 475116115 ps
T387 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1693239524 Jul 23 06:30:46 PM PDT 24 Jul 23 06:30:51 PM PDT 24 321526193 ps
T388 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.705962986 Jul 23 06:30:46 PM PDT 24 Jul 23 06:30:50 PM PDT 24 454882120 ps
T389 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4073277292 Jul 23 06:30:28 PM PDT 24 Jul 23 06:30:41 PM PDT 24 7962751244 ps
T70 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2432998978 Jul 23 06:30:49 PM PDT 24 Jul 23 06:30:55 PM PDT 24 281069685 ps
T390 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.664242821 Jul 23 06:30:45 PM PDT 24 Jul 23 06:30:49 PM PDT 24 424058777 ps
T391 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.739568589 Jul 23 06:30:57 PM PDT 24 Jul 23 06:31:06 PM PDT 24 414086773 ps
T392 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.327400527 Jul 23 06:31:04 PM PDT 24 Jul 23 06:31:11 PM PDT 24 476811072 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3104877495 Jul 23 06:30:29 PM PDT 24 Jul 23 06:30:36 PM PDT 24 442867773 ps
T394 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.338295239 Jul 23 06:30:46 PM PDT 24 Jul 23 06:30:56 PM PDT 24 3771602966 ps
T395 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1095773267 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:13 PM PDT 24 352746111 ps
T77 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.474046224 Jul 23 06:30:28 PM PDT 24 Jul 23 06:30:36 PM PDT 24 1177636867 ps
T196 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.522379474 Jul 23 06:30:54 PM PDT 24 Jul 23 06:31:02 PM PDT 24 4319828827 ps
T396 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3964346558 Jul 23 06:31:00 PM PDT 24 Jul 23 06:31:07 PM PDT 24 509578548 ps
T397 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1602030675 Jul 23 06:30:58 PM PDT 24 Jul 23 06:31:06 PM PDT 24 989960707 ps
T398 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.303525619 Jul 23 06:30:45 PM PDT 24 Jul 23 06:30:49 PM PDT 24 542670337 ps
T399 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2752076443 Jul 23 06:31:02 PM PDT 24 Jul 23 06:31:09 PM PDT 24 352421440 ps
T400 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3257956687 Jul 23 06:31:02 PM PDT 24 Jul 23 06:31:08 PM PDT 24 313039238 ps
T401 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2385984873 Jul 23 06:30:40 PM PDT 24 Jul 23 06:30:43 PM PDT 24 491340590 ps
T402 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2815036545 Jul 23 06:30:57 PM PDT 24 Jul 23 06:31:18 PM PDT 24 8615119845 ps
T403 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1900412129 Jul 23 06:30:29 PM PDT 24 Jul 23 06:30:37 PM PDT 24 1148143735 ps
T404 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3688291502 Jul 23 06:30:34 PM PDT 24 Jul 23 06:30:39 PM PDT 24 2436373728 ps
T405 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.144652498 Jul 23 06:30:28 PM PDT 24 Jul 23 06:30:36 PM PDT 24 631691424 ps
T406 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1301391035 Jul 23 06:31:01 PM PDT 24 Jul 23 06:31:08 PM PDT 24 307654625 ps
T407 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1310607574 Jul 23 06:31:06 PM PDT 24 Jul 23 06:31:14 PM PDT 24 311091884 ps
T408 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2596346548 Jul 23 06:30:28 PM PDT 24 Jul 23 06:30:36 PM PDT 24 471887935 ps
T409 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3363920398 Jul 23 06:30:30 PM PDT 24 Jul 23 06:30:36 PM PDT 24 884967460 ps
T410 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1994682882 Jul 23 06:30:30 PM PDT 24 Jul 23 06:30:36 PM PDT 24 335222775 ps
T411 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1042054312 Jul 23 06:30:48 PM PDT 24 Jul 23 06:30:54 PM PDT 24 300840539 ps
T412 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1798464194 Jul 23 06:30:59 PM PDT 24 Jul 23 06:31:09 PM PDT 24 2414351712 ps
T413 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.439185162 Jul 23 06:30:28 PM PDT 24 Jul 23 06:30:40 PM PDT 24 5900010447 ps
T414 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1368416990 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:12 PM PDT 24 316805685 ps
T415 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2506789476 Jul 23 06:30:24 PM PDT 24 Jul 23 06:30:41 PM PDT 24 13671999389 ps
T416 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3595614701 Jul 23 06:30:46 PM PDT 24 Jul 23 06:30:50 PM PDT 24 368954234 ps
T417 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.4073760582 Jul 23 06:31:05 PM PDT 24 Jul 23 06:31:13 PM PDT 24 416355206 ps
T418 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2184290621 Jul 23 06:30:47 PM PDT 24 Jul 23 06:30:55 PM PDT 24 8326433328 ps
T419 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2997462448 Jul 23 06:30:25 PM PDT 24 Jul 23 06:30:35 PM PDT 24 4339575996 ps
T420 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3874449296 Jul 23 06:30:51 PM PDT 24 Jul 23 06:30:57 PM PDT 24 368553992 ps
T421 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2858536337 Jul 23 06:30:46 PM PDT 24 Jul 23 06:30:51 PM PDT 24 640092396 ps
T422 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1306732059 Jul 23 06:30:51 PM PDT 24 Jul 23 06:30:58 PM PDT 24 593183725 ps
T423 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2060882330 Jul 23 06:30:25 PM PDT 24 Jul 23 06:30:34 PM PDT 24 375568388 ps
T424 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.714727376 Jul 23 06:30:45 PM PDT 24 Jul 23 06:30:50 PM PDT 24 452737539 ps
T425 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3270985882 Jul 23 06:30:53 PM PDT 24 Jul 23 06:30:59 PM PDT 24 350778282 ps

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.689646422
Short name T9
Test name
Test status
Simulation time 252497562302 ps
CPU time 357.77 seconds
Started Jul 23 06:50:33 PM PDT 24
Finished Jul 23 06:56:32 PM PDT 24
Peak memory 213824 kb
Host smart-8923397e-ea2c-4f3b-a5d0-69de0b5cc3f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689646422 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.689646422
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2991082783
Short name T14
Test name
Test status
Simulation time 64233401802 ps
CPU time 506.05 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:59:07 PM PDT 24
Peak memory 202420 kb
Host smart-57332fca-da4b-411c-87d3-0db358fc7a0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991082783 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2991082783
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.103912452
Short name T34
Test name
Test status
Simulation time 4687488513 ps
CPU time 4.45 seconds
Started Jul 23 06:30:33 PM PDT 24
Finished Jul 23 06:30:41 PM PDT 24
Peak memory 198416 kb
Host smart-fc1f81bf-c31a-4d8a-a93e-4ada10fb3b5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103912452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.103912452
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1934083765
Short name T103
Test name
Test status
Simulation time 580103289809 ps
CPU time 998.89 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 07:07:30 PM PDT 24
Peak memory 214860 kb
Host smart-eeba4b65-606c-451b-bed8-00f1ce4ac669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934083765 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1934083765
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.784009329
Short name T63
Test name
Test status
Simulation time 277349768273 ps
CPU time 645.54 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 07:01:33 PM PDT 24
Peak memory 214416 kb
Host smart-1700ecee-1377-4874-9b39-2e7245a5d315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784009329 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.784009329
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.694748531
Short name T8
Test name
Test status
Simulation time 106640607310 ps
CPU time 69.1 seconds
Started Jul 23 06:50:32 PM PDT 24
Finished Jul 23 06:51:43 PM PDT 24
Peak memory 183880 kb
Host smart-3c9ea8c4-cf22-4fe8-98d1-fb0d1d1f49f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694748531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.694748531
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2471524813
Short name T97
Test name
Test status
Simulation time 172361065394 ps
CPU time 540.48 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:59:26 PM PDT 24
Peak memory 206688 kb
Host smart-e8c7e9fd-6bf9-48d7-83df-37361032027d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471524813 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2471524813
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3511251694
Short name T100
Test name
Test status
Simulation time 60245237505 ps
CPU time 215.46 seconds
Started Jul 23 06:50:48 PM PDT 24
Finished Jul 23 06:54:26 PM PDT 24
Peak memory 206608 kb
Host smart-a6b8d06f-0788-4de9-8630-9b0d73868474
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511251694 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3511251694
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1802189289
Short name T153
Test name
Test status
Simulation time 142768085479 ps
CPU time 805.68 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 07:04:06 PM PDT 24
Peak memory 214828 kb
Host smart-988fddcd-1ffd-4ef0-9cd2-ef8c80a06f55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802189289 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1802189289
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1744812444
Short name T30
Test name
Test status
Simulation time 508499449589 ps
CPU time 304.52 seconds
Started Jul 23 06:50:22 PM PDT 24
Finished Jul 23 06:55:28 PM PDT 24
Peak memory 193008 kb
Host smart-d46fa1bc-fa8e-4d2e-94f3-2c606647b320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744812444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1744812444
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.820225079
Short name T120
Test name
Test status
Simulation time 57189476098 ps
CPU time 313.28 seconds
Started Jul 23 06:50:40 PM PDT 24
Finished Jul 23 06:55:56 PM PDT 24
Peak memory 207924 kb
Host smart-90dcf1dc-1569-49d9-bb5e-766c8024652a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820225079 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.820225079
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.355522948
Short name T16
Test name
Test status
Simulation time 8418722677 ps
CPU time 2.38 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:29 PM PDT 24
Peak memory 215608 kb
Host smart-2de654d5-c368-41ec-87af-0269bcea1988
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355522948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.355522948
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1288983286
Short name T115
Test name
Test status
Simulation time 114812062269 ps
CPU time 189.97 seconds
Started Jul 23 06:50:27 PM PDT 24
Finished Jul 23 06:53:40 PM PDT 24
Peak memory 206680 kb
Host smart-b16e0c1f-95e1-466e-afa6-b18abfaf3eb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288983286 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1288983286
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2776433824
Short name T37
Test name
Test status
Simulation time 353563183496 ps
CPU time 720.57 seconds
Started Jul 23 06:50:22 PM PDT 24
Finished Jul 23 07:02:24 PM PDT 24
Peak memory 214872 kb
Host smart-6175429c-40ea-475a-947e-738be0da07bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776433824 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2776433824
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2086466876
Short name T156
Test name
Test status
Simulation time 32903877699 ps
CPU time 25.87 seconds
Started Jul 23 06:50:50 PM PDT 24
Finished Jul 23 06:51:18 PM PDT 24
Peak memory 191900 kb
Host smart-3b51423d-262f-486a-b7d7-706902ee99e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086466876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2086466876
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.645401002
Short name T95
Test name
Test status
Simulation time 404007544552 ps
CPU time 780.95 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 07:03:32 PM PDT 24
Peak memory 214880 kb
Host smart-22bd81bc-4469-4755-817f-4a5b7901d40b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645401002 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.645401002
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3194648636
Short name T126
Test name
Test status
Simulation time 159534422292 ps
CPU time 211.63 seconds
Started Jul 23 06:50:27 PM PDT 24
Finished Jul 23 06:54:01 PM PDT 24
Peak memory 184184 kb
Host smart-9452a833-0ea6-4ed9-bc57-54274f7a7fb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194648636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3194648636
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.96487405
Short name T113
Test name
Test status
Simulation time 233977477561 ps
CPU time 302.47 seconds
Started Jul 23 06:50:33 PM PDT 24
Finished Jul 23 06:55:37 PM PDT 24
Peak memory 193120 kb
Host smart-b6ba0e59-e0ec-4609-91d7-83d6ed39c4e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96487405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_al
l.96487405
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2710747238
Short name T107
Test name
Test status
Simulation time 185832802058 ps
CPU time 106.15 seconds
Started Jul 23 06:50:37 PM PDT 24
Finished Jul 23 06:52:25 PM PDT 24
Peak memory 198212 kb
Host smart-e6df0573-980a-4127-aebd-5e3a6ce08a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710747238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2710747238
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1389514184
Short name T128
Test name
Test status
Simulation time 112370282092 ps
CPU time 42.11 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 06:51:30 PM PDT 24
Peak memory 184520 kb
Host smart-28c11543-f3b2-4efe-906f-8993006cfa22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389514184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1389514184
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2116813195
Short name T142
Test name
Test status
Simulation time 137271238322 ps
CPU time 295.35 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:55:21 PM PDT 24
Peak memory 206672 kb
Host smart-a15fe9e6-0f8a-4ab5-878a-475d2a0d561a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116813195 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2116813195
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4014805514
Short name T119
Test name
Test status
Simulation time 31151581272 ps
CPU time 295.08 seconds
Started Jul 23 06:50:50 PM PDT 24
Finished Jul 23 06:55:48 PM PDT 24
Peak memory 206288 kb
Host smart-5fdb9268-d912-49e4-9070-c5f2b56d238a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014805514 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4014805514
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1961865383
Short name T50
Test name
Test status
Simulation time 91294795407 ps
CPU time 125.29 seconds
Started Jul 23 06:50:35 PM PDT 24
Finished Jul 23 06:52:42 PM PDT 24
Peak memory 192972 kb
Host smart-2ace0393-58f8-4385-b4da-75180f1a8d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961865383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1961865383
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.4225925781
Short name T81
Test name
Test status
Simulation time 52843530634 ps
CPU time 38.6 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:51:39 PM PDT 24
Peak memory 198564 kb
Host smart-a1381f9f-8a3e-4af3-bab9-b853d4fa42ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225925781 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.4225925781
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4072325137
Short name T129
Test name
Test status
Simulation time 59067422872 ps
CPU time 191.31 seconds
Started Jul 23 06:50:16 PM PDT 24
Finished Jul 23 06:53:28 PM PDT 24
Peak memory 214376 kb
Host smart-2967d5c5-bb0a-4567-bffc-b3703280dc21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072325137 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4072325137
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.796701969
Short name T123
Test name
Test status
Simulation time 140494620980 ps
CPU time 217.89 seconds
Started Jul 23 06:50:38 PM PDT 24
Finished Jul 23 06:54:17 PM PDT 24
Peak memory 193004 kb
Host smart-353d2d8b-91e6-4edc-97d5-c4e85aeafe53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796701969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.796701969
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3423236263
Short name T135
Test name
Test status
Simulation time 215801240702 ps
CPU time 320.03 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 06:56:11 PM PDT 24
Peak memory 192096 kb
Host smart-8150b5cf-a245-4651-9fd9-bee15d587c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423236263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3423236263
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1592559817
Short name T139
Test name
Test status
Simulation time 341036576776 ps
CPU time 250.46 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:54:37 PM PDT 24
Peak memory 192704 kb
Host smart-c828a732-ffa3-46e3-9475-e123b3cfae91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592559817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1592559817
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2237843406
Short name T127
Test name
Test status
Simulation time 23148017918 ps
CPU time 180.67 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 06:53:49 PM PDT 24
Peak memory 214668 kb
Host smart-61e274ac-f6e3-45b1-ba7e-467565d05cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237843406 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2237843406
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.445864596
Short name T11
Test name
Test status
Simulation time 205919564025 ps
CPU time 76.41 seconds
Started Jul 23 06:50:14 PM PDT 24
Finished Jul 23 06:51:32 PM PDT 24
Peak memory 192480 kb
Host smart-7cbe5057-73f0-4ce7-8292-6c269d32bd1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445864596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.445864596
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.372851134
Short name T64
Test name
Test status
Simulation time 466921343 ps
CPU time 0.78 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:01 PM PDT 24
Peak memory 192476 kb
Host smart-6510b1af-2a47-4f9f-a987-ec6f01283cb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372851134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.372851134
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3870946504
Short name T162
Test name
Test status
Simulation time 228032962144 ps
CPU time 349.24 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:56:30 PM PDT 24
Peak memory 198236 kb
Host smart-9217538b-e7da-4c4f-a624-8d91d8fe64a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870946504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3870946504
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2249593612
Short name T15
Test name
Test status
Simulation time 182148563487 ps
CPU time 426.01 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:58:03 PM PDT 24
Peak memory 211384 kb
Host smart-4f8a2b44-f057-456b-8c2a-0d09f3a9207f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249593612 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2249593612
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1350628867
Short name T144
Test name
Test status
Simulation time 92380278792 ps
CPU time 27.92 seconds
Started Jul 23 06:50:26 PM PDT 24
Finished Jul 23 06:50:56 PM PDT 24
Peak memory 198216 kb
Host smart-5477d10c-5a90-44a2-b763-522a9f064f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350628867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1350628867
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1079188077
Short name T40
Test name
Test status
Simulation time 233230289081 ps
CPU time 315.68 seconds
Started Jul 23 06:50:28 PM PDT 24
Finished Jul 23 06:55:46 PM PDT 24
Peak memory 209704 kb
Host smart-92def4f1-381f-4fe8-92da-fbf397ec59ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079188077 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1079188077
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1586261355
Short name T7
Test name
Test status
Simulation time 156437943835 ps
CPU time 214.88 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 06:54:21 PM PDT 24
Peak memory 192376 kb
Host smart-df8bf605-4492-48a1-98a4-f4e975c045e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586261355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1586261355
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1143015581
Short name T58
Test name
Test status
Simulation time 68869182542 ps
CPU time 424.3 seconds
Started Jul 23 06:50:25 PM PDT 24
Finished Jul 23 06:57:32 PM PDT 24
Peak memory 200488 kb
Host smart-ff468211-ecbe-4404-ab5c-e61c017dc132
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143015581 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1143015581
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3382593576
Short name T130
Test name
Test status
Simulation time 204311004506 ps
CPU time 296.23 seconds
Started Jul 23 06:50:31 PM PDT 24
Finished Jul 23 06:55:29 PM PDT 24
Peak memory 198188 kb
Host smart-587d72da-c701-45d1-a111-406bff081ab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382593576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3382593576
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1362063831
Short name T39
Test name
Test status
Simulation time 185911807594 ps
CPU time 440.33 seconds
Started Jul 23 06:50:44 PM PDT 24
Finished Jul 23 06:58:05 PM PDT 24
Peak memory 211448 kb
Host smart-37a0eb6a-c179-45f0-a345-190d9f140463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362063831 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1362063831
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.186048810
Short name T109
Test name
Test status
Simulation time 16196990178 ps
CPU time 97.98 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 06:52:09 PM PDT 24
Peak memory 198476 kb
Host smart-f91c4e4c-b756-4169-8f7d-3f53033c6899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186048810 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.186048810
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3152858301
Short name T62
Test name
Test status
Simulation time 93802456011 ps
CPU time 300.42 seconds
Started Jul 23 06:50:34 PM PDT 24
Finished Jul 23 06:55:36 PM PDT 24
Peak memory 200580 kb
Host smart-d3a03e42-c8e1-4654-8abc-d4d62a698ff2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152858301 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3152858301
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1478752868
Short name T125
Test name
Test status
Simulation time 186534203303 ps
CPU time 21.62 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:51:18 PM PDT 24
Peak memory 198264 kb
Host smart-0ecc3b1f-0c5d-4d3b-91d1-7418c77e3c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478752868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1478752868
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2684371414
Short name T134
Test name
Test status
Simulation time 197687754214 ps
CPU time 50.6 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:51:17 PM PDT 24
Peak memory 191888 kb
Host smart-657452b3-0c5c-4e75-827a-1b4087e5b16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684371414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2684371414
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3843223872
Short name T60
Test name
Test status
Simulation time 168542298718 ps
CPU time 415.21 seconds
Started Jul 23 06:50:23 PM PDT 24
Finished Jul 23 06:57:20 PM PDT 24
Peak memory 214680 kb
Host smart-94c40498-f2a5-4f70-b45b-9927184d279b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843223872 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3843223872
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1296549499
Short name T131
Test name
Test status
Simulation time 69046186570 ps
CPU time 23.24 seconds
Started Jul 23 06:50:43 PM PDT 24
Finished Jul 23 06:51:07 PM PDT 24
Peak memory 191896 kb
Host smart-4aab8cd1-b26e-4c5c-aea0-c53e0121af30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296549499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1296549499
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.673865493
Short name T158
Test name
Test status
Simulation time 60479750226 ps
CPU time 47.14 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 06:51:35 PM PDT 24
Peak memory 198236 kb
Host smart-f2e310e3-b08b-421b-b3ca-7720964f5b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673865493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.673865493
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2105775003
Short name T148
Test name
Test status
Simulation time 68501793139 ps
CPU time 28.18 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:54 PM PDT 24
Peak memory 191876 kb
Host smart-fd36489f-2440-44a2-b7b5-5ca6e152f96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105775003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2105775003
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2770613270
Short name T38
Test name
Test status
Simulation time 796735689354 ps
CPU time 320 seconds
Started Jul 23 06:50:37 PM PDT 24
Finished Jul 23 06:55:59 PM PDT 24
Peak memory 206720 kb
Host smart-e8f7798f-7f4e-4b94-b0ec-0d18b3029e9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770613270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2770613270
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3956675859
Short name T110
Test name
Test status
Simulation time 52244726078 ps
CPU time 172.73 seconds
Started Jul 23 06:50:22 PM PDT 24
Finished Jul 23 06:53:17 PM PDT 24
Peak memory 206668 kb
Host smart-3004e6b0-e8f4-40a5-bdec-3390d093b920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956675859 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3956675859
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1535859862
Short name T59
Test name
Test status
Simulation time 76310765732 ps
CPU time 601.85 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 07:00:50 PM PDT 24
Peak memory 212752 kb
Host smart-1d76a078-a919-4bae-8d3d-e5d50e60f958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535859862 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1535859862
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2348284627
Short name T176
Test name
Test status
Simulation time 6854189616 ps
CPU time 10.1 seconds
Started Jul 23 06:50:31 PM PDT 24
Finished Jul 23 06:50:42 PM PDT 24
Peak memory 191840 kb
Host smart-dda25ace-13fc-48fb-bd1c-3c49c8e9b078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348284627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2348284627
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.550115662
Short name T79
Test name
Test status
Simulation time 342119190193 ps
CPU time 239.84 seconds
Started Jul 23 06:50:33 PM PDT 24
Finished Jul 23 06:54:34 PM PDT 24
Peak memory 198184 kb
Host smart-43d077ec-ab87-429b-a2f1-215db1791d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550115662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.550115662
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.504271658
Short name T86
Test name
Test status
Simulation time 277206566617 ps
CPU time 107.34 seconds
Started Jul 23 06:50:33 PM PDT 24
Finished Jul 23 06:52:22 PM PDT 24
Peak memory 198220 kb
Host smart-281b6494-ccc2-481c-821d-a6084afc094d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504271658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.504271658
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3101209708
Short name T118
Test name
Test status
Simulation time 195729644226 ps
CPU time 133.3 seconds
Started Jul 23 06:50:21 PM PDT 24
Finished Jul 23 06:52:35 PM PDT 24
Peak memory 191900 kb
Host smart-4b16f725-01ec-4418-a119-391ca9799552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101209708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3101209708
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1038512686
Short name T43
Test name
Test status
Simulation time 22693549907 ps
CPU time 117.8 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 06:52:50 PM PDT 24
Peak memory 214028 kb
Host smart-44eb2a41-ff15-4056-863b-83c5e2295268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038512686 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1038512686
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1222935898
Short name T180
Test name
Test status
Simulation time 88621327219 ps
CPU time 139.58 seconds
Started Jul 23 06:50:21 PM PDT 24
Finished Jul 23 06:52:42 PM PDT 24
Peak memory 198212 kb
Host smart-caffd061-d1fc-4f12-b187-90edfcd14fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222935898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1222935898
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1788645511
Short name T42
Test name
Test status
Simulation time 27455749831 ps
CPU time 113.42 seconds
Started Jul 23 06:50:27 PM PDT 24
Finished Jul 23 06:52:22 PM PDT 24
Peak memory 206716 kb
Host smart-618ddea3-4460-4e04-b48d-35808f5c8f6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788645511 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1788645511
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2186385473
Short name T101
Test name
Test status
Simulation time 23615516440 ps
CPU time 58.78 seconds
Started Jul 23 06:50:31 PM PDT 24
Finished Jul 23 06:51:31 PM PDT 24
Peak memory 214196 kb
Host smart-e33aa234-c60c-44c3-97ff-9e07768ca370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186385473 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2186385473
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.853326594
Short name T111
Test name
Test status
Simulation time 266928481512 ps
CPU time 356.77 seconds
Started Jul 23 06:50:35 PM PDT 24
Finished Jul 23 06:56:33 PM PDT 24
Peak memory 192168 kb
Host smart-cb464c70-c397-4306-baeb-86fbce174814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853326594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.853326594
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.728464256
Short name T138
Test name
Test status
Simulation time 294085417290 ps
CPU time 88.35 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 06:52:16 PM PDT 24
Peak memory 184432 kb
Host smart-80792b14-c4e7-4675-9b78-b4dafc760538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728464256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.728464256
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.847890285
Short name T61
Test name
Test status
Simulation time 215572007532 ps
CPU time 724.41 seconds
Started Jul 23 06:50:25 PM PDT 24
Finished Jul 23 07:02:32 PM PDT 24
Peak memory 211340 kb
Host smart-e3c85fe7-0030-47d8-a624-7a9d6ac192af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847890285 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.847890285
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.4217322700
Short name T140
Test name
Test status
Simulation time 149131808878 ps
CPU time 261.08 seconds
Started Jul 23 06:50:42 PM PDT 24
Finished Jul 23 06:55:04 PM PDT 24
Peak memory 209584 kb
Host smart-9fdb7b42-24cf-495c-9245-1120b87ff78d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217322700 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.4217322700
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2716534594
Short name T41
Test name
Test status
Simulation time 40189849321 ps
CPU time 162.09 seconds
Started Jul 23 06:50:21 PM PDT 24
Finished Jul 23 06:53:04 PM PDT 24
Peak memory 198508 kb
Host smart-e0a66ec2-08a1-43ba-af64-b3bb3a9bc3c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716534594 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2716534594
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3140116617
Short name T136
Test name
Test status
Simulation time 140796721069 ps
CPU time 115.38 seconds
Started Jul 23 06:50:32 PM PDT 24
Finished Jul 23 06:52:29 PM PDT 24
Peak memory 192996 kb
Host smart-d7427d54-01f9-464b-bc1b-02e529520ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140116617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3140116617
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3163992244
Short name T150
Test name
Test status
Simulation time 178728728473 ps
CPU time 58.52 seconds
Started Jul 23 06:50:35 PM PDT 24
Finished Jul 23 06:51:35 PM PDT 24
Peak memory 191792 kb
Host smart-bb47f657-b398-4129-9f57-fcf3f255c730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163992244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3163992244
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.279689989
Short name T155
Test name
Test status
Simulation time 584930959 ps
CPU time 0.82 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:50:41 PM PDT 24
Peak memory 196504 kb
Host smart-a48df8f6-ccba-463e-b893-098b7e8e8fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279689989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.279689989
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2731392880
Short name T26
Test name
Test status
Simulation time 72466399750 ps
CPU time 26.76 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 06:51:14 PM PDT 24
Peak memory 192960 kb
Host smart-e3391e9e-82a7-4e95-8539-6f0bcf82bbd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731392880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2731392880
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.4249822121
Short name T122
Test name
Test status
Simulation time 333415137 ps
CPU time 1.07 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 06:50:48 PM PDT 24
Peak memory 196620 kb
Host smart-14fe47d5-63f2-46dc-b368-1793cf730149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249822121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.4249822121
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1257090107
Short name T51
Test name
Test status
Simulation time 54486351323 ps
CPU time 40.22 seconds
Started Jul 23 06:50:51 PM PDT 24
Finished Jul 23 06:51:34 PM PDT 24
Peak memory 192884 kb
Host smart-38297773-bdd2-4f46-98ac-6563df188e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257090107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1257090107
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3699518985
Short name T165
Test name
Test status
Simulation time 289864067585 ps
CPU time 30.99 seconds
Started Jul 23 06:50:22 PM PDT 24
Finished Jul 23 06:50:55 PM PDT 24
Peak memory 192880 kb
Host smart-2e111855-64fe-4435-a954-41e55f68fa6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699518985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3699518985
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.482923939
Short name T181
Test name
Test status
Simulation time 35087712099 ps
CPU time 55.36 seconds
Started Jul 23 06:50:25 PM PDT 24
Finished Jul 23 06:51:23 PM PDT 24
Peak memory 192892 kb
Host smart-a8495cf4-4f42-47d2-9d68-018c2fde1850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482923939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.482923939
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.4036909058
Short name T23
Test name
Test status
Simulation time 457560444 ps
CPU time 0.66 seconds
Started Jul 23 06:50:48 PM PDT 24
Finished Jul 23 06:50:51 PM PDT 24
Peak memory 196564 kb
Host smart-aa4ddcec-dbcb-4a09-99ca-8a20ca7b9022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036909058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4036909058
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1157348410
Short name T141
Test name
Test status
Simulation time 274725092383 ps
CPU time 361.16 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 06:56:49 PM PDT 24
Peak memory 193080 kb
Host smart-a0dfa2ea-b4c1-4f8a-884b-d60bc91ee6b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157348410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1157348410
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.535526828
Short name T159
Test name
Test status
Simulation time 570879833 ps
CPU time 0.78 seconds
Started Jul 23 06:50:23 PM PDT 24
Finished Jul 23 06:50:25 PM PDT 24
Peak memory 196580 kb
Host smart-418e321d-6403-4391-8200-ae62aeb871c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535526828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.535526828
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2238104120
Short name T117
Test name
Test status
Simulation time 544892017 ps
CPU time 0.94 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:50:57 PM PDT 24
Peak memory 196548 kb
Host smart-767d7b14-246f-49b0-9039-d5a0c954ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238104120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2238104120
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2370433385
Short name T146
Test name
Test status
Simulation time 120365251446 ps
CPU time 38.73 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:51:35 PM PDT 24
Peak memory 192984 kb
Host smart-489538f8-544e-4068-9ffa-898091d13827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370433385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2370433385
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1302194746
Short name T96
Test name
Test status
Simulation time 59593445111 ps
CPU time 339.72 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:56:38 PM PDT 24
Peak memory 198900 kb
Host smart-12fd7ee0-98e3-4ea2-8452-fa44d97bbf06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302194746 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1302194746
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3681231085
Short name T56
Test name
Test status
Simulation time 588532005 ps
CPU time 1.42 seconds
Started Jul 23 06:50:23 PM PDT 24
Finished Jul 23 06:50:26 PM PDT 24
Peak memory 196692 kb
Host smart-7fc396f2-70d5-4574-bfb0-ca1d205a9f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681231085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3681231085
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.891887888
Short name T98
Test name
Test status
Simulation time 56122823421 ps
CPU time 207.85 seconds
Started Jul 23 06:50:26 PM PDT 24
Finished Jul 23 06:53:57 PM PDT 24
Peak memory 214380 kb
Host smart-11e54f91-0516-43e2-a61d-7b6668e49342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891887888 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.891887888
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2834225349
Short name T137
Test name
Test status
Simulation time 473542103 ps
CPU time 1.24 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 06:50:32 PM PDT 24
Peak memory 196576 kb
Host smart-691c17ad-0daf-42c0-808b-9392c3aeb26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834225349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2834225349
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.663981694
Short name T167
Test name
Test status
Simulation time 479610596 ps
CPU time 1.22 seconds
Started Jul 23 06:50:38 PM PDT 24
Finished Jul 23 06:50:40 PM PDT 24
Peak memory 196580 kb
Host smart-19f4730e-2484-4347-93bc-6c71f0654e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663981694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.663981694
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2315940822
Short name T169
Test name
Test status
Simulation time 392979964 ps
CPU time 0.78 seconds
Started Jul 23 06:50:34 PM PDT 24
Finished Jul 23 06:50:37 PM PDT 24
Peak memory 196648 kb
Host smart-9dfe034c-7a87-4440-9d80-9c24a78877b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315940822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2315940822
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2426331132
Short name T160
Test name
Test status
Simulation time 121887095390 ps
CPU time 45.74 seconds
Started Jul 23 06:50:43 PM PDT 24
Finished Jul 23 06:51:30 PM PDT 24
Peak memory 192992 kb
Host smart-029d34b0-7e4d-4baf-b572-b46a5d61e5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426331132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2426331132
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.755349337
Short name T1
Test name
Test status
Simulation time 354707392 ps
CPU time 0.85 seconds
Started Jul 23 06:50:47 PM PDT 24
Finished Jul 23 06:50:50 PM PDT 24
Peak memory 196552 kb
Host smart-f7ad11c6-d567-44b0-aa86-47d62575ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755349337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.755349337
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2229809499
Short name T147
Test name
Test status
Simulation time 224588779321 ps
CPU time 316.44 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 06:56:02 PM PDT 24
Peak memory 198208 kb
Host smart-19e8d07f-e82a-40db-a569-5063cdde9c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229809499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2229809499
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3890895954
Short name T161
Test name
Test status
Simulation time 293166383884 ps
CPU time 365.85 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 06:56:37 PM PDT 24
Peak memory 192988 kb
Host smart-83962f22-e65c-411c-b0f1-d749e01682ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890895954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3890895954
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2938209336
Short name T163
Test name
Test status
Simulation time 422089233 ps
CPU time 0.67 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:27 PM PDT 24
Peak memory 196448 kb
Host smart-6e0f408f-256c-4ee3-b478-7aa0584a7266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938209336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2938209336
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2419315906
Short name T27
Test name
Test status
Simulation time 21231643129 ps
CPU time 212.92 seconds
Started Jul 23 06:50:31 PM PDT 24
Finished Jul 23 06:54:06 PM PDT 24
Peak memory 206676 kb
Host smart-fe9944a1-8777-424e-865a-5fb55ae9cac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419315906 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2419315906
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2705130371
Short name T114
Test name
Test status
Simulation time 50207667370 ps
CPU time 109.86 seconds
Started Jul 23 06:50:40 PM PDT 24
Finished Jul 23 06:52:31 PM PDT 24
Peak memory 198476 kb
Host smart-200e4865-1cce-4b78-8aff-4785bfea5205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705130371 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2705130371
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3954397390
Short name T121
Test name
Test status
Simulation time 567355604 ps
CPU time 1.05 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 06:50:53 PM PDT 24
Peak memory 196628 kb
Host smart-d10fb0cf-00c4-4777-b2ad-e8bce4b3e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954397390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3954397390
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1084118431
Short name T151
Test name
Test status
Simulation time 18406981738 ps
CPU time 6.85 seconds
Started Jul 23 06:50:25 PM PDT 24
Finished Jul 23 06:50:35 PM PDT 24
Peak memory 192892 kb
Host smart-a11deefd-af61-4900-8437-231167842a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084118431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1084118431
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1550252335
Short name T145
Test name
Test status
Simulation time 68650278681 ps
CPU time 95.08 seconds
Started Jul 23 06:50:26 PM PDT 24
Finished Jul 23 06:52:04 PM PDT 24
Peak memory 192820 kb
Host smart-1687c765-1b7d-4178-96ae-0cd1cbb2b1bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550252335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1550252335
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1323865985
Short name T168
Test name
Test status
Simulation time 539990137 ps
CPU time 1.3 seconds
Started Jul 23 06:50:36 PM PDT 24
Finished Jul 23 06:50:39 PM PDT 24
Peak memory 196596 kb
Host smart-dabf8b10-dc22-4552-b04d-1be130083ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323865985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1323865985
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1198311003
Short name T54
Test name
Test status
Simulation time 396351748 ps
CPU time 0.92 seconds
Started Jul 23 06:50:30 PM PDT 24
Finished Jul 23 06:50:33 PM PDT 24
Peak memory 196652 kb
Host smart-81b33342-d982-4614-94d3-bbadd507ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198311003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1198311003
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1651561466
Short name T154
Test name
Test status
Simulation time 496358220 ps
CPU time 1.29 seconds
Started Jul 23 06:50:13 PM PDT 24
Finished Jul 23 06:50:15 PM PDT 24
Peak memory 196576 kb
Host smart-9ff2244b-8b62-4ef2-b71c-4f03c6e87bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651561466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1651561466
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2894539695
Short name T124
Test name
Test status
Simulation time 564585836 ps
CPU time 1.42 seconds
Started Jul 23 06:50:33 PM PDT 24
Finished Jul 23 06:50:37 PM PDT 24
Peak memory 196624 kb
Host smart-3b2ffbf1-c650-4771-a731-d79f6b739d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894539695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2894539695
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3970647682
Short name T149
Test name
Test status
Simulation time 119362868800 ps
CPU time 191.96 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:53:53 PM PDT 24
Peak memory 191900 kb
Host smart-3217a2e9-e36d-47a7-9598-2899d348d4c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970647682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3970647682
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2750455168
Short name T116
Test name
Test status
Simulation time 569172835 ps
CPU time 1.43 seconds
Started Jul 23 06:50:41 PM PDT 24
Finished Jul 23 06:50:44 PM PDT 24
Peak memory 196580 kb
Host smart-d654ed00-364d-4d67-8fbf-03b0d1164c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750455168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2750455168
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1992693280
Short name T21
Test name
Test status
Simulation time 102692681529 ps
CPU time 41.05 seconds
Started Jul 23 06:50:48 PM PDT 24
Finished Jul 23 06:51:32 PM PDT 24
Peak memory 192968 kb
Host smart-4fa85237-7d92-46d6-8b01-0a9d04057461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992693280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1992693280
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1332310280
Short name T152
Test name
Test status
Simulation time 431547192 ps
CPU time 0.71 seconds
Started Jul 23 06:50:50 PM PDT 24
Finished Jul 23 06:50:54 PM PDT 24
Peak memory 196600 kb
Host smart-abf0afe4-44f8-43e7-ae9f-e3ebfa056f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332310280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1332310280
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.360460127
Short name T143
Test name
Test status
Simulation time 506635988 ps
CPU time 0.78 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:51:00 PM PDT 24
Peak memory 196604 kb
Host smart-0ca9a464-524a-4a10-9574-85ac232a5906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360460127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.360460127
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2323340640
Short name T174
Test name
Test status
Simulation time 28891170988 ps
CPU time 318.26 seconds
Started Jul 23 06:50:20 PM PDT 24
Finished Jul 23 06:55:40 PM PDT 24
Peak memory 214040 kb
Host smart-af1a44a9-04cc-40a6-a246-cfc93017d912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323340640 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2323340640
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4181506264
Short name T132
Test name
Test status
Simulation time 481085349 ps
CPU time 1.32 seconds
Started Jul 23 06:50:18 PM PDT 24
Finished Jul 23 06:50:20 PM PDT 24
Peak memory 196524 kb
Host smart-2fb9f606-fac2-497e-b738-7b1aa6c19a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181506264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4181506264
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2809364013
Short name T5
Test name
Test status
Simulation time 531583536 ps
CPU time 1.41 seconds
Started Jul 23 06:50:22 PM PDT 24
Finished Jul 23 06:50:25 PM PDT 24
Peak memory 196620 kb
Host smart-1bef554f-0568-4165-8b72-bb174e638691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809364013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2809364013
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3606805724
Short name T57
Test name
Test status
Simulation time 73386087110 ps
CPU time 55.8 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 06:51:27 PM PDT 24
Peak memory 191972 kb
Host smart-d3d1b73f-9390-4ab1-a6a0-e4edaf615a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606805724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3606805724
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.814651928
Short name T99
Test name
Test status
Simulation time 53925820410 ps
CPU time 264.39 seconds
Started Jul 23 06:50:36 PM PDT 24
Finished Jul 23 06:55:02 PM PDT 24
Peak memory 213964 kb
Host smart-d22f29c6-84d6-407b-a09e-1c063f6400ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814651928 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.814651928
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3596866734
Short name T133
Test name
Test status
Simulation time 543746637 ps
CPU time 0.75 seconds
Started Jul 23 06:50:40 PM PDT 24
Finished Jul 23 06:50:43 PM PDT 24
Peak memory 196516 kb
Host smart-89c56795-1eee-4048-8905-f502a884eb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596866734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3596866734
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2350859546
Short name T170
Test name
Test status
Simulation time 453127678 ps
CPU time 1.24 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 06:50:48 PM PDT 24
Peak memory 196584 kb
Host smart-8e1207ab-ee2a-48bf-aeb3-4392b1bb4a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350859546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2350859546
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3013347076
Short name T177
Test name
Test status
Simulation time 47480034297 ps
CPU time 373.14 seconds
Started Jul 23 06:50:43 PM PDT 24
Finished Jul 23 06:56:57 PM PDT 24
Peak memory 206728 kb
Host smart-2272a0df-e9e0-4a61-b3cc-761f84afb0a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013347076 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3013347076
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2643445550
Short name T182
Test name
Test status
Simulation time 441682297 ps
CPU time 1.22 seconds
Started Jul 23 06:50:31 PM PDT 24
Finished Jul 23 06:50:34 PM PDT 24
Peak memory 196484 kb
Host smart-ecc510e1-6c65-41a6-8d4b-9ac02ef812b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643445550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2643445550
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2389496915
Short name T183
Test name
Test status
Simulation time 620401597 ps
CPU time 0.74 seconds
Started Jul 23 06:50:30 PM PDT 24
Finished Jul 23 06:50:32 PM PDT 24
Peak memory 196536 kb
Host smart-7ef034e2-6b2d-4892-a613-b12c6752ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389496915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2389496915
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1284026269
Short name T173
Test name
Test status
Simulation time 430398119 ps
CPU time 0.89 seconds
Started Jul 23 06:50:37 PM PDT 24
Finished Jul 23 06:50:39 PM PDT 24
Peak memory 196612 kb
Host smart-633e8c26-d85f-4951-ac74-66e79b856c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284026269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1284026269
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3714236410
Short name T104
Test name
Test status
Simulation time 22062141831 ps
CPU time 176.27 seconds
Started Jul 23 06:50:34 PM PDT 24
Finished Jul 23 06:53:32 PM PDT 24
Peak memory 206704 kb
Host smart-1fa4ece0-29b4-4798-9805-bfe681b4e110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714236410 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3714236410
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.522379474
Short name T196
Test name
Test status
Simulation time 4319828827 ps
CPU time 2.42 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:02 PM PDT 24
Peak memory 198368 kb
Host smart-b1451f4f-d78b-42a7-be22-0484d4a30039
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522379474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.522379474
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1103747264
Short name T108
Test name
Test status
Simulation time 457508878 ps
CPU time 0.62 seconds
Started Jul 23 06:50:16 PM PDT 24
Finished Jul 23 06:50:18 PM PDT 24
Peak memory 196572 kb
Host smart-c2f8518e-6cde-4846-89a6-32b87e53b496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103747264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1103747264
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3225748714
Short name T179
Test name
Test status
Simulation time 459003670 ps
CPU time 0.78 seconds
Started Jul 23 06:50:30 PM PDT 24
Finished Jul 23 06:50:32 PM PDT 24
Peak memory 196640 kb
Host smart-3380c794-18df-4398-8a3b-e12d09ab260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225748714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3225748714
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3841948832
Short name T112
Test name
Test status
Simulation time 222083249408 ps
CPU time 175.2 seconds
Started Jul 23 06:50:28 PM PDT 24
Finished Jul 23 06:53:25 PM PDT 24
Peak memory 198204 kb
Host smart-1a9d3967-2d25-430e-86cf-b794242bae2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841948832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3841948832
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3095015462
Short name T164
Test name
Test status
Simulation time 570842156 ps
CPU time 1.48 seconds
Started Jul 23 06:50:32 PM PDT 24
Finished Jul 23 06:50:35 PM PDT 24
Peak memory 196584 kb
Host smart-0608c42d-9c23-4583-8338-d84cf5da16c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095015462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3095015462
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2482140532
Short name T29
Test name
Test status
Simulation time 200670170849 ps
CPU time 116.33 seconds
Started Jul 23 06:50:33 PM PDT 24
Finished Jul 23 06:52:31 PM PDT 24
Peak memory 213956 kb
Host smart-5c85ee6f-ae57-4009-85ca-a21485e38861
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482140532 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2482140532
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2127882385
Short name T178
Test name
Test status
Simulation time 504032567 ps
CPU time 0.72 seconds
Started Jul 23 06:50:37 PM PDT 24
Finished Jul 23 06:50:39 PM PDT 24
Peak memory 196572 kb
Host smart-c915d8ec-f537-4061-953e-258246cfb8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127882385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2127882385
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1307312421
Short name T187
Test name
Test status
Simulation time 430958422 ps
CPU time 0.74 seconds
Started Jul 23 06:50:38 PM PDT 24
Finished Jul 23 06:50:40 PM PDT 24
Peak memory 196572 kb
Host smart-37c436b1-d1b8-490d-a232-3d48a915eb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307312421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1307312421
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2830588539
Short name T175
Test name
Test status
Simulation time 526740679 ps
CPU time 1.13 seconds
Started Jul 23 06:50:51 PM PDT 24
Finished Jul 23 06:50:55 PM PDT 24
Peak memory 196548 kb
Host smart-e0b2ca56-37a8-42c6-b57c-5a79ebcc483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830588539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2830588539
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.907505304
Short name T157
Test name
Test status
Simulation time 618290817 ps
CPU time 0.67 seconds
Started Jul 23 06:50:47 PM PDT 24
Finished Jul 23 06:50:50 PM PDT 24
Peak memory 196756 kb
Host smart-0bc0cc8c-1d95-4401-ab40-a4808a1cfc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907505304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.907505304
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3539133470
Short name T190
Test name
Test status
Simulation time 126021321209 ps
CPU time 182.23 seconds
Started Jul 23 06:50:53 PM PDT 24
Finished Jul 23 06:53:59 PM PDT 24
Peak memory 191848 kb
Host smart-28e356a0-1661-43f4-a0f5-32c7a99e305c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539133470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3539133470
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1420471730
Short name T45
Test name
Test status
Simulation time 351860489 ps
CPU time 1.15 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:27 PM PDT 24
Peak memory 196584 kb
Host smart-2c07bb6a-685d-40de-8d26-569d5bbac334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420471730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1420471730
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3294802268
Short name T184
Test name
Test status
Simulation time 445760267 ps
CPU time 0.75 seconds
Started Jul 23 06:50:30 PM PDT 24
Finished Jul 23 06:50:32 PM PDT 24
Peak memory 196504 kb
Host smart-8157d653-5b0c-4a35-9276-d266592f8d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294802268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3294802268
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.316045637
Short name T3
Test name
Test status
Simulation time 518783142 ps
CPU time 0.66 seconds
Started Jul 23 06:50:33 PM PDT 24
Finished Jul 23 06:50:35 PM PDT 24
Peak memory 196556 kb
Host smart-e9f14df5-a3e8-4289-baca-b29b9103f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316045637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.316045637
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3950004030
Short name T47
Test name
Test status
Simulation time 583034309 ps
CPU time 1.36 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:28 PM PDT 24
Peak memory 196464 kb
Host smart-30fddeb6-433e-42eb-8cf7-2fd134a54893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950004030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3950004030
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.182539926
Short name T191
Test name
Test status
Simulation time 396230314 ps
CPU time 0.88 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 06:50:49 PM PDT 24
Peak memory 196528 kb
Host smart-8e913eb0-3efb-4cb7-b899-fc0773221bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182539926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.182539926
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1278088037
Short name T106
Test name
Test status
Simulation time 533655462 ps
CPU time 1.24 seconds
Started Jul 23 06:50:50 PM PDT 24
Finished Jul 23 06:50:54 PM PDT 24
Peak memory 196580 kb
Host smart-d7dc2cfe-3f81-4e5f-9205-084c70d5faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278088037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1278088037
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1593947789
Short name T78
Test name
Test status
Simulation time 40268887340 ps
CPU time 13.91 seconds
Started Jul 23 06:50:47 PM PDT 24
Finished Jul 23 06:51:04 PM PDT 24
Peak memory 191976 kb
Host smart-c5602a01-51aa-421d-95a9-db2f01047ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593947789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1593947789
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2345358019
Short name T85
Test name
Test status
Simulation time 556859223 ps
CPU time 0.79 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 06:50:52 PM PDT 24
Peak memory 196540 kb
Host smart-0cf4cb9c-62ef-4e24-95fb-b60aec5f72b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345358019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2345358019
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.683804649
Short name T166
Test name
Test status
Simulation time 441463849 ps
CPU time 0.65 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 06:50:48 PM PDT 24
Peak memory 196216 kb
Host smart-1b29af90-b4c7-4bf4-b1ed-66f115686a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683804649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.683804649
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2482430580
Short name T171
Test name
Test status
Simulation time 356124665 ps
CPU time 0.73 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:51:00 PM PDT 24
Peak memory 196548 kb
Host smart-d17b732c-36f0-40f6-ab1e-cdfacda43920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482430580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2482430580
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.305246568
Short name T188
Test name
Test status
Simulation time 415106318 ps
CPU time 1.16 seconds
Started Jul 23 06:50:22 PM PDT 24
Finished Jul 23 06:50:25 PM PDT 24
Peak memory 196192 kb
Host smart-2dcfb17c-2bc9-4395-80b8-388e8557f559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305246568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.305246568
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1476037567
Short name T186
Test name
Test status
Simulation time 568095111 ps
CPU time 0.91 seconds
Started Jul 23 06:50:25 PM PDT 24
Finished Jul 23 06:50:28 PM PDT 24
Peak memory 196532 kb
Host smart-28653dd4-dd7e-4d2a-8824-6d2b183497a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476037567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1476037567
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3373335014
Short name T73
Test name
Test status
Simulation time 410480016 ps
CPU time 1.03 seconds
Started Jul 23 06:30:23 PM PDT 24
Finished Jul 23 06:30:33 PM PDT 24
Peak memory 194852 kb
Host smart-1f092dd5-e1e4-4395-b930-3f0d978beef3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373335014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3373335014
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2506789476
Short name T415
Test name
Test status
Simulation time 13671999389 ps
CPU time 8.81 seconds
Started Jul 23 06:30:24 PM PDT 24
Finished Jul 23 06:30:41 PM PDT 24
Peak memory 192696 kb
Host smart-1778ce13-4a4b-4d16-845d-4251329b9312
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506789476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2506789476
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.144652498
Short name T405
Test name
Test status
Simulation time 631691424 ps
CPU time 1.51 seconds
Started Jul 23 06:30:28 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 193452 kb
Host smart-05d39f56-6285-48e3-90e4-21b327560134
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144652498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.144652498
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2596346548
Short name T408
Test name
Test status
Simulation time 471887935 ps
CPU time 1.31 seconds
Started Jul 23 06:30:28 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 196352 kb
Host smart-e81918d5-722b-4a8b-9c9e-ae97971957ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596346548 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2596346548
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4120854031
Short name T342
Test name
Test status
Simulation time 352292741 ps
CPU time 0.71 seconds
Started Jul 23 06:30:23 PM PDT 24
Finished Jul 23 06:30:33 PM PDT 24
Peak memory 193452 kb
Host smart-a0563f7b-42f4-452f-9730-63b02a2ee072
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120854031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4120854031
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2060882330
Short name T423
Test name
Test status
Simulation time 375568388 ps
CPU time 0.81 seconds
Started Jul 23 06:30:25 PM PDT 24
Finished Jul 23 06:30:34 PM PDT 24
Peak memory 184244 kb
Host smart-7db4cd2f-c8bf-4e81-9eb2-8f40f2825f07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060882330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2060882330
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.119378255
Short name T326
Test name
Test status
Simulation time 278498831 ps
CPU time 0.94 seconds
Started Jul 23 06:30:31 PM PDT 24
Finished Jul 23 06:30:37 PM PDT 24
Peak memory 184164 kb
Host smart-ccc054d3-dd93-4a5f-8f0e-d4686240246d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119378255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.119378255
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1496198970
Short name T358
Test name
Test status
Simulation time 432573662 ps
CPU time 0.82 seconds
Started Jul 23 06:30:24 PM PDT 24
Finished Jul 23 06:30:33 PM PDT 24
Peak memory 184112 kb
Host smart-92489ba9-898a-4953-b013-975d7dad65cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496198970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1496198970
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2516952492
Short name T92
Test name
Test status
Simulation time 2786394051 ps
CPU time 1.66 seconds
Started Jul 23 06:30:31 PM PDT 24
Finished Jul 23 06:30:38 PM PDT 24
Peak memory 194988 kb
Host smart-966a3b89-ff92-4d48-9196-c08a84d1f3d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516952492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2516952492
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4178430391
Short name T341
Test name
Test status
Simulation time 472886247 ps
CPU time 2.19 seconds
Started Jul 23 06:30:25 PM PDT 24
Finished Jul 23 06:30:35 PM PDT 24
Peak memory 199004 kb
Host smart-23704e81-11f8-455d-a766-9b2bb063167a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178430391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.4178430391
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2997462448
Short name T419
Test name
Test status
Simulation time 4339575996 ps
CPU time 2.09 seconds
Started Jul 23 06:30:25 PM PDT 24
Finished Jul 23 06:30:35 PM PDT 24
Peak memory 198336 kb
Host smart-11044631-5246-400c-9eaa-a1734735867d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997462448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2997462448
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3388425135
Short name T76
Test name
Test status
Simulation time 484025687 ps
CPU time 1.47 seconds
Started Jul 23 06:30:31 PM PDT 24
Finished Jul 23 06:30:38 PM PDT 24
Peak memory 195184 kb
Host smart-4d0ae334-e9b5-408d-b15d-ed2e35258e1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388425135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3388425135
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.439185162
Short name T413
Test name
Test status
Simulation time 5900010447 ps
CPU time 5.27 seconds
Started Jul 23 06:30:28 PM PDT 24
Finished Jul 23 06:30:40 PM PDT 24
Peak memory 196820 kb
Host smart-5978fe5d-a21c-4f52-921e-77a468dbbf41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439185162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.439185162
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.474046224
Short name T77
Test name
Test status
Simulation time 1177636867 ps
CPU time 1.07 seconds
Started Jul 23 06:30:28 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 193748 kb
Host smart-8937fbf4-a367-4e0d-9cf5-fdcbb889ae2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474046224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.474046224
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4140385764
Short name T325
Test name
Test status
Simulation time 465976061 ps
CPU time 1.25 seconds
Started Jul 23 06:30:28 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 195628 kb
Host smart-1e1fe6f0-b17f-4e89-b7d0-cc724d90c3fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140385764 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.4140385764
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2539449508
Short name T332
Test name
Test status
Simulation time 322546386 ps
CPU time 1.05 seconds
Started Jul 23 06:30:27 PM PDT 24
Finished Jul 23 06:30:35 PM PDT 24
Peak memory 193448 kb
Host smart-ba57ce42-13c6-4623-a3b0-5aa312e5389d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539449508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2539449508
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4189377501
Short name T304
Test name
Test status
Simulation time 404376245 ps
CPU time 1.15 seconds
Started Jul 23 06:30:28 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 184240 kb
Host smart-ed5e2e9e-07b8-4922-953a-f70575b4b7be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189377501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4189377501
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3104877495
Short name T393
Test name
Test status
Simulation time 442867773 ps
CPU time 0.66 seconds
Started Jul 23 06:30:29 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 184116 kb
Host smart-ee67ac25-d4e9-4b9a-8d9a-979c5d157ce6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104877495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3104877495
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2067979583
Short name T309
Test name
Test status
Simulation time 448212713 ps
CPU time 0.61 seconds
Started Jul 23 06:30:28 PM PDT 24
Finished Jul 23 06:30:35 PM PDT 24
Peak memory 184020 kb
Host smart-548eaca5-fb4b-4417-a799-1adcc0faeecf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067979583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2067979583
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3570723947
Short name T315
Test name
Test status
Simulation time 1862264806 ps
CPU time 1.98 seconds
Started Jul 23 06:30:27 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 195396 kb
Host smart-741ab6ed-e75c-4bce-b15b-61562105b577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570723947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3570723947
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.403728834
Short name T307
Test name
Test status
Simulation time 697599057 ps
CPU time 1.58 seconds
Started Jul 23 06:30:27 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 199060 kb
Host smart-daedfe58-dd0e-40ee-9d2a-6bb0f21f2ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403728834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.403728834
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4073277292
Short name T389
Test name
Test status
Simulation time 7962751244 ps
CPU time 6.28 seconds
Started Jul 23 06:30:28 PM PDT 24
Finished Jul 23 06:30:41 PM PDT 24
Peak memory 198968 kb
Host smart-aa6e6b63-7a36-4b8c-83cf-3e677f4a1938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073277292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.4073277292
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2810741739
Short name T379
Test name
Test status
Simulation time 605591863 ps
CPU time 0.92 seconds
Started Jul 23 06:30:52 PM PDT 24
Finished Jul 23 06:30:58 PM PDT 24
Peak memory 196964 kb
Host smart-d7129699-f3ac-4e0c-8b20-1cc222ea860c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810741739 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2810741739
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1114937975
Short name T317
Test name
Test status
Simulation time 376320165 ps
CPU time 0.64 seconds
Started Jul 23 06:30:52 PM PDT 24
Finished Jul 23 06:30:58 PM PDT 24
Peak memory 192716 kb
Host smart-671499dd-d0d3-4f54-82d7-f49a0f40d184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114937975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1114937975
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1424741090
Short name T290
Test name
Test status
Simulation time 409663535 ps
CPU time 0.72 seconds
Started Jul 23 06:30:53 PM PDT 24
Finished Jul 23 06:30:59 PM PDT 24
Peak memory 184236 kb
Host smart-9bdb54e8-8a6f-48b5-a2d3-b7b552487caa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424741090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1424741090
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.493449224
Short name T383
Test name
Test status
Simulation time 1267196602 ps
CPU time 2.31 seconds
Started Jul 23 06:30:52 PM PDT 24
Finished Jul 23 06:31:00 PM PDT 24
Peak memory 193348 kb
Host smart-65a4d44f-9e89-4307-bfaf-5c79e8b4d4ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493449224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.493449224
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.313227259
Short name T318
Test name
Test status
Simulation time 359962332 ps
CPU time 1.83 seconds
Started Jul 23 06:30:51 PM PDT 24
Finished Jul 23 06:30:58 PM PDT 24
Peak memory 199056 kb
Host smart-e4deb78b-2e42-4d5a-84ab-9e107bf9edd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313227259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.313227259
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2286961625
Short name T308
Test name
Test status
Simulation time 4438508964 ps
CPU time 3.88 seconds
Started Jul 23 06:30:51 PM PDT 24
Finished Jul 23 06:31:00 PM PDT 24
Peak memory 198516 kb
Host smart-6d370c1e-c3ac-4de4-a366-29f5df97f7d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286961625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2286961625
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3390771130
Short name T365
Test name
Test status
Simulation time 322558182 ps
CPU time 0.77 seconds
Started Jul 23 06:30:56 PM PDT 24
Finished Jul 23 06:31:03 PM PDT 24
Peak memory 196476 kb
Host smart-6da90fba-f13f-4a02-a1bb-f3ae4114c8da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390771130 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3390771130
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1916370780
Short name T285
Test name
Test status
Simulation time 279345027 ps
CPU time 0.94 seconds
Started Jul 23 06:30:51 PM PDT 24
Finished Jul 23 06:30:57 PM PDT 24
Peak memory 184208 kb
Host smart-01fbc33a-c8c7-428b-a60a-368843a73f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916370780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1916370780
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.600827531
Short name T340
Test name
Test status
Simulation time 2601750378 ps
CPU time 2.38 seconds
Started Jul 23 06:30:59 PM PDT 24
Finished Jul 23 06:31:08 PM PDT 24
Peak memory 192732 kb
Host smart-b80a31f5-c50a-4c2f-bc0a-e2553eb8bffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600827531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.600827531
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1762322102
Short name T311
Test name
Test status
Simulation time 1021355320 ps
CPU time 2.21 seconds
Started Jul 23 06:30:52 PM PDT 24
Finished Jul 23 06:31:00 PM PDT 24
Peak memory 199076 kb
Host smart-d0613702-1c7c-40f2-99b2-db249df0be4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762322102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1762322102
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3068684505
Short name T380
Test name
Test status
Simulation time 9954215658 ps
CPU time 1.93 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 198912 kb
Host smart-be472322-7b87-4266-9852-60a7582682b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068684505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3068684505
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3814200201
Short name T351
Test name
Test status
Simulation time 405364407 ps
CPU time 0.72 seconds
Started Jul 23 06:30:57 PM PDT 24
Finished Jul 23 06:31:04 PM PDT 24
Peak memory 196384 kb
Host smart-94037a19-8f25-45b0-b10d-70f80630ddc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814200201 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3814200201
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1445167617
Short name T378
Test name
Test status
Simulation time 527012633 ps
CPU time 1.36 seconds
Started Jul 23 06:30:51 PM PDT 24
Finished Jul 23 06:30:58 PM PDT 24
Peak memory 192472 kb
Host smart-0e26486b-7073-4bc3-b410-114ed293416b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445167617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1445167617
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2744738895
Short name T291
Test name
Test status
Simulation time 285347675 ps
CPU time 0.76 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:00 PM PDT 24
Peak memory 184180 kb
Host smart-e30bf0b5-8317-4e63-a238-b9630e480c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744738895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2744738895
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.900174268
Short name T344
Test name
Test status
Simulation time 1194228336 ps
CPU time 3 seconds
Started Jul 23 06:30:50 PM PDT 24
Finished Jul 23 06:30:59 PM PDT 24
Peak memory 184392 kb
Host smart-7f8df572-45d1-4c91-ba6d-57677b69270f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900174268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.900174268
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1306732059
Short name T422
Test name
Test status
Simulation time 593183725 ps
CPU time 1.99 seconds
Started Jul 23 06:30:51 PM PDT 24
Finished Jul 23 06:30:58 PM PDT 24
Peak memory 199068 kb
Host smart-ab5ebbff-7a6c-4e4b-bff5-0dbc0c21fe07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306732059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1306732059
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.407331081
Short name T324
Test name
Test status
Simulation time 478721649 ps
CPU time 1.39 seconds
Started Jul 23 06:30:59 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 197252 kb
Host smart-72a18697-9997-4a72-86bb-02e27f5928de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407331081 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.407331081
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3270985882
Short name T425
Test name
Test status
Simulation time 350778282 ps
CPU time 1.02 seconds
Started Jul 23 06:30:53 PM PDT 24
Finished Jul 23 06:30:59 PM PDT 24
Peak memory 192452 kb
Host smart-9659a486-efe8-4c08-a737-54db866e4f1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270985882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3270985882
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3874449296
Short name T420
Test name
Test status
Simulation time 368553992 ps
CPU time 0.62 seconds
Started Jul 23 06:30:51 PM PDT 24
Finished Jul 23 06:30:57 PM PDT 24
Peak memory 184240 kb
Host smart-3e99cefc-ee0d-4cac-aeb3-492b2b3418ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874449296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3874449296
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3984861928
Short name T356
Test name
Test status
Simulation time 2232986799 ps
CPU time 1.74 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:02 PM PDT 24
Peak memory 194364 kb
Host smart-32eed8da-53f4-4cae-abe6-ded7979c3dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984861928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3984861928
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.50951443
Short name T283
Test name
Test status
Simulation time 473391658 ps
CPU time 2 seconds
Started Jul 23 06:30:52 PM PDT 24
Finished Jul 23 06:31:00 PM PDT 24
Peak memory 198936 kb
Host smart-15041103-6f78-427e-ace1-7e29fe5466e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50951443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.50951443
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1530632857
Short name T194
Test name
Test status
Simulation time 8212227402 ps
CPU time 4.35 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:04 PM PDT 24
Peak memory 198648 kb
Host smart-2f54150b-b0a6-47a8-a38f-8ad0f631fbf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530632857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1530632857
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2503553519
Short name T289
Test name
Test status
Simulation time 384857174 ps
CPU time 1 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:01 PM PDT 24
Peak memory 196712 kb
Host smart-47c9b41b-154d-4537-85a4-987908d579a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503553519 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2503553519
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1159709119
Short name T87
Test name
Test status
Simulation time 440027595 ps
CPU time 0.68 seconds
Started Jul 23 06:30:55 PM PDT 24
Finished Jul 23 06:31:02 PM PDT 24
Peak memory 193388 kb
Host smart-29bc36fb-4e02-4d71-897d-c2bb947263e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159709119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1159709119
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2352772825
Short name T345
Test name
Test status
Simulation time 389902134 ps
CPU time 1.15 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:01 PM PDT 24
Peak memory 184252 kb
Host smart-29bf5181-dd12-4336-961d-99c77f6ae1d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352772825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2352772825
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1084997193
Short name T328
Test name
Test status
Simulation time 2554121679 ps
CPU time 8.47 seconds
Started Jul 23 06:30:55 PM PDT 24
Finished Jul 23 06:31:10 PM PDT 24
Peak memory 195496 kb
Host smart-c9936580-2a29-42c1-aa37-5c686301cb96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084997193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1084997193
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1175678941
Short name T303
Test name
Test status
Simulation time 296425473 ps
CPU time 1.38 seconds
Started Jul 23 06:30:56 PM PDT 24
Finished Jul 23 06:31:04 PM PDT 24
Peak memory 198760 kb
Host smart-f50d80e9-0b22-4818-8b0f-75e6a2d247e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175678941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1175678941
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2264153739
Short name T330
Test name
Test status
Simulation time 8366715250 ps
CPU time 13.06 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:18 PM PDT 24
Peak memory 198696 kb
Host smart-0d9bc9fd-8ed5-4b6d-9405-1f0df68f6bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264153739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2264153739
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1357949605
Short name T362
Test name
Test status
Simulation time 581267093 ps
CPU time 1.06 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:05 PM PDT 24
Peak memory 198900 kb
Host smart-4d0f484c-a04b-429f-bceb-234bffaa82be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357949605 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1357949605
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.600640437
Short name T69
Test name
Test status
Simulation time 412153758 ps
CPU time 1.15 seconds
Started Jul 23 06:30:59 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 193868 kb
Host smart-c0a5877a-fc05-4155-842f-d026741abd94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600640437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.600640437
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.699589265
Short name T371
Test name
Test status
Simulation time 615294796 ps
CPU time 0.6 seconds
Started Jul 23 06:30:57 PM PDT 24
Finished Jul 23 06:31:04 PM PDT 24
Peak memory 184112 kb
Host smart-91776982-f105-4f02-950f-3e867d71cc93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699589265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.699589265
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1798464194
Short name T412
Test name
Test status
Simulation time 2414351712 ps
CPU time 3.52 seconds
Started Jul 23 06:30:59 PM PDT 24
Finished Jul 23 06:31:09 PM PDT 24
Peak memory 195528 kb
Host smart-78a3befe-01d4-484a-88c6-4e8e04a0695c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798464194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1798464194
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4229589051
Short name T357
Test name
Test status
Simulation time 928204156 ps
CPU time 2.63 seconds
Started Jul 23 06:30:50 PM PDT 24
Finished Jul 23 06:30:58 PM PDT 24
Peak memory 199028 kb
Host smart-350da396-cb8f-4629-9ded-f499bbfa83c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229589051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4229589051
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.64860004
Short name T333
Test name
Test status
Simulation time 8353188185 ps
CPU time 12.36 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:12 PM PDT 24
Peak memory 198856 kb
Host smart-36da7e02-f803-4b47-92d1-cb41294f35c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64860004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_
intg_err.64860004
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1784531295
Short name T355
Test name
Test status
Simulation time 460174274 ps
CPU time 1.32 seconds
Started Jul 23 06:30:59 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 196988 kb
Host smart-90fc538f-1d0c-4ff1-a485-842550fccc4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784531295 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1784531295
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.844367728
Short name T66
Test name
Test status
Simulation time 339063745 ps
CPU time 0.77 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:05 PM PDT 24
Peak memory 193460 kb
Host smart-64a70617-fbc5-424c-936f-892ba1c26c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844367728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.844367728
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3964346558
Short name T396
Test name
Test status
Simulation time 509578548 ps
CPU time 0.92 seconds
Started Jul 23 06:31:00 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 184188 kb
Host smart-61a93cb6-04df-4935-a72b-f07b9806faed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964346558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3964346558
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.200716710
Short name T93
Test name
Test status
Simulation time 1276118604 ps
CPU time 1.46 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:06 PM PDT 24
Peak memory 193432 kb
Host smart-0bb387ea-8e24-4943-940f-649400b9d4d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200716710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.200716710
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1332348394
Short name T339
Test name
Test status
Simulation time 410667774 ps
CPU time 1.83 seconds
Started Jul 23 06:30:59 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 199228 kb
Host smart-0156649d-4e7a-4b4d-9b1c-8c2c13efb021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332348394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1332348394
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.374794867
Short name T33
Test name
Test status
Simulation time 8036651453 ps
CPU time 6.93 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:11 PM PDT 24
Peak memory 198804 kb
Host smart-94901d02-35e5-4253-9cfe-57e2965f7e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374794867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.374794867
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1395396095
Short name T347
Test name
Test status
Simulation time 348717584 ps
CPU time 0.83 seconds
Started Jul 23 06:30:57 PM PDT 24
Finished Jul 23 06:31:04 PM PDT 24
Peak memory 196544 kb
Host smart-afc7ad09-8666-4f29-9e76-cbcb12b55739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395396095 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1395396095
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3248739848
Short name T199
Test name
Test status
Simulation time 363698653 ps
CPU time 1.12 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:10 PM PDT 24
Peak memory 193412 kb
Host smart-f5af2095-bc02-4303-ab1d-d74a173659c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248739848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3248739848
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2823850340
Short name T292
Test name
Test status
Simulation time 318932667 ps
CPU time 0.74 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:06 PM PDT 24
Peak memory 184112 kb
Host smart-50f789d6-2a0b-4e48-abe7-c38286a53153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823850340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2823850340
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.226282930
Short name T360
Test name
Test status
Simulation time 1562248957 ps
CPU time 2.25 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 193384 kb
Host smart-16d324a9-ee77-4c42-bf61-cf0614cf11b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226282930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.226282930
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.739568589
Short name T391
Test name
Test status
Simulation time 414086773 ps
CPU time 2.57 seconds
Started Jul 23 06:30:57 PM PDT 24
Finished Jul 23 06:31:06 PM PDT 24
Peak memory 199032 kb
Host smart-0497c762-86c6-4613-b8ed-096d3ba7e3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739568589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.739568589
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3615352815
Short name T381
Test name
Test status
Simulation time 4391091135 ps
CPU time 6.92 seconds
Started Jul 23 06:31:00 PM PDT 24
Finished Jul 23 06:31:13 PM PDT 24
Peak memory 198624 kb
Host smart-a73bbfd9-813e-4387-a78b-d4f9f70514b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615352815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3615352815
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2684612823
Short name T353
Test name
Test status
Simulation time 523604036 ps
CPU time 0.82 seconds
Started Jul 23 06:30:56 PM PDT 24
Finished Jul 23 06:31:03 PM PDT 24
Peak memory 196444 kb
Host smart-b99988ae-b5b6-4326-833d-fb4793f168cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684612823 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2684612823
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2943847799
Short name T68
Test name
Test status
Simulation time 472753875 ps
CPU time 0.78 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:06 PM PDT 24
Peak memory 193464 kb
Host smart-dc09f966-9437-4f2f-9048-6d67da9f2b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943847799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2943847799
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3602316723
Short name T284
Test name
Test status
Simulation time 466798807 ps
CPU time 0.72 seconds
Started Jul 23 06:30:56 PM PDT 24
Finished Jul 23 06:31:03 PM PDT 24
Peak memory 184204 kb
Host smart-9323946a-a368-4b2e-be5b-9442d6c93ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602316723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3602316723
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1602030675
Short name T397
Test name
Test status
Simulation time 989960707 ps
CPU time 1.95 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:06 PM PDT 24
Peak memory 194088 kb
Host smart-78a32592-786d-44c4-ae7f-d09681213a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602030675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1602030675
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3206031029
Short name T287
Test name
Test status
Simulation time 473251578 ps
CPU time 2.74 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 199072 kb
Host smart-b7cbfc0e-a12e-4776-98ca-4f3080d8bf81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206031029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3206031029
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4229412004
Short name T195
Test name
Test status
Simulation time 8275744397 ps
CPU time 13.34 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:22 PM PDT 24
Peak memory 198664 kb
Host smart-e395b503-a10a-4a21-89c6-c1b355532c96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229412004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.4229412004
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.811364118
Short name T336
Test name
Test status
Simulation time 419573713 ps
CPU time 0.98 seconds
Started Jul 23 06:31:00 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 196168 kb
Host smart-443056c6-e48c-4d45-b162-124012fa9601
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811364118 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.811364118
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3446795395
Short name T72
Test name
Test status
Simulation time 418556828 ps
CPU time 0.77 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:05 PM PDT 24
Peak memory 194480 kb
Host smart-815987d2-b16e-4bfd-afbd-b51f8e884554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446795395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3446795395
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3384321372
Short name T319
Test name
Test status
Simulation time 414175650 ps
CPU time 0.72 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:05 PM PDT 24
Peak memory 193392 kb
Host smart-2a3c06c7-39b1-469b-8211-7ee3257bafed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384321372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3384321372
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3244216481
Short name T334
Test name
Test status
Simulation time 1236571437 ps
CPU time 1.01 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:11 PM PDT 24
Peak memory 194468 kb
Host smart-4050564a-ed15-4b58-aaa1-ea56478cbc7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244216481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3244216481
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2668162838
Short name T338
Test name
Test status
Simulation time 580109277 ps
CPU time 2.04 seconds
Started Jul 23 06:31:00 PM PDT 24
Finished Jul 23 06:31:08 PM PDT 24
Peak memory 199028 kb
Host smart-15101c90-ed77-4424-9bf2-48e983975106
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668162838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2668162838
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2815036545
Short name T402
Test name
Test status
Simulation time 8615119845 ps
CPU time 14.7 seconds
Started Jul 23 06:30:57 PM PDT 24
Finished Jul 23 06:31:18 PM PDT 24
Peak memory 198752 kb
Host smart-bbdf1d2d-e3ce-4584-b85c-773d8378487c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815036545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2815036545
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3363920398
Short name T409
Test name
Test status
Simulation time 884967460 ps
CPU time 0.86 seconds
Started Jul 23 06:30:30 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 194756 kb
Host smart-5b41344c-8581-44c9-8221-982fc4161353
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363920398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3363920398
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3959734032
Short name T297
Test name
Test status
Simulation time 7091379937 ps
CPU time 20.33 seconds
Started Jul 23 06:30:29 PM PDT 24
Finished Jul 23 06:30:55 PM PDT 24
Peak memory 196220 kb
Host smart-62484334-ba55-427a-91b4-c08c3b35cef2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959734032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3959734032
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1900412129
Short name T403
Test name
Test status
Simulation time 1148143735 ps
CPU time 2.43 seconds
Started Jul 23 06:30:29 PM PDT 24
Finished Jul 23 06:30:37 PM PDT 24
Peak memory 193824 kb
Host smart-f4033122-8bda-4326-938e-32b835066746
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900412129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1900412129
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2228848339
Short name T293
Test name
Test status
Simulation time 425309578 ps
CPU time 1.03 seconds
Started Jul 23 06:30:36 PM PDT 24
Finished Jul 23 06:30:39 PM PDT 24
Peak memory 197384 kb
Host smart-e7f57993-ac00-49f9-bf70-c2a404236e18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228848339 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2228848339
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1994682882
Short name T410
Test name
Test status
Simulation time 335222775 ps
CPU time 1 seconds
Started Jul 23 06:30:30 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 192504 kb
Host smart-6f31fec6-17ce-46ff-b023-9a82e6e89a34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994682882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1994682882
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.234932093
Short name T294
Test name
Test status
Simulation time 399715794 ps
CPU time 1.2 seconds
Started Jul 23 06:30:31 PM PDT 24
Finished Jul 23 06:30:37 PM PDT 24
Peak memory 193476 kb
Host smart-f304d5d7-b277-4986-816a-73b73d92c90a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234932093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.234932093
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1525888970
Short name T327
Test name
Test status
Simulation time 338242190 ps
CPU time 0.63 seconds
Started Jul 23 06:30:28 PM PDT 24
Finished Jul 23 06:30:35 PM PDT 24
Peak memory 184120 kb
Host smart-a05d3e0f-5d3e-4129-807e-addf5e1ce639
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525888970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1525888970
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3864315876
Short name T305
Test name
Test status
Simulation time 359281803 ps
CPU time 0.72 seconds
Started Jul 23 06:30:30 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 184104 kb
Host smart-f46769da-d4aa-4bd2-9824-533d697ae6fb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864315876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3864315876
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3688291502
Short name T404
Test name
Test status
Simulation time 2436373728 ps
CPU time 1.73 seconds
Started Jul 23 06:30:34 PM PDT 24
Finished Jul 23 06:30:39 PM PDT 24
Peak memory 184540 kb
Host smart-2be22a90-fa63-40e9-a8d9-0fd55d064928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688291502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3688291502
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.859159228
Short name T373
Test name
Test status
Simulation time 603095724 ps
CPU time 1.35 seconds
Started Jul 23 06:30:29 PM PDT 24
Finished Jul 23 06:30:36 PM PDT 24
Peak memory 198860 kb
Host smart-1c0fda38-5ef2-4f70-95b1-9614b07dbaa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859159228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.859159228
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2588219416
Short name T296
Test name
Test status
Simulation time 4496761728 ps
CPU time 4.42 seconds
Started Jul 23 06:30:27 PM PDT 24
Finished Jul 23 06:30:38 PM PDT 24
Peak memory 198504 kb
Host smart-2b0dc0a2-bf27-43b9-aa0d-29885b562736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588219416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2588219416
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1615337376
Short name T299
Test name
Test status
Simulation time 345919489 ps
CPU time 0.8 seconds
Started Jul 23 06:30:58 PM PDT 24
Finished Jul 23 06:31:06 PM PDT 24
Peak memory 184220 kb
Host smart-635539b0-b959-49e2-87bf-0c7de628a642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615337376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1615337376
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1301391035
Short name T406
Test name
Test status
Simulation time 307654625 ps
CPU time 1.01 seconds
Started Jul 23 06:31:01 PM PDT 24
Finished Jul 23 06:31:08 PM PDT 24
Peak memory 184208 kb
Host smart-df6609d0-0fca-4da4-8ff2-98cb86f53811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301391035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1301391035
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4078251968
Short name T306
Test name
Test status
Simulation time 473126089 ps
CPU time 0.77 seconds
Started Jul 23 06:31:00 PM PDT 24
Finished Jul 23 06:31:07 PM PDT 24
Peak memory 184204 kb
Host smart-52899649-62b1-4916-b20e-aff339c859d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078251968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4078251968
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3567228680
Short name T337
Test name
Test status
Simulation time 460715497 ps
CPU time 0.74 seconds
Started Jul 23 06:31:02 PM PDT 24
Finished Jul 23 06:31:09 PM PDT 24
Peak memory 193480 kb
Host smart-e4013092-dd75-4cdd-b61d-0f9613c9720d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567228680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3567228680
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3974988828
Short name T377
Test name
Test status
Simulation time 493602012 ps
CPU time 1.23 seconds
Started Jul 23 06:31:02 PM PDT 24
Finished Jul 23 06:31:09 PM PDT 24
Peak memory 184196 kb
Host smart-ffe4c7a0-3b1e-4a1b-8f2e-69735fa9b243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974988828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3974988828
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1368416990
Short name T414
Test name
Test status
Simulation time 316805685 ps
CPU time 0.77 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:12 PM PDT 24
Peak memory 193428 kb
Host smart-6c7939fa-2f51-4336-b932-9f426c14c482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368416990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1368416990
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2320147367
Short name T331
Test name
Test status
Simulation time 385190710 ps
CPU time 0.76 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:10 PM PDT 24
Peak memory 193436 kb
Host smart-99797369-0279-4a04-aee9-5db5ae56b78a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320147367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2320147367
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1062182277
Short name T286
Test name
Test status
Simulation time 366783912 ps
CPU time 0.8 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 184220 kb
Host smart-15bfc098-48d7-4e5c-ad42-6553ef5c07f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062182277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1062182277
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4042476592
Short name T385
Test name
Test status
Simulation time 515096036 ps
CPU time 0.68 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:09 PM PDT 24
Peak memory 184172 kb
Host smart-9761b351-f33f-434f-a2c3-1826c43bbb7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042476592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4042476592
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1968011098
Short name T368
Test name
Test status
Simulation time 496254003 ps
CPU time 0.82 seconds
Started Jul 23 06:31:02 PM PDT 24
Finished Jul 23 06:31:09 PM PDT 24
Peak memory 184204 kb
Host smart-c25f4102-24d3-4729-acaa-dafbadc9d2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968011098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1968011098
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2385984873
Short name T401
Test name
Test status
Simulation time 491340590 ps
CPU time 0.83 seconds
Started Jul 23 06:30:40 PM PDT 24
Finished Jul 23 06:30:43 PM PDT 24
Peak memory 184208 kb
Host smart-13261728-5c73-4622-8bf3-29af02f8d675
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385984873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2385984873
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2454615147
Short name T300
Test name
Test status
Simulation time 7134982213 ps
CPU time 16.3 seconds
Started Jul 23 06:30:40 PM PDT 24
Finished Jul 23 06:30:58 PM PDT 24
Peak memory 196540 kb
Host smart-baa0a9aa-51c4-4944-b039-43af838fa909
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454615147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2454615147
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1445487377
Short name T75
Test name
Test status
Simulation time 704967717 ps
CPU time 1.12 seconds
Started Jul 23 06:30:44 PM PDT 24
Finished Jul 23 06:30:47 PM PDT 24
Peak memory 193480 kb
Host smart-66dde9ba-3721-4095-bc21-5d748c507903
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445487377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1445487377
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4241430496
Short name T382
Test name
Test status
Simulation time 370445928 ps
CPU time 0.94 seconds
Started Jul 23 06:30:41 PM PDT 24
Finished Jul 23 06:30:44 PM PDT 24
Peak memory 196888 kb
Host smart-8e97339f-9b51-4416-bc2c-2a250a07bf3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241430496 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.4241430496
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.163255395
Short name T32
Test name
Test status
Simulation time 351075029 ps
CPU time 1.11 seconds
Started Jul 23 06:30:43 PM PDT 24
Finished Jul 23 06:30:45 PM PDT 24
Peak memory 192692 kb
Host smart-ba43446c-88cb-4820-9577-48b388d8612c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163255395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.163255395
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4197633437
Short name T301
Test name
Test status
Simulation time 371472894 ps
CPU time 1.09 seconds
Started Jul 23 06:30:35 PM PDT 24
Finished Jul 23 06:30:39 PM PDT 24
Peak memory 184208 kb
Host smart-3e582bd2-f725-404e-97f1-107c693257d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197633437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4197633437
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1155823794
Short name T369
Test name
Test status
Simulation time 502137987 ps
CPU time 1.19 seconds
Started Jul 23 06:30:39 PM PDT 24
Finished Jul 23 06:30:41 PM PDT 24
Peak memory 184120 kb
Host smart-3a7c59c8-6d54-405c-9b7c-2cd2faf04fa5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155823794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1155823794
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1539074198
Short name T322
Test name
Test status
Simulation time 350100500 ps
CPU time 0.76 seconds
Started Jul 23 06:30:43 PM PDT 24
Finished Jul 23 06:30:45 PM PDT 24
Peak memory 184336 kb
Host smart-546a72b7-961c-44ac-9772-41d08d05fbe7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539074198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1539074198
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.445677149
Short name T374
Test name
Test status
Simulation time 1223461815 ps
CPU time 4.12 seconds
Started Jul 23 06:30:39 PM PDT 24
Finished Jul 23 06:30:45 PM PDT 24
Peak memory 194268 kb
Host smart-119c3509-777c-441b-b6f0-828d4490d4d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445677149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.445677149
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3606250328
Short name T313
Test name
Test status
Simulation time 713346792 ps
CPU time 1.23 seconds
Started Jul 23 06:30:35 PM PDT 24
Finished Jul 23 06:30:39 PM PDT 24
Peak memory 198848 kb
Host smart-0c92330a-d656-49b3-b36b-8748612efa4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606250328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3606250328
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.4073760582
Short name T417
Test name
Test status
Simulation time 416355206 ps
CPU time 1.21 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:13 PM PDT 24
Peak memory 193424 kb
Host smart-ba5b6067-4f25-4dd9-ab94-ca6d952e225f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073760582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.4073760582
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3803350338
Short name T348
Test name
Test status
Simulation time 405929508 ps
CPU time 0.78 seconds
Started Jul 23 06:31:10 PM PDT 24
Finished Jul 23 06:31:21 PM PDT 24
Peak memory 184228 kb
Host smart-3e3e8af3-697b-40aa-a1c8-60218502e722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803350338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3803350338
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2971354152
Short name T310
Test name
Test status
Simulation time 411696253 ps
CPU time 1.19 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:13 PM PDT 24
Peak memory 184204 kb
Host smart-97d5fb0a-8a63-477a-96cc-6ecfaff012a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971354152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2971354152
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3257956687
Short name T400
Test name
Test status
Simulation time 313039238 ps
CPU time 0.69 seconds
Started Jul 23 06:31:02 PM PDT 24
Finished Jul 23 06:31:08 PM PDT 24
Peak memory 193448 kb
Host smart-feac607c-b82d-4535-a9f4-34eccfab930b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257956687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3257956687
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2332068645
Short name T314
Test name
Test status
Simulation time 321525071 ps
CPU time 0.98 seconds
Started Jul 23 06:31:07 PM PDT 24
Finished Jul 23 06:31:15 PM PDT 24
Peak memory 184240 kb
Host smart-21bbe781-7775-40dc-9835-f9a13065bbbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332068645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2332068645
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.502574135
Short name T346
Test name
Test status
Simulation time 455848918 ps
CPU time 1.11 seconds
Started Jul 23 06:31:02 PM PDT 24
Finished Jul 23 06:31:09 PM PDT 24
Peak memory 193364 kb
Host smart-c3213c81-ff6c-4ba8-b734-555395813957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502574135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.502574135
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1310607574
Short name T407
Test name
Test status
Simulation time 311091884 ps
CPU time 0.99 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 184204 kb
Host smart-27bbc9eb-f9db-4cf2-87a3-676db3b84011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310607574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1310607574
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3356913914
Short name T335
Test name
Test status
Simulation time 468692135 ps
CPU time 0.77 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 184240 kb
Host smart-f05cf151-41f3-4430-82d5-147e6a91a10a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356913914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3356913914
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4190678014
Short name T323
Test name
Test status
Simulation time 333504418 ps
CPU time 0.7 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:10 PM PDT 24
Peak memory 184204 kb
Host smart-9a0f3e04-6d4d-471d-8c49-b4d19f07172f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190678014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4190678014
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.94120251
Short name T384
Test name
Test status
Simulation time 288523695 ps
CPU time 0.94 seconds
Started Jul 23 06:31:01 PM PDT 24
Finished Jul 23 06:31:08 PM PDT 24
Peak memory 184212 kb
Host smart-9fc8a65b-6611-499c-b0bd-e4d7f653811c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94120251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.94120251
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2398526130
Short name T74
Test name
Test status
Simulation time 475694588 ps
CPU time 0.91 seconds
Started Jul 23 06:30:40 PM PDT 24
Finished Jul 23 06:30:43 PM PDT 24
Peak memory 195096 kb
Host smart-789661ec-fe68-4887-b11a-1509dc16eb2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398526130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2398526130
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3904458163
Short name T65
Test name
Test status
Simulation time 776840877 ps
CPU time 3.52 seconds
Started Jul 23 06:30:40 PM PDT 24
Finished Jul 23 06:30:45 PM PDT 24
Peak memory 192616 kb
Host smart-523bd75c-7861-4a8f-803b-583c10d606c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904458163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3904458163
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.99854755
Short name T361
Test name
Test status
Simulation time 628904439 ps
CPU time 1.1 seconds
Started Jul 23 06:30:39 PM PDT 24
Finished Jul 23 06:30:42 PM PDT 24
Peak memory 184216 kb
Host smart-06b5901b-0b6f-47dc-9a25-7e549ea0b816
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99854755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_
reset.99854755
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.714727376
Short name T424
Test name
Test status
Simulation time 452737539 ps
CPU time 1.41 seconds
Started Jul 23 06:30:45 PM PDT 24
Finished Jul 23 06:30:50 PM PDT 24
Peak memory 196952 kb
Host smart-543548ba-71d7-4018-b113-dc8f82e7e244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714727376 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.714727376
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3576146351
Short name T71
Test name
Test status
Simulation time 508723043 ps
CPU time 1 seconds
Started Jul 23 06:30:38 PM PDT 24
Finished Jul 23 06:30:40 PM PDT 24
Peak memory 193972 kb
Host smart-afe73a15-02bd-44ad-a0ec-578e86ced244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576146351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3576146351
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3706695674
Short name T295
Test name
Test status
Simulation time 451481930 ps
CPU time 0.68 seconds
Started Jul 23 06:30:39 PM PDT 24
Finished Jul 23 06:30:40 PM PDT 24
Peak memory 184232 kb
Host smart-3dc368a1-7602-4c18-84a3-5b3d39578751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706695674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3706695674
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2216322402
Short name T370
Test name
Test status
Simulation time 414595922 ps
CPU time 0.75 seconds
Started Jul 23 06:30:40 PM PDT 24
Finished Jul 23 06:30:42 PM PDT 24
Peak memory 184144 kb
Host smart-d975a036-ce71-410b-aacf-2ab58c8d3706
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216322402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2216322402
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.147950531
Short name T372
Test name
Test status
Simulation time 320386326 ps
CPU time 0.59 seconds
Started Jul 23 06:30:40 PM PDT 24
Finished Jul 23 06:30:43 PM PDT 24
Peak memory 184088 kb
Host smart-e29ae651-a9e9-4268-88a0-5aee5c4bc2ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147950531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.147950531
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2780754552
Short name T90
Test name
Test status
Simulation time 1208868609 ps
CPU time 2.17 seconds
Started Jul 23 06:30:40 PM PDT 24
Finished Jul 23 06:30:44 PM PDT 24
Peak memory 194196 kb
Host smart-c35b142a-c60f-40f6-ba74-d881f42dc7f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780754552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2780754552
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1121906159
Short name T359
Test name
Test status
Simulation time 577629085 ps
CPU time 2.47 seconds
Started Jul 23 06:30:40 PM PDT 24
Finished Jul 23 06:30:45 PM PDT 24
Peak memory 199048 kb
Host smart-98e66604-3c79-434c-b185-a1cc744dd065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121906159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1121906159
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2984209916
Short name T197
Test name
Test status
Simulation time 8447623533 ps
CPU time 12.09 seconds
Started Jul 23 06:30:44 PM PDT 24
Finished Jul 23 06:30:57 PM PDT 24
Peak memory 198948 kb
Host smart-07e0385e-19d6-4edf-91be-726069fe95ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984209916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2984209916
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1701164517
Short name T376
Test name
Test status
Simulation time 505216779 ps
CPU time 0.89 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:13 PM PDT 24
Peak memory 193448 kb
Host smart-8f625ae7-d295-46f1-88b9-e9979b84d493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701164517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1701164517
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2889251701
Short name T350
Test name
Test status
Simulation time 517574227 ps
CPU time 0.76 seconds
Started Jul 23 06:31:06 PM PDT 24
Finished Jul 23 06:31:14 PM PDT 24
Peak memory 193448 kb
Host smart-dbcdf108-fd44-4cc8-9403-90ca41efb213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889251701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2889251701
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1095773267
Short name T395
Test name
Test status
Simulation time 352746111 ps
CPU time 0.83 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:13 PM PDT 24
Peak memory 184128 kb
Host smart-472b9757-7e3d-40e2-a536-05d212ac0430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095773267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1095773267
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2540822189
Short name T302
Test name
Test status
Simulation time 328800176 ps
CPU time 0.77 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:10 PM PDT 24
Peak memory 184236 kb
Host smart-1ac19e30-51ab-42e7-8090-0b5fa82c9a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540822189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2540822189
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3890347858
Short name T320
Test name
Test status
Simulation time 407459088 ps
CPU time 0.73 seconds
Started Jul 23 06:31:05 PM PDT 24
Finished Jul 23 06:31:12 PM PDT 24
Peak memory 193444 kb
Host smart-f7d9a1a2-a999-40a4-a358-529eb8647d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890347858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3890347858
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2244025160
Short name T375
Test name
Test status
Simulation time 497696477 ps
CPU time 0.77 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:10 PM PDT 24
Peak memory 193452 kb
Host smart-e4abc16a-875e-48ea-8ce4-26c890dc339e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244025160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2244025160
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.2836008776
Short name T352
Test name
Test status
Simulation time 307873192 ps
CPU time 1.02 seconds
Started Jul 23 06:31:01 PM PDT 24
Finished Jul 23 06:31:08 PM PDT 24
Peak memory 193468 kb
Host smart-584614c6-52db-492c-9392-7f794e4ac528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836008776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.2836008776
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3780074974
Short name T329
Test name
Test status
Simulation time 340454318 ps
CPU time 0.69 seconds
Started Jul 23 06:31:03 PM PDT 24
Finished Jul 23 06:31:09 PM PDT 24
Peak memory 193424 kb
Host smart-18f1c64a-a694-4ae4-852c-bfbcbb91a4ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780074974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3780074974
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2752076443
Short name T399
Test name
Test status
Simulation time 352421440 ps
CPU time 0.79 seconds
Started Jul 23 06:31:02 PM PDT 24
Finished Jul 23 06:31:09 PM PDT 24
Peak memory 184244 kb
Host smart-36c21091-d0d8-4a29-bacb-198efefdeb30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752076443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2752076443
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.327400527
Short name T392
Test name
Test status
Simulation time 476811072 ps
CPU time 0.72 seconds
Started Jul 23 06:31:04 PM PDT 24
Finished Jul 23 06:31:11 PM PDT 24
Peak memory 184212 kb
Host smart-7fb53d62-1eb7-4def-8e29-b4de969ff7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327400527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.327400527
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1635271481
Short name T349
Test name
Test status
Simulation time 386582693 ps
CPU time 1.29 seconds
Started Jul 23 06:30:46 PM PDT 24
Finished Jul 23 06:30:51 PM PDT 24
Peak memory 197612 kb
Host smart-0682da6e-49cd-430f-8a89-d6721b61a889
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635271481 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1635271481
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.537370108
Short name T343
Test name
Test status
Simulation time 364099056 ps
CPU time 1.14 seconds
Started Jul 23 06:30:46 PM PDT 24
Finished Jul 23 06:30:50 PM PDT 24
Peak memory 193472 kb
Host smart-d72ef018-3405-41b3-859f-650932c20738
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537370108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.537370108
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.664242821
Short name T390
Test name
Test status
Simulation time 424058777 ps
CPU time 0.68 seconds
Started Jul 23 06:30:45 PM PDT 24
Finished Jul 23 06:30:49 PM PDT 24
Peak memory 184228 kb
Host smart-8f7b9353-e0bf-4153-8e8b-9efcc269247d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664242821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.664242821
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.615392195
Short name T89
Test name
Test status
Simulation time 2307256749 ps
CPU time 3.04 seconds
Started Jul 23 06:30:45 PM PDT 24
Finished Jul 23 06:30:50 PM PDT 24
Peak memory 195576 kb
Host smart-61f766f8-c72c-4616-83c1-bf1be8ddb089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615392195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.615392195
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3595614701
Short name T416
Test name
Test status
Simulation time 368954234 ps
CPU time 1.21 seconds
Started Jul 23 06:30:46 PM PDT 24
Finished Jul 23 06:30:50 PM PDT 24
Peak memory 199084 kb
Host smart-09d1cbbe-b532-4e6e-b994-19da865b9cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595614701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3595614701
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2184290621
Short name T418
Test name
Test status
Simulation time 8326433328 ps
CPU time 4.2 seconds
Started Jul 23 06:30:47 PM PDT 24
Finished Jul 23 06:30:55 PM PDT 24
Peak memory 198740 kb
Host smart-39ef8ad5-f228-438d-ab55-f90405c71433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184290621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2184290621
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2762186676
Short name T386
Test name
Test status
Simulation time 475116115 ps
CPU time 1.32 seconds
Started Jul 23 06:30:46 PM PDT 24
Finished Jul 23 06:30:51 PM PDT 24
Peak memory 196720 kb
Host smart-231b6afd-bdd8-46b5-ae53-72ad96bfa464
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762186676 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2762186676
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3091735984
Short name T67
Test name
Test status
Simulation time 502426164 ps
CPU time 1.21 seconds
Started Jul 23 06:30:49 PM PDT 24
Finished Jul 23 06:30:56 PM PDT 24
Peak memory 193464 kb
Host smart-3748eb14-a71c-4472-a05c-7ea886b0ed2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091735984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3091735984
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.705962986
Short name T388
Test name
Test status
Simulation time 454882120 ps
CPU time 0.86 seconds
Started Jul 23 06:30:46 PM PDT 24
Finished Jul 23 06:30:50 PM PDT 24
Peak memory 193432 kb
Host smart-d7457056-fc14-408f-bd00-d2f1289db81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705962986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.705962986
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.863415523
Short name T31
Test name
Test status
Simulation time 2601645731 ps
CPU time 1.57 seconds
Started Jul 23 06:30:45 PM PDT 24
Finished Jul 23 06:30:50 PM PDT 24
Peak memory 195724 kb
Host smart-0e186442-57d0-4be3-901d-73c5d47b2e7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863415523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.863415523
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.955408285
Short name T366
Test name
Test status
Simulation time 364545015 ps
CPU time 1.2 seconds
Started Jul 23 06:30:49 PM PDT 24
Finished Jul 23 06:30:56 PM PDT 24
Peak memory 198868 kb
Host smart-8de8bffa-feba-4757-a93b-d849ef4bf999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955408285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.955408285
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2339553267
Short name T35
Test name
Test status
Simulation time 4465822050 ps
CPU time 8.02 seconds
Started Jul 23 06:30:50 PM PDT 24
Finished Jul 23 06:31:04 PM PDT 24
Peak memory 198016 kb
Host smart-6bf4a91e-bbff-40ee-b3af-7ad125003025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339553267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2339553267
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.303525619
Short name T398
Test name
Test status
Simulation time 542670337 ps
CPU time 1.15 seconds
Started Jul 23 06:30:45 PM PDT 24
Finished Jul 23 06:30:49 PM PDT 24
Peak memory 198012 kb
Host smart-dea065c6-7e3d-49f5-aaec-042c3cff5b4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303525619 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.303525619
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2432998978
Short name T70
Test name
Test status
Simulation time 281069685 ps
CPU time 1 seconds
Started Jul 23 06:30:49 PM PDT 24
Finished Jul 23 06:30:55 PM PDT 24
Peak memory 192484 kb
Host smart-dc62e226-d312-4a91-8d82-d3e280cc0c09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432998978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2432998978
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1042054312
Short name T411
Test name
Test status
Simulation time 300840539 ps
CPU time 1.02 seconds
Started Jul 23 06:30:48 PM PDT 24
Finished Jul 23 06:30:54 PM PDT 24
Peak memory 193448 kb
Host smart-fbf21bb7-67d9-4619-a93f-cb04acbfee11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042054312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1042054312
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.802538640
Short name T91
Test name
Test status
Simulation time 1122619683 ps
CPU time 3.32 seconds
Started Jul 23 06:30:50 PM PDT 24
Finished Jul 23 06:30:58 PM PDT 24
Peak memory 193428 kb
Host smart-b4679c93-aa78-47b9-9de6-858f39304a44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802538640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.802538640
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.434801216
Short name T354
Test name
Test status
Simulation time 588095011 ps
CPU time 2.15 seconds
Started Jul 23 06:30:46 PM PDT 24
Finished Jul 23 06:30:53 PM PDT 24
Peak memory 199068 kb
Host smart-490f5e74-e7ae-48b4-84ee-8bce1ebba525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434801216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.434801216
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2937568637
Short name T298
Test name
Test status
Simulation time 4545431528 ps
CPU time 7.54 seconds
Started Jul 23 06:30:45 PM PDT 24
Finished Jul 23 06:30:56 PM PDT 24
Peak memory 198512 kb
Host smart-89f9fd31-deda-4dae-81ff-afb484920c13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937568637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2937568637
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1693239524
Short name T387
Test name
Test status
Simulation time 321526193 ps
CPU time 1.19 seconds
Started Jul 23 06:30:46 PM PDT 24
Finished Jul 23 06:30:51 PM PDT 24
Peak memory 197132 kb
Host smart-86eafe2f-14b0-4670-b517-6d1f3d0f829a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693239524 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1693239524
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.242487919
Short name T316
Test name
Test status
Simulation time 496207984 ps
CPU time 0.6 seconds
Started Jul 23 06:30:45 PM PDT 24
Finished Jul 23 06:30:49 PM PDT 24
Peak memory 193460 kb
Host smart-1a49572e-2312-44f2-ae66-c8b1c9ff25e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242487919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.242487919
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2175478808
Short name T312
Test name
Test status
Simulation time 467658707 ps
CPU time 0.74 seconds
Started Jul 23 06:30:50 PM PDT 24
Finished Jul 23 06:30:57 PM PDT 24
Peak memory 184240 kb
Host smart-9bdd1298-b716-48e9-a026-582de0b0e562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175478808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2175478808
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2695353972
Short name T88
Test name
Test status
Simulation time 1425695510 ps
CPU time 4.09 seconds
Started Jul 23 06:30:48 PM PDT 24
Finished Jul 23 06:30:57 PM PDT 24
Peak memory 193444 kb
Host smart-de1bf866-8b73-4629-bb11-4ce353640874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695353972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2695353972
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.188629497
Short name T288
Test name
Test status
Simulation time 410758372 ps
CPU time 1.5 seconds
Started Jul 23 06:30:49 PM PDT 24
Finished Jul 23 06:30:56 PM PDT 24
Peak memory 199108 kb
Host smart-97246d4b-a960-4474-b4e3-02a9b0c68efb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188629497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.188629497
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.338295239
Short name T394
Test name
Test status
Simulation time 3771602966 ps
CPU time 6.15 seconds
Started Jul 23 06:30:46 PM PDT 24
Finished Jul 23 06:30:56 PM PDT 24
Peak memory 198136 kb
Host smart-9563cff0-d15f-4977-9ae6-a09e6a82dcb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338295239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.338295239
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1388554821
Short name T36
Test name
Test status
Simulation time 863062915 ps
CPU time 1.41 seconds
Started Jul 23 06:30:55 PM PDT 24
Finished Jul 23 06:31:03 PM PDT 24
Peak memory 198792 kb
Host smart-bd0162de-c5e6-42da-be54-9b410fdcd73d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388554821 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1388554821
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.590418542
Short name T367
Test name
Test status
Simulation time 460253277 ps
CPU time 0.86 seconds
Started Jul 23 06:30:50 PM PDT 24
Finished Jul 23 06:30:57 PM PDT 24
Peak memory 193664 kb
Host smart-48d109b8-26b2-4356-b6c0-3d5660b14fe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590418542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.590418542
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3088093258
Short name T363
Test name
Test status
Simulation time 472761881 ps
CPU time 0.75 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:01 PM PDT 24
Peak memory 184208 kb
Host smart-ff813708-227f-47d7-8d64-70150149d0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088093258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3088093258
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3068668556
Short name T364
Test name
Test status
Simulation time 1927256238 ps
CPU time 4.75 seconds
Started Jul 23 06:30:54 PM PDT 24
Finished Jul 23 06:31:04 PM PDT 24
Peak memory 194356 kb
Host smart-cdd6b2eb-37ca-4836-985a-5b6794d13b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068668556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3068668556
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2858536337
Short name T421
Test name
Test status
Simulation time 640092396 ps
CPU time 2.31 seconds
Started Jul 23 06:30:46 PM PDT 24
Finished Jul 23 06:30:51 PM PDT 24
Peak memory 199020 kb
Host smart-81b5f46e-5f1d-4540-a323-c18cfeae932d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858536337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2858536337
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1139371409
Short name T321
Test name
Test status
Simulation time 4651361945 ps
CPU time 2.74 seconds
Started Jul 23 06:30:45 PM PDT 24
Finished Jul 23 06:30:51 PM PDT 24
Peak memory 198384 kb
Host smart-c6fecb3e-151f-4c4f-9830-e7629f752ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139371409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1139371409
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3337002034
Short name T221
Test name
Test status
Simulation time 31631155989 ps
CPU time 12.7 seconds
Started Jul 23 06:50:14 PM PDT 24
Finished Jul 23 06:50:28 PM PDT 24
Peak memory 196904 kb
Host smart-f63fb8bf-3fe2-4644-8322-0aec8d1715c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337002034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3337002034
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.575088186
Short name T208
Test name
Test status
Simulation time 380529368 ps
CPU time 1.12 seconds
Started Jul 23 06:50:13 PM PDT 24
Finished Jul 23 06:50:16 PM PDT 24
Peak memory 191780 kb
Host smart-4803f9bf-c9a2-4c0e-96ae-e1e2797d6429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575088186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.575088186
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.713726011
Short name T198
Test name
Test status
Simulation time 86099569540 ps
CPU time 64.96 seconds
Started Jul 23 06:50:19 PM PDT 24
Finished Jul 23 06:51:25 PM PDT 24
Peak memory 198224 kb
Host smart-88460c4a-f131-413b-86da-2265348164ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713726011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.713726011
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3579081064
Short name T44
Test name
Test status
Simulation time 41099850154 ps
CPU time 16.74 seconds
Started Jul 23 06:50:18 PM PDT 24
Finished Jul 23 06:50:36 PM PDT 24
Peak memory 191880 kb
Host smart-1ad6f66a-8d6c-4e25-8adb-42879d3e6972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579081064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3579081064
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2335677045
Short name T17
Test name
Test status
Simulation time 7548205028 ps
CPU time 8.77 seconds
Started Jul 23 06:50:14 PM PDT 24
Finished Jul 23 06:50:24 PM PDT 24
Peak memory 215820 kb
Host smart-1f43de66-5681-497d-ba0d-f55e1082eae0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335677045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2335677045
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3223307494
Short name T205
Test name
Test status
Simulation time 565036874 ps
CPU time 0.79 seconds
Started Jul 23 06:50:20 PM PDT 24
Finished Jul 23 06:50:22 PM PDT 24
Peak memory 196588 kb
Host smart-45340c16-7960-4708-8eb7-d36d6c8e2534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223307494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3223307494
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1580048826
Short name T211
Test name
Test status
Simulation time 39985337126 ps
CPU time 32.44 seconds
Started Jul 23 06:50:25 PM PDT 24
Finished Jul 23 06:51:00 PM PDT 24
Peak memory 191724 kb
Host smart-369cef4e-dba9-4ac8-b7ec-5abd577f2103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580048826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1580048826
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.238442302
Short name T278
Test name
Test status
Simulation time 493911709 ps
CPU time 0.71 seconds
Started Jul 23 06:50:25 PM PDT 24
Finished Jul 23 06:50:28 PM PDT 24
Peak memory 196388 kb
Host smart-971fbb32-61de-4ebc-aaed-ff88bc42dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238442302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.238442302
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3659095899
Short name T12
Test name
Test status
Simulation time 8520529384 ps
CPU time 12.96 seconds
Started Jul 23 06:50:22 PM PDT 24
Finished Jul 23 06:50:37 PM PDT 24
Peak memory 191904 kb
Host smart-c1eebe1a-ebb6-4d59-bce4-3a06537700bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659095899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3659095899
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.730928967
Short name T82
Test name
Test status
Simulation time 430837299 ps
CPU time 1.18 seconds
Started Jul 23 06:50:28 PM PDT 24
Finished Jul 23 06:50:31 PM PDT 24
Peak memory 196560 kb
Host smart-0bc94640-810f-4a80-bb28-f68b9161a05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730928967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.730928967
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1045733331
Short name T83
Test name
Test status
Simulation time 10349400575 ps
CPU time 103.83 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 06:52:15 PM PDT 24
Peak memory 206692 kb
Host smart-1c3031c2-e379-48f5-91ab-84f196622bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045733331 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1045733331
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.853974222
Short name T216
Test name
Test status
Simulation time 4352048059 ps
CPU time 7.22 seconds
Started Jul 23 06:50:25 PM PDT 24
Finished Jul 23 06:50:35 PM PDT 24
Peak memory 196792 kb
Host smart-5d629ffe-2f5d-4f03-9bac-9b3afeb7047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853974222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.853974222
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.147465289
Short name T247
Test name
Test status
Simulation time 447648659 ps
CPU time 1.2 seconds
Started Jul 23 06:50:26 PM PDT 24
Finished Jul 23 06:50:30 PM PDT 24
Peak memory 191704 kb
Host smart-13643c7e-4798-4132-b593-47221c47e98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147465289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.147465289
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.185989817
Short name T258
Test name
Test status
Simulation time 7889014939 ps
CPU time 11.29 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 06:50:42 PM PDT 24
Peak memory 191876 kb
Host smart-dc8781c5-3a61-4879-972f-99a508cb84b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185989817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.185989817
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1430608136
Short name T200
Test name
Test status
Simulation time 459592780 ps
CPU time 1.24 seconds
Started Jul 23 06:50:26 PM PDT 24
Finished Jul 23 06:50:29 PM PDT 24
Peak memory 191736 kb
Host smart-1e519ce2-61b3-4655-aa84-087bb62b493f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430608136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1430608136
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1328256990
Short name T281
Test name
Test status
Simulation time 25203054600 ps
CPU time 18.2 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 06:50:50 PM PDT 24
Peak memory 191904 kb
Host smart-21b0efe8-62e4-4241-aa76-42df083effb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328256990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1328256990
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.4276674351
Short name T253
Test name
Test status
Simulation time 619657704 ps
CPU time 0.71 seconds
Started Jul 23 06:50:33 PM PDT 24
Finished Jul 23 06:50:35 PM PDT 24
Peak memory 191776 kb
Host smart-cba6217f-0a92-4868-b0a9-ecfcad8d7b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276674351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4276674351
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3113687159
Short name T260
Test name
Test status
Simulation time 39439853529 ps
CPU time 26.3 seconds
Started Jul 23 06:50:34 PM PDT 24
Finished Jul 23 06:51:02 PM PDT 24
Peak memory 191800 kb
Host smart-10dc7d8d-e942-4524-bc68-2a734a34847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113687159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3113687159
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1042552249
Short name T277
Test name
Test status
Simulation time 469448527 ps
CPU time 0.73 seconds
Started Jul 23 06:50:28 PM PDT 24
Finished Jul 23 06:50:31 PM PDT 24
Peak memory 196584 kb
Host smart-8bf96511-58fa-42ff-bb83-0a61c5024c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042552249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1042552249
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2687370476
Short name T274
Test name
Test status
Simulation time 23839279020 ps
CPU time 7.45 seconds
Started Jul 23 06:50:32 PM PDT 24
Finished Jul 23 06:50:41 PM PDT 24
Peak memory 196640 kb
Host smart-d8b09cfc-220e-455d-a465-495f940e1b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687370476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2687370476
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2277206317
Short name T201
Test name
Test status
Simulation time 497282906 ps
CPU time 0.76 seconds
Started Jul 23 06:50:28 PM PDT 24
Finished Jul 23 06:50:31 PM PDT 24
Peak memory 196548 kb
Host smart-43653bbe-fa60-493c-81cc-6df3ff62b587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277206317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2277206317
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1852125413
Short name T172
Test name
Test status
Simulation time 389259828 ps
CPU time 0.88 seconds
Started Jul 23 06:50:36 PM PDT 24
Finished Jul 23 06:50:38 PM PDT 24
Peak memory 196464 kb
Host smart-c56bd11e-e3cb-4c14-8e1d-de6eef05d49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852125413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1852125413
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.202255779
Short name T246
Test name
Test status
Simulation time 39122410732 ps
CPU time 62.04 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 191872 kb
Host smart-ab97000b-ab6e-4791-b82b-2e80a77064b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202255779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.202255779
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3214934377
Short name T219
Test name
Test status
Simulation time 518778872 ps
CPU time 1.24 seconds
Started Jul 23 06:50:34 PM PDT 24
Finished Jul 23 06:50:37 PM PDT 24
Peak memory 196460 kb
Host smart-09d5b82f-5da9-4d0d-98a2-a55128f5721a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214934377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3214934377
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2786011783
Short name T227
Test name
Test status
Simulation time 22119097656 ps
CPU time 33.76 seconds
Started Jul 23 06:50:29 PM PDT 24
Finished Jul 23 06:51:05 PM PDT 24
Peak memory 191904 kb
Host smart-72f6f9c7-a338-419d-b94f-127fde0aab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786011783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2786011783
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1016170017
Short name T204
Test name
Test status
Simulation time 629627475 ps
CPU time 0.78 seconds
Started Jul 23 06:50:36 PM PDT 24
Finished Jul 23 06:50:39 PM PDT 24
Peak memory 191708 kb
Host smart-8a94847b-2e3b-4033-ac46-125dba7ffcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016170017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1016170017
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1432792572
Short name T210
Test name
Test status
Simulation time 21979438013 ps
CPU time 15.2 seconds
Started Jul 23 06:50:36 PM PDT 24
Finished Jul 23 06:50:53 PM PDT 24
Peak memory 191828 kb
Host smart-0d2ce518-4fe0-4ba9-9acf-89a52ba0c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432792572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1432792572
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2765347975
Short name T252
Test name
Test status
Simulation time 649267134 ps
CPU time 0.68 seconds
Started Jul 23 06:50:31 PM PDT 24
Finished Jul 23 06:50:33 PM PDT 24
Peak memory 191692 kb
Host smart-6adad37b-47e6-4d19-b7c2-313cf68972f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765347975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2765347975
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1692908067
Short name T243
Test name
Test status
Simulation time 3946817670 ps
CPU time 2.89 seconds
Started Jul 23 06:50:21 PM PDT 24
Finished Jul 23 06:50:25 PM PDT 24
Peak memory 191856 kb
Host smart-76779f1a-7c0b-49ff-8a22-ef12064a61dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692908067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1692908067
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2678547286
Short name T19
Test name
Test status
Simulation time 4381429068 ps
CPU time 2.41 seconds
Started Jul 23 06:50:22 PM PDT 24
Finished Jul 23 06:50:26 PM PDT 24
Peak memory 215788 kb
Host smart-9cbef404-0302-44ce-81e2-56b952ad9dc6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678547286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2678547286
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2964282315
Short name T203
Test name
Test status
Simulation time 463336047 ps
CPU time 1.11 seconds
Started Jul 23 06:50:23 PM PDT 24
Finished Jul 23 06:50:26 PM PDT 24
Peak memory 191564 kb
Host smart-40d9797a-3cd2-4a30-b501-cab049883d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964282315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2964282315
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3994052643
Short name T25
Test name
Test status
Simulation time 8119519656 ps
CPU time 2.25 seconds
Started Jul 23 06:50:28 PM PDT 24
Finished Jul 23 06:50:33 PM PDT 24
Peak memory 196876 kb
Host smart-cda3cb01-5582-407b-8767-40f0abd7a5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994052643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3994052643
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.524468716
Short name T80
Test name
Test status
Simulation time 390532102 ps
CPU time 0.81 seconds
Started Jul 23 06:50:28 PM PDT 24
Finished Jul 23 06:50:31 PM PDT 24
Peak memory 191864 kb
Host smart-a9fb1e4a-a1e6-4e00-9b52-d33f5575e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524468716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.524468716
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3893302264
Short name T46
Test name
Test status
Simulation time 499425513 ps
CPU time 1.22 seconds
Started Jul 23 06:50:30 PM PDT 24
Finished Jul 23 06:50:33 PM PDT 24
Peak memory 196528 kb
Host smart-d5f0b097-e36e-4522-860d-3752fed6a927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893302264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3893302264
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.258369366
Short name T270
Test name
Test status
Simulation time 18088112360 ps
CPU time 30.28 seconds
Started Jul 23 06:50:36 PM PDT 24
Finished Jul 23 06:51:08 PM PDT 24
Peak memory 191840 kb
Host smart-92b5d9ed-5173-4123-a429-fed678151d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258369366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.258369366
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3158729352
Short name T242
Test name
Test status
Simulation time 548256583 ps
CPU time 0.96 seconds
Started Jul 23 06:50:30 PM PDT 24
Finished Jul 23 06:50:33 PM PDT 24
Peak memory 191780 kb
Host smart-27e51078-21ba-44dd-9ed1-eac732c17937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158729352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3158729352
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1105114812
Short name T224
Test name
Test status
Simulation time 26628426137 ps
CPU time 29.95 seconds
Started Jul 23 06:50:36 PM PDT 24
Finished Jul 23 06:51:08 PM PDT 24
Peak memory 191892 kb
Host smart-8d138e87-fdda-4a05-af05-6ef980b6849e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105114812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1105114812
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4224566176
Short name T13
Test name
Test status
Simulation time 544037975 ps
CPU time 1.39 seconds
Started Jul 23 06:50:33 PM PDT 24
Finished Jul 23 06:50:36 PM PDT 24
Peak memory 196644 kb
Host smart-1204d51d-33ba-4203-bc87-c87cdd973d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224566176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4224566176
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.4110944534
Short name T232
Test name
Test status
Simulation time 24817612051 ps
CPU time 9.45 seconds
Started Jul 23 06:50:35 PM PDT 24
Finished Jul 23 06:50:46 PM PDT 24
Peak memory 191888 kb
Host smart-eca4d9d4-a47e-4fc5-be18-d198b9935b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110944534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.4110944534
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.694064776
Short name T234
Test name
Test status
Simulation time 505714897 ps
CPU time 0.64 seconds
Started Jul 23 06:50:35 PM PDT 24
Finished Jul 23 06:50:37 PM PDT 24
Peak memory 191672 kb
Host smart-835fbb7d-7964-4503-bb53-33ae00999b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694064776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.694064776
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1446188347
Short name T185
Test name
Test status
Simulation time 564046947 ps
CPU time 1.44 seconds
Started Jul 23 06:50:34 PM PDT 24
Finished Jul 23 06:50:37 PM PDT 24
Peak memory 196484 kb
Host smart-a5eb08d5-e1d1-4580-83e7-3c6a52e69f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446188347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1446188347
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.261230678
Short name T235
Test name
Test status
Simulation time 3604376215 ps
CPU time 1.95 seconds
Started Jul 23 06:50:35 PM PDT 24
Finished Jul 23 06:50:38 PM PDT 24
Peak memory 196620 kb
Host smart-e0825939-dcfa-4de5-9ae1-7019e000b206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261230678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.261230678
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2540863236
Short name T248
Test name
Test status
Simulation time 480479294 ps
CPU time 0.78 seconds
Started Jul 23 06:50:34 PM PDT 24
Finished Jul 23 06:50:37 PM PDT 24
Peak memory 191756 kb
Host smart-fde0d44b-fef1-4cf0-b77f-5d26eb9c5725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540863236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2540863236
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.91216737
Short name T230
Test name
Test status
Simulation time 19900210866 ps
CPU time 5.62 seconds
Started Jul 23 06:50:35 PM PDT 24
Finished Jul 23 06:50:42 PM PDT 24
Peak memory 191888 kb
Host smart-456069f9-8cd3-4e44-8381-b89194253af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91216737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.91216737
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1699295644
Short name T264
Test name
Test status
Simulation time 528917399 ps
CPU time 0.98 seconds
Started Jul 23 06:50:37 PM PDT 24
Finished Jul 23 06:50:39 PM PDT 24
Peak memory 191776 kb
Host smart-532961fc-ef0a-4356-9633-cc199cd9ffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699295644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1699295644
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1330183316
Short name T265
Test name
Test status
Simulation time 10273425529 ps
CPU time 4.35 seconds
Started Jul 23 06:50:34 PM PDT 24
Finished Jul 23 06:50:40 PM PDT 24
Peak memory 191900 kb
Host smart-9edef9c5-6474-4d86-a283-af01f0f880e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330183316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1330183316
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1985773254
Short name T249
Test name
Test status
Simulation time 439975934 ps
CPU time 1.17 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:50:41 PM PDT 24
Peak memory 191712 kb
Host smart-80348e07-bb9f-4a7b-86b9-f40f5babf6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985773254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1985773254
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3916465808
Short name T102
Test name
Test status
Simulation time 61636373196 ps
CPU time 123.82 seconds
Started Jul 23 06:50:32 PM PDT 24
Finished Jul 23 06:52:37 PM PDT 24
Peak memory 206648 kb
Host smart-0731b072-b747-4990-a93c-4c3b0a5f40b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916465808 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3916465808
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3712671715
Short name T267
Test name
Test status
Simulation time 1650942827 ps
CPU time 2.75 seconds
Started Jul 23 06:50:38 PM PDT 24
Finished Jul 23 06:50:42 PM PDT 24
Peak memory 191776 kb
Host smart-e3b45faf-6d3a-4b38-85c2-a9c60e91bb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712671715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3712671715
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1173621317
Short name T223
Test name
Test status
Simulation time 365484567 ps
CPU time 1.05 seconds
Started Jul 23 06:50:34 PM PDT 24
Finished Jul 23 06:50:37 PM PDT 24
Peak memory 191744 kb
Host smart-3ec036d1-edc8-406a-b991-58aea48737f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173621317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1173621317
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2135829096
Short name T55
Test name
Test status
Simulation time 61950123884 ps
CPU time 87.17 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:52:08 PM PDT 24
Peak memory 191896 kb
Host smart-23b6d54c-1635-487a-b7a4-1ab59825ba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135829096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2135829096
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2011675043
Short name T272
Test name
Test status
Simulation time 600924752 ps
CPU time 1.01 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:50:42 PM PDT 24
Peak memory 191752 kb
Host smart-c311babd-79a7-424e-8d0b-eade6b3d31a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011675043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2011675043
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3048247813
Short name T240
Test name
Test status
Simulation time 9591110916 ps
CPU time 2.16 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:50:43 PM PDT 24
Peak memory 191892 kb
Host smart-07acc6d4-78a8-46f0-998c-e6ab979a44ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048247813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3048247813
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.551788097
Short name T225
Test name
Test status
Simulation time 429433044 ps
CPU time 1.24 seconds
Started Jul 23 06:50:40 PM PDT 24
Finished Jul 23 06:50:43 PM PDT 24
Peak memory 191768 kb
Host smart-b404b603-4c4c-45b6-85c0-f38905d3a3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551788097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.551788097
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1742898259
Short name T49
Test name
Test status
Simulation time 61079684859 ps
CPU time 98.51 seconds
Started Jul 23 06:50:20 PM PDT 24
Finished Jul 23 06:52:00 PM PDT 24
Peak memory 191776 kb
Host smart-6437a0ae-08b5-42f9-9c67-b92ce31ae768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742898259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1742898259
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.192897480
Short name T18
Test name
Test status
Simulation time 4040785306 ps
CPU time 3.7 seconds
Started Jul 23 06:50:22 PM PDT 24
Finished Jul 23 06:50:28 PM PDT 24
Peak memory 215208 kb
Host smart-9943ddf3-4bce-42c6-be13-8c5628c5883a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192897480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.192897480
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.83521984
Short name T215
Test name
Test status
Simulation time 481605620 ps
CPU time 1.33 seconds
Started Jul 23 06:50:23 PM PDT 24
Finished Jul 23 06:50:25 PM PDT 24
Peak memory 196604 kb
Host smart-aec6a14d-6014-4339-bff3-dde4b9e618e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83521984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.83521984
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3815707961
Short name T229
Test name
Test status
Simulation time 57928214074 ps
CPU time 15.36 seconds
Started Jul 23 06:50:40 PM PDT 24
Finished Jul 23 06:50:58 PM PDT 24
Peak memory 191900 kb
Host smart-982aa61c-a5d2-4f13-9e65-8e3ea3ab6d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815707961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3815707961
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3891139842
Short name T275
Test name
Test status
Simulation time 409106362 ps
CPU time 0.73 seconds
Started Jul 23 06:50:41 PM PDT 24
Finished Jul 23 06:50:44 PM PDT 24
Peak memory 196588 kb
Host smart-0fd7cce3-d8a4-4305-a941-8397f17cde9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891139842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3891139842
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2337411932
Short name T192
Test name
Test status
Simulation time 477627185 ps
CPU time 1.36 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:50:42 PM PDT 24
Peak memory 196512 kb
Host smart-980c5945-8a49-4da7-873f-0cacf023d1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337411932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2337411932
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3804966194
Short name T257
Test name
Test status
Simulation time 25237184114 ps
CPU time 25.07 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:51:06 PM PDT 24
Peak memory 191896 kb
Host smart-517abf74-ddfa-497b-8825-4fd68c1d31eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804966194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3804966194
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1878080760
Short name T209
Test name
Test status
Simulation time 509610362 ps
CPU time 1.45 seconds
Started Jul 23 06:50:41 PM PDT 24
Finished Jul 23 06:50:44 PM PDT 24
Peak memory 191776 kb
Host smart-d30b3b34-ab7a-4344-b39d-4655a56e48e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878080760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1878080760
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1057499281
Short name T6
Test name
Test status
Simulation time 28701765422 ps
CPU time 21.9 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:51:03 PM PDT 24
Peak memory 191800 kb
Host smart-5b6bf750-958d-4d02-9e5d-0dc087294857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057499281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1057499281
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2779539203
Short name T202
Test name
Test status
Simulation time 475962551 ps
CPU time 0.66 seconds
Started Jul 23 06:50:39 PM PDT 24
Finished Jul 23 06:50:42 PM PDT 24
Peak memory 191768 kb
Host smart-357c3bb5-f1da-41e7-bbc4-48e77395cb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779539203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2779539203
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.207889424
Short name T2
Test name
Test status
Simulation time 54434759930 ps
CPU time 80.93 seconds
Started Jul 23 06:50:40 PM PDT 24
Finished Jul 23 06:52:03 PM PDT 24
Peak memory 196832 kb
Host smart-f60059f2-5792-4467-9340-3eeb2d046d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207889424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.207889424
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1459732671
Short name T268
Test name
Test status
Simulation time 499144155 ps
CPU time 0.76 seconds
Started Jul 23 06:50:38 PM PDT 24
Finished Jul 23 06:50:40 PM PDT 24
Peak memory 191772 kb
Host smart-e80ff84d-41b2-4c73-8cae-bf97f93aa04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459732671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1459732671
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1434352204
Short name T213
Test name
Test status
Simulation time 4194168072 ps
CPU time 1.93 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 06:50:48 PM PDT 24
Peak memory 191816 kb
Host smart-44d3642b-1cb9-4e0c-af1c-69377200cc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434352204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1434352204
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1086292306
Short name T220
Test name
Test status
Simulation time 496767801 ps
CPU time 0.94 seconds
Started Jul 23 06:50:40 PM PDT 24
Finished Jul 23 06:50:42 PM PDT 24
Peak memory 196544 kb
Host smart-8a3ba193-0e20-4441-9005-194991c81791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086292306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1086292306
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1059947281
Short name T244
Test name
Test status
Simulation time 32236021847 ps
CPU time 12.81 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 06:51:05 PM PDT 24
Peak memory 191872 kb
Host smart-9637fa01-d6ef-4f12-83c8-5d5abd61140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059947281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1059947281
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.541206912
Short name T236
Test name
Test status
Simulation time 427806094 ps
CPU time 0.73 seconds
Started Jul 23 06:50:48 PM PDT 24
Finished Jul 23 06:50:51 PM PDT 24
Peak memory 191752 kb
Host smart-855d2c5e-7890-4f89-9a90-59ac1878140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541206912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.541206912
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2295548019
Short name T207
Test name
Test status
Simulation time 15470309348 ps
CPU time 5.5 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 06:50:51 PM PDT 24
Peak memory 191876 kb
Host smart-079cd0b6-9417-4a8f-a9da-a0ef0ad9df05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295548019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2295548019
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1160767400
Short name T84
Test name
Test status
Simulation time 445684321 ps
CPU time 1.15 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 06:50:52 PM PDT 24
Peak memory 191776 kb
Host smart-31c848fd-0998-45b6-bc07-0cf6f8567520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160767400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1160767400
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3949355473
Short name T10
Test name
Test status
Simulation time 21845513588 ps
CPU time 33.54 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 06:51:20 PM PDT 24
Peak memory 196856 kb
Host smart-2f32e9e2-81a0-45d2-a3fb-da6df8c2a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949355473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3949355473
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3499813411
Short name T262
Test name
Test status
Simulation time 467582586 ps
CPU time 0.73 seconds
Started Jul 23 06:50:48 PM PDT 24
Finished Jul 23 06:50:51 PM PDT 24
Peak memory 191760 kb
Host smart-f4201049-8548-4b43-9bf9-2b904da43af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499813411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3499813411
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.424873246
Short name T261
Test name
Test status
Simulation time 3535772330 ps
CPU time 0.91 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:50:57 PM PDT 24
Peak memory 191840 kb
Host smart-3657e0a4-ff81-4310-9622-d6c5b11d0d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424873246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.424873246
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.327725345
Short name T269
Test name
Test status
Simulation time 527447085 ps
CPU time 1.27 seconds
Started Jul 23 06:50:48 PM PDT 24
Finished Jul 23 06:50:52 PM PDT 24
Peak memory 191780 kb
Host smart-d8b91601-9d17-4fde-b7b9-c10781d5c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327725345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.327725345
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3458191717
Short name T94
Test name
Test status
Simulation time 10402563924 ps
CPU time 67.92 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:52:04 PM PDT 24
Peak memory 214172 kb
Host smart-cbb75d48-1584-4cbd-bbc5-5379ef0f8c69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458191717 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3458191717
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.712535823
Short name T48
Test name
Test status
Simulation time 37358050090 ps
CPU time 10.74 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 06:51:03 PM PDT 24
Peak memory 191884 kb
Host smart-719bc7d0-c5fd-41f8-9474-e5d431163c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712535823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.712535823
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3161197660
Short name T266
Test name
Test status
Simulation time 477970805 ps
CPU time 0.93 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 06:50:53 PM PDT 24
Peak memory 191768 kb
Host smart-1458de67-047b-4164-854a-573de1eeb549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161197660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3161197660
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2839010576
Short name T276
Test name
Test status
Simulation time 41330865935 ps
CPU time 5.73 seconds
Started Jul 23 06:50:21 PM PDT 24
Finished Jul 23 06:50:28 PM PDT 24
Peak memory 196884 kb
Host smart-6fd87a6d-bfc1-442a-b50d-034b995ee213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839010576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2839010576
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2052277460
Short name T20
Test name
Test status
Simulation time 7711105071 ps
CPU time 3.19 seconds
Started Jul 23 06:50:19 PM PDT 24
Finished Jul 23 06:50:23 PM PDT 24
Peak memory 215904 kb
Host smart-52a869c6-628b-4a93-ba68-b440cbc50c92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052277460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2052277460
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.793707160
Short name T22
Test name
Test status
Simulation time 366966216 ps
CPU time 0.73 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:27 PM PDT 24
Peak memory 196424 kb
Host smart-4190fec0-e1f0-4e70-a076-54f8c5ffcc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793707160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.793707160
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3182930151
Short name T254
Test name
Test status
Simulation time 12146971615 ps
CPU time 10.41 seconds
Started Jul 23 06:50:47 PM PDT 24
Finished Jul 23 06:51:00 PM PDT 24
Peak memory 191800 kb
Host smart-62c6839b-c7d4-4618-90e1-e261aad50dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182930151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3182930151
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1999687213
Short name T241
Test name
Test status
Simulation time 340044023 ps
CPU time 1.05 seconds
Started Jul 23 06:50:51 PM PDT 24
Finished Jul 23 06:50:55 PM PDT 24
Peak memory 196636 kb
Host smart-bb8a5653-4524-4f0c-a728-2dc4864215df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999687213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1999687213
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3354208137
Short name T250
Test name
Test status
Simulation time 2952612519 ps
CPU time 1.73 seconds
Started Jul 23 06:50:48 PM PDT 24
Finished Jul 23 06:50:52 PM PDT 24
Peak memory 191816 kb
Host smart-34f631e5-de71-44b3-bb65-b74b06763ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354208137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3354208137
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1065944238
Short name T217
Test name
Test status
Simulation time 572345500 ps
CPU time 0.92 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 06:50:49 PM PDT 24
Peak memory 191776 kb
Host smart-9055a213-cf98-448a-a428-f340ab7b8746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065944238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1065944238
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.280724915
Short name T263
Test name
Test status
Simulation time 34991533151 ps
CPU time 25.15 seconds
Started Jul 23 06:50:47 PM PDT 24
Finished Jul 23 06:51:14 PM PDT 24
Peak memory 191852 kb
Host smart-38357f42-dc67-4f2a-b76c-bec260d3b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280724915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.280724915
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1228349484
Short name T206
Test name
Test status
Simulation time 522695382 ps
CPU time 1.48 seconds
Started Jul 23 06:50:50 PM PDT 24
Finished Jul 23 06:50:54 PM PDT 24
Peak memory 191796 kb
Host smart-bbea0dec-0a5a-4643-8690-d5a2d2f6e4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228349484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1228349484
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.55096646
Short name T228
Test name
Test status
Simulation time 38210692955 ps
CPU time 11.31 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:51:11 PM PDT 24
Peak memory 191904 kb
Host smart-d8b1f13b-dc93-4d3b-a456-18ac7f00b650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55096646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.55096646
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3813746604
Short name T24
Test name
Test status
Simulation time 577879940 ps
CPU time 0.65 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:51:01 PM PDT 24
Peak memory 196612 kb
Host smart-3094886e-1682-4fbf-9fa5-56c2369c314a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813746604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3813746604
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2928134768
Short name T255
Test name
Test status
Simulation time 174064198598 ps
CPU time 272.43 seconds
Started Jul 23 06:50:46 PM PDT 24
Finished Jul 23 06:55:21 PM PDT 24
Peak memory 183740 kb
Host smart-d3e28a37-421b-475f-8fb5-023053a939b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928134768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2928134768
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2689781548
Short name T259
Test name
Test status
Simulation time 5060082400 ps
CPU time 1.29 seconds
Started Jul 23 06:50:45 PM PDT 24
Finished Jul 23 06:50:48 PM PDT 24
Peak memory 196936 kb
Host smart-0af66af4-5729-40de-bfc8-c8b92dd0cfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689781548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2689781548
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3110549151
Short name T52
Test name
Test status
Simulation time 595433083 ps
CPU time 0.79 seconds
Started Jul 23 06:50:50 PM PDT 24
Finished Jul 23 06:50:53 PM PDT 24
Peak memory 196608 kb
Host smart-45a85ad5-4407-43c6-856c-d72f315ade0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110549151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3110549151
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2249682114
Short name T28
Test name
Test status
Simulation time 10257470948 ps
CPU time 15.27 seconds
Started Jul 23 06:50:47 PM PDT 24
Finished Jul 23 06:51:04 PM PDT 24
Peak memory 197060 kb
Host smart-4dc393ec-f1ab-4122-9159-db1240801643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249682114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2249682114
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1412076773
Short name T245
Test name
Test status
Simulation time 591863093 ps
CPU time 0.8 seconds
Started Jul 23 06:50:48 PM PDT 24
Finished Jul 23 06:50:51 PM PDT 24
Peak memory 191772 kb
Host smart-5058c9fb-0c61-48a7-97f7-11f32259f07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412076773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1412076773
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2296378171
Short name T105
Test name
Test status
Simulation time 33452101960 ps
CPU time 230 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:54:50 PM PDT 24
Peak memory 213924 kb
Host smart-29977b31-df5b-47cc-ad5f-900e51f7c916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296378171 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2296378171
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3427072283
Short name T233
Test name
Test status
Simulation time 23056686209 ps
CPU time 15.78 seconds
Started Jul 23 06:50:49 PM PDT 24
Finished Jul 23 06:51:08 PM PDT 24
Peak memory 191864 kb
Host smart-7c05cba2-2502-431e-8038-5fc6f1bb8ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427072283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3427072283
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4022458433
Short name T4
Test name
Test status
Simulation time 484791573 ps
CPU time 0.63 seconds
Started Jul 23 06:50:50 PM PDT 24
Finished Jul 23 06:50:53 PM PDT 24
Peak memory 196204 kb
Host smart-c7ff7d9c-7053-4c72-9a91-708459b4532f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022458433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4022458433
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.393369204
Short name T218
Test name
Test status
Simulation time 27438932625 ps
CPU time 36.57 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:51:33 PM PDT 24
Peak memory 191904 kb
Host smart-19cf278c-6432-4a0c-824d-5932a813a3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393369204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.393369204
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4039646733
Short name T271
Test name
Test status
Simulation time 487046520 ps
CPU time 0.78 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:51:00 PM PDT 24
Peak memory 191676 kb
Host smart-44529fa8-6f8b-442a-b3a1-451ef69658fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039646733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4039646733
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_jump.474468080
Short name T193
Test name
Test status
Simulation time 508452894 ps
CPU time 0.79 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:50:59 PM PDT 24
Peak memory 196560 kb
Host smart-637d0528-a28e-4567-bd06-a5a9330e12aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474468080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.474468080
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.837363509
Short name T214
Test name
Test status
Simulation time 10940003383 ps
CPU time 8.42 seconds
Started Jul 23 06:50:56 PM PDT 24
Finished Jul 23 06:51:09 PM PDT 24
Peak memory 196892 kb
Host smart-75928f54-5947-4005-97ab-de045def38ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837363509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.837363509
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.641378421
Short name T53
Test name
Test status
Simulation time 510998699 ps
CPU time 0.91 seconds
Started Jul 23 06:50:55 PM PDT 24
Finished Jul 23 06:51:02 PM PDT 24
Peak memory 196604 kb
Host smart-0b386b8f-ce8c-47cb-9d07-7242b89af60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641378421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.641378421
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3066775807
Short name T226
Test name
Test status
Simulation time 16926968837 ps
CPU time 15.42 seconds
Started Jul 23 06:50:54 PM PDT 24
Finished Jul 23 06:51:14 PM PDT 24
Peak memory 191904 kb
Host smart-4f86ff60-bb0a-4160-9dd7-054088119058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066775807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3066775807
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3685197009
Short name T282
Test name
Test status
Simulation time 507554488 ps
CPU time 1.24 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:50:58 PM PDT 24
Peak memory 191700 kb
Host smart-1ec7e58f-8c08-49a9-8337-7175dd05a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685197009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3685197009
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.828595356
Short name T280
Test name
Test status
Simulation time 26044409273 ps
CPU time 221.98 seconds
Started Jul 23 06:50:52 PM PDT 24
Finished Jul 23 06:54:37 PM PDT 24
Peak memory 206708 kb
Host smart-2527deb6-22a5-4cfa-a9d2-8b27b50e3b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828595356 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.828595356
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3639408414
Short name T222
Test name
Test status
Simulation time 50983501142 ps
CPU time 13.48 seconds
Started Jul 23 06:50:20 PM PDT 24
Finished Jul 23 06:50:35 PM PDT 24
Peak memory 191892 kb
Host smart-fd72d1cd-39a5-4d71-8b97-1130cb22bfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639408414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3639408414
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3943273497
Short name T238
Test name
Test status
Simulation time 627604963 ps
CPU time 0.76 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:27 PM PDT 24
Peak memory 191680 kb
Host smart-64cf9d21-78bb-45ac-8f85-6598a9de71d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943273497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3943273497
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.267073332
Short name T251
Test name
Test status
Simulation time 10211559506 ps
CPU time 8.62 seconds
Started Jul 23 06:50:23 PM PDT 24
Finished Jul 23 06:50:33 PM PDT 24
Peak memory 191864 kb
Host smart-9b753905-b597-4207-8b99-bcce83babaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267073332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.267073332
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3304677223
Short name T237
Test name
Test status
Simulation time 387730965 ps
CPU time 1.13 seconds
Started Jul 23 06:50:21 PM PDT 24
Finished Jul 23 06:50:23 PM PDT 24
Peak memory 191788 kb
Host smart-db6e2d96-0b0f-430d-845f-e2103e23eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304677223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3304677223
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.435776900
Short name T189
Test name
Test status
Simulation time 336966899 ps
CPU time 1.16 seconds
Started Jul 23 06:50:25 PM PDT 24
Finished Jul 23 06:50:28 PM PDT 24
Peak memory 196452 kb
Host smart-12a3ff4d-57a4-4934-9490-ce948c6847c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435776900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.435776900
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1735987009
Short name T231
Test name
Test status
Simulation time 30377228648 ps
CPU time 21.47 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:48 PM PDT 24
Peak memory 191800 kb
Host smart-f344b562-e25f-4271-9aa6-66571f14a61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735987009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1735987009
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3818827360
Short name T273
Test name
Test status
Simulation time 390153329 ps
CPU time 0.8 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:27 PM PDT 24
Peak memory 191764 kb
Host smart-1c8b4e24-0abb-45a3-908d-b373c2ec7598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818827360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3818827360
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1943443700
Short name T279
Test name
Test status
Simulation time 44538639606 ps
CPU time 15.63 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:42 PM PDT 24
Peak memory 191816 kb
Host smart-ab17f7d7-e7ce-4ce9-a274-a45423f6a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943443700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1943443700
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2814317830
Short name T256
Test name
Test status
Simulation time 437417595 ps
CPU time 0.74 seconds
Started Jul 23 06:50:28 PM PDT 24
Finished Jul 23 06:50:31 PM PDT 24
Peak memory 191716 kb
Host smart-b8b98c85-7994-496d-9bf1-d611f542d6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814317830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2814317830
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.490326768
Short name T239
Test name
Test status
Simulation time 11770148341 ps
CPU time 9.51 seconds
Started Jul 23 06:50:26 PM PDT 24
Finished Jul 23 06:50:38 PM PDT 24
Peak memory 191916 kb
Host smart-d53dafc1-fb36-4203-90b2-7ee6026437f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490326768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.490326768
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1919549496
Short name T212
Test name
Test status
Simulation time 558825970 ps
CPU time 0.74 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:27 PM PDT 24
Peak memory 191740 kb
Host smart-a329b276-43ba-4e19-bf39-52366f72ecbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919549496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1919549496
Directory /workspace/9.aon_timer_smoke/latest
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