Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30043	1		T1	12		T2	640		T3	96
bark[1]	484	1		T5	21		T44	21		T82	21
bark[2]	722	1		T38	77		T39	210		T148	131
bark[3]	379	1		T26	21		T23	14		T79	21
bark[4]	388	1		T8	21		T22	21		T95	26
bark[5]	439	1		T99	21		T82	52		T45	21
bark[6]	948	1		T7	7		T10	45		T14	26
bark[7]	704	1		T39	26		T119	70		T45	21
bark[8]	840	1		T8	5		T10	21		T27	21
bark[9]	746	1		T8	21		T10	98		T27	229
bark[10]	922	1		T154	40		T78	26		T24	30
bark[11]	166	1		T86	14		T87	26		T50	21
bark[12]	462	1		T3	51		T7	35		T27	67
bark[13]	716	1		T14	14		T37	31		T82	21
bark[14]	608	1		T7	21		T8	194		T38	26
bark[15]	576	1		T4	21		T7	198		T14	21
bark[16]	726	1		T38	21		T78	43		T175	61
bark[17]	474	1		T2	21		T133	21		T45	26
bark[18]	196	1		T5	21		T14	21		T26	42
bark[19]	523	1		T31	14		T37	21		T42	26
bark[20]	598	1		T14	21		T36	47		T38	21
bark[21]	844	1		T5	21		T6	14		T37	110
bark[22]	446	1		T148	39		T24	30		T108	21
bark[23]	631	1		T2	21		T4	21		T10	45
bark[24]	1004	1		T2	40		T3	115		T26	21
bark[25]	541	1		T2	26		T5	61		T46	61
bark[26]	466	1		T3	126		T26	21		T37	26
bark[27]	1180	1		T26	21		T36	219		T154	31
bark[28]	668	1		T5	21		T7	321		T27	141
bark[29]	1145	1		T10	925		T14	21		T26	40
bark[30]	281	1		T26	30		T36	21		T42	26
bark[31]	272	1		T2	47		T26	26		T37	21
bark_0	5089	1		T1	7		T2	102		T3	49

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	29078	1		T1	11		T2	633		T3	93
bite[1]	409	1		T4	21		T24	30		T102	21
bite[2]	586	1		T26	30		T44	21		T17	21
bite[3]	671	1		T8	21		T42	26		T119	70
bite[4]	841	1		T2	21		T26	39		T82	21
bite[5]	335	1		T5	21		T10	21		T14	34
bite[6]	1001	1		T7	197		T26	21		T27	66
bite[7]	315	1		T6	13		T8	21		T154	30
bite[8]	179	1		T5	21		T26	21		T127	74
bite[9]	221	1		T82	21		T22	21		T126	26
bite[10]	820	1		T7	21		T26	21		T44	13
bite[11]	186	1		T42	30		T99	21		T176	13
bite[12]	684	1		T42	26		T82	31		T78	25
bite[13]	399	1		T3	21		T7	35		T24	262
bite[14]	1049	1		T26	21		T36	21		T107	13
bite[15]	904	1		T2	21		T5	21		T10	97
bite[16]	625	1		T3	30		T27	21		T31	13
bite[17]	179	1		T134	26		T171	13		T147	13
bite[18]	399	1		T41	13		T38	102		T17	42
bite[19]	679	1		T2	25		T26	26		T36	46
bite[20]	1075	1		T8	46		T14	21		T27	140
bite[21]	301	1		T14	21		T38	21		T39	21
bite[22]	825	1		T7	326		T37	25		T44	30
bite[23]	656	1		T2	46		T148	21		T45	23
bite[24]	540	1		T2	39		T5	61		T39	72
bite[25]	435	1		T8	21		T44	21		T75	21
bite[26]	896	1		T8	150		T27	228		T154	30
bite[27]	752	1		T3	114		T5	21		T36	218
bite[28]	1824	1		T3	125		T10	924		T14	21
bite[29]	962	1		T10	44		T44	26		T154	40
bite[30]	445	1		T4	21		T37	21		T25	13
bite[31]	361	1		T10	44		T133	23		T39	209
bite_0	5595	1		T1	8		T2	112		T3	54

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	45466	1		T1	19		T2	897		T3	437
auto[1]	8761	1		T10	64		T14	20		T26	20

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1343	1		T4	24		T7	53		T37	26
prescale[1]	871	1		T2	47		T27	49		T37	19
prescale[2]	1135	1		T5	44		T36	19		T99	28
prescale[3]	1004	1		T7	93		T36	57		T125	45
prescale[4]	708	1		T8	2		T10	9		T14	49
prescale[5]	675	1		T37	40		T44	70		T38	24
prescale[6]	699	1		T2	2		T5	19		T10	21
prescale[7]	717	1		T2	91		T82	44		T39	19
prescale[8]	666	1		T4	37		T37	2		T193	9
prescale[9]	654	1		T3	36		T7	62		T27	2
prescale[10]	815	1		T27	2		T43	9		T99	19
prescale[11]	1300	1		T2	19		T7	71		T10	140
prescale[12]	879	1		T2	87		T5	40		T10	41
prescale[13]	801	1		T2	32		T7	167		T8	2
prescale[14]	501	1		T37	19		T148	31		T127	56
prescale[15]	651	1		T2	2		T3	28		T10	19
prescale[16]	990	1		T2	2		T5	40		T7	28
prescale[17]	893	1		T2	154		T36	2		T38	44
prescale[18]	624	1		T2	2		T4	19		T36	78
prescale[19]	769	1		T3	2		T5	19		T7	62
prescale[20]	1005	1		T3	28		T8	81		T10	291
prescale[21]	618	1		T10	4		T37	16		T38	37
prescale[22]	653	1		T2	2		T7	40		T37	76
prescale[23]	966	1		T73	9		T36	87		T45	85
prescale[24]	1483	1		T2	40		T4	32		T8	36
prescale[25]	559	1		T2	19		T4	45		T7	102
prescale[26]	626	1		T7	2		T42	45		T39	2
prescale[27]	831	1		T2	47		T7	30		T26	32
prescale[28]	1013	1		T5	23		T7	36		T10	181
prescale[29]	488	1		T7	21		T10	109		T36	2
prescale[30]	819	1		T1	9		T3	2		T5	19
prescale[31]	1164	1		T2	2		T4	40		T7	41
prescale_0	27307	1		T1	10		T2	349		T3	341

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40889	1		T1	9		T2	689		T3	345
auto[1]	13338	1		T1	10		T2	208		T3	92

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	54227	1		T1	19		T2	897		T3	437

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	31114	1		T1	14		T2	479		T3	205
wkup[1]	156	1		T7	21		T86	15		T75	21
wkup[2]	393	1		T7	21		T26	21		T27	21
wkup[3]	242	1		T27	26		T38	26		T74	21
wkup[4]	291	1		T3	21		T36	21		T39	42
wkup[5]	291	1		T8	6		T38	21		T102	39
wkup[6]	222	1		T7	21		T8	21		T39	26
wkup[7]	175	1		T26	20		T165	21		T108	21
wkup[8]	288	1		T2	21		T7	21		T10	21
wkup[9]	250	1		T3	21		T4	21		T8	21
wkup[10]	354	1		T2	20		T7	21		T10	21
wkup[11]	334	1		T3	21		T27	42		T133	21
wkup[12]	332	1		T8	30		T24	21		T50	21
wkup[13]	486	1		T27	15		T36	21		T42	26
wkup[14]	261	1		T2	21		T7	21		T14	21
wkup[15]	390	1		T4	26		T10	21		T27	21
wkup[16]	303	1		T5	21		T7	21		T8	21
wkup[17]	301	1		T27	21		T37	21		T154	21
wkup[18]	288	1		T7	35		T36	30		T78	35
wkup[19]	299	1		T7	50		T10	31		T27	47
wkup[20]	253	1		T2	56		T8	21		T37	21
wkup[21]	462	1		T8	21		T10	21		T45	21
wkup[22]	357	1		T7	21		T8	15		T10	30
wkup[23]	230	1		T7	21		T27	21		T133	21
wkup[24]	340	1		T26	21		T133	21		T38	15
wkup[25]	255	1		T10	31		T39	21		T148	39
wkup[26]	281	1		T4	21		T26	47		T148	21
wkup[27]	168	1		T7	26		T10	42		T36	21
wkup[28]	318	1		T2	42		T10	30		T125	21
wkup[29]	276	1		T7	21		T10	26		T26	30
wkup[30]	193	1		T5	21		T10	26		T45	26
wkup[31]	313	1		T44	21		T78	21		T45	21
wkup[32]	318	1		T10	21		T27	42		T45	21
wkup[33]	191	1		T14	21		T127	21		T17	42
wkup[34]	209	1		T127	21		T78	21		T175	21
wkup[35]	149	1		T36	8		T37	21		T185	15
wkup[36]	342	1		T2	29		T3	30		T7	15
wkup[37]	353	1		T5	21		T36	21		T37	21
wkup[38]	400	1		T6	15		T7	30		T14	15
wkup[39]	422	1		T7	21		T8	21		T27	30
wkup[40]	309	1		T4	21		T14	26		T36	21
wkup[41]	214	1		T10	26		T119	21		T165	42
wkup[42]	193	1		T5	21		T27	8		T74	42
wkup[43]	326	1		T2	63		T26	21		T27	30
wkup[44]	165	1		T7	24		T31	15		T37	21
wkup[45]	277	1		T2	21		T7	21		T26	21
wkup[46]	192	1		T3	21		T39	21		T78	21
wkup[47]	271	1		T42	30		T133	25		T17	30
wkup[48]	469	1		T3	21		T10	30		T36	21
wkup[49]	392	1		T2	21		T10	21		T37	21
wkup[50]	126	1		T5	21		T8	63		T148	21
wkup[51]	338	1		T7	42		T10	21		T38	21
wkup[52]	221	1		T37	30		T74	51		T80	30
wkup[53]	288	1		T39	8		T74	21		T87	26
wkup[54]	400	1		T7	30		T10	56		T37	21
wkup[55]	310	1		T7	40		T27	21		T148	21
wkup[56]	356	1		T36	21		T78	21		T45	21
wkup[57]	571	1		T2	21		T3	42		T27	26
wkup[58]	434	1		T7	21		T14	21		T78	21
wkup[59]	367	1		T8	21		T10	21		T14	21
wkup[60]	285	1		T99	21		T45	30		T87	21
wkup[61]	358	1		T3	16		T5	21		T37	21
wkup[62]	362	1		T10	51		T14	30		T107	15
wkup[63]	383	1		T2	21		T7	26		T26	21
wkup_0	4020	1		T1	5		T2	82		T3	39