Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.59 99.33 93.67 100.00 98.40 99.51 52.62


Total test records in report: 423
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T287 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4117760985 Jul 24 05:22:23 PM PDT 24 Jul 24 05:22:24 PM PDT 24 409126311 ps
T35 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.914864980 Jul 24 05:22:03 PM PDT 24 Jul 24 05:22:05 PM PDT 24 1227216495 ps
T288 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.570796367 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:29 PM PDT 24 450155054 ps
T289 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1659267335 Jul 24 05:22:06 PM PDT 24 Jul 24 05:22:08 PM PDT 24 424493317 ps
T28 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4120715983 Jul 24 05:22:07 PM PDT 24 Jul 24 05:22:12 PM PDT 24 1789911833 ps
T29 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1795161674 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:25 PM PDT 24 532662980 ps
T30 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3972848701 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:26 PM PDT 24 553993220 ps
T51 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1563759184 Jul 24 05:22:08 PM PDT 24 Jul 24 05:22:13 PM PDT 24 14521341762 ps
T65 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1852403010 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:10 PM PDT 24 1454152364 ps
T66 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2797417809 Jul 24 05:22:23 PM PDT 24 Jul 24 05:22:28 PM PDT 24 2422133213 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2637393505 Jul 24 05:21:53 PM PDT 24 Jul 24 05:21:54 PM PDT 24 514285541 ps
T32 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2678725021 Jul 24 05:22:12 PM PDT 24 Jul 24 05:22:25 PM PDT 24 8144115361 ps
T33 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3052399169 Jul 24 05:22:15 PM PDT 24 Jul 24 05:22:19 PM PDT 24 4146278244 ps
T291 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.242166340 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:10 PM PDT 24 355604220 ps
T194 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.9514451 Jul 24 05:22:22 PM PDT 24 Jul 24 05:22:24 PM PDT 24 412158542 ps
T52 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3810190894 Jul 24 05:22:12 PM PDT 24 Jul 24 05:22:13 PM PDT 24 402150692 ps
T53 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2878241297 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:11 PM PDT 24 447053861 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2767772477 Jul 24 05:21:57 PM PDT 24 Jul 24 05:21:59 PM PDT 24 538396631 ps
T34 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2023904692 Jul 24 05:22:07 PM PDT 24 Jul 24 05:22:11 PM PDT 24 4066816926 ps
T192 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3112514142 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:19 PM PDT 24 4223428768 ps
T293 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1411744760 Jul 24 05:22:23 PM PDT 24 Jul 24 05:22:24 PM PDT 24 311686326 ps
T294 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1114950152 Jul 24 05:22:14 PM PDT 24 Jul 24 05:22:16 PM PDT 24 462622710 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4127600702 Jul 24 05:21:57 PM PDT 24 Jul 24 05:22:06 PM PDT 24 7614396605 ps
T295 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2687355105 Jul 24 05:22:06 PM PDT 24 Jul 24 05:22:07 PM PDT 24 513379319 ps
T296 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1449882390 Jul 24 05:22:07 PM PDT 24 Jul 24 05:22:09 PM PDT 24 294822525 ps
T297 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2062914805 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:29 PM PDT 24 442920849 ps
T298 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3830142325 Jul 24 05:21:57 PM PDT 24 Jul 24 05:21:59 PM PDT 24 509272578 ps
T299 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2983613154 Jul 24 05:22:16 PM PDT 24 Jul 24 05:22:17 PM PDT 24 360185854 ps
T67 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4105870472 Jul 24 05:22:06 PM PDT 24 Jul 24 05:22:09 PM PDT 24 2181419047 ps
T55 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1059000188 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:12 PM PDT 24 419856650 ps
T300 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.776793378 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:30 PM PDT 24 427345058 ps
T187 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1038744141 Jul 24 05:22:05 PM PDT 24 Jul 24 05:22:08 PM PDT 24 8215113542 ps
T301 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3371680263 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:26 PM PDT 24 419640385 ps
T188 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1342535688 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:40 PM PDT 24 8349661915 ps
T302 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2256723613 Jul 24 05:21:57 PM PDT 24 Jul 24 05:21:58 PM PDT 24 344096940 ps
T303 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3865476135 Jul 24 05:22:19 PM PDT 24 Jul 24 05:22:20 PM PDT 24 452021373 ps
T304 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2423943591 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:28 PM PDT 24 384750785 ps
T305 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.712599572 Jul 24 05:22:15 PM PDT 24 Jul 24 05:22:16 PM PDT 24 509463312 ps
T306 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4007985612 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:26 PM PDT 24 507819252 ps
T189 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.625397143 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:37 PM PDT 24 8265039515 ps
T307 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1204809976 Jul 24 05:22:06 PM PDT 24 Jul 24 05:22:08 PM PDT 24 474733314 ps
T308 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1464439067 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:11 PM PDT 24 439489136 ps
T309 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2096617643 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:13 PM PDT 24 762320976 ps
T310 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2294300267 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:25 PM PDT 24 429090911 ps
T56 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.489262827 Jul 24 05:21:56 PM PDT 24 Jul 24 05:22:02 PM PDT 24 12848079870 ps
T311 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4133963455 Jul 24 05:22:03 PM PDT 24 Jul 24 05:22:07 PM PDT 24 8147624583 ps
T312 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2352927802 Jul 24 05:22:08 PM PDT 24 Jul 24 05:22:09 PM PDT 24 385764540 ps
T313 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2866730237 Jul 24 05:22:15 PM PDT 24 Jul 24 05:22:16 PM PDT 24 445935337 ps
T314 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3889901337 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:28 PM PDT 24 446609288 ps
T315 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1903567373 Jul 24 05:22:13 PM PDT 24 Jul 24 05:22:14 PM PDT 24 374254093 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1849849842 Jul 24 05:22:06 PM PDT 24 Jul 24 05:22:07 PM PDT 24 499089157 ps
T68 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3998842006 Jul 24 05:22:04 PM PDT 24 Jul 24 05:22:05 PM PDT 24 1063068485 ps
T317 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.172401227 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:29 PM PDT 24 493533015 ps
T318 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.504919198 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:28 PM PDT 24 563959381 ps
T69 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2102429654 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:13 PM PDT 24 1117447234 ps
T319 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2611071801 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:10 PM PDT 24 368049357 ps
T320 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1666507981 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:12 PM PDT 24 389473872 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2457681668 Jul 24 05:22:03 PM PDT 24 Jul 24 05:22:04 PM PDT 24 346041288 ps
T321 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2167093254 Jul 24 05:22:13 PM PDT 24 Jul 24 05:22:15 PM PDT 24 501997601 ps
T322 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3450576500 Jul 24 05:22:23 PM PDT 24 Jul 24 05:22:25 PM PDT 24 378450272 ps
T70 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1528183278 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:14 PM PDT 24 2285561244 ps
T323 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1178335179 Jul 24 05:22:16 PM PDT 24 Jul 24 05:22:17 PM PDT 24 498896752 ps
T324 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2843446624 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:30 PM PDT 24 1183783369 ps
T325 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2399214513 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:26 PM PDT 24 411679548 ps
T326 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4151474855 Jul 24 05:22:12 PM PDT 24 Jul 24 05:22:19 PM PDT 24 8368087986 ps
T327 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2574408032 Jul 24 05:22:20 PM PDT 24 Jul 24 05:22:23 PM PDT 24 463054437 ps
T59 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1026190096 Jul 24 05:22:04 PM PDT 24 Jul 24 05:22:16 PM PDT 24 8901122387 ps
T328 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2239499510 Jul 24 05:22:16 PM PDT 24 Jul 24 05:22:17 PM PDT 24 745300377 ps
T329 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3134976312 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:29 PM PDT 24 378504048 ps
T330 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3823736865 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:11 PM PDT 24 516094066 ps
T331 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3955081091 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:13 PM PDT 24 554499641 ps
T332 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.990648797 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:13 PM PDT 24 617500322 ps
T333 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2742427405 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:12 PM PDT 24 506620634 ps
T334 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3953074287 Jul 24 05:22:12 PM PDT 24 Jul 24 05:22:14 PM PDT 24 511984355 ps
T335 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1930600059 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:30 PM PDT 24 323810076 ps
T336 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2026204885 Jul 24 05:21:57 PM PDT 24 Jul 24 05:21:58 PM PDT 24 291310417 ps
T71 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.654154332 Jul 24 05:22:12 PM PDT 24 Jul 24 05:22:13 PM PDT 24 434766886 ps
T337 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3172432575 Jul 24 05:21:57 PM PDT 24 Jul 24 05:21:59 PM PDT 24 510814505 ps
T72 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.356446076 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:25 PM PDT 24 447714317 ps
T338 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3426328566 Jul 24 05:22:01 PM PDT 24 Jul 24 05:22:03 PM PDT 24 661635981 ps
T339 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2172190197 Jul 24 05:22:15 PM PDT 24 Jul 24 05:22:17 PM PDT 24 2534331747 ps
T340 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2281630384 Jul 24 05:21:57 PM PDT 24 Jul 24 05:21:58 PM PDT 24 1848336694 ps
T341 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1178505478 Jul 24 05:22:03 PM PDT 24 Jul 24 05:22:04 PM PDT 24 629084003 ps
T342 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1516871934 Jul 24 05:22:21 PM PDT 24 Jul 24 05:22:26 PM PDT 24 8331289672 ps
T343 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3418834614 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:29 PM PDT 24 370245314 ps
T344 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3899958406 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:09 PM PDT 24 531203648 ps
T345 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3459126852 Jul 24 05:22:19 PM PDT 24 Jul 24 05:22:20 PM PDT 24 463839713 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2592719838 Jul 24 05:22:14 PM PDT 24 Jul 24 05:22:16 PM PDT 24 525589007 ps
T346 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2368237866 Jul 24 05:21:58 PM PDT 24 Jul 24 05:22:00 PM PDT 24 466783152 ps
T61 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4119278155 Jul 24 05:22:00 PM PDT 24 Jul 24 05:22:01 PM PDT 24 557308796 ps
T347 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.216816722 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:15 PM PDT 24 2327333948 ps
T348 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2639915360 Jul 24 05:21:55 PM PDT 24 Jul 24 05:21:58 PM PDT 24 553515492 ps
T62 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1769113184 Jul 24 05:22:07 PM PDT 24 Jul 24 05:22:09 PM PDT 24 530047045 ps
T349 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.754272343 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:29 PM PDT 24 406854668 ps
T350 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1757402578 Jul 24 05:22:23 PM PDT 24 Jul 24 05:22:25 PM PDT 24 4284429861 ps
T351 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2986299466 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:11 PM PDT 24 325678922 ps
T352 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2915840150 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:12 PM PDT 24 832447756 ps
T353 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.139987524 Jul 24 05:22:04 PM PDT 24 Jul 24 05:22:07 PM PDT 24 4622671028 ps
T354 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3743035510 Jul 24 05:22:01 PM PDT 24 Jul 24 05:22:04 PM PDT 24 4812153791 ps
T355 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2154136569 Jul 24 05:22:08 PM PDT 24 Jul 24 05:22:09 PM PDT 24 493147245 ps
T356 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1723948814 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:29 PM PDT 24 292177434 ps
T357 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3660757919 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:11 PM PDT 24 467856328 ps
T358 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4234219063 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:27 PM PDT 24 441599360 ps
T359 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1080829986 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:26 PM PDT 24 408399107 ps
T360 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3735942485 Jul 24 05:21:56 PM PDT 24 Jul 24 05:21:57 PM PDT 24 341022003 ps
T361 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1284698071 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:28 PM PDT 24 333127291 ps
T362 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.412192894 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:12 PM PDT 24 347249060 ps
T363 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2449480459 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:12 PM PDT 24 586070422 ps
T364 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3977617745 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:12 PM PDT 24 454245789 ps
T57 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1889448034 Jul 24 05:22:02 PM PDT 24 Jul 24 05:22:04 PM PDT 24 389944786 ps
T365 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1097937088 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:12 PM PDT 24 500854303 ps
T366 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1067314156 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:27 PM PDT 24 2589540567 ps
T367 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1197803522 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:28 PM PDT 24 287936425 ps
T368 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4037398656 Jul 24 05:22:13 PM PDT 24 Jul 24 05:22:14 PM PDT 24 325978207 ps
T190 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3785529533 Jul 24 05:22:13 PM PDT 24 Jul 24 05:22:21 PM PDT 24 8239287669 ps
T369 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1797442859 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:13 PM PDT 24 5075526728 ps
T370 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.34657819 Jul 24 05:22:19 PM PDT 24 Jul 24 05:22:20 PM PDT 24 550252018 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1657240180 Jul 24 05:22:07 PM PDT 24 Jul 24 05:22:08 PM PDT 24 462971232 ps
T372 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3030994569 Jul 24 05:22:20 PM PDT 24 Jul 24 05:22:22 PM PDT 24 2143380534 ps
T373 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4010529937 Jul 24 05:22:22 PM PDT 24 Jul 24 05:22:24 PM PDT 24 795264787 ps
T374 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.528836036 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:27 PM PDT 24 314752238 ps
T375 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2193331406 Jul 24 05:22:15 PM PDT 24 Jul 24 05:22:18 PM PDT 24 929945596 ps
T376 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2871910998 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:32 PM PDT 24 540861606 ps
T377 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.229346747 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:27 PM PDT 24 289055867 ps
T378 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3161326659 Jul 24 05:22:23 PM PDT 24 Jul 24 05:22:24 PM PDT 24 358082747 ps
T379 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2004699430 Jul 24 05:22:15 PM PDT 24 Jul 24 05:22:16 PM PDT 24 400126839 ps
T380 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3879960711 Jul 24 05:22:03 PM PDT 24 Jul 24 05:22:04 PM PDT 24 518478925 ps
T381 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.129672635 Jul 24 05:22:12 PM PDT 24 Jul 24 05:22:14 PM PDT 24 804067641 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.221604464 Jul 24 05:21:58 PM PDT 24 Jul 24 05:21:59 PM PDT 24 520210904 ps
T383 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4191722180 Jul 24 05:22:23 PM PDT 24 Jul 24 05:22:24 PM PDT 24 320429639 ps
T384 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.545645397 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:25 PM PDT 24 449617595 ps
T385 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.105810835 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:11 PM PDT 24 1367110399 ps
T386 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.292446809 Jul 24 05:22:15 PM PDT 24 Jul 24 05:22:16 PM PDT 24 424234641 ps
T387 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1658879173 Jul 24 05:22:23 PM PDT 24 Jul 24 05:22:26 PM PDT 24 1307950295 ps
T388 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4179625318 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:10 PM PDT 24 2346696066 ps
T389 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.486258006 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:24 PM PDT 24 315342697 ps
T390 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2528904091 Jul 24 05:22:03 PM PDT 24 Jul 24 05:22:04 PM PDT 24 290870459 ps
T391 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3454381815 Jul 24 05:22:05 PM PDT 24 Jul 24 05:22:06 PM PDT 24 461545072 ps
T392 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4246225095 Jul 24 05:21:56 PM PDT 24 Jul 24 05:21:57 PM PDT 24 404525957 ps
T393 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2319114382 Jul 24 05:21:54 PM PDT 24 Jul 24 05:21:54 PM PDT 24 402673424 ps
T394 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2197119951 Jul 24 05:22:16 PM PDT 24 Jul 24 05:22:17 PM PDT 24 1254795309 ps
T395 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1371671693 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:13 PM PDT 24 490609897 ps
T64 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3314282515 Jul 24 05:21:51 PM PDT 24 Jul 24 05:21:52 PM PDT 24 359968723 ps
T396 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4113348464 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:12 PM PDT 24 987684831 ps
T397 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2055938595 Jul 24 05:22:16 PM PDT 24 Jul 24 05:22:18 PM PDT 24 486708106 ps
T398 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.543396158 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:29 PM PDT 24 2520093277 ps
T399 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4011335502 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:11 PM PDT 24 291022500 ps
T400 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3703553487 Jul 24 05:21:57 PM PDT 24 Jul 24 05:21:58 PM PDT 24 321735613 ps
T401 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2666049409 Jul 24 05:21:56 PM PDT 24 Jul 24 05:21:59 PM PDT 24 4365425490 ps
T402 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1636487145 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:11 PM PDT 24 469757928 ps
T403 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2824608604 Jul 24 05:22:19 PM PDT 24 Jul 24 05:22:27 PM PDT 24 8165451389 ps
T404 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2461655132 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:27 PM PDT 24 456277552 ps
T405 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3340810611 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:13 PM PDT 24 305468532 ps
T406 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2070400299 Jul 24 05:22:30 PM PDT 24 Jul 24 05:22:32 PM PDT 24 490889973 ps
T407 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.429816050 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:13 PM PDT 24 534605645 ps
T408 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3073797832 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:11 PM PDT 24 570778380 ps
T63 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3899939868 Jul 24 05:22:18 PM PDT 24 Jul 24 05:22:19 PM PDT 24 479068702 ps
T191 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1463345635 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:17 PM PDT 24 4159689012 ps
T409 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1410315550 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:11 PM PDT 24 504308339 ps
T410 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3494762945 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:28 PM PDT 24 400205633 ps
T411 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1007257434 Jul 24 05:22:10 PM PDT 24 Jul 24 05:22:14 PM PDT 24 1356515762 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1840573387 Jul 24 05:22:01 PM PDT 24 Jul 24 05:22:09 PM PDT 24 4549584788 ps
T413 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2500282866 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:29 PM PDT 24 301822264 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.433049663 Jul 24 05:22:07 PM PDT 24 Jul 24 05:22:10 PM PDT 24 1141928488 ps
T415 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2096244559 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:29 PM PDT 24 322432302 ps
T416 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3680895654 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:15 PM PDT 24 9231430698 ps
T417 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3110233365 Jul 24 05:22:16 PM PDT 24 Jul 24 05:22:17 PM PDT 24 557280968 ps
T418 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3652694712 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:27 PM PDT 24 1415597718 ps
T419 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1077660685 Jul 24 05:22:11 PM PDT 24 Jul 24 05:22:12 PM PDT 24 344585751 ps
T420 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.926693762 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:26 PM PDT 24 381203488 ps
T421 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1031068248 Jul 24 05:22:09 PM PDT 24 Jul 24 05:22:11 PM PDT 24 512571797 ps
T422 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.181507615 Jul 24 05:21:59 PM PDT 24 Jul 24 05:22:00 PM PDT 24 982589420 ps
T423 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3708929678 Jul 24 05:22:04 PM PDT 24 Jul 24 05:22:06 PM PDT 24 527450808 ps

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2498363757
Short name T7
Test name
Test status
Simulation time 345133312569 ps
CPU time 306.99 seconds
Started Jul 24 05:19:31 PM PDT 24
Finished Jul 24 05:24:39 PM PDT 24
Peak memory 201576 kb
Host smart-50119dbe-8761-4ad3-b3e7-5b3aca47b546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498363757 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2498363757
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.394011417
Short name T26
Test name
Test status
Simulation time 142754675568 ps
CPU time 49.21 seconds
Started Jul 24 05:19:42 PM PDT 24
Finished Jul 24 05:20:31 PM PDT 24
Peak memory 198276 kb
Host smart-3eba1242-a1f8-41bb-923a-4aa9158c4632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394011417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.394011417
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1563759184
Short name T51
Test name
Test status
Simulation time 14521341762 ps
CPU time 4.37 seconds
Started Jul 24 05:22:08 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 196576 kb
Host smart-64c5f5b5-01e5-4d2f-8e61-964f6b01ea21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563759184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1563759184
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3393608583
Short name T13
Test name
Test status
Simulation time 8183612123 ps
CPU time 3.38 seconds
Started Jul 24 05:19:25 PM PDT 24
Finished Jul 24 05:19:28 PM PDT 24
Peak memory 215796 kb
Host smart-ac180e7b-4a5a-4961-a6f6-6e152e820bef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393608583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3393608583
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2810162474
Short name T39
Test name
Test status
Simulation time 504427743849 ps
CPU time 673.22 seconds
Started Jul 24 05:19:46 PM PDT 24
Finished Jul 24 05:30:59 PM PDT 24
Peak memory 214852 kb
Host smart-4c92e0f5-d3a5-4393-a6da-79d801b1ceb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810162474 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2810162474
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2017399980
Short name T77
Test name
Test status
Simulation time 381924340294 ps
CPU time 1336.79 seconds
Started Jul 24 05:19:41 PM PDT 24
Finished Jul 24 05:41:58 PM PDT 24
Peak memory 214872 kb
Host smart-c8d027ae-2233-4322-bf85-dffaef5d824b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017399980 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2017399980
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.845319487
Short name T37
Test name
Test status
Simulation time 61038850361 ps
CPU time 443.19 seconds
Started Jul 24 05:19:24 PM PDT 24
Finished Jul 24 05:26:47 PM PDT 24
Peak memory 209388 kb
Host smart-227403d6-89f5-4ff9-b26e-d2c657b9a83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845319487 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.845319487
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2857115270
Short name T8
Test name
Test status
Simulation time 27373237729 ps
CPU time 223.18 seconds
Started Jul 24 05:19:46 PM PDT 24
Finished Jul 24 05:23:29 PM PDT 24
Peak memory 198432 kb
Host smart-1708e6eb-893c-4d39-9b26-2df74008d15e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857115270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2857115270
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3978196134
Short name T85
Test name
Test status
Simulation time 172260038764 ps
CPU time 708.47 seconds
Started Jul 24 05:19:21 PM PDT 24
Finished Jul 24 05:31:10 PM PDT 24
Peak memory 214852 kb
Host smart-7810e218-3f7c-48ec-9153-1061bc38c9a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978196134 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3978196134
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2914825895
Short name T24
Test name
Test status
Simulation time 419331807507 ps
CPU time 657.31 seconds
Started Jul 24 05:19:45 PM PDT 24
Finished Jul 24 05:30:42 PM PDT 24
Peak memory 205736 kb
Host smart-d1603402-6fc4-4568-8af1-37fb5693b4b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914825895 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2914825895
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1368335364
Short name T101
Test name
Test status
Simulation time 174135171180 ps
CPU time 722.07 seconds
Started Jul 24 05:19:34 PM PDT 24
Finished Jul 24 05:31:36 PM PDT 24
Peak memory 206328 kb
Host smart-4f3b43a1-bf83-4b44-a810-0ae3dfced866
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368335364 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1368335364
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.392653225
Short name T10
Test name
Test status
Simulation time 290025857773 ps
CPU time 707.48 seconds
Started Jul 24 05:19:27 PM PDT 24
Finished Jul 24 05:31:15 PM PDT 24
Peak memory 207128 kb
Host smart-4f153ac9-f49b-45f9-8f40-cc6d7bff7497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392653225 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.392653225
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2422840542
Short name T79
Test name
Test status
Simulation time 88936970783 ps
CPU time 343.26 seconds
Started Jul 24 05:19:45 PM PDT 24
Finished Jul 24 05:25:28 PM PDT 24
Peak memory 201372 kb
Host smart-2abe0c78-c456-45a6-a815-8f00ed17a8ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422840542 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2422840542
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.474332115
Short name T82
Test name
Test status
Simulation time 4595708211 ps
CPU time 2.44 seconds
Started Jul 24 05:19:48 PM PDT 24
Finished Jul 24 05:19:50 PM PDT 24
Peak memory 184196 kb
Host smart-7c48749c-71a8-416e-843a-a7822942ac2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474332115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.474332115
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3767103685
Short name T2
Test name
Test status
Simulation time 127455049159 ps
CPU time 272.35 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:23:59 PM PDT 24
Peak memory 206732 kb
Host smart-c19dc624-9a22-4a96-8510-bebcf87b6806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767103685 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3767103685
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.123212644
Short name T150
Test name
Test status
Simulation time 453539001892 ps
CPU time 344.6 seconds
Started Jul 24 05:19:50 PM PDT 24
Finished Jul 24 05:25:35 PM PDT 24
Peak memory 210184 kb
Host smart-3be3f792-60c8-4a92-a431-690a76f5f2ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123212644 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.123212644
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.450752920
Short name T93
Test name
Test status
Simulation time 46721878794 ps
CPU time 17.82 seconds
Started Jul 24 05:19:27 PM PDT 24
Finished Jul 24 05:19:45 PM PDT 24
Peak memory 198280 kb
Host smart-04695e9f-400e-44f4-991e-a791965efe88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450752920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.450752920
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.789163392
Short name T87
Test name
Test status
Simulation time 102634225905 ps
CPU time 816.35 seconds
Started Jul 24 05:19:30 PM PDT 24
Finished Jul 24 05:33:07 PM PDT 24
Peak memory 208076 kb
Host smart-42312e52-094c-4089-a521-6552831fb707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789163392 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.789163392
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.4127441035
Short name T45
Test name
Test status
Simulation time 56046585861 ps
CPU time 209.18 seconds
Started Jul 24 05:19:45 PM PDT 24
Finished Jul 24 05:23:15 PM PDT 24
Peak memory 198496 kb
Host smart-6b9738ca-7c88-494d-b45c-e7c6c9574e09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127441035 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.4127441035
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1182538129
Short name T129
Test name
Test status
Simulation time 143033588556 ps
CPU time 261.42 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:23:50 PM PDT 24
Peak memory 209084 kb
Host smart-e2e77b4d-d017-4601-acc6-d6d270ef524e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182538129 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1182538129
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.332174324
Short name T27
Test name
Test status
Simulation time 40584839942 ps
CPU time 337.4 seconds
Started Jul 24 05:20:08 PM PDT 24
Finished Jul 24 05:25:46 PM PDT 24
Peak memory 207044 kb
Host smart-b1fdadc5-7eef-4174-a6b2-784b1e384a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332174324 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.332174324
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1253751942
Short name T78
Test name
Test status
Simulation time 122476315712 ps
CPU time 941.37 seconds
Started Jul 24 05:19:39 PM PDT 24
Finished Jul 24 05:35:21 PM PDT 24
Peak memory 214928 kb
Host smart-b2189cc3-b9d2-4ca9-adf9-fbed39236ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253751942 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1253751942
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3052399169
Short name T33
Test name
Test status
Simulation time 4146278244 ps
CPU time 4.03 seconds
Started Jul 24 05:22:15 PM PDT 24
Finished Jul 24 05:22:19 PM PDT 24
Peak memory 198324 kb
Host smart-83d8d178-00e3-48a7-81d6-9e3f97061bcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052399169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3052399169
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.427094436
Short name T132
Test name
Test status
Simulation time 44850968791 ps
CPU time 329.93 seconds
Started Jul 24 05:19:54 PM PDT 24
Finished Jul 24 05:25:24 PM PDT 24
Peak memory 213932 kb
Host smart-3b182abf-ac4c-4cc6-bad1-ecf180d906c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427094436 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.427094436
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3420316961
Short name T74
Test name
Test status
Simulation time 93967271346 ps
CPU time 777.33 seconds
Started Jul 24 05:19:33 PM PDT 24
Finished Jul 24 05:32:31 PM PDT 24
Peak memory 206020 kb
Host smart-103ee42a-41cd-484f-b720-91a0db01fc6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420316961 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3420316961
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.458644555
Short name T104
Test name
Test status
Simulation time 18697033015 ps
CPU time 7.43 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:19:48 PM PDT 24
Peak memory 192944 kb
Host smart-909eea62-76c9-4be9-97cf-3250341861c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458644555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.458644555
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3273906290
Short name T38
Test name
Test status
Simulation time 257796047873 ps
CPU time 596.09 seconds
Started Jul 24 05:19:50 PM PDT 24
Finished Jul 24 05:29:46 PM PDT 24
Peak memory 213496 kb
Host smart-d4ebe132-9f76-41c8-ba09-c044a273097a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273906290 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3273906290
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3908469676
Short name T105
Test name
Test status
Simulation time 479923651921 ps
CPU time 835.97 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:33:24 PM PDT 24
Peak memory 214832 kb
Host smart-04dc0f03-a5a6-4847-a911-b7267c83ef3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908469676 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3908469676
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.203274473
Short name T157
Test name
Test status
Simulation time 64840153916 ps
CPU time 350.63 seconds
Started Jul 24 05:19:27 PM PDT 24
Finished Jul 24 05:25:18 PM PDT 24
Peak memory 206728 kb
Host smart-18a8f413-fdba-4bf0-90a9-573a8ba1457d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203274473 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.203274473
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1432964628
Short name T14
Test name
Test status
Simulation time 37717827899 ps
CPU time 52.83 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:20:21 PM PDT 24
Peak memory 191820 kb
Host smart-a06ecf8f-4f30-4398-9f0c-ee7a2f3ff6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432964628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1432964628
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.404179715
Short name T50
Test name
Test status
Simulation time 113429533009 ps
CPU time 1032.06 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:36:39 PM PDT 24
Peak memory 214920 kb
Host smart-a763bc91-d71d-4149-b8d1-65b73b01c95e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404179715 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.404179715
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.649944363
Short name T103
Test name
Test status
Simulation time 194651699937 ps
CPU time 26.73 seconds
Started Jul 24 05:20:06 PM PDT 24
Finished Jul 24 05:20:33 PM PDT 24
Peak memory 192972 kb
Host smart-34e3d3f5-8c98-4eac-bd13-5babc8a3ea3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649944363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.649944363
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1958203869
Short name T115
Test name
Test status
Simulation time 287226146378 ps
CPU time 352.17 seconds
Started Jul 24 05:19:55 PM PDT 24
Finished Jul 24 05:25:47 PM PDT 24
Peak memory 193008 kb
Host smart-78e0b917-f0f3-4cf3-a237-6bcf5ddf1d9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958203869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1958203869
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.765361447
Short name T44
Test name
Test status
Simulation time 53265695110 ps
CPU time 80.09 seconds
Started Jul 24 05:19:31 PM PDT 24
Finished Jul 24 05:20:52 PM PDT 24
Peak memory 192956 kb
Host smart-ef3277b1-76f9-4546-b93a-537131527c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765361447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.765361447
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1903932734
Short name T91
Test name
Test status
Simulation time 60179937579 ps
CPU time 595.89 seconds
Started Jul 24 05:19:49 PM PDT 24
Finished Jul 24 05:29:45 PM PDT 24
Peak memory 206672 kb
Host smart-8c38cb6a-85ad-4b40-b01c-2523807ffa4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903932734 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1903932734
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.4147403830
Short name T3
Test name
Test status
Simulation time 194380841776 ps
CPU time 395.34 seconds
Started Jul 24 05:19:32 PM PDT 24
Finished Jul 24 05:26:07 PM PDT 24
Peak memory 210892 kb
Host smart-eac7b5ab-b2a6-4204-bd3a-dde0e9cf46e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147403830 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.4147403830
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.375614441
Short name T80
Test name
Test status
Simulation time 244377544754 ps
CPU time 330.85 seconds
Started Jul 24 05:20:01 PM PDT 24
Finished Jul 24 05:25:32 PM PDT 24
Peak memory 209796 kb
Host smart-31319e69-b761-4e4b-b805-2d75d1c813a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375614441 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.375614441
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2859529318
Short name T134
Test name
Test status
Simulation time 33293356287 ps
CPU time 13.96 seconds
Started Jul 24 05:19:25 PM PDT 24
Finished Jul 24 05:19:39 PM PDT 24
Peak memory 198176 kb
Host smart-e299fc3b-ad6b-445e-85bc-a6f73bb7a50e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859529318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2859529318
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3097006759
Short name T88
Test name
Test status
Simulation time 175506632433 ps
CPU time 42.28 seconds
Started Jul 24 05:19:44 PM PDT 24
Finished Jul 24 05:20:27 PM PDT 24
Peak memory 184164 kb
Host smart-3e699090-7380-4c94-add9-d6ea4cf44dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097006759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3097006759
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4252121552
Short name T111
Test name
Test status
Simulation time 125077162217 ps
CPU time 94.57 seconds
Started Jul 24 05:19:38 PM PDT 24
Finished Jul 24 05:21:13 PM PDT 24
Peak memory 192828 kb
Host smart-8ee988b1-ac12-42f5-a084-2d5f378c2722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252121552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4252121552
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1472434750
Short name T109
Test name
Test status
Simulation time 199863625067 ps
CPU time 401.14 seconds
Started Jul 24 05:19:33 PM PDT 24
Finished Jul 24 05:26:14 PM PDT 24
Peak memory 211132 kb
Host smart-63af6853-7a0c-48a3-92a8-44808f7008db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472434750 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1472434750
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3178376141
Short name T116
Test name
Test status
Simulation time 15272310292 ps
CPU time 157.65 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:22:18 PM PDT 24
Peak memory 198648 kb
Host smart-88e61481-eca4-4c9e-8b56-eaa38ff3d06c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178376141 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3178376141
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2409734933
Short name T96
Test name
Test status
Simulation time 101619163072 ps
CPU time 165.59 seconds
Started Jul 24 05:19:43 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 192992 kb
Host smart-22b37b71-9ce5-4a6f-b8bc-4170cb06bae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409734933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2409734933
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.802442109
Short name T75
Test name
Test status
Simulation time 58563660909 ps
CPU time 600.69 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:29:29 PM PDT 24
Peak memory 206624 kb
Host smart-d702be7e-f37c-4760-a611-0dd3e993cfb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802442109 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.802442109
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2027809910
Short name T102
Test name
Test status
Simulation time 28926748707 ps
CPU time 42.85 seconds
Started Jul 24 05:20:00 PM PDT 24
Finished Jul 24 05:20:43 PM PDT 24
Peak memory 192880 kb
Host smart-9a74033b-2175-489b-9c71-6fa71762d727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027809910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2027809910
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3442239051
Short name T140
Test name
Test status
Simulation time 29802028380 ps
CPU time 9.97 seconds
Started Jul 24 05:19:31 PM PDT 24
Finished Jul 24 05:19:41 PM PDT 24
Peak memory 198128 kb
Host smart-0c3e6673-b92f-4a85-8eb7-af180d99f68e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442239051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3442239051
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.747345245
Short name T118
Test name
Test status
Simulation time 109903286418 ps
CPU time 45.57 seconds
Started Jul 24 05:20:02 PM PDT 24
Finished Jul 24 05:20:48 PM PDT 24
Peak memory 192876 kb
Host smart-3730e8dc-9a8d-4400-8f79-393ccf3a9d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747345245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.747345245
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.233118511
Short name T149
Test name
Test status
Simulation time 64472047822 ps
CPU time 378.51 seconds
Started Jul 24 05:19:50 PM PDT 24
Finished Jul 24 05:26:09 PM PDT 24
Peak memory 213988 kb
Host smart-517a6758-863c-41ed-96ab-c354e6e7ac4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233118511 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.233118511
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3871673344
Short name T4
Test name
Test status
Simulation time 275713786468 ps
CPU time 386.93 seconds
Started Jul 24 05:19:34 PM PDT 24
Finished Jul 24 05:26:01 PM PDT 24
Peak memory 198208 kb
Host smart-b2b65a9c-6537-4a42-8aa8-9ce07f29cc78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871673344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3871673344
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2715757614
Short name T127
Test name
Test status
Simulation time 427170599404 ps
CPU time 90.99 seconds
Started Jul 24 05:19:36 PM PDT 24
Finished Jul 24 05:21:07 PM PDT 24
Peak memory 192412 kb
Host smart-16c0ddab-0e52-48b5-b337-f025bc50bfde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715757614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2715757614
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2277273003
Short name T84
Test name
Test status
Simulation time 125647395653 ps
CPU time 9.73 seconds
Started Jul 24 05:19:32 PM PDT 24
Finished Jul 24 05:19:42 PM PDT 24
Peak memory 192944 kb
Host smart-756a5b73-eaf9-49f5-b0fc-54ab99d86a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277273003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2277273003
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.4222401615
Short name T5
Test name
Test status
Simulation time 360399256199 ps
CPU time 266.34 seconds
Started Jul 24 05:20:00 PM PDT 24
Finished Jul 24 05:24:26 PM PDT 24
Peak memory 192948 kb
Host smart-cf431e4e-6308-46f7-9200-c0a380ea854a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222401615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.4222401615
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.174014816
Short name T106
Test name
Test status
Simulation time 542587182818 ps
CPU time 49.18 seconds
Started Jul 24 05:20:04 PM PDT 24
Finished Jul 24 05:20:53 PM PDT 24
Peak memory 192872 kb
Host smart-a3014592-2ea0-4fd5-b1c1-7863913bd54e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174014816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.174014816
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1190322074
Short name T95
Test name
Test status
Simulation time 91126974132 ps
CPU time 28.3 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:19:58 PM PDT 24
Peak memory 198156 kb
Host smart-5e31f017-57f1-46d4-83cd-6dcff52e661d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190322074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1190322074
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1287257515
Short name T121
Test name
Test status
Simulation time 34773435035 ps
CPU time 21.81 seconds
Started Jul 24 05:19:41 PM PDT 24
Finished Jul 24 05:20:03 PM PDT 24
Peak memory 198140 kb
Host smart-85d22233-12e8-499b-9af3-3519f6e1ecf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287257515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1287257515
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.45415081
Short name T17
Test name
Test status
Simulation time 93609672247 ps
CPU time 550.18 seconds
Started Jul 24 05:19:32 PM PDT 24
Finished Jul 24 05:28:43 PM PDT 24
Peak memory 214188 kb
Host smart-e2448474-2490-44ee-a2e7-d76fe03279cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45415081 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.45415081
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1938769287
Short name T36
Test name
Test status
Simulation time 116543279083 ps
CPU time 226.83 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:23:27 PM PDT 24
Peak memory 200292 kb
Host smart-f042b08d-06fc-4cfd-b215-db7474814c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938769287 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1938769287
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4120715983
Short name T28
Test name
Test status
Simulation time 1789911833 ps
CPU time 4.95 seconds
Started Jul 24 05:22:07 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 192396 kb
Host smart-be194d38-92f7-4498-9633-f188606bf3c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120715983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.4120715983
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.717965813
Short name T110
Test name
Test status
Simulation time 126299591000 ps
CPU time 163.19 seconds
Started Jul 24 05:19:37 PM PDT 24
Finished Jul 24 05:22:20 PM PDT 24
Peak memory 192928 kb
Host smart-d885be0c-667d-4799-98b1-f146f36dc42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717965813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.717965813
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1111890444
Short name T148
Test name
Test status
Simulation time 271687075517 ps
CPU time 212.58 seconds
Started Jul 24 05:19:38 PM PDT 24
Finished Jul 24 05:23:11 PM PDT 24
Peak memory 192892 kb
Host smart-85bf07eb-e8ce-44ed-b0c3-0a21fe68f808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111890444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1111890444
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2392536897
Short name T97
Test name
Test status
Simulation time 56763697826 ps
CPU time 334.21 seconds
Started Jul 24 05:19:45 PM PDT 24
Finished Jul 24 05:25:19 PM PDT 24
Peak memory 199860 kb
Host smart-b96f972f-c505-4b13-abad-e6876dc68869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392536897 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2392536897
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2991079056
Short name T143
Test name
Test status
Simulation time 586777097659 ps
CPU time 181.75 seconds
Started Jul 24 05:19:44 PM PDT 24
Finished Jul 24 05:22:46 PM PDT 24
Peak memory 192824 kb
Host smart-649b4af6-d36b-4ef8-a8c9-e06b5d6fcb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991079056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2991079056
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.387105203
Short name T162
Test name
Test status
Simulation time 54573577571 ps
CPU time 229.51 seconds
Started Jul 24 05:20:09 PM PDT 24
Finished Jul 24 05:23:59 PM PDT 24
Peak memory 206700 kb
Host smart-842ab245-d152-42ae-bb33-a4b5e7f1af09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387105203 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.387105203
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2052229734
Short name T125
Test name
Test status
Simulation time 93425312858 ps
CPU time 197.77 seconds
Started Jul 24 05:19:41 PM PDT 24
Finished Jul 24 05:22:59 PM PDT 24
Peak memory 199840 kb
Host smart-649dff3c-c165-465d-875f-769cfb3bf006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052229734 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2052229734
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.482810269
Short name T22
Test name
Test status
Simulation time 610033579044 ps
CPU time 221.01 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:23:21 PM PDT 24
Peak memory 192420 kb
Host smart-9dd40114-7f93-4787-bdd8-b710155d0d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482810269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.482810269
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1232206688
Short name T130
Test name
Test status
Simulation time 104768492388 ps
CPU time 162.21 seconds
Started Jul 24 05:19:35 PM PDT 24
Finished Jul 24 05:22:18 PM PDT 24
Peak memory 198240 kb
Host smart-7d13e55d-dbd4-4404-b16d-5c74f7d1d4ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232206688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1232206688
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3792113624
Short name T145
Test name
Test status
Simulation time 17985643645 ps
CPU time 176.55 seconds
Started Jul 24 05:19:33 PM PDT 24
Finished Jul 24 05:22:30 PM PDT 24
Peak memory 213824 kb
Host smart-44772ef2-3e38-464c-a5b0-a3289077cb6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792113624 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3792113624
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.833990386
Short name T81
Test name
Test status
Simulation time 111242010807 ps
CPU time 101.68 seconds
Started Jul 24 05:19:23 PM PDT 24
Finished Jul 24 05:21:05 PM PDT 24
Peak memory 198984 kb
Host smart-b4ca4f91-7139-42cc-91b5-041d2cbe2391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833990386 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.833990386
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1915335333
Short name T89
Test name
Test status
Simulation time 489126631574 ps
CPU time 177.19 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:22:24 PM PDT 24
Peak memory 192980 kb
Host smart-e9e280cd-fc79-4f97-9982-d0d8a306d08d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915335333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1915335333
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2288675817
Short name T99
Test name
Test status
Simulation time 58789218269 ps
CPU time 19.55 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:19:49 PM PDT 24
Peak memory 191900 kb
Host smart-d81594e5-c396-4a7d-a5e6-406db637028e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288675817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2288675817
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3603847281
Short name T108
Test name
Test status
Simulation time 99142799786 ps
CPU time 69.55 seconds
Started Jul 24 05:19:30 PM PDT 24
Finished Jul 24 05:20:40 PM PDT 24
Peak memory 191840 kb
Host smart-f598e982-9d9c-4c78-9422-8234c95f44e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603847281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3603847281
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1287969036
Short name T76
Test name
Test status
Simulation time 142089204002 ps
CPU time 275.31 seconds
Started Jul 24 05:19:38 PM PDT 24
Finished Jul 24 05:24:13 PM PDT 24
Peak memory 214408 kb
Host smart-2d8a4599-4ca4-483b-bb4e-d5978707ac9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287969036 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1287969036
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1569023130
Short name T153
Test name
Test status
Simulation time 250827561536 ps
CPU time 50.89 seconds
Started Jul 24 05:19:54 PM PDT 24
Finished Jul 24 05:20:45 PM PDT 24
Peak memory 192920 kb
Host smart-1902d0ef-2839-49fc-8ef2-1b97380463ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569023130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1569023130
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2956390909
Short name T49
Test name
Test status
Simulation time 64925102807 ps
CPU time 306.11 seconds
Started Jul 24 05:19:55 PM PDT 24
Finished Jul 24 05:25:01 PM PDT 24
Peak memory 206736 kb
Host smart-31b4df1f-660a-4cb8-b109-be95083eabe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956390909 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2956390909
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1201324619
Short name T119
Test name
Test status
Simulation time 475704945413 ps
CPU time 325.26 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:24:53 PM PDT 24
Peak memory 198288 kb
Host smart-ae0a5487-b788-43df-ad4b-f074decca60d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201324619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1201324619
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4947272
Short name T142
Test name
Test status
Simulation time 108494123028 ps
CPU time 41.95 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:20:09 PM PDT 24
Peak memory 191904 kb
Host smart-6f40664e-4706-4ada-93ea-3b6c979a6326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4947272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.4947272
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1240957124
Short name T42
Test name
Test status
Simulation time 55145896953 ps
CPU time 69.45 seconds
Started Jul 24 05:19:44 PM PDT 24
Finished Jul 24 05:20:53 PM PDT 24
Peak memory 198252 kb
Host smart-9de0fdbe-f8b6-483c-91c7-373fb722c61f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240957124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1240957124
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2201172827
Short name T161
Test name
Test status
Simulation time 119248184627 ps
CPU time 170.04 seconds
Started Jul 24 05:19:41 PM PDT 24
Finished Jul 24 05:22:31 PM PDT 24
Peak memory 192932 kb
Host smart-ebc785a8-d957-4876-874d-cb25a4cbbb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201172827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2201172827
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3135397703
Short name T137
Test name
Test status
Simulation time 63589695020 ps
CPU time 170.12 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:22:18 PM PDT 24
Peak memory 198664 kb
Host smart-2e2975e7-19b3-4612-8ee7-9e140a01f57f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135397703 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3135397703
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1868239086
Short name T46
Test name
Test status
Simulation time 25601563172 ps
CPU time 90.72 seconds
Started Jul 24 05:19:31 PM PDT 24
Finished Jul 24 05:21:02 PM PDT 24
Peak memory 206708 kb
Host smart-1642aac1-f3bc-45dd-ba89-9a746da49cb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868239086 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1868239086
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.4230628875
Short name T117
Test name
Test status
Simulation time 50576912477 ps
CPU time 35.49 seconds
Started Jul 24 05:19:35 PM PDT 24
Finished Jul 24 05:20:11 PM PDT 24
Peak memory 197740 kb
Host smart-9acc1cff-fc08-4584-968f-166ba5014d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230628875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.4230628875
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1930667108
Short name T90
Test name
Test status
Simulation time 452562990 ps
CPU time 0.8 seconds
Started Jul 24 05:19:49 PM PDT 24
Finished Jul 24 05:19:50 PM PDT 24
Peak memory 196604 kb
Host smart-cf952bd2-4172-449f-940c-d35257fba275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930667108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1930667108
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1039036149
Short name T122
Test name
Test status
Simulation time 101813752554 ps
CPU time 133.57 seconds
Started Jul 24 05:19:55 PM PDT 24
Finished Jul 24 05:22:09 PM PDT 24
Peak memory 198204 kb
Host smart-553d7673-52b9-4a93-891e-4a12ac82b606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039036149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1039036149
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1457898485
Short name T126
Test name
Test status
Simulation time 110653623093 ps
CPU time 38.2 seconds
Started Jul 24 05:19:44 PM PDT 24
Finished Jul 24 05:20:23 PM PDT 24
Peak memory 191808 kb
Host smart-4a74f428-89bd-44e4-a9d0-60d3db732fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457898485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1457898485
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3672877308
Short name T133
Test name
Test status
Simulation time 57538614093 ps
CPU time 46.26 seconds
Started Jul 24 05:19:44 PM PDT 24
Finished Jul 24 05:20:31 PM PDT 24
Peak memory 198148 kb
Host smart-ef4f4b3f-e57e-488a-8224-3e37cdcbaf23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672877308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3672877308
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.378038755
Short name T138
Test name
Test status
Simulation time 467157356 ps
CPU time 0.98 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:19:30 PM PDT 24
Peak memory 196580 kb
Host smart-7f21d951-78c3-4e37-af5d-dfcefeee2e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378038755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.378038755
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4152401098
Short name T124
Test name
Test status
Simulation time 559269448 ps
CPU time 1.42 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:28 PM PDT 24
Peak memory 196560 kb
Host smart-b9468513-3edf-49cb-ba00-b5cf3a4edeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152401098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4152401098
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1542529580
Short name T128
Test name
Test status
Simulation time 443891300 ps
CPU time 1.24 seconds
Started Jul 24 05:19:37 PM PDT 24
Finished Jul 24 05:19:39 PM PDT 24
Peak memory 196600 kb
Host smart-454526b4-aa52-4656-88d9-ffdbafeb42af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542529580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1542529580
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2422060084
Short name T114
Test name
Test status
Simulation time 366688413 ps
CPU time 0.81 seconds
Started Jul 24 05:19:33 PM PDT 24
Finished Jul 24 05:19:34 PM PDT 24
Peak memory 196516 kb
Host smart-2ceec5ed-ae9c-421b-bbde-1a89477e52d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422060084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2422060084
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_jump.4022554354
Short name T112
Test name
Test status
Simulation time 579888925 ps
CPU time 0.69 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:27 PM PDT 24
Peak memory 196536 kb
Host smart-6e258ced-37a9-416c-963b-f22108cc58db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022554354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.4022554354
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3073105907
Short name T151
Test name
Test status
Simulation time 574362285 ps
CPU time 1.42 seconds
Started Jul 24 05:19:41 PM PDT 24
Finished Jul 24 05:19:43 PM PDT 24
Peak memory 196756 kb
Host smart-b08bb4ce-bffc-4121-b403-333eba2984ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073105907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3073105907
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2377990821
Short name T144
Test name
Test status
Simulation time 450383003 ps
CPU time 0.89 seconds
Started Jul 24 05:19:39 PM PDT 24
Finished Jul 24 05:19:40 PM PDT 24
Peak memory 196644 kb
Host smart-1a465d9c-f3df-4f5d-9143-27eceebeb91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377990821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2377990821
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2460868904
Short name T98
Test name
Test status
Simulation time 594740803 ps
CPU time 0.85 seconds
Started Jul 24 05:19:41 PM PDT 24
Finished Jul 24 05:19:42 PM PDT 24
Peak memory 196620 kb
Host smart-73f45d93-3f23-429b-b578-a1edde65c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460868904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2460868904
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.558772398
Short name T120
Test name
Test status
Simulation time 154885159361 ps
CPU time 212.98 seconds
Started Jul 24 05:19:57 PM PDT 24
Finished Jul 24 05:23:30 PM PDT 24
Peak memory 192856 kb
Host smart-6241b31b-9471-4ee0-8253-2c8415f91bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558772398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.558772398
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.193577854
Short name T131
Test name
Test status
Simulation time 415336808 ps
CPU time 0.67 seconds
Started Jul 24 05:19:43 PM PDT 24
Finished Jul 24 05:19:44 PM PDT 24
Peak memory 196556 kb
Host smart-207353e5-2f27-4e94-8498-b7ca2e2a5fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193577854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.193577854
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2380499459
Short name T139
Test name
Test status
Simulation time 458801415 ps
CPU time 0.74 seconds
Started Jul 24 05:19:46 PM PDT 24
Finished Jul 24 05:19:46 PM PDT 24
Peak memory 196588 kb
Host smart-e13bd4dc-d9c4-4b51-baeb-94515b8d743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380499459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2380499459
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1392307380
Short name T146
Test name
Test status
Simulation time 458274312 ps
CPU time 1.01 seconds
Started Jul 24 05:19:36 PM PDT 24
Finished Jul 24 05:19:37 PM PDT 24
Peak memory 196680 kb
Host smart-1ad0144a-76fa-4a46-8a8a-0f2a05d950c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392307380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1392307380
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2928909716
Short name T165
Test name
Test status
Simulation time 324853701712 ps
CPU time 549.23 seconds
Started Jul 24 05:19:27 PM PDT 24
Finished Jul 24 05:28:37 PM PDT 24
Peak memory 204896 kb
Host smart-128a0b66-980c-43e5-b687-a21abb974cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928909716 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2928909716
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.616591524
Short name T156
Test name
Test status
Simulation time 229887687163 ps
CPU time 92.48 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:20:59 PM PDT 24
Peak memory 207124 kb
Host smart-ea639a5a-f09b-41f7-ba51-3e4f1a16983c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616591524 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.616591524
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3979252965
Short name T147
Test name
Test status
Simulation time 549915835 ps
CPU time 0.78 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 196636 kb
Host smart-ddc258d7-1909-47d8-b876-8bd8a86efeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979252965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3979252965
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3734147418
Short name T107
Test name
Test status
Simulation time 378021457 ps
CPU time 0.8 seconds
Started Jul 24 05:19:50 PM PDT 24
Finished Jul 24 05:19:51 PM PDT 24
Peak memory 196576 kb
Host smart-c640e100-2d6a-4c54-8f9a-bfa94174695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734147418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3734147418
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1348185405
Short name T113
Test name
Test status
Simulation time 91920660948 ps
CPU time 137.84 seconds
Started Jul 24 05:20:04 PM PDT 24
Finished Jul 24 05:22:22 PM PDT 24
Peak memory 191864 kb
Host smart-66954dc0-f38e-4abf-a483-8d9da15f216a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348185405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1348185405
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2145584882
Short name T135
Test name
Test status
Simulation time 97460886864 ps
CPU time 133.72 seconds
Started Jul 24 05:19:41 PM PDT 24
Finished Jul 24 05:21:55 PM PDT 24
Peak memory 192316 kb
Host smart-d9bbaa98-74c5-49d6-912f-05e67d374567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145584882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2145584882
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.73370786
Short name T100
Test name
Test status
Simulation time 186263714723 ps
CPU time 182.11 seconds
Started Jul 24 05:19:23 PM PDT 24
Finished Jul 24 05:22:25 PM PDT 24
Peak memory 191848 kb
Host smart-ad133141-cf0b-4db6-97cd-28daf2566c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73370786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all
.73370786
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.219481859
Short name T152
Test name
Test status
Simulation time 86450997389 ps
CPU time 32.89 seconds
Started Jul 24 05:19:44 PM PDT 24
Finished Jul 24 05:20:17 PM PDT 24
Peak memory 192316 kb
Host smart-8367ff77-76e1-401f-851f-2372630fc21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219481859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.219481859
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.337451948
Short name T184
Test name
Test status
Simulation time 539394705 ps
CPU time 0.93 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:27 PM PDT 24
Peak memory 196500 kb
Host smart-1b97f4e7-f6ac-4bb0-9ebe-867bd0624365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337451948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.337451948
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.729381196
Short name T166
Test name
Test status
Simulation time 125524724246 ps
CPU time 193.07 seconds
Started Jul 24 05:19:38 PM PDT 24
Finished Jul 24 05:22:51 PM PDT 24
Peak memory 184128 kb
Host smart-85c26163-a28e-4cd1-8321-99bfd9a8d445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729381196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.729381196
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2361790854
Short name T180
Test name
Test status
Simulation time 483816630 ps
CPU time 1.22 seconds
Started Jul 24 05:19:33 PM PDT 24
Finished Jul 24 05:19:34 PM PDT 24
Peak memory 196680 kb
Host smart-e149fa8e-1d70-419e-bbee-aba3603f6864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361790854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2361790854
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2387604739
Short name T92
Test name
Test status
Simulation time 469382867 ps
CPU time 1.18 seconds
Started Jul 24 05:19:37 PM PDT 24
Finished Jul 24 05:19:38 PM PDT 24
Peak memory 196540 kb
Host smart-d528c786-00cb-49e4-a279-5aeee3fc934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387604739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2387604739
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1785267537
Short name T41
Test name
Test status
Simulation time 471038337 ps
CPU time 1.31 seconds
Started Jul 24 05:19:47 PM PDT 24
Finished Jul 24 05:19:48 PM PDT 24
Peak memory 196524 kb
Host smart-ee26e147-3a28-4b7e-ba8e-542805bc116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785267537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1785267537
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_jump.699019769
Short name T178
Test name
Test status
Simulation time 419994878 ps
CPU time 0.73 seconds
Started Jul 24 05:19:39 PM PDT 24
Finished Jul 24 05:19:40 PM PDT 24
Peak memory 196540 kb
Host smart-83d1f93d-8d6a-4aa9-9194-d823e961b424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699019769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.699019769
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_jump.680458314
Short name T86
Test name
Test status
Simulation time 389414600 ps
CPU time 1.08 seconds
Started Jul 24 05:19:42 PM PDT 24
Finished Jul 24 05:19:44 PM PDT 24
Peak memory 196584 kb
Host smart-5abca08a-0a0d-4425-b9f4-cbc870c069ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680458314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.680458314
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_jump.354444860
Short name T136
Test name
Test status
Simulation time 477401432 ps
CPU time 0.98 seconds
Started Jul 24 05:19:41 PM PDT 24
Finished Jul 24 05:19:42 PM PDT 24
Peak memory 196604 kb
Host smart-d18b5ca9-5ad9-4e02-924d-fb9726db3a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354444860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.354444860
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2442986266
Short name T163
Test name
Test status
Simulation time 405899125 ps
CPU time 0.77 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:28 PM PDT 24
Peak memory 196648 kb
Host smart-b0ec548b-d6e1-47ab-b625-7a7f0f92595c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442986266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2442986266
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2831655384
Short name T83
Test name
Test status
Simulation time 3794048056 ps
CPU time 3.11 seconds
Started Jul 24 05:19:27 PM PDT 24
Finished Jul 24 05:19:30 PM PDT 24
Peak memory 198160 kb
Host smart-a3ff2e54-3730-4540-a0b7-5c9d64b7041a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831655384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2831655384
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.3785529533
Short name T190
Test name
Test status
Simulation time 8239287669 ps
CPU time 7.45 seconds
Started Jul 24 05:22:13 PM PDT 24
Finished Jul 24 05:22:21 PM PDT 24
Peak memory 198888 kb
Host smart-2f3ab247-c671-4149-a2be-8023937e01fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785529533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.3785529533
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.895699460
Short name T25
Test name
Test status
Simulation time 422932078 ps
CPU time 1.18 seconds
Started Jul 24 05:19:27 PM PDT 24
Finished Jul 24 05:19:28 PM PDT 24
Peak memory 196516 kb
Host smart-c5bdf90b-6910-4992-91d6-f896d5c29a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895699460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.895699460
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3791392200
Short name T179
Test name
Test status
Simulation time 386139890 ps
CPU time 0.71 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:19:30 PM PDT 24
Peak memory 196512 kb
Host smart-f1d9a845-c0dd-48f4-a8a1-60aecf0c5ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791392200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3791392200
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3609486248
Short name T171
Test name
Test status
Simulation time 482295381 ps
CPU time 0.78 seconds
Started Jul 24 05:19:35 PM PDT 24
Finished Jul 24 05:19:36 PM PDT 24
Peak memory 196472 kb
Host smart-0ea33ac4-3cc6-4d35-98a8-2f24a19409a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609486248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3609486248
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.618537135
Short name T164
Test name
Test status
Simulation time 536587166 ps
CPU time 0.96 seconds
Started Jul 24 05:19:56 PM PDT 24
Finished Jul 24 05:19:57 PM PDT 24
Peak memory 196656 kb
Host smart-4b9e1b95-ed06-4741-944f-f91a77dd9038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618537135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.618537135
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.861077652
Short name T173
Test name
Test status
Simulation time 469297146 ps
CPU time 0.75 seconds
Started Jul 24 05:19:47 PM PDT 24
Finished Jul 24 05:19:48 PM PDT 24
Peak memory 196524 kb
Host smart-ecc25aaf-18b5-4b49-af42-4835073b2178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861077652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.861077652
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_jump.797363128
Short name T185
Test name
Test status
Simulation time 490718348 ps
CPU time 0.73 seconds
Started Jul 24 05:19:59 PM PDT 24
Finished Jul 24 05:20:00 PM PDT 24
Peak memory 196652 kb
Host smart-324a0f5e-9ec5-4082-b2b4-6336c4f9c133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797363128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.797363128
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.306653350
Short name T94
Test name
Test status
Simulation time 475499847 ps
CPU time 1.24 seconds
Started Jul 24 05:19:47 PM PDT 24
Finished Jul 24 05:19:48 PM PDT 24
Peak memory 196568 kb
Host smart-5a37286a-1e3b-4473-8224-4d8a224e8ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306653350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.306653350
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2851644299
Short name T170
Test name
Test status
Simulation time 517948786 ps
CPU time 1.35 seconds
Started Jul 24 05:19:44 PM PDT 24
Finished Jul 24 05:19:46 PM PDT 24
Peak memory 196488 kb
Host smart-79b938b9-2522-4b6f-992c-eb9c3921c464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851644299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2851644299
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_jump.304013436
Short name T19
Test name
Test status
Simulation time 552330295 ps
CPU time 1.11 seconds
Started Jul 24 05:19:58 PM PDT 24
Finished Jul 24 05:19:59 PM PDT 24
Peak memory 196512 kb
Host smart-0b87d392-4c95-44ea-a461-fd826164bc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304013436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.304013436
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.433881428
Short name T154
Test name
Test status
Simulation time 89271374929 ps
CPU time 17.6 seconds
Started Jul 24 05:19:43 PM PDT 24
Finished Jul 24 05:20:01 PM PDT 24
Peak memory 192024 kb
Host smart-e8bae2ca-ae9f-43e4-aba8-216a9ac83155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433881428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.433881428
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2889903472
Short name T23
Test name
Test status
Simulation time 493341146 ps
CPU time 0.81 seconds
Started Jul 24 05:19:50 PM PDT 24
Finished Jul 24 05:19:51 PM PDT 24
Peak memory 196572 kb
Host smart-1d045d5d-4f1b-45c2-a2b6-95450d894f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889903472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2889903472
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4289070596
Short name T159
Test name
Test status
Simulation time 400535841 ps
CPU time 1.26 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:19:30 PM PDT 24
Peak memory 196516 kb
Host smart-8fe4160a-f2de-4344-9889-1220287ed384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289070596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4289070596
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3121612535
Short name T123
Test name
Test status
Simulation time 534756092 ps
CPU time 1.29 seconds
Started Jul 24 05:19:22 PM PDT 24
Finished Jul 24 05:19:23 PM PDT 24
Peak memory 196640 kb
Host smart-7b8ae9e8-08d1-4149-bd86-1ec9c989e4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121612535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3121612535
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1343349972
Short name T160
Test name
Test status
Simulation time 630686736 ps
CPU time 0.8 seconds
Started Jul 24 05:19:27 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 196524 kb
Host smart-73495108-a5bf-4363-be8a-42a1806bdac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343349972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1343349972
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.241201040
Short name T174
Test name
Test status
Simulation time 35341131983 ps
CPU time 181.64 seconds
Started Jul 24 05:19:31 PM PDT 24
Finished Jul 24 05:22:33 PM PDT 24
Peak memory 214576 kb
Host smart-8297c3da-f865-4323-80ce-39980997ea0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241201040 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.241201040
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3171038328
Short name T177
Test name
Test status
Simulation time 245581613949 ps
CPU time 74.55 seconds
Started Jul 24 05:19:35 PM PDT 24
Finished Jul 24 05:20:50 PM PDT 24
Peak memory 191668 kb
Host smart-4e129f41-ad49-4116-b0d2-a8484d994db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171038328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3171038328
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2987720654
Short name T169
Test name
Test status
Simulation time 422915720 ps
CPU time 0.65 seconds
Started Jul 24 05:19:30 PM PDT 24
Finished Jul 24 05:19:31 PM PDT 24
Peak memory 196620 kb
Host smart-9c77425e-6915-4d2f-bf4d-b28521f29324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987720654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2987720654
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_jump.306856602
Short name T168
Test name
Test status
Simulation time 377268586 ps
CPU time 0.74 seconds
Started Jul 24 05:19:31 PM PDT 24
Finished Jul 24 05:19:32 PM PDT 24
Peak memory 196528 kb
Host smart-5e19c235-5824-4b53-b7d0-e4bbd88de526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306856602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.306856602
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1404159937
Short name T183
Test name
Test status
Simulation time 536439565 ps
CPU time 1.07 seconds
Started Jul 24 05:19:36 PM PDT 24
Finished Jul 24 05:19:37 PM PDT 24
Peak memory 196500 kb
Host smart-c2bfe09e-48cd-4320-bfad-65199852d213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404159937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1404159937
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3762797005
Short name T182
Test name
Test status
Simulation time 365380467 ps
CPU time 1.15 seconds
Started Jul 24 05:19:35 PM PDT 24
Finished Jul 24 05:19:36 PM PDT 24
Peak memory 196656 kb
Host smart-57892c36-b271-479c-801e-d3460e81f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762797005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3762797005
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1678279294
Short name T176
Test name
Test status
Simulation time 475297647 ps
CPU time 1.35 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:19:42 PM PDT 24
Peak memory 196552 kb
Host smart-36e1d3d6-ab02-4c15-ae16-63f0b7131e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678279294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1678279294
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_jump.556583313
Short name T158
Test name
Test status
Simulation time 475813180 ps
CPU time 0.78 seconds
Started Jul 24 05:19:47 PM PDT 24
Finished Jul 24 05:19:48 PM PDT 24
Peak memory 196564 kb
Host smart-3e8de911-0883-4941-9ff6-5fa2e6a554a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556583313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.556583313
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_jump.4173327213
Short name T21
Test name
Test status
Simulation time 455443925 ps
CPU time 1.23 seconds
Started Jul 24 05:19:48 PM PDT 24
Finished Jul 24 05:19:49 PM PDT 24
Peak memory 196400 kb
Host smart-99edc1a8-9b4f-4b1a-86d4-3b973ffd8602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173327213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.4173327213
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3963754872
Short name T175
Test name
Test status
Simulation time 198085672761 ps
CPU time 278.21 seconds
Started Jul 24 05:19:23 PM PDT 24
Finished Jul 24 05:24:01 PM PDT 24
Peak memory 198116 kb
Host smart-451c7d08-10f4-41d0-b4da-0090fb7bda01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963754872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3963754872
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.4118530101
Short name T172
Test name
Test status
Simulation time 501507350 ps
CPU time 0.75 seconds
Started Jul 24 05:20:04 PM PDT 24
Finished Jul 24 05:20:05 PM PDT 24
Peak memory 196548 kb
Host smart-ebf452c9-57f1-434d-bc61-39cd96d65198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118530101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.4118530101
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3074030653
Short name T155
Test name
Test status
Simulation time 344573367 ps
CPU time 1.14 seconds
Started Jul 24 05:19:54 PM PDT 24
Finished Jul 24 05:19:55 PM PDT 24
Peak memory 196628 kb
Host smart-420b8e37-f0fc-4a51-b0bd-ff83cab585d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074030653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3074030653
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4119278155
Short name T61
Test name
Test status
Simulation time 557308796 ps
CPU time 0.87 seconds
Started Jul 24 05:22:00 PM PDT 24
Finished Jul 24 05:22:01 PM PDT 24
Peak memory 184276 kb
Host smart-0eaa47ed-e3d2-4f4b-a554-aaf61b563092
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119278155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4119278155
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2843446624
Short name T324
Test name
Test status
Simulation time 1183783369 ps
CPU time 0.94 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:30 PM PDT 24
Peak memory 193464 kb
Host smart-a7a3adf2-93a8-48a5-8584-5a7ec9eea8c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843446624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2843446624
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3172432575
Short name T337
Test name
Test status
Simulation time 510814505 ps
CPU time 1.11 seconds
Started Jul 24 05:21:57 PM PDT 24
Finished Jul 24 05:21:59 PM PDT 24
Peak memory 197048 kb
Host smart-2545d9ad-afbe-44a2-95f1-69481df3cbc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172432575 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3172432575
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3314282515
Short name T64
Test name
Test status
Simulation time 359968723 ps
CPU time 0.87 seconds
Started Jul 24 05:21:51 PM PDT 24
Finished Jul 24 05:21:52 PM PDT 24
Peak memory 193672 kb
Host smart-eb1723cd-99a7-4feb-8a8d-15c4404b3db8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314282515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3314282515
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4191722180
Short name T383
Test name
Test status
Simulation time 320429639 ps
CPU time 0.63 seconds
Started Jul 24 05:22:23 PM PDT 24
Finished Jul 24 05:22:24 PM PDT 24
Peak memory 183996 kb
Host smart-d678143d-fda9-4650-96f5-b995f701a94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191722180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4191722180
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2637393505
Short name T290
Test name
Test status
Simulation time 514285541 ps
CPU time 1.32 seconds
Started Jul 24 05:21:53 PM PDT 24
Finished Jul 24 05:21:54 PM PDT 24
Peak memory 184136 kb
Host smart-67de4b79-c354-4c13-8c87-3268267df71d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637393505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2637393505
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2352927802
Short name T312
Test name
Test status
Simulation time 385764540 ps
CPU time 1.1 seconds
Started Jul 24 05:22:08 PM PDT 24
Finished Jul 24 05:22:09 PM PDT 24
Peak memory 184092 kb
Host smart-63e26da1-f45e-4987-b09e-ee60042ececb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352927802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2352927802
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1449882390
Short name T296
Test name
Test status
Simulation time 294822525 ps
CPU time 2.18 seconds
Started Jul 24 05:22:07 PM PDT 24
Finished Jul 24 05:22:09 PM PDT 24
Peak memory 199036 kb
Host smart-343e6434-7b98-4d47-b3d6-6b9354b463f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449882390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1449882390
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2023904692
Short name T34
Test name
Test status
Simulation time 4066816926 ps
CPU time 3.87 seconds
Started Jul 24 05:22:07 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 198284 kb
Host smart-9d8afadc-71ba-4bd2-ba6e-c76c7bb49f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023904692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2023904692
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2154136569
Short name T355
Test name
Test status
Simulation time 493147245 ps
CPU time 1.39 seconds
Started Jul 24 05:22:08 PM PDT 24
Finished Jul 24 05:22:09 PM PDT 24
Peak memory 184196 kb
Host smart-fa01a469-ecf2-41a1-8854-9f610176b600
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154136569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2154136569
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4127600702
Short name T54
Test name
Test status
Simulation time 7614396605 ps
CPU time 8.58 seconds
Started Jul 24 05:21:57 PM PDT 24
Finished Jul 24 05:22:06 PM PDT 24
Peak memory 192740 kb
Host smart-6db22825-9193-4f23-9c54-081af27a70b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127600702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4127600702
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.4113348464
Short name T396
Test name
Test status
Simulation time 987684831 ps
CPU time 1.84 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 193736 kb
Host smart-dbf4359b-a537-4ce7-bc95-d735f233ca4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113348464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.4113348464
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2368237866
Short name T346
Test name
Test status
Simulation time 466783152 ps
CPU time 1.41 seconds
Started Jul 24 05:21:58 PM PDT 24
Finished Jul 24 05:22:00 PM PDT 24
Peak memory 196784 kb
Host smart-aff2bded-5cea-4f5a-a5ce-62ace6298dd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368237866 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2368237866
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1077660685
Short name T419
Test name
Test status
Simulation time 344585751 ps
CPU time 1.09 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 193372 kb
Host smart-ad156491-eb5d-4752-9c29-d02adae75100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077660685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1077660685
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2256723613
Short name T302
Test name
Test status
Simulation time 344096940 ps
CPU time 0.63 seconds
Started Jul 24 05:21:57 PM PDT 24
Finished Jul 24 05:21:58 PM PDT 24
Peak memory 184184 kb
Host smart-322f5c40-a891-4eb8-bcb8-5ca3c76af33c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256723613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2256723613
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1657240180
Short name T371
Test name
Test status
Simulation time 462971232 ps
CPU time 0.9 seconds
Started Jul 24 05:22:07 PM PDT 24
Finished Jul 24 05:22:08 PM PDT 24
Peak memory 184016 kb
Host smart-97c616b3-a845-4720-8fa2-0d3a79f65239
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657240180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1657240180
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1636487145
Short name T402
Test name
Test status
Simulation time 469757928 ps
CPU time 1.17 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 184140 kb
Host smart-6ac52ef5-89db-4d80-b57d-136a5e471551
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636487145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1636487145
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.4105870472
Short name T67
Test name
Test status
Simulation time 2181419047 ps
CPU time 2.74 seconds
Started Jul 24 05:22:06 PM PDT 24
Finished Jul 24 05:22:09 PM PDT 24
Peak memory 194436 kb
Host smart-f2af6b8e-a310-4b14-93a5-ccbc836280a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105870472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.4105870472
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2639915360
Short name T348
Test name
Test status
Simulation time 553515492 ps
CPU time 2.29 seconds
Started Jul 24 05:21:55 PM PDT 24
Finished Jul 24 05:21:58 PM PDT 24
Peak memory 199056 kb
Host smart-47031934-5a84-48af-a74c-dae7d7eb1be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639915360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2639915360
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2666049409
Short name T401
Test name
Test status
Simulation time 4365425490 ps
CPU time 2.47 seconds
Started Jul 24 05:21:56 PM PDT 24
Finished Jul 24 05:21:59 PM PDT 24
Peak memory 198200 kb
Host smart-b13a5e34-36cf-4f44-b641-5bb00e96d6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666049409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2666049409
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3865476135
Short name T303
Test name
Test status
Simulation time 452021373 ps
CPU time 1.24 seconds
Started Jul 24 05:22:19 PM PDT 24
Finished Jul 24 05:22:20 PM PDT 24
Peak memory 196700 kb
Host smart-46820718-d860-4e67-9a32-e81d6b4b4347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865476135 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3865476135
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4007985612
Short name T306
Test name
Test status
Simulation time 507819252 ps
CPU time 0.75 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:26 PM PDT 24
Peak memory 193420 kb
Host smart-100c6e72-e7ab-4375-8231-3d5ce6aeb64a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007985612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4007985612
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4037398656
Short name T368
Test name
Test status
Simulation time 325978207 ps
CPU time 0.89 seconds
Started Jul 24 05:22:13 PM PDT 24
Finished Jul 24 05:22:14 PM PDT 24
Peak memory 184244 kb
Host smart-44dce5c6-b2ca-4b11-a5b5-321ffa44b22c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037398656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4037398656
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2172190197
Short name T339
Test name
Test status
Simulation time 2534331747 ps
CPU time 1.59 seconds
Started Jul 24 05:22:15 PM PDT 24
Finished Jul 24 05:22:17 PM PDT 24
Peak memory 194400 kb
Host smart-d581d8a5-8b4d-46f1-affb-20d8b1d031b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172190197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2172190197
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3955081091
Short name T331
Test name
Test status
Simulation time 554499641 ps
CPU time 1.64 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 199048 kb
Host smart-b33cc380-739d-4989-b18e-22a7c4e3c503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955081091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3955081091
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3953074287
Short name T334
Test name
Test status
Simulation time 511984355 ps
CPU time 1.25 seconds
Started Jul 24 05:22:12 PM PDT 24
Finished Jul 24 05:22:14 PM PDT 24
Peak memory 199068 kb
Host smart-5e9e6058-4837-479f-8a08-6fe528161092
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953074287 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3953074287
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2878241297
Short name T53
Test name
Test status
Simulation time 447053861 ps
CPU time 0.69 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 193444 kb
Host smart-d03244d0-6761-4864-b1c8-db77f47b9b53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878241297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2878241297
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.412192894
Short name T362
Test name
Test status
Simulation time 347249060 ps
CPU time 1.07 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 184176 kb
Host smart-c10c0f75-c0e6-4a3a-b484-935b30eff7eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412192894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.412192894
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2102429654
Short name T69
Test name
Test status
Simulation time 1117447234 ps
CPU time 2.15 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 193456 kb
Host smart-10c71264-8f32-451d-8c62-245224a6fd1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102429654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2102429654
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1371671693
Short name T395
Test name
Test status
Simulation time 490609897 ps
CPU time 1.97 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 198888 kb
Host smart-c0f8a12b-e21f-461d-a815-5650463fdf00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371671693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1371671693
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3680895654
Short name T416
Test name
Test status
Simulation time 9231430698 ps
CPU time 3.54 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:15 PM PDT 24
Peak memory 198784 kb
Host smart-3d83ccff-4e77-4637-98b9-990bca330ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680895654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3680895654
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.429816050
Short name T407
Test name
Test status
Simulation time 534605645 ps
CPU time 1.37 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 196832 kb
Host smart-cd1cdf12-2e2e-4576-afff-f658b3da4710
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429816050 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.429816050
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2449480459
Short name T363
Test name
Test status
Simulation time 586070422 ps
CPU time 0.76 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 193808 kb
Host smart-7dc480a2-7eed-48b7-80c5-7309c2981869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449480459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2449480459
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2611071801
Short name T319
Test name
Test status
Simulation time 368049357 ps
CPU time 0.88 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:10 PM PDT 24
Peak memory 184208 kb
Host smart-ef61c569-bc19-4cf5-b824-3a4272c23514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611071801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2611071801
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1528183278
Short name T70
Test name
Test status
Simulation time 2285561244 ps
CPU time 2.35 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:14 PM PDT 24
Peak memory 195740 kb
Host smart-81a101d1-50c1-4d1f-be22-e44d7ed607f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528183278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1528183278
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3977617745
Short name T364
Test name
Test status
Simulation time 454245789 ps
CPU time 2.39 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 199060 kb
Host smart-a25e1783-8332-4bf6-acb6-c3d829503181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977617745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3977617745
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1463345635
Short name T191
Test name
Test status
Simulation time 4159689012 ps
CPU time 6.88 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:17 PM PDT 24
Peak memory 198460 kb
Host smart-c3f36b02-b808-4b84-a959-95e42bb53ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463345635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1463345635
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1178335179
Short name T323
Test name
Test status
Simulation time 498896752 ps
CPU time 1.24 seconds
Started Jul 24 05:22:16 PM PDT 24
Finished Jul 24 05:22:17 PM PDT 24
Peak memory 196472 kb
Host smart-dec68320-c192-420c-b72b-9434eac53f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178335179 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1178335179
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1059000188
Short name T55
Test name
Test status
Simulation time 419856650 ps
CPU time 0.77 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 193692 kb
Host smart-8ddd1905-2ebf-4d7d-ad69-c8dd72ce70a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059000188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1059000188
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1464439067
Short name T308
Test name
Test status
Simulation time 439489136 ps
CPU time 0.69 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 184424 kb
Host smart-12997d02-277b-432a-b1a2-6cf4e2e11a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464439067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1464439067
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.4010529937
Short name T373
Test name
Test status
Simulation time 795264787 ps
CPU time 0.99 seconds
Started Jul 24 05:22:22 PM PDT 24
Finished Jul 24 05:22:24 PM PDT 24
Peak memory 194428 kb
Host smart-0ccd00b5-e8ae-486d-b61d-75b3a95d3139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010529937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.4010529937
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2096617643
Short name T309
Test name
Test status
Simulation time 762320976 ps
CPU time 2.1 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 199100 kb
Host smart-d9675687-0b69-4e83-b038-3a810939e459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096617643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2096617643
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3112514142
Short name T192
Test name
Test status
Simulation time 4223428768 ps
CPU time 7.27 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:19 PM PDT 24
Peak memory 198196 kb
Host smart-681d3ba9-16d4-4082-bc2b-fa79d3fda2e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112514142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3112514142
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2004699430
Short name T379
Test name
Test status
Simulation time 400126839 ps
CPU time 0.78 seconds
Started Jul 24 05:22:15 PM PDT 24
Finished Jul 24 05:22:16 PM PDT 24
Peak memory 195676 kb
Host smart-30b54d38-1c5a-4eec-bcd3-f17394503b86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004699430 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2004699430
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2983613154
Short name T299
Test name
Test status
Simulation time 360185854 ps
CPU time 0.9 seconds
Started Jul 24 05:22:16 PM PDT 24
Finished Jul 24 05:22:17 PM PDT 24
Peak memory 192464 kb
Host smart-fe6568a4-b082-4220-9267-19d7641563aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983613154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2983613154
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2866730237
Short name T313
Test name
Test status
Simulation time 445935337 ps
CPU time 1.21 seconds
Started Jul 24 05:22:15 PM PDT 24
Finished Jul 24 05:22:16 PM PDT 24
Peak memory 193472 kb
Host smart-1380508c-ef1c-424c-bfe2-92815421a5eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866730237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2866730237
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2797417809
Short name T66
Test name
Test status
Simulation time 2422133213 ps
CPU time 4.26 seconds
Started Jul 24 05:22:23 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 184428 kb
Host smart-5ec0ee4e-0a42-47a2-9cc0-af05b6e5cc79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797417809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2797417809
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3371680263
Short name T301
Test name
Test status
Simulation time 419640385 ps
CPU time 2.62 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:26 PM PDT 24
Peak memory 199096 kb
Host smart-2588e9f2-18a1-4626-ad58-926109681cca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371680263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3371680263
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.625397143
Short name T189
Test name
Test status
Simulation time 8265039515 ps
CPU time 12.43 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:37 PM PDT 24
Peak memory 198696 kb
Host smart-175dfbd3-4cd9-4117-b29f-8c841ccb9d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625397143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.625397143
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2871910998
Short name T376
Test name
Test status
Simulation time 540861606 ps
CPU time 1.4 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:32 PM PDT 24
Peak memory 195864 kb
Host smart-35eb81c2-98e0-4525-95e4-e866d24e6892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871910998 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2871910998
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.9514451
Short name T194
Test name
Test status
Simulation time 412158542 ps
CPU time 0.86 seconds
Started Jul 24 05:22:22 PM PDT 24
Finished Jul 24 05:22:24 PM PDT 24
Peak memory 193596 kb
Host smart-873c365e-b6f0-4a96-8017-98a34d92ac31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9514451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.9514451
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3134976312
Short name T329
Test name
Test status
Simulation time 378504048 ps
CPU time 1.18 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 193396 kb
Host smart-7d915336-01ff-457a-b584-28b2160567bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134976312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3134976312
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1067314156
Short name T366
Test name
Test status
Simulation time 2589540567 ps
CPU time 1.83 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:27 PM PDT 24
Peak memory 195384 kb
Host smart-f89e3108-df70-4290-8c8e-43b8e09c8a37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067314156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1067314156
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2193331406
Short name T375
Test name
Test status
Simulation time 929945596 ps
CPU time 2.04 seconds
Started Jul 24 05:22:15 PM PDT 24
Finished Jul 24 05:22:18 PM PDT 24
Peak memory 199012 kb
Host smart-ef147ac9-4be4-4c63-a52a-96f9e1e00771
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193331406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2193331406
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2824608604
Short name T403
Test name
Test status
Simulation time 8165451389 ps
CPU time 7.65 seconds
Started Jul 24 05:22:19 PM PDT 24
Finished Jul 24 05:22:27 PM PDT 24
Peak memory 198864 kb
Host smart-31e7cb67-2eeb-4a8d-b6d5-8a9826023764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824608604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2824608604
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2167093254
Short name T321
Test name
Test status
Simulation time 501997601 ps
CPU time 1.4 seconds
Started Jul 24 05:22:13 PM PDT 24
Finished Jul 24 05:22:15 PM PDT 24
Peak memory 196204 kb
Host smart-b94a44f9-1b94-46a4-aaf9-1c4e54842689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167093254 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2167093254
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1795161674
Short name T29
Test name
Test status
Simulation time 532662980 ps
CPU time 0.77 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:25 PM PDT 24
Peak memory 193744 kb
Host smart-a085820f-800e-46fb-b62b-e0b6279d9a3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795161674 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1795161674
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1114950152
Short name T294
Test name
Test status
Simulation time 462622710 ps
CPU time 1.22 seconds
Started Jul 24 05:22:14 PM PDT 24
Finished Jul 24 05:22:16 PM PDT 24
Peak memory 184172 kb
Host smart-58e99e1f-912a-4b0e-bf3b-9bcdc7683a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114950152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1114950152
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3652694712
Short name T418
Test name
Test status
Simulation time 1415597718 ps
CPU time 1.31 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:27 PM PDT 24
Peak memory 193460 kb
Host smart-cbd2fc76-d2bc-4754-8df1-e0c8a93c93d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652694712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3652694712
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4234219063
Short name T358
Test name
Test status
Simulation time 441599360 ps
CPU time 2.25 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:27 PM PDT 24
Peak memory 199056 kb
Host smart-55ed4c50-d56e-40d6-9c90-fd4f2545058b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234219063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4234219063
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1342535688
Short name T188
Test name
Test status
Simulation time 8349661915 ps
CPU time 13.38 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:40 PM PDT 24
Peak memory 198612 kb
Host smart-b57c4c2f-a1a5-4c98-a328-002696fa0f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342535688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1342535688
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3972848701
Short name T30
Test name
Test status
Simulation time 553993220 ps
CPU time 1.36 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:26 PM PDT 24
Peak memory 196824 kb
Host smart-910d6c52-f48d-4056-b2b1-836cd1829157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972848701 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3972848701
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3899939868
Short name T63
Test name
Test status
Simulation time 479068702 ps
CPU time 1.23 seconds
Started Jul 24 05:22:18 PM PDT 24
Finished Jul 24 05:22:19 PM PDT 24
Peak memory 194460 kb
Host smart-1c7e715c-44b5-42e8-b9ae-1fa08383afb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899939868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3899939868
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4117760985
Short name T287
Test name
Test status
Simulation time 409126311 ps
CPU time 0.66 seconds
Started Jul 24 05:22:23 PM PDT 24
Finished Jul 24 05:22:24 PM PDT 24
Peak memory 193436 kb
Host smart-5b5650e6-14b3-4fc3-98de-ce7eb25c9c03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117760985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.4117760985
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2197119951
Short name T394
Test name
Test status
Simulation time 1254795309 ps
CPU time 0.91 seconds
Started Jul 24 05:22:16 PM PDT 24
Finished Jul 24 05:22:17 PM PDT 24
Peak memory 194048 kb
Host smart-34edafe6-4716-4ec9-bd08-3b874f62bfee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197119951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2197119951
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3110233365
Short name T417
Test name
Test status
Simulation time 557280968 ps
CPU time 1.2 seconds
Started Jul 24 05:22:16 PM PDT 24
Finished Jul 24 05:22:17 PM PDT 24
Peak memory 199040 kb
Host smart-8da89aa0-0b02-427a-8cee-80089941704d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110233365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3110233365
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1757402578
Short name T350
Test name
Test status
Simulation time 4284429861 ps
CPU time 2.41 seconds
Started Jul 24 05:22:23 PM PDT 24
Finished Jul 24 05:22:25 PM PDT 24
Peak memory 198104 kb
Host smart-2f895ebb-23d4-448b-a90b-e7d2eb2eae5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757402578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1757402578
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2399214513
Short name T325
Test name
Test status
Simulation time 411679548 ps
CPU time 0.91 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:26 PM PDT 24
Peak memory 198180 kb
Host smart-117915b0-02e5-44e0-a6e6-4776482c0e80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399214513 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2399214513
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.356446076
Short name T72
Test name
Test status
Simulation time 447714317 ps
CPU time 0.91 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:25 PM PDT 24
Peak memory 193720 kb
Host smart-67baa0de-262d-45eb-980e-e1a1452f0850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356446076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.356446076
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.545645397
Short name T384
Test name
Test status
Simulation time 449617595 ps
CPU time 1.13 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:25 PM PDT 24
Peak memory 184204 kb
Host smart-a0df1bf7-6639-4fc7-bd3a-0dca30b6e623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545645397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.545645397
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.543396158
Short name T398
Test name
Test status
Simulation time 2520093277 ps
CPU time 3.97 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 195712 kb
Host smart-2c83f237-2fc8-4869-910d-9686a1b3a7cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543396158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.543396158
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2574408032
Short name T327
Test name
Test status
Simulation time 463054437 ps
CPU time 2.32 seconds
Started Jul 24 05:22:20 PM PDT 24
Finished Jul 24 05:22:23 PM PDT 24
Peak memory 199112 kb
Host smart-0f5019f5-0dad-420a-8516-763b48fdb01d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574408032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2574408032
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1516871934
Short name T342
Test name
Test status
Simulation time 8331289672 ps
CPU time 5.24 seconds
Started Jul 24 05:22:21 PM PDT 24
Finished Jul 24 05:22:26 PM PDT 24
Peak memory 198708 kb
Host smart-c306598d-7b1f-448d-b9d0-f57dbaccd77d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516871934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1516871934
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.34657819
Short name T370
Test name
Test status
Simulation time 550252018 ps
CPU time 0.81 seconds
Started Jul 24 05:22:19 PM PDT 24
Finished Jul 24 05:22:20 PM PDT 24
Peak memory 197656 kb
Host smart-db9f30e9-3934-4801-bf35-ee2299c07212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34657819 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.34657819
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1080829986
Short name T359
Test name
Test status
Simulation time 408399107 ps
CPU time 1.08 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:26 PM PDT 24
Peak memory 193812 kb
Host smart-c2db911b-a346-40b6-960b-777c0d56dda4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080829986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1080829986
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.292446809
Short name T386
Test name
Test status
Simulation time 424234641 ps
CPU time 1.07 seconds
Started Jul 24 05:22:15 PM PDT 24
Finished Jul 24 05:22:16 PM PDT 24
Peak memory 193464 kb
Host smart-02ecf64b-25eb-41e6-b739-779716c9e90c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292446809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.292446809
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1658879173
Short name T387
Test name
Test status
Simulation time 1307950295 ps
CPU time 2.91 seconds
Started Jul 24 05:22:23 PM PDT 24
Finished Jul 24 05:22:26 PM PDT 24
Peak memory 193344 kb
Host smart-eee506d5-2e0c-429f-8c91-2b5afba82946
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658879173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1658879173
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2396697256
Short name T285
Test name
Test status
Simulation time 494430672 ps
CPU time 1.74 seconds
Started Jul 24 05:22:14 PM PDT 24
Finished Jul 24 05:22:15 PM PDT 24
Peak memory 198800 kb
Host smart-aaa4caa7-b28c-4d4b-8694-c1a3669161d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396697256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2396697256
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2687355105
Short name T295
Test name
Test status
Simulation time 513379319 ps
CPU time 0.8 seconds
Started Jul 24 05:22:06 PM PDT 24
Finished Jul 24 05:22:07 PM PDT 24
Peak memory 184228 kb
Host smart-25bc0dc7-f8ca-482c-90c9-75bfa9effb79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687355105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2687355105
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.489262827
Short name T56
Test name
Test status
Simulation time 12848079870 ps
CPU time 6.3 seconds
Started Jul 24 05:21:56 PM PDT 24
Finished Jul 24 05:22:02 PM PDT 24
Peak memory 196864 kb
Host smart-1bafd69c-74c1-4b49-a532-d96ead66553e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489262827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.489262827
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.181507615
Short name T422
Test name
Test status
Simulation time 982589420 ps
CPU time 0.93 seconds
Started Jul 24 05:21:59 PM PDT 24
Finished Jul 24 05:22:00 PM PDT 24
Peak memory 192556 kb
Host smart-cbe575d8-fe64-4f69-91c3-f4c4382b5c11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181507615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.181507615
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2767772477
Short name T292
Test name
Test status
Simulation time 538396631 ps
CPU time 0.81 seconds
Started Jul 24 05:21:57 PM PDT 24
Finished Jul 24 05:21:59 PM PDT 24
Peak memory 195596 kb
Host smart-c6e2e4b0-48f2-4f16-952e-b4ce6dbeb21b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767772477 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2767772477
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1889448034
Short name T57
Test name
Test status
Simulation time 389944786 ps
CPU time 1.09 seconds
Started Jul 24 05:22:02 PM PDT 24
Finished Jul 24 05:22:04 PM PDT 24
Peak memory 193420 kb
Host smart-c74f6736-7b03-40ce-9e0b-ce5afd6bd81c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889448034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1889448034
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1031068248
Short name T421
Test name
Test status
Simulation time 512571797 ps
CPU time 0.98 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 184220 kb
Host smart-b316b724-68ad-41c1-ac05-ee98ad25f022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031068248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1031068248
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.221604464
Short name T382
Test name
Test status
Simulation time 520210904 ps
CPU time 0.64 seconds
Started Jul 24 05:21:58 PM PDT 24
Finished Jul 24 05:21:59 PM PDT 24
Peak memory 184172 kb
Host smart-f576abe6-7a30-4c06-b76f-4b83b79a59a5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221604464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.221604464
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4246225095
Short name T392
Test name
Test status
Simulation time 404525957 ps
CPU time 0.61 seconds
Started Jul 24 05:21:56 PM PDT 24
Finished Jul 24 05:21:57 PM PDT 24
Peak memory 184096 kb
Host smart-614ed5a5-e4d4-47fa-935d-6a366f7b2c2c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246225095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4246225095
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.105810835
Short name T385
Test name
Test status
Simulation time 1367110399 ps
CPU time 1.84 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 193892 kb
Host smart-19aaa4f7-59e7-4f91-9a9f-c31cdde61d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105810835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.105810835
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3660757919
Short name T357
Test name
Test status
Simulation time 467856328 ps
CPU time 1.83 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 199072 kb
Host smart-d0b9732e-17ae-44df-8e49-1963f7093d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660757919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3660757919
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1038744141
Short name T187
Test name
Test status
Simulation time 8215113542 ps
CPU time 2.9 seconds
Started Jul 24 05:22:05 PM PDT 24
Finished Jul 24 05:22:08 PM PDT 24
Peak memory 198752 kb
Host smart-b95ae447-dd0c-41f9-883e-603817262995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038744141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1038744141
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3161326659
Short name T378
Test name
Test status
Simulation time 358082747 ps
CPU time 0.94 seconds
Started Jul 24 05:22:23 PM PDT 24
Finished Jul 24 05:22:24 PM PDT 24
Peak memory 184268 kb
Host smart-86f080d7-1ee7-4ab2-a75f-d1cf6046ca48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161326659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3161326659
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1411744760
Short name T293
Test name
Test status
Simulation time 311686326 ps
CPU time 0.64 seconds
Started Jul 24 05:22:23 PM PDT 24
Finished Jul 24 05:22:24 PM PDT 24
Peak memory 193388 kb
Host smart-34c02252-d37a-4845-8ff9-1ee3f58a6e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411744760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1411744760
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.504919198
Short name T318
Test name
Test status
Simulation time 563959381 ps
CPU time 0.57 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 184224 kb
Host smart-bf677542-46dd-4f63-9925-5aeb8889300c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504919198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.504919198
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3459126852
Short name T345
Test name
Test status
Simulation time 463839713 ps
CPU time 1.25 seconds
Started Jul 24 05:22:19 PM PDT 24
Finished Jul 24 05:22:20 PM PDT 24
Peak memory 193396 kb
Host smart-3bcab32a-6ea7-4a4f-abd7-d4c8d2409b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459126852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3459126852
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2055938595
Short name T397
Test name
Test status
Simulation time 486708106 ps
CPU time 1.19 seconds
Started Jul 24 05:22:16 PM PDT 24
Finished Jul 24 05:22:18 PM PDT 24
Peak memory 184228 kb
Host smart-cd7dee95-79a0-4296-91f7-f25ac250490e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055938595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2055938595
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3889901337
Short name T314
Test name
Test status
Simulation time 446609288 ps
CPU time 0.7 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 184192 kb
Host smart-4af48b47-c737-453e-b00e-04a72c4d7cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889901337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3889901337
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2294300267
Short name T310
Test name
Test status
Simulation time 429090911 ps
CPU time 0.87 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:25 PM PDT 24
Peak memory 184212 kb
Host smart-beff75e3-e24c-456c-846a-5825ac94ebaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294300267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2294300267
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.570796367
Short name T288
Test name
Test status
Simulation time 450155054 ps
CPU time 0.72 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 184232 kb
Host smart-3d11a755-1f1d-4ca1-80f0-b53e4e965f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570796367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.570796367
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.712599572
Short name T305
Test name
Test status
Simulation time 509463312 ps
CPU time 1.21 seconds
Started Jul 24 05:22:15 PM PDT 24
Finished Jul 24 05:22:16 PM PDT 24
Peak memory 193396 kb
Host smart-1e1adf67-1487-400c-9775-5f3fad0d2e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712599572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.712599572
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3494762945
Short name T410
Test name
Test status
Simulation time 400205633 ps
CPU time 0.82 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 184184 kb
Host smart-3cf7bea3-8f45-4bff-aee4-fb14a48d4042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494762945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3494762945
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1769113184
Short name T62
Test name
Test status
Simulation time 530047045 ps
CPU time 1.8 seconds
Started Jul 24 05:22:07 PM PDT 24
Finished Jul 24 05:22:09 PM PDT 24
Peak memory 192348 kb
Host smart-1414eada-8ad9-4480-8d62-bd32cb37ab1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769113184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1769113184
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.914864980
Short name T35
Test name
Test status
Simulation time 1227216495 ps
CPU time 2.23 seconds
Started Jul 24 05:22:03 PM PDT 24
Finished Jul 24 05:22:05 PM PDT 24
Peak memory 192584 kb
Host smart-12ff913d-aadc-4d67-b7f9-f0d23a1bdf5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914864980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.914864980
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2915840150
Short name T352
Test name
Test status
Simulation time 832447756 ps
CPU time 0.87 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 192608 kb
Host smart-1fee4418-6bc2-460f-9507-321688e9ceba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915840150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2915840150
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2986299466
Short name T351
Test name
Test status
Simulation time 325678922 ps
CPU time 0.7 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 196152 kb
Host smart-a008adc1-8496-42ae-9826-726435923e0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986299466 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2986299466
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3735942485
Short name T360
Test name
Test status
Simulation time 341022003 ps
CPU time 0.66 seconds
Started Jul 24 05:21:56 PM PDT 24
Finished Jul 24 05:21:57 PM PDT 24
Peak memory 193444 kb
Host smart-555c183b-046c-4a3e-b4f1-e1aea63de2b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735942485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3735942485
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2319114382
Short name T393
Test name
Test status
Simulation time 402673424 ps
CPU time 0.59 seconds
Started Jul 24 05:21:54 PM PDT 24
Finished Jul 24 05:21:54 PM PDT 24
Peak memory 193420 kb
Host smart-bb401f75-831d-4c17-974f-1fa6eff0e395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319114382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2319114382
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3703553487
Short name T400
Test name
Test status
Simulation time 321735613 ps
CPU time 0.74 seconds
Started Jul 24 05:21:57 PM PDT 24
Finished Jul 24 05:21:58 PM PDT 24
Peak memory 184148 kb
Host smart-afff35c5-5029-4d57-8b68-5e5764c7c71b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703553487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3703553487
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3830142325
Short name T298
Test name
Test status
Simulation time 509272578 ps
CPU time 1.3 seconds
Started Jul 24 05:21:57 PM PDT 24
Finished Jul 24 05:21:59 PM PDT 24
Peak memory 184140 kb
Host smart-379d2dbf-1545-4a7c-95d6-769218254514
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830142325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3830142325
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2281630384
Short name T340
Test name
Test status
Simulation time 1848336694 ps
CPU time 1.43 seconds
Started Jul 24 05:21:57 PM PDT 24
Finished Jul 24 05:21:58 PM PDT 24
Peak memory 194364 kb
Host smart-fed2c26e-e3f3-48b8-8979-48c5e7309a68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281630384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2281630384
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2026204885
Short name T336
Test name
Test status
Simulation time 291310417 ps
CPU time 1.37 seconds
Started Jul 24 05:21:57 PM PDT 24
Finished Jul 24 05:21:58 PM PDT 24
Peak memory 198764 kb
Host smart-de84789c-9573-42fd-88eb-56311e020175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026204885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2026204885
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1840573387
Short name T412
Test name
Test status
Simulation time 4549584788 ps
CPU time 7.18 seconds
Started Jul 24 05:22:01 PM PDT 24
Finished Jul 24 05:22:09 PM PDT 24
Peak memory 198732 kb
Host smart-2d0934ad-f16c-438c-8975-e98e6f016b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840573387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1840573387
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.486258006
Short name T389
Test name
Test status
Simulation time 315342697 ps
CPU time 0.64 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:24 PM PDT 24
Peak memory 184188 kb
Host smart-9046b690-82f9-4543-b4c5-52422a31c2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486258006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.486258006
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2423943591
Short name T304
Test name
Test status
Simulation time 384750785 ps
CPU time 0.71 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 184196 kb
Host smart-8f19ccbd-1a1f-4626-ba9b-d7efdb338fff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423943591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2423943591
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.776793378
Short name T300
Test name
Test status
Simulation time 427345058 ps
CPU time 1.02 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:30 PM PDT 24
Peak memory 184212 kb
Host smart-a2d80ada-0e0b-4849-81e9-2e9d514c36f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776793378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.776793378
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.229346747
Short name T377
Test name
Test status
Simulation time 289055867 ps
CPU time 0.79 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:27 PM PDT 24
Peak memory 193416 kb
Host smart-d36da6e7-1186-4776-b7f2-b3d72a077c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229346747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.229346747
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2062914805
Short name T297
Test name
Test status
Simulation time 442920849 ps
CPU time 0.67 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 184196 kb
Host smart-a8f211fd-e30b-4938-b8d5-2260944b2f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062914805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2062914805
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3248498403
Short name T286
Test name
Test status
Simulation time 328929663 ps
CPU time 0.98 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:30 PM PDT 24
Peak memory 193452 kb
Host smart-eb80db61-bd45-4959-9e64-08cdc17c4c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248498403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3248498403
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.754272343
Short name T349
Test name
Test status
Simulation time 406854668 ps
CPU time 0.97 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 184188 kb
Host smart-10af9aec-4611-4e47-96d1-2c20355ea8f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754272343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.754272343
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.172401227
Short name T317
Test name
Test status
Simulation time 493533015 ps
CPU time 0.71 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 184136 kb
Host smart-e46a5763-a49a-4fe9-a75c-8abd2c3e222d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172401227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.172401227
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1197803522
Short name T367
Test name
Test status
Simulation time 287936425 ps
CPU time 0.99 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 193436 kb
Host smart-b9f89e8b-3319-43e6-a655-92112e6b9839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197803522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1197803522
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1284698071
Short name T361
Test name
Test status
Simulation time 333127291 ps
CPU time 0.97 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 184100 kb
Host smart-0c4575fc-1fc0-4f4a-a166-ab3d244423d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284698071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1284698071
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2592719838
Short name T60
Test name
Test status
Simulation time 525589007 ps
CPU time 1.03 seconds
Started Jul 24 05:22:14 PM PDT 24
Finished Jul 24 05:22:16 PM PDT 24
Peak memory 192412 kb
Host smart-178d9a35-7f4e-4037-91f6-ae463a030d76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592719838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2592719838
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1026190096
Short name T59
Test name
Test status
Simulation time 8901122387 ps
CPU time 12.27 seconds
Started Jul 24 05:22:04 PM PDT 24
Finished Jul 24 05:22:16 PM PDT 24
Peak memory 192668 kb
Host smart-4bb042b1-a6ef-4a6b-936e-29262b9c332b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026190096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1026190096
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.433049663
Short name T414
Test name
Test status
Simulation time 1141928488 ps
CPU time 2.31 seconds
Started Jul 24 05:22:07 PM PDT 24
Finished Jul 24 05:22:10 PM PDT 24
Peak memory 193508 kb
Host smart-0b46cf35-07fa-4165-9044-945519bbc56c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433049663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.433049663
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1849849842
Short name T316
Test name
Test status
Simulation time 499089157 ps
CPU time 1.32 seconds
Started Jul 24 05:22:06 PM PDT 24
Finished Jul 24 05:22:07 PM PDT 24
Peak memory 196356 kb
Host smart-5d60eaaa-f208-4c2a-adb9-5c890088230a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849849842 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1849849842
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2457681668
Short name T58
Test name
Test status
Simulation time 346041288 ps
CPU time 1.1 seconds
Started Jul 24 05:22:03 PM PDT 24
Finished Jul 24 05:22:04 PM PDT 24
Peak memory 193460 kb
Host smart-97c2ec28-b2d7-42de-8ff3-051e3211ab13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457681668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2457681668
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2528904091
Short name T390
Test name
Test status
Simulation time 290870459 ps
CPU time 0.62 seconds
Started Jul 24 05:22:03 PM PDT 24
Finished Jul 24 05:22:04 PM PDT 24
Peak memory 184240 kb
Host smart-03e1cf36-3907-4afd-88e1-639b81010d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528904091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2528904091
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3454381815
Short name T391
Test name
Test status
Simulation time 461545072 ps
CPU time 0.78 seconds
Started Jul 24 05:22:05 PM PDT 24
Finished Jul 24 05:22:06 PM PDT 24
Peak memory 184152 kb
Host smart-0f58e86f-a41d-4f28-b00c-ff551abfabcf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454381815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3454381815
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3823736865
Short name T330
Test name
Test status
Simulation time 516094066 ps
CPU time 1.19 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 184140 kb
Host smart-07648209-88af-4968-a579-08bfc60a0abc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823736865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3823736865
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1007257434
Short name T411
Test name
Test status
Simulation time 1356515762 ps
CPU time 3.77 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:14 PM PDT 24
Peak memory 192280 kb
Host smart-0f442153-2182-4c7c-8ee2-480f8cec09f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007257434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1007257434
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1659267335
Short name T289
Test name
Test status
Simulation time 424493317 ps
CPU time 1.56 seconds
Started Jul 24 05:22:06 PM PDT 24
Finished Jul 24 05:22:08 PM PDT 24
Peak memory 198684 kb
Host smart-5a4a1159-8c41-4ecc-90a6-fc40afec906b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659267335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1659267335
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.139987524
Short name T353
Test name
Test status
Simulation time 4622671028 ps
CPU time 2.49 seconds
Started Jul 24 05:22:04 PM PDT 24
Finished Jul 24 05:22:07 PM PDT 24
Peak memory 198328 kb
Host smart-cda7719b-db2c-499c-8f12-a213b306d251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139987524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.139987524
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.926693762
Short name T420
Test name
Test status
Simulation time 381203488 ps
CPU time 1.12 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:26 PM PDT 24
Peak memory 193416 kb
Host smart-aa25c195-7a4f-400e-a8fd-7fe994e9da44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926693762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.926693762
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2096244559
Short name T415
Test name
Test status
Simulation time 322432302 ps
CPU time 0.94 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 193416 kb
Host smart-27079bf5-7198-4d39-ad37-2b89383ef351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096244559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2096244559
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1723948814
Short name T356
Test name
Test status
Simulation time 292177434 ps
CPU time 0.63 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 184232 kb
Host smart-d0ea8799-8f16-4f15-adc3-cf4720999727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723948814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1723948814
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2070400299
Short name T406
Test name
Test status
Simulation time 490889973 ps
CPU time 1.21 seconds
Started Jul 24 05:22:30 PM PDT 24
Finished Jul 24 05:22:32 PM PDT 24
Peak memory 193396 kb
Host smart-fdcd8d3a-4c06-4eda-8ae9-9aede6733de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070400299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2070400299
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3450576500
Short name T322
Test name
Test status
Simulation time 378450272 ps
CPU time 1.04 seconds
Started Jul 24 05:22:23 PM PDT 24
Finished Jul 24 05:22:25 PM PDT 24
Peak memory 193388 kb
Host smart-e6430ce5-14cc-4d6e-a4ef-9d90de84843e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450576500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3450576500
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2461655132
Short name T404
Test name
Test status
Simulation time 456277552 ps
CPU time 0.66 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:27 PM PDT 24
Peak memory 184216 kb
Host smart-f783daae-306b-49dc-b6ee-a7c850abd1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461655132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2461655132
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1930600059
Short name T335
Test name
Test status
Simulation time 323810076 ps
CPU time 0.99 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:30 PM PDT 24
Peak memory 184196 kb
Host smart-e6844bc3-6161-4127-9124-f6c332497934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930600059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1930600059
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3418834614
Short name T343
Test name
Test status
Simulation time 370245314 ps
CPU time 1.01 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 193392 kb
Host smart-ddff5922-0106-4c4d-8e8a-cf8ef272e116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418834614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3418834614
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.528836036
Short name T374
Test name
Test status
Simulation time 314752238 ps
CPU time 0.65 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:27 PM PDT 24
Peak memory 184232 kb
Host smart-2e65601a-e4cf-47b1-a8de-157ddc5f05fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528836036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.528836036
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2500282866
Short name T413
Test name
Test status
Simulation time 301822264 ps
CPU time 0.96 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 184208 kb
Host smart-852fd7cb-23fb-4866-a9ad-7bd19f344327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500282866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2500282866
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3073797832
Short name T408
Test name
Test status
Simulation time 570778380 ps
CPU time 0.79 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 196648 kb
Host smart-a2d0b423-f271-47f7-a91b-c831965eda54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073797832 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3073797832
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3810190894
Short name T52
Test name
Test status
Simulation time 402150692 ps
CPU time 0.75 seconds
Started Jul 24 05:22:12 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 193700 kb
Host smart-70f86d58-7c89-420f-9761-2bb1a4c326f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810190894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3810190894
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1204809976
Short name T307
Test name
Test status
Simulation time 474733314 ps
CPU time 1.16 seconds
Started Jul 24 05:22:06 PM PDT 24
Finished Jul 24 05:22:08 PM PDT 24
Peak memory 184232 kb
Host smart-a44f3a16-4186-400f-a38c-44f993baba46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204809976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1204809976
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.216816722
Short name T347
Test name
Test status
Simulation time 2327333948 ps
CPU time 3.38 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:15 PM PDT 24
Peak memory 192544 kb
Host smart-2f82ca26-f203-4174-a18d-356560ba0ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216816722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.216816722
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3708929678
Short name T423
Test name
Test status
Simulation time 527450808 ps
CPU time 1.47 seconds
Started Jul 24 05:22:04 PM PDT 24
Finished Jul 24 05:22:06 PM PDT 24
Peak memory 199064 kb
Host smart-d5d8faa3-3d86-4d85-8643-35be8a191082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708929678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3708929678
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1797442859
Short name T369
Test name
Test status
Simulation time 5075526728 ps
CPU time 3.93 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 197212 kb
Host smart-6cc4cde0-ccba-46e7-bb03-f6427ddc14e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797442859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1797442859
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1178505478
Short name T341
Test name
Test status
Simulation time 629084003 ps
CPU time 1.05 seconds
Started Jul 24 05:22:03 PM PDT 24
Finished Jul 24 05:22:04 PM PDT 24
Peak memory 198884 kb
Host smart-85f42750-077b-495f-8117-588fdfced74e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178505478 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1178505478
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.654154332
Short name T71
Test name
Test status
Simulation time 434766886 ps
CPU time 0.91 seconds
Started Jul 24 05:22:12 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 194464 kb
Host smart-1e473c8f-e358-4089-b9b2-0c75c4ab95af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654154332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.654154332
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3879960711
Short name T380
Test name
Test status
Simulation time 518478925 ps
CPU time 0.57 seconds
Started Jul 24 05:22:03 PM PDT 24
Finished Jul 24 05:22:04 PM PDT 24
Peak memory 193444 kb
Host smart-a5071625-8a83-41b7-b486-f78b8a7a7e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879960711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3879960711
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3998842006
Short name T68
Test name
Test status
Simulation time 1063068485 ps
CPU time 1.01 seconds
Started Jul 24 05:22:04 PM PDT 24
Finished Jul 24 05:22:05 PM PDT 24
Peak memory 193464 kb
Host smart-2d5b1f50-7bfd-4abe-8f8a-e343b3d84541
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998842006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3998842006
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3426328566
Short name T338
Test name
Test status
Simulation time 661635981 ps
CPU time 1.79 seconds
Started Jul 24 05:22:01 PM PDT 24
Finished Jul 24 05:22:03 PM PDT 24
Peak memory 199016 kb
Host smart-5e627b40-d10c-47fe-b210-aa0100a6c30b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426328566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3426328566
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4133963455
Short name T311
Test name
Test status
Simulation time 8147624583 ps
CPU time 4.24 seconds
Started Jul 24 05:22:03 PM PDT 24
Finished Jul 24 05:22:07 PM PDT 24
Peak memory 198664 kb
Host smart-7a5c9ffc-3035-48bf-83ef-6f52b16fdb7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133963455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.4133963455
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1666507981
Short name T320
Test name
Test status
Simulation time 389473872 ps
CPU time 0.93 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 196448 kb
Host smart-e46e48bd-277c-49ec-b3bf-576960878677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666507981 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1666507981
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3899958406
Short name T344
Test name
Test status
Simulation time 531203648 ps
CPU time 0.75 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:09 PM PDT 24
Peak memory 192500 kb
Host smart-894871fc-abb2-4bfe-aba1-82997f6dacb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899958406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3899958406
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1903567373
Short name T315
Test name
Test status
Simulation time 374254093 ps
CPU time 0.81 seconds
Started Jul 24 05:22:13 PM PDT 24
Finished Jul 24 05:22:14 PM PDT 24
Peak memory 184244 kb
Host smart-a5441453-60bc-4854-9bbf-e2510d2e7da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903567373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1903567373
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1852403010
Short name T65
Test name
Test status
Simulation time 1454152364 ps
CPU time 0.81 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:10 PM PDT 24
Peak memory 184220 kb
Host smart-d0adbf6a-7d31-4b1b-aea9-80e491b69381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852403010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1852403010
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.990648797
Short name T332
Test name
Test status
Simulation time 617500322 ps
CPU time 1.52 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 199064 kb
Host smart-d7647446-15e8-458b-847a-252125b42de1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990648797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.990648797
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3743035510
Short name T354
Test name
Test status
Simulation time 4812153791 ps
CPU time 2.49 seconds
Started Jul 24 05:22:01 PM PDT 24
Finished Jul 24 05:22:04 PM PDT 24
Peak memory 198348 kb
Host smart-d554cb93-f2a7-4f90-9763-a8b99b08ae29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743035510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3743035510
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.242166340
Short name T291
Test name
Test status
Simulation time 355604220 ps
CPU time 1.01 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:10 PM PDT 24
Peak memory 196156 kb
Host smart-54add38b-2dbe-4362-a746-1be33aa85a3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242166340 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.242166340
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3340810611
Short name T405
Test name
Test status
Simulation time 305468532 ps
CPU time 1.02 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:13 PM PDT 24
Peak memory 193700 kb
Host smart-8856da45-c409-449e-adda-b6caa2757f69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340810611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3340810611
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4011335502
Short name T399
Test name
Test status
Simulation time 291022500 ps
CPU time 0.65 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 193300 kb
Host smart-c63e26ed-2bba-4bdd-98f3-624fc996fa16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011335502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.4011335502
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.4179625318
Short name T388
Test name
Test status
Simulation time 2346696066 ps
CPU time 1.12 seconds
Started Jul 24 05:22:09 PM PDT 24
Finished Jul 24 05:22:10 PM PDT 24
Peak memory 195292 kb
Host smart-62f97a4e-2189-46c3-ac20-2bb516c8528c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179625318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.4179625318
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1097937088
Short name T365
Test name
Test status
Simulation time 500854303 ps
CPU time 1.53 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 199040 kb
Host smart-51e588c7-907b-4e75-83bd-c56ce788845e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097937088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1097937088
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4151474855
Short name T326
Test name
Test status
Simulation time 8368087986 ps
CPU time 6.61 seconds
Started Jul 24 05:22:12 PM PDT 24
Finished Jul 24 05:22:19 PM PDT 24
Peak memory 198732 kb
Host smart-a9af84e5-b757-4fec-af98-351121ff0a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151474855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.4151474855
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2239499510
Short name T328
Test name
Test status
Simulation time 745300377 ps
CPU time 0.9 seconds
Started Jul 24 05:22:16 PM PDT 24
Finished Jul 24 05:22:17 PM PDT 24
Peak memory 198524 kb
Host smart-3bfa5693-09d6-41ba-bcd3-4ade21beb046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239499510 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2239499510
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1410315550
Short name T409
Test name
Test status
Simulation time 504308339 ps
CPU time 1.35 seconds
Started Jul 24 05:22:10 PM PDT 24
Finished Jul 24 05:22:11 PM PDT 24
Peak memory 194360 kb
Host smart-a71b4ae2-ff1a-4975-ac24-d496ea9868ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410315550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1410315550
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2742427405
Short name T333
Test name
Test status
Simulation time 506620634 ps
CPU time 0.9 seconds
Started Jul 24 05:22:11 PM PDT 24
Finished Jul 24 05:22:12 PM PDT 24
Peak memory 193452 kb
Host smart-84206de7-81e9-45a9-afce-0f409df6b8ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742427405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2742427405
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3030994569
Short name T372
Test name
Test status
Simulation time 2143380534 ps
CPU time 1.04 seconds
Started Jul 24 05:22:20 PM PDT 24
Finished Jul 24 05:22:22 PM PDT 24
Peak memory 195420 kb
Host smart-18f6c998-1502-4cd7-bcd5-cf8d3a453c64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030994569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3030994569
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.129672635
Short name T381
Test name
Test status
Simulation time 804067641 ps
CPU time 1.29 seconds
Started Jul 24 05:22:12 PM PDT 24
Finished Jul 24 05:22:14 PM PDT 24
Peak memory 198880 kb
Host smart-b4d67b99-09f2-491f-a181-01318e0cf8d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129672635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.129672635
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2678725021
Short name T32
Test name
Test status
Simulation time 8144115361 ps
CPU time 13.41 seconds
Started Jul 24 05:22:12 PM PDT 24
Finished Jul 24 05:22:25 PM PDT 24
Peak memory 198880 kb
Host smart-4e9ad1a9-a284-4753-8570-b21ad4d493e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678725021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2678725021
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.569564090
Short name T226
Test name
Test status
Simulation time 38094562779 ps
CPU time 27.73 seconds
Started Jul 24 05:19:20 PM PDT 24
Finished Jul 24 05:19:47 PM PDT 24
Peak memory 191940 kb
Host smart-aab7e38a-4b48-41e0-8140-48ce37d5bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569564090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.569564090
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.537544614
Short name T235
Test name
Test status
Simulation time 541212293 ps
CPU time 1.39 seconds
Started Jul 24 05:19:23 PM PDT 24
Finished Jul 24 05:19:25 PM PDT 24
Peak memory 191776 kb
Host smart-754730ae-730f-4d64-a61e-904b6be308b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537544614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.537544614
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1150920341
Short name T267
Test name
Test status
Simulation time 10066788690 ps
CPU time 8.51 seconds
Started Jul 24 05:19:22 PM PDT 24
Finished Jul 24 05:19:31 PM PDT 24
Peak memory 191872 kb
Host smart-c1a52079-8a1a-4bbc-9054-55c216aa6665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150920341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1150920341
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2816902537
Short name T12
Test name
Test status
Simulation time 8477063610 ps
CPU time 5.57 seconds
Started Jul 24 05:19:23 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 215808 kb
Host smart-42612770-436d-4af6-8138-f5eb1195abc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816902537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2816902537
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.844861516
Short name T248
Test name
Test status
Simulation time 473330482 ps
CPU time 1.26 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:27 PM PDT 24
Peak memory 191744 kb
Host smart-b98b0c36-e83f-4831-9ed2-71e88779480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844861516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.844861516
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2780825566
Short name T241
Test name
Test status
Simulation time 57971904872 ps
CPU time 38.16 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:20:07 PM PDT 24
Peak memory 191868 kb
Host smart-cea0b696-56d2-4f17-8877-9012a7f27ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780825566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2780825566
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3048864451
Short name T209
Test name
Test status
Simulation time 592059762 ps
CPU time 1.42 seconds
Started Jul 24 05:19:27 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 196600 kb
Host smart-b180ba1b-e0f6-4804-ab47-2b4756a0a5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048864451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3048864451
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2502698111
Short name T9
Test name
Test status
Simulation time 39018927323 ps
CPU time 4.75 seconds
Started Jul 24 05:19:30 PM PDT 24
Finished Jul 24 05:19:35 PM PDT 24
Peak memory 191724 kb
Host smart-44e89312-1a88-4e89-91af-4b0a84ae2de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502698111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2502698111
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1912934469
Short name T213
Test name
Test status
Simulation time 546489544 ps
CPU time 1.44 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:19:31 PM PDT 24
Peak memory 191780 kb
Host smart-d25d04e6-b9b7-41fd-8364-599cd81304c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912934469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1912934469
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3360500214
Short name T242
Test name
Test status
Simulation time 29307943042 ps
CPU time 17.83 seconds
Started Jul 24 05:19:36 PM PDT 24
Finished Jul 24 05:19:54 PM PDT 24
Peak memory 196888 kb
Host smart-127f9112-0a69-42bb-bab6-2fd43758a492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360500214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3360500214
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.4216103105
Short name T216
Test name
Test status
Simulation time 410548990 ps
CPU time 0.68 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:28 PM PDT 24
Peak memory 196656 kb
Host smart-54f932df-8ec2-4bde-b3cf-58e0e93fe4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216103105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.4216103105
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1527026810
Short name T284
Test name
Test status
Simulation time 31756494587 ps
CPU time 11.08 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:19:40 PM PDT 24
Peak memory 191868 kb
Host smart-6dc8615a-b8e9-48e1-9797-0089f68b81a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527026810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1527026810
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2044576831
Short name T222
Test name
Test status
Simulation time 465649945 ps
CPU time 0.73 seconds
Started Jul 24 05:19:27 PM PDT 24
Finished Jul 24 05:19:28 PM PDT 24
Peak memory 191736 kb
Host smart-8216f338-0085-44e6-a377-4fb94828ea21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044576831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2044576831
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1484403081
Short name T181
Test name
Test status
Simulation time 464947583 ps
CPU time 1.3 seconds
Started Jul 24 05:19:36 PM PDT 24
Finished Jul 24 05:19:38 PM PDT 24
Peak memory 196436 kb
Host smart-a05bc859-cea5-4e34-809d-3a896c7a8c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484403081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1484403081
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2984138072
Short name T217
Test name
Test status
Simulation time 6195495643 ps
CPU time 8.8 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:35 PM PDT 24
Peak memory 196884 kb
Host smart-39859ac5-c5b4-42a8-b697-dc9ef649dcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984138072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2984138072
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1185831191
Short name T239
Test name
Test status
Simulation time 514907758 ps
CPU time 0.99 seconds
Started Jul 24 05:19:30 PM PDT 24
Finished Jul 24 05:19:32 PM PDT 24
Peak memory 191688 kb
Host smart-5797cf7e-40ba-4a91-980f-0e677a83513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185831191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1185831191
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1078196945
Short name T244
Test name
Test status
Simulation time 30004809035 ps
CPU time 27.33 seconds
Started Jul 24 05:19:31 PM PDT 24
Finished Jul 24 05:19:58 PM PDT 24
Peak memory 191892 kb
Host smart-a3cf9277-fb1f-4c72-b3c8-ffb3f765ef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078196945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1078196945
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1030323346
Short name T283
Test name
Test status
Simulation time 609667572 ps
CPU time 0.68 seconds
Started Jul 24 05:19:34 PM PDT 24
Finished Jul 24 05:19:34 PM PDT 24
Peak memory 191652 kb
Host smart-ba1a860b-41ad-487b-b42a-2084d785c7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030323346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1030323346
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1962255195
Short name T40
Test name
Test status
Simulation time 14625327010 ps
CPU time 6.26 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:19:34 PM PDT 24
Peak memory 191864 kb
Host smart-2dcf6f4c-fb78-472c-9b52-773517615fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962255195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1962255195
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3861347058
Short name T258
Test name
Test status
Simulation time 443680213 ps
CPU time 0.72 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 191648 kb
Host smart-b7bd32ba-6d70-492b-9e3d-1af2b51e2185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861347058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3861347058
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2875228043
Short name T214
Test name
Test status
Simulation time 54588054768 ps
CPU time 28.51 seconds
Started Jul 24 05:19:35 PM PDT 24
Finished Jul 24 05:20:03 PM PDT 24
Peak memory 196896 kb
Host smart-1316864a-a0d7-40b7-ac11-b8b7f1e570aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875228043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2875228043
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2639749001
Short name T207
Test name
Test status
Simulation time 450233939 ps
CPU time 1.19 seconds
Started Jul 24 05:19:31 PM PDT 24
Finished Jul 24 05:19:33 PM PDT 24
Peak memory 191804 kb
Host smart-613e7318-817a-4684-ad6c-dd1bc2d7a528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639749001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2639749001
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1623885360
Short name T186
Test name
Test status
Simulation time 441018587 ps
CPU time 0.78 seconds
Started Jul 24 05:19:36 PM PDT 24
Finished Jul 24 05:19:37 PM PDT 24
Peak memory 196364 kb
Host smart-34f0f0cf-52a0-482f-91e1-98620d64abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623885360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1623885360
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1253820917
Short name T203
Test name
Test status
Simulation time 28121301799 ps
CPU time 30.17 seconds
Started Jul 24 05:19:33 PM PDT 24
Finished Jul 24 05:20:03 PM PDT 24
Peak memory 196864 kb
Host smart-55edafa7-2682-4ba3-ad92-90cffce50106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253820917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1253820917
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2497277249
Short name T271
Test name
Test status
Simulation time 575517579 ps
CPU time 0.8 seconds
Started Jul 24 05:19:32 PM PDT 24
Finished Jul 24 05:19:33 PM PDT 24
Peak memory 196568 kb
Host smart-58600f9f-5c80-4527-b63c-f8d97e6286ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497277249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2497277249
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.712317959
Short name T264
Test name
Test status
Simulation time 37801411258 ps
CPU time 24.85 seconds
Started Jul 24 05:19:36 PM PDT 24
Finished Jul 24 05:20:01 PM PDT 24
Peak memory 191648 kb
Host smart-d75ea99c-13c6-4a82-845a-bf53186c5612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712317959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.712317959
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3878658062
Short name T279
Test name
Test status
Simulation time 546738914 ps
CPU time 1.38 seconds
Started Jul 24 05:19:32 PM PDT 24
Finished Jul 24 05:19:33 PM PDT 24
Peak memory 191768 kb
Host smart-d3c39a81-1901-4612-8e3d-1bee3fda2c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878658062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3878658062
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2868565695
Short name T275
Test name
Test status
Simulation time 12719915361 ps
CPU time 2.13 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 191836 kb
Host smart-e9a9aa2a-296a-4cb6-a0e3-b3943a90fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868565695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2868565695
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2484397111
Short name T15
Test name
Test status
Simulation time 4396504327 ps
CPU time 2.19 seconds
Started Jul 24 05:19:33 PM PDT 24
Finished Jul 24 05:19:35 PM PDT 24
Peak memory 215856 kb
Host smart-4ff4db31-7df1-4faf-9fb4-f0981c4a008a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484397111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2484397111
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.589613404
Short name T262
Test name
Test status
Simulation time 489028422 ps
CPU time 0.75 seconds
Started Jul 24 05:19:21 PM PDT 24
Finished Jul 24 05:19:22 PM PDT 24
Peak memory 196532 kb
Host smart-638edfdc-27b7-41cd-98aa-e1adb1e11683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589613404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.589613404
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3828060916
Short name T278
Test name
Test status
Simulation time 24250429425 ps
CPU time 29.72 seconds
Started Jul 24 05:19:33 PM PDT 24
Finished Jul 24 05:20:03 PM PDT 24
Peak memory 191840 kb
Host smart-b1400072-3598-47fe-a69f-0c1cf7e00725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828060916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3828060916
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1207676877
Short name T256
Test name
Test status
Simulation time 659987357 ps
CPU time 0.68 seconds
Started Jul 24 05:19:35 PM PDT 24
Finished Jul 24 05:19:35 PM PDT 24
Peak memory 191664 kb
Host smart-e9ec96c3-78d7-4be9-b6c1-42344ecb3873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207676877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1207676877
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1650011934
Short name T245
Test name
Test status
Simulation time 3494784317 ps
CPU time 1.8 seconds
Started Jul 24 05:19:47 PM PDT 24
Finished Jul 24 05:19:49 PM PDT 24
Peak memory 191792 kb
Host smart-e9cd50c0-e36e-4154-aef8-09b72b675863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650011934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1650011934
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.4260226111
Short name T260
Test name
Test status
Simulation time 419311996 ps
CPU time 0.72 seconds
Started Jul 24 05:19:30 PM PDT 24
Finished Jul 24 05:19:31 PM PDT 24
Peak memory 196528 kb
Host smart-465c6cc8-2c04-4fec-8736-73cbd71f0993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260226111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.4260226111
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3860143359
Short name T195
Test name
Test status
Simulation time 37746683852 ps
CPU time 12.91 seconds
Started Jul 24 05:19:32 PM PDT 24
Finished Jul 24 05:19:45 PM PDT 24
Peak memory 191864 kb
Host smart-f661e779-f318-4e69-b093-bd99ee94ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860143359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3860143359
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2392745964
Short name T243
Test name
Test status
Simulation time 576979265 ps
CPU time 1.38 seconds
Started Jul 24 05:19:53 PM PDT 24
Finished Jul 24 05:19:54 PM PDT 24
Peak memory 191672 kb
Host smart-35845fee-e6ee-453b-82d5-3a52649c689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392745964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2392745964
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3641143936
Short name T220
Test name
Test status
Simulation time 15673680636 ps
CPU time 5.99 seconds
Started Jul 24 05:19:34 PM PDT 24
Finished Jul 24 05:19:41 PM PDT 24
Peak memory 196876 kb
Host smart-90abf66d-5532-4d5a-9582-ad941c81a6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641143936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3641143936
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.212527940
Short name T268
Test name
Test status
Simulation time 515474747 ps
CPU time 1.23 seconds
Started Jul 24 05:19:35 PM PDT 24
Finished Jul 24 05:19:37 PM PDT 24
Peak memory 191692 kb
Host smart-19603393-835c-4a82-a558-b8b1305a56a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212527940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.212527940
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3540004869
Short name T229
Test name
Test status
Simulation time 26941832600 ps
CPU time 21.18 seconds
Started Jul 24 05:19:34 PM PDT 24
Finished Jul 24 05:19:55 PM PDT 24
Peak memory 191816 kb
Host smart-000202cc-bb54-4e08-9da6-232729387d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540004869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3540004869
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3730535175
Short name T18
Test name
Test status
Simulation time 502588615 ps
CPU time 0.94 seconds
Started Jul 24 05:19:37 PM PDT 24
Finished Jul 24 05:19:38 PM PDT 24
Peak memory 191828 kb
Host smart-35c62f9a-a2de-4639-8981-579524b16ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730535175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3730535175
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1144704728
Short name T266
Test name
Test status
Simulation time 39663267309 ps
CPU time 3.73 seconds
Started Jul 24 05:19:38 PM PDT 24
Finished Jul 24 05:19:42 PM PDT 24
Peak memory 196876 kb
Host smart-3594f8ac-2106-42bc-9e9d-4bbc21846d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144704728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1144704728
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3639713227
Short name T277
Test name
Test status
Simulation time 557869710 ps
CPU time 0.74 seconds
Started Jul 24 05:19:36 PM PDT 24
Finished Jul 24 05:19:37 PM PDT 24
Peak memory 191744 kb
Host smart-8252021a-fbdd-4f75-aa59-8cd6ce988792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639713227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3639713227
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1203021723
Short name T201
Test name
Test status
Simulation time 40849062748 ps
CPU time 32.39 seconds
Started Jul 24 05:19:39 PM PDT 24
Finished Jul 24 05:20:12 PM PDT 24
Peak memory 191848 kb
Host smart-d6558356-7bcd-444f-9a0e-8de23a15697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203021723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1203021723
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3505646234
Short name T255
Test name
Test status
Simulation time 548371111 ps
CPU time 0.91 seconds
Started Jul 24 05:19:33 PM PDT 24
Finished Jul 24 05:19:34 PM PDT 24
Peak memory 191724 kb
Host smart-602e2254-5ad7-4fff-8e0d-bef43cfb3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505646234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3505646234
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3734269050
Short name T200
Test name
Test status
Simulation time 20872708921 ps
CPU time 2.91 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:19:43 PM PDT 24
Peak memory 190860 kb
Host smart-ac306705-585c-4eac-b28c-b74b7b8058a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734269050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3734269050
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.408213722
Short name T253
Test name
Test status
Simulation time 568218824 ps
CPU time 0.75 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:19:41 PM PDT 24
Peak memory 196564 kb
Host smart-0d7be063-2900-4b34-b70f-f5e5ca309dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408213722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.408213722
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.78237788
Short name T210
Test name
Test status
Simulation time 32653164666 ps
CPU time 50.72 seconds
Started Jul 24 05:19:45 PM PDT 24
Finished Jul 24 05:20:36 PM PDT 24
Peak memory 196880 kb
Host smart-9f4089d8-3ba3-459b-830c-09ffdb88eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78237788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.78237788
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2390009299
Short name T223
Test name
Test status
Simulation time 370554556 ps
CPU time 1.11 seconds
Started Jul 24 05:19:52 PM PDT 24
Finished Jul 24 05:19:54 PM PDT 24
Peak memory 191788 kb
Host smart-593c2c6a-5879-407e-948d-e089e247ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390009299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2390009299
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2449417810
Short name T273
Test name
Test status
Simulation time 3963263997 ps
CPU time 6.84 seconds
Started Jul 24 05:19:44 PM PDT 24
Finished Jul 24 05:19:52 PM PDT 24
Peak memory 196608 kb
Host smart-09101038-c7a6-4460-a6a8-99c8ef001c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449417810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2449417810
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2241512788
Short name T221
Test name
Test status
Simulation time 500297570 ps
CPU time 0.63 seconds
Started Jul 24 05:19:58 PM PDT 24
Finished Jul 24 05:19:59 PM PDT 24
Peak memory 191728 kb
Host smart-deff66ef-ba66-4d6b-bbad-26b193276552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241512788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2241512788
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.336732453
Short name T208
Test name
Test status
Simulation time 28345573703 ps
CPU time 41.23 seconds
Started Jul 24 05:19:23 PM PDT 24
Finished Jul 24 05:20:05 PM PDT 24
Peak memory 191864 kb
Host smart-59f7ee56-489b-4bbe-bde1-0479f208e113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336732453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.336732453
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.562765491
Short name T11
Test name
Test status
Simulation time 4246366003 ps
CPU time 6.28 seconds
Started Jul 24 05:19:22 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 215572 kb
Host smart-ba422607-499b-455e-ba99-18cab5758864
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562765491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.562765491
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1215202040
Short name T280
Test name
Test status
Simulation time 623298977 ps
CPU time 0.74 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:27 PM PDT 24
Peak memory 191724 kb
Host smart-af7bfce0-bdf4-4135-88d2-65ebdeaa81f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215202040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1215202040
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4204661254
Short name T31
Test name
Test status
Simulation time 575551746 ps
CPU time 1 seconds
Started Jul 24 05:20:02 PM PDT 24
Finished Jul 24 05:20:03 PM PDT 24
Peak memory 196612 kb
Host smart-678704b0-066c-4800-ae47-d9969e0f68de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204661254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4204661254
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.17898443
Short name T73
Test name
Test status
Simulation time 30793012610 ps
CPU time 38.95 seconds
Started Jul 24 05:19:48 PM PDT 24
Finished Jul 24 05:20:27 PM PDT 24
Peak memory 191844 kb
Host smart-19280b52-cc56-47e2-bf0d-49b086c42a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17898443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.17898443
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3845537280
Short name T276
Test name
Test status
Simulation time 531597136 ps
CPU time 0.99 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:19:42 PM PDT 24
Peak memory 196564 kb
Host smart-2dac2d79-1298-4695-98ff-6cd70cf4262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845537280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3845537280
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3684560882
Short name T282
Test name
Test status
Simulation time 37686675328 ps
CPU time 12.82 seconds
Started Jul 24 05:19:39 PM PDT 24
Finished Jul 24 05:19:52 PM PDT 24
Peak memory 196844 kb
Host smart-4bd13620-c7be-4d58-97a4-2b35abd4a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684560882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3684560882
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.373016943
Short name T206
Test name
Test status
Simulation time 484635706 ps
CPU time 0.89 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:19:41 PM PDT 24
Peak memory 191676 kb
Host smart-09a0f660-53fa-4df7-a98a-f9a0effb55c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373016943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.373016943
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2517567511
Short name T234
Test name
Test status
Simulation time 45198846670 ps
CPU time 6.08 seconds
Started Jul 24 05:19:52 PM PDT 24
Finished Jul 24 05:19:59 PM PDT 24
Peak memory 191888 kb
Host smart-012d1655-0eed-46f8-9735-0939f5bb3755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517567511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2517567511
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2813660851
Short name T215
Test name
Test status
Simulation time 496943123 ps
CPU time 0.71 seconds
Started Jul 24 05:19:54 PM PDT 24
Finished Jul 24 05:19:54 PM PDT 24
Peak memory 191712 kb
Host smart-2f210367-7a71-4895-8b62-08838cbf39ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813660851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2813660851
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2467074825
Short name T193
Test name
Test status
Simulation time 11419788415 ps
CPU time 7.48 seconds
Started Jul 24 05:19:42 PM PDT 24
Finished Jul 24 05:19:50 PM PDT 24
Peak memory 196872 kb
Host smart-41bce7a7-b767-4462-8a4d-04e94bbf3bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467074825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2467074825
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.870017871
Short name T233
Test name
Test status
Simulation time 636209634 ps
CPU time 0.79 seconds
Started Jul 24 05:19:57 PM PDT 24
Finished Jul 24 05:19:58 PM PDT 24
Peak memory 196560 kb
Host smart-b03b46e6-eade-4a1c-bca0-f004db27af0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870017871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.870017871
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3988203368
Short name T227
Test name
Test status
Simulation time 49192828354 ps
CPU time 37.76 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:20:18 PM PDT 24
Peak memory 191864 kb
Host smart-2df9ea65-8387-4fdc-8d03-82c61de30e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988203368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3988203368
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1706009259
Short name T219
Test name
Test status
Simulation time 462934801 ps
CPU time 1.17 seconds
Started Jul 24 05:19:47 PM PDT 24
Finished Jul 24 05:19:48 PM PDT 24
Peak memory 196584 kb
Host smart-38fa5e2b-c15d-4a4e-9136-3ec1fe15f9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706009259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1706009259
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3275616837
Short name T254
Test name
Test status
Simulation time 45415232282 ps
CPU time 18.97 seconds
Started Jul 24 05:19:42 PM PDT 24
Finished Jul 24 05:20:01 PM PDT 24
Peak memory 191892 kb
Host smart-f1da4a39-7296-4dea-a56f-7ae7955a21cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275616837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3275616837
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3791777262
Short name T197
Test name
Test status
Simulation time 534968456 ps
CPU time 0.96 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:19:42 PM PDT 24
Peak memory 191764 kb
Host smart-a7f39115-a534-4fe6-bfb0-e8cffbd9240f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791777262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3791777262
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1584430395
Short name T47
Test name
Test status
Simulation time 10064530000 ps
CPU time 12.6 seconds
Started Jul 24 05:19:49 PM PDT 24
Finished Jul 24 05:20:01 PM PDT 24
Peak memory 191844 kb
Host smart-c2db77b2-bdce-41b1-bddc-637221a5ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584430395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1584430395
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3899881246
Short name T259
Test name
Test status
Simulation time 649818500 ps
CPU time 0.6 seconds
Started Jul 24 05:19:58 PM PDT 24
Finished Jul 24 05:19:59 PM PDT 24
Peak memory 191608 kb
Host smart-957c74c5-0505-4cb2-8e4f-a2802c39a6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899881246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3899881246
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3605166692
Short name T225
Test name
Test status
Simulation time 51244222712 ps
CPU time 79.36 seconds
Started Jul 24 05:20:01 PM PDT 24
Finished Jul 24 05:21:20 PM PDT 24
Peak memory 191840 kb
Host smart-91956def-9f5d-46bf-b3f4-7bbd15764ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605166692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3605166692
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2313590703
Short name T263
Test name
Test status
Simulation time 414663873 ps
CPU time 1.21 seconds
Started Jul 24 05:19:38 PM PDT 24
Finished Jul 24 05:19:40 PM PDT 24
Peak memory 196544 kb
Host smart-99066a77-93b7-4899-8e36-07c6ae4ccaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313590703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2313590703
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2040887682
Short name T20
Test name
Test status
Simulation time 52511699471 ps
CPU time 20.57 seconds
Started Jul 24 05:19:46 PM PDT 24
Finished Jul 24 05:20:07 PM PDT 24
Peak memory 191848 kb
Host smart-0b2710b1-648d-43f0-844b-9fb1c3a496f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040887682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2040887682
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3584913207
Short name T205
Test name
Test status
Simulation time 593934532 ps
CPU time 0.77 seconds
Started Jul 24 05:19:47 PM PDT 24
Finished Jul 24 05:19:48 PM PDT 24
Peak memory 191780 kb
Host smart-ad6b0f92-df31-419e-b8f5-e8ba844fc60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584913207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3584913207
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3664862657
Short name T236
Test name
Test status
Simulation time 38145372555 ps
CPU time 9.12 seconds
Started Jul 24 05:19:40 PM PDT 24
Finished Jul 24 05:19:49 PM PDT 24
Peak memory 190848 kb
Host smart-729219f1-3e69-45d8-9908-9e41d1730bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664862657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3664862657
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.430182065
Short name T251
Test name
Test status
Simulation time 430028706 ps
CPU time 0.67 seconds
Started Jul 24 05:19:53 PM PDT 24
Finished Jul 24 05:19:54 PM PDT 24
Peak memory 191744 kb
Host smart-f6bf4cbb-765b-4e95-92dd-b8be53b7a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430182065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.430182065
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1065660026
Short name T141
Test name
Test status
Simulation time 414249115 ps
CPU time 1.19 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:28 PM PDT 24
Peak memory 196592 kb
Host smart-ea9ccfd2-42f6-4d3b-917d-85f801ca6cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065660026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1065660026
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1173498763
Short name T204
Test name
Test status
Simulation time 9730078421 ps
CPU time 4.31 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:31 PM PDT 24
Peak memory 191912 kb
Host smart-643699e7-2b44-4a40-a611-ea94123e9c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173498763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1173498763
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2368457085
Short name T16
Test name
Test status
Simulation time 4343428608 ps
CPU time 4.07 seconds
Started Jul 24 05:19:24 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 215740 kb
Host smart-bf49a048-d5d0-424f-9dcb-ce60b10a5178
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368457085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2368457085
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2626240003
Short name T228
Test name
Test status
Simulation time 507215810 ps
CPU time 1.23 seconds
Started Jul 24 05:19:24 PM PDT 24
Finished Jul 24 05:19:26 PM PDT 24
Peak memory 196580 kb
Host smart-136a9626-ec93-4db2-a8a7-862aa6d653ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626240003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2626240003
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.711358900
Short name T230
Test name
Test status
Simulation time 33986018999 ps
CPU time 49.79 seconds
Started Jul 24 05:19:55 PM PDT 24
Finished Jul 24 05:20:45 PM PDT 24
Peak memory 196884 kb
Host smart-81937f93-8e4e-4f43-a1bf-766eff06a433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711358900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.711358900
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1591639942
Short name T246
Test name
Test status
Simulation time 330850914 ps
CPU time 1.08 seconds
Started Jul 24 05:20:03 PM PDT 24
Finished Jul 24 05:20:04 PM PDT 24
Peak memory 196572 kb
Host smart-b2382162-6642-4278-b1d5-4038f162f6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591639942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1591639942
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2207692318
Short name T265
Test name
Test status
Simulation time 26142874769 ps
CPU time 19.8 seconds
Started Jul 24 05:19:48 PM PDT 24
Finished Jul 24 05:20:08 PM PDT 24
Peak memory 191892 kb
Host smart-b1954085-a4b5-42e7-880d-1638d4fc596b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207692318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2207692318
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2046453330
Short name T211
Test name
Test status
Simulation time 580441471 ps
CPU time 0.85 seconds
Started Jul 24 05:20:09 PM PDT 24
Finished Jul 24 05:20:10 PM PDT 24
Peak memory 191732 kb
Host smart-95198d41-3de4-49cd-8404-36e343ca9c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046453330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2046453330
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2400952172
Short name T224
Test name
Test status
Simulation time 52349846324 ps
CPU time 35.77 seconds
Started Jul 24 05:19:50 PM PDT 24
Finished Jul 24 05:20:25 PM PDT 24
Peak memory 191892 kb
Host smart-3b6fc4f8-002f-45bb-8420-2568913f2414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400952172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2400952172
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2265992715
Short name T48
Test name
Test status
Simulation time 402120208 ps
CPU time 0.7 seconds
Started Jul 24 05:19:48 PM PDT 24
Finished Jul 24 05:19:49 PM PDT 24
Peak memory 196568 kb
Host smart-313a42a7-4346-4ba8-8b8a-afa2917f7048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265992715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2265992715
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.818092521
Short name T281
Test name
Test status
Simulation time 38026250286 ps
CPU time 57.27 seconds
Started Jul 24 05:19:54 PM PDT 24
Finished Jul 24 05:20:52 PM PDT 24
Peak memory 196808 kb
Host smart-5bbae58e-7670-4308-9d81-3e6b5e5a1c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818092521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.818092521
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2044167338
Short name T250
Test name
Test status
Simulation time 615433335 ps
CPU time 1.47 seconds
Started Jul 24 05:19:59 PM PDT 24
Finished Jul 24 05:20:01 PM PDT 24
Peak memory 191732 kb
Host smart-885d93ae-0609-4c28-a863-a71b9746567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044167338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2044167338
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.4116994457
Short name T198
Test name
Test status
Simulation time 31418732116 ps
CPU time 39.27 seconds
Started Jul 24 05:20:10 PM PDT 24
Finished Jul 24 05:20:49 PM PDT 24
Peak memory 196864 kb
Host smart-20f92af9-e23c-4ec4-b5e8-dfb805e50cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116994457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.4116994457
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2628116206
Short name T249
Test name
Test status
Simulation time 396579158 ps
CPU time 1.1 seconds
Started Jul 24 05:19:45 PM PDT 24
Finished Jul 24 05:19:46 PM PDT 24
Peak memory 191824 kb
Host smart-14213a88-0b42-4fc8-8a4d-491f453e5114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628116206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2628116206
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.868830476
Short name T252
Test name
Test status
Simulation time 20095737560 ps
CPU time 31.14 seconds
Started Jul 24 05:19:45 PM PDT 24
Finished Jul 24 05:20:16 PM PDT 24
Peak memory 196344 kb
Host smart-4d012e4b-accf-4303-8285-5fcecdfb75a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868830476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.868830476
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.892113439
Short name T212
Test name
Test status
Simulation time 510399588 ps
CPU time 1.23 seconds
Started Jul 24 05:19:56 PM PDT 24
Finished Jul 24 05:19:57 PM PDT 24
Peak memory 196632 kb
Host smart-7a968f16-086f-4682-8e82-8b15fff47721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892113439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.892113439
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2080322414
Short name T196
Test name
Test status
Simulation time 19870117729 ps
CPU time 13.56 seconds
Started Jul 24 05:19:58 PM PDT 24
Finished Jul 24 05:20:12 PM PDT 24
Peak memory 192040 kb
Host smart-2d972461-9a96-44bc-825a-0c03eaddeb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080322414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2080322414
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1213448294
Short name T238
Test name
Test status
Simulation time 417676133 ps
CPU time 0.73 seconds
Started Jul 24 05:20:03 PM PDT 24
Finished Jul 24 05:20:04 PM PDT 24
Peak memory 191740 kb
Host smart-e29a223f-402b-477d-8efc-974de13974f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213448294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1213448294
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1669321924
Short name T272
Test name
Test status
Simulation time 50187945783 ps
CPU time 74.1 seconds
Started Jul 24 05:19:44 PM PDT 24
Finished Jul 24 05:20:59 PM PDT 24
Peak memory 196884 kb
Host smart-c362f695-dbb2-4aee-b171-a17590a0c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669321924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1669321924
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.86235860
Short name T202
Test name
Test status
Simulation time 522280033 ps
CPU time 0.97 seconds
Started Jul 24 05:19:41 PM PDT 24
Finished Jul 24 05:19:42 PM PDT 24
Peak memory 191708 kb
Host smart-d45c409f-cb89-4ea4-9563-2c6c329306ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86235860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.86235860
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_jump.4228750064
Short name T6
Test name
Test status
Simulation time 545931406 ps
CPU time 0.64 seconds
Started Jul 24 05:19:43 PM PDT 24
Finished Jul 24 05:19:44 PM PDT 24
Peak memory 196532 kb
Host smart-ed00c4e0-6704-43b2-8d86-ceaa2d737bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228750064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.4228750064
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3584667719
Short name T269
Test name
Test status
Simulation time 7685708713 ps
CPU time 5.92 seconds
Started Jul 24 05:19:50 PM PDT 24
Finished Jul 24 05:19:57 PM PDT 24
Peak memory 196780 kb
Host smart-0e20cad7-ae34-4c7c-bdd3-7b79eca197a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584667719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3584667719
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2010772652
Short name T237
Test name
Test status
Simulation time 370394578 ps
CPU time 1.01 seconds
Started Jul 24 05:20:05 PM PDT 24
Finished Jul 24 05:20:06 PM PDT 24
Peak memory 191724 kb
Host smart-a3aed574-354c-4ff3-8a2d-233647d2ad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010772652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2010772652
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4145107989
Short name T232
Test name
Test status
Simulation time 22794515757 ps
CPU time 30.25 seconds
Started Jul 24 05:19:51 PM PDT 24
Finished Jul 24 05:20:21 PM PDT 24
Peak memory 196884 kb
Host smart-62b86921-c3ef-4d6b-b3ac-f94b5b060a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145107989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4145107989
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2676067915
Short name T274
Test name
Test status
Simulation time 396818987 ps
CPU time 1.13 seconds
Started Jul 24 05:19:52 PM PDT 24
Finished Jul 24 05:19:53 PM PDT 24
Peak memory 191676 kb
Host smart-beae4816-2670-40e4-9fdd-14fac395b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676067915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2676067915
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_jump.4122612704
Short name T167
Test name
Test status
Simulation time 601725021 ps
CPU time 1 seconds
Started Jul 24 05:19:29 PM PDT 24
Finished Jul 24 05:19:31 PM PDT 24
Peak memory 196564 kb
Host smart-e4b37ad4-ebba-44bc-8a18-63a0c1c4a7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122612704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.4122612704
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1232283421
Short name T247
Test name
Test status
Simulation time 9447445951 ps
CPU time 7.16 seconds
Started Jul 24 05:19:23 PM PDT 24
Finished Jul 24 05:19:31 PM PDT 24
Peak memory 196860 kb
Host smart-81789f75-6474-4210-bc4b-be17cd8a2cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232283421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1232283421
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.107629563
Short name T270
Test name
Test status
Simulation time 534446789 ps
CPU time 0.72 seconds
Started Jul 24 05:19:24 PM PDT 24
Finished Jul 24 05:19:24 PM PDT 24
Peak memory 191764 kb
Host smart-9b5ee3bd-cd38-4744-ad1b-36bdf68ed014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107629563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.107629563
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1936598997
Short name T43
Test name
Test status
Simulation time 14226489666 ps
CPU time 5.93 seconds
Started Jul 24 05:19:30 PM PDT 24
Finished Jul 24 05:19:36 PM PDT 24
Peak memory 191880 kb
Host smart-7e073cdd-d5ec-4ded-931a-6264f297d0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936598997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1936598997
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2646382453
Short name T261
Test name
Test status
Simulation time 473596817 ps
CPU time 0.73 seconds
Started Jul 24 05:19:26 PM PDT 24
Finished Jul 24 05:19:27 PM PDT 24
Peak memory 191664 kb
Host smart-aa4fac25-dfac-40a0-a01a-23727895dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646382453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2646382453
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3982996216
Short name T257
Test name
Test status
Simulation time 35311040284 ps
CPU time 24.69 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:19:53 PM PDT 24
Peak memory 196860 kb
Host smart-5335002d-0a60-48fa-9a9f-2eaabd21ba83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982996216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3982996216
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1262997703
Short name T240
Test name
Test status
Simulation time 553240952 ps
CPU time 1.13 seconds
Started Jul 24 05:19:25 PM PDT 24
Finished Jul 24 05:19:27 PM PDT 24
Peak memory 196608 kb
Host smart-edb7410f-3fac-4ef7-a1e3-daf2b04a61a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262997703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1262997703
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.407997377
Short name T1
Test name
Test status
Simulation time 58659514384 ps
CPU time 22.23 seconds
Started Jul 24 05:19:25 PM PDT 24
Finished Jul 24 05:19:47 PM PDT 24
Peak memory 191764 kb
Host smart-e5ef7846-805b-44ee-b63d-4aac231fed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407997377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.407997377
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.168415515
Short name T218
Test name
Test status
Simulation time 485870285 ps
CPU time 0.73 seconds
Started Jul 24 05:19:36 PM PDT 24
Finished Jul 24 05:19:37 PM PDT 24
Peak memory 191732 kb
Host smart-f51d44fa-f813-4cbf-a891-7aa359bf9647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168415515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.168415515
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2219115080
Short name T231
Test name
Test status
Simulation time 27581072656 ps
CPU time 38.17 seconds
Started Jul 24 05:19:25 PM PDT 24
Finished Jul 24 05:20:03 PM PDT 24
Peak memory 196848 kb
Host smart-7c6dd5a3-cb6d-4540-8915-9eca393e2910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219115080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2219115080
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1144019036
Short name T199
Test name
Test status
Simulation time 551525480 ps
CPU time 0.78 seconds
Started Jul 24 05:19:28 PM PDT 24
Finished Jul 24 05:19:29 PM PDT 24
Peak memory 191680 kb
Host smart-bf0ff131-2e11-457c-8128-10e241d14d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144019036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1144019036
Directory /workspace/9.aon_timer_smoke/latest
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