Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	4	169	97.69

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	0	2	100.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	1	65	98.48	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	30171	1		T2	161		T3	10		T4	12
bark[1]	790	1		T8	32		T13	63		T126	57
bark[2]	394	1		T109	14		T50	26		T150	51
bark[3]	405	1		T126	14		T47	21		T28	21
bark[4]	1135	1		T25	318		T123	14		T58	205
bark[5]	757	1		T2	21		T33	21		T16	21
bark[6]	751	1		T6	14		T13	56		T33	52
bark[7]	268	1		T26	21		T192	14		T138	21
bark[8]	492	1		T109	26		T28	146		T147	21
bark[9]	334	1		T32	32		T121	14		T83	73
bark[10]	400	1		T11	21		T31	14		T126	21
bark[11]	691	1		T16	179		T49	26		T39	30
bark[12]	900	1		T126	21		T50	233		T170	279
bark[13]	286	1		T39	21		T134	42		T131	14
bark[14]	463	1		T8	21		T98	21		T181	14
bark[15]	1001	1		T8	21		T126	26		T28	151
bark[16]	647	1		T126	51		T102	14		T16	249
bark[17]	914	1		T33	21		T34	21		T109	21
bark[18]	785	1		T8	21		T13	21		T48	145
bark[19]	264	1		T34	30		T119	21		T138	50
bark[20]	492	1		T11	213		T32	61		T34	31
bark[21]	621	1		T25	225		T28	39		T150	42
bark[22]	693	1		T34	21		T159	14		T171	257
bark[23]	769	1		T2	45		T98	21		T49	47
bark[24]	174	1		T26	26		T81	21		T152	14
bark[25]	1036	1		T1	14		T101	14		T25	179
bark[26]	463	1		T49	60		T88	21		T90	66
bark[27]	653	1		T2	26		T32	21		T15	21
bark[28]	435	1		T10	14		T82	224		T185	47
bark[29]	546	1		T47	21		T28	26		T171	57
bark[30]	646	1		T34	14		T102	21		T47	30
bark[31]	810	1		T2	30		T102	21		T173	47
bark_0	4604	1		T1	7		T2	12		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	30121	1		T2	160		T3	9		T4	11
bite[1]	451	1		T188	13		T83	72		T94	281
bite[2]	836	1		T8	21		T10	13		T13	21
bite[3]	472	1		T33	21		T102	21		T96	13
bite[4]	739	1		T31	13		T34	21		T126	77
bite[5]	458	1		T35	74		T186	13		T59	260
bite[6]	402	1		T126	13		T134	13		T82	223
bite[7]	687	1		T126	21		T109	13		T174	30
bite[8]	877	1		T1	13		T95	13		T28	145
bite[9]	743	1		T2	45		T34	30		T98	21
bite[10]	467	1		T13	42		T34	21		T126	57
bite[11]	202	1		T8	21		T33	21		T25	21
bite[12]	771	1		T32	61		T102	21		T25	21
bite[13]	927	1		T15	21		T47	21		T24	13
bite[14]	194	1		T47	21		T28	21		T152	13
bite[15]	589	1		T13	21		T15	21		T25	13
bite[16]	927	1		T2	51		T102	57		T16	248
bite[17]	511	1		T102	13		T25	21		T26	26
bite[18]	811	1		T32	21		T16	157		T28	145
bite[19]	314	1		T98	21		T49	59		T115	30
bite[20]	801	1		T6	13		T11	212		T34	31
bite[21]	115	1		T40	13		T53	13		T134	21
bite[22]	402	1		T109	26		T83	21		T162	42
bite[23]	583	1		T34	21		T16	21		T25	178
bite[24]	542	1		T153	13		T150	42		T58	21
bite[25]	654	1		T98	21		T101	13		T25	224
bite[26]	859	1		T8	31		T11	21		T28	39
bite[27]	383	1		T48	76		T50	30		T173	43
bite[28]	850	1		T32	31		T33	30		T159	13
bite[29]	786	1		T109	21		T26	21		T48	70
bite[30]	368	1		T34	13		T49	26		T119	21
bite[31]	868	1		T2	26		T11	126		T13	56
bite_0	5080	1		T1	8		T2	13		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for pause_in_sleep_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	46614	1		T1	21		T2	275		T3	17
auto[1]	7176	1		T2	20		T11	183		T33	43

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1123	1		T11	19		T126	36		T47	24
prescale[1]	1097	1		T2	19		T8	50		T13	74
prescale[2]	1284	1		T109	53		T16	76		T98	19
prescale[3]	833	1		T2	19		T5	19		T13	9
prescale[4]	674	1		T2	23		T109	19		T15	2
prescale[5]	1108	1		T11	134		T25	76		T50	125
prescale[6]	891	1		T8	19		T109	44		T25	42
prescale[7]	645	1		T15	127		T25	64		T28	2
prescale[8]	714	1		T47	23		T25	19		T28	61
prescale[9]	745	1		T11	2		T26	254		T203	9
prescale[10]	720	1		T5	19		T11	2		T15	73
prescale[11]	502	1		T33	45		T34	53		T39	24
prescale[12]	1124	1		T11	57		T15	9		T47	121
prescale[13]	932	1		T8	24		T109	19		T98	33
prescale[14]	1112	1		T126	40		T109	19		T28	40
prescale[15]	868	1		T2	40		T5	28		T34	54
prescale[16]	1083	1		T5	19		T34	30		T109	23
prescale[17]	353	1		T11	9		T16	2		T28	29
prescale[18]	457	1		T47	117		T25	19		T50	19
prescale[19]	836	1		T126	44		T26	127		T173	19
prescale[20]	665	1		T11	18		T12	9		T33	64
prescale[21]	828	1		T32	23		T33	24		T47	2
prescale[22]	891	1		T13	100		T16	95		T28	2
prescale[23]	413	1		T47	2		T48	2		T49	2
prescale[24]	1099	1		T2	23		T5	24		T13	19
prescale[25]	713	1		T4	9		T126	89		T102	40
prescale[26]	767	1		T45	9		T15	19		T98	19
prescale[27]	538	1		T126	23		T16	2		T47	36
prescale[28]	1098	1		T11	2		T51	9		T34	19
prescale[29]	704	1		T9	9		T47	28		T28	50
prescale[30]	946	1		T5	9		T13	45		T16	2
prescale[31]	1652	1		T11	154		T25	61		T28	83
prescale_0	26375	1		T1	21		T2	171		T3	17

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	40617	1		T1	9		T2	221		T3	17
auto[1]	13173	1		T1	12		T2	74		T4	10

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	53790	1		T1	21		T2	295		T3	17

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	1	65	98.48

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	30658	1		T1	1		T2	161		T3	12
wkup[1]	209	1		T13	21		T47	21		T24	15
wkup[2]	404	1		T126	21		T15	21		T16	21
wkup[3]	182	1		T109	26		T81	42		T171	15
wkup[4]	410	1		T102	21		T25	21		T50	21
wkup[5]	300	1		T5	21		T25	15		T48	21
wkup[6]	339	1		T11	21		T28	42		T81	21
wkup[7]	360	1		T47	21		T25	30		T81	21
wkup[8]	355	1		T33	21		T26	21		T28	21
wkup[9]	187	1		T25	21		T193	15		T58	15
wkup[10]	449	1		T25	42		T49	21		T50	42
wkup[11]	291	1		T126	26		T15	21		T28	21
wkup[12]	290	1		T98	21		T26	21		T48	8
wkup[13]	416	1		T8	54		T11	39		T39	21
wkup[14]	312	1		T34	30		T15	21		T16	21
wkup[15]	310	1		T126	15		T15	21		T16	21
wkup[16]	311	1		T33	21		T15	21		T28	30
wkup[17]	335	1		T15	21		T25	51		T134	42
wkup[18]	184	1		T13	30		T47	8		T124	21
wkup[19]	422	1		T2	26		T109	21		T15	21
wkup[20]	135	1		T28	21		T91	6		T175	21
wkup[21]	363	1		T8	21		T11	30		T31	15
wkup[22]	278	1		T11	21		T13	21		T25	8
wkup[23]	277	1		T109	21		T102	21		T25	26
wkup[24]	271	1		T26	26		T50	21		T173	21
wkup[25]	394	1		T13	21		T32	33		T102	15
wkup[26]	444	1		T48	30		T50	21		T147	21
wkup[27]	328	1		T11	21		T95	15		T25	21
wkup[28]	194	1		T25	21		T28	39		T147	21
wkup[29]	239	1		T11	21		T15	21		T81	42
wkup[30]	310	1		T32	35		T33	21		T16	26
wkup[31]	205	1		T10	15		T35	21		T58	26
wkup[32]	456	1		T32	26		T33	21		T47	63
wkup[33]	323	1		T25	21		T81	26		T90	21
wkup[34]	181	1		T48	26		T150	21		T83	21
wkup[35]	298	1		T98	21		T25	21		T26	26
wkup[36]	275	1		T109	15		T28	21		T39	15
wkup[37]	365	1		T2	26		T11	21		T16	21
wkup[38]	233	1		T11	21		T28	21		T48	21
wkup[39]	332	1		T2	21		T102	21		T98	21
wkup[40]	247	1		T15	21		T102	21		T26	30
wkup[41]	306	1		T98	21		T150	21		T58	21
wkup[42]	282	1		T8	21		T15	42		T28	21
wkup[43]	458	1		T1	15		T13	21		T34	31
wkup[44]	379	1		T2	30		T6	15		T15	21
wkup[45]	362	1		T25	21		T49	21		T50	35
wkup[46]	269	1		T25	21		T28	42		T50	21
wkup[47]	464	1		T33	21		T34	15		T25	47
wkup[48]	406	1		T11	21		T32	21		T126	63
wkup[49]	154	1		T34	21		T25	21		T28	21
wkup[50]	276	1		T126	21		T121	15		T171	21
wkup[51]	351	1		T32	31		T26	31		T39	30
wkup[52]	428	1		T11	21		T15	21		T96	15
wkup[53]	300	1		T176	15		T88	21		T127	21
wkup[54]	152	1		T26	21		T50	26		T81	21
wkup[55]	213	1		T34	21		T28	21		T50	15
wkup[56]	356	1		T13	35		T15	21		T28	79
wkup[57]	407	1		T2	21		T13	21		T15	44
wkup[58]	314	1		T47	44		T28	21		T58	42
wkup[59]	350	1		T25	21		T26	21		T28	21
wkup[60]	239	1		T32	26		T147	26		T58	42
wkup[61]	447	1		T50	21		T173	21		T81	30
wkup[62]	168	1		T47	21		T25	21		T26	21
wkup[63]	249	1		T13	21		T147	26		T58	21
wkup_0	3588	1		T1	5		T2	10		T3	5