Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.54 99.33 93.67 100.00 98.40 99.51 52.33


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T284 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1297276592 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 315652557 ps
T42 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2679409887 Jul 25 06:02:56 PM PDT 24 Jul 25 06:03:09 PM PDT 24 8050276312 ps
T285 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.389617426 Jul 25 06:03:09 PM PDT 24 Jul 25 06:03:11 PM PDT 24 334042312 ps
T286 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3319656860 Jul 25 06:03:00 PM PDT 24 Jul 25 06:03:01 PM PDT 24 278908396 ps
T74 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1413543986 Jul 25 06:03:11 PM PDT 24 Jul 25 06:03:17 PM PDT 24 3329384518 ps
T75 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1442363286 Jul 25 06:02:57 PM PDT 24 Jul 25 06:02:59 PM PDT 24 2913689873 ps
T60 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3494773546 Jul 25 06:03:09 PM PDT 24 Jul 25 06:03:10 PM PDT 24 524063597 ps
T76 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1542642264 Jul 25 06:03:33 PM PDT 24 Jul 25 06:03:34 PM PDT 24 417073096 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2727209462 Jul 25 06:02:57 PM PDT 24 Jul 25 06:03:02 PM PDT 24 10660940029 ps
T204 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2493916141 Jul 25 06:03:25 PM PDT 24 Jul 25 06:03:26 PM PDT 24 330827689 ps
T287 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2793196412 Jul 25 06:03:27 PM PDT 24 Jul 25 06:03:28 PM PDT 24 571324806 ps
T288 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1805674258 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 383120737 ps
T206 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3736015615 Jul 25 06:03:19 PM PDT 24 Jul 25 06:03:36 PM PDT 24 7061743358 ps
T289 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.916126609 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 415630050 ps
T62 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.600042696 Jul 25 06:03:08 PM PDT 24 Jul 25 06:03:09 PM PDT 24 455653120 ps
T290 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2030749510 Jul 25 06:03:16 PM PDT 24 Jul 25 06:03:18 PM PDT 24 517958788 ps
T291 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2800706382 Jul 25 06:02:59 PM PDT 24 Jul 25 06:03:00 PM PDT 24 494610245 ps
T77 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3176772341 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:16 PM PDT 24 1586925803 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2889281039 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:15 PM PDT 24 773496572 ps
T292 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.912569876 Jul 25 06:02:58 PM PDT 24 Jul 25 06:02:59 PM PDT 24 300528186 ps
T205 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2483775019 Jul 25 06:03:16 PM PDT 24 Jul 25 06:03:17 PM PDT 24 427084472 ps
T78 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2926868882 Jul 25 06:03:13 PM PDT 24 Jul 25 06:03:15 PM PDT 24 3000181662 ps
T293 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.423587195 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 300292743 ps
T79 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1892013714 Jul 25 06:03:08 PM PDT 24 Jul 25 06:03:11 PM PDT 24 1459665254 ps
T43 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3311631633 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:28 PM PDT 24 8162846940 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1747443485 Jul 25 06:03:25 PM PDT 24 Jul 25 06:03:26 PM PDT 24 377375876 ps
T295 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.161094853 Jul 25 06:03:27 PM PDT 24 Jul 25 06:03:29 PM PDT 24 551746594 ps
T44 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1149974411 Jul 25 06:03:12 PM PDT 24 Jul 25 06:03:17 PM PDT 24 4695533948 ps
T296 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.600980769 Jul 25 06:03:35 PM PDT 24 Jul 25 06:03:36 PM PDT 24 483996937 ps
T297 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.101625337 Jul 25 06:03:25 PM PDT 24 Jul 25 06:03:26 PM PDT 24 383795972 ps
T197 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3194549159 Jul 25 06:02:59 PM PDT 24 Jul 25 06:03:13 PM PDT 24 8631556908 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.372017686 Jul 25 06:02:57 PM PDT 24 Jul 25 06:03:00 PM PDT 24 615404473 ps
T299 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3074675389 Jul 25 06:03:24 PM PDT 24 Jul 25 06:03:25 PM PDT 24 370215928 ps
T201 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.296380264 Jul 25 06:03:29 PM PDT 24 Jul 25 06:03:30 PM PDT 24 4635685115 ps
T300 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1865089703 Jul 25 06:03:07 PM PDT 24 Jul 25 06:03:08 PM PDT 24 495805595 ps
T301 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.937703105 Jul 25 06:03:10 PM PDT 24 Jul 25 06:03:12 PM PDT 24 550340012 ps
T302 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1197181905 Jul 25 06:03:32 PM PDT 24 Jul 25 06:03:34 PM PDT 24 424604915 ps
T80 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4222652331 Jul 25 06:03:26 PM PDT 24 Jul 25 06:03:28 PM PDT 24 1104084787 ps
T303 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2486839667 Jul 25 06:03:13 PM PDT 24 Jul 25 06:03:14 PM PDT 24 477193470 ps
T304 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3961641088 Jul 25 06:03:15 PM PDT 24 Jul 25 06:03:16 PM PDT 24 302787073 ps
T305 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.544496469 Jul 25 06:03:21 PM PDT 24 Jul 25 06:03:22 PM PDT 24 397880781 ps
T306 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.948784724 Jul 25 06:03:31 PM PDT 24 Jul 25 06:03:31 PM PDT 24 508417059 ps
T307 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2942061080 Jul 25 06:02:59 PM PDT 24 Jul 25 06:03:00 PM PDT 24 613790013 ps
T308 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3996149502 Jul 25 06:02:57 PM PDT 24 Jul 25 06:03:03 PM PDT 24 14086075174 ps
T309 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.570462135 Jul 25 06:03:13 PM PDT 24 Jul 25 06:03:14 PM PDT 24 491140824 ps
T64 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1640532419 Jul 25 06:02:57 PM PDT 24 Jul 25 06:02:58 PM PDT 24 345481141 ps
T310 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3458423675 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 336210731 ps
T311 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2516674690 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 328520544 ps
T312 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2167979739 Jul 25 06:03:33 PM PDT 24 Jul 25 06:03:35 PM PDT 24 518264631 ps
T313 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.56796385 Jul 25 06:03:06 PM PDT 24 Jul 25 06:03:06 PM PDT 24 412134573 ps
T202 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3235517904 Jul 25 06:03:15 PM PDT 24 Jul 25 06:03:19 PM PDT 24 7996316805 ps
T314 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1662979545 Jul 25 06:03:26 PM PDT 24 Jul 25 06:03:27 PM PDT 24 326549882 ps
T315 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3485127732 Jul 25 06:03:42 PM PDT 24 Jul 25 06:03:43 PM PDT 24 486439593 ps
T198 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.306892366 Jul 25 06:03:26 PM PDT 24 Jul 25 06:03:31 PM PDT 24 8562471682 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.975415195 Jul 25 06:03:06 PM PDT 24 Jul 25 06:03:08 PM PDT 24 403177196 ps
T317 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3390283855 Jul 25 06:03:05 PM PDT 24 Jul 25 06:03:08 PM PDT 24 978592803 ps
T318 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.259037274 Jul 25 06:03:19 PM PDT 24 Jul 25 06:03:21 PM PDT 24 334163405 ps
T319 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1055384258 Jul 25 06:03:26 PM PDT 24 Jul 25 06:03:30 PM PDT 24 436938257 ps
T320 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1435890708 Jul 25 06:03:08 PM PDT 24 Jul 25 06:03:10 PM PDT 24 2314743687 ps
T321 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4149935080 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:36 PM PDT 24 409157173 ps
T322 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.925680536 Jul 25 06:03:12 PM PDT 24 Jul 25 06:03:16 PM PDT 24 4486169300 ps
T323 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4025636159 Jul 25 06:03:12 PM PDT 24 Jul 25 06:03:14 PM PDT 24 1004577028 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.998364136 Jul 25 06:02:56 PM PDT 24 Jul 25 06:02:57 PM PDT 24 431907970 ps
T324 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1831778049 Jul 25 06:03:35 PM PDT 24 Jul 25 06:03:35 PM PDT 24 424291445 ps
T325 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2223189774 Jul 25 06:03:18 PM PDT 24 Jul 25 06:03:25 PM PDT 24 2937551805 ps
T326 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.566277218 Jul 25 06:03:09 PM PDT 24 Jul 25 06:03:10 PM PDT 24 546440558 ps
T327 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.350963429 Jul 25 06:03:24 PM PDT 24 Jul 25 06:03:26 PM PDT 24 2623693079 ps
T328 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1660738436 Jul 25 06:03:12 PM PDT 24 Jul 25 06:03:16 PM PDT 24 4207420760 ps
T329 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1129507120 Jul 25 06:03:29 PM PDT 24 Jul 25 06:03:31 PM PDT 24 2090683492 ps
T330 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.411009830 Jul 25 06:03:06 PM PDT 24 Jul 25 06:03:11 PM PDT 24 4622578750 ps
T66 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3173200907 Jul 25 06:03:17 PM PDT 24 Jul 25 06:03:19 PM PDT 24 5736030318 ps
T68 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.793797604 Jul 25 06:03:05 PM PDT 24 Jul 25 06:03:06 PM PDT 24 1337697051 ps
T331 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.438198419 Jul 25 06:03:27 PM PDT 24 Jul 25 06:03:30 PM PDT 24 760911752 ps
T332 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4127567859 Jul 25 06:03:07 PM PDT 24 Jul 25 06:03:08 PM PDT 24 446052511 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3445008244 Jul 25 06:03:27 PM PDT 24 Jul 25 06:03:28 PM PDT 24 519759765 ps
T334 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3656149471 Jul 25 06:03:08 PM PDT 24 Jul 25 06:03:09 PM PDT 24 372656312 ps
T335 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2563834361 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:14 PM PDT 24 487255441 ps
T336 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2910374284 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:16 PM PDT 24 510690985 ps
T337 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.474303640 Jul 25 06:03:06 PM PDT 24 Jul 25 06:03:07 PM PDT 24 418689733 ps
T338 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3679771656 Jul 25 06:03:18 PM PDT 24 Jul 25 06:03:19 PM PDT 24 406795570 ps
T339 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3120868789 Jul 25 06:03:21 PM PDT 24 Jul 25 06:03:22 PM PDT 24 435981020 ps
T340 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2843869507 Jul 25 06:03:08 PM PDT 24 Jul 25 06:03:10 PM PDT 24 422242941 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.384377046 Jul 25 06:03:06 PM PDT 24 Jul 25 06:03:08 PM PDT 24 564986438 ps
T342 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4277422144 Jul 25 06:03:32 PM PDT 24 Jul 25 06:03:33 PM PDT 24 450101616 ps
T199 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1738035236 Jul 25 06:03:29 PM PDT 24 Jul 25 06:03:34 PM PDT 24 8294931174 ps
T343 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2851689651 Jul 25 06:03:16 PM PDT 24 Jul 25 06:03:17 PM PDT 24 295484185 ps
T200 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3100508546 Jul 25 06:03:13 PM PDT 24 Jul 25 06:03:17 PM PDT 24 8678356810 ps
T344 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3413634305 Jul 25 06:03:13 PM PDT 24 Jul 25 06:03:16 PM PDT 24 2535157843 ps
T67 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.677977594 Jul 25 06:03:07 PM PDT 24 Jul 25 06:03:09 PM PDT 24 556608257 ps
T345 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1404543197 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 314696759 ps
T346 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3290421211 Jul 25 06:03:32 PM PDT 24 Jul 25 06:03:33 PM PDT 24 473841815 ps
T347 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2397140111 Jul 25 06:03:16 PM PDT 24 Jul 25 06:03:29 PM PDT 24 8053081491 ps
T348 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2940481467 Jul 25 06:03:29 PM PDT 24 Jul 25 06:03:30 PM PDT 24 546756544 ps
T349 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2849357509 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 463438184 ps
T350 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1237627592 Jul 25 06:03:17 PM PDT 24 Jul 25 06:03:18 PM PDT 24 420743384 ps
T351 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2375798257 Jul 25 06:03:08 PM PDT 24 Jul 25 06:03:09 PM PDT 24 306101690 ps
T352 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1898136408 Jul 25 06:03:46 PM PDT 24 Jul 25 06:03:47 PM PDT 24 437833908 ps
T353 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.769030261 Jul 25 06:03:29 PM PDT 24 Jul 25 06:03:30 PM PDT 24 413355002 ps
T354 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3459254223 Jul 25 06:03:29 PM PDT 24 Jul 25 06:03:30 PM PDT 24 495296553 ps
T355 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2005718241 Jul 25 06:02:59 PM PDT 24 Jul 25 06:03:00 PM PDT 24 299999125 ps
T73 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3428193585 Jul 25 06:03:06 PM PDT 24 Jul 25 06:03:07 PM PDT 24 350130571 ps
T356 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4273467979 Jul 25 06:03:17 PM PDT 24 Jul 25 06:03:18 PM PDT 24 2238062098 ps
T357 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3700134721 Jul 25 06:03:32 PM PDT 24 Jul 25 06:03:33 PM PDT 24 385724186 ps
T358 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2259403370 Jul 25 06:03:09 PM PDT 24 Jul 25 06:03:10 PM PDT 24 294065385 ps
T359 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3755927756 Jul 25 06:03:16 PM PDT 24 Jul 25 06:03:18 PM PDT 24 378464671 ps
T360 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3881289080 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 373564193 ps
T361 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.232064051 Jul 25 06:03:34 PM PDT 24 Jul 25 06:03:35 PM PDT 24 422232034 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.701268388 Jul 25 06:02:58 PM PDT 24 Jul 25 06:03:01 PM PDT 24 2752303697 ps
T363 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1919728956 Jul 25 06:03:30 PM PDT 24 Jul 25 06:03:31 PM PDT 24 1011980376 ps
T364 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3505551383 Jul 25 06:03:09 PM PDT 24 Jul 25 06:03:10 PM PDT 24 528324818 ps
T365 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.946193642 Jul 25 06:03:12 PM PDT 24 Jul 25 06:03:13 PM PDT 24 469466402 ps
T366 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2791275096 Jul 25 06:03:27 PM PDT 24 Jul 25 06:03:28 PM PDT 24 527384848 ps
T367 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3024816348 Jul 25 06:03:08 PM PDT 24 Jul 25 06:03:09 PM PDT 24 310303854 ps
T368 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1426892927 Jul 25 06:03:31 PM PDT 24 Jul 25 06:03:32 PM PDT 24 287037020 ps
T69 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.230272935 Jul 25 06:03:11 PM PDT 24 Jul 25 06:03:12 PM PDT 24 507656737 ps
T369 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1249623324 Jul 25 06:03:20 PM PDT 24 Jul 25 06:03:22 PM PDT 24 440298544 ps
T370 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3700465158 Jul 25 06:03:54 PM PDT 24 Jul 25 06:03:56 PM PDT 24 326623401 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1138359051 Jul 25 06:03:06 PM PDT 24 Jul 25 06:03:08 PM PDT 24 596885458 ps
T372 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3014377784 Jul 25 06:03:09 PM PDT 24 Jul 25 06:03:13 PM PDT 24 8089381686 ps
T373 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1229220526 Jul 25 06:03:35 PM PDT 24 Jul 25 06:03:36 PM PDT 24 464952944 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.960602231 Jul 25 06:03:06 PM PDT 24 Jul 25 06:03:07 PM PDT 24 324466993 ps
T375 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.81583690 Jul 25 06:03:09 PM PDT 24 Jul 25 06:03:12 PM PDT 24 4673490272 ps
T376 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2126921870 Jul 25 06:03:25 PM PDT 24 Jul 25 06:03:32 PM PDT 24 4373279032 ps
T377 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.211351010 Jul 25 06:03:07 PM PDT 24 Jul 25 06:03:10 PM PDT 24 962077276 ps
T378 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.362681151 Jul 25 06:03:13 PM PDT 24 Jul 25 06:03:14 PM PDT 24 411405814 ps
T379 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3954186045 Jul 25 06:03:13 PM PDT 24 Jul 25 06:03:14 PM PDT 24 326903170 ps
T380 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3617079392 Jul 25 06:03:10 PM PDT 24 Jul 25 06:03:11 PM PDT 24 1347976517 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1184096592 Jul 25 06:02:58 PM PDT 24 Jul 25 06:02:59 PM PDT 24 648186683 ps
T381 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.313486409 Jul 25 06:03:33 PM PDT 24 Jul 25 06:03:34 PM PDT 24 382036929 ps
T382 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2556055943 Jul 25 06:03:32 PM PDT 24 Jul 25 06:03:33 PM PDT 24 340298212 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2503603799 Jul 25 06:03:20 PM PDT 24 Jul 25 06:03:22 PM PDT 24 1192468006 ps
T383 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2768619007 Jul 25 06:03:17 PM PDT 24 Jul 25 06:03:18 PM PDT 24 1056323179 ps
T384 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3001369799 Jul 25 06:03:32 PM PDT 24 Jul 25 06:03:33 PM PDT 24 461608167 ps
T385 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3972835074 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:17 PM PDT 24 389099041 ps
T386 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3786968885 Jul 25 06:03:29 PM PDT 24 Jul 25 06:03:30 PM PDT 24 449156581 ps
T387 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.36714819 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:15 PM PDT 24 300499776 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1461443216 Jul 25 06:03:06 PM PDT 24 Jul 25 06:03:07 PM PDT 24 561041043 ps
T389 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.919365024 Jul 25 06:03:07 PM PDT 24 Jul 25 06:03:08 PM PDT 24 456408949 ps
T390 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.986762435 Jul 25 06:03:40 PM PDT 24 Jul 25 06:03:41 PM PDT 24 370713667 ps
T391 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.556743339 Jul 25 06:03:19 PM PDT 24 Jul 25 06:03:21 PM PDT 24 4227926558 ps
T392 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3269288233 Jul 25 06:03:19 PM PDT 24 Jul 25 06:03:21 PM PDT 24 502985664 ps
T393 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.141680446 Jul 25 06:03:09 PM PDT 24 Jul 25 06:03:10 PM PDT 24 430723209 ps
T394 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4029416339 Jul 25 06:03:17 PM PDT 24 Jul 25 06:03:21 PM PDT 24 9053832999 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3523462320 Jul 25 06:03:16 PM PDT 24 Jul 25 06:03:17 PM PDT 24 566498712 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1649807653 Jul 25 06:03:10 PM PDT 24 Jul 25 06:03:27 PM PDT 24 7408268690 ps
T397 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2148012640 Jul 25 06:03:08 PM PDT 24 Jul 25 06:03:09 PM PDT 24 384391337 ps
T398 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.199442333 Jul 25 06:03:15 PM PDT 24 Jul 25 06:03:18 PM PDT 24 2696144002 ps
T399 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2621756271 Jul 25 06:03:24 PM PDT 24 Jul 25 06:03:26 PM PDT 24 874858498 ps
T400 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4294687619 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:16 PM PDT 24 439378464 ps
T401 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1013997819 Jul 25 06:03:16 PM PDT 24 Jul 25 06:03:18 PM PDT 24 476974600 ps
T402 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2288954611 Jul 25 06:02:57 PM PDT 24 Jul 25 06:02:58 PM PDT 24 345335794 ps
T403 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1750056288 Jul 25 06:03:25 PM PDT 24 Jul 25 06:03:37 PM PDT 24 8204418602 ps
T404 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.808889893 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:22 PM PDT 24 8764227402 ps
T405 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1367786691 Jul 25 06:03:15 PM PDT 24 Jul 25 06:03:16 PM PDT 24 958903048 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2348156471 Jul 25 06:02:58 PM PDT 24 Jul 25 06:03:00 PM PDT 24 594875111 ps
T407 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2978844773 Jul 25 06:03:12 PM PDT 24 Jul 25 06:03:13 PM PDT 24 454273656 ps
T408 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2059117305 Jul 25 06:03:27 PM PDT 24 Jul 25 06:03:28 PM PDT 24 1105641182 ps
T409 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3321071130 Jul 25 06:02:58 PM PDT 24 Jul 25 06:02:59 PM PDT 24 436181686 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4203008174 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:15 PM PDT 24 306023731 ps
T411 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1937537177 Jul 25 06:03:32 PM PDT 24 Jul 25 06:03:33 PM PDT 24 347527926 ps
T412 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2988219941 Jul 25 06:03:16 PM PDT 24 Jul 25 06:03:18 PM PDT 24 446135843 ps
T413 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1640774168 Jul 25 06:03:14 PM PDT 24 Jul 25 06:03:15 PM PDT 24 383992842 ps
T72 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2357100860 Jul 25 06:03:11 PM PDT 24 Jul 25 06:03:12 PM PDT 24 577320381 ps
T414 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.89061600 Jul 25 06:02:57 PM PDT 24 Jul 25 06:02:58 PM PDT 24 420947098 ps
T415 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3594671642 Jul 25 06:03:50 PM PDT 24 Jul 25 06:03:52 PM PDT 24 509187852 ps
T416 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2686423455 Jul 25 06:03:07 PM PDT 24 Jul 25 06:03:08 PM PDT 24 378864505 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3425324511 Jul 25 06:03:10 PM PDT 24 Jul 25 06:03:11 PM PDT 24 340929148 ps
T418 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.720996969 Jul 25 06:03:33 PM PDT 24 Jul 25 06:03:34 PM PDT 24 355723774 ps
T419 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1481481111 Jul 25 06:03:08 PM PDT 24 Jul 25 06:03:09 PM PDT 24 457766928 ps
T420 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4135825621 Jul 25 06:03:28 PM PDT 24 Jul 25 06:03:29 PM PDT 24 545501694 ps

Test location /workspace/coverage/default/22.aon_timer_prescaler.1244149246
Short name T9
Test name
Test status
Simulation time 37961350023 ps
CPU time 48.57 seconds
Started Jul 25 06:02:08 PM PDT 24
Finished Jul 25 06:02:56 PM PDT 24
Peak memory 196932 kb
Host smart-cc3292d3-94a8-4aa3-b857-79489f24564c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244149246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1244149246
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3186126224
Short name T11
Test name
Test status
Simulation time 16872182357 ps
CPU time 128.35 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:04:06 PM PDT 24
Peak memory 206808 kb
Host smart-41784d14-16a5-4553-a5a7-39e77cee4321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186126224 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3186126224
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2171951316
Short name T25
Test name
Test status
Simulation time 1041132014395 ps
CPU time 714.61 seconds
Started Jul 25 06:02:06 PM PDT 24
Finished Jul 25 06:14:01 PM PDT 24
Peak memory 214628 kb
Host smart-f6e8fbe1-3cf4-4dd8-b98e-c676d582f0ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171951316 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2171951316
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2679409887
Short name T42
Test name
Test status
Simulation time 8050276312 ps
CPU time 12.64 seconds
Started Jul 25 06:02:56 PM PDT 24
Finished Jul 25 06:03:09 PM PDT 24
Peak memory 198784 kb
Host smart-ceaedbf5-c705-4d3e-9844-02fe162abfbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679409887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2679409887
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3000336788
Short name T58
Test name
Test status
Simulation time 209312479316 ps
CPU time 526.33 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:10:58 PM PDT 24
Peak memory 204176 kb
Host smart-3cc318c9-9d41-4055-bbc6-cb920a2af6ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000336788 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3000336788
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2709678031
Short name T8
Test name
Test status
Simulation time 6445529104 ps
CPU time 5.7 seconds
Started Jul 25 06:01:47 PM PDT 24
Finished Jul 25 06:01:53 PM PDT 24
Peak memory 191888 kb
Host smart-302f3e80-fa13-464a-baef-83d68f346871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709678031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2709678031
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3514452780
Short name T94
Test name
Test status
Simulation time 1081610484971 ps
CPU time 773.97 seconds
Started Jul 25 06:02:27 PM PDT 24
Finished Jul 25 06:15:21 PM PDT 24
Peak memory 206776 kb
Host smart-bfb4b21e-bc45-47cf-b031-0b93cdc47453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514452780 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3514452780
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2036795335
Short name T81
Test name
Test status
Simulation time 93635067189 ps
CPU time 601.32 seconds
Started Jul 25 06:01:59 PM PDT 24
Finished Jul 25 06:12:01 PM PDT 24
Peak memory 214492 kb
Host smart-5e67660f-7b4d-450f-9351-7e521ed84e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036795335 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2036795335
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3990805118
Short name T116
Test name
Test status
Simulation time 286965015643 ps
CPU time 631.05 seconds
Started Jul 25 06:01:59 PM PDT 24
Finished Jul 25 06:12:30 PM PDT 24
Peak memory 207016 kb
Host smart-c4e26ecf-0fc1-4073-9543-f341e5eaa7bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990805118 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3990805118
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.689974933
Short name T28
Test name
Test status
Simulation time 150702935154 ps
CPU time 1241.53 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:22:51 PM PDT 24
Peak memory 211280 kb
Host smart-49736854-5593-406f-97f0-fffcb0619bf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689974933 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.689974933
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.4250886088
Short name T118
Test name
Test status
Simulation time 41511228363 ps
CPU time 280.94 seconds
Started Jul 25 06:01:55 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 206676 kb
Host smart-5cd47dcf-6eab-45c3-a863-122f36da1535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250886088 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.4250886088
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3879258783
Short name T87
Test name
Test status
Simulation time 171970524719 ps
CPU time 361.46 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:09:00 PM PDT 24
Peak memory 214896 kb
Host smart-32f855bd-9c59-443d-88ce-5c619e39043b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879258783 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3879258783
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2235761562
Short name T148
Test name
Test status
Simulation time 531084100027 ps
CPU time 1382.81 seconds
Started Jul 25 06:02:24 PM PDT 24
Finished Jul 25 06:25:28 PM PDT 24
Peak memory 215088 kb
Host smart-a78ccfb6-7d7b-48fe-98a1-c5f4e1ce1e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235761562 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2235761562
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.683028169
Short name T20
Test name
Test status
Simulation time 8540206017 ps
CPU time 1.72 seconds
Started Jul 25 06:01:49 PM PDT 24
Finished Jul 25 06:01:51 PM PDT 24
Peak memory 215880 kb
Host smart-74d5261f-8bb2-4e0e-9fc6-6bbda9145eed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683028169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.683028169
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.956893817
Short name T50
Test name
Test status
Simulation time 55460160816 ps
CPU time 226.59 seconds
Started Jul 25 06:02:15 PM PDT 24
Finished Jul 25 06:06:02 PM PDT 24
Peak memory 198616 kb
Host smart-4478485d-2b57-46f8-83a9-8d66378a5246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956893817 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.956893817
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3025392782
Short name T114
Test name
Test status
Simulation time 58284489091 ps
CPU time 444.37 seconds
Started Jul 25 06:02:15 PM PDT 24
Finished Jul 25 06:09:40 PM PDT 24
Peak memory 209312 kb
Host smart-0b280d3c-5e87-44e6-a30b-a7ed81478673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025392782 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3025392782
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1133958838
Short name T47
Test name
Test status
Simulation time 79962430011 ps
CPU time 578.2 seconds
Started Jul 25 06:01:57 PM PDT 24
Finished Jul 25 06:11:36 PM PDT 24
Peak memory 203772 kb
Host smart-4053cb02-266e-4548-a641-1bf9ed12403c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133958838 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1133958838
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.876618276
Short name T59
Test name
Test status
Simulation time 618455513721 ps
CPU time 854.24 seconds
Started Jul 25 06:01:47 PM PDT 24
Finished Jul 25 06:16:02 PM PDT 24
Peak memory 214876 kb
Host smart-0e06af85-781b-46cc-9273-8d3a64a46d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876618276 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.876618276
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.2727782518
Short name T107
Test name
Test status
Simulation time 666635660893 ps
CPU time 1084.35 seconds
Started Jul 25 06:02:41 PM PDT 24
Finished Jul 25 06:20:45 PM PDT 24
Peak memory 210576 kb
Host smart-d96025b1-a8fa-4b0f-a260-c2b3281b18b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727782518 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.2727782518
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1907670340
Short name T13
Test name
Test status
Simulation time 201337788166 ps
CPU time 58.57 seconds
Started Jul 25 06:01:48 PM PDT 24
Finished Jul 25 06:02:46 PM PDT 24
Peak memory 193020 kb
Host smart-bec4b9b7-3901-492e-b6f7-e886e3b43bb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907670340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1907670340
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.517275470
Short name T126
Test name
Test status
Simulation time 222321081790 ps
CPU time 128.88 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:04:21 PM PDT 24
Peak memory 184576 kb
Host smart-4ecffb39-433a-430f-bb08-2a716b654f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517275470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.517275470
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2489115084
Short name T83
Test name
Test status
Simulation time 57327032406 ps
CPU time 292.06 seconds
Started Jul 25 06:02:41 PM PDT 24
Finished Jul 25 06:07:33 PM PDT 24
Peak memory 206688 kb
Host smart-30521d39-3d25-45b0-9b93-5f8494ccebc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489115084 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2489115084
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.865520755
Short name T104
Test name
Test status
Simulation time 28198552761 ps
CPU time 110.55 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:04:49 PM PDT 24
Peak memory 206808 kb
Host smart-cd48ce3b-0bb5-4c4f-b88f-c20136ea7b29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865520755 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.865520755
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3412637761
Short name T106
Test name
Test status
Simulation time 173339135885 ps
CPU time 273.31 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:06:43 PM PDT 24
Peak memory 198260 kb
Host smart-b41fe77b-7b98-41c4-8c19-bf6263080646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412637761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3412637761
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.492484098
Short name T119
Test name
Test status
Simulation time 65263381007 ps
CPU time 369.5 seconds
Started Jul 25 06:01:54 PM PDT 24
Finished Jul 25 06:08:04 PM PDT 24
Peak memory 201108 kb
Host smart-40760d1c-ee07-4cb0-96d7-4151839c6e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492484098 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.492484098
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2210354742
Short name T91
Test name
Test status
Simulation time 95484910965 ps
CPU time 576.96 seconds
Started Jul 25 06:01:59 PM PDT 24
Finished Jul 25 06:11:36 PM PDT 24
Peak memory 204728 kb
Host smart-f83e040c-3852-4577-aac6-0b6c74adcadb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210354742 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2210354742
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3377818787
Short name T144
Test name
Test status
Simulation time 6473909313 ps
CPU time 2.49 seconds
Started Jul 25 06:01:57 PM PDT 24
Finished Jul 25 06:02:00 PM PDT 24
Peak memory 193004 kb
Host smart-e89ed049-f8b5-477f-b75e-f6a7278d4fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377818787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3377818787
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1730724608
Short name T132
Test name
Test status
Simulation time 301111405800 ps
CPU time 113 seconds
Started Jul 25 06:02:11 PM PDT 24
Finished Jul 25 06:04:04 PM PDT 24
Peak memory 192984 kb
Host smart-308da525-8c37-4b59-af06-5ec0c60ac526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730724608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1730724608
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1508000876
Short name T16
Test name
Test status
Simulation time 60032525218 ps
CPU time 58.99 seconds
Started Jul 25 06:01:48 PM PDT 24
Finished Jul 25 06:02:47 PM PDT 24
Peak memory 206708 kb
Host smart-14ace7e6-4723-4dc0-b714-0b428b810986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508000876 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1508000876
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1064618465
Short name T34
Test name
Test status
Simulation time 150485508601 ps
CPU time 214.01 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:06:32 PM PDT 24
Peak memory 191868 kb
Host smart-24d94887-4eeb-4be1-9f2f-6be28d765934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064618465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1064618465
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3494773546
Short name T60
Test name
Test status
Simulation time 524063597 ps
CPU time 1.43 seconds
Started Jul 25 06:03:09 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 193748 kb
Host smart-208bb874-57a8-4dab-bc48-931c0d15723f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494773546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3494773546
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2475051756
Short name T15
Test name
Test status
Simulation time 60250412967 ps
CPU time 628.71 seconds
Started Jul 25 06:01:54 PM PDT 24
Finished Jul 25 06:12:23 PM PDT 24
Peak memory 206716 kb
Host smart-b6aea3b6-f942-4a05-90c8-c6f50739b724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475051756 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2475051756
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1029786495
Short name T2
Test name
Test status
Simulation time 96855962660 ps
CPU time 39.02 seconds
Started Jul 25 06:02:39 PM PDT 24
Finished Jul 25 06:03:19 PM PDT 24
Peak memory 192900 kb
Host smart-26c2c808-f430-4117-b9f5-092026d1d57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029786495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1029786495
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2958182456
Short name T48
Test name
Test status
Simulation time 65296207165 ps
CPU time 359.7 seconds
Started Jul 25 06:02:41 PM PDT 24
Finished Jul 25 06:08:41 PM PDT 24
Peak memory 201100 kb
Host smart-918cf2bb-1846-4e8f-8d37-e33c775936df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958182456 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2958182456
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1554030738
Short name T39
Test name
Test status
Simulation time 31735848100 ps
CPU time 6.65 seconds
Started Jul 25 06:02:24 PM PDT 24
Finished Jul 25 06:02:31 PM PDT 24
Peak memory 192604 kb
Host smart-279375de-42fd-4854-97c5-6d16cc863cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554030738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1554030738
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4262056097
Short name T117
Test name
Test status
Simulation time 151792258445 ps
CPU time 59.35 seconds
Started Jul 25 06:02:00 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 198252 kb
Host smart-7dc5b77c-e48e-42d4-8de9-15f302237c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262056097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4262056097
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.4163763863
Short name T32
Test name
Test status
Simulation time 44198258477 ps
CPU time 32.29 seconds
Started Jul 25 06:02:19 PM PDT 24
Finished Jul 25 06:02:52 PM PDT 24
Peak memory 191888 kb
Host smart-a0aab797-d5a8-4348-823d-35928351df02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163763863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.4163763863
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1223559903
Short name T103
Test name
Test status
Simulation time 130909996531 ps
CPU time 126.33 seconds
Started Jul 25 06:02:04 PM PDT 24
Finished Jul 25 06:04:10 PM PDT 24
Peak memory 192920 kb
Host smart-13522db8-a217-45dc-946c-34875d3b942f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223559903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1223559903
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1403973919
Short name T112
Test name
Test status
Simulation time 55175367449 ps
CPU time 28.31 seconds
Started Jul 25 06:02:40 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 191900 kb
Host smart-262258ac-074e-4d58-b615-b31c2f153d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403973919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1403973919
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2172648818
Short name T82
Test name
Test status
Simulation time 144024758661 ps
CPU time 398.71 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:08:48 PM PDT 24
Peak memory 210704 kb
Host smart-b771dc41-4eac-41af-ba96-9814f0d52865
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172648818 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2172648818
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1319950245
Short name T128
Test name
Test status
Simulation time 81692198031 ps
CPU time 25.88 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:02:35 PM PDT 24
Peak memory 198260 kb
Host smart-78785575-92cd-4e67-8698-eded95817eb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319950245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1319950245
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3161227854
Short name T33
Test name
Test status
Simulation time 228178011557 ps
CPU time 337.65 seconds
Started Jul 25 06:01:50 PM PDT 24
Finished Jul 25 06:07:28 PM PDT 24
Peak memory 192464 kb
Host smart-a8500f81-0536-4dc9-978a-f9c39434ba84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161227854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3161227854
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2742026515
Short name T149
Test name
Test status
Simulation time 97565362339 ps
CPU time 286.49 seconds
Started Jul 25 06:02:13 PM PDT 24
Finished Jul 25 06:07:00 PM PDT 24
Peak memory 201164 kb
Host smart-1e69be04-4766-4946-afde-fe2e2ad941d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742026515 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2742026515
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3036225993
Short name T105
Test name
Test status
Simulation time 138340494331 ps
CPU time 657.54 seconds
Started Jul 25 06:02:40 PM PDT 24
Finished Jul 25 06:13:38 PM PDT 24
Peak memory 214460 kb
Host smart-a5ef55ca-692e-4a27-881a-43b1ccea80d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036225993 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3036225993
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4118363689
Short name T161
Test name
Test status
Simulation time 29454662956 ps
CPU time 6.18 seconds
Started Jul 25 06:02:41 PM PDT 24
Finished Jul 25 06:02:48 PM PDT 24
Peak memory 191900 kb
Host smart-5010214d-3d04-4a7b-b0c4-c99f60670051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118363689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4118363689
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3858020293
Short name T90
Test name
Test status
Simulation time 345747341853 ps
CPU time 345.18 seconds
Started Jul 25 06:02:55 PM PDT 24
Finished Jul 25 06:08:40 PM PDT 24
Peak memory 209928 kb
Host smart-6ebe117c-61e2-4f6f-9d23-0f348a44f470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858020293 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3858020293
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1654990457
Short name T145
Test name
Test status
Simulation time 296640887830 ps
CPU time 95.55 seconds
Started Jul 25 06:02:55 PM PDT 24
Finished Jul 25 06:04:31 PM PDT 24
Peak memory 193004 kb
Host smart-d758a85f-644f-4daa-8eb6-fe962b48a332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654990457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1654990457
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1052270291
Short name T122
Test name
Test status
Simulation time 69091904757 ps
CPU time 33.05 seconds
Started Jul 25 06:02:15 PM PDT 24
Finished Jul 25 06:02:48 PM PDT 24
Peak memory 191900 kb
Host smart-b2f4c8ef-a531-498d-8645-1ce7e90bfb67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052270291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1052270291
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.174783366
Short name T154
Test name
Test status
Simulation time 541030468421 ps
CPU time 302.72 seconds
Started Jul 25 06:02:42 PM PDT 24
Finished Jul 25 06:07:45 PM PDT 24
Peak memory 201820 kb
Host smart-160458d8-90d2-494d-87d8-ad411ea259fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174783366 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.174783366
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2100582231
Short name T170
Test name
Test status
Simulation time 100108028828 ps
CPU time 927.88 seconds
Started Jul 25 06:02:39 PM PDT 24
Finished Jul 25 06:18:08 PM PDT 24
Peak memory 211264 kb
Host smart-cd7ec9aa-5b94-4e45-a176-255181990d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100582231 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2100582231
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.357670239
Short name T171
Test name
Test status
Simulation time 38861099001 ps
CPU time 406.98 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:09:45 PM PDT 24
Peak memory 206672 kb
Host smart-ae75838a-d8aa-4dc5-a1a6-46b9c36e6307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357670239 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.357670239
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.341064679
Short name T141
Test name
Test status
Simulation time 164035229987 ps
CPU time 44.81 seconds
Started Jul 25 06:02:00 PM PDT 24
Finished Jul 25 06:02:45 PM PDT 24
Peak memory 198108 kb
Host smart-0dd389db-46de-4f44-afa3-342fe80c6c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341064679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.341064679
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4283557817
Short name T147
Test name
Test status
Simulation time 50604953940 ps
CPU time 205.77 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:05:35 PM PDT 24
Peak memory 206696 kb
Host smart-8d802e3e-7f0f-4914-985a-a6856471055b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283557817 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4283557817
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1873775037
Short name T88
Test name
Test status
Simulation time 75393079860 ps
CPU time 289.26 seconds
Started Jul 25 06:02:29 PM PDT 24
Finished Jul 25 06:07:18 PM PDT 24
Peak memory 200276 kb
Host smart-7259800c-e578-4c7c-a634-1669ce97ba61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873775037 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1873775037
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2548827322
Short name T158
Test name
Test status
Simulation time 161900412426 ps
CPU time 51.84 seconds
Started Jul 25 06:02:56 PM PDT 24
Finished Jul 25 06:03:48 PM PDT 24
Peak memory 193016 kb
Host smart-344cb188-e088-4b25-983f-758a3d2a86c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548827322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2548827322
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.833822281
Short name T138
Test name
Test status
Simulation time 214850633243 ps
CPU time 319.2 seconds
Started Jul 25 06:02:06 PM PDT 24
Finished Jul 25 06:07:25 PM PDT 24
Peak memory 191916 kb
Host smart-40bce2e7-4549-4477-89ed-01d67e94267a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833822281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.833822281
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1464635113
Short name T162
Test name
Test status
Simulation time 163022848880 ps
CPU time 11.66 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:02:24 PM PDT 24
Peak memory 198232 kb
Host smart-fcf99900-9d48-4336-be3d-64ad53704dd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464635113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1464635113
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.210780072
Short name T84
Test name
Test status
Simulation time 45853629971 ps
CPU time 482.15 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:10:12 PM PDT 24
Peak memory 209504 kb
Host smart-429fb61d-2ddc-4c2d-9c9b-084819abf501
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210780072 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.210780072
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.901592190
Short name T175
Test name
Test status
Simulation time 67357494420 ps
CPU time 90.08 seconds
Started Jul 25 06:01:47 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 191908 kb
Host smart-64df5884-6854-4d5a-a958-889d5c5f0e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901592190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.901592190
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.810602796
Short name T109
Test name
Test status
Simulation time 112259902471 ps
CPU time 151.74 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:04:44 PM PDT 24
Peak memory 198172 kb
Host smart-849ab63c-ab69-44cf-b522-95e0145b9059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810602796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.810602796
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1333955204
Short name T26
Test name
Test status
Simulation time 77255585505 ps
CPU time 317.99 seconds
Started Jul 25 06:02:21 PM PDT 24
Finished Jul 25 06:07:39 PM PDT 24
Peak memory 209236 kb
Host smart-f6ddf4f8-9f69-494f-96a2-a72cd0da6b60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333955204 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1333955204
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.107877761
Short name T150
Test name
Test status
Simulation time 174077585944 ps
CPU time 235.28 seconds
Started Jul 25 06:02:19 PM PDT 24
Finished Jul 25 06:06:15 PM PDT 24
Peak memory 192552 kb
Host smart-3d557470-c911-4f81-af71-741339c8638a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107877761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.107877761
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3758160677
Short name T135
Test name
Test status
Simulation time 90643548727 ps
CPU time 32.41 seconds
Started Jul 25 06:02:21 PM PDT 24
Finished Jul 25 06:02:53 PM PDT 24
Peak memory 191948 kb
Host smart-0c4c3e7f-83aa-4625-945e-1f4929dcc4ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758160677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3758160677
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.4137053655
Short name T115
Test name
Test status
Simulation time 143061561279 ps
CPU time 25.37 seconds
Started Jul 25 06:02:43 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 198272 kb
Host smart-33203c0f-d93a-427f-be6f-eb7bd4c9e50c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137053655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.4137053655
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1464713133
Short name T156
Test name
Test status
Simulation time 223140008192 ps
CPU time 323.34 seconds
Started Jul 25 06:02:43 PM PDT 24
Finished Jul 25 06:08:07 PM PDT 24
Peak memory 184160 kb
Host smart-ceb23eea-cae3-4a09-84a6-fbdc29cf168d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464713133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1464713133
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.99889011
Short name T124
Test name
Test status
Simulation time 151432012758 ps
CPU time 139.09 seconds
Started Jul 25 06:02:44 PM PDT 24
Finished Jul 25 06:05:03 PM PDT 24
Peak memory 193012 kb
Host smart-29ac38fc-54c1-41d4-a51a-0bccd8879c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99889011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_al
l.99889011
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.185439220
Short name T49
Test name
Test status
Simulation time 50921486336 ps
CPU time 201.97 seconds
Started Jul 25 06:02:56 PM PDT 24
Finished Jul 25 06:06:18 PM PDT 24
Peak memory 198492 kb
Host smart-2a83c1f9-f43f-4099-916d-87b316009826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185439220 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.185439220
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.430264418
Short name T35
Test name
Test status
Simulation time 171607063066 ps
CPU time 266.66 seconds
Started Jul 25 06:02:59 PM PDT 24
Finished Jul 25 06:07:26 PM PDT 24
Peak memory 192560 kb
Host smart-ec888dbc-9b9c-4655-8297-bbb0de2b7574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430264418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.430264418
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3666413958
Short name T102
Test name
Test status
Simulation time 184949811236 ps
CPU time 274.26 seconds
Started Jul 25 06:02:04 PM PDT 24
Finished Jul 25 06:06:39 PM PDT 24
Peak memory 198244 kb
Host smart-e0596a32-b535-4abe-ada6-b356f05b7428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666413958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3666413958
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3438479241
Short name T155
Test name
Test status
Simulation time 143580779101 ps
CPU time 52.39 seconds
Started Jul 25 06:02:13 PM PDT 24
Finished Jul 25 06:03:05 PM PDT 24
Peak memory 184288 kb
Host smart-6e9805a3-8560-42e0-97d1-8ec2967fdf5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438479241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3438479241
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.635721757
Short name T125
Test name
Test status
Simulation time 473101406 ps
CPU time 0.65 seconds
Started Jul 25 06:02:26 PM PDT 24
Finished Jul 25 06:02:26 PM PDT 24
Peak memory 196644 kb
Host smart-706e3afd-4ce6-49b4-b859-6a10ae82e1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635721757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.635721757
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2756089512
Short name T184
Test name
Test status
Simulation time 576956101510 ps
CPU time 891.09 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:17:50 PM PDT 24
Peak memory 192908 kb
Host smart-38bd580e-e6ec-4e2f-96c4-32e94750fe4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756089512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2756089512
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.959238753
Short name T127
Test name
Test status
Simulation time 56993115038 ps
CPU time 247.03 seconds
Started Jul 25 06:02:55 PM PDT 24
Finished Jul 25 06:07:02 PM PDT 24
Peak memory 198776 kb
Host smart-49073760-39e6-4dc8-838f-972aa00a1b58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959238753 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.959238753
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3135868307
Short name T146
Test name
Test status
Simulation time 537460922 ps
CPU time 0.62 seconds
Started Jul 25 06:02:06 PM PDT 24
Finished Jul 25 06:02:07 PM PDT 24
Peak memory 196624 kb
Host smart-e85e0d85-2d2f-45c5-9f53-2a0350dcb23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135868307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3135868307
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1948824814
Short name T151
Test name
Test status
Simulation time 461865243 ps
CPU time 1.12 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:01:59 PM PDT 24
Peak memory 196664 kb
Host smart-caa894a6-23fc-41df-9a05-4d2bfbf4b1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948824814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1948824814
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3608286422
Short name T85
Test name
Test status
Simulation time 95848684521 ps
CPU time 731.42 seconds
Started Jul 25 06:01:56 PM PDT 24
Finished Jul 25 06:14:08 PM PDT 24
Peak memory 214900 kb
Host smart-64e7bead-bb6c-4e86-84d3-c1cd3d07ec3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608286422 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3608286422
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3048178680
Short name T143
Test name
Test status
Simulation time 607297507 ps
CPU time 1.43 seconds
Started Jul 25 06:02:19 PM PDT 24
Finished Jul 25 06:02:20 PM PDT 24
Peak memory 196656 kb
Host smart-f5df5cfd-998b-4ae2-9f04-102935326736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048178680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3048178680
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3892705993
Short name T183
Test name
Test status
Simulation time 38221633126 ps
CPU time 25.58 seconds
Started Jul 25 06:02:11 PM PDT 24
Finished Jul 25 06:02:37 PM PDT 24
Peak memory 191904 kb
Host smart-e1f5b585-00d3-4341-a818-3a71ba568e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892705993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3892705993
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1431142382
Short name T24
Test name
Test status
Simulation time 404411284 ps
CPU time 0.72 seconds
Started Jul 25 06:01:54 PM PDT 24
Finished Jul 25 06:01:55 PM PDT 24
Peak memory 196592 kb
Host smart-e72b8687-3253-46dd-ab71-9f224bb0ef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431142382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1431142382
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1833738195
Short name T53
Test name
Test status
Simulation time 427813028 ps
CPU time 0.92 seconds
Started Jul 25 06:02:04 PM PDT 24
Finished Jul 25 06:02:05 PM PDT 24
Peak memory 196604 kb
Host smart-8a42d382-f034-4c6e-80e1-0f1317ec57a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833738195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1833738195
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2184271278
Short name T157
Test name
Test status
Simulation time 566814894 ps
CPU time 1.06 seconds
Started Jul 25 06:02:10 PM PDT 24
Finished Jul 25 06:02:11 PM PDT 24
Peak memory 196676 kb
Host smart-bf3e0bc7-7a3a-4ec3-b97c-6ce1df7fe970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184271278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2184271278
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2777966032
Short name T153
Test name
Test status
Simulation time 382183137 ps
CPU time 0.73 seconds
Started Jul 25 06:02:18 PM PDT 24
Finished Jul 25 06:02:19 PM PDT 24
Peak memory 196740 kb
Host smart-7a5e71da-f9f9-4380-a378-7fafabf40a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777966032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2777966032
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2531843879
Short name T140
Test name
Test status
Simulation time 514344348 ps
CPU time 0.65 seconds
Started Jul 25 06:02:20 PM PDT 24
Finished Jul 25 06:02:21 PM PDT 24
Peak memory 196608 kb
Host smart-44334a43-5871-4fbe-b097-12d6cde9abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531843879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2531843879
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.4293270381
Short name T134
Test name
Test status
Simulation time 254088791304 ps
CPU time 349.29 seconds
Started Jul 25 06:02:25 PM PDT 24
Finished Jul 25 06:08:15 PM PDT 24
Peak memory 198272 kb
Host smart-af8fbede-1603-45d5-9e32-3dfe4a255b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293270381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.4293270381
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1132734012
Short name T121
Test name
Test status
Simulation time 565206128 ps
CPU time 0.79 seconds
Started Jul 25 06:01:57 PM PDT 24
Finished Jul 25 06:01:58 PM PDT 24
Peak memory 196656 kb
Host smart-9bec400e-2732-4600-93cf-875f58daa83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132734012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1132734012
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2005391340
Short name T139
Test name
Test status
Simulation time 349415508 ps
CPU time 1.09 seconds
Started Jul 25 06:02:18 PM PDT 24
Finished Jul 25 06:02:20 PM PDT 24
Peak memory 196684 kb
Host smart-32cab113-8748-4cf4-8a3b-c9c16be973be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005391340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2005391340
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1752316676
Short name T120
Test name
Test status
Simulation time 438832854 ps
CPU time 0.74 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:02:13 PM PDT 24
Peak memory 196700 kb
Host smart-5df9e375-e4c8-4aba-a4dc-9e8cc8aee433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752316676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1752316676
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3940481589
Short name T152
Test name
Test status
Simulation time 405823789 ps
CPU time 1.13 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:02:13 PM PDT 24
Peak memory 196600 kb
Host smart-8e066464-9aa4-4f4e-a7d3-5060ca131378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940481589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3940481589
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2254846342
Short name T111
Test name
Test status
Simulation time 549233255 ps
CPU time 0.82 seconds
Started Jul 25 06:02:21 PM PDT 24
Finished Jul 25 06:02:22 PM PDT 24
Peak memory 196644 kb
Host smart-844c7af9-e67b-49b3-8c18-22d15090ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254846342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2254846342
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1339905759
Short name T172
Test name
Test status
Simulation time 282745117833 ps
CPU time 110.56 seconds
Started Jul 25 06:02:42 PM PDT 24
Finished Jul 25 06:04:33 PM PDT 24
Peak memory 198268 kb
Host smart-99a84210-691d-4a59-9ef9-b5fcd60a58bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339905759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1339905759
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3320763419
Short name T137
Test name
Test status
Simulation time 369675743 ps
CPU time 0.72 seconds
Started Jul 25 06:02:43 PM PDT 24
Finished Jul 25 06:02:44 PM PDT 24
Peak memory 196604 kb
Host smart-3f658a56-212a-4431-ae20-671e6057230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320763419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3320763419
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_jump.4059769517
Short name T130
Test name
Test status
Simulation time 406977424 ps
CPU time 1.08 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:58 PM PDT 24
Peak memory 196592 kb
Host smart-8bc35742-2443-4b46-94b7-59f854710514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059769517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.4059769517
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_jump.975512597
Short name T159
Test name
Test status
Simulation time 613942891 ps
CPU time 0.72 seconds
Started Jul 25 06:01:59 PM PDT 24
Finished Jul 25 06:02:00 PM PDT 24
Peak memory 196644 kb
Host smart-7defc030-ab44-47ac-85f4-f189a8e8ae3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975512597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.975512597
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3451972664
Short name T142
Test name
Test status
Simulation time 514922400 ps
CPU time 1.28 seconds
Started Jul 25 06:01:50 PM PDT 24
Finished Jul 25 06:01:52 PM PDT 24
Peak memory 196604 kb
Host smart-4d2cb8cb-5600-4cc2-9bcc-6adc2e058962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451972664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3451972664
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.966095216
Short name T169
Test name
Test status
Simulation time 39807182149 ps
CPU time 142.98 seconds
Started Jul 25 06:01:53 PM PDT 24
Finished Jul 25 06:04:16 PM PDT 24
Peak memory 198452 kb
Host smart-d9a3021e-6fb7-49c7-b0fd-e2d46ef93b5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966095216 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.966095216
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2703225448
Short name T131
Test name
Test status
Simulation time 363514582 ps
CPU time 0.74 seconds
Started Jul 25 06:02:04 PM PDT 24
Finished Jul 25 06:02:05 PM PDT 24
Peak memory 196596 kb
Host smart-256d4390-bc33-4fae-9607-b1e1ee3754a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703225448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2703225448
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.276718753
Short name T93
Test name
Test status
Simulation time 38902473369 ps
CPU time 265.3 seconds
Started Jul 25 06:02:06 PM PDT 24
Finished Jul 25 06:06:32 PM PDT 24
Peak memory 206600 kb
Host smart-f123517d-9d50-459e-9aa3-a5f8032162e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276718753 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.276718753
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2680669018
Short name T89
Test name
Test status
Simulation time 41853452540 ps
CPU time 176.76 seconds
Started Jul 25 06:02:16 PM PDT 24
Finished Jul 25 06:05:13 PM PDT 24
Peak memory 198508 kb
Host smart-f3c7dbb3-554a-40d3-b9e1-3930b2e3483a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680669018 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2680669018
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3299757231
Short name T92
Test name
Test status
Simulation time 39427932460 ps
CPU time 293.34 seconds
Started Jul 25 06:02:14 PM PDT 24
Finished Jul 25 06:07:07 PM PDT 24
Peak memory 206724 kb
Host smart-932448cb-33af-4629-b4ff-cd7a126d758e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299757231 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3299757231
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.987575119
Short name T113
Test name
Test status
Simulation time 553779640 ps
CPU time 0.78 seconds
Started Jul 25 06:02:40 PM PDT 24
Finished Jul 25 06:02:41 PM PDT 24
Peak memory 196616 kb
Host smart-509d217b-41a4-463e-aee9-4ae021a94a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987575119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.987575119
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2832483061
Short name T10
Test name
Test status
Simulation time 589657399 ps
CPU time 1 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 196592 kb
Host smart-86169513-42d0-491c-bd55-3b051faeeb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832483061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2832483061
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3368370284
Short name T174
Test name
Test status
Simulation time 345428378457 ps
CPU time 274.21 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:06:33 PM PDT 24
Peak memory 192516 kb
Host smart-852ee890-8b92-4f4a-9a54-839b171d5d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368370284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3368370284
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1992672978
Short name T98
Test name
Test status
Simulation time 166534503741 ps
CPU time 226.14 seconds
Started Jul 25 06:01:59 PM PDT 24
Finished Jul 25 06:05:45 PM PDT 24
Peak memory 198232 kb
Host smart-599b727a-fde1-4686-ae65-8d6b2f485f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992672978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1992672978
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.882952963
Short name T96
Test name
Test status
Simulation time 410024232 ps
CPU time 1.19 seconds
Started Jul 25 06:02:00 PM PDT 24
Finished Jul 25 06:02:01 PM PDT 24
Peak memory 196672 kb
Host smart-2cee8e25-d750-4df3-a2cd-8dd84296bb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882952963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.882952963
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_jump.715536695
Short name T133
Test name
Test status
Simulation time 492457560 ps
CPU time 0.93 seconds
Started Jul 25 06:02:14 PM PDT 24
Finished Jul 25 06:02:15 PM PDT 24
Peak memory 196604 kb
Host smart-26fb052d-cd0a-4777-88e4-01d66e360b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715536695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.715536695
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.429514652
Short name T173
Test name
Test status
Simulation time 256653434407 ps
CPU time 329.51 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:07:39 PM PDT 24
Peak memory 193008 kb
Host smart-9b0d9787-16bb-4eaf-ae91-b1ad047efd9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429514652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.429514652
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2787386319
Short name T165
Test name
Test status
Simulation time 434877119 ps
CPU time 1.19 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:02:10 PM PDT 24
Peak memory 196576 kb
Host smart-dbad1c3d-4326-4b7d-b564-eb81152b2e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787386319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2787386319
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.58152692
Short name T187
Test name
Test status
Simulation time 40614042681 ps
CPU time 239.51 seconds
Started Jul 25 06:02:42 PM PDT 24
Finished Jul 25 06:06:42 PM PDT 24
Peak memory 214644 kb
Host smart-ea3adb9d-4d62-4fd8-8c6c-823aaff3883e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58152692 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.58152692
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.4238467934
Short name T86
Test name
Test status
Simulation time 98029951857 ps
CPU time 294.84 seconds
Started Jul 25 06:02:42 PM PDT 24
Finished Jul 25 06:07:38 PM PDT 24
Peak memory 207572 kb
Host smart-de7fe2ac-b402-494a-a981-c0c8976a67fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238467934 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.4238467934
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4134732607
Short name T160
Test name
Test status
Simulation time 462091343 ps
CPU time 0.72 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 196596 kb
Host smart-701cfa8b-87f3-46ea-8e89-3ee55596fbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134732607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4134732607
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_jump.4241566745
Short name T123
Test name
Test status
Simulation time 478710055 ps
CPU time 0.81 seconds
Started Jul 25 06:01:56 PM PDT 24
Finished Jul 25 06:01:57 PM PDT 24
Peak memory 196632 kb
Host smart-ed5ddd93-9270-426c-9a79-2aefbab515e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241566745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.4241566745
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4209813869
Short name T108
Test name
Test status
Simulation time 399664077 ps
CPU time 1.17 seconds
Started Jul 25 06:01:57 PM PDT 24
Finished Jul 25 06:01:58 PM PDT 24
Peak memory 196652 kb
Host smart-15aa0910-a853-4088-b755-faf8dbf61749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209813869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4209813869
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2381619717
Short name T40
Test name
Test status
Simulation time 562194080 ps
CPU time 0.95 seconds
Started Jul 25 06:01:47 PM PDT 24
Finished Jul 25 06:01:48 PM PDT 24
Peak memory 196680 kb
Host smart-25b4c2ce-d6d6-42e3-9ffb-7d7442bd068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381619717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2381619717
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3995752062
Short name T168
Test name
Test status
Simulation time 290129715199 ps
CPU time 218.9 seconds
Started Jul 25 06:01:56 PM PDT 24
Finished Jul 25 06:05:35 PM PDT 24
Peak memory 198208 kb
Host smart-c1179536-f0e8-4f86-bede-2779fbd86c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995752062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3995752062
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2622232493
Short name T177
Test name
Test status
Simulation time 86903217741 ps
CPU time 39.15 seconds
Started Jul 25 06:01:56 PM PDT 24
Finished Jul 25 06:02:35 PM PDT 24
Peak memory 192876 kb
Host smart-4b0b1a80-356d-44f6-b7f6-3a309e9ac00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622232493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2622232493
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4081101954
Short name T1
Test name
Test status
Simulation time 516188174 ps
CPU time 1.31 seconds
Started Jul 25 06:02:08 PM PDT 24
Finished Jul 25 06:02:09 PM PDT 24
Peak memory 196588 kb
Host smart-c4d8f183-0f6d-487c-af0d-9e33fba8b94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081101954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4081101954
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_jump.562015642
Short name T95
Test name
Test status
Simulation time 541633899 ps
CPU time 1.13 seconds
Started Jul 25 06:01:47 PM PDT 24
Finished Jul 25 06:01:48 PM PDT 24
Peak memory 196552 kb
Host smart-4af15776-da6b-4f80-abf1-94a742a3bb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562015642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.562015642
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2349513997
Short name T6
Test name
Test status
Simulation time 443477933 ps
CPU time 0.71 seconds
Started Jul 25 06:02:15 PM PDT 24
Finished Jul 25 06:02:16 PM PDT 24
Peak memory 196560 kb
Host smart-ef6aed6d-f44e-49a0-be4e-532c9eaf7565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349513997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2349513997
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3551330916
Short name T136
Test name
Test status
Simulation time 599472865 ps
CPU time 0.83 seconds
Started Jul 25 06:02:43 PM PDT 24
Finished Jul 25 06:02:44 PM PDT 24
Peak memory 196568 kb
Host smart-cbda691b-09f9-4255-b136-da5b9a0dbcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551330916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3551330916
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2659065504
Short name T186
Test name
Test status
Simulation time 597087439 ps
CPU time 0.82 seconds
Started Jul 25 06:01:57 PM PDT 24
Finished Jul 25 06:01:58 PM PDT 24
Peak memory 196556 kb
Host smart-1f2dd77f-3467-4a34-a62b-a6789751acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659065504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2659065504
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.98957301
Short name T185
Test name
Test status
Simulation time 234579401713 ps
CPU time 341.98 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:07:40 PM PDT 24
Peak memory 184492 kb
Host smart-8cdffae7-11a0-4b27-af3d-94a7eec70c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98957301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all
.98957301
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3235517904
Short name T202
Test name
Test status
Simulation time 7996316805 ps
CPU time 4.16 seconds
Started Jul 25 06:03:15 PM PDT 24
Finished Jul 25 06:03:19 PM PDT 24
Peak memory 198808 kb
Host smart-e7aaf8c4-a288-48fb-b636-cabd821093dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235517904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3235517904
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/2.aon_timer_jump.946742726
Short name T31
Test name
Test status
Simulation time 382890480 ps
CPU time 0.72 seconds
Started Jul 25 06:01:49 PM PDT 24
Finished Jul 25 06:01:50 PM PDT 24
Peak memory 196596 kb
Host smart-00cfe14a-9f83-4007-83e0-7dd0f2fbff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946742726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.946742726
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1046599440
Short name T193
Test name
Test status
Simulation time 386050605 ps
CPU time 0.73 seconds
Started Jul 25 06:02:16 PM PDT 24
Finished Jul 25 06:02:17 PM PDT 24
Peak memory 196544 kb
Host smart-4f200fb1-9c79-4d6a-b2b6-bd2ed41bff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046599440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1046599440
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_jump.979099993
Short name T194
Test name
Test status
Simulation time 482529726 ps
CPU time 0.74 seconds
Started Jul 25 06:02:40 PM PDT 24
Finished Jul 25 06:02:41 PM PDT 24
Peak memory 196516 kb
Host smart-54af31be-4512-45e7-8dd5-1ece2d0255a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979099993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.979099993
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.727768308
Short name T189
Test name
Test status
Simulation time 245481962658 ps
CPU time 62.62 seconds
Started Jul 25 06:02:39 PM PDT 24
Finished Jul 25 06:03:42 PM PDT 24
Peak memory 198224 kb
Host smart-ec57b5ed-83f4-4566-8375-448044c9de6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727768308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.727768308
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1967818537
Short name T176
Test name
Test status
Simulation time 516413503 ps
CPU time 1.28 seconds
Started Jul 25 06:02:43 PM PDT 24
Finished Jul 25 06:02:45 PM PDT 24
Peak memory 196540 kb
Host smart-10168d9c-f99f-47e1-81ab-db7efb94b2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967818537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1967818537
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3907673226
Short name T163
Test name
Test status
Simulation time 203130296247 ps
CPU time 29.65 seconds
Started Jul 25 06:01:55 PM PDT 24
Finished Jul 25 06:02:24 PM PDT 24
Peak memory 192796 kb
Host smart-46215ba8-9a21-4cce-84c0-62dd5de3bfd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907673226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3907673226
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3463999447
Short name T181
Test name
Test status
Simulation time 158275949460 ps
CPU time 31.7 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:03:30 PM PDT 24
Peak memory 191812 kb
Host smart-1be87bf6-beb5-485f-a156-0aad7c09905e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463999447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3463999447
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1611655060
Short name T55
Test name
Test status
Simulation time 439899213 ps
CPU time 1.16 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 196568 kb
Host smart-737514fe-d385-448c-9c85-78038c891894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611655060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1611655060
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1562451580
Short name T164
Test name
Test status
Simulation time 222063401126 ps
CPU time 150.66 seconds
Started Jul 25 06:03:01 PM PDT 24
Finished Jul 25 06:05:32 PM PDT 24
Peak memory 191892 kb
Host smart-fb7064dd-cae3-49e0-acb5-02ba267ee1ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562451580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1562451580
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3100508546
Short name T200
Test name
Test status
Simulation time 8678356810 ps
CPU time 3.97 seconds
Started Jul 25 06:03:13 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 198548 kb
Host smart-184f2f3e-bf5b-4008-968b-b9cb89682eba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100508546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3100508546
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2290153161
Short name T110
Test name
Test status
Simulation time 383852157 ps
CPU time 0.72 seconds
Started Jul 25 06:01:57 PM PDT 24
Finished Jul 25 06:01:58 PM PDT 24
Peak memory 196648 kb
Host smart-86f1c58a-5ccd-4b1d-a3e1-b14e7d62db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290153161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2290153161
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_jump.927110867
Short name T191
Test name
Test status
Simulation time 503981371 ps
CPU time 0.62 seconds
Started Jul 25 06:02:08 PM PDT 24
Finished Jul 25 06:02:09 PM PDT 24
Peak memory 196668 kb
Host smart-fec3f69d-24fc-4351-8409-b16ff01ea234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927110867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.927110867
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3686725587
Short name T179
Test name
Test status
Simulation time 400886425 ps
CPU time 1.13 seconds
Started Jul 25 06:02:18 PM PDT 24
Finished Jul 25 06:02:19 PM PDT 24
Peak memory 196596 kb
Host smart-45368fec-fd83-46b4-b4f3-64cb3a012e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686725587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3686725587
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1822727005
Short name T129
Test name
Test status
Simulation time 189175768390 ps
CPU time 72.12 seconds
Started Jul 25 06:02:25 PM PDT 24
Finished Jul 25 06:03:37 PM PDT 24
Peak memory 198280 kb
Host smart-32af299e-91da-43ca-ad29-cdb22d09b9e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822727005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1822727005
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2029810068
Short name T190
Test name
Test status
Simulation time 564573340 ps
CPU time 1.03 seconds
Started Jul 25 06:02:28 PM PDT 24
Finished Jul 25 06:02:29 PM PDT 24
Peak memory 196644 kb
Host smart-901be8e1-0b22-40ab-9dd6-f6559b5a1ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029810068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2029810068
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1478711815
Short name T182
Test name
Test status
Simulation time 434338603 ps
CPU time 0.74 seconds
Started Jul 25 06:02:40 PM PDT 24
Finished Jul 25 06:02:40 PM PDT 24
Peak memory 196552 kb
Host smart-17b13dcf-6116-41a8-a54d-4623fc162320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478711815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1478711815
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2326417342
Short name T196
Test name
Test status
Simulation time 546322611 ps
CPU time 1.05 seconds
Started Jul 25 06:02:39 PM PDT 24
Finished Jul 25 06:02:41 PM PDT 24
Peak memory 196568 kb
Host smart-fe705ceb-05ce-4c45-913d-0af74084eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326417342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2326417342
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2638912501
Short name T195
Test name
Test status
Simulation time 607081339 ps
CPU time 0.65 seconds
Started Jul 25 06:02:42 PM PDT 24
Finished Jul 25 06:02:42 PM PDT 24
Peak memory 196640 kb
Host smart-dc959b18-a075-458d-b192-94068a0ded04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638912501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2638912501
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.998364136
Short name T65
Test name
Test status
Simulation time 431907970 ps
CPU time 1.3 seconds
Started Jul 25 06:02:56 PM PDT 24
Finished Jul 25 06:02:57 PM PDT 24
Peak memory 193752 kb
Host smart-b4b91324-ad5c-4cd9-beed-13122af0bc51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998364136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.998364136
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3996149502
Short name T308
Test name
Test status
Simulation time 14086075174 ps
CPU time 6.37 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:03:03 PM PDT 24
Peak memory 196984 kb
Host smart-619052d3-9b41-4426-93fb-9b6ccc4c4518
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996149502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3996149502
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2032100727
Short name T37
Test name
Test status
Simulation time 1054475277 ps
CPU time 0.92 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:58 PM PDT 24
Peak memory 184212 kb
Host smart-3119d88c-4ced-4781-853e-574099f2b797
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032100727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2032100727
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3321071130
Short name T409
Test name
Test status
Simulation time 436181686 ps
CPU time 0.9 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 198080 kb
Host smart-81e29dee-c928-4d90-972f-ef2278d2428e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321071130 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3321071130
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1640532419
Short name T64
Test name
Test status
Simulation time 345481141 ps
CPU time 0.68 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:58 PM PDT 24
Peak memory 193452 kb
Host smart-a9ef9a49-94c1-43b1-826e-475b04d1f0bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640532419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1640532419
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2288954611
Short name T402
Test name
Test status
Simulation time 345335794 ps
CPU time 1.1 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:58 PM PDT 24
Peak memory 184168 kb
Host smart-5c8e43a7-3a31-4c52-bb37-f7a010a4fed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288954611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2288954611
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.89061600
Short name T414
Test name
Test status
Simulation time 420947098 ps
CPU time 0.54 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:58 PM PDT 24
Peak memory 184144 kb
Host smart-0fb0f59e-dc37-4818-a10b-7eb18b46a9b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89061600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_mem_partial_access.89061600
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2005718241
Short name T355
Test name
Test status
Simulation time 299999125 ps
CPU time 0.73 seconds
Started Jul 25 06:02:59 PM PDT 24
Finished Jul 25 06:03:00 PM PDT 24
Peak memory 184144 kb
Host smart-b66c88eb-c1ad-4049-b99e-b2f622d285d1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005718241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2005718241
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1442363286
Short name T75
Test name
Test status
Simulation time 2913689873 ps
CPU time 1.97 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 192556 kb
Host smart-676b5ca6-4aa2-4171-ac6c-1df5122c7206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442363286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1442363286
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.372017686
Short name T298
Test name
Test status
Simulation time 615404473 ps
CPU time 2.5 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:03:00 PM PDT 24
Peak memory 199104 kb
Host smart-01fecfce-e92b-4bfc-a694-8ce2e7a7a38a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372017686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.372017686
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1184096592
Short name T70
Test name
Test status
Simulation time 648186683 ps
CPU time 1.22 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 184264 kb
Host smart-fb53dc97-e8b8-41b0-9d54-31282917880c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184096592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1184096592
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2727209462
Short name T61
Test name
Test status
Simulation time 10660940029 ps
CPU time 4.17 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:03:02 PM PDT 24
Peak memory 196128 kb
Host smart-c938a93a-13d7-419a-9c7c-eb5585e1caf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727209462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2727209462
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1138359051
Short name T371
Test name
Test status
Simulation time 596885458 ps
CPU time 1.45 seconds
Started Jul 25 06:03:06 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 193452 kb
Host smart-a53edaf6-1901-45b6-9fbf-51e979585b92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138359051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1138359051
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2942061080
Short name T307
Test name
Test status
Simulation time 613790013 ps
CPU time 0.95 seconds
Started Jul 25 06:02:59 PM PDT 24
Finished Jul 25 06:03:00 PM PDT 24
Peak memory 197320 kb
Host smart-5dc0a31c-3ed7-4905-9c87-428310435a3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942061080 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2942061080
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3428193585
Short name T73
Test name
Test status
Simulation time 350130571 ps
CPU time 0.74 seconds
Started Jul 25 06:03:06 PM PDT 24
Finished Jul 25 06:03:07 PM PDT 24
Peak memory 192512 kb
Host smart-c44ed3e5-aebf-48b3-ac4f-c38c13a17fc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428193585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3428193585
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2800706382
Short name T291
Test name
Test status
Simulation time 494610245 ps
CPU time 0.77 seconds
Started Jul 25 06:02:59 PM PDT 24
Finished Jul 25 06:03:00 PM PDT 24
Peak memory 184196 kb
Host smart-33854fed-eb6c-46fe-b875-076d9289e998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800706382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2800706382
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.912569876
Short name T292
Test name
Test status
Simulation time 300528186 ps
CPU time 0.6 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 184168 kb
Host smart-430957a6-4d99-4d3a-82ce-70d0ef6efa2c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912569876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.912569876
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3319656860
Short name T286
Test name
Test status
Simulation time 278908396 ps
CPU time 0.66 seconds
Started Jul 25 06:03:00 PM PDT 24
Finished Jul 25 06:03:01 PM PDT 24
Peak memory 184144 kb
Host smart-66dd3280-72f1-437a-8cea-16f450a8d319
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319656860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3319656860
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.701268388
Short name T362
Test name
Test status
Simulation time 2752303697 ps
CPU time 2.72 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:03:01 PM PDT 24
Peak memory 184556 kb
Host smart-404d691c-f2fb-49c5-891f-6b857ef0e48d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701268388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.701268388
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2348156471
Short name T406
Test name
Test status
Simulation time 594875111 ps
CPU time 1.38 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:03:00 PM PDT 24
Peak memory 199036 kb
Host smart-67e9e0a3-a7fd-4ced-9759-0b9f34aa4ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348156471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2348156471
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3194549159
Short name T197
Test name
Test status
Simulation time 8631556908 ps
CPU time 14.13 seconds
Started Jul 25 06:02:59 PM PDT 24
Finished Jul 25 06:03:13 PM PDT 24
Peak memory 198792 kb
Host smart-90800f5b-f67f-4559-b0ec-45118982ea53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194549159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3194549159
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.570462135
Short name T309
Test name
Test status
Simulation time 491140824 ps
CPU time 1.08 seconds
Started Jul 25 06:03:13 PM PDT 24
Finished Jul 25 06:03:14 PM PDT 24
Peak memory 196600 kb
Host smart-9064dbe5-cfb2-4bac-b13b-51ef7308984a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570462135 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.570462135
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4294687619
Short name T400
Test name
Test status
Simulation time 439378464 ps
CPU time 1.37 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 194472 kb
Host smart-aa42cf68-34c2-4703-ad41-0a0de9155631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294687619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4294687619
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3954186045
Short name T379
Test name
Test status
Simulation time 326903170 ps
CPU time 0.65 seconds
Started Jul 25 06:03:13 PM PDT 24
Finished Jul 25 06:03:14 PM PDT 24
Peak memory 184224 kb
Host smart-b69ed485-fdb4-4274-9830-32f723ed37bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954186045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3954186045
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3617079392
Short name T380
Test name
Test status
Simulation time 1347976517 ps
CPU time 1.28 seconds
Started Jul 25 06:03:10 PM PDT 24
Finished Jul 25 06:03:11 PM PDT 24
Peak memory 193484 kb
Host smart-9f8960dc-68e2-483d-89b9-5a8fda54b5f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617079392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3617079392
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2910374284
Short name T336
Test name
Test status
Simulation time 510690985 ps
CPU time 1.74 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 199032 kb
Host smart-26297438-5075-47e0-94b0-0ab24a594510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910374284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2910374284
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4203008174
Short name T410
Test name
Test status
Simulation time 306023731 ps
CPU time 0.93 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:15 PM PDT 24
Peak memory 196344 kb
Host smart-3745f20b-7a20-4a75-86c7-5629eeffcb70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203008174 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4203008174
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3120868789
Short name T339
Test name
Test status
Simulation time 435981020 ps
CPU time 0.86 seconds
Started Jul 25 06:03:21 PM PDT 24
Finished Jul 25 06:03:22 PM PDT 24
Peak memory 193448 kb
Host smart-5b8dd4b1-afb2-4297-a5d7-591ed81fbfaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120868789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3120868789
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3961641088
Short name T304
Test name
Test status
Simulation time 302787073 ps
CPU time 0.79 seconds
Started Jul 25 06:03:15 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 184232 kb
Host smart-47018652-45ac-4573-9c92-2d060fbe0d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961641088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3961641088
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2768619007
Short name T383
Test name
Test status
Simulation time 1056323179 ps
CPU time 0.94 seconds
Started Jul 25 06:03:17 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 192440 kb
Host smart-bd63eb52-8cfe-4a66-bedf-9b23c7fab971
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768619007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2768619007
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2988219941
Short name T412
Test name
Test status
Simulation time 446135843 ps
CPU time 1.69 seconds
Started Jul 25 06:03:16 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 198836 kb
Host smart-17ce7985-422c-47c0-b2f1-9c6d1d315238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988219941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2988219941
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3679771656
Short name T338
Test name
Test status
Simulation time 406795570 ps
CPU time 1.24 seconds
Started Jul 25 06:03:18 PM PDT 24
Finished Jul 25 06:03:19 PM PDT 24
Peak memory 197792 kb
Host smart-3d1d766d-0f77-4875-b5ef-5f5ea19ba407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679771656 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3679771656
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1126238994
Short name T46
Test name
Test status
Simulation time 582657877 ps
CPU time 0.61 seconds
Started Jul 25 06:03:15 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 192728 kb
Host smart-8a017cc4-040c-4292-9260-67dd6ba899ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126238994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1126238994
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2851689651
Short name T343
Test name
Test status
Simulation time 295484185 ps
CPU time 0.65 seconds
Started Jul 25 06:03:16 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 193444 kb
Host smart-31b08b9e-d4db-4f1b-af3d-2249ec40d356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851689651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2851689651
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.4273467979
Short name T356
Test name
Test status
Simulation time 2238062098 ps
CPU time 1.35 seconds
Started Jul 25 06:03:17 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 194328 kb
Host smart-aa71e32b-8fce-4f88-9955-5a7207a5f2be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273467979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.4273467979
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3269288233
Short name T392
Test name
Test status
Simulation time 502985664 ps
CPU time 1.92 seconds
Started Jul 25 06:03:19 PM PDT 24
Finished Jul 25 06:03:21 PM PDT 24
Peak memory 199028 kb
Host smart-083f7f69-9896-458c-a573-d452bbe17883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269288233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3269288233
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.556743339
Short name T391
Test name
Test status
Simulation time 4227926558 ps
CPU time 2.48 seconds
Started Jul 25 06:03:19 PM PDT 24
Finished Jul 25 06:03:21 PM PDT 24
Peak memory 198344 kb
Host smart-01107a6d-b0a1-42a9-b3db-f97d78e2d24d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556743339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.556743339
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.544496469
Short name T305
Test name
Test status
Simulation time 397880781 ps
CPU time 1 seconds
Started Jul 25 06:03:21 PM PDT 24
Finished Jul 25 06:03:22 PM PDT 24
Peak memory 196564 kb
Host smart-a7fd8531-754d-4d40-a688-cc0af1d9c144
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544496469 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.544496469
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1640774168
Short name T413
Test name
Test status
Simulation time 383992842 ps
CPU time 0.88 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:15 PM PDT 24
Peak memory 193776 kb
Host smart-50fdd322-a8df-47df-875f-6c5aa42f7b12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640774168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1640774168
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2030749510
Short name T290
Test name
Test status
Simulation time 517958788 ps
CPU time 0.87 seconds
Started Jul 25 06:03:16 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 184272 kb
Host smart-995524ab-cd53-4d0d-a43c-591ab69be346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030749510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2030749510
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.199442333
Short name T398
Test name
Test status
Simulation time 2696144002 ps
CPU time 2.31 seconds
Started Jul 25 06:03:15 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 192500 kb
Host smart-17a1b853-84c4-4441-a9eb-2edd8546b5e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199442333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.199442333
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3755927756
Short name T359
Test name
Test status
Simulation time 378464671 ps
CPU time 1.63 seconds
Started Jul 25 06:03:16 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 199096 kb
Host smart-6790f1c2-1678-4988-9009-5e44c75ba01a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755927756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3755927756
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4029416339
Short name T394
Test name
Test status
Simulation time 9053832999 ps
CPU time 3.9 seconds
Started Jul 25 06:03:17 PM PDT 24
Finished Jul 25 06:03:21 PM PDT 24
Peak memory 198852 kb
Host smart-016d4d7e-53f6-43d2-9e8b-9100a6754730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029416339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.4029416339
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1237627592
Short name T350
Test name
Test status
Simulation time 420743384 ps
CPU time 0.76 seconds
Started Jul 25 06:03:17 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 195656 kb
Host smart-3f82fb1d-092d-4060-9334-2e2bfec7a51a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237627592 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1237627592
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2483775019
Short name T205
Test name
Test status
Simulation time 427084472 ps
CPU time 0.89 seconds
Started Jul 25 06:03:16 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 193436 kb
Host smart-8bc9b44d-9593-434c-ba40-5e91109127e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483775019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2483775019
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1013997819
Short name T401
Test name
Test status
Simulation time 476974600 ps
CPU time 1.21 seconds
Started Jul 25 06:03:16 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 184216 kb
Host smart-8a4228e0-4132-4875-b1e3-565a7e1f9a41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013997819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1013997819
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2223189774
Short name T325
Test name
Test status
Simulation time 2937551805 ps
CPU time 6.87 seconds
Started Jul 25 06:03:18 PM PDT 24
Finished Jul 25 06:03:25 PM PDT 24
Peak memory 195000 kb
Host smart-e5248182-4dbd-4479-aded-73758eddab9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223189774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2223189774
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1367786691
Short name T405
Test name
Test status
Simulation time 958903048 ps
CPU time 1.8 seconds
Started Jul 25 06:03:15 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 199116 kb
Host smart-da161c70-84fb-4e2e-9cb4-2f4b6e886662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367786691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1367786691
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2397140111
Short name T347
Test name
Test status
Simulation time 8053081491 ps
CPU time 12.32 seconds
Started Jul 25 06:03:16 PM PDT 24
Finished Jul 25 06:03:29 PM PDT 24
Peak memory 198772 kb
Host smart-2efc0365-6b3b-4f48-993e-27b5c23e2130
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397140111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2397140111
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3445008244
Short name T333
Test name
Test status
Simulation time 519759765 ps
CPU time 1.04 seconds
Started Jul 25 06:03:27 PM PDT 24
Finished Jul 25 06:03:28 PM PDT 24
Peak memory 196480 kb
Host smart-ef4aa774-1a2c-43f6-b3d8-b5f67d4a9df8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445008244 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3445008244
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.101625337
Short name T297
Test name
Test status
Simulation time 383795972 ps
CPU time 1.19 seconds
Started Jul 25 06:03:25 PM PDT 24
Finished Jul 25 06:03:26 PM PDT 24
Peak memory 193848 kb
Host smart-bdb0d671-840e-400c-851c-2e4d9f11dfda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101625337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.101625337
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1747443485
Short name T294
Test name
Test status
Simulation time 377375876 ps
CPU time 0.65 seconds
Started Jul 25 06:03:25 PM PDT 24
Finished Jul 25 06:03:26 PM PDT 24
Peak memory 184300 kb
Host smart-19be1e43-3c33-4293-8e84-7174b51f667d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747443485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1747443485
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.350963429
Short name T327
Test name
Test status
Simulation time 2623693079 ps
CPU time 1.53 seconds
Started Jul 25 06:03:24 PM PDT 24
Finished Jul 25 06:03:26 PM PDT 24
Peak memory 195560 kb
Host smart-1f0cc768-5f48-4482-86e3-3ab1240cae60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350963429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.350963429
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1055384258
Short name T319
Test name
Test status
Simulation time 436938257 ps
CPU time 2.97 seconds
Started Jul 25 06:03:26 PM PDT 24
Finished Jul 25 06:03:30 PM PDT 24
Peak memory 199068 kb
Host smart-2fa52704-763a-4a65-9247-f84aab34e288
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055384258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1055384258
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2126921870
Short name T376
Test name
Test status
Simulation time 4373279032 ps
CPU time 6.9 seconds
Started Jul 25 06:03:25 PM PDT 24
Finished Jul 25 06:03:32 PM PDT 24
Peak memory 198488 kb
Host smart-cbcc9840-503f-41b1-99e2-fe8b9914b795
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126921870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2126921870
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4149935080
Short name T321
Test name
Test status
Simulation time 409157173 ps
CPU time 1.23 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:36 PM PDT 24
Peak memory 196684 kb
Host smart-adff4445-bd1e-45c5-bc6f-a19a9e110a82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149935080 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4149935080
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1662979545
Short name T314
Test name
Test status
Simulation time 326549882 ps
CPU time 1.1 seconds
Started Jul 25 06:03:26 PM PDT 24
Finished Jul 25 06:03:27 PM PDT 24
Peak memory 193416 kb
Host smart-5c8c4325-603c-437d-b1f9-1ad57f83579f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662979545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1662979545
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3074675389
Short name T299
Test name
Test status
Simulation time 370215928 ps
CPU time 0.78 seconds
Started Jul 25 06:03:24 PM PDT 24
Finished Jul 25 06:03:25 PM PDT 24
Peak memory 184232 kb
Host smart-f4389974-6378-44d6-8b4d-19f93f000e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074675389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3074675389
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1919728956
Short name T363
Test name
Test status
Simulation time 1011980376 ps
CPU time 0.89 seconds
Started Jul 25 06:03:30 PM PDT 24
Finished Jul 25 06:03:31 PM PDT 24
Peak memory 194276 kb
Host smart-cfa77655-2f5e-4c2f-a61e-d5dc5061aae4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919728956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1919728956
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.161094853
Short name T295
Test name
Test status
Simulation time 551746594 ps
CPU time 2.21 seconds
Started Jul 25 06:03:27 PM PDT 24
Finished Jul 25 06:03:29 PM PDT 24
Peak memory 199080 kb
Host smart-9a92c62e-3abb-4ff6-9bda-42631e4953d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161094853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.161094853
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1738035236
Short name T199
Test name
Test status
Simulation time 8294931174 ps
CPU time 4.12 seconds
Started Jul 25 06:03:29 PM PDT 24
Finished Jul 25 06:03:34 PM PDT 24
Peak memory 198884 kb
Host smart-cf6d8d0f-a881-492e-9a3f-b4569ecfa54c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738035236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1738035236
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2493916141
Short name T204
Test name
Test status
Simulation time 330827689 ps
CPU time 0.83 seconds
Started Jul 25 06:03:25 PM PDT 24
Finished Jul 25 06:03:26 PM PDT 24
Peak memory 196688 kb
Host smart-f790a09c-fe98-406b-bab4-11b6cedcd494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493916141 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2493916141
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.769030261
Short name T353
Test name
Test status
Simulation time 413355002 ps
CPU time 0.7 seconds
Started Jul 25 06:03:29 PM PDT 24
Finished Jul 25 06:03:30 PM PDT 24
Peak memory 193392 kb
Host smart-b45d4be5-7618-4bdd-8218-310bcbcb6ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769030261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.769030261
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4135825621
Short name T420
Test name
Test status
Simulation time 545501694 ps
CPU time 0.74 seconds
Started Jul 25 06:03:28 PM PDT 24
Finished Jul 25 06:03:29 PM PDT 24
Peak memory 184200 kb
Host smart-e9daab53-ede4-4ffa-8f4a-6b56e34ec08a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135825621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.4135825621
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4222652331
Short name T80
Test name
Test status
Simulation time 1104084787 ps
CPU time 2.2 seconds
Started Jul 25 06:03:26 PM PDT 24
Finished Jul 25 06:03:28 PM PDT 24
Peak memory 194460 kb
Host smart-779bd8e5-1936-4057-8ba1-e94ad95abe7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222652331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.4222652331
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2621756271
Short name T399
Test name
Test status
Simulation time 874858498 ps
CPU time 2.06 seconds
Started Jul 25 06:03:24 PM PDT 24
Finished Jul 25 06:03:26 PM PDT 24
Peak memory 199100 kb
Host smart-e14ba8d9-373c-413d-9456-09ef4393b424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621756271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2621756271
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1750056288
Short name T403
Test name
Test status
Simulation time 8204418602 ps
CPU time 12.39 seconds
Started Jul 25 06:03:25 PM PDT 24
Finished Jul 25 06:03:37 PM PDT 24
Peak memory 198788 kb
Host smart-502e82ef-1608-4320-af33-bc9fe6b5e0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750056288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1750056288
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2167979739
Short name T312
Test name
Test status
Simulation time 518264631 ps
CPU time 1.42 seconds
Started Jul 25 06:03:33 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 196592 kb
Host smart-8d6f2b49-07ee-48e5-b9ef-6172cc93e6bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167979739 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2167979739
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3459254223
Short name T354
Test name
Test status
Simulation time 495296553 ps
CPU time 0.79 seconds
Started Jul 25 06:03:29 PM PDT 24
Finished Jul 25 06:03:30 PM PDT 24
Peak memory 193416 kb
Host smart-7a8a0706-d20e-476e-a2df-cb5996844f2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459254223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3459254223
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2940481467
Short name T348
Test name
Test status
Simulation time 546756544 ps
CPU time 0.64 seconds
Started Jul 25 06:03:29 PM PDT 24
Finished Jul 25 06:03:30 PM PDT 24
Peak memory 184200 kb
Host smart-5de94fb4-e795-43a8-a3c9-1d8f182f4b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940481467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2940481467
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2059117305
Short name T408
Test name
Test status
Simulation time 1105641182 ps
CPU time 1.1 seconds
Started Jul 25 06:03:27 PM PDT 24
Finished Jul 25 06:03:28 PM PDT 24
Peak memory 192508 kb
Host smart-a296d2c8-5af0-4446-91bd-1fd36f86140a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059117305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2059117305
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2793196412
Short name T287
Test name
Test status
Simulation time 571324806 ps
CPU time 1.44 seconds
Started Jul 25 06:03:27 PM PDT 24
Finished Jul 25 06:03:28 PM PDT 24
Peak memory 198844 kb
Host smart-bd4632f4-8cc8-451f-8849-aeb33500deff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793196412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2793196412
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.306892366
Short name T198
Test name
Test status
Simulation time 8562471682 ps
CPU time 4.35 seconds
Started Jul 25 06:03:26 PM PDT 24
Finished Jul 25 06:03:31 PM PDT 24
Peak memory 198676 kb
Host smart-9153dcfe-0cbc-4438-bddb-b77411c768c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306892366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.306892366
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3786968885
Short name T386
Test name
Test status
Simulation time 449156581 ps
CPU time 0.9 seconds
Started Jul 25 06:03:29 PM PDT 24
Finished Jul 25 06:03:30 PM PDT 24
Peak memory 198212 kb
Host smart-42f7ef63-006a-46a8-9694-b6836fb4354f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786968885 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3786968885
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1542642264
Short name T76
Test name
Test status
Simulation time 417073096 ps
CPU time 0.65 seconds
Started Jul 25 06:03:33 PM PDT 24
Finished Jul 25 06:03:34 PM PDT 24
Peak memory 193760 kb
Host smart-72b215c2-66e6-4540-a8cb-185ba92ece54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542642264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1542642264
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.720996969
Short name T418
Test name
Test status
Simulation time 355723774 ps
CPU time 0.66 seconds
Started Jul 25 06:03:33 PM PDT 24
Finished Jul 25 06:03:34 PM PDT 24
Peak memory 184264 kb
Host smart-94c4c7b0-bbbd-4b88-b63c-368c3164d093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720996969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.720996969
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1129507120
Short name T329
Test name
Test status
Simulation time 2090683492 ps
CPU time 1.97 seconds
Started Jul 25 06:03:29 PM PDT 24
Finished Jul 25 06:03:31 PM PDT 24
Peak memory 194412 kb
Host smart-f3a979ba-e3e4-48e3-9293-879f92e93c36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129507120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1129507120
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.438198419
Short name T331
Test name
Test status
Simulation time 760911752 ps
CPU time 2.53 seconds
Started Jul 25 06:03:27 PM PDT 24
Finished Jul 25 06:03:30 PM PDT 24
Peak memory 199104 kb
Host smart-26c2cdf1-0613-4725-add3-493e317c1651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438198419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.438198419
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.296380264
Short name T201
Test name
Test status
Simulation time 4635685115 ps
CPU time 1.41 seconds
Started Jul 25 06:03:29 PM PDT 24
Finished Jul 25 06:03:30 PM PDT 24
Peak memory 197212 kb
Host smart-92269933-428e-4519-966c-ba03a69efc47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296380264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.296380264
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.677977594
Short name T67
Test name
Test status
Simulation time 556608257 ps
CPU time 1.62 seconds
Started Jul 25 06:03:07 PM PDT 24
Finished Jul 25 06:03:09 PM PDT 24
Peak memory 194864 kb
Host smart-b7eeb00b-70ef-430e-9b36-f5731d8be2bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677977594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.677977594
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1649807653
Short name T396
Test name
Test status
Simulation time 7408268690 ps
CPU time 16.6 seconds
Started Jul 25 06:03:10 PM PDT 24
Finished Jul 25 06:03:27 PM PDT 24
Peak memory 196320 kb
Host smart-b67d1321-07ee-4f9a-b2a1-c315f448bf24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649807653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1649807653
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.793797604
Short name T68
Test name
Test status
Simulation time 1337697051 ps
CPU time 1.09 seconds
Started Jul 25 06:03:05 PM PDT 24
Finished Jul 25 06:03:06 PM PDT 24
Peak memory 193472 kb
Host smart-60edefb8-a106-4da2-adcb-11b413672fe6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793797604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.793797604
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.566277218
Short name T326
Test name
Test status
Simulation time 546440558 ps
CPU time 1.11 seconds
Started Jul 25 06:03:09 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 196796 kb
Host smart-364ebaa6-f046-4f14-bb7f-ccf2db697e90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566277218 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.566277218
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.56796385
Short name T313
Test name
Test status
Simulation time 412134573 ps
CPU time 0.67 seconds
Started Jul 25 06:03:06 PM PDT 24
Finished Jul 25 06:03:06 PM PDT 24
Peak memory 193452 kb
Host smart-77b5df6b-de5d-4878-935c-97d5df7ea28a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56796385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.56796385
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.919365024
Short name T389
Test name
Test status
Simulation time 456408949 ps
CPU time 0.68 seconds
Started Jul 25 06:03:07 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 193392 kb
Host smart-9711fb28-ac89-41b5-8d1f-272d5bc365c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919365024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.919365024
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.474303640
Short name T337
Test name
Test status
Simulation time 418689733 ps
CPU time 0.82 seconds
Started Jul 25 06:03:06 PM PDT 24
Finished Jul 25 06:03:07 PM PDT 24
Peak memory 184160 kb
Host smart-fa80de89-03fb-479a-8659-afcede7ec15c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474303640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.474303640
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2686423455
Short name T416
Test name
Test status
Simulation time 378864505 ps
CPU time 0.61 seconds
Started Jul 25 06:03:07 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 184084 kb
Host smart-59c41256-b373-49be-a139-2d4539dd5a80
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686423455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2686423455
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3413634305
Short name T344
Test name
Test status
Simulation time 2535157843 ps
CPU time 1.9 seconds
Started Jul 25 06:03:13 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 194796 kb
Host smart-f08cbf14-2a16-4d2a-b488-2b59fa77c9cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413634305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3413634305
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2843869507
Short name T340
Test name
Test status
Simulation time 422242941 ps
CPU time 2.23 seconds
Started Jul 25 06:03:08 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 199064 kb
Host smart-80a0503c-19fc-4d18-b683-c0b4292ca2ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843869507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2843869507
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.411009830
Short name T330
Test name
Test status
Simulation time 4622578750 ps
CPU time 4.34 seconds
Started Jul 25 06:03:06 PM PDT 24
Finished Jul 25 06:03:11 PM PDT 24
Peak memory 198196 kb
Host smart-394bdc7d-9826-4380-ab99-31b5196fdf6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411009830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.411009830
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2791275096
Short name T366
Test name
Test status
Simulation time 527384848 ps
CPU time 0.83 seconds
Started Jul 25 06:03:27 PM PDT 24
Finished Jul 25 06:03:28 PM PDT 24
Peak memory 184252 kb
Host smart-dbf9f279-1783-4356-b2b2-87121e1fcb92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791275096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2791275096
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3350147031
Short name T283
Test name
Test status
Simulation time 415361000 ps
CPU time 0.72 seconds
Started Jul 25 06:03:32 PM PDT 24
Finished Jul 25 06:03:33 PM PDT 24
Peak memory 184256 kb
Host smart-782cab6e-2a2c-4bbf-96d5-876b65ad7f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350147031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3350147031
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.232064051
Short name T361
Test name
Test status
Simulation time 422232034 ps
CPU time 0.66 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184236 kb
Host smart-ab15d790-45e4-46aa-b38d-0559e9f52992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232064051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.232064051
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3700134721
Short name T357
Test name
Test status
Simulation time 385724186 ps
CPU time 1.08 seconds
Started Jul 25 06:03:32 PM PDT 24
Finished Jul 25 06:03:33 PM PDT 24
Peak memory 184224 kb
Host smart-5ebcbdf5-b768-47f2-a406-0834f8262139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700134721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3700134721
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.600980769
Short name T296
Test name
Test status
Simulation time 483996937 ps
CPU time 1.2 seconds
Started Jul 25 06:03:35 PM PDT 24
Finished Jul 25 06:03:36 PM PDT 24
Peak memory 184296 kb
Host smart-edbdec4e-beb8-40c4-8727-64a73970c3ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600980769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.600980769
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4277422144
Short name T342
Test name
Test status
Simulation time 450101616 ps
CPU time 0.73 seconds
Started Jul 25 06:03:32 PM PDT 24
Finished Jul 25 06:03:33 PM PDT 24
Peak memory 184208 kb
Host smart-b066c9a2-fa93-411a-b220-4cc432f44db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277422144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4277422144
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1229220526
Short name T373
Test name
Test status
Simulation time 464952944 ps
CPU time 0.7 seconds
Started Jul 25 06:03:35 PM PDT 24
Finished Jul 25 06:03:36 PM PDT 24
Peak memory 184248 kb
Host smart-01803048-906f-4a36-91ef-803d60ee1ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229220526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1229220526
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1805674258
Short name T288
Test name
Test status
Simulation time 383120737 ps
CPU time 0.68 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 193456 kb
Host smart-8a7383a3-4f2a-4eb2-9161-d4e4c4934536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805674258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1805674258
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1426892927
Short name T368
Test name
Test status
Simulation time 287037020 ps
CPU time 0.78 seconds
Started Jul 25 06:03:31 PM PDT 24
Finished Jul 25 06:03:32 PM PDT 24
Peak memory 184236 kb
Host smart-e489c4b6-6524-4374-ae0b-9c7105e2c820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426892927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1426892927
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1937537177
Short name T411
Test name
Test status
Simulation time 347527926 ps
CPU time 0.77 seconds
Started Jul 25 06:03:32 PM PDT 24
Finished Jul 25 06:03:33 PM PDT 24
Peak memory 184228 kb
Host smart-b06e61bf-1fa5-4969-868d-ed2150c1cc91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937537177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1937537177
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.384377046
Short name T341
Test name
Test status
Simulation time 564986438 ps
CPU time 1.2 seconds
Started Jul 25 06:03:06 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 184344 kb
Host smart-f45878b8-e19b-4e7b-8222-774586bac322
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384377046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.384377046
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3736015615
Short name T206
Test name
Test status
Simulation time 7061743358 ps
CPU time 16.44 seconds
Started Jul 25 06:03:19 PM PDT 24
Finished Jul 25 06:03:36 PM PDT 24
Peak memory 196380 kb
Host smart-2e874767-0fa1-4197-839a-36e6b1dbd305
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736015615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3736015615
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2889281039
Short name T63
Test name
Test status
Simulation time 773496572 ps
CPU time 1.26 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:15 PM PDT 24
Peak memory 184236 kb
Host smart-4dd483ed-d461-47f8-8536-4e6ed85c97d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889281039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2889281039
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.362681151
Short name T378
Test name
Test status
Simulation time 411405814 ps
CPU time 0.99 seconds
Started Jul 25 06:03:13 PM PDT 24
Finished Jul 25 06:03:14 PM PDT 24
Peak memory 198884 kb
Host smart-e4c3afb5-723d-4b2a-afe3-d57ed547b0cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362681151 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.362681151
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.230272935
Short name T69
Test name
Test status
Simulation time 507656737 ps
CPU time 1.2 seconds
Started Jul 25 06:03:11 PM PDT 24
Finished Jul 25 06:03:12 PM PDT 24
Peak memory 192480 kb
Host smart-5a349f82-05cb-4b97-908d-5f8d9aec5bf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230272935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.230272935
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.2375798257
Short name T351
Test name
Test status
Simulation time 306101690 ps
CPU time 0.64 seconds
Started Jul 25 06:03:08 PM PDT 24
Finished Jul 25 06:03:09 PM PDT 24
Peak memory 184268 kb
Host smart-79319ba7-4f2d-4513-8365-c180aee81657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375798257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.2375798257
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1481481111
Short name T419
Test name
Test status
Simulation time 457766928 ps
CPU time 1.14 seconds
Started Jul 25 06:03:08 PM PDT 24
Finished Jul 25 06:03:09 PM PDT 24
Peak memory 184092 kb
Host smart-1c5d41c9-c319-4f08-a210-3b569ecd5df5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481481111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1481481111
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2148012640
Short name T397
Test name
Test status
Simulation time 384391337 ps
CPU time 0.63 seconds
Started Jul 25 06:03:08 PM PDT 24
Finished Jul 25 06:03:09 PM PDT 24
Peak memory 184136 kb
Host smart-52f64e45-e6a0-4d09-a23f-562f493d0784
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148012640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2148012640
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1435890708
Short name T320
Test name
Test status
Simulation time 2314743687 ps
CPU time 2.17 seconds
Started Jul 25 06:03:08 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 194540 kb
Host smart-2930b5d7-0470-4f14-95f4-90a8f5c76bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435890708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1435890708
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1461443216
Short name T388
Test name
Test status
Simulation time 561041043 ps
CPU time 1.32 seconds
Started Jul 25 06:03:06 PM PDT 24
Finished Jul 25 06:03:07 PM PDT 24
Peak memory 198836 kb
Host smart-3ff89298-4418-45ad-9ac3-446052566484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461443216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1461443216
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1660738436
Short name T328
Test name
Test status
Simulation time 4207420760 ps
CPU time 3.63 seconds
Started Jul 25 06:03:12 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 198372 kb
Host smart-4182842e-4ff3-4076-8064-d40e150a4282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660738436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1660738436
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.313486409
Short name T381
Test name
Test status
Simulation time 382036929 ps
CPU time 0.92 seconds
Started Jul 25 06:03:33 PM PDT 24
Finished Jul 25 06:03:34 PM PDT 24
Peak memory 193456 kb
Host smart-4d39ab6b-46b5-40cc-bc77-c025cadf9753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313486409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.313486409
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1831778049
Short name T324
Test name
Test status
Simulation time 424291445 ps
CPU time 0.6 seconds
Started Jul 25 06:03:35 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184300 kb
Host smart-b8ba5f17-3e13-4611-8f8b-e58ea2ea53f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831778049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1831778049
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3881289080
Short name T360
Test name
Test status
Simulation time 373564193 ps
CPU time 0.6 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184196 kb
Host smart-b35769ba-c5d5-4b8b-a02d-4bf4ccf41011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881289080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3881289080
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2849357509
Short name T349
Test name
Test status
Simulation time 463438184 ps
CPU time 1.2 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184200 kb
Host smart-4b471183-d619-4db2-9e66-b47c6e2e8d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849357509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2849357509
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1197181905
Short name T302
Test name
Test status
Simulation time 424604915 ps
CPU time 0.84 seconds
Started Jul 25 06:03:32 PM PDT 24
Finished Jul 25 06:03:34 PM PDT 24
Peak memory 184196 kb
Host smart-5eb4a01b-fbf9-44e5-98a8-e7bd6b22875f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197181905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1197181905
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2516674690
Short name T311
Test name
Test status
Simulation time 328520544 ps
CPU time 0.61 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184236 kb
Host smart-300c2927-f2f0-407b-922b-0cf5b52f5642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516674690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2516674690
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.916126609
Short name T289
Test name
Test status
Simulation time 415630050 ps
CPU time 1.21 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184164 kb
Host smart-2122bef9-fadc-40d2-ba71-29973801ad66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916126609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.916126609
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.423587195
Short name T293
Test name
Test status
Simulation time 300292743 ps
CPU time 0.73 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184212 kb
Host smart-aa2f787b-aa7a-43e9-8bf7-97d708108001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423587195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.423587195
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3001369799
Short name T384
Test name
Test status
Simulation time 461608167 ps
CPU time 0.94 seconds
Started Jul 25 06:03:32 PM PDT 24
Finished Jul 25 06:03:33 PM PDT 24
Peak memory 184280 kb
Host smart-a4ba6818-3f06-4a37-baca-315885209b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001369799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3001369799
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2556055943
Short name T382
Test name
Test status
Simulation time 340298212 ps
CPU time 0.72 seconds
Started Jul 25 06:03:32 PM PDT 24
Finished Jul 25 06:03:33 PM PDT 24
Peak memory 184188 kb
Host smart-c6dd1e71-a329-4901-b187-ef28040077bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556055943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2556055943
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2357100860
Short name T72
Test name
Test status
Simulation time 577320381 ps
CPU time 0.77 seconds
Started Jul 25 06:03:11 PM PDT 24
Finished Jul 25 06:03:12 PM PDT 24
Peak memory 184408 kb
Host smart-f762f301-d55d-4878-b254-0a4bc974fc6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357100860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2357100860
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3173200907
Short name T66
Test name
Test status
Simulation time 5736030318 ps
CPU time 2.52 seconds
Started Jul 25 06:03:17 PM PDT 24
Finished Jul 25 06:03:19 PM PDT 24
Peak memory 196812 kb
Host smart-7045630c-3b51-4b9e-8efa-4115f8dd473e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173200907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3173200907
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2503603799
Short name T71
Test name
Test status
Simulation time 1192468006 ps
CPU time 1.57 seconds
Started Jul 25 06:03:20 PM PDT 24
Finished Jul 25 06:03:22 PM PDT 24
Peak memory 193616 kb
Host smart-23dbb587-b039-4b44-a9b0-d3d46dd28631
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503603799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2503603799
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.975415195
Short name T316
Test name
Test status
Simulation time 403177196 ps
CPU time 1.2 seconds
Started Jul 25 06:03:06 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 196596 kb
Host smart-802acc0a-47ca-4b62-a551-6948bcda651b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975415195 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.975415195
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.4127567859
Short name T332
Test name
Test status
Simulation time 446052511 ps
CPU time 0.92 seconds
Started Jul 25 06:03:07 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 194476 kb
Host smart-5534aa55-4e33-4e81-b71e-802850444113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127567859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.4127567859
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3425324511
Short name T417
Test name
Test status
Simulation time 340929148 ps
CPU time 0.6 seconds
Started Jul 25 06:03:10 PM PDT 24
Finished Jul 25 06:03:11 PM PDT 24
Peak memory 184216 kb
Host smart-e2b7d8d7-8398-40d7-b430-5a2fa1505f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425324511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3425324511
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3656149471
Short name T334
Test name
Test status
Simulation time 372656312 ps
CPU time 0.77 seconds
Started Jul 25 06:03:08 PM PDT 24
Finished Jul 25 06:03:09 PM PDT 24
Peak memory 184140 kb
Host smart-71180322-6f06-40e2-85af-e6ef88253d76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656149471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3656149471
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.960602231
Short name T374
Test name
Test status
Simulation time 324466993 ps
CPU time 0.73 seconds
Started Jul 25 06:03:06 PM PDT 24
Finished Jul 25 06:03:07 PM PDT 24
Peak memory 184108 kb
Host smart-87826796-3be6-439a-b152-214031796e6d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960602231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.960602231
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3176772341
Short name T77
Test name
Test status
Simulation time 1586925803 ps
CPU time 2.58 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 194384 kb
Host smart-3695c545-2f11-40c6-b911-271303b1fcf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176772341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3176772341
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.389617426
Short name T285
Test name
Test status
Simulation time 334042312 ps
CPU time 1.69 seconds
Started Jul 25 06:03:09 PM PDT 24
Finished Jul 25 06:03:11 PM PDT 24
Peak memory 199072 kb
Host smart-92b2e4e1-c8e9-468a-9543-e8bb96f8d45c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389617426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.389617426
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1149974411
Short name T44
Test name
Test status
Simulation time 4695533948 ps
CPU time 4.51 seconds
Started Jul 25 06:03:12 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 198108 kb
Host smart-01c5484a-4b07-4481-82ef-f964376b0b42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149974411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1149974411
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1297276592
Short name T284
Test name
Test status
Simulation time 315652557 ps
CPU time 0.96 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184200 kb
Host smart-206e3e84-48b6-4ece-a933-6be910c3255e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297276592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1297276592
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.948784724
Short name T306
Test name
Test status
Simulation time 508417059 ps
CPU time 0.71 seconds
Started Jul 25 06:03:31 PM PDT 24
Finished Jul 25 06:03:31 PM PDT 24
Peak memory 193384 kb
Host smart-5fc2309e-4ff4-4da8-93da-2d2703e4ef96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948784724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.948784724
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1404543197
Short name T345
Test name
Test status
Simulation time 314696759 ps
CPU time 0.76 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184212 kb
Host smart-c39ed31c-1d9a-4d5c-b41f-55bc68e0172f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404543197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1404543197
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3290421211
Short name T346
Test name
Test status
Simulation time 473841815 ps
CPU time 0.87 seconds
Started Jul 25 06:03:32 PM PDT 24
Finished Jul 25 06:03:33 PM PDT 24
Peak memory 184224 kb
Host smart-304cd0f4-91eb-4e97-9d1c-c882965a70d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290421211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3290421211
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3458423675
Short name T310
Test name
Test status
Simulation time 336210731 ps
CPU time 0.81 seconds
Started Jul 25 06:03:34 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 184164 kb
Host smart-e93ac374-ea3a-4ba1-985c-4914c7cd3aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458423675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3458423675
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3700465158
Short name T370
Test name
Test status
Simulation time 326623401 ps
CPU time 1.05 seconds
Started Jul 25 06:03:54 PM PDT 24
Finished Jul 25 06:03:56 PM PDT 24
Peak memory 193324 kb
Host smart-85b85113-efb3-48f9-88f6-5782ebc62fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700465158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3700465158
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3485127732
Short name T315
Test name
Test status
Simulation time 486439593 ps
CPU time 1.16 seconds
Started Jul 25 06:03:42 PM PDT 24
Finished Jul 25 06:03:43 PM PDT 24
Peak memory 184184 kb
Host smart-71b22285-8ace-4819-acd8-333afc122d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485127732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3485127732
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.986762435
Short name T390
Test name
Test status
Simulation time 370713667 ps
CPU time 0.77 seconds
Started Jul 25 06:03:40 PM PDT 24
Finished Jul 25 06:03:41 PM PDT 24
Peak memory 193456 kb
Host smart-d47d3fb6-5336-4a01-a979-90e00808d2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986762435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.986762435
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3594671642
Short name T415
Test name
Test status
Simulation time 509187852 ps
CPU time 1.34 seconds
Started Jul 25 06:03:50 PM PDT 24
Finished Jul 25 06:03:52 PM PDT 24
Peak memory 184232 kb
Host smart-eb4e061b-0ce1-4cbf-9a8f-e8157f47f46f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594671642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3594671642
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1898136408
Short name T352
Test name
Test status
Simulation time 437833908 ps
CPU time 1.24 seconds
Started Jul 25 06:03:46 PM PDT 24
Finished Jul 25 06:03:47 PM PDT 24
Peak memory 184236 kb
Host smart-dd617405-92b5-4f95-94b1-3e9fba0d6f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898136408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1898136408
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.141680446
Short name T393
Test name
Test status
Simulation time 430723209 ps
CPU time 0.87 seconds
Started Jul 25 06:03:09 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 198552 kb
Host smart-efd2d33a-e789-4889-aa86-e233953beb6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141680446 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.141680446
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3505551383
Short name T364
Test name
Test status
Simulation time 528324818 ps
CPU time 0.76 seconds
Started Jul 25 06:03:09 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 192500 kb
Host smart-a6b84b35-4884-4de9-a65d-749822a70ff9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505551383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3505551383
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3024816348
Short name T367
Test name
Test status
Simulation time 310303854 ps
CPU time 0.92 seconds
Started Jul 25 06:03:08 PM PDT 24
Finished Jul 25 06:03:09 PM PDT 24
Peak memory 184200 kb
Host smart-24177fc2-9fc6-42f8-b892-3bef23bfaa80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024816348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3024816348
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1892013714
Short name T79
Test name
Test status
Simulation time 1459665254 ps
CPU time 2.7 seconds
Started Jul 25 06:03:08 PM PDT 24
Finished Jul 25 06:03:11 PM PDT 24
Peak memory 193468 kb
Host smart-9de95868-34d9-4cb8-9c42-7406005d0f88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892013714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1892013714
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3390283855
Short name T317
Test name
Test status
Simulation time 978592803 ps
CPU time 2.83 seconds
Started Jul 25 06:03:05 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 199100 kb
Host smart-8edfed37-e259-4e44-9bb7-81f7c46aa5fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390283855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3390283855
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3014377784
Short name T372
Test name
Test status
Simulation time 8089381686 ps
CPU time 3.72 seconds
Started Jul 25 06:03:09 PM PDT 24
Finished Jul 25 06:03:13 PM PDT 24
Peak memory 198528 kb
Host smart-4b00edfd-d93a-49e5-8b75-db572cad631e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014377784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3014377784
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.946193642
Short name T365
Test name
Test status
Simulation time 469466402 ps
CPU time 0.97 seconds
Started Jul 25 06:03:12 PM PDT 24
Finished Jul 25 06:03:13 PM PDT 24
Peak memory 196328 kb
Host smart-7f7c9798-05c2-4064-9ae2-a85555e1e17d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946193642 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.946193642
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3523462320
Short name T395
Test name
Test status
Simulation time 566498712 ps
CPU time 0.74 seconds
Started Jul 25 06:03:16 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 194492 kb
Host smart-162d7080-e86d-4b7c-baf5-46f1810079e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523462320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3523462320
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2486839667
Short name T303
Test name
Test status
Simulation time 477193470 ps
CPU time 0.74 seconds
Started Jul 25 06:03:13 PM PDT 24
Finished Jul 25 06:03:14 PM PDT 24
Peak memory 183924 kb
Host smart-a719edab-3850-43ed-817f-e5f847ca8ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486839667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2486839667
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2926868882
Short name T78
Test name
Test status
Simulation time 3000181662 ps
CPU time 2.3 seconds
Started Jul 25 06:03:13 PM PDT 24
Finished Jul 25 06:03:15 PM PDT 24
Peak memory 192552 kb
Host smart-8aa44acc-bec0-4410-ba61-b1355c226e7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926868882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2926868882
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.211351010
Short name T377
Test name
Test status
Simulation time 962077276 ps
CPU time 2.43 seconds
Started Jul 25 06:03:07 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 199088 kb
Host smart-53277d1b-5fca-4c93-8499-a8c8ab42718c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211351010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.211351010
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.925680536
Short name T322
Test name
Test status
Simulation time 4486169300 ps
CPU time 4.56 seconds
Started Jul 25 06:03:12 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 197396 kb
Host smart-78e85e73-cc01-4f16-94a1-01b5383421e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925680536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.925680536
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1865089703
Short name T300
Test name
Test status
Simulation time 495805595 ps
CPU time 0.88 seconds
Started Jul 25 06:03:07 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 196568 kb
Host smart-7b91ea14-c083-43b2-9f52-99da2f4c083f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865089703 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1865089703
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2563834361
Short name T335
Test name
Test status
Simulation time 487255441 ps
CPU time 0.67 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:14 PM PDT 24
Peak memory 184236 kb
Host smart-d9d4eef0-6293-49cb-a20b-8da21742c9db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563834361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2563834361
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1615676813
Short name T36
Test name
Test status
Simulation time 2261868658 ps
CPU time 3.61 seconds
Started Jul 25 06:03:12 PM PDT 24
Finished Jul 25 06:03:16 PM PDT 24
Peak memory 194476 kb
Host smart-7a99ed76-0e26-48a8-91c3-dbc732e5b3b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615676813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1615676813
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3972835074
Short name T385
Test name
Test status
Simulation time 389099041 ps
CPU time 2.14 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 199048 kb
Host smart-a61407e2-dd34-451e-b185-cab5d33b06a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972835074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3972835074
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3311631633
Short name T43
Test name
Test status
Simulation time 8162846940 ps
CPU time 12.78 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:28 PM PDT 24
Peak memory 198780 kb
Host smart-1498ca7f-c06e-40b8-8707-c0d6958e170b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311631633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3311631633
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2978844773
Short name T407
Test name
Test status
Simulation time 454273656 ps
CPU time 1.34 seconds
Started Jul 25 06:03:12 PM PDT 24
Finished Jul 25 06:03:13 PM PDT 24
Peak memory 195892 kb
Host smart-bac981ca-a4ec-4321-a342-04e6803b242b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978844773 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2978844773
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2259403370
Short name T358
Test name
Test status
Simulation time 294065385 ps
CPU time 0.98 seconds
Started Jul 25 06:03:09 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 192536 kb
Host smart-d4bd7406-2649-4665-b4fe-e08915a3a7df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259403370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2259403370
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.36714819
Short name T387
Test name
Test status
Simulation time 300499776 ps
CPU time 0.85 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:15 PM PDT 24
Peak memory 184208 kb
Host smart-82d3e92e-d32a-49e9-9acf-d4a88b76fb80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36714819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.36714819
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1413543986
Short name T74
Test name
Test status
Simulation time 3329384518 ps
CPU time 5.74 seconds
Started Jul 25 06:03:11 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 196132 kb
Host smart-a93edeba-c0b7-4ce5-83cd-b03e15e6e55d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413543986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1413543986
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.937703105
Short name T301
Test name
Test status
Simulation time 550340012 ps
CPU time 1.27 seconds
Started Jul 25 06:03:10 PM PDT 24
Finished Jul 25 06:03:12 PM PDT 24
Peak memory 199048 kb
Host smart-95318e85-2fa5-40b5-97fc-bb71b47263d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937703105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.937703105
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.808889893
Short name T404
Test name
Test status
Simulation time 8764227402 ps
CPU time 8.49 seconds
Started Jul 25 06:03:14 PM PDT 24
Finished Jul 25 06:03:22 PM PDT 24
Peak memory 198776 kb
Host smart-6ca1c500-4a33-4a57-845f-a71df9748f76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808889893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.808889893
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1249623324
Short name T369
Test name
Test status
Simulation time 440298544 ps
CPU time 1.31 seconds
Started Jul 25 06:03:20 PM PDT 24
Finished Jul 25 06:03:22 PM PDT 24
Peak memory 196780 kb
Host smart-bea1d8cf-b5f5-4c6e-a5e4-1d280c560d52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249623324 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1249623324
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.600042696
Short name T62
Test name
Test status
Simulation time 455653120 ps
CPU time 0.67 seconds
Started Jul 25 06:03:08 PM PDT 24
Finished Jul 25 06:03:09 PM PDT 24
Peak memory 193472 kb
Host smart-65a50a4f-d63e-4f01-901f-1420152047b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600042696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.600042696
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.259037274
Short name T318
Test name
Test status
Simulation time 334163405 ps
CPU time 1.01 seconds
Started Jul 25 06:03:19 PM PDT 24
Finished Jul 25 06:03:21 PM PDT 24
Peak memory 184128 kb
Host smart-668222e4-326c-4edd-b31c-71e1c5a2063d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259037274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.259037274
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1623978421
Short name T38
Test name
Test status
Simulation time 2278375842 ps
CPU time 3.41 seconds
Started Jul 25 06:03:20 PM PDT 24
Finished Jul 25 06:03:23 PM PDT 24
Peak memory 194156 kb
Host smart-7df0b1ce-f914-4135-96f2-b01ba45290c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623978421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1623978421
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4025636159
Short name T323
Test name
Test status
Simulation time 1004577028 ps
CPU time 1.93 seconds
Started Jul 25 06:03:12 PM PDT 24
Finished Jul 25 06:03:14 PM PDT 24
Peak memory 199020 kb
Host smart-c4038df4-4e43-4556-9333-1f8f6a58343c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025636159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4025636159
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.81583690
Short name T375
Test name
Test status
Simulation time 4673490272 ps
CPU time 2.33 seconds
Started Jul 25 06:03:09 PM PDT 24
Finished Jul 25 06:03:12 PM PDT 24
Peak memory 197328 kb
Host smart-0cb4c41c-830b-4173-9822-917d6f6e2977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81583690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_i
ntg_err.81583690
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.692973123
Short name T279
Test name
Test status
Simulation time 3948260687 ps
CPU time 2.15 seconds
Started Jul 25 06:01:47 PM PDT 24
Finished Jul 25 06:01:50 PM PDT 24
Peak memory 191808 kb
Host smart-435d823f-0b19-40a2-8fda-b87a8b1b4205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692973123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.692973123
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.851724644
Short name T232
Test name
Test status
Simulation time 556065038 ps
CPU time 0.66 seconds
Started Jul 25 06:01:46 PM PDT 24
Finished Jul 25 06:01:47 PM PDT 24
Peak memory 191712 kb
Host smart-59f3bed3-634c-4af9-9fb5-525e8c79a55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851724644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.851724644
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2681134436
Short name T250
Test name
Test status
Simulation time 24157093462 ps
CPU time 30.65 seconds
Started Jul 25 06:01:46 PM PDT 24
Finished Jul 25 06:02:17 PM PDT 24
Peak memory 191896 kb
Host smart-a021bdb9-9feb-4a4a-aefb-6892551d9d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681134436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2681134436
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3483851294
Short name T17
Test name
Test status
Simulation time 7820962970 ps
CPU time 3.44 seconds
Started Jul 25 06:01:47 PM PDT 24
Finished Jul 25 06:01:50 PM PDT 24
Peak memory 215964 kb
Host smart-dc9e042b-c3e6-45b4-b669-7d3ff1cc127f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483851294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3483851294
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3374147730
Short name T166
Test name
Test status
Simulation time 477164103 ps
CPU time 1.29 seconds
Started Jul 25 06:01:48 PM PDT 24
Finished Jul 25 06:01:50 PM PDT 24
Peak memory 196608 kb
Host smart-4a70428d-0a05-4b70-b51a-e1196722a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374147730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3374147730
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1754886654
Short name T45
Test name
Test status
Simulation time 51163018219 ps
CPU time 17.32 seconds
Started Jul 25 06:01:57 PM PDT 24
Finished Jul 25 06:02:15 PM PDT 24
Peak memory 196824 kb
Host smart-340e8ce4-e139-4638-819d-6ae7fdd3ed76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754886654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1754886654
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3001477002
Short name T14
Test name
Test status
Simulation time 425277716 ps
CPU time 0.61 seconds
Started Jul 25 06:01:53 PM PDT 24
Finished Jul 25 06:01:54 PM PDT 24
Peak memory 196544 kb
Host smart-f8b57cc6-7291-4287-8e1a-762f42a70d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001477002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3001477002
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.537514115
Short name T281
Test name
Test status
Simulation time 43612973352 ps
CPU time 41.03 seconds
Started Jul 25 06:01:55 PM PDT 24
Finished Jul 25 06:02:36 PM PDT 24
Peak memory 191912 kb
Host smart-c0d6e807-aa2b-4c6a-b8e8-990dbd5c8f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537514115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.537514115
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1562230680
Short name T227
Test name
Test status
Simulation time 600784586 ps
CPU time 0.82 seconds
Started Jul 25 06:01:57 PM PDT 24
Finished Jul 25 06:01:58 PM PDT 24
Peak memory 191744 kb
Host smart-0ec1cb0c-fa31-47ec-845b-a5532e63acd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562230680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1562230680
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.4146558142
Short name T260
Test name
Test status
Simulation time 2141088154 ps
CPU time 1.52 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:02:00 PM PDT 24
Peak memory 191728 kb
Host smart-b0a91a68-8a26-42a4-b9b8-f31c567684cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146558142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.4146558142
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.1191670507
Short name T7
Test name
Test status
Simulation time 538545787 ps
CPU time 0.8 seconds
Started Jul 25 06:02:00 PM PDT 24
Finished Jul 25 06:02:01 PM PDT 24
Peak memory 191612 kb
Host smart-2eee9dd7-d377-4739-8bfe-e1139bf89244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191670507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.1191670507
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1807467158
Short name T254
Test name
Test status
Simulation time 12937080780 ps
CPU time 9.23 seconds
Started Jul 25 06:01:54 PM PDT 24
Finished Jul 25 06:02:03 PM PDT 24
Peak memory 196880 kb
Host smart-c090986d-1865-4262-b272-bb663c10060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807467158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1807467158
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2936028138
Short name T30
Test name
Test status
Simulation time 527299197 ps
CPU time 0.78 seconds
Started Jul 25 06:02:00 PM PDT 24
Finished Jul 25 06:02:01 PM PDT 24
Peak memory 191764 kb
Host smart-5853011a-ff8a-42c2-bd6b-f05fa2ad7b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936028138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2936028138
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1226739257
Short name T212
Test name
Test status
Simulation time 7813211372 ps
CPU time 3.5 seconds
Started Jul 25 06:02:00 PM PDT 24
Finished Jul 25 06:02:04 PM PDT 24
Peak memory 191884 kb
Host smart-581c4427-384e-4fb7-8d9a-34d79b34bc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226739257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1226739257
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2209688618
Short name T41
Test name
Test status
Simulation time 364027128 ps
CPU time 1.14 seconds
Started Jul 25 06:02:04 PM PDT 24
Finished Jul 25 06:02:05 PM PDT 24
Peak memory 196576 kb
Host smart-c5a08704-a0e0-40bb-a151-3e134c7b7475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209688618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2209688618
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.4233654156
Short name T242
Test name
Test status
Simulation time 54814192045 ps
CPU time 37.78 seconds
Started Jul 25 06:02:02 PM PDT 24
Finished Jul 25 06:02:39 PM PDT 24
Peak memory 196956 kb
Host smart-30d8271e-83ea-43d9-b9a2-24cbd8382772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233654156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.4233654156
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.973527005
Short name T282
Test name
Test status
Simulation time 444701723 ps
CPU time 1.19 seconds
Started Jul 25 06:02:00 PM PDT 24
Finished Jul 25 06:02:01 PM PDT 24
Peak memory 191756 kb
Host smart-873bf84a-048a-46dd-8791-3d0c324f5091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973527005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.973527005
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2502627830
Short name T244
Test name
Test status
Simulation time 56840119077 ps
CPU time 25.74 seconds
Started Jul 25 06:02:05 PM PDT 24
Finished Jul 25 06:02:31 PM PDT 24
Peak memory 196884 kb
Host smart-e7212b86-3c45-495c-a992-689a4dfe4631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502627830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2502627830
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3062648753
Short name T249
Test name
Test status
Simulation time 387852361 ps
CPU time 0.76 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:01:58 PM PDT 24
Peak memory 191720 kb
Host smart-75e7b697-47f4-4ff7-b78c-6ccc1df5c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062648753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3062648753
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2029264751
Short name T229
Test name
Test status
Simulation time 46880329395 ps
CPU time 64.98 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 191812 kb
Host smart-af132283-80a5-4940-b3a4-197a3e1cb945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029264751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2029264751
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4269558698
Short name T256
Test name
Test status
Simulation time 577101123 ps
CPU time 0.84 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:02:13 PM PDT 24
Peak memory 196432 kb
Host smart-d3aef293-42c2-4729-9fb6-7482090ba55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269558698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4269558698
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1828905771
Short name T228
Test name
Test status
Simulation time 6114575622 ps
CPU time 9.3 seconds
Started Jul 25 06:02:08 PM PDT 24
Finished Jul 25 06:02:18 PM PDT 24
Peak memory 196876 kb
Host smart-d1ce7e37-3cf2-494d-9ae3-55766df3fd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828905771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1828905771
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1844385967
Short name T269
Test name
Test status
Simulation time 572096881 ps
CPU time 1.4 seconds
Started Jul 25 06:02:10 PM PDT 24
Finished Jul 25 06:02:11 PM PDT 24
Peak memory 191768 kb
Host smart-64ac10b7-7eab-4c54-b4b8-14a3e3af032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844385967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1844385967
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2871688967
Short name T261
Test name
Test status
Simulation time 7284221120 ps
CPU time 1.89 seconds
Started Jul 25 06:02:11 PM PDT 24
Finished Jul 25 06:02:13 PM PDT 24
Peak memory 196808 kb
Host smart-d0322da6-eb3b-4d95-a65f-b4eed27e9f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871688967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2871688967
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.995458124
Short name T241
Test name
Test status
Simulation time 405864565 ps
CPU time 0.7 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:02:10 PM PDT 24
Peak memory 191760 kb
Host smart-fc6ff43e-97c5-47c5-b395-180b50c78c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995458124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.995458124
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2512389758
Short name T278
Test name
Test status
Simulation time 9918898230 ps
CPU time 4.34 seconds
Started Jul 25 06:01:49 PM PDT 24
Finished Jul 25 06:01:53 PM PDT 24
Peak memory 191924 kb
Host smart-5c308742-c643-487c-b082-f3d3f9bbbd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512389758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2512389758
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1107122451
Short name T18
Test name
Test status
Simulation time 8090596185 ps
CPU time 6.65 seconds
Started Jul 25 06:01:49 PM PDT 24
Finished Jul 25 06:01:56 PM PDT 24
Peak memory 215920 kb
Host smart-40842e4b-2b94-4080-8e91-5a21407d6482
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107122451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1107122451
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1303201111
Short name T209
Test name
Test status
Simulation time 538465608 ps
CPU time 0.97 seconds
Started Jul 25 06:01:48 PM PDT 24
Finished Jul 25 06:01:50 PM PDT 24
Peak memory 196556 kb
Host smart-19c6c84f-35c2-4e25-8e2d-9e3974d0979e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303201111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1303201111
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1849824957
Short name T23
Test name
Test status
Simulation time 5517459551 ps
CPU time 7.7 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:02:20 PM PDT 24
Peak memory 191856 kb
Host smart-ae12be14-de28-4adf-8adc-8ed6e86c8c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849824957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1849824957
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2806333568
Short name T258
Test name
Test status
Simulation time 447384301 ps
CPU time 0.73 seconds
Started Jul 25 06:02:07 PM PDT 24
Finished Jul 25 06:02:07 PM PDT 24
Peak memory 196544 kb
Host smart-28160116-7c0d-4d19-a0db-a009c6bc924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806333568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2806333568
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3557043537
Short name T56
Test name
Test status
Simulation time 19011251646 ps
CPU time 6.89 seconds
Started Jul 25 06:02:13 PM PDT 24
Finished Jul 25 06:02:20 PM PDT 24
Peak memory 191828 kb
Host smart-fec16ed8-473c-4d51-8b18-90f712d01b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557043537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3557043537
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2657478790
Short name T246
Test name
Test status
Simulation time 537640219 ps
CPU time 0.72 seconds
Started Jul 25 06:02:10 PM PDT 24
Finished Jul 25 06:02:11 PM PDT 24
Peak memory 191760 kb
Host smart-20f8ee2b-e6db-471c-b493-6d0b96e828ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657478790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2657478790
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2429478877
Short name T5
Test name
Test status
Simulation time 171511599030 ps
CPU time 59.6 seconds
Started Jul 25 06:02:11 PM PDT 24
Finished Jul 25 06:03:11 PM PDT 24
Peak memory 191868 kb
Host smart-749a4708-1d72-4441-9a4b-b1c1a13f8247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429478877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2429478877
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.455955604
Short name T270
Test name
Test status
Simulation time 375886987 ps
CPU time 1.07 seconds
Started Jul 25 06:02:06 PM PDT 24
Finished Jul 25 06:02:08 PM PDT 24
Peak memory 191784 kb
Host smart-0ec36d30-a4c9-485d-9388-9a62948f2833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455955604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.455955604
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2554994373
Short name T101
Test name
Test status
Simulation time 416399401 ps
CPU time 0.88 seconds
Started Jul 25 06:02:11 PM PDT 24
Finished Jul 25 06:02:12 PM PDT 24
Peak memory 196576 kb
Host smart-f4dcefb6-7d1d-4260-bea3-1607d98ffa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554994373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2554994373
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2656741530
Short name T221
Test name
Test status
Simulation time 19201726291 ps
CPU time 4.51 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:02:14 PM PDT 24
Peak memory 191892 kb
Host smart-80bdac39-5b8f-47da-b7e2-688529be515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656741530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2656741530
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2500122010
Short name T216
Test name
Test status
Simulation time 562948730 ps
CPU time 1.02 seconds
Started Jul 25 06:02:07 PM PDT 24
Finished Jul 25 06:02:08 PM PDT 24
Peak memory 196588 kb
Host smart-8d48206b-9bf9-4702-8a04-57a298eabc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500122010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2500122010
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3169292998
Short name T99
Test name
Test status
Simulation time 29885034204 ps
CPU time 10.8 seconds
Started Jul 25 06:02:11 PM PDT 24
Finished Jul 25 06:02:22 PM PDT 24
Peak memory 191856 kb
Host smart-3ee1dad2-2e56-4035-ad31-c58cb998b7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169292998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3169292998
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3160833593
Short name T208
Test name
Test status
Simulation time 532334019 ps
CPU time 0.78 seconds
Started Jul 25 06:02:10 PM PDT 24
Finished Jul 25 06:02:11 PM PDT 24
Peak memory 191760 kb
Host smart-0812265f-f306-4c04-b95f-2d746441b838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160833593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3160833593
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1187372240
Short name T240
Test name
Test status
Simulation time 37476535035 ps
CPU time 28.67 seconds
Started Jul 25 06:02:11 PM PDT 24
Finished Jul 25 06:02:39 PM PDT 24
Peak memory 196900 kb
Host smart-88b7da79-cbfb-4e2f-a22e-3b7c1660aa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187372240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1187372240
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4047738996
Short name T243
Test name
Test status
Simulation time 548983227 ps
CPU time 0.67 seconds
Started Jul 25 06:02:15 PM PDT 24
Finished Jul 25 06:02:15 PM PDT 24
Peak memory 191780 kb
Host smart-67eef7f9-da75-47c4-ba83-76546bbbd75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047738996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4047738996
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.521338041
Short name T245
Test name
Test status
Simulation time 23066481462 ps
CPU time 7.82 seconds
Started Jul 25 06:02:11 PM PDT 24
Finished Jul 25 06:02:19 PM PDT 24
Peak memory 196844 kb
Host smart-922dfb20-034e-479c-ab51-4335514e9007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521338041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.521338041
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1949918588
Short name T52
Test name
Test status
Simulation time 564206089 ps
CPU time 0.93 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:02:10 PM PDT 24
Peak memory 191744 kb
Host smart-d574244a-9dc8-4d2f-baea-fa4b3957d408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949918588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1949918588
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3012529890
Short name T233
Test name
Test status
Simulation time 8555294990 ps
CPU time 11.46 seconds
Started Jul 25 06:02:10 PM PDT 24
Finished Jul 25 06:02:22 PM PDT 24
Peak memory 191872 kb
Host smart-505d9724-4bc0-414a-9cb6-3327e27cf24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012529890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3012529890
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3195262330
Short name T54
Test name
Test status
Simulation time 497637520 ps
CPU time 1.32 seconds
Started Jul 25 06:02:10 PM PDT 24
Finished Jul 25 06:02:11 PM PDT 24
Peak memory 191712 kb
Host smart-f9c4e5cb-35ea-45d7-bda2-0189021c5b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195262330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3195262330
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2286336382
Short name T211
Test name
Test status
Simulation time 1622134714 ps
CPU time 2.9 seconds
Started Jul 25 06:02:12 PM PDT 24
Finished Jul 25 06:02:15 PM PDT 24
Peak memory 191724 kb
Host smart-48c608f7-7252-450d-b98f-46518ad2ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286336382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2286336382
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1344206044
Short name T266
Test name
Test status
Simulation time 496077540 ps
CPU time 1.18 seconds
Started Jul 25 06:02:09 PM PDT 24
Finished Jul 25 06:02:11 PM PDT 24
Peak memory 191752 kb
Host smart-de3007b2-a89f-40ba-9d19-f404f77efd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344206044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1344206044
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3177417224
Short name T4
Test name
Test status
Simulation time 49265926791 ps
CPU time 16.81 seconds
Started Jul 25 06:02:20 PM PDT 24
Finished Jul 25 06:02:36 PM PDT 24
Peak memory 191884 kb
Host smart-2da7b300-8c24-4df4-aaeb-e729b82e14ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177417224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3177417224
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3797359635
Short name T214
Test name
Test status
Simulation time 580396362 ps
CPU time 1.43 seconds
Started Jul 25 06:02:21 PM PDT 24
Finished Jul 25 06:02:22 PM PDT 24
Peak memory 191836 kb
Host smart-f84fdbe5-6a8b-4daa-8b91-d1bbe786a0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797359635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3797359635
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2719801430
Short name T248
Test name
Test status
Simulation time 30413153801 ps
CPU time 12.22 seconds
Started Jul 25 06:01:48 PM PDT 24
Finished Jul 25 06:02:01 PM PDT 24
Peak memory 191872 kb
Host smart-89c97b92-53b6-4698-beff-81d7fe77d56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719801430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2719801430
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.14054361
Short name T21
Test name
Test status
Simulation time 4234825077 ps
CPU time 6.87 seconds
Started Jul 25 06:01:49 PM PDT 24
Finished Jul 25 06:01:56 PM PDT 24
Peak memory 215420 kb
Host smart-3685847d-4a39-4950-a1b8-1a102acb0255
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14054361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.14054361
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.115225326
Short name T275
Test name
Test status
Simulation time 614502215 ps
CPU time 0.77 seconds
Started Jul 25 06:01:50 PM PDT 24
Finished Jul 25 06:01:51 PM PDT 24
Peak memory 191780 kb
Host smart-75bfee86-9733-429f-bf2d-2cbb54523dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115225326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.115225326
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.879052575
Short name T251
Test name
Test status
Simulation time 29530735141 ps
CPU time 21.77 seconds
Started Jul 25 06:02:15 PM PDT 24
Finished Jul 25 06:02:37 PM PDT 24
Peak memory 191832 kb
Host smart-93f67384-c578-41ae-bdc9-8fa54eafcca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879052575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.879052575
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.478784882
Short name T267
Test name
Test status
Simulation time 557146015 ps
CPU time 1.2 seconds
Started Jul 25 06:02:13 PM PDT 24
Finished Jul 25 06:02:14 PM PDT 24
Peak memory 196548 kb
Host smart-f88883a0-8e02-4d02-b7dd-1cb09e8d61c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478784882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.478784882
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.139566476
Short name T29
Test name
Test status
Simulation time 32105321983 ps
CPU time 22.44 seconds
Started Jul 25 06:02:15 PM PDT 24
Finished Jul 25 06:02:38 PM PDT 24
Peak memory 191904 kb
Host smart-78b33d52-2830-4f26-b95e-dde1c525e65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139566476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.139566476
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2644782708
Short name T252
Test name
Test status
Simulation time 382066871 ps
CPU time 1.17 seconds
Started Jul 25 06:02:15 PM PDT 24
Finished Jul 25 06:02:17 PM PDT 24
Peak memory 191776 kb
Host smart-dac4b6e8-9ee8-4022-a895-43a13748582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644782708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2644782708
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3190703782
Short name T268
Test name
Test status
Simulation time 5836324678 ps
CPU time 8.54 seconds
Started Jul 25 06:02:19 PM PDT 24
Finished Jul 25 06:02:28 PM PDT 24
Peak memory 196892 kb
Host smart-8c28d00d-1759-4762-b9a9-1f428f7ea944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190703782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3190703782
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.391480683
Short name T274
Test name
Test status
Simulation time 528063093 ps
CPU time 1.39 seconds
Started Jul 25 06:02:21 PM PDT 24
Finished Jul 25 06:02:22 PM PDT 24
Peak memory 191832 kb
Host smart-85362bb5-0f48-4381-8b2e-c66512d8420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391480683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.391480683
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3297072043
Short name T271
Test name
Test status
Simulation time 48033881771 ps
CPU time 17.25 seconds
Started Jul 25 06:02:23 PM PDT 24
Finished Jul 25 06:02:41 PM PDT 24
Peak memory 191880 kb
Host smart-278162f3-5603-4d8f-9cb5-f7e5a175d54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297072043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3297072043
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2109278522
Short name T27
Test name
Test status
Simulation time 554539081 ps
CPU time 1.27 seconds
Started Jul 25 06:02:26 PM PDT 24
Finished Jul 25 06:02:28 PM PDT 24
Peak memory 191776 kb
Host smart-729aa5c7-cef0-4e50-bd8a-eb89db2daff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109278522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2109278522
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3111655547
Short name T57
Test name
Test status
Simulation time 23047483063 ps
CPU time 19.63 seconds
Started Jul 25 06:02:31 PM PDT 24
Finished Jul 25 06:02:50 PM PDT 24
Peak memory 196972 kb
Host smart-3891e7f1-1455-44c6-bd09-d40630c19b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111655547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3111655547
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.408848642
Short name T265
Test name
Test status
Simulation time 574053239 ps
CPU time 1.47 seconds
Started Jul 25 06:02:27 PM PDT 24
Finished Jul 25 06:02:28 PM PDT 24
Peak memory 196572 kb
Host smart-b7dc61c6-0aae-4f54-953f-884cdba941a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408848642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.408848642
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_jump.836652289
Short name T192
Test name
Test status
Simulation time 450835516 ps
CPU time 0.94 seconds
Started Jul 25 06:02:24 PM PDT 24
Finished Jul 25 06:02:25 PM PDT 24
Peak memory 196560 kb
Host smart-3b2f4b34-5fb4-4883-926e-cee3885012ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836652289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.836652289
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3019651633
Short name T222
Test name
Test status
Simulation time 954279319 ps
CPU time 1.9 seconds
Started Jul 25 06:02:26 PM PDT 24
Finished Jul 25 06:02:28 PM PDT 24
Peak memory 191776 kb
Host smart-899020a6-ee88-4f29-9b3d-d6b044dec74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019651633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3019651633
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1707307994
Short name T263
Test name
Test status
Simulation time 567904646 ps
CPU time 0.78 seconds
Started Jul 25 06:02:24 PM PDT 24
Finished Jul 25 06:02:25 PM PDT 24
Peak memory 196508 kb
Host smart-c52334b0-ae75-42da-819d-0f58f5b9bd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707307994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1707307994
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2915754027
Short name T100
Test name
Test status
Simulation time 32704150129 ps
CPU time 11.54 seconds
Started Jul 25 06:02:40 PM PDT 24
Finished Jul 25 06:02:51 PM PDT 24
Peak memory 191868 kb
Host smart-6c8c2419-fc82-4f8b-929e-560e61e1c046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915754027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2915754027
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.654422126
Short name T213
Test name
Test status
Simulation time 428926670 ps
CPU time 0.87 seconds
Started Jul 25 06:02:39 PM PDT 24
Finished Jul 25 06:02:40 PM PDT 24
Peak memory 191756 kb
Host smart-3348d3a1-09b8-4c6e-a488-eee440ef3b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654422126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.654422126
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.259502310
Short name T226
Test name
Test status
Simulation time 7808466684 ps
CPU time 13.19 seconds
Started Jul 25 06:02:38 PM PDT 24
Finished Jul 25 06:02:51 PM PDT 24
Peak memory 196844 kb
Host smart-b783447d-8255-405f-8cab-df2fa8a47c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259502310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.259502310
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3789233058
Short name T262
Test name
Test status
Simulation time 571984336 ps
CPU time 1.43 seconds
Started Jul 25 06:02:40 PM PDT 24
Finished Jul 25 06:02:41 PM PDT 24
Peak memory 191772 kb
Host smart-ec0b0988-8e33-4a41-a394-4bb14c00c971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789233058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3789233058
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3556244494
Short name T277
Test name
Test status
Simulation time 61397949812 ps
CPU time 21.12 seconds
Started Jul 25 06:02:41 PM PDT 24
Finished Jul 25 06:03:03 PM PDT 24
Peak memory 196876 kb
Host smart-be0a1836-6bc2-4967-8d63-853b60fd09fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556244494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3556244494
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2535438400
Short name T231
Test name
Test status
Simulation time 381535740 ps
CPU time 1.1 seconds
Started Jul 25 06:02:42 PM PDT 24
Finished Jul 25 06:02:44 PM PDT 24
Peak memory 191764 kb
Host smart-6d3b446d-b1c3-416b-acc8-3b33d51619e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535438400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2535438400
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1061012132
Short name T210
Test name
Test status
Simulation time 16756566465 ps
CPU time 7.81 seconds
Started Jul 25 06:02:42 PM PDT 24
Finished Jul 25 06:02:50 PM PDT 24
Peak memory 191888 kb
Host smart-8b86bce9-ab1c-4b84-8393-ee452f7f570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061012132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1061012132
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2886170524
Short name T236
Test name
Test status
Simulation time 366422661 ps
CPU time 0.72 seconds
Started Jul 25 06:02:40 PM PDT 24
Finished Jul 25 06:02:41 PM PDT 24
Peak memory 191764 kb
Host smart-498b550e-5437-4af6-870d-45cdef1c793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886170524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2886170524
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.550807353
Short name T247
Test name
Test status
Simulation time 13393576200 ps
CPU time 16.87 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:02:15 PM PDT 24
Peak memory 196884 kb
Host smart-76f03664-bfe2-43e2-99e8-7c72f00428ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550807353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.550807353
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3102440804
Short name T19
Test name
Test status
Simulation time 8472548547 ps
CPU time 11.9 seconds
Started Jul 25 06:02:05 PM PDT 24
Finished Jul 25 06:02:17 PM PDT 24
Peak memory 215872 kb
Host smart-1c337e5c-861b-4a57-a309-836b74a00f93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102440804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3102440804
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.510119578
Short name T238
Test name
Test status
Simulation time 467601148 ps
CPU time 1.17 seconds
Started Jul 25 06:01:55 PM PDT 24
Finished Jul 25 06:01:57 PM PDT 24
Peak memory 191796 kb
Host smart-f7731480-0889-4ae3-8856-e49b35aa1435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510119578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.510119578
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2213905567
Short name T234
Test name
Test status
Simulation time 24898318237 ps
CPU time 18.17 seconds
Started Jul 25 06:02:44 PM PDT 24
Finished Jul 25 06:03:02 PM PDT 24
Peak memory 196900 kb
Host smart-415c1be6-3a97-4503-90a4-15161c210e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213905567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2213905567
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2294431495
Short name T255
Test name
Test status
Simulation time 470191051 ps
CPU time 1.28 seconds
Started Jul 25 06:02:42 PM PDT 24
Finished Jul 25 06:02:44 PM PDT 24
Peak memory 196600 kb
Host smart-d48b544f-9f01-47aa-ae5d-0759d56d4a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294431495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2294431495
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2953971486
Short name T259
Test name
Test status
Simulation time 32864696142 ps
CPU time 51.49 seconds
Started Jul 25 06:02:44 PM PDT 24
Finished Jul 25 06:03:35 PM PDT 24
Peak memory 191884 kb
Host smart-6a20820e-546b-4360-ad6d-67418e30a0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953971486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2953971486
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3431327715
Short name T235
Test name
Test status
Simulation time 581575574 ps
CPU time 1.44 seconds
Started Jul 25 06:02:41 PM PDT 24
Finished Jul 25 06:02:43 PM PDT 24
Peak memory 191764 kb
Host smart-ed10eeab-9451-47e6-a29f-2bd769582284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431327715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3431327715
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1802094699
Short name T203
Test name
Test status
Simulation time 12607724791 ps
CPU time 4.98 seconds
Started Jul 25 06:02:42 PM PDT 24
Finished Jul 25 06:02:48 PM PDT 24
Peak memory 191868 kb
Host smart-ccfe0e6a-3f39-476c-92f2-7e9067bc0f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802094699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1802094699
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1281739156
Short name T217
Test name
Test status
Simulation time 601626115 ps
CPU time 0.78 seconds
Started Jul 25 06:02:43 PM PDT 24
Finished Jul 25 06:02:44 PM PDT 24
Peak memory 191764 kb
Host smart-f32f629c-ba12-4c91-b6f7-08f1a08c74ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281739156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1281739156
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1792441787
Short name T280
Test name
Test status
Simulation time 36576196417 ps
CPU time 24.48 seconds
Started Jul 25 06:02:43 PM PDT 24
Finished Jul 25 06:03:08 PM PDT 24
Peak memory 196860 kb
Host smart-908fb31b-8893-49a9-a0d4-50ce960ee035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792441787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1792441787
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.163899921
Short name T223
Test name
Test status
Simulation time 500382275 ps
CPU time 0.74 seconds
Started Jul 25 06:02:40 PM PDT 24
Finished Jul 25 06:02:41 PM PDT 24
Peak memory 196664 kb
Host smart-cfe1ad6d-fce8-4fbe-b937-286da6a2d5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163899921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.163899921
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_jump.928733421
Short name T180
Test name
Test status
Simulation time 584682189 ps
CPU time 0.77 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 196552 kb
Host smart-29973d4d-55a0-4fbe-9098-bb232c437f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928733421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.928733421
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1248139816
Short name T224
Test name
Test status
Simulation time 45805547965 ps
CPU time 68.61 seconds
Started Jul 25 06:02:55 PM PDT 24
Finished Jul 25 06:04:04 PM PDT 24
Peak memory 191900 kb
Host smart-a4466964-b632-41ad-a4c4-ef4c1f0bf983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248139816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1248139816
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1948692013
Short name T207
Test name
Test status
Simulation time 406635842 ps
CPU time 0.72 seconds
Started Jul 25 06:02:56 PM PDT 24
Finished Jul 25 06:02:57 PM PDT 24
Peak memory 196540 kb
Host smart-16459f00-10c1-4f90-82be-f07f6b0630cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948692013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1948692013
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4242178793
Short name T230
Test name
Test status
Simulation time 40134069272 ps
CPU time 58.72 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:03:57 PM PDT 24
Peak memory 191872 kb
Host smart-0ea65de5-c7d0-4d20-b86d-394df3f84c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242178793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4242178793
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.278553430
Short name T97
Test name
Test status
Simulation time 390205483 ps
CPU time 1.17 seconds
Started Jul 25 06:02:58 PM PDT 24
Finished Jul 25 06:02:59 PM PDT 24
Peak memory 191700 kb
Host smart-d4cb635f-6ae3-4c15-a7e7-3eab428db689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278553430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.278553430
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1701203200
Short name T237
Test name
Test status
Simulation time 24894796141 ps
CPU time 33.79 seconds
Started Jul 25 06:02:55 PM PDT 24
Finished Jul 25 06:03:29 PM PDT 24
Peak memory 191860 kb
Host smart-2da8b268-a0fe-4457-b9e5-05791ae73918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701203200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1701203200
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2850969059
Short name T167
Test name
Test status
Simulation time 379784818 ps
CPU time 0.83 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:58 PM PDT 24
Peak memory 191732 kb
Host smart-fdb0ca7c-0168-4a9b-a07d-c3976a4ade63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850969059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2850969059
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3681423978
Short name T272
Test name
Test status
Simulation time 34254021696 ps
CPU time 12.73 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 196900 kb
Host smart-6b44bf53-5d59-4cd0-9a5f-52e0a12abe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681423978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3681423978
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.280390268
Short name T264
Test name
Test status
Simulation time 536313734 ps
CPU time 1.02 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:58 PM PDT 24
Peak memory 191780 kb
Host smart-d24db43c-ce91-436d-b8b6-05f5fa122d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280390268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.280390268
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1250677113
Short name T178
Test name
Test status
Simulation time 606695045 ps
CPU time 0.72 seconds
Started Jul 25 06:02:56 PM PDT 24
Finished Jul 25 06:02:57 PM PDT 24
Peak memory 196664 kb
Host smart-1bd84091-4c77-4a40-9072-afb99b6bb03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250677113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1250677113
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3879243595
Short name T273
Test name
Test status
Simulation time 33191690313 ps
CPU time 25.48 seconds
Started Jul 25 06:02:55 PM PDT 24
Finished Jul 25 06:03:21 PM PDT 24
Peak memory 191876 kb
Host smart-0f1c5262-6f6d-4e79-b6f2-6e1ead0f0480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879243595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3879243595
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.222947937
Short name T218
Test name
Test status
Simulation time 565859056 ps
CPU time 0.63 seconds
Started Jul 25 06:02:57 PM PDT 24
Finished Jul 25 06:02:58 PM PDT 24
Peak memory 191752 kb
Host smart-55ca2c82-0aa7-4d4c-abf1-9ef6bc3a1fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222947937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.222947937
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2096036066
Short name T12
Test name
Test status
Simulation time 25922551131 ps
CPU time 18.01 seconds
Started Jul 25 06:02:59 PM PDT 24
Finished Jul 25 06:03:17 PM PDT 24
Peak memory 196912 kb
Host smart-3f56030b-820e-4e50-9290-8b283c335018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096036066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2096036066
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1760914896
Short name T3
Test name
Test status
Simulation time 510908453 ps
CPU time 0.76 seconds
Started Jul 25 06:02:56 PM PDT 24
Finished Jul 25 06:02:57 PM PDT 24
Peak memory 191756 kb
Host smart-06962d12-1f50-47dd-ad08-6b24c63c9b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760914896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1760914896
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3612262153
Short name T22
Test name
Test status
Simulation time 39056480294 ps
CPU time 9.93 seconds
Started Jul 25 06:01:55 PM PDT 24
Finished Jul 25 06:02:05 PM PDT 24
Peak memory 196908 kb
Host smart-466220e5-36d0-4e20-9894-90110c68fcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612262153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3612262153
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1916834724
Short name T220
Test name
Test status
Simulation time 487809918 ps
CPU time 0.69 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:01:58 PM PDT 24
Peak memory 191760 kb
Host smart-0c18dfb6-1951-41ab-bb17-c0e31ac46476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916834724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1916834724
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.38669071
Short name T215
Test name
Test status
Simulation time 29343641644 ps
CPU time 36.19 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:02:34 PM PDT 24
Peak memory 196880 kb
Host smart-69c30450-183a-404a-88f1-cb0dc42a6e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38669071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.38669071
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1269064087
Short name T276
Test name
Test status
Simulation time 522540167 ps
CPU time 0.74 seconds
Started Jul 25 06:01:55 PM PDT 24
Finished Jul 25 06:01:55 PM PDT 24
Peak memory 196552 kb
Host smart-d8f8a02a-fd03-4744-95e4-73f286af4b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269064087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1269064087
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_jump.968747454
Short name T188
Test name
Test status
Simulation time 462235339 ps
CPU time 0.86 seconds
Started Jul 25 06:01:56 PM PDT 24
Finished Jul 25 06:01:57 PM PDT 24
Peak memory 196668 kb
Host smart-5df42471-0299-49c9-be20-3fb1d8e672c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968747454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.968747454
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2998355798
Short name T257
Test name
Test status
Simulation time 59481390531 ps
CPU time 91.23 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:03:29 PM PDT 24
Peak memory 196888 kb
Host smart-5779ec60-9de9-4c17-ae3c-004f0a30246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998355798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2998355798
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3239513788
Short name T225
Test name
Test status
Simulation time 487003127 ps
CPU time 0.89 seconds
Started Jul 25 06:02:01 PM PDT 24
Finished Jul 25 06:02:02 PM PDT 24
Peak memory 196572 kb
Host smart-81829fa3-614a-4233-8632-cd615e9c82b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239513788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3239513788
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1100737696
Short name T219
Test name
Test status
Simulation time 58402849872 ps
CPU time 22.13 seconds
Started Jul 25 06:01:58 PM PDT 24
Finished Jul 25 06:02:20 PM PDT 24
Peak memory 191864 kb
Host smart-efde2a28-1e1f-4f38-bdfb-ffa8f795697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100737696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1100737696
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3536097599
Short name T239
Test name
Test status
Simulation time 412779044 ps
CPU time 1.21 seconds
Started Jul 25 06:02:05 PM PDT 24
Finished Jul 25 06:02:06 PM PDT 24
Peak memory 191776 kb
Host smart-19200587-349b-4f1e-8e81-c6913b8b16dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536097599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3536097599
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.241007682
Short name T51
Test name
Test status
Simulation time 36604504894 ps
CPU time 14.05 seconds
Started Jul 25 06:01:56 PM PDT 24
Finished Jul 25 06:02:10 PM PDT 24
Peak memory 191896 kb
Host smart-d4164fac-f421-44a0-a686-8cfb5eac2f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241007682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.241007682
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1674790878
Short name T253
Test name
Test status
Simulation time 555185203 ps
CPU time 1.2 seconds
Started Jul 25 06:01:59 PM PDT 24
Finished Jul 25 06:02:01 PM PDT 24
Peak memory 191748 kb
Host smart-f51a6134-3c4b-467a-99dc-9c4182cfaffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674790878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1674790878
Directory /workspace/9.aon_timer_smoke/latest
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